[llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
Changes in directory llvm/utils/TableGen:
RegisterInfoEmitter.cpp updated: 1.58 -> 1.59
---
Log message:
One additional field in TargetRegisterDesc.
---
Diffs of the changes: (+1 -1)
RegisterInfoEmitter.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.58
llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.59
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.58Tue Jun 26 15:54:46 2007
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Wed Jun 27 12:09:34 2007
@@ -468,7 +468,7 @@
}
OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { //
Descriptors\n";
- OS << "{ \"NOREG\",\t0,\t0,\t0 },\n";
+ OS << "{ \"NOREG\",\t0,\t0,\t0,\t0 },\n";
// Now that register alias and sub-registers sets have been emitted, emit the
// register descriptors now.
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[llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
Changes in directory llvm/utils/TableGen:
RegisterInfoEmitter.cpp updated: 1.57 -> 1.58
---
Log message:
Add immediate sub-registers.
---
Diffs of the changes: (+21 -0)
RegisterInfoEmitter.cpp | 21 +
1 files changed, 21 insertions(+)
Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.57
llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.58
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.57Wed Jun 13 17:20:15 2007
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Tue Jun 26 15:54:46 2007
@@ -359,6 +359,7 @@
OS << " };\n";
// Emit register sub-registers / super-registers, aliases...
+ std::map > RegisterImmSubRegs;
std::map > RegisterSubRegs;
std::map > RegisterSuperRegs;
std::map > RegisterAliases;
@@ -397,6 +398,7 @@
cerr << "Warning: register " << getQualifiedName(SubReg)
<< " specified as a sub-register of " << getQualifiedName(R)
<< " multiple times!\n";
+ RegisterImmSubRegs[R].insert(SubReg);
addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
RegisterAliases, *this);
}
@@ -434,6 +436,21 @@
OS << "0 };\n";
}
+ if (!RegisterImmSubRegs.empty())
+OS << "\n\n // Register Immediate Sub-registers Sets...\n";
+
+ // Loop over all of the registers which have sub-registers, emitting the
+ // sub-registers list to memory.
+ for (std::map >::iterator
+ I = RegisterImmSubRegs.begin(), E = RegisterImmSubRegs.end();
+ I != E; ++I) {
+OS << " const unsigned " << I->first->getName() << "_ImmSubRegsSet[] = {
";
+for (std::set::iterator ASI = I->second.begin(),
+ E = I->second.end(); ASI != E; ++ASI)
+ OS << getQualifiedName(*ASI) << ", ";
+OS << "0 };\n";
+ }
+
if (!RegisterSuperRegs.empty())
OS << "\n\n // Register Super-registers Sets...\n";
@@ -472,6 +489,10 @@
OS << Reg.getName() << "_SubRegsSet,\t";
else
OS << "Empty_SubRegsSet,\t";
+if (RegisterImmSubRegs.count(Reg.TheDef))
+ OS << Reg.getName() << "_ImmSubRegsSet,\t";
+else
+ OS << "Empty_SubRegsSet,\t";
if (RegisterSuperRegs.count(Reg.TheDef))
OS << Reg.getName() << "_SuperRegsSet },\n";
else
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[llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp CodeGenTarget.cpp CodeGenRegisters.h
Changes in directory llvm/utils/TableGen:
RegisterInfoEmitter.cpp updated: 1.56 -> 1.57
CodeGenTarget.cpp updated: 1.91 -> 1.92
CodeGenRegisters.h updated: 1.11 -> 1.12
---
Log message:
Add support to tablegen for specifying subregister classes on a per register
class basis.
---
Diffs of the changes: (+50 -0)
CodeGenRegisters.h |1 +
CodeGenTarget.cpp | 10 ++
RegisterInfoEmitter.cpp | 39 +++
3 files changed, 50 insertions(+)
Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.56
llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.57
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.56Mon Jun 4 18:52:59 2007
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Wed Jun 13 17:20:15 2007
@@ -224,6 +224,44 @@
std::map > SuperClassMap;
OS << "\n";
+
+
+// Emit the sub-register classes for each RegisterClass
+for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
+ const CodeGenRegisterClass &RC = RegisterClasses[rc];
+
+ // Give the register class a legal C name if it's anonymous.
+ std::string Name = RC.TheDef->getName();
+
+ OS << " // " << Name
+ << " Sub-register Classess...\n"
+ << " static const TargetRegisterClass* const "
+ << Name << "SubRegClasses [] = {\n";
+
+ bool Empty = true;
+
+ for (unsigned subrc = 0, e2 = RC.SubRegClasses.size();
+subrc != e2; ++subrc) {
+unsigned rc2 = 0, e2 = RegisterClasses.size();
+for (; rc2 != e2; ++rc2) {
+ const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
+ if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) {
+if (!Empty) OS << ", ";
+ OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
+Empty = false;
+break;
+ }
+}
+if (rc2 == e2)
+ throw "Register Class member '" +
+RC.SubRegClasses[subrc]->getName() +
+"' is not a valid RegisterClass!";
+ }
+
+ OS << (!Empty ? ", " : "") << "NULL";
+ OS << "\n };\n\n";
+}
+
// Emit the sub-classes array for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc];
@@ -304,6 +342,7 @@
<< RC.getName() + "VTs" << ", "
<< RC.getName() + "Subclasses" << ", "
<< RC.getName() + "Superclasses" << ", "
+ << RC.getName() + "SubRegClasses" << ", "
<< RC.SpillSize/8 << ", "
<< RC.SpillAlignment/8 << ", " << RC.getName() << ", "
<< RC.getName() << " + " << RC.Elements.size() << ") {}\n";
Index: llvm/utils/TableGen/CodeGenTarget.cpp
diff -u llvm/utils/TableGen/CodeGenTarget.cpp:1.91
llvm/utils/TableGen/CodeGenTarget.cpp:1.92
--- llvm/utils/TableGen/CodeGenTarget.cpp:1.91 Wed Jun 6 05:14:55 2007
+++ llvm/utils/TableGen/CodeGenTarget.cpp Wed Jun 13 17:20:15 2007
@@ -199,6 +199,16 @@
Elements.push_back(Reg);
}
+ std::vector SubRegClassList =
+R->getValueAsListOfDefs("SubRegClassList");
+ for (unsigned i = 0, e = SubRegClassList.size(); i != e; ++i) {
+Record *SubRegClass = SubRegClassList[i];
+if (!SubRegClass->isSubClassOf("RegisterClass"))
+ throw "Register Class member '" + SubRegClass->getName() +
+"' does not derive from the RegisterClass class!";
+SubRegClasses.push_back(SubRegClass);
+ }
+
// Allow targets to override the size in bits of the RegisterClass.
unsigned Size = R->getValueAsInt("Size");
Index: llvm/utils/TableGen/CodeGenRegisters.h
diff -u llvm/utils/TableGen/CodeGenRegisters.h:1.11
llvm/utils/TableGen/CodeGenRegisters.h:1.12
--- llvm/utils/TableGen/CodeGenRegisters.h:1.11 Thu Dec 29 18:12:56 2005
+++ llvm/utils/TableGen/CodeGenRegisters.h Wed Jun 13 17:20:15 2007
@@ -38,6 +38,7 @@
std::vector VTs;
unsigned SpillSize;
unsigned SpillAlignment;
+std::vector SubRegClasses;
std::string MethodProtos, MethodBodies;
const std::string &getName() const;
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[llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
Changes in directory llvm/utils/TableGen: RegisterInfoEmitter.cpp updated: 1.55 -> 1.56 --- Log message: Patches by Chuck Rose to unbreak V Studio builds. Thanks Chuck! --- Diffs of the changes: (+1 -0) RegisterInfoEmitter.cpp |1 + 1 files changed, 1 insertion(+) Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.55 llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.56 --- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.55Mon Jun 4 11:11:03 2007 +++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Mon Jun 4 18:52:59 2007 @@ -478,6 +478,7 @@ OS << "}; break;\n"; } OS << " };\n"; + OS << " return 0;\n"; OS << "}\n\n"; // Emit the constructor of the class... ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
On May 1, 2007, at 1:28 PM, Nate Begeman wrote: >> I believe that sub/super register generator unions the set of sub/ >> super registers in a deterministic fashion and produces the >> necessary tables in the RegisterInfo.inc already. The only thing is >> that this would make the sub register index implicit in the >> ordering of the sub register list in the RegisterInfo.td. > > I'm not sure things are sufficiently well ordered internally for > that, or sorted in any particular fashion. I'll look into it, but it > seems like it would be less flexible and make the td files far less > intuitive as to what is actually going on. If tablegen picked the > numbering, I would have to go read the generated file to know what to > write in the ISel for that backend, which seems backwards to me. I agree with both of you. We should have the subreg number in the .td file, but we should merge this with the existing subreg stuff if possible. One simple thing would be for nates new syntax to populate the old tables, making the old syntax unneeded? -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
On May 1, 2007, at 2:03 PM, Christopher Lamb wrote: > I see the problem in generating the ISel. Perhaps it would be be > best to go the other way and have the sub/super reg sets be > determined by the the explicit sets defined. My goal was simply to > eliminate redundant, and possibly erroneously conflicting > information from the file. Right now there are two different ways > to specify sub registers, and if they don't match there could be > problems. > >> >>> Also, would it be possible to emit the information gathered as >>> table lookups rather than a massive two level switch statement? I >>> believe all the information to get the necessary mappings should be >>> available. >> >> It would be possible, but seems like significantly more work. I'm >> sure it will be possible to improve upon the initial implementation, >> which should be good enough to address most of the issues blocked by >> the lack of subregs exposed to the selection dag. > > Thanks for working on this. I didn't expect to get it addressed for > quite a while! No prob. I appreciate the feedback; I'll definitely be keeping it in mind while I finish the rest of the bug. Hopefully for 2.1 we can have everything done with no duplication of subreg info. Thanks, Nate ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
On May 1, 2007, at 3:28 PM, Nate Begeman wrote: On May 1, 2007, at 12:24 PM, Christopher Lamb wrote: Hi Nate, Could you look into the possibility of re-using the sub/super register support that Evan recently added? This may prevent much duplication of information in the RegisterInfo.td, especially for targets with vector registers that have many subregisters. It certainly would, I agree. I believe that sub/super register generator unions the set of sub/ super registers in a deterministic fashion and produces the necessary tables in the RegisterInfo.inc already. The only thing is that this would make the sub register index implicit in the ordering of the sub register list in the RegisterInfo.td. I'm not sure things are sufficiently well ordered internally for that, or sorted in any particular fashion. I'll look into it, but it seems like it would be less flexible and make the td files far less intuitive as to what is actually going on. If tablegen picked the numbering, I would have to go read the generated file to know what to write in the ISel for that backend, which seems backwards to me. I see the problem in generating the ISel. Perhaps it would be be best to go the other way and have the sub/super reg sets be determined by the the explicit sets defined. My goal was simply to eliminate redundant, and possibly erroneously conflicting information from the file. Right now there are two different ways to specify sub registers, and if they don't match there could be problems. Also, would it be possible to emit the information gathered as table lookups rather than a massive two level switch statement? I believe all the information to get the necessary mappings should be available. It would be possible, but seems like significantly more work. I'm sure it will be possible to improve upon the initial implementation, which should be good enough to address most of the issues blocked by the lack of subregs exposed to the selection dag. Thanks for working on this. I didn't expect to get it addressed for quite a while! -- Christopher Lamb ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
On May 1, 2007, at 12:24 PM, Christopher Lamb wrote: > Hi Nate, > > Could you look into the possibility of re-using the sub/super > register support that Evan recently added? This may prevent much > duplication of information in the RegisterInfo.td, especially for > targets with vector registers that have many subregisters. It certainly would, I agree. > I believe that sub/super register generator unions the set of sub/ > super registers in a deterministic fashion and produces the > necessary tables in the RegisterInfo.inc already. The only thing is > that this would make the sub register index implicit in the > ordering of the sub register list in the RegisterInfo.td. I'm not sure things are sufficiently well ordered internally for that, or sorted in any particular fashion. I'll look into it, but it seems like it would be less flexible and make the td files far less intuitive as to what is actually going on. If tablegen picked the numbering, I would have to go read the generated file to know what to write in the ISel for that backend, which seems backwards to me. > Also, would it be possible to emit the information gathered as > table lookups rather than a massive two level switch statement? I > believe all the information to get the necessary mappings should be > available. It would be possible, but seems like significantly more work. I'm sure it will be possible to improve upon the initial implementation, which should be good enough to address most of the issues blocked by the lack of subregs exposed to the selection dag. Nate ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
Hi Nate,
Could you look into the possibility of re-using the sub/super
register support that Evan recently added? This may prevent much
duplication of information in the RegisterInfo.td, especially for
targets with vector registers that have many subregisters.
I believe that sub/super register generator unions the set of sub/
super registers in a deterministic fashion and produces the necessary
tables in the RegisterInfo.inc already. The only thing is that this
would make the sub register index implicit in the ordering of the sub
register list in the RegisterInfo.td.
Also, would it be possible to emit the information gathered as table
lookups rather than a massive two level switch statement? I believe
all the information to get the necessary mappings should be available.
--
Christopher Lamb
On May 1, 2007, at 12:57 AM, Nate Begeman wrote:
Changes in directory llvm/utils/TableGen:
RegisterInfoEmitter.cpp updated: 1.52 -> 1.53
---
Log message:
llvm bug #1350, parts 1, 2, and 3.
---
Diffs of the changes: (+36 -0)
RegisterInfoEmitter.cpp | 36
1 files changed, 36 insertions(+)
Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.52 llvm/utils/
TableGen/RegisterInfoEmitter.cpp:1.53
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.52 Fri Apr 20
19:55:29 2007
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Tue May 1 00:57:02
2007
@@ -61,6 +61,7 @@
<< " " << ClassName
<< "(int CallFrameSetupOpcode = -1, int
CallFrameDestroyOpcode = -1);\n"
<< " int getDwarfRegNum(unsigned RegNum) const;\n"
+ << " unsigned getSubReg(unsigned RegNo, unsigned Index)
const;\n"
<< "};\n\n";
const std::vector &RegisterClasses =
@@ -322,6 +323,7 @@
std::map > RegisterSubRegs;
std::map > RegisterSuperRegs;
std::map > RegisterAliases;
+ std::map > >
SubRegVectors;
const std::vector &Regs = Target.getRegisters();
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
@@ -441,6 +443,40 @@
std::string ClassName = Target.getName() + "GenRegisterInfo";
+ // Calculate the mapping of subregister+index pairs to physical
registers.
+ std::vector SubRegs = Records.getAllDerivedDefinitions
("SubRegSet");
+ for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
+int subRegIndex = SubRegs[i]->getValueAsInt("index");
+std::vector From = SubRegs[i]->getValueAsListOfDefs
("From");
+std::vector To = SubRegs[i]->getValueAsListOfDefs
("To");
+
+assert((From.size() == To.size()) &&
+ "SubRegSet has mismatched from/to size");
+
+// For each entry in from/to vectors, insert the to register
at index
+for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii)
+ SubRegVectors[From[ii]].push_back(std::make_pair
(subRegIndex, To[ii]));
+ }
+
+ // Emit the subregister + index mapping function based on the
information
+ // calculated above.
+ OS << "unsigned " << ClassName
+ << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
+ << " switch (RegNo) {\n"
+ << " default: abort(); break;\n";
+ for (std::map >
>::iterator
+I = SubRegVectors.begin(), E = SubRegVectors.end(); I !=
E; ++I) {
+OS << " case " << getQualifiedName(I->first) << ":\n";
+OS << "switch (Index) {\n";
+OS << "default: abort(); break;\n";
+for (unsigned i = 0, e = I->second.size(); i != e; ++i)
+ OS << "case " << (I->second)[i].first << ": return "
+ << getQualifiedName((I->second)[i].second) << ";\n";
+OS << "}; break;\n";
+ }
+ OS << " };\n";
+ OS << "}\n\n";
+
// Emit the constructor of the class...
OS << ClassName << "::" << ClassName
<< "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
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[llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
Changes in directory llvm/utils/TableGen:
RegisterInfoEmitter.cpp updated: 1.53 -> 1.54
---
Log message:
A bit of feedback from Chris that I missed; error rather than asserting.
---
Diffs of the changes: (+5 -2)
RegisterInfoEmitter.cpp |7 +--
1 files changed, 5 insertions(+), 2 deletions(-)
Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.53
llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.54
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.53Tue May 1 00:57:02 2007
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Tue May 1 01:08:36 2007
@@ -450,8 +450,11 @@
std::vector From = SubRegs[i]->getValueAsListOfDefs("From");
std::vector To = SubRegs[i]->getValueAsListOfDefs("To");
-assert((From.size() == To.size()) &&
- "SubRegSet has mismatched from/to size");
+if (From.size() != To.size()) {
+ cerr << "Error: register list and sub-register list not of equal length"
+ << " in SubRegSet\n";
+ exit(1);
+}
// For each entry in from/to vectors, insert the to register at index
for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii)
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[llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
Changes in directory llvm/utils/TableGen:
RegisterInfoEmitter.cpp updated: 1.52 -> 1.53
---
Log message:
llvm bug #1350, parts 1, 2, and 3.
---
Diffs of the changes: (+36 -0)
RegisterInfoEmitter.cpp | 36
1 files changed, 36 insertions(+)
Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.52
llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.53
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.52Fri Apr 20 19:55:29 2007
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Tue May 1 00:57:02 2007
@@ -61,6 +61,7 @@
<< " " << ClassName
<< "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
<< " int getDwarfRegNum(unsigned RegNum) const;\n"
+ << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
<< "};\n\n";
const std::vector &RegisterClasses =
@@ -322,6 +323,7 @@
std::map > RegisterSubRegs;
std::map > RegisterSuperRegs;
std::map > RegisterAliases;
+ std::map > > SubRegVectors;
const std::vector &Regs = Target.getRegisters();
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
@@ -441,6 +443,40 @@
std::string ClassName = Target.getName() + "GenRegisterInfo";
+ // Calculate the mapping of subregister+index pairs to physical registers.
+ std::vector SubRegs = Records.getAllDerivedDefinitions("SubRegSet");
+ for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) {
+int subRegIndex = SubRegs[i]->getValueAsInt("index");
+std::vector From = SubRegs[i]->getValueAsListOfDefs("From");
+std::vector To = SubRegs[i]->getValueAsListOfDefs("To");
+
+assert((From.size() == To.size()) &&
+ "SubRegSet has mismatched from/to size");
+
+// For each entry in from/to vectors, insert the to register at index
+for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii)
+ SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii]));
+ }
+
+ // Emit the subregister + index mapping function based on the information
+ // calculated above.
+ OS << "unsigned " << ClassName
+ << "::getSubReg(unsigned RegNo, unsigned Index) const {\n"
+ << " switch (RegNo) {\n"
+ << " default: abort(); break;\n";
+ for (std::map > >::iterator
+I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) {
+OS << " case " << getQualifiedName(I->first) << ":\n";
+OS << "switch (Index) {\n";
+OS << "default: abort(); break;\n";
+for (unsigned i = 0, e = I->second.size(); i != e; ++i)
+ OS << "case " << (I->second)[i].first << ": return "
+ << getQualifiedName((I->second)[i].second) << ";\n";
+OS << "}; break;\n";
+ }
+ OS << " };\n";
+ OS << "}\n\n";
+
// Emit the constructor of the class...
OS << ClassName << "::" << ClassName
<< "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n"
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[llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
Changes in directory llvm/utils/TableGen:
RegisterInfoEmitter.cpp updated: 1.51 -> 1.52
---
Log message:
Bug fix; add super-registers sets.
---
Diffs of the changes: (+58 -11)
RegisterInfoEmitter.cpp | 69
1 files changed, 58 insertions(+), 11 deletions(-)
Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.51
llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.52
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.51Fri Apr 20 16:12:49 2007
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Fri Apr 20 19:55:29 2007
@@ -107,10 +107,33 @@
return true;
}
-static void addSubReg(Record *R, Record *S,
- std::map > &SubRegs,
- std::map > &Aliases,
- RegisterInfoEmitter &RIE) {
+static void addSuperReg(Record *R, Record *S,
+std::map > &SubRegs,
+std::map > &SuperRegs,
+std::map > &Aliases,
+RegisterInfoEmitter &RIE) {
+ if (R == S) {
+cerr << "Error: recursive sub-register relationship between"
+ << " register " << RIE.getQualifiedName(R)
+ << " and its sub-registers?\n";
+abort();
+ }
+ if (!SuperRegs[R].insert(S).second)
+return;
+ SubRegs[S].insert(R);
+ Aliases[R].insert(S);
+ Aliases[S].insert(R);
+ if (SuperRegs.count(S))
+for (std::set::iterator I = SuperRegs[S].begin(),
+ E = SuperRegs[S].end(); I != E; ++I)
+ addSuperReg(R, *I, SubRegs, SuperRegs, Aliases, RIE);
+}
+
+static void addSubSuperReg(Record *R, Record *S,
+ std::map > &SubRegs,
+ std::map > &SuperRegs,
+ std::map > &Aliases,
+ RegisterInfoEmitter &RIE) {
if (R == S) {
cerr << "Error: recursive sub-register relationship between"
<< " register " << RIE.getQualifiedName(R)
@@ -120,12 +143,13 @@
if (!SubRegs[R].insert(S).second)
return;
+ addSuperReg(S, R, SubRegs, SuperRegs, Aliases, RIE);
Aliases[R].insert(S);
Aliases[S].insert(R);
if (SubRegs.count(S))
for (std::set::iterator I = SubRegs[S].begin(),
E = SubRegs[S].end(); I != E; ++I)
- addSubReg(R, *I, SubRegs, Aliases, RIE);
+ addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases, RIE);
}
// RegisterInfoEmitter::run - Main register file description emitter.
@@ -294,8 +318,9 @@
<< "RegClass,\n";
OS << " };\n";
- // Emit register sub-registers / aliases...
+ // Emit register sub-registers / super-registers, aliases...
std::map > RegisterSubRegs;
+ std::map > RegisterSuperRegs;
std::map > RegisterAliases;
const std::vector &Regs = Target.getRegisters();
@@ -320,6 +345,7 @@
}
}
+ // Process sub-register sets.
for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
Record *R = Regs[i].TheDef;
std::vector LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
@@ -330,7 +356,8 @@
cerr << "Warning: register " << getQualifiedName(SubReg)
<< " specified as a sub-register of " << getQualifiedName(R)
<< " multiple times!\n";
- addSubReg(R, SubReg, RegisterSubRegs, RegisterAliases, *this);
+ addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs,
+ RegisterAliases, *this);
}
}
@@ -365,9 +392,25 @@
OS << getQualifiedName(*ASI) << ", ";
OS << "0 };\n";
}
- OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { //
Descriptors\n";
- OS << "{ \"NOREG\",\t0,\t0 },\n";
+ if (!RegisterSuperRegs.empty())
+OS << "\n\n // Register Super-registers Sets...\n";
+
+ // Emit the empty super-registers list
+ OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n";
+ // Loop over all of the registers which have super-registers, emitting the
+ // super-registers list to memory.
+ for (std::map >::iterator
+ I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E;
++I) {
+OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { ";
+for (std::set::iterator ASI = I->second.begin(),
+ E = I->second.end(); ASI != E; ++ASI)
+ OS << getQualifiedName(*ASI) << ", ";
+OS << "0 };\n";
+ }
+
+ OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { //
Descriptors\n";
+ OS << "{ \"NOREG\",\t0,\t0,\t0 },\n";
// Now that register alias and sub-registers sets have been emitted, emit the
// register descriptors now.
@@ -385,9 +428,13 @@
else
OS << "Empty_AliasSet,\t";
if (RegisterSubRegs.count(Reg.TheDef))
- OS << Reg.getName() << "_SubRegsSet },\n";
+ OS << Reg.getName() << "_SubRegsSet,\t";
+else
+ OS << "Empty_SubRegsSet,\t";
+if (RegisterSuperRegs.count(Reg.TheDef))
+ OS << Reg.getName() << "_SuperRegsSet },\n";
else
- OS << "Empty_SubRegsSet },\
[llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
Changes in directory llvm/utils/TableGen:
RegisterInfoEmitter.cpp updated: 1.50 -> 1.51
---
Log message:
Add sub-registers sets.
---
Diffs of the changes: (+61 -6)
RegisterInfoEmitter.cpp | 67 +++-
1 files changed, 61 insertions(+), 6 deletions(-)
Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.50
llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.51
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.50Sun Feb 25 21:34:38 2007
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Fri Apr 20 16:12:49 2007
@@ -107,6 +107,27 @@
return true;
}
+static void addSubReg(Record *R, Record *S,
+ std::map > &SubRegs,
+ std::map > &Aliases,
+ RegisterInfoEmitter &RIE) {
+ if (R == S) {
+cerr << "Error: recursive sub-register relationship between"
+ << " register " << RIE.getQualifiedName(R)
+ << " and its sub-registers?\n";
+abort();
+ }
+
+ if (!SubRegs[R].insert(S).second)
+return;
+ Aliases[R].insert(S);
+ Aliases[S].insert(R);
+ if (SubRegs.count(S))
+for (std::set::iterator I = SubRegs[S].begin(),
+ E = SubRegs[S].end(); I != E; ++I)
+ addSubReg(R, *I, SubRegs, Aliases, RIE);
+}
+
// RegisterInfoEmitter::run - Main register file description emitter.
//
void RegisterInfoEmitter::run(std::ostream &OS) {
@@ -273,7 +294,8 @@
<< "RegClass,\n";
OS << " };\n";
- // Emit register class aliases...
+ // Emit register sub-registers / aliases...
+ std::map > RegisterSubRegs;
std::map > RegisterAliases;
const std::vector &Regs = Target.getRegisters();
@@ -298,6 +320,20 @@
}
}
+ for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
+Record *R = Regs[i].TheDef;
+std::vector LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs");
+// Process sub-register set and add aliases information.
+for (unsigned j = 0, e = LI.size(); j != e; ++j) {
+ Record *SubReg = LI[j];
+ if (RegisterSubRegs[R].count(SubReg))
+cerr << "Warning: register " << getQualifiedName(SubReg)
+ << " specified as a sub-register of " << getQualifiedName(R)
+ << " multiple times!\n";
+ addSubReg(R, SubReg, RegisterSubRegs, RegisterAliases, *this);
+}
+ }
+
if (!RegisterAliases.empty())
OS << "\n\n // Register Alias Sets...\n";
@@ -314,12 +350,27 @@
OS << "0 };\n";
}
+ if (!RegisterSubRegs.empty())
+OS << "\n\n // Register Sub-registers Sets...\n";
+
+ // Emit the empty sub-registers list
+ OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n";
+ // Loop over all of the registers which have sub-registers, emitting the
+ // sub-registers list to memory.
+ for (std::map >::iterator
+ I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) {
+OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { ";
+for (std::set::iterator ASI = I->second.begin(),
+ E = I->second.end(); ASI != E; ++ASI)
+ OS << getQualifiedName(*ASI) << ", ";
+OS << "0 };\n";
+ }
OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { //
Descriptors\n";
- OS << "{ \"NOREG\",\t0 },\n";
+ OS << "{ \"NOREG\",\t0,\t0 },\n";
- // Now that register alias sets have been emitted, emit the register
- // descriptors now.
+ // Now that register alias and sub-registers sets have been emitted, emit the
+ // register descriptors now.
const std::vector &Registers = Target.getRegisters();
for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
const CodeGenRegister &Reg = Registers[i];
@@ -330,9 +381,13 @@
OS << Reg.getName();
OS << "\",\t";
if (RegisterAliases.count(Reg.TheDef))
- OS << Reg.getName() << "_AliasSet },\n";
+ OS << Reg.getName() << "_AliasSet,\t";
+else
+ OS << "Empty_AliasSet,\t";
+if (RegisterSubRegs.count(Reg.TheDef))
+ OS << Reg.getName() << "_SubRegsSet },\n";
else
- OS << "Empty_AliasSet },\n";
+ OS << "Empty_SubRegsSet },\n";
}
OS << " };\n"; // End of register descriptors...
OS << "}\n\n"; // End of anonymous namespace...
___
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[llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
Changes in directory llvm/utils/TableGen:
RegisterInfoEmitter.cpp updated: 1.49 -> 1.50
---
Log message:
emit an enum value for the # of target registers.
---
Diffs of the changes: (+2 -2)
RegisterInfoEmitter.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.49
llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.50
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.49Thu Dec 7 16:21:48 2006
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Sun Feb 25 21:34:38 2007
@@ -38,8 +38,8 @@
OS << " enum {\nNoRegister,\n";
for (unsigned i = 0, e = Registers.size(); i != e; ++i)
-OS << "" << Registers[i].getName() << (i != (e-1) ? ", \t// " : "
\t// ") << i+1 << "\n";
-
+OS << "" << Registers[i].getName() << ", \t// " << i+1 << "\n";
+ OS << "NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n";
OS << " };\n";
if (!Namespace.empty())
OS << "}\n";
___
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[llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
Changes in directory llvm/utils/TableGen:
RegisterInfoEmitter.cpp updated: 1.46 -> 1.47
---
Log message:
Make sub- and super- register classes const.
---
Diffs of the changes: (+5 -4)
RegisterInfoEmitter.cpp |9 +
1 files changed, 5 insertions(+), 4 deletions(-)
Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.46
llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.47
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.46Tue Jul 18 17:18:31 2006
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Wed Jul 19 00:58:18 2006
@@ -149,8 +149,9 @@
// Emit the register list now.
OS << " // " << Name
- << " Register Class Value Types...\n const MVT::ValueType " << Name
- << "[] = {\n";
+ << " Register Class Value Types...\n"
+ << " static const MVT::ValueType " << Name
+ << "[] = {\n";
for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i)
OS << RC.VTs[i] << ", ";
OS << "MVT::Other\n };\n\n";
@@ -182,7 +183,7 @@
OS << " // " << Name
<< " Register Class sub-classes...\n"
- << " static const TargetRegisterClass* "
+ << " static const TargetRegisterClass* const "
<< Name << "Subclasses [] = {\n";
bool Empty = true;
@@ -217,7 +218,7 @@
OS << " // " << Name
<< " Register Class super-classes...\n"
- << " static const TargetRegisterClass* "
+ << " static const TargetRegisterClass* const "
<< Name << "Superclasses [] = {\n";
bool Empty = true;
___
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[llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
Changes in directory llvm/utils/TableGen:
RegisterInfoEmitter.cpp updated: 1.45 -> 1.46
---
Log message:
Make sub- super- reg-class tables static.
---
Diffs of the changes: (+6 -3)
RegisterInfoEmitter.cpp |9 ++---
1 files changed, 6 insertions(+), 3 deletions(-)
Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.45
llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.46
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.45Wed Jun 14 19:16:37 2006
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Tue Jul 18 17:18:31 2006
@@ -127,7 +127,8 @@
std::string Name = RC.TheDef->getName();
// Emit the register list now.
-OS << " // " << Name << " Register Class...\n const unsigned " << Name
+OS << " // " << Name << " Register Class...\n"
+ << " static const unsigned " << Name
<< "[] = {\n";
for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
Record *Reg = RC.Elements[i];
@@ -180,7 +181,8 @@
}
OS << " // " << Name
- << " Register Class sub-classes...\n const TargetRegisterClass* "
+ << " Register Class sub-classes...\n"
+ << " static const TargetRegisterClass* "
<< Name << "Subclasses [] = {\n";
bool Empty = true;
@@ -214,7 +216,8 @@
std::string Name = RC.TheDef->getName();
OS << " // " << Name
- << " Register Class super-classes...\n const TargetRegisterClass* "
+ << " Register Class super-classes...\n"
+ << " static const TargetRegisterClass* "
<< Name << "Superclasses [] = {\n";
bool Empty = true;
___
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[llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
Changes in directory llvm/utils/TableGen:
RegisterInfoEmitter.cpp updated: 1.43 -> 1.44
---
Log message:
Patches to make the LLVM sources more -pedantic clean. Patch provided
by Anton Korobeynikov! This is a step towards closing PR786:
http://llvm.cs.uiuc.edu/PR786 .
---
Diffs of the changes: (+1 -1)
RegisterInfoEmitter.cpp |2 +-
1 files changed, 1 insertion(+), 1 deletion(-)
Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.43
llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.44
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.43Wed May 17 19:08:46 2006
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Wed May 24 12:04:05 2006
@@ -37,7 +37,7 @@
OS << " enum {\nNoRegister,\n";
for (unsigned i = 0, e = Registers.size(); i != e; ++i)
-OS << "" << Registers[i].getName() << ", \t// " << i+1 << "\n";
+OS << "" << Registers[i].getName() << (i != (e-1) ? ", \t// " : "
\t// ") << i+1 << "\n";
OS << " };\n";
if (!Namespace.empty())
___
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[llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
Changes in directory llvm/utils/TableGen:
RegisterInfoEmitter.cpp updated: 1.41 -> 1.42
---
Log message:
Also add super- register classes info.
---
Diffs of the changes: (+38 -0)
RegisterInfoEmitter.cpp | 38 ++
1 files changed, 38 insertions(+)
Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.41
llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.42
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.41Tue May 9 01:34:26 2006
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Thu May 11 02:30:26 2006
@@ -166,6 +166,7 @@
OS << " " << RegisterClasses[i].getName() << "Class\t"
<< RegisterClasses[i].getName() << "RegClass;\n";
+std::map > SuperClassMap;
OS << "\n";
// Emit the sub-classes array for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
@@ -194,12 +195,48 @@
if (!Empty) OS << ", ";
OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
Empty = false;
+
+std::map >::iterator SCMI =
+ SuperClassMap.find(rc2);
+if (SCMI == SuperClassMap.end()) {
+ SuperClassMap.insert(std::make_pair(rc2, std::set()));
+ SCMI = SuperClassMap.find(rc2);
+}
+SCMI->second.insert(rc);
}
OS << (!Empty ? ", " : "") << "NULL";
OS << "\n };\n\n";
}
+for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
+ const CodeGenRegisterClass &RC = RegisterClasses[rc];
+
+ // Give the register class a legal C name if it's anonymous.
+ std::string Name = RC.TheDef->getName();
+
+ OS << " // " << Name
+ << " Register Class super-classes...\n const TargetRegisterClass* "
+ << Name << "Superclasses [] = {\n";
+
+ bool Empty = true;
+ std::map >::iterator I =
+SuperClassMap.find(rc);
+ if (I != SuperClassMap.end()) {
+for (std::set::iterator II = I->second.begin(),
+ EE = I->second.end(); II != EE; ++II) {
+ const CodeGenRegisterClass &RC2 = RegisterClasses[*II];
+ if (!Empty) OS << ", ";
+ OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
+ Empty = false;
+}
+ }
+
+ OS << (!Empty ? ", " : "") << "NULL";
+ OS << "\n };\n\n";
+}
+
+
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
const CodeGenRegisterClass &RC = RegisterClasses[i];
OS << RC.MethodBodies << "\n";
@@ -207,6 +244,7 @@
<< "Class() : TargetRegisterClass("
<< RC.getName() + "VTs" << ", "
<< RC.getName() + "Subclasses" << ", "
+ << RC.getName() + "Superclasses" << ", "
<< RC.SpillSize/8 << ", "
<< RC.SpillAlignment/8 << ", " << RC.getName() << ", "
<< RC.getName() << " + " << RC.Elements.size() << ") {}\n";
___
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[llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
Changes in directory llvm/utils/TableGen:
RegisterInfoEmitter.cpp updated: 1.40 -> 1.41
---
Log message:
Add sub-register class information.
---
Diffs of the changes: (+49 -3)
RegisterInfoEmitter.cpp | 52 +---
1 files changed, 49 insertions(+), 3 deletions(-)
Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.40
llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.41
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.40Fri Mar 24 15:15:58 2006
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Tue May 9 01:34:26 2006
@@ -89,6 +89,16 @@
OS << "} // End llvm namespace \n";
}
+bool isSubRegisterClass(const CodeGenRegisterClass &RC,
+std::set &RegSet) {
+ for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
+Record *Reg = RC.Elements[i];
+if (!RegSet.count(Reg))
+ return false;
+ }
+ return true;
+}
+
// RegisterInfoEmitter::run - Main register file description emitter.
//
void RegisterInfoEmitter::run(std::ostream &OS) {
@@ -130,7 +140,7 @@
}
OS << "\n };\n\n";
}
-
+
// Emit the ValueType arrays for each RegisterClass
for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
const CodeGenRegisterClass &RC = RegisterClasses[rc];
@@ -155,12 +165,48 @@
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i)
OS << " " << RegisterClasses[i].getName() << "Class\t"
<< RegisterClasses[i].getName() << "RegClass;\n";
-
+
+OS << "\n";
+// Emit the sub-classes array for each RegisterClass
+for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) {
+ const CodeGenRegisterClass &RC = RegisterClasses[rc];
+
+ // Give the register class a legal C name if it's anonymous.
+ std::string Name = RC.TheDef->getName();
+
+ std::set RegSet;
+ for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) {
+Record *Reg = RC.Elements[i];
+RegSet.insert(Reg);
+ }
+
+ OS << " // " << Name
+ << " Register Class sub-classes...\n const TargetRegisterClass* "
+ << Name << "Subclasses [] = {\n";
+
+ bool Empty = true;
+ for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) {
+const CodeGenRegisterClass &RC2 = RegisterClasses[rc2];
+if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() ||
+RC.SpillSize != RC2.SpillSize || !isSubRegisterClass(RC2, RegSet))
+ continue;
+
+if (!Empty) OS << ", ";
+OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass";
+Empty = false;
+ }
+
+ OS << (!Empty ? ", " : "") << "NULL";
+ OS << "\n };\n\n";
+}
+
for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) {
const CodeGenRegisterClass &RC = RegisterClasses[i];
OS << RC.MethodBodies << "\n";
OS << RC.getName() << "Class::" << RC.getName()
- << "Class() : TargetRegisterClass(" << RC.getName() + "VTs" << ", "
+ << "Class() : TargetRegisterClass("
+ << RC.getName() + "VTs" << ", "
+ << RC.getName() + "Subclasses" << ", "
<< RC.SpillSize/8 << ", "
<< RC.SpillAlignment/8 << ", " << RC.getName() << ", "
<< RC.getName() << " + " << RC.Elements.size() << ") {}\n";
___
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[llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
Changes in directory llvm/utils/TableGen:
RegisterInfoEmitter.cpp updated: 1.39 -> 1.40
---
Log message:
Add dwarf register numbering to register data.
---
Diffs of the changes: (+18 -1)
RegisterInfoEmitter.cpp | 19 ++-
1 files changed, 18 insertions(+), 1 deletion(-)
Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.39
llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.40
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.39Tue Dec 27 04:56:22 2005
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Fri Mar 24 15:15:58 2006
@@ -60,7 +60,8 @@
<< " " << ClassName
<< "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
<< " const unsigned* getCalleeSaveRegs() const;\n"
- << "const TargetRegisterClass* const *getCalleeSaveRegClasses() const;\n"
+ << " const TargetRegisterClass* const *getCalleeSaveRegClasses()
const;\n"
+ << " int getDwarfRegNum(unsigned RegNum) const;\n"
<< "};\n\n";
const std::vector &RegisterClasses =
@@ -277,6 +278,22 @@
OS << "&" << getQualifiedName(RC->TheDef) << "RegClass, ";
}
OS << " 0\n };\n return CalleeSaveRegClasses;\n}\n\n";
+
+ // Emit information about the dwarf register numbers.
+ OS << "int " << ClassName << "::getDwarfRegNum(unsigned RegNum) const {\n";
+ OS << " static const int DwarfRegNums[] = { -1, // NoRegister";
+ for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
+if (!(i % 16)) OS << "\n";
+const CodeGenRegister &Reg = Registers[i];
+int DwarfRegNum = Reg.TheDef->getValueAsInt("DwarfNumber");
+OS << DwarfRegNum;
+if ((i + 1) != e) OS << ", ";
+ }
+ OS << "\n };\n";
+ OS << " assert(RegNum < (sizeof(DwarfRegNums)/sizeof(int)) &&\n";
+ OS << " \"RegNum exceeds number of registers\");\n";
+ OS << " return DwarfRegNums[RegNum];\n";
+ OS << "}\n\n";
OS << "} // End llvm namespace \n";
}
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[llvm-commits] CVS: llvm/utils/TableGen/RegisterInfoEmitter.cpp
Changes in directory llvm/utils/TableGen:
RegisterInfoEmitter.cpp updated: 1.38 -> 1.39
---
Log message:
This gets most of the backends building with HP HappyC++.
---
Diffs of the changes: (+2 -1)
RegisterInfoEmitter.cpp |3 ++-
1 files changed, 2 insertions(+), 1 deletion(-)
Index: llvm/utils/TableGen/RegisterInfoEmitter.cpp
diff -u llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.38
llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.39
--- llvm/utils/TableGen/RegisterInfoEmitter.cpp:1.38Wed Nov 30 22:51:06 2005
+++ llvm/utils/TableGen/RegisterInfoEmitter.cpp Tue Dec 27 04:56:22 2005
@@ -51,7 +51,8 @@
const std::string &TargetName = Target.getName();
std::string ClassName = TargetName + "GenRegisterInfo";
- OS << "#include \"llvm/Target/MRegisterInfo.h\"\n\n";
+ OS << "#include \"llvm/Target/MRegisterInfo.h\"\n";
+ OS << "#include \n\n";
OS << "namespace llvm {\n\n";
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