Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86.td
> One question: are there any cpus that support "3dnowa" but not > "3dnow"? I definitely think, that no. -- With best regards, Anton Korobeynikov. Faculty of Mathematics & Mechanics, Saint Petersburg State University. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86.td
> >> Does 64-bit imply sse2 or sse3? >> > Again, I didn't know. :-) If they do, I can fix it. X86Subtarget.cpp says that SSE2 is always available if the cpu is 64- bit. Can the logic in that file be simplified with your changes? (is it ever possible to have SSE2 bit set but not SSE1 now?) -Chris > -bw > >> -Chris >> >>> >>> --- >>> Diffs of the changes: (+21 -17) >>> >>> X86.td | 38 +- >>> 1 files changed, 21 insertions(+), 17 deletions(-) >>> >>> >>> Index: llvm/lib/Target/X86/X86.td >>> diff -u llvm/lib/Target/X86/X86.td:1.31 llvm/lib/Target/X86/X86.td: >>> 1.32 >>> --- llvm/lib/Target/X86/X86.td:1.31 Wed Apr 25 16:31:48 2007 >>> +++ llvm/lib/Target/X86/X86.td Fri May 4 15:38:40 2007 >>> @@ -18,24 +18,28 @@ >>> >>> // >>> ===- >>> - >>> - >>> ---===// >>> // X86 Subtarget features. >>> -// >>> +// >>> ===- >>> - >>> - >>> ---===// >>> >>> -def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", >>> "true", >>> -"Support 64-bit >>> instructions">; >>> -def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX", >>> -"Enable MMX instructions">; >>> -def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", >>> "SSE1", >>> -"Enable SSE instructions">; >>> -def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", >>> "SSE2", >>> -"Enable SSE2 >>> instructions">; >>> -def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", >>> "SSE3", >>> -"Enable SSE3 >>> instructions">; >>> -def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", >>> "SSSE3", >>> -"Enable SSSE3 >>> instructions">; >>> -def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", >>> "ThreeDNow", >>> -"Enable 3DNow! >>> instructions">; >>> -def Feature3DNowA: SubtargetFeature<"3dnowa", "X863DNowLevel", >>> "ThreeDNowA", >>> -"Enable 3DNow! Athlon >>> instructions">; >>> +def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", >>> + "Support 64-bit >>> instructions">; >>> +def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX", >>> + "Enable MMX instructions">; >>> +def FeatureSSE1: SubtargetFeature<"sse", "X86SSELevel", "SSE1", >>> + "Enable SSE instructions", >>> + [FeatureMMX]>; >>> +def FeatureSSE2: SubtargetFeature<"sse2", "X86SSELevel", >>> "SSE2", >>> + "Enable SSE2 instructions", >>> + [FeatureSSE1]>; >>> +def FeatureSSE3: SubtargetFeature<"sse3", "X86SSELevel", >>> "SSE3", >>> + "Enable SSE3 instructions", >>> + [FeatureSSE2]>; >>> +def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", >>> "SSSE3", >>> + "Enable SSSE3 instructions", >>> + [FeatureSSE3]>; >>> +def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", >>> "ThreeDNow", >>> + "Enable 3DNow! >>> instructions">; >>> +def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", >>> "ThreeDNowA", >>> + "Enable 3DNow! Athlon >>> instructions">; >>> >>> // >>> ===- >>> - >>> - >>> ---===// >>> // X86 processors supported. >>> >>> >>> >>> ___ >>> llvm-commits mailing list >>> llvm-commits@cs.uiuc.edu >>> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits >> >> ___ >> llvm-commits mailing list >> llvm-commits@cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > ___ > llvm-commits mailing list > llvm-commits@cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86.td
On May 5, 2007, at 1:43 PM, Bill Wendling wrote: > On May 5, 2007, at 1:32 PM, Anton Korobeynikov wrote: > >> Hello, Bill. >> >>> I didn't know if they should or not. Should they? :-) >> I can check anything 3dnow-related in hardware. Do you have some >> testcase? >> > Not for 3dnow...In truth, our support for 3dnow is lacking. We don't > have a lot of the builtins for it supported. One question: are there any cpus that support "3dnowa" but not "3dnow"? I would guess not. -Chris ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86.td
On May 5, 2007, at 1:32 PM, Anton Korobeynikov wrote: > Hello, Bill. > >> I didn't know if they should or not. Should they? :-) > I can check anything 3dnow-related in hardware. Do you have some > testcase? > Not for 3dnow...In truth, our support for 3dnow is lacking. We don't have a lot of the builtins for it supported. -bw ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86.td
Hello, Bill. > I didn't know if they should or not. Should they? :-) I can check anything 3dnow-related in hardware. Do you have some testcase? -- With best regards, Anton Korobeynikov. Faculty of Mathematics & Mechanics, Saint Petersburg State University. ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86.td
On May 5, 2007, at 10:56 AM, Chris Lattner wrote: > On May 4, 2007, at 1:39 PM, Bill Wendling wrote: >> Add an "implies" field to features. This indicates that, if the >> current >> feature is set, then the features in the implied list should be set >> also. >> The opposite is also enforced: if a feature in the implied list >> isn't set, >> then the feature that owns that implies list shouldn't be set either. > > Looks good. Does 3dnowa imply 3dnow? > I didn't know if they should or not. Should they? :-) > Does 64-bit imply sse2 or sse3? > Again, I didn't know. :-) If they do, I can fix it. -bw > -Chris > >> >> --- >> Diffs of the changes: (+21 -17) >> >> X86.td | 38 +- >> 1 files changed, 21 insertions(+), 17 deletions(-) >> >> >> Index: llvm/lib/Target/X86/X86.td >> diff -u llvm/lib/Target/X86/X86.td:1.31 llvm/lib/Target/X86/X86.td: >> 1.32 >> --- llvm/lib/Target/X86/X86.td:1.31 Wed Apr 25 16:31:48 2007 >> +++ llvm/lib/Target/X86/X86.td Fri May 4 15:38:40 2007 >> @@ -18,24 +18,28 @@ >> >> // >> ===-- >> - >> ---===// >> // X86 Subtarget features. >> -// >> +// >> ===-- >> - >> ---===// >> >> -def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", >> "true", >> -"Support 64-bit >> instructions">; >> -def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX", >> -"Enable MMX instructions">; >> -def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", >> "SSE1", >> -"Enable SSE instructions">; >> -def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", >> "SSE2", >> -"Enable SSE2 instructions">; >> -def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", >> "SSE3", >> -"Enable SSE3 instructions">; >> -def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", >> "SSSE3", >> -"Enable SSSE3 >> instructions">; >> -def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", >> "ThreeDNow", >> -"Enable 3DNow! >> instructions">; >> -def Feature3DNowA: SubtargetFeature<"3dnowa", "X863DNowLevel", >> "ThreeDNowA", >> -"Enable 3DNow! Athlon >> instructions">; >> +def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", >> + "Support 64-bit >> instructions">; >> +def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX", >> + "Enable MMX instructions">; >> +def FeatureSSE1: SubtargetFeature<"sse", "X86SSELevel", "SSE1", >> + "Enable SSE instructions", >> + [FeatureMMX]>; >> +def FeatureSSE2: SubtargetFeature<"sse2", "X86SSELevel", "SSE2", >> + "Enable SSE2 instructions", >> + [FeatureSSE1]>; >> +def FeatureSSE3: SubtargetFeature<"sse3", "X86SSELevel", "SSE3", >> + "Enable SSE3 instructions", >> + [FeatureSSE2]>; >> +def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", >> "SSSE3", >> + "Enable SSSE3 instructions", >> + [FeatureSSE3]>; >> +def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", >> "ThreeDNow", >> + "Enable 3DNow! instructions">; >> +def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", >> "ThreeDNowA", >> + "Enable 3DNow! Athlon >> instructions">; >> >> // >> ===-- >> - >> ---===// >> // X86 processors supported. >> >> >> >> ___ >> llvm-commits mailing list >> llvm-commits@cs.uiuc.edu >> http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits > > ___ > llvm-commits mailing list > llvm-commits@cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
Re: [llvm-commits] CVS: llvm/lib/Target/X86/X86.td
On May 4, 2007, at 1:39 PM, Bill Wendling wrote: > Add an "implies" field to features. This indicates that, if the > current > feature is set, then the features in the implied list should be set > also. > The opposite is also enforced: if a feature in the implied list > isn't set, > then the feature that owns that implies list shouldn't be set either. Looks good. Does 3dnowa imply 3dnow? Does 64-bit imply sse2 or sse3? -Chris > > --- > Diffs of the changes: (+21 -17) > > X86.td | 38 +- > 1 files changed, 21 insertions(+), 17 deletions(-) > > > Index: llvm/lib/Target/X86/X86.td > diff -u llvm/lib/Target/X86/X86.td:1.31 llvm/lib/Target/X86/X86.td: > 1.32 > --- llvm/lib/Target/X86/X86.td:1.31 Wed Apr 25 16:31:48 2007 > +++ llvm/lib/Target/X86/X86.tdFri May 4 15:38:40 2007 > @@ -18,24 +18,28 @@ > > // > ===--- > ---===// > // X86 Subtarget features. > -// > +// > ===--- > ---===// > > -def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", > -"Support 64-bit > instructions">; > -def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX", > -"Enable MMX instructions">; > -def FeatureSSE1 : SubtargetFeature<"sse", "X86SSELevel", "SSE1", > -"Enable SSE instructions">; > -def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", > "SSE2", > -"Enable SSE2 instructions">; > -def FeatureSSE3 : SubtargetFeature<"sse3", "X86SSELevel", > "SSE3", > -"Enable SSE3 instructions">; > -def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", > "SSSE3", > -"Enable SSSE3 instructions">; > -def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", > "ThreeDNow", > -"Enable 3DNow! > instructions">; > -def Feature3DNowA: SubtargetFeature<"3dnowa", "X863DNowLevel", > "ThreeDNowA", > -"Enable 3DNow! Athlon > instructions">; > +def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true", > + "Support 64-bit instructions">; > +def FeatureMMX : SubtargetFeature<"mmx","X86SSELevel", "MMX", > + "Enable MMX instructions">; > +def FeatureSSE1: SubtargetFeature<"sse", "X86SSELevel", "SSE1", > + "Enable SSE instructions", > + [FeatureMMX]>; > +def FeatureSSE2: SubtargetFeature<"sse2", "X86SSELevel", "SSE2", > + "Enable SSE2 instructions", > + [FeatureSSE1]>; > +def FeatureSSE3: SubtargetFeature<"sse3", "X86SSELevel", "SSE3", > + "Enable SSE3 instructions", > + [FeatureSSE2]>; > +def FeatureSSSE3 : SubtargetFeature<"ssse3", "X86SSELevel", > "SSSE3", > + "Enable SSSE3 instructions", > + [FeatureSSE3]>; > +def Feature3DNow : SubtargetFeature<"3dnow", "X863DNowLevel", > "ThreeDNow", > + "Enable 3DNow! instructions">; > +def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", > "ThreeDNowA", > + "Enable 3DNow! Athlon > instructions">; > > // > ===--- > ---===// > // X86 processors supported. > > > > ___ > llvm-commits mailing list > llvm-commits@cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits ___ llvm-commits mailing list llvm-commits@cs.uiuc.edu http://lists.cs.uiuc.edu/mailman/listinfo/llvm-commits
