Mesa (master): egl: Check extensions.
Module: Mesa
Branch: master
Commit: 6b2f1561ad66c358a5d6b7a5ed5eb8f550a3b098
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b2f1561ad66c358a5d6b7a5ed5eb8f550a3b098
Author: Chia-I Wu o...@lunarg.com
Date: Fri Sep 24 02:42:15 2010 +0800
egl: Check extensions.
Do not call into the driver if the extension for the called function is
not enabled.
---
src/egl/main/eglapi.c | 52 ++--
1 files changed, 41 insertions(+), 11 deletions(-)
diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index 829d700..e8f856f 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -402,10 +402,15 @@ eglCreateContext(EGLDisplay dpy, EGLConfig config,
EGLContext share_list,
_EGLContext *context;
EGLContext ret;
- if (config)
- _EGL_CHECK_CONFIG(disp, conf, EGL_NO_CONTEXT, drv);
- else
- _EGL_CHECK_DISPLAY(disp, EGL_NO_CONTEXT, drv);
+ _EGL_CHECK_DISPLAY(disp, EGL_NO_CONTEXT, drv);
+
+ if (!config) {
+ /* config may be NULL if surfaceless */
+ if (!disp-Extensions.KHR_surfaceless_gles1
+ !disp-Extensions.KHR_surfaceless_gles2
+ !disp-Extensions.KHR_surfaceless_opengl)
+ RETURN_EGL_ERROR(disp, EGL_BAD_CONFIG, EGL_NO_CONTEXT);
+ }
if (!share share_list != EGL_NO_CONTEXT)
RETURN_EGL_ERROR(disp, EGL_BAD_CONTEXT, EGL_NO_CONTEXT);
@@ -459,9 +464,19 @@ eglMakeCurrent(EGLDisplay dpy, EGLSurface draw, EGLSurface
read,
if (!context ctx != EGL_NO_CONTEXT)
RETURN_EGL_ERROR(disp, EGL_BAD_CONTEXT, EGL_FALSE);
- if ((!draw_surf draw != EGL_NO_SURFACE) ||
- (!read_surf read != EGL_NO_SURFACE))
- RETURN_EGL_ERROR(disp, EGL_BAD_SURFACE, EGL_FALSE);
+ if (!draw_surf || !read_surf) {
+ /* surfaces may be NULL if surfaceless */
+ if (!disp-Extensions.KHR_surfaceless_gles1
+ !disp-Extensions.KHR_surfaceless_gles2
+ !disp-Extensions.KHR_surfaceless_opengl)
+ RETURN_EGL_ERROR(disp, EGL_BAD_SURFACE, EGL_FALSE);
+
+ if ((!draw_surf draw != EGL_NO_SURFACE) ||
+ (!read_surf read != EGL_NO_SURFACE))
+ RETURN_EGL_ERROR(disp, EGL_BAD_SURFACE, EGL_FALSE);
+ if (draw_surf || read_surf)
+ RETURN_EGL_ERROR(disp, EGL_BAD_MATCH, EGL_FALSE);
+ }
ret = drv-API.MakeCurrent(drv, disp, draw_surf, read_surf, context);
@@ -1276,6 +1291,8 @@ eglCreateImageKHR(EGLDisplay dpy, EGLContext ctx, EGLenum
target,
EGLImageKHR ret;
_EGL_CHECK_DISPLAY(disp, EGL_NO_IMAGE_KHR, drv);
+ if (!disp-Extensions.KHR_image_base)
+ RETURN_EGL_EVAL(disp, EGL_NO_IMAGE_KHR);
if (!context ctx != EGL_NO_CONTEXT)
RETURN_EGL_ERROR(disp, EGL_BAD_CONTEXT, EGL_NO_IMAGE_KHR);
@@ -1296,6 +1313,8 @@ eglDestroyImageKHR(EGLDisplay dpy, EGLImageKHR image)
EGLBoolean ret;
_EGL_CHECK_DISPLAY(disp, EGL_FALSE, drv);
+ if (!disp-Extensions.KHR_image_base)
+ RETURN_EGL_EVAL(disp, EGL_FALSE);
if (!img)
RETURN_EGL_ERROR(disp, EGL_BAD_PARAMETER, EGL_FALSE);
@@ -1321,6 +1340,8 @@ eglCreateSyncKHR(EGLDisplay dpy, EGLenum type, const
EGLint *attrib_list)
EGLSyncKHR ret;
_EGL_CHECK_DISPLAY(disp, EGL_NO_SYNC_KHR, drv);
+ if (!disp-Extensions.KHR_reusable_sync)
+ RETURN_EGL_EVAL(disp, EGL_NO_SYNC_KHR);
sync = drv-API.CreateSyncKHR(drv, disp, type, attrib_list);
ret = (sync) ? _eglLinkSync(sync, disp) : EGL_NO_SYNC_KHR;
@@ -1338,6 +1359,8 @@ eglDestroySyncKHR(EGLDisplay dpy, EGLSyncKHR sync)
EGLBoolean ret;
_EGL_CHECK_SYNC(disp, s, EGL_FALSE, drv);
+ assert(disp-Extensions.KHR_reusable_sync);
+
_eglUnlinkSync(s);
ret = drv-API.DestroySyncKHR(drv, disp, s);
@@ -1354,6 +1377,7 @@ eglClientWaitSyncKHR(EGLDisplay dpy, EGLSyncKHR sync,
EGLint flags, EGLTimeKHR t
EGLint ret;
_EGL_CHECK_SYNC(disp, s, EGL_FALSE, drv);
+ assert(disp-Extensions.KHR_reusable_sync);
ret = drv-API.ClientWaitSyncKHR(drv, disp, s, flags, timeout);
RETURN_EGL_EVAL(disp, ret);
@@ -1369,6 +1393,7 @@ eglSignalSyncKHR(EGLDisplay dpy, EGLSyncKHR sync, EGLenum
mode)
EGLBoolean ret;
_EGL_CHECK_SYNC(disp, s, EGL_FALSE, drv);
+ assert(disp-Extensions.KHR_reusable_sync);
ret = drv-API.SignalSyncKHR(drv, disp, s, mode);
RETURN_EGL_EVAL(disp, ret);
@@ -1384,6 +1409,7 @@ eglGetSyncAttribKHR(EGLDisplay dpy, EGLSyncKHR sync,
EGLint attribute, EGLint *v
EGLBoolean ret;
_EGL_CHECK_SYNC(disp, s, EGL_FALSE, drv);
+ assert(disp-Extensions.KHR_reusable_sync);
ret = drv-API.GetSyncAttribKHR(drv, disp, s, attribute, value);
RETURN_EGL_EVAL(disp, ret);
@@ -1407,14 +1433,14 @@ eglSwapBuffersRegionNOK(EGLDisplay dpy, EGLSurface
surface,
_EGL_CHECK_SURFACE(disp, surf, EGL_FALSE, drv);
+ if (!disp-Extensions.NOK_swap_region)
+ RETURN_EGL_EVAL(disp, EGL_FALSE);
+
/* surface must be bound to current context in EGL 1.4 */
if (!ctx || !_eglIsContextLinked(ctx) || surf != ctx-DrawSurface)
Mesa (master): st/egl: Skip single-buffered configs in EGL.
Module: Mesa Branch: master Commit: d63b2622f1c47d6f82fe96c9f1b749d908883a23 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d63b2622f1c47d6f82fe96c9f1b749d908883a23 Author: Chia-I Wu o...@lunarg.com Date: Thu Sep 30 16:53:33 2010 +0800 st/egl: Skip single-buffered configs in EGL. Let DRI2 report single-buffered configs and skip them in EGL. This is based on the patch by Luca Barbieri. --- src/gallium/state_trackers/egl/common/egl_g3d.c |4 src/gallium/state_trackers/egl/x11/native_dri2.c |4 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/gallium/state_trackers/egl/common/egl_g3d.c b/src/gallium/state_trackers/egl/common/egl_g3d.c index ce2b1f7..bfbb431 100644 --- a/src/gallium/state_trackers/egl/common/egl_g3d.c +++ b/src/gallium/state_trackers/egl/common/egl_g3d.c @@ -258,6 +258,10 @@ egl_g3d_init_config(_EGLDriver *drv, _EGLDisplay *dpy, EGLint buffer_mask, api_mask; EGLBoolean valid; + /* skip single-buffered configs */ + if (!(nconf-buffer_mask (1 NATIVE_ATTACHMENT_BACK_LEFT))) + return EGL_FALSE; + buffer_mask = 0x0; if (nconf-buffer_mask (1 NATIVE_ATTACHMENT_FRONT_LEFT)) buffer_mask |= ST_ATTACHMENT_FRONT_LEFT_MASK; diff --git a/src/gallium/state_trackers/egl/x11/native_dri2.c b/src/gallium/state_trackers/egl/x11/native_dri2.c index 1be1e42..1169e27 100644 --- a/src/gallium/state_trackers/egl/x11/native_dri2.c +++ b/src/gallium/state_trackers/egl/x11/native_dri2.c @@ -518,10 +518,6 @@ dri2_display_convert_config(struct native_display *ndpy, if (!(mode-renderType GLX_RGBA_BIT) || !mode-rgbMode) return FALSE; - /* skip single-buffered configs */ - if (!mode-doubleBufferMode) - return FALSE; - /* only interested in native renderable configs */ if (!mode-xRenderable || !mode-drawableType) return FALSE; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mapi: Fix compiler warnings.
Module: Mesa
Branch: master
Commit: ebeb4a7e8af9f59ce8f45f78654b611bb546979d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ebeb4a7e8af9f59ce8f45f78654b611bb546979d
Author: Chia-I Wu o...@lunarg.com
Date: Thu Sep 30 17:09:59 2010 +0800
mapi: Fix compiler warnings.
Do not use void * in arithmetics.
---
src/mapi/mapi/entry_x86-64_tls.h |2 +-
src/mapi/mapi/entry_x86_tls.h|2 +-
src/mapi/mapi/entry_x86_tsd.h|2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mapi/mapi/entry_x86-64_tls.h b/src/mapi/mapi/entry_x86-64_tls.h
index 0f6e812..2fbe73b 100644
--- a/src/mapi/mapi/entry_x86-64_tls.h
+++ b/src/mapi/mapi/entry_x86-64_tls.h
@@ -61,7 +61,7 @@ entry_patch_public(void)
void
entry_patch(mapi_func entry, int slot)
{
- void *code = (void *) entry;
+ char *code = (char *) entry;
*((unsigned int *) (code + 12)) = slot * sizeof(mapi_func);
}
diff --git a/src/mapi/mapi/entry_x86_tls.h b/src/mapi/mapi/entry_x86_tls.h
index ff2b957..d4f7d98 100644
--- a/src/mapi/mapi/entry_x86_tls.h
+++ b/src/mapi/mapi/entry_x86_tls.h
@@ -91,7 +91,7 @@ entry_patch_public(void)
void
entry_patch(mapi_func entry, int slot)
{
- void *code = (void *) entry;
+ char *code = (char *) entry;
*((unsigned long *) (code + 8)) = slot * sizeof(mapi_func);
}
diff --git a/src/mapi/mapi/entry_x86_tsd.h b/src/mapi/mapi/entry_x86_tsd.h
index fbf4ec5..f37c747 100644
--- a/src/mapi/mapi/entry_x86_tsd.h
+++ b/src/mapi/mapi/entry_x86_tsd.h
@@ -63,7 +63,7 @@ entry_patch_public(void)
void
entry_patch(mapi_func entry, int slot)
{
- void *code = (void *) entry;
+ char *code = (char *) entry;
*((unsigned long *) (code + 11)) = slot * sizeof(mapi_func);
*((unsigned long *) (code + 22)) = slot * sizeof(mapi_func);
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Mesa (7.9): mapi: Fix compiler warnings.
Module: Mesa
Branch: 7.9
Commit: f6eb5d991c0b93a89b970c15b9876ec3806a4e36
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f6eb5d991c0b93a89b970c15b9876ec3806a4e36
Author: Chia-I Wu o...@lunarg.com
Date: Thu Sep 30 17:09:59 2010 +0800
mapi: Fix compiler warnings.
Do not use void * in arithmetics.
(cherry picked from commit ebeb4a7e8af9f59ce8f45f78654b611bb546979d)
---
src/mapi/mapi/entry_x86-64_tls.h |2 +-
src/mapi/mapi/entry_x86_tls.h|2 +-
src/mapi/mapi/entry_x86_tsd.h|2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mapi/mapi/entry_x86-64_tls.h b/src/mapi/mapi/entry_x86-64_tls.h
index 0f6e812..2fbe73b 100644
--- a/src/mapi/mapi/entry_x86-64_tls.h
+++ b/src/mapi/mapi/entry_x86-64_tls.h
@@ -61,7 +61,7 @@ entry_patch_public(void)
void
entry_patch(mapi_func entry, int slot)
{
- void *code = (void *) entry;
+ char *code = (char *) entry;
*((unsigned int *) (code + 12)) = slot * sizeof(mapi_func);
}
diff --git a/src/mapi/mapi/entry_x86_tls.h b/src/mapi/mapi/entry_x86_tls.h
index ff2b957..d4f7d98 100644
--- a/src/mapi/mapi/entry_x86_tls.h
+++ b/src/mapi/mapi/entry_x86_tls.h
@@ -91,7 +91,7 @@ entry_patch_public(void)
void
entry_patch(mapi_func entry, int slot)
{
- void *code = (void *) entry;
+ char *code = (char *) entry;
*((unsigned long *) (code + 8)) = slot * sizeof(mapi_func);
}
diff --git a/src/mapi/mapi/entry_x86_tsd.h b/src/mapi/mapi/entry_x86_tsd.h
index fbf4ec5..f37c747 100644
--- a/src/mapi/mapi/entry_x86_tsd.h
+++ b/src/mapi/mapi/entry_x86_tsd.h
@@ -63,7 +63,7 @@ entry_patch_public(void)
void
entry_patch(mapi_func entry, int slot)
{
- void *code = (void *) entry;
+ char *code = (char *) entry;
*((unsigned long *) (code + 11)) = slot * sizeof(mapi_func);
*((unsigned long *) (code + 22)) = slot * sizeof(mapi_func);
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Mesa (master): dri/nouveau: Remove unnecessary flush.
Module: Mesa
Branch: master
Commit: bdd19da2183c685056c4c2eee5cea8358d9935cb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bdd19da2183c685056c4c2eee5cea8358d9935cb
Author: Francisco Jerez curroje...@riseup.net
Date: Tue Sep 28 22:24:05 2010 +0200
dri/nouveau: Remove unnecessary flush.
---
src/mesa/drivers/dri/nouveau/nouveau_context.c |4 +---
1 files changed, 1 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_context.c
b/src/mesa/drivers/dri/nouveau/nouveau_context.c
index fbe4ede..1121d2d 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_context.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_context.c
@@ -353,8 +353,6 @@ nouveau_validate_framebuffer(GLcontext *ctx)
validate_framebuffer(dri_ctx, dri_read,
dri_ctx-dri2.read_stamp);
- if (nouveau_next_dirty_state(ctx) = 0) {
+ if (nouveau_next_dirty_state(ctx) = 0)
nouveau_state_emit(ctx);
- FIRE_RING(context_chan(ctx));
- }
}
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Mesa (master): dri/nouveau: Have a smaller amount of larger scratch buffers .
Module: Mesa
Branch: master
Commit: 6f39280ba910e290fb3cda378057dc91e5811c95
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f39280ba910e290fb3cda378057dc91e5811c95
Author: Francisco Jerez curroje...@riseup.net
Date: Tue Sep 28 22:20:12 2010 +0200
dri/nouveau: Have a smaller amount of larger scratch buffers.
Larger VBOs avoid many kernel trips to get them in sync with the GPU.
---
src/mesa/drivers/dri/nouveau/nouveau_render.h |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_render.h
b/src/mesa/drivers/dri/nouveau/nouveau_render.h
index 923b79b..29d96ed 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_render.h
+++ b/src/mesa/drivers/dri/nouveau/nouveau_render.h
@@ -55,8 +55,8 @@ struct nouveau_array_state {
extract_f_t extract_f;
};
-#define RENDER_SCRATCH_COUNT 32
-#define RENDER_SCRATCH_SIZE 64*1024
+#define RENDER_SCRATCH_COUNT 2
+#define RENDER_SCRATCH_SIZE 2*1024*1024
struct nouveau_scratch_state {
struct nouveau_bo *bo[RENDER_SCRATCH_COUNT];
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Mesa (master): dri/nv10: Use fast Z clears.
Module: Mesa
Branch: master
Commit: 065163bcd2df12494ca523538736282fc847fa6b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=065163bcd2df12494ca523538736282fc847fa6b
Author: Francisco Jerez curroje...@riseup.net
Date: Sat Sep 25 15:29:02 2010 +0200
dri/nv10: Use fast Z clears.
---
src/mesa/drivers/dri/nouveau/nouveau_class.h |6 +++
src/mesa/drivers/dri/nouveau/nouveau_context.h |5 +++
src/mesa/drivers/dri/nouveau/nouveau_fbo.h |6 +++-
src/mesa/drivers/dri/nouveau/nv10_context.c| 45 +---
src/mesa/drivers/dri/nouveau/nv10_driver.h |8
src/mesa/drivers/dri/nouveau/nv10_state_fb.c | 29 +---
6 files changed, 88 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_class.h
b/src/mesa/drivers/dri/nouveau/nouveau_class.h
index 5cb13ac..d41d431 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_class.h
+++ b/src/mesa/drivers/dri/nouveau/nouveau_class.h
@@ -3191,6 +3191,12 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
#define NV17TCL_DMA_IN_MEMORY4
0x01ac
#define NV17TCL_DMA_IN_MEMORY5
0x01b0
#define NV17TCL_COLOR_MASK_ENABLE
0x02bc
+#define NV17TCL_ZCLEAR_ENABLE
0x03f8
+#define NV17TCL_ZCLEAR_VALUE
0x03fc
+#define NV17TCL_ZCLEAR_VALUE_DEPTH_SHIFT
8
+#define NV17TCL_ZCLEAR_VALUE_DEPTH_MASK
0xff00
+#define NV17TCL_ZCLEAR_VALUE_SEQUENCE_SHIFT
0
+#define NV17TCL_ZCLEAR_VALUE_SEQUENCE_MASK
0x00ff
#define NV17TCL_LMA_DEPTH_BUFFER_PITCH
0x0d5c
#define NV17TCL_LMA_DEPTH_BUFFER_OFFSET
0x0d60
#define NV17TCL_LMA_DEPTH_FILL_VALUE
0x0d68
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_context.h
b/src/mesa/drivers/dri/nouveau/nouveau_context.h
index 3dbe729..5f00327 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_context.h
+++ b/src/mesa/drivers/dri/nouveau/nouveau_context.h
@@ -67,6 +67,11 @@ struct nouveau_context {
struct nouveau_hw_state hw;
struct nouveau_bo_state bo;
struct nouveau_render_state render;
+
+ struct {
+ GLboolean clear_blocked;
+ int clear_seq;
+ } hierz;
};
#define to_nouveau_context(ctx)((struct nouveau_context *)(ctx))
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_fbo.h
b/src/mesa/drivers/dri/nouveau/nouveau_fbo.h
index 0fe6c08..05ea03a 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_fbo.h
+++ b/src/mesa/drivers/dri/nouveau/nouveau_fbo.h
@@ -29,8 +29,12 @@
struct nouveau_framebuffer {
struct gl_framebuffer base;
- struct nouveau_bo *lma_bo;
GLboolean need_front;
+
+ struct {
+ struct nouveau_bo *bo;
+ uint32_t clear_value;
+ } hierz;
};
#define to_nouveau_framebuffer(x) ((struct nouveau_framebuffer *)(x))
diff --git a/src/mesa/drivers/dri/nouveau/nv10_context.c
b/src/mesa/drivers/dri/nouveau/nv10_context.c
index 08be2a2..41723ff 100644
--- a/src/mesa/drivers/dri/nouveau/nv10_context.c
+++ b/src/mesa/drivers/dri/nouveau/nv10_context.c
@@ -40,9 +40,31 @@ static const struct dri_extension nv10_extensions[] = {
{ NULL, NULL }
};
+static GLboolean
+use_fast_zclear(GLcontext *ctx, GLbitfield buffers)
+{
+ struct nouveau_context *nctx = to_nouveau_context(ctx);
+ struct gl_framebuffer *fb = ctx-DrawBuffer;
+
+ if (buffers BUFFER_BIT_STENCIL) {
+ /*
+* The stencil test is bypassed when fast Z clears are
+* enabled.
+*/
+ nctx-hierz.clear_blocked = GL_TRUE;
+ context_dirty(ctx, ZCLEAR);
+ return GL_FALSE;
+ }
+
+ return !nctx-hierz.clear_blocked
+ fb-_Xmax == fb-Width fb-_Xmin == 0
+ fb-_Ymax == fb-Height fb-_Ymin == 0;
+}
+
static void
nv10_clear(GLcontext *ctx, GLbitfield buffers)
{
+ struct nouveau_context *nctx = to_nouveau_context(ctx);
struct nouveau_channel *chan = context_chan(ctx);
struct nouveau_grobj *celsius = context_eng3d(ctx);
struct nouveau_framebuffer *nfb = to_nouveau_framebuffer(
@@ -50,16 +72,28 @@ nv10_clear(GLcontext *ctx, GLbitfield buffers)
nouveau_validate_framebuffer(ctx);
- /* Clear the LMA depth buffer, if present. */
- if ((buffers BUFFER_BIT_DEPTH)
Mesa (master): 24 new commits
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4160d947d289c07f1de6b8bf21a874e842b51f51 Author: Nicolas Kaiser ni...@nikai.net Date: Thu Sep 30 07:53:13 2010 -0700 st: remove duplicated include Remove duplicated include. Signed-off-by: Brian Paul bri...@vmware.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bad10b961aeae8d695ecec600d47de5f8505b396 Author: Nicolas Kaiser ni...@nikai.net Date: Thu Sep 30 07:52:02 2010 -0700 math: remove duplicated includes Remove duplicated includes. Signed-off-by: Brian Paul bri...@vmware.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9674929bce0c0ea4862b468d0a1a7e58b2664049 Author: Nicolas Kaiser ni...@nikai.net Date: Thu Sep 30 07:50:43 2010 -0700 main: remove duplicated includes Remove duplicated includes. Signed-off-by: Brian Paul bri...@vmware.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c92a80b6210bf7d977816690476ff336b350c79 Author: Nicolas Kaiser ni...@nikai.net Date: Thu Sep 30 07:48:29 2010 -0700 dri/savage: remove duplicated include Remove duplicated include. Signed-off-by: Brian Paul bri...@vmware.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1663e6da2f15ff8db9f08ca6a7337f8bd28add17 Author: Nicolas Kaiser ni...@nikai.net Date: Thu Sep 30 07:47:22 2010 -0700 dri/radeon: remove duplicated includes Remove duplicated includes. Signed-off-by: Brian Paul bri...@vmware.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7670be8a15c56b625f2f1aad08eeff2414200b4 Author: Nicolas Kaiser ni...@nikai.net Date: Thu Sep 30 07:46:06 2010 -0700 dri/r600: remove duplicated include Remove duplicated include. Signed-off-by: Brian Paul bri...@vmware.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=223c4b418854a6c260723ae8bc4afd7a27463c22 Author: Nicolas Kaiser ni...@nikai.net Date: Thu Sep 30 07:44:55 2010 -0700 dri/r300: remove duplicated include Remove duplicated include. Signed-off-by: Brian Paul bri...@vmware.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=705d98deb80db476ef37674d256530fae68171c1 Author: Nicolas Kaiser ni...@nikai.net Date: Thu Sep 30 07:43:48 2010 -0700 dri/r128: remove duplicated include Remove duplicated include. Signed-off-by: Brian Paul bri...@vmware.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f094b352073bf5414a101b056f47f1ee2f814e81 Author: Nicolas Kaiser ni...@nikai.net Date: Thu Sep 30 07:42:41 2010 -0700 dri/mga: remove duplicated include Remove duplicated include. Signed-off-by: Brian Paul bri...@vmware.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a98a463043e1558b1ad6ebf79a1371d6218ac5a Author: Nicolas Kaiser ni...@nikai.net Date: Thu Sep 30 07:41:26 2010 -0700 dri/intel: remove duplicated include Remove duplicated include. Signed-off-by: Brian Paul bri...@vmware.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c24144f41fe797a0448f60705d9023902f1178ce Author: Nicolas Kaiser ni...@nikai.net Date: Thu Sep 30 07:39:59 2010 -0700 dri/i965: remove duplicated include Remove duplicated include. Signed-off-by: Brian Paul bri...@vmware.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f831212eabe25ea2603be13d8d40b12477012acc Author: Nicolas Kaiser ni...@nikai.net Date: Thu Sep 30 07:38:53 2010 -0700 dri/i915: remove duplicated include Remove duplicated include. Signed-off-by: Brian Paul bri...@vmware.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b958dabe1602d9a59b0aef0c004f8cf20c3e9c70 Author: Nicolas Kaiser ni...@nikai.net Date: Thu Sep 30 07:37:26 2010 -0700 dri/i810: remove duplicated include Remove duplicated include. Signed-off-by: Brian Paul bri...@vmware.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c24e062fdbf21114904258687f95d3d45911f893 Author: Nicolas Kaiser ni...@nikai.net Date: Thu Sep 30 07:36:12 2010 -0700 dri/common: remove duplicated include Remove duplicated include. Signed-off-by: Brian Paul bri...@vmware.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7eed3dba58740a8ade94cfab315afa198d1beebe Author: Nicolas Kaiser ni...@nikai.net Date: Thu Sep 30 07:34:53 2010 -0700 glx: remove duplicated include Remove duplicated include. Signed-off-by: Brian Paul bri...@vmware.com URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f28dbd9bb78f03681005cafa115008595b3c27d Author: Nicolas Kaiser ni...@nikai.net Date: Thu Sep 30 07:33:43 2010 -0700 gallium/winsys: remove duplicated include Remove duplicated include. Signed-off-by: Brian Paul bri...@vmware.com URL:
Mesa (master): st/egl: Drop context argument from egl_g3d_get_egl_image.
Module: Mesa
Branch: master
Commit: e2b51b7c5b21e64df1377ce0be5c83d016ff
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2b51b7c5b21e64df1377ce0be5c83d016ff
Author: Chia-I Wu o...@lunarg.com
Date: Thu Sep 30 23:43:58 2010 +0800
st/egl: Drop context argument from egl_g3d_get_egl_image.
Fix a regression since 17eace581d25a626a7d75d9d1205d012cbb14a6e.
---
src/gallium/state_trackers/egl/common/egl_g3d_st.c |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/src/gallium/state_trackers/egl/common/egl_g3d_st.c
b/src/gallium/state_trackers/egl/common/egl_g3d_st.c
index 05cdb0d..0affe63 100644
--- a/src/gallium/state_trackers/egl/common/egl_g3d_st.c
+++ b/src/gallium/state_trackers/egl/common/egl_g3d_st.c
@@ -51,7 +51,6 @@ egl_g3d_st_manager(struct st_manager *smapi)
static boolean
egl_g3d_st_manager_get_egl_image(struct st_manager *smapi,
- struct st_context_iface *stctx,
void *egl_image,
struct st_egl_image *out)
{
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Mesa (7.9): st/egl: Drop context argument from egl_g3d_get_egl_image.
Module: Mesa
Branch: 7.9
Commit: 9bab8ca4f8c8f3e618bfa8e9aedfcdcf272d3495
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9bab8ca4f8c8f3e618bfa8e9aedfcdcf272d3495
Author: Chia-I Wu o...@lunarg.com
Date: Thu Sep 30 23:43:58 2010 +0800
st/egl: Drop context argument from egl_g3d_get_egl_image.
Fix a regression since 17eace581d25a626a7d75d9d1205d012cbb14a6e.
(cherry picked from commit e2b51b7c5b21e64df1377ce0be5c83d016ff)
---
src/gallium/state_trackers/egl/common/egl_g3d_st.c |1 -
1 files changed, 0 insertions(+), 1 deletions(-)
diff --git a/src/gallium/state_trackers/egl/common/egl_g3d_st.c
b/src/gallium/state_trackers/egl/common/egl_g3d_st.c
index 05cdb0d..0affe63 100644
--- a/src/gallium/state_trackers/egl/common/egl_g3d_st.c
+++ b/src/gallium/state_trackers/egl/common/egl_g3d_st.c
@@ -51,7 +51,6 @@ egl_g3d_st_manager(struct st_manager *smapi)
static boolean
egl_g3d_st_manager_get_egl_image(struct st_manager *smapi,
- struct st_context_iface *stctx,
void *egl_image,
struct st_egl_image *out)
{
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Mesa (master): gallivm: More comprehensive border usage logic.
Module: Mesa
Branch: master
Commit: 4e6f5e8d43ee87c6f8cdc75de2eeb96f70beb013
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e6f5e8d43ee87c6f8cdc75de2eeb96f70beb013
Author: José Fonseca jfons...@vmware.com
Date: Thu Sep 30 17:39:17 2010 +0100
gallivm: More comprehensive border usage logic.
---
src/gallium/auxiliary/gallivm/lp_bld_sample.c | 33
src/gallium/auxiliary/gallivm/lp_bld_sample.h |5 ++
src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c | 42 ++--
3 files changed, 51 insertions(+), 29 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample.c
b/src/gallium/auxiliary/gallivm/lp_bld_sample.c
index d9fbc0f..d9fbbbe 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample.c
@@ -46,6 +46,39 @@
/**
+ * Does the given texture wrap mode allow sampling the texture border color?
+ * XXX maybe move this into gallium util code.
+ */
+boolean
+lp_sampler_wrap_mode_uses_border_color(unsigned mode,
+ unsigned min_img_filter,
+ unsigned mag_img_filter)
+{
+ switch (mode) {
+ case PIPE_TEX_WRAP_REPEAT:
+ case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
+ case PIPE_TEX_WRAP_MIRROR_REPEAT:
+ case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
+ return FALSE;
+ case PIPE_TEX_WRAP_CLAMP:
+ case PIPE_TEX_WRAP_MIRROR_CLAMP:
+ if (min_img_filter == PIPE_TEX_FILTER_NEAREST
+ mag_img_filter == PIPE_TEX_FILTER_NEAREST) {
+ return FALSE;
+ } else {
+ return TRUE;
+ }
+ case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
+ case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
+ return TRUE;
+ default:
+ assert(0 unexpected wrap mode);
+ return FALSE;
+ }
+}
+
+
+/**
* Initialize lp_sampler_static_state object with the gallium sampler
* and texture state.
* The former is considered to be static and the later dynamic.
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample.h
b/src/gallium/auxiliary/gallivm/lp_bld_sample.h
index bb48578..9fc9a38 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample.h
@@ -254,6 +254,11 @@ texture_dims(enum pipe_texture_target tex)
}
+boolean
+lp_sampler_wrap_mode_uses_border_color(unsigned mode,
+ unsigned min_img_filter,
+ unsigned mag_img_filter);
+
/**
* Derive the sampler static state.
*/
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
index 33740f9..36a77d3 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
@@ -59,31 +59,6 @@
/**
- * Does the given texture wrap mode allow sampling the texture border color?
- * XXX maybe move this into gallium util code.
- */
-static boolean
-wrap_mode_uses_border_color(unsigned mode)
-{
- switch (mode) {
- case PIPE_TEX_WRAP_REPEAT:
- case PIPE_TEX_WRAP_CLAMP_TO_EDGE:
- case PIPE_TEX_WRAP_MIRROR_REPEAT:
- case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_EDGE:
- return FALSE;
- case PIPE_TEX_WRAP_CLAMP:
- case PIPE_TEX_WRAP_CLAMP_TO_BORDER:
- case PIPE_TEX_WRAP_MIRROR_CLAMP:
- case PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER:
- return TRUE;
- default:
- assert(0 unexpected wrap mode);
- return FALSE;
- }
-}
-
-
-/**
* Generate code to fetch a texel from a texture at int coords (x, y, z).
* The computation depends on whether the texture is 1D, 2D or 3D.
* The result, texel, will be float vectors:
@@ -106,21 +81,27 @@ lp_build_sample_texel_soa(struct lp_build_sample_context
*bld,
LLVMValueRef data_ptr,
LLVMValueRef texel_out[4])
{
- const int dims = texture_dims(bld-static_state-target);
+ const struct lp_sampler_static_state *static_state = bld-static_state;
+ const int dims = texture_dims(static_state-target);
struct lp_build_context *int_coord_bld = bld-int_coord_bld;
LLVMValueRef offset;
LLVMValueRef i, j;
LLVMValueRef use_border = NULL;
/* use_border = x 0 || x = width || y 0 || y = height */
- if (wrap_mode_uses_border_color(bld-static_state-wrap_s)) {
+ if (lp_sampler_wrap_mode_uses_border_color(static_state-wrap_s,
+ static_state-min_img_filter,
+ static_state-mag_img_filter)) {
LLVMValueRef b1, b2;
b1 = lp_build_cmp(int_coord_bld, PIPE_FUNC_LESS, x, int_coord_bld-zero);
b2 = lp_build_cmp(int_coord_bld, PIPE_FUNC_GEQUAL, x, width);
use_border = LLVMBuildOr(bld-builder, b1, b2, b1_or_b2);
}
- if (dims = 2 wrap_mode_uses_border_color(bld-static_state-wrap_t)) {
+ if (dims = 2
+ lp_sampler_wrap_mode_uses_border_color(static_state-wrap_t,
+
Mesa (master): gallivm: check for level=0 case in lp_build_minify()
Module: Mesa
Branch: master
Commit: 874f3a57ce5ae41ced103bf5a549a2eb663db6c5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=874f3a57ce5ae41ced103bf5a549a2eb663db6c5
Author: Brian Paul bri...@vmware.com
Date: Thu Sep 30 10:52:26 2010 -0600
gallivm: check for level=0 case in lp_build_minify()
This lets us avoid the shift and max() operations.
---
src/gallium/auxiliary/gallivm/lp_bld_sample.c | 13 ++---
1 files changed, 10 insertions(+), 3 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample.c
b/src/gallium/auxiliary/gallivm/lp_bld_sample.c
index d9fbbbe..6e53bca 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample.c
@@ -362,9 +362,16 @@ lp_build_minify(struct lp_build_sample_context *bld,
LLVMValueRef base_size,
LLVMValueRef level)
{
- LLVMValueRef size = LLVMBuildLShr(bld-builder, base_size, level, minify);
- size = lp_build_max(bld-int_coord_bld, size, bld-int_coord_bld.one);
- return size;
+ if (level == bld-int_coord_bld.zero) {
+ /* if we're using mipmap level zero, no minification is needed */
+ return base_size;
+ }
+ else {
+ LLVMValueRef size =
+ LLVMBuildLShr(bld-builder, base_size, level, minify);
+ size = lp_build_max(bld-int_coord_bld, size, bld-int_coord_bld.one);
+ return size;
+ }
}
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Mesa (master): r600g: use constant buffer instead of register for constant
Module: Mesa
Branch: master
Commit: 153105cfbfd8d6ff30de144605016f6e4f2a1b9e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=153105cfbfd8d6ff30de144605016f6e4f2a1b9e
Author: Jerome Glisse jgli...@redhat.com
Date: Thu Sep 30 10:43:26 2010 -0400
r600g: use constant buffer instead of register for constant
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/r600_state.c | 47 +++--
src/gallium/drivers/r600/r600d.h |5 +++
src/gallium/winsys/r600/drm/r600_hw_context.c | 34 +++---
src/gallium/winsys/r600/drm/r600d.h |5 +++
4 files changed, 36 insertions(+), 55 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 23323f1..23c2e59 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1148,41 +1148,35 @@ static void r600_set_constant_buffer(struct
pipe_context *ctx, uint shader, uint
struct pipe_resource *buffer)
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
- struct r600_pipe_state *rstate;
- struct pipe_transfer *transfer;
- unsigned *nconst = NULL;
- u32 *ptr, offset;
+ struct r600_resource *rbuffer = (struct r600_resource*)buffer;
switch (shader) {
case PIPE_SHADER_VERTEX:
- rstate = rctx-vs_const;
- nconst = rctx-vs_nconst;
- offset = R_03_SQ_ALU_CONSTANT0_0 + 0x1000;
+ rctx-vs_const_buffer.nregs = 0;
+ r600_pipe_state_add_reg(rctx-vs_const_buffer,
+ R_028180_ALU_CONST_BUFFER_SIZE_VS_0,
+ ALIGN_DIVUP(buffer-width0 4, 16),
+ 0x, NULL);
+ r600_pipe_state_add_reg(rctx-vs_const_buffer,
+ R_028980_ALU_CONST_CACHE_VS_0,
+ 0, 0x, rbuffer-bo);
+ r600_context_pipe_state_set(rctx-ctx, rctx-vs_const_buffer);
break;
case PIPE_SHADER_FRAGMENT:
- rstate = rctx-ps_const;
- nconst = rctx-ps_nconst;
- offset = R_03_SQ_ALU_CONSTANT0_0;
+ rctx-ps_const_buffer.nregs = 0;
+ r600_pipe_state_add_reg(rctx-ps_const_buffer,
+ R_028140_ALU_CONST_BUFFER_SIZE_PS_0,
+ ALIGN_DIVUP(buffer-width0 4, 16),
+ 0x, NULL);
+ r600_pipe_state_add_reg(rctx-ps_const_buffer,
+ R_028940_ALU_CONST_CACHE_PS_0,
+ 0, 0x, rbuffer-bo);
+ r600_context_pipe_state_set(rctx-ctx, rctx-ps_const_buffer);
break;
default:
R600_ERR(unsupported %d\n, shader);
return;
}
- if (buffer buffer-width0 0) {
- *nconst = buffer-width0 / 16;
- ptr = pipe_buffer_map(ctx, buffer, PIPE_TRANSFER_READ,
transfer);
- if (ptr == NULL)
- return;
- for (int i = 0; i *nconst; i++, offset += 0x10) {
- rstate[i].nregs = 0;
- r600_pipe_state_add_reg(rstate[i], offset + 0x0, ptr[i
* 4 + 0], 0x, NULL);
- r600_pipe_state_add_reg(rstate[i], offset + 0x4, ptr[i
* 4 + 1], 0x, NULL);
- r600_pipe_state_add_reg(rstate[i], offset + 0x8, ptr[i
* 4 + 2], 0x, NULL);
- r600_pipe_state_add_reg(rstate[i], offset + 0xC, ptr[i
* 4 + 3], 0x, NULL);
- r600_context_pipe_state_set(rctx-ctx, rstate[i]);
- }
- pipe_buffer_unmap(ctx, buffer, transfer);
- }
}
static void *r600_create_shader_state(struct pipe_context *ctx,
@@ -1191,6 +1185,7 @@ static void *r600_create_shader_state(struct pipe_context
*ctx,
struct r600_pipe_shader *shader = CALLOC_STRUCT(r600_pipe_shader);
int r;
+ shader-shader.use_mem_constant = TRUE;
r = r600_pipe_shader_create(ctx, shader, state-tokens);
if (r) {
return NULL;
@@ -1436,7 +1431,7 @@ void r600_init_config(struct r600_pipe_context *rctx)
tmp |= S_008C00_VC_ENABLE(1);
break;
}
- tmp |= S_008C00_DX9_CONSTS(1);
+ tmp |= S_008C00_DX9_CONSTS(0);
tmp |= S_008C00_ALU_INST_PREFER_VECTOR(1);
tmp |= S_008C00_PS_PRIO(ps_prio);
tmp |= S_008C00_VS_PRIO(vs_prio);
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 47ab1eb..169cda5 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
Mesa (master): i965: Update renderer strings for sandybridge
Module: Mesa Branch: master Commit: 0c86e1f29483d9557f30796c03b94a34d965c095 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c86e1f29483d9557f30796c03b94a34d965c095 Author: Adam Jackson a...@redhat.com Date: Thu Sep 30 14:08:35 2010 -0400 i965: Update renderer strings for sandybridge Signed-off-by: Adam Jackson a...@redhat.com --- src/mesa/drivers/dri/intel/intel_context.c | 13 + 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index edcc953..039ac6d 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -163,6 +163,19 @@ intelGetString(GLcontext * ctx, GLenum name) case PCI_CHIP_ILM_G: chipset = Intel(R) Ironlake Mobile; break; + case PCI_CHIP_SANDYBRIDGE_GT1: + case PCI_CHIP_SANDYBRIDGE_GT2: + case PCI_CHIP_SANDYBRIDGE_GT2_PLUS: +chipset = Intel(R) Sandybridge Desktop; +break; + case PCI_CHIP_SANDYBRIDGE_M_GT1: + case PCI_CHIP_SANDYBRIDGE_M_GT2: + case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS: +chipset = Intel(R) Sandybridge Mobile; +break; + case PCI_CHIP_SANDYBRIDGE_S: +chipset = Intel(R) Sandybridge Server; +break; default: chipset = Unknown Intel Chipset; break; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (7.8): Implement x86_64 atomics for compilers w/o intrinsics.
Module: Mesa
Branch: 7.8
Commit: cc32ff741c5d32a66531a586b1f9268b94846c58
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc32ff741c5d32a66531a586b1f9268b94846c58
Author: Tom Fogal tfo...@alumni.unh.edu
Date: Sun Sep 26 18:57:59 2010 -0600
Implement x86_64 atomics for compilers w/o intrinsics.
Really old gcc's (3.3, at least) don't have support for the
intrinsics we need. This implements a fallback for that case.
---
src/gallium/auxiliary/util/u_atomic.h | 47 +
1 files changed, 47 insertions(+), 0 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_atomic.h
b/src/gallium/auxiliary/util/u_atomic.h
index a156823..8434491 100644
--- a/src/gallium/auxiliary/util/u_atomic.h
+++ b/src/gallium/auxiliary/util/u_atomic.h
@@ -29,6 +29,8 @@
#define PIPE_ATOMIC_ASM_MSVC_X86
#elif (defined(PIPE_CC_GCC) defined(PIPE_ARCH_X86))
#define PIPE_ATOMIC_ASM_GCC_X86
+#elif (defined(PIPE_CC_GCC) defined(PIPE_ARCH_X86_64))
+#define PIPE_ATOMIC_ASM_GCC_X86_64
#elif defined(PIPE_CC_GCC) (PIPE_CC_GCC_VERSION = 401)
#define PIPE_ATOMIC_GCC_INTRINSIC
#else
@@ -36,6 +38,51 @@
#endif
+#if defined(PIPE_ATOMIC_ASM_GCC_X86_64)
+#define PIPE_ATOMIC GCC x86_64 assembly
+
+#ifdef __cplusplus
+extern C {
+#endif
+
+#define p_atomic_set(_v, _i) (*(_v) = (_i))
+#define p_atomic_read(_v) (*(_v))
+
+static INLINE boolean
+p_atomic_dec_zero(int32_t *v)
+{
+ unsigned char c;
+
+ __asm__ __volatile__(lock; decl %0; sete %1:+m(*v), =qm(c)
+ ::memory);
+
+ return c != 0;
+}
+
+static INLINE void
+p_atomic_inc(int32_t *v)
+{
+ __asm__ __volatile__(lock; incl %0:+m(*v));
+}
+
+static INLINE void
+p_atomic_dec(int32_t *v)
+{
+ __asm__ __volatile__(lock; decl %0:+m(*v));
+}
+
+static INLINE int32_t
+p_atomic_cmpxchg(int32_t *v, int32_t old, int32_t _new)
+{
+ return __sync_val_compare_and_swap(v, old, _new);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PIPE_ATOMIC_ASM_GCC_X86_64 */
+
#if defined(PIPE_ATOMIC_ASM_GCC_X86)
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Mesa (7.8): Prefer intrinsics to handrolled atomic ops.
Module: Mesa Branch: 7.8 Commit: 337dace22dc2b0eab2372375f1574d94b894ef84 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=337dace22dc2b0eab2372375f1574d94b894ef84 Author: Tom Fogal tfo...@alumni.unh.edu Date: Sun Sep 26 22:32:15 2010 -0600 Prefer intrinsics to handrolled atomic ops. --- src/gallium/auxiliary/util/u_atomic.h |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/auxiliary/util/u_atomic.h b/src/gallium/auxiliary/util/u_atomic.h index 8434491..4ae6def 100644 --- a/src/gallium/auxiliary/util/u_atomic.h +++ b/src/gallium/auxiliary/util/u_atomic.h @@ -27,12 +27,12 @@ #define PIPE_ATOMIC_MSVC_INTRINSIC #elif (defined(PIPE_CC_MSVC) defined(PIPE_ARCH_X86)) #define PIPE_ATOMIC_ASM_MSVC_X86 +#elif defined(PIPE_CC_GCC) (PIPE_CC_GCC_VERSION = 401) +#define PIPE_ATOMIC_GCC_INTRINSIC #elif (defined(PIPE_CC_GCC) defined(PIPE_ARCH_X86)) #define PIPE_ATOMIC_ASM_GCC_X86 #elif (defined(PIPE_CC_GCC) defined(PIPE_ARCH_X86_64)) #define PIPE_ATOMIC_ASM_GCC_X86_64 -#elif defined(PIPE_CC_GCC) (PIPE_CC_GCC_VERSION = 401) -#define PIPE_ATOMIC_GCC_INTRINSIC #else #error Unsupported platform #endif ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): Implement x86_64 atomics for compilers w/o intrinsics.
Module: Mesa
Branch: master
Commit: 76a60faf529e6107e3f50406c0d40e64bc484686
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=76a60faf529e6107e3f50406c0d40e64bc484686
Author: Tom Fogal tfo...@alumni.unh.edu
Date: Sun Sep 26 18:57:59 2010 -0600
Implement x86_64 atomics for compilers w/o intrinsics.
Really old gcc's (3.3, at least) don't have support for the
intrinsics we need. This implements a fallback for that case.
---
src/gallium/auxiliary/util/u_atomic.h | 47 +
1 files changed, 47 insertions(+), 0 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_atomic.h
b/src/gallium/auxiliary/util/u_atomic.h
index a156823..8434491 100644
--- a/src/gallium/auxiliary/util/u_atomic.h
+++ b/src/gallium/auxiliary/util/u_atomic.h
@@ -29,6 +29,8 @@
#define PIPE_ATOMIC_ASM_MSVC_X86
#elif (defined(PIPE_CC_GCC) defined(PIPE_ARCH_X86))
#define PIPE_ATOMIC_ASM_GCC_X86
+#elif (defined(PIPE_CC_GCC) defined(PIPE_ARCH_X86_64))
+#define PIPE_ATOMIC_ASM_GCC_X86_64
#elif defined(PIPE_CC_GCC) (PIPE_CC_GCC_VERSION = 401)
#define PIPE_ATOMIC_GCC_INTRINSIC
#else
@@ -36,6 +38,51 @@
#endif
+#if defined(PIPE_ATOMIC_ASM_GCC_X86_64)
+#define PIPE_ATOMIC GCC x86_64 assembly
+
+#ifdef __cplusplus
+extern C {
+#endif
+
+#define p_atomic_set(_v, _i) (*(_v) = (_i))
+#define p_atomic_read(_v) (*(_v))
+
+static INLINE boolean
+p_atomic_dec_zero(int32_t *v)
+{
+ unsigned char c;
+
+ __asm__ __volatile__(lock; decl %0; sete %1:+m(*v), =qm(c)
+ ::memory);
+
+ return c != 0;
+}
+
+static INLINE void
+p_atomic_inc(int32_t *v)
+{
+ __asm__ __volatile__(lock; incl %0:+m(*v));
+}
+
+static INLINE void
+p_atomic_dec(int32_t *v)
+{
+ __asm__ __volatile__(lock; decl %0:+m(*v));
+}
+
+static INLINE int32_t
+p_atomic_cmpxchg(int32_t *v, int32_t old, int32_t _new)
+{
+ return __sync_val_compare_and_swap(v, old, _new);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PIPE_ATOMIC_ASM_GCC_X86_64 */
+
#if defined(PIPE_ATOMIC_ASM_GCC_X86)
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Mesa (master): Prefer intrinsics to handrolled atomic ops.
Module: Mesa Branch: master Commit: 5f66b340aa49c6bc8d0acb2d1a6f8e9a7ef2cb2e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f66b340aa49c6bc8d0acb2d1a6f8e9a7ef2cb2e Author: Tom Fogal tfo...@alumni.unh.edu Date: Sun Sep 26 22:32:15 2010 -0600 Prefer intrinsics to handrolled atomic ops. --- src/gallium/auxiliary/util/u_atomic.h |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/auxiliary/util/u_atomic.h b/src/gallium/auxiliary/util/u_atomic.h index 8434491..4ae6def 100644 --- a/src/gallium/auxiliary/util/u_atomic.h +++ b/src/gallium/auxiliary/util/u_atomic.h @@ -27,12 +27,12 @@ #define PIPE_ATOMIC_MSVC_INTRINSIC #elif (defined(PIPE_CC_MSVC) defined(PIPE_ARCH_X86)) #define PIPE_ATOMIC_ASM_MSVC_X86 +#elif defined(PIPE_CC_GCC) (PIPE_CC_GCC_VERSION = 401) +#define PIPE_ATOMIC_GCC_INTRINSIC #elif (defined(PIPE_CC_GCC) defined(PIPE_ARCH_X86)) #define PIPE_ATOMIC_ASM_GCC_X86 #elif (defined(PIPE_CC_GCC) defined(PIPE_ARCH_X86_64)) #define PIPE_ATOMIC_ASM_GCC_X86_64 -#elif defined(PIPE_CC_GCC) (PIPE_CC_GCC_VERSION = 401) -#define PIPE_ATOMIC_GCC_INTRINSIC #else #error Unsupported platform #endif ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (7.9): r300g: fix conditional rendering in non-wait path
Module: Mesa
Branch: 7.9
Commit: 9f076a0848fcb26fd8ae4551aa0db1d1f709e502
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f076a0848fcb26fd8ae4551aa0db1d1f709e502
Author: Marek Olšák mar...@gmail.com
Date: Thu Sep 30 01:08:58 2010 +0200
r300g: fix conditional rendering in non-wait path
NOTE: This is a candidate for the 7.9 branch.
(cherry picked from commit 83278d384ee123fa207229cc444f6e77e2d9a0d2)
---
src/gallium/drivers/r300/r300_query.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/r300/r300_query.c
b/src/gallium/drivers/r300/r300_query.c
index 5b0121c..5f34fcb 100644
--- a/src/gallium/drivers/r300/r300_query.c
+++ b/src/gallium/drivers/r300/r300_query.c
@@ -158,7 +158,7 @@ static void r300_render_condition(struct pipe_context *pipe,
uint mode)
{
struct r300_context *r300 = r300_context(pipe);
-uint64_t result;
+uint64_t result = 0;
boolean wait;
if (query) {
@@ -167,9 +167,9 @@ static void r300_render_condition(struct pipe_context *pipe,
if (!r300_get_query_result(pipe, query, wait, result)) {
r300-skip_rendering = FALSE;
+} else {
+r300-skip_rendering = result == 0;
}
-
-r300-skip_rendering = result == 0;
} else {
r300-skip_rendering = FALSE;
}
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Mesa (7.9): glsl: Copyright, not Constantright
Module: Mesa Branch: 7.9 Commit: 5d43c78d03f05e8a6023265a0c12a8bed1a3ff01 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d43c78d03f05e8a6023265a0c12a8bed1a3ff01 Author: Kenneth Graunke kenn...@whitecape.org Date: Tue Sep 28 21:13:41 2010 -0700 glsl: Copyright, not Constantright Clearly this started out as ir_copy_propagation.cpp, but the search and replace was a bit overzealous. (cherry picked from commit 565ff676887fc40b4715b44d9407c638480485e6) --- src/glsl/ir_constant_propagation.cpp |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/glsl/ir_constant_propagation.cpp b/src/glsl/ir_constant_propagation.cpp index 390f295..5d875b7 100644 --- a/src/glsl/ir_constant_propagation.cpp +++ b/src/glsl/ir_constant_propagation.cpp @@ -1,5 +1,5 @@ /* - * Constantright © 2010 Intel Corporation + * Copyright © 2010 Intel Corporation * * Permission is hereby granted, free of charge, to any person obtaining a * constant of this software and associated documentation files (the Software), ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (7.9): i965: fallback lineloop on sandybridge for now
Module: Mesa
Branch: 7.9
Commit: 1c8795075fa3f5518b728184abd09b758ca84397
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c8795075fa3f5518b728184abd09b758ca84397
Author: Zhenyu Wang zhen...@linux.intel.com
Date: Sun Sep 26 13:15:39 2010 +0800
i965: fallback lineloop on sandybridge for now
Until we fixed GS hang issue.
(cherry picked from commit 73dab75b4165f7d2214a68d4ba8e3cb7aab9b4ac)
---
src/mesa/drivers/dri/i965/brw_draw.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 16331cc..6a4dda2 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -204,6 +204,13 @@ static GLboolean check_fallbacks( struct brw_context *brw,
GLcontext *ctx = brw-intel.ctx;
GLuint i;
+ /* XXX FIXME */
+ if (brw-intel.gen = 6) {
+ for (i = 0; i nr_prims; i++)
+ if (prim[i].mode == GL_LINE_LOOP)
+ return GL_TRUE;
+ }
+
/* If we don't require strict OpenGL conformance, never
* use fallbacks. If we're forcing fallbacks, always
* use fallfacks.
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Mesa (7.9): i965: always set tiling for fbo depth buffer on sandybridge
Module: Mesa
Branch: 7.9
Commit: 4af00f1a5e12b7e0b2c4024f2480247cb16f836b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4af00f1a5e12b7e0b2c4024f2480247cb16f836b
Author: Zhenyu Wang zhen...@linux.intel.com
Date: Thu Sep 30 10:49:47 2010 +0800
i965: always set tiling for fbo depth buffer on sandybridge
Sandybridge requires depth buffer must be tiling.
Fix 'fbo_firecube' demo.
(cherry picked from commit 72b368ae69bc037681ab4e458296c07cb04349be)
---
src/mesa/drivers/dri/intel/intel_fbo.c | 10 --
1 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index 363a5c0..d3f4464 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -102,7 +102,7 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct
gl_renderbuffer *rb,
{
struct intel_context *intel = intel_context(ctx);
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
- int cpp;
+ int cpp, tiling;
ASSERT(rb-Name != 0);
@@ -176,7 +176,13 @@ intel_alloc_renderbuffer_storage(GLcontext * ctx, struct
gl_renderbuffer *rb,
/* alloc hardware renderbuffer */
DBG(Allocating %d x %d Intel RBO\n, width, height);
- irb-region = intel_region_alloc(intel-intelScreen, I915_TILING_NONE, cpp,
+ tiling = I915_TILING_NONE;
+
+ /* Gen6 requires depth must be tiling */
+ if (intel-gen = 6 rb-Format == MESA_FORMAT_S8_Z24)
+ tiling = I915_TILING_Y;
+
+ irb-region = intel_region_alloc(intel-intelScreen, tiling, cpp,
width, height, GL_TRUE);
if (!irb-region)
return GL_FALSE; /* out of memory? */
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Mesa (master): r600g: fix constant literal src splitting, also fix mplayer gl2 shader
Module: Mesa
Branch: master
Commit: 9d4ae914e28ac7857a32a88ba27aecc182f697c6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d4ae914e28ac7857a32a88ba27aecc182f697c6
Author: Jerome Glisse jgli...@redhat.com
Date: Thu Sep 30 16:26:33 2010 -0400
r600g: fix constant literal src splitting, also fix mplayer gl2 shader
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/r600_shader.c | 56 ++-
1 files changed, 40 insertions(+), 16 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 8d40079..a2091db 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -777,12 +777,12 @@ static int tgsi_split_constant(struct r600_shader_ctx
*ctx, struct r600_bc_alu_s
}
}
for (i = 0, j = nconst - 1; i inst-Instruction.NumSrcRegs; i++) {
- if (inst-Src[j].Register.File == TGSI_FILE_CONSTANT j 0) {
+ if (j 0 inst-Src[i].Register.File == TGSI_FILE_CONSTANT) {
int treg = r600_get_temp(ctx);
for (k = 0; k 4; k++) {
memset(alu, 0, sizeof(struct r600_bc_alu));
alu.inst =
CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
- alu.src[0].sel = r600_src[j].sel;
+ alu.src[0].sel = r600_src[i].sel;
alu.src[0].chan = k;
alu.dst.sel = treg;
alu.dst.chan = k;
@@ -793,7 +793,7 @@ static int tgsi_split_constant(struct r600_shader_ctx *ctx,
struct r600_bc_alu_s
if (r)
return r;
}
- r600_src[j].sel = treg;
+ r600_src[i].sel = treg;
j--;
}
}
@@ -805,20 +805,20 @@ static int tgsi_split_literal_constant(struct
r600_shader_ctx *ctx, struct r600_
{
struct tgsi_full_instruction *inst =
ctx-parse.FullToken.FullInstruction;
struct r600_bc_alu alu;
- int i, j, k, nliteral, r;
+ int i, j, k, nliteral, r, index;
for (i = 0, nliteral = 0; i inst-Instruction.NumSrcRegs; i++) {
if (inst-Src[i].Register.File == TGSI_FILE_IMMEDIATE) {
nliteral++;
}
}
- for (i = 0, j = 0; i inst-Instruction.NumSrcRegs; i++) {
- if (inst-Src[j].Register.File == TGSI_FILE_IMMEDIATE) {
+ for (i = 0, j = nliteral - 1; i inst-Instruction.NumSrcRegs; i++) {
+ if (j 0 inst-Src[i].Register.File == TGSI_FILE_IMMEDIATE)
{
int treg = r600_get_temp(ctx);
for (k = 0; k 4; k++) {
memset(alu, 0, sizeof(struct r600_bc_alu));
alu.inst =
CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV);
- alu.src[0].sel = r600_src[j].sel;
+ alu.src[0].sel = r600_src[i].sel;
alu.src[0].chan = k;
alu.dst.sel = treg;
alu.dst.chan = k;
@@ -829,11 +829,11 @@ static int tgsi_split_literal_constant(struct
r600_shader_ctx *ctx, struct r600_
if (r)
return r;
}
- r = r600_bc_add_literal(ctx-bc, ctx-value);
+ r = r600_bc_add_literal(ctx-bc,
ctx-literals[inst-Src[i].Register.Index * 4]);
if (r)
return r;
- r600_src[j].sel = treg;
- j++;
+ r600_src[i].sel = treg;
+ j--;
}
}
return 0;
@@ -856,6 +856,9 @@ static int tgsi_op2_s(struct r600_shader_ctx *ctx, int swap)
r = tgsi_split_constant(ctx, r600_src);
if (r)
return r;
+ r = tgsi_split_literal_constant(ctx, r600_src);
+ if (r)
+ return r;
for (i = 0; i lasti + 1; i++) {
if (!(inst-Dst[0].Register.WriteMask (1 i)))
continue;
@@ -926,6 +929,9 @@ static int tgsi_setup_trig(struct r600_shader_ctx *ctx,
r = tgsi_split_constant(ctx, r600_src);
if (r)
return r;
+ r = tgsi_split_literal_constant(ctx, r600_src);
+ if (r)
+ return r;
r = tgsi_split_literal_constant(ctx, r600_src);
if (r)
@@ -1465,6 +1471,9 @@ static int tgsi_ssg(struct r600_shader_ctx *ctx)
r = tgsi_split_constant(ctx, r600_src);
if (r)
return r;
+ r = tgsi_split_literal_constant(ctx, r600_src);
Mesa (7.9): i965: Update renderer strings for sandybridge
Module: Mesa Branch: 7.9 Commit: 759e9fb7376ca24b1e5c7819e3e6036e96762951 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=759e9fb7376ca24b1e5c7819e3e6036e96762951 Author: Adam Jackson a...@redhat.com Date: Thu Sep 30 14:08:35 2010 -0400 i965: Update renderer strings for sandybridge Signed-off-by: Adam Jackson a...@redhat.com (cherry picked from commit 0c86e1f29483d9557f30796c03b94a34d965c095) --- src/mesa/drivers/dri/intel/intel_context.c | 13 + 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 5ae3e4b..779e651 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -163,6 +163,19 @@ intelGetString(GLcontext * ctx, GLenum name) case PCI_CHIP_ILM_G: chipset = Intel(R) Ironlake Mobile; break; + case PCI_CHIP_SANDYBRIDGE_GT1: + case PCI_CHIP_SANDYBRIDGE_GT2: + case PCI_CHIP_SANDYBRIDGE_GT2_PLUS: +chipset = Intel(R) Sandybridge Desktop; +break; + case PCI_CHIP_SANDYBRIDGE_M_GT1: + case PCI_CHIP_SANDYBRIDGE_M_GT2: + case PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS: +chipset = Intel(R) Sandybridge Mobile; +break; + case PCI_CHIP_SANDYBRIDGE_S: +chipset = Intel(R) Sandybridge Server; +break; default: chipset = Unknown Intel Chipset; break; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): Revert Prefer intrinsics to handrolled atomic ops.
Module: Mesa Branch: master Commit: 3661f757ee7e75348f0df834ecf1febb211ddf66 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3661f757ee7e75348f0df834ecf1febb211ddf66 Author: Tom Fogal tfo...@alumni.unh.edu Date: Thu Sep 30 14:39:14 2010 -0600 Revert Prefer intrinsics to handrolled atomic ops. This reverts commit 5f66b340aa49c6bc8d0acb2d1a6f8e9a7ef2cb2e, quickly fixing 30514. --- src/gallium/auxiliary/util/u_atomic.h |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/auxiliary/util/u_atomic.h b/src/gallium/auxiliary/util/u_atomic.h index 4ae6def..8434491 100644 --- a/src/gallium/auxiliary/util/u_atomic.h +++ b/src/gallium/auxiliary/util/u_atomic.h @@ -27,12 +27,12 @@ #define PIPE_ATOMIC_MSVC_INTRINSIC #elif (defined(PIPE_CC_MSVC) defined(PIPE_ARCH_X86)) #define PIPE_ATOMIC_ASM_MSVC_X86 -#elif defined(PIPE_CC_GCC) (PIPE_CC_GCC_VERSION = 401) -#define PIPE_ATOMIC_GCC_INTRINSIC #elif (defined(PIPE_CC_GCC) defined(PIPE_ARCH_X86)) #define PIPE_ATOMIC_ASM_GCC_X86 #elif (defined(PIPE_CC_GCC) defined(PIPE_ARCH_X86_64)) #define PIPE_ATOMIC_ASM_GCC_X86_64 +#elif defined(PIPE_CC_GCC) (PIPE_CC_GCC_VERSION = 401) +#define PIPE_ATOMIC_GCC_INTRINSIC #else #error Unsupported platform #endif ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (7.8): Revert Prefer intrinsics to handrolled atomic ops.
Module: Mesa Branch: 7.8 Commit: 3af43c0b4c29f7cb82df72d0b65bcd190053f57c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3af43c0b4c29f7cb82df72d0b65bcd190053f57c Author: Tom Fogal tfo...@alumni.unh.edu Date: Thu Sep 30 14:39:14 2010 -0600 Revert Prefer intrinsics to handrolled atomic ops. This reverts commit 5f66b340aa49c6bc8d0acb2d1a6f8e9a7ef2cb2e, quickly fixing 30514. --- src/gallium/auxiliary/util/u_atomic.h |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/auxiliary/util/u_atomic.h b/src/gallium/auxiliary/util/u_atomic.h index 4ae6def..8434491 100644 --- a/src/gallium/auxiliary/util/u_atomic.h +++ b/src/gallium/auxiliary/util/u_atomic.h @@ -27,12 +27,12 @@ #define PIPE_ATOMIC_MSVC_INTRINSIC #elif (defined(PIPE_CC_MSVC) defined(PIPE_ARCH_X86)) #define PIPE_ATOMIC_ASM_MSVC_X86 -#elif defined(PIPE_CC_GCC) (PIPE_CC_GCC_VERSION = 401) -#define PIPE_ATOMIC_GCC_INTRINSIC #elif (defined(PIPE_CC_GCC) defined(PIPE_ARCH_X86)) #define PIPE_ATOMIC_ASM_GCC_X86 #elif (defined(PIPE_CC_GCC) defined(PIPE_ARCH_X86_64)) #define PIPE_ATOMIC_ASM_GCC_X86_64 +#elif defined(PIPE_CC_GCC) (PIPE_CC_GCC_VERSION = 401) +#define PIPE_ATOMIC_GCC_INTRINSIC #else #error Unsupported platform #endif ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Fix whole-structure/array assignment in new FS.
Module: Mesa
Branch: master
Commit: 6f6542a483ec726538f8a4555bddaeb0be6b2146
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f6542a483ec726538f8a4555bddaeb0be6b2146
Author: Eric Anholt e...@anholt.net
Date: Thu Sep 30 11:46:24 2010 -0700
i965: Fix whole-structure/array assignment in new FS.
We need to walk the type tree to get the right register types for
structure components. Fixes glsl-fs-statevar-call.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 76 -
1 files changed, 55 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index efbb4c6..efa0f21 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -469,6 +469,8 @@ public:
void emit_general_interpolation(ir_variable *ir);
void emit_interpolation_setup();
void emit_fb_writes();
+ void emit_assignment_writes(fs_reg l, fs_reg r,
+ const glsl_type *type, bool predicated);
struct brw_reg interp_reg(int location, int channel);
int setup_uniform_values(int loc, const glsl_type *type);
@@ -1138,11 +1140,50 @@ fs_visitor::visit(ir_expression *ir)
}
void
+fs_visitor::emit_assignment_writes(fs_reg l, fs_reg r,
+ const glsl_type *type, bool predicated)
+{
+ switch (type-base_type) {
+ case GLSL_TYPE_FLOAT:
+ case GLSL_TYPE_UINT:
+ case GLSL_TYPE_INT:
+ case GLSL_TYPE_BOOL:
+ for (unsigned int i = 0; i type-components(); i++) {
+l.type = brw_type_for_base_type(type);
+r.type = brw_type_for_base_type(type);
+
+fs_inst *inst = emit(fs_inst(BRW_OPCODE_MOV, l, r));
+inst-predicated = predicated;
+
+l.reg_offset++;
+r.reg_offset++;
+ }
+ break;
+ case GLSL_TYPE_ARRAY:
+ for (unsigned int i = 0; i type-length; i++) {
+emit_assignment_writes(l, r, type-fields.array, predicated);
+ }
+
+ case GLSL_TYPE_STRUCT:
+ for (unsigned int i = 0; i type-length; i++) {
+emit_assignment_writes(l, r, type-fields.structure[i].type,
+ predicated);
+ }
+ break;
+
+ case GLSL_TYPE_SAMPLER:
+ break;
+
+ default:
+ assert(!not reached);
+ break;
+ }
+}
+
+void
fs_visitor::visit(ir_assignment *ir)
{
struct fs_reg l, r;
- int i;
- int write_mask;
fs_inst *inst;
/* FINISHME: arrays on the lhs */
@@ -1152,18 +1193,6 @@ fs_visitor::visit(ir_assignment *ir)
ir-rhs-accept(this);
r = this-result;
- /* FINISHME: This should really set to the correct maximal writemask for
each
-* FINISHME: component written (in the loops below). This case can only
-* FINISHME: occur for matrices, arrays, and structures.
-*/
- if (ir-write_mask == 0) {
- assert(!ir-lhs-type-is_scalar() !ir-lhs-type-is_vector());
- write_mask = WRITEMASK_XYZW;
- } else {
- assert(ir-lhs-type-is_vector() || ir-lhs-type-is_scalar());
- write_mask = ir-write_mask;
- }
-
assert(l.file != BAD_FILE);
assert(r.file != BAD_FILE);
@@ -1174,14 +1203,19 @@ fs_visitor::visit(ir_assignment *ir)
inst-conditional_mod = BRW_CONDITIONAL_NZ;
}
- for (i = 0; i type_size(ir-lhs-type); i++) {
- if (i = 4 || (write_mask (1 i))) {
-inst = emit(fs_inst(BRW_OPCODE_MOV, l, r));
-if (ir-condition)
- inst-predicated = true;
-r.reg_offset++;
+ if (ir-lhs-type-is_scalar() ||
+ ir-lhs-type-is_vector()) {
+ for (int i = 0; i ir-lhs-type-vector_elements; i++) {
+if (ir-write_mask (1 i)) {
+ inst = emit(fs_inst(BRW_OPCODE_MOV, l, r));
+ if (ir-condition)
+ inst-predicated = true;
+ r.reg_offset++;
+}
+l.reg_offset++;
}
- l.reg_offset++;
+ } else {
+ emit_assignment_writes(l, r, ir-lhs-type, ir-condition != NULL);
}
}
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Mesa (master): mesa: Don' t reference a W component in setting up a vec3 uniform component.
Module: Mesa
Branch: master
Commit: a7cddd7de3123eb13e68c35aa111ff4060669f59
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7cddd7de3123eb13e68c35aa111ff4060669f59
Author: Eric Anholt e...@anholt.net
Date: Thu Sep 30 13:40:22 2010 -0700
mesa: Don't reference a W component in setting up a vec3 uniform component.
The 965 driver would try to set up storage for the W component, and
the offsets would get mixed up.
---
src/mesa/main/uniforms.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/src/mesa/main/uniforms.c b/src/mesa/main/uniforms.c
index 29a9be8..87ce6e4 100644
--- a/src/mesa/main/uniforms.c
+++ b/src/mesa/main/uniforms.c
@@ -122,7 +122,11 @@ static struct gl_builtin_uniform_element
gl_LightSource_elements[] = {
{specular, {STATE_LIGHT, 0, STATE_SPECULAR}, SWIZZLE_XYZW},
{position, {STATE_LIGHT, 0, STATE_POSITION}, SWIZZLE_XYZW},
{halfVector, {STATE_LIGHT, 0, STATE_HALF_VECTOR}, SWIZZLE_XYZW},
- {spotDirection, {STATE_LIGHT, 0, STATE_SPOT_DIRECTION}, SWIZZLE_XYZW},
+ {spotDirection, {STATE_LIGHT, 0, STATE_SPOT_DIRECTION},
+MAKE_SWIZZLE4(SWIZZLE_X,
+ SWIZZLE_Y,
+ SWIZZLE_Z,
+ SWIZZLE_Z)},
{spotCosCutoff, {STATE_LIGHT, 0, STATE_SPOT_DIRECTION}, SWIZZLE_},
{spotCutoff, {STATE_LIGHT, 0, STATE_SPOT_CUTOFF}, SWIZZLE_},
{spotExponent, {STATE_LIGHT, 0, STATE_ATTENUATION}, SWIZZLE_},
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Mesa (master): i965: Fix new FS handling of builtin uniforms with packed scalars in structs.
Module: Mesa
Branch: master
Commit: c6960e4471abe287448b9d0e7e6519d588cdf43c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c6960e4471abe287448b9d0e7e6519d588cdf43c
Author: Eric Anholt e...@anholt.net
Date: Thu Sep 30 13:26:38 2010 -0700
i965: Fix new FS handling of builtin uniforms with packed scalars in structs.
We were pointing each element at the .x channel of the
ParameterValues.
Fixes glsl1-linear fog.
---
src/mesa/drivers/dri/i965/brw_fs.cpp |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index efa0f21..0a77b5a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -696,12 +696,12 @@ fs_visitor::setup_builtin_uniform_values(ir_variable *ir)
*/
int last_swiz = -1;
for (unsigned int i = 0; i 4; i++) {
- int this_swiz = GET_SWZ(element-swizzle, i);
- if (this_swiz == last_swiz)
+ int swiz = GET_SWZ(element-swizzle, i);
+ if (swiz == last_swiz)
break;
- last_swiz = this_swiz;
+ last_swiz = swiz;
- c-prog_data.param[c-prog_data.nr_params++] = vec_values[i];
+ c-prog_data.param[c-prog_data.nr_params++] = vec_values[swiz];
}
}
}
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Mesa (master): evergreeng: avoid overlapping border color btw VS PS
Module: Mesa
Branch: master
Commit: 113f1cdfcedf858e4b426ce2dba9e99d2a1e0286
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=113f1cdfcedf858e4b426ce2dba9e99d2a1e0286
Author: Jerome Glisse jgli...@redhat.com
Date: Thu Sep 30 17:06:29 2010 -0400
evergreeng: avoid overlapping border color btw VS PS
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/winsys/r600/drm/evergreen_hw_context.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index 7ba778e..7d6bd50 100644
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -467,7 +467,7 @@ static int evergreen_state_sampler_border_init(struct
r600_context *ctx, u32 off
{PKT3_SET_CONFIG_REG, 0, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA,
0, 0},
};
unsigned nreg = sizeof(r600_shader_sampler_border)/sizeof(struct
r600_reg);
- unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX)
* 0x10 + 0x4 + id * 0x1C;
+ unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX)
* 0x100 + 0x4 + id * 0x1C;
struct r600_range *range;
struct r600_block *block;
int r;
@@ -665,7 +665,7 @@ static inline void
evergreen_context_pipe_state_set_sampler(struct r600_context
static inline void evergreen_context_pipe_state_set_sampler_border(struct
r600_context *ctx, struct r600_pipe_state *state, unsigned offset, unsigned id)
{
- unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX)
* 0x10 + 0x4 + id * 0x1C;
+ unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX)
* 0x100 + 0x4 + id * 0x1C;
struct r600_range *range;
struct r600_block *block;
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Mesa (master): r600g: don't double count dirty block
Module: Mesa
Branch: master
Commit: dde1391cc95478f4dedccdf920ba0a6607472937
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dde1391cc95478f4dedccdf920ba0a6607472937
Author: John Doe gli...@barney.(none)
Date: Thu Sep 30 17:30:25 2010 -0400
r600g: don't double count dirty block
This avoid to overcount the number of dwords we need and
thus avoid maximazation of cs buffer use.
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/winsys/r600/drm/evergreen_hw_context.c | 32 ---
src/gallium/winsys/r600/drm/r600_hw_context.c | 32 ---
src/gallium/winsys/r600/drm/r600_priv.h|4 +-
3 files changed, 42 insertions(+), 26 deletions(-)
diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index 7d6bd50..e3390fd 100644
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -625,9 +625,11 @@ static inline void
evergreen_context_pipe_state_set_resource(struct r600_context
radeon_ws_bo_reference(ctx-radeon, block-reloc[1].bo,
state-regs[2].bo);
radeon_ws_bo_reference(ctx-radeon, block-reloc[2].bo,
state-regs[3].bo);
}
- block-status |= R600_BLOCK_STATUS_ENABLED;
- block-status |= R600_BLOCK_STATUS_DIRTY;
- ctx-pm4_dirty_cdwords += block-pm4_ndwords;
+ if (!(block-status R600_BLOCK_STATUS_DIRTY)) {
+ block-status |= R600_BLOCK_STATUS_ENABLED;
+ block-status |= R600_BLOCK_STATUS_DIRTY;
+ ctx-pm4_dirty_cdwords += block-pm4_ndwords;
+ }
}
void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx,
struct r600_pipe_state *state, unsigned rid)
@@ -658,9 +660,11 @@ static inline void
evergreen_context_pipe_state_set_sampler(struct r600_context
block-reg[0] = state-regs[0].value;
block-reg[1] = state-regs[1].value;
block-reg[2] = state-regs[2].value;
- block-status |= R600_BLOCK_STATUS_ENABLED;
- block-status |= R600_BLOCK_STATUS_DIRTY;
- ctx-pm4_dirty_cdwords += block-pm4_ndwords;
+ if (!(block-status R600_BLOCK_STATUS_DIRTY)) {
+ block-status |= R600_BLOCK_STATUS_ENABLED;
+ block-status |= R600_BLOCK_STATUS_DIRTY;
+ ctx-pm4_dirty_cdwords += block-pm4_ndwords;
+ }
}
static inline void evergreen_context_pipe_state_set_sampler_border(struct
r600_context *ctx, struct r600_pipe_state *state, unsigned offset, unsigned id)
@@ -683,9 +687,11 @@ static inline void
evergreen_context_pipe_state_set_sampler_border(struct r600_c
block-reg[2] = state-regs[4].value;
block-reg[3] = state-regs[5].value;
block-reg[4] = state-regs[6].value;
- block-status |= R600_BLOCK_STATUS_ENABLED;
- block-status |= R600_BLOCK_STATUS_DIRTY;
- ctx-pm4_dirty_cdwords += block-pm4_ndwords;
+ if (!(block-status R600_BLOCK_STATUS_DIRTY)) {
+ block-status |= R600_BLOCK_STATUS_ENABLED;
+ block-status |= R600_BLOCK_STATUS_DIRTY;
+ ctx-pm4_dirty_cdwords += block-pm4_ndwords;
+ }
}
void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx,
struct r600_pipe_state *state, unsigned id)
@@ -837,9 +843,11 @@ static inline void evergreen_resource_set(struct
r600_context *ctx, struct r600_
radeon_ws_bo_reference(ctx-radeon, block-reloc[1].bo,
state-regs[2].bo);
radeon_ws_bo_reference(ctx-radeon, block-reloc[2].bo,
state-regs[3].bo);
}
- block-status |= R600_BLOCK_STATUS_ENABLED;
- block-status |= R600_BLOCK_STATUS_DIRTY;
- ctx-pm4_dirty_cdwords += block-pm4_ndwords;
+ if (!(block-status R600_BLOCK_STATUS_DIRTY)) {
+ block-status |= R600_BLOCK_STATUS_ENABLED;
+ block-status |= R600_BLOCK_STATUS_DIRTY;
+ ctx-pm4_dirty_cdwords += block-pm4_ndwords;
+ }
}
void evergreen_ps_resource_set(struct r600_context *ctx, struct
r600_pipe_state *state, unsigned rid)
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c
b/src/gallium/winsys/r600/drm/r600_hw_context.c
index f363b69..6cb0b94 100644
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -721,9 +721,11 @@ void r600_context_pipe_state_set(struct r600_context *ctx,
struct r600_pipe_stat
id = block-pm4_bo_index[id];
radeon_ws_bo_reference(ctx-radeon,
block-reloc[id].bo, state-regs[i].bo);
}
- block-status |= R600_BLOCK_STATUS_ENABLED;
- block-status |= R600_BLOCK_STATUS_DIRTY;
- ctx-pm4_dirty_cdwords += block-pm4_ndwords;
+ if (!(block-status R600_BLOCK_STATUS_DIRTY)) {
+ block-status |= R600_BLOCK_STATUS_ENABLED;
+ block-status
Mesa (master): r600g: keep a mapping around for each bo
Module: Mesa
Branch: master
Commit: 40181aef6045af9df9d8baa8910210c0c8f84f46
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=40181aef6045af9df9d8baa8910210c0c8f84f46
Author: John Doe gli...@barney.(none)
Date: Thu Sep 30 17:53:36 2010 -0400
r600g: keep a mapping around for each bo
Save a lot of call into the kernel and thus improve performances.
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/winsys/r600/drm/r600_priv.h | 14 -
src/gallium/winsys/r600/drm/radeon_bo.c | 91 +++
2 files changed, 54 insertions(+), 51 deletions(-)
diff --git a/src/gallium/winsys/r600/drm/r600_priv.h
b/src/gallium/winsys/r600/drm/r600_priv.h
index 125fb4f..f39778d 100644
--- a/src/gallium/winsys/r600/drm/r600_priv.h
+++ b/src/gallium/winsys/r600/drm/r600_priv.h
@@ -33,7 +33,6 @@
#include pipebuffer/pb_bufmgr.h
#include r600.h
-
struct radeon {
int fd;
int refcount;
@@ -83,8 +82,6 @@ struct radeon_bo *radeon_bo_pb_get_bo(struct pb_buffer *_buf);
void r600_context_bo_reloc(struct r600_context *ctx, u32 *pm4, struct
radeon_bo *bo);
struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
unsigned size, unsigned alignment, void *ptr);
-int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo);
-void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo);
void radeon_bo_reference(struct radeon *radeon, struct radeon_bo **dst,
struct radeon_bo *src);
int radeon_bo_wait(struct radeon *radeon, struct radeon_bo *bo);
@@ -145,4 +142,15 @@ static inline void r600_context_block_emit_dirty(struct
r600_context *ctx, struc
block-status ^= R600_BLOCK_STATUS_DIRTY;
}
+static inline int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo)
+{
+ bo-map_count++;
+}
+
+static inline void radeon_bo_unmap(struct radeon *radeon, struct radeon_bo *bo)
+{
+ bo-map_count--;
+ assert(bo-map_count = 0);
+}
+
#endif
diff --git a/src/gallium/winsys/r600/drm/radeon_bo.c
b/src/gallium/winsys/r600/drm/radeon_bo.c
index d16e38d..bb93ce6 100644
--- a/src/gallium/winsys/r600/drm/radeon_bo.c
+++ b/src/gallium/winsys/r600/drm/radeon_bo.c
@@ -33,6 +33,43 @@
#include xf86drm.h
#include radeon_drm.h
+static int radeon_bo_fixed_map(struct radeon *radeon, struct radeon_bo *bo)
+{
+ struct drm_radeon_gem_mmap args;
+ void *ptr;
+ int r;
+
+ /* Zero out args to make valgrind happy */
+ memset(args, 0, sizeof(args));
+ args.handle = bo-handle;
+ args.offset = 0;
+ args.size = (uint64_t)bo-size;
+ r = drmCommandWriteRead(radeon-fd, DRM_RADEON_GEM_MMAP,
+ args, sizeof(args));
+ if (r) {
+ fprintf(stderr, error mapping %p 0x%08X (error = %d)\n,
+ bo, bo-handle, r);
+ return r;
+ }
+ ptr = mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED, radeon-fd,
args.addr_ptr);
+ if (ptr == MAP_FAILED) {
+ fprintf(stderr, %s failed to map bo\n, __func__);
+ return -errno;
+ }
+ bo-data = ptr;
+
+success:
+ bo-map_count++;
+
+ return 0;
+}
+
+static void radeon_bo_fixed_unmap(struct radeon *radeon, struct radeon_bo *bo)
+{
+ munmap(bo-data, bo-size);
+ bo-data = NULL;
+}
+
struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
unsigned size, unsigned alignment, void *ptr)
{
@@ -79,65 +116,23 @@ struct radeon_bo *radeon_bo(struct radeon *radeon,
unsigned handle,
return NULL;
}
}
+ if (radeon_bo_fixed_map(radeon, bo)) {
+ R600_ERR(failed to map bo\n);
+ radeon_bo_reference(radeon, bo, NULL);
+ return bo;
+ }
if (ptr) {
- if (radeon_bo_map(radeon, bo)) {
- fprintf(stderr, %s failed to copy data into bo\n,
__func__);
- radeon_bo_reference(radeon, bo, NULL);
- return bo;
- }
memcpy(bo-data, ptr, size);
- radeon_bo_unmap(radeon, bo);
}
return bo;
}
-int radeon_bo_map(struct radeon *radeon, struct radeon_bo *bo)
-{
- struct drm_radeon_gem_mmap args;
- void *ptr;
- int r;
-
- if (bo-map_count != 0) {
- goto success;
- }
- /* Zero out args to make valgrind happy */
- memset(args, 0, sizeof(args));
- args.handle = bo-handle;
- args.offset = 0;
- args.size = (uint64_t)bo-size;
- r = drmCommandWriteRead(radeon-fd, DRM_RADEON_GEM_MMAP,
- args, sizeof(args));
- if (r) {
- fprintf(stderr, error mapping %p 0x%08X (error = %d)\n,
- bo, bo-handle, r);
- return r;
-
Mesa (master): draw: check for null sampler pointers
Module: Mesa
Branch: master
Commit: 66992463ac294b1a106090250ad2af305f9d8a10
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=66992463ac294b1a106090250ad2af305f9d8a10
Author: Brian Paul bri...@vmware.com
Date: Thu Sep 30 16:41:31 2010 -0600
draw: check for null sampler pointers
http://bugs.freedesktop.org/show_bug.cgi?id=30516
---
src/gallium/auxiliary/draw/draw_llvm.c | 10 ++
1 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/gallium/auxiliary/draw/draw_llvm.c
b/src/gallium/auxiliary/draw/draw_llvm.c
index 4749bb5..7fb86d7 100644
--- a/src/gallium/auxiliary/draw/draw_llvm.c
+++ b/src/gallium/auxiliary/draw/draw_llvm.c
@@ -1099,10 +1099,12 @@ draw_llvm_set_sampler_state(struct draw_context *draw)
for (i = 0; i draw-num_samplers; i++) {
struct draw_jit_texture *jit_tex = draw-llvm-jit_context.textures[i];
- jit_tex-min_lod = draw-samplers[i]-min_lod;
- jit_tex-max_lod = draw-samplers[i]-max_lod;
- jit_tex-lod_bias = draw-samplers[i]-lod_bias;
- COPY_4V(jit_tex-border_color, draw-samplers[i]-border_color);
+ if (draw-samplers[i]) {
+ jit_tex-min_lod = draw-samplers[i]-min_lod;
+ jit_tex-max_lod = draw-samplers[i]-max_lod;
+ jit_tex-lod_bias = draw-samplers[i]-lod_bias;
+ COPY_4V(jit_tex-border_color, draw-samplers[i]-border_color);
+ }
}
}
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Mesa (master): gallivm: added some comments
Module: Mesa
Branch: master
Commit: 542d6cb1b8a87615b4c4498ce1fcbf39d743f963
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=542d6cb1b8a87615b4c4498ce1fcbf39d743f963
Author: Brian Paul bri...@vmware.com
Date: Thu Sep 30 11:01:09 2010 -0600
gallivm: added some comments
---
src/gallium/auxiliary/gallivm/lp_bld_sample.c |5 +
src/gallium/auxiliary/gallivm/lp_bld_sample.h | 19 +++
2 files changed, 16 insertions(+), 8 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample.c
b/src/gallium/auxiliary/gallivm/lp_bld_sample.c
index 6e53bca..aee94c1 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample.c
@@ -331,6 +331,11 @@ lp_build_linear_mip_levels(struct lp_build_sample_context
*bld,
}
+/**
+ * Return pointer to a single mipmap level.
+ * \param data_array array of pointers to mipmap levels
+ * \param level integer mipmap level
+ */
LLVMValueRef
lp_build_get_mipmap_level(struct lp_build_sample_context *bld,
LLVMValueRef data_array, LLVMValueRef level)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample.h
b/src/gallium/auxiliary/gallivm/lp_bld_sample.h
index 9fc9a38..4d2eeaa 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample.h
@@ -99,61 +99,64 @@ struct lp_sampler_static_state
struct lp_sampler_dynamic_state
{
- /** Obtain the base texture width. */
+ /** Obtain the base texture width (returns int32) */
LLVMValueRef
(*width)( const struct lp_sampler_dynamic_state *state,
LLVMBuilderRef builder,
unsigned unit);
- /** Obtain the base texture height. */
+ /** Obtain the base texture height (returns int32) */
LLVMValueRef
(*height)( const struct lp_sampler_dynamic_state *state,
LLVMBuilderRef builder,
unsigned unit);
- /** Obtain the base texture depth. */
+ /** Obtain the base texture depth (returns int32) */
LLVMValueRef
(*depth)( const struct lp_sampler_dynamic_state *state,
LLVMBuilderRef builder,
unsigned unit);
- /** Obtain the number of mipmap levels (minus one). */
+ /** Obtain the number of mipmap levels minus one (returns int32) */
LLVMValueRef
(*last_level)( const struct lp_sampler_dynamic_state *state,
LLVMBuilderRef builder,
unsigned unit);
+ /** Obtain stride in bytes between image rows/blocks (returns int32) */
LLVMValueRef
(*row_stride)( const struct lp_sampler_dynamic_state *state,
LLVMBuilderRef builder,
unsigned unit);
+ /** Obtain stride in bytes between image slices (returns int32) */
LLVMValueRef
(*img_stride)( const struct lp_sampler_dynamic_state *state,
LLVMBuilderRef builder,
unsigned unit);
+ /** Obtain pointer to array of pointers to mimpap levels */
LLVMValueRef
(*data_ptr)( const struct lp_sampler_dynamic_state *state,
LLVMBuilderRef builder,
unsigned unit);
- /** Obtain texture min lod */
+ /** Obtain texture min lod (returns float) */
LLVMValueRef
(*min_lod)(const struct lp_sampler_dynamic_state *state,
LLVMBuilderRef builder, unsigned unit);
- /** Obtain texture max lod */
+ /** Obtain texture max lod (returns float) */
LLVMValueRef
(*max_lod)(const struct lp_sampler_dynamic_state *state,
LLVMBuilderRef builder, unsigned unit);
- /** Obtain texture lod bias */
+ /** Obtain texture lod bias (returns float) */
LLVMValueRef
(*lod_bias)(const struct lp_sampler_dynamic_state *state,
LLVMBuilderRef builder, unsigned unit);
- /** Obtain texture border color */
+ /** Obtain texture border color (returns ptr to float[4]) */
LLVMValueRef
(*border_color)(const struct lp_sampler_dynamic_state *state,
LLVMBuilderRef builder, unsigned unit);
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Mesa (master): r600g: fix evergreen depth flushing.
Module: Mesa
Branch: master
Commit: 084c29baedf2702200b310d6e63a5d0f95aaac37
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=084c29baedf2702200b310d6e63a5d0f95aaac37
Author: Dave Airlie airl...@redhat.com
Date: Fri Oct 1 10:13:04 2010 +1000
r600g: fix evergreen depth flushing.
although evergreen can apparantly sample direct from 24-bit,
just make it work with the current method for now.
---
src/gallium/drivers/r600/evergreen_state.c | 52 +++
src/gallium/drivers/r600/evergreend.h |8
src/gallium/drivers/r600/r600_pipe.c | 45 +++-
src/gallium/drivers/r600/r600_pipe.h |3 +-
src/gallium/drivers/r600/r600_state.c | 38
5 files changed, 98 insertions(+), 48 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 64fadb1..5775b04 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -440,14 +440,11 @@ static struct pipe_sampler_view
*evergreen_create_sampler_view(struct pipe_conte
bo[1] = rbuffer-bo;
/* FIXME depth texture decompression */
if (tmp-depth) {
-#if 0
- r = evergreen_texture_from_depth(ctx, tmp, view-first_level);
- if (r) {
- return;
- }
- bo[0] = radeon_ws_bo_incref(rscreen-rw, tmp-uncompressed);
- bo[1] = radeon_ws_bo_incref(rscreen-rw, tmp-uncompressed);
-#endif
+ r600_texture_depth_flush(ctx, texture);
+ tmp = (struct r600_resource_texture*)texture;
+ rbuffer = tmp-flushed_depth_texture-resource;
+ bo[0] = rbuffer-bo;
+ bo[1] = rbuffer-bo;
}
pitch = align(tmp-pitch[0] / tmp-bpt, 8);
@@ -852,6 +849,7 @@ static void evergreen_set_framebuffer_state(struct
pipe_context *ctx,
}
pipe_surface_reference(rctx-framebuffer.zsbuf, state-zsbuf);
rctx-framebuffer = *state;
+ rctx-pframebuffer = rctx-framebuffer;
/* build states */
for (int i = 0; i state-nr_cbufs; i++) {
@@ -1645,3 +1643,41 @@ void evergreen_pipe_shader_vs(struct pipe_context *ctx,
struct r600_pipe_shader
R_0288A4_SQ_PGM_START_FS,
0x, 0x, shader-bo);
}
+
+void *evergreen_create_db_flush_dsa(struct r600_pipe_context *rctx)
+{
+ struct pipe_depth_stencil_alpha_state dsa;
+ struct r600_pipe_state *rstate;
+ boolean quirk = false;
+
+ if (rctx-family == CHIP_RV610 || rctx-family == CHIP_RV630 ||
+ rctx-family == CHIP_RV620 || rctx-family == CHIP_RV635)
+ quirk = true;
+
+ memset(dsa, 0, sizeof(dsa));
+
+ if (quirk) {
+ dsa.depth.enabled = 1;
+ dsa.depth.func = PIPE_FUNC_LEQUAL;
+ dsa.stencil[0].enabled = 1;
+ dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
+ dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
+ dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
+ dsa.stencil[0].writemask = 0xff;
+ }
+
+ rstate = rctx-context.create_depth_stencil_alpha_state(rctx-context,
dsa);
+ r600_pipe_state_add_reg(rstate,
+ R_02880C_DB_SHADER_CONTROL,
+ 0x0,
+ S_02880C_DUAL_EXPORT_ENABLE(1), NULL);
+ r600_pipe_state_add_reg(rstate,
+ R_028000_DB_RENDER_CONTROL,
+ S_028000_DEPTH_COPY_ENABLE(1) |
+ S_028000_STENCIL_COPY_ENABLE(1) |
+ S_028000_COPY_CENTROID(1),
+ S_028000_DEPTH_COPY_ENABLE(1) |
+ S_028000_STENCIL_COPY_ENABLE(1) |
+ S_028000_COPY_CENTROID(1), NULL);
+ return rstate;
+}
diff --git a/src/gallium/drivers/r600/evergreend.h
b/src/gallium/drivers/r600/evergreend.h
index 486cb29..54b26f6 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -1424,8 +1424,16 @@
#define R_008C0C_SQ_THREAD_RESOURCE_MGMT 0x8C0C
#define R_008D8C_SQ_DYN_GPR_CNTL_PS_FLUSH_REQ0x8D8C
#define R_028000_DB_RENDER_CONTROL 0x00028000
+#define S_028000_DEPTH_CLEAR_ENABLE(x) (((x) 0x1) 0)
+#define S_028000_STENCIL_CLEAR_ENABLE(x) (((x) 0x1) 1)
+#define S_028000_DEPTH_COPY_ENABLE(x)(((x) 0x1) 2)
+#define S_028000_STENCIL_COPY_ENABLE(x) (((x) 0x1) 3)
+#define S_028000_RESUMMARIZE_ENABLE(x) (((x) 0x1) 4)
#define S_028000_STENCIL_COMPRESS_DISABLE(x) (((x) 0x1) 5)
#define S_028000_DEPTH_COMPRESS_DISABLE(x) (((x) 0x1) 6)
+#define S_028000_COPY_CENTROID(x)
Mesa (master): r600g: use Elements macro instead of manual sizeofs
Module: Mesa
Branch: master
Commit: 7ae4da8056c5aa6b65dc06fb8a0d0785123938db
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ae4da8056c5aa6b65dc06fb8a0d0785123938db
Author: Dave Airlie airl...@redhat.com
Date: Fri Oct 1 09:39:35 2010 +1000
r600g: use Elements macro instead of manual sizeofs
---
src/gallium/winsys/r600/drm/evergreen_hw_context.c | 11 ++-
src/gallium/winsys/r600/drm/r600_hw_context.c | 11 ++-
2 files changed, 12 insertions(+), 10 deletions(-)
diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index e3390fd..a92c32e 100644
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -35,6 +35,7 @@
#include bof.h
#include pipe/p_compiler.h
#include util/u_inlines.h
+#include util/u_memory.h
#include pipebuffer/pb_bufmgr.h
#include r600_priv.h
@@ -432,7 +433,7 @@ static int evergreen_state_resource_init(struct
r600_context *ctx, u32 offset)
{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET,
R_030018_RESOURCE0_WORD6, 0, 0},
{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET,
R_03001C_RESOURCE0_WORD7, 0, 0},
};
- unsigned nreg = sizeof(r600_shader_resource)/sizeof(struct r600_reg);
+ unsigned nreg = Elements(r600_shader_resource);
for (int i = 0; i nreg; i++) {
r600_shader_resource[i].offset += offset;
@@ -448,7 +449,7 @@ static int r600_state_sampler_init(struct r600_context
*ctx, u32 offset)
{PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET,
R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0},
{PKT3_SET_SAMPLER, EVERGREEN_SAMPLER_OFFSET,
R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0},
};
- unsigned nreg = sizeof(r600_shader_sampler)/sizeof(struct r600_reg);
+ unsigned nreg = Elements(r600_shader_sampler);
for (int i = 0; i nreg; i++) {
r600_shader_sampler[i].offset += offset;
@@ -466,7 +467,7 @@ static int evergreen_state_sampler_border_init(struct
r600_context *ctx, u32 off
{PKT3_SET_CONFIG_REG, 0, R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE,
0, 0},
{PKT3_SET_CONFIG_REG, 0, R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA,
0, 0},
};
- unsigned nreg = sizeof(r600_shader_sampler_border)/sizeof(struct
r600_reg);
+ unsigned nreg = Elements(r600_shader_sampler_border);
unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX)
* 0x100 + 0x4 + id * 0x1C;
struct r600_range *range;
struct r600_block *block;
@@ -510,11 +511,11 @@ int evergreen_context_init(struct r600_context *ctx,
struct radeon *radeon)
/* add blocks */
r = r600_context_add_block(ctx, evergreen_config_reg_list,
-
sizeof(evergreen_config_reg_list)/sizeof(struct r600_reg));
+ Elements(evergreen_config_reg_list));
if (r)
goto out_err;
r = r600_context_add_block(ctx, evergreen_context_reg_list,
-
sizeof(evergreen_context_reg_list)/sizeof(struct r600_reg));
+ Elements(evergreen_context_reg_list));
if (r)
goto out_err;
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c
b/src/gallium/winsys/r600/drm/r600_hw_context.c
index 6cb0b94..53783e8 100644
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -35,6 +35,7 @@
#include bof.h
#include pipe/p_compiler.h
#include util/u_inlines.h
+#include util/u_memory.h
#include pipebuffer/pb_bufmgr.h
#include r600_priv.h
@@ -495,7 +496,7 @@ static int r600_state_resource_init(struct r600_context
*ctx, u32 offset)
{PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET,
R_038014_RESOURCE0_WORD5, 0, 0},
{PKT3_SET_RESOURCE, R600_RESOURCE_OFFSET,
R_038018_RESOURCE0_WORD6, 0, 0},
};
- unsigned nreg = sizeof(r600_shader_resource)/sizeof(struct r600_reg);
+ unsigned nreg = Elements(r600_shader_resource);
for (int i = 0; i nreg; i++) {
r600_shader_resource[i].offset += offset;
@@ -511,7 +512,7 @@ static int r600_state_sampler_init(struct r600_context
*ctx, u32 offset)
{PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET,
R_03C004_SQ_TEX_SAMPLER_WORD1_0, 0, 0},
{PKT3_SET_SAMPLER, R600_SAMPLER_OFFSET,
R_03C008_SQ_TEX_SAMPLER_WORD2_0, 0, 0},
};
- unsigned nreg = sizeof(r600_shader_sampler)/sizeof(struct r600_reg);
+ unsigned nreg = Elements(r600_shader_sampler);
for (int i = 0; i nreg; i++) {
r600_shader_sampler[i].offset += offset;
@@ -528,7 +529,7 @@ static int r600_state_sampler_border_init(struct
r600_context *ctx, u32 offset)
{PKT3_SET_CONFIG_REG, R600_CONFIG_REG_OFFSET,
R_00A408_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0},
Mesa (master): r600g: drop depth quirk on evergreen
Module: Mesa
Branch: master
Commit: 40ccb235d693ea6184ab61529f2910086e68edda
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=40ccb235d693ea6184ab61529f2910086e68edda
Author: Dave Airlie airl...@redhat.com
Date: Fri Oct 1 10:19:39 2010 +1000
r600g: drop depth quirk on evergreen
none of the EG cards need the quirk.
---
src/gallium/drivers/r600/evergreen_state.c | 15 ---
1 files changed, 0 insertions(+), 15 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 21d3394..7337839 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1650,24 +1650,9 @@ void *evergreen_create_db_flush_dsa(struct
r600_pipe_context *rctx)
{
struct pipe_depth_stencil_alpha_state dsa;
struct r600_pipe_state *rstate;
- boolean quirk = false;
-
- if (rctx-family == CHIP_RV610 || rctx-family == CHIP_RV630 ||
- rctx-family == CHIP_RV620 || rctx-family == CHIP_RV635)
- quirk = true;
memset(dsa, 0, sizeof(dsa));
- if (quirk) {
- dsa.depth.enabled = 1;
- dsa.depth.func = PIPE_FUNC_LEQUAL;
- dsa.stencil[0].enabled = 1;
- dsa.stencil[0].func = PIPE_FUNC_ALWAYS;
- dsa.stencil[0].zpass_op = PIPE_STENCIL_OP_KEEP;
- dsa.stencil[0].zfail_op = PIPE_STENCIL_OP_INCR;
- dsa.stencil[0].writemask = 0xff;
- }
-
rstate = rctx-context.create_depth_stencil_alpha_state(rctx-context,
dsa);
r600_pipe_state_add_reg(rstate,
R_02880C_DB_SHADER_CONTROL,
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Mesa (master): r600g: add winsys support for CTL constants.
Module: Mesa
Branch: master
Commit: 05d1d86907b12011fdb80e147ae68b4cd207f789
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=05d1d86907b12011fdb80e147ae68b4cd207f789
Author: Dave Airlie airl...@redhat.com
Date: Fri Oct 1 09:43:14 2010 +1000
r600g: add winsys support for CTL constants.
These need to be emitted, we also need them to do proper vtx start,
instead of abusing index offset.
---
src/gallium/drivers/r600/evergreen_state.c |2 ++
src/gallium/drivers/r600/evergreend.h |6 ++
src/gallium/drivers/r600/r600_state.c |2 ++
src/gallium/drivers/r600/r600d.h |3 +++
src/gallium/winsys/r600/drm/evergreen_hw_context.c | 10 ++
src/gallium/winsys/r600/drm/r600_hw_context.c |9 +
src/gallium/winsys/r600/drm/r600d.h|3 +++
7 files changed, 35 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 5775b04..21d3394 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1450,6 +1450,8 @@ void evergreen_draw(struct pipe_context *ctx, const
struct pipe_draw_info *info)
r600_pipe_state_add_reg(vgt, R_028238_CB_TARGET_MASK,
rctx-cb_target_mask mask, 0x, NULL);
r600_pipe_state_add_reg(vgt, R_028400_VGT_MAX_VTX_INDX,
draw.max_index, 0x, NULL);
r600_pipe_state_add_reg(vgt, R_028404_VGT_MIN_VTX_INDX,
draw.min_index, 0x, NULL);
+ r600_pipe_state_add_reg(vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0,
0x, NULL);
+ r600_pipe_state_add_reg(vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0,
0x, NULL);
if (rctx-rasterizer rctx-framebuffer.zsbuf) {
float offset_units = rctx-rasterizer-offset_units;
diff --git a/src/gallium/drivers/r600/evergreend.h
b/src/gallium/drivers/r600/evergreend.h
index 54b26f6..ce2b667 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -40,6 +40,9 @@
#define EVERGREEN_SAMPLER_OFFSET0X0003C000
#define EVERGREEN_SAMPLER_END 0X0003CFF0
+#define EVERGREEN_CTL_CONST_OFFSET 0x0003CFF0
+#define EVERGREEN_CTL_CONST_END 0x0003E200
+
#define EVENT_TYPE_ZPASS_DONE 0x15
#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16
@@ -1890,4 +1893,7 @@
#define R_008970_VGT_NUM_INDICES 0x008970
#define R_0287F0_VGT_DRAW_INITIATOR 0x0287F0
+#define R_03CFF0_SQ_VTX_BASE_VTX_LOC0x03CFF0
+#define R_03CFF4_SQ_VTX_START_INST_LOC 0x03CFF4
+
#endif
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 83eedd2..c86bad7 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -126,6 +126,8 @@ static void r600_draw_common(struct r600_drawl *draw)
r600_pipe_state_add_reg(vgt, R_028400_VGT_MAX_VTX_INDX,
draw-max_index, 0x, NULL);
r600_pipe_state_add_reg(vgt, R_028404_VGT_MIN_VTX_INDX,
draw-min_index, 0x, NULL);
r600_pipe_state_add_reg(vgt, R_028238_CB_TARGET_MASK,
rctx-cb_target_mask mask, 0x, NULL);
+ r600_pipe_state_add_reg(vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0,
0x, NULL);
+ r600_pipe_state_add_reg(vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0,
0x, NULL);
/* build late state */
if (rctx-rasterizer rctx-framebuffer.zsbuf) {
float offset_units = rctx-rasterizer-offset_units;
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 169cda5..02e3734 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -3489,6 +3489,9 @@
#define R_028940_ALU_CONST_CACHE_PS_00x00028940
#define R_028980_ALU_CONST_CACHE_VS_00x00028980
+#define R_03CFF0_SQ_VTX_BASE_VTX_LOC 0x03CFF0
+#define R_03CFF4_SQ_VTX_START_INST_LOC 0x03CFF4
+
#define SQ_TEX_INST_LD 0x03
#define SQ_TEX_INST_GET_GRADIENTS_H 0x7
#define SQ_TEX_INST_GET_GRADIENTS_V 0x8
diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index a92c32e..225027b 100644
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -61,6 +61,11 @@ static const struct r600_reg evergreen_config_reg_list[] = {
{PKT3_SET_CONFIG_REG, EVERGREEN_CONFIG_REG_OFFSET,
R_00913C_SPI_CONFIG_CNTL_1, 0, 0},
};
+static const struct r600_reg evergreen_ctl_const_list[] = {
+ {PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET,
R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0, 0},
+ {PKT3_SET_CTL_CONST, EVERGREEN_CTL_CONST_OFFSET,
R_03CFF4_SQ_VTX_START_INST_LOC, 0, 0},
+};
+
static const struct r600_reg
Mesa (master): r600g: add reloc for evergreen color attrib
Module: Mesa
Branch: master
Commit: 5eccdc62b998a6b3a82d9fd204db733d4852fc73
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5eccdc62b998a6b3a82d9fd204db733d4852fc73
Author: Dave Airlie airl...@redhat.com
Date: Fri Oct 1 10:52:09 2010 +1000
r600g: add reloc for evergreen color attrib
we'll need this for color tiling on evergreen.
---
src/gallium/drivers/r600/evergreen_state.c |2 +-
src/gallium/winsys/r600/drm/evergreen_hw_context.c | 24 ++--
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 7337839..55eede9 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -786,7 +786,7 @@ static void evergreen_cb(struct r600_pipe_context *rctx,
struct r600_pipe_state
r600_pipe_state_add_reg(rstate,
R_028C74_CB_COLOR0_ATTRIB + cb * 0x3C,
S_028C74_NON_DISP_TILING_ORDER(1),
- 0x, NULL);
+ 0x, bo[0]);
}
static void evergreen_db(struct r600_pipe_context *rctx, struct
r600_pipe_state *rstate,
diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index 225027b..3af299c 100644
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -333,7 +333,7 @@ static const struct r600_reg evergreen_context_reg_list[] =
{
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028C68_CB_COLOR0_SLICE, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028C6C_CB_COLOR0_VIEW, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028C70_CB_COLOR0_INFO, 1, 0},
- {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028C74_CB_COLOR0_ATTRIB, 0, 0},
+ {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028C74_CB_COLOR0_ATTRIB, 1, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028C78_CB_COLOR0_DIM, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
GROUP_FORCE_NEW_BLOCK, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028C9C_CB_COLOR1_BASE, 1, 0},
@@ -341,7 +341,7 @@ static const struct r600_reg evergreen_context_reg_list[] =
{
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028CA4_CB_COLOR1_SLICE, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028CA8_CB_COLOR1_VIEW, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028CAC_CB_COLOR1_INFO, 1, 0},
- {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028CB0_CB_COLOR1_ATTRIB, 0, 0},
+ {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028CB0_CB_COLOR1_ATTRIB, 1, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028CB8_CB_COLOR1_DIM, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
GROUP_FORCE_NEW_BLOCK, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028CD8_CB_COLOR2_BASE, 1, 0},
@@ -349,7 +349,7 @@ static const struct r600_reg evergreen_context_reg_list[] =
{
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028CE0_CB_COLOR2_SLICE, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028CE4_CB_COLOR2_VIEW, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028CE8_CB_COLOR2_INFO, 1, 0},
- {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028CEC_CB_COLOR2_ATTRIB, 0, 0},
+ {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028CEC_CB_COLOR2_ATTRIB, 1, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028CF0_CB_COLOR2_DIM, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
GROUP_FORCE_NEW_BLOCK, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028D14_CB_COLOR3_BASE, 1, 0},
@@ -357,7 +357,7 @@ static const struct r600_reg evergreen_context_reg_list[] =
{
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028D1C_CB_COLOR3_SLICE, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028D20_CB_COLOR3_VIEW, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028D24_CB_COLOR3_INFO, 1, 0},
- {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028D28_CB_COLOR3_ATTRIB, 0, 0},
+ {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028D28_CB_COLOR3_ATTRIB, 1, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028D2C_CB_COLOR3_DIM, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
GROUP_FORCE_NEW_BLOCK, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028D50_CB_COLOR4_BASE, 1, 0},
@@ -365,7 +365,7 @@ static const struct r600_reg evergreen_context_reg_list[] =
{
{PKT3_SET_CONTEXT_REG,
Mesa (master): r600c: add reloc for CB_COLOR0_ATTRIB
Module: Mesa Branch: master Commit: a3e9998614da6bd10d9015134bc19f5b8cf6e518 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a3e9998614da6bd10d9015134bc19f5b8cf6e518 Author: Alex Deucher alexdeuc...@gmail.com Date: Thu Sep 30 20:54:26 2010 -0400 r600c: add reloc for CB_COLOR0_ATTRIB We'll need a reloc for tiling eventually, so add it now. --- src/mesa/drivers/dri/r600/evergreen_chip.c | 14 +++--- 1 files changed, 11 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/r600/evergreen_chip.c b/src/mesa/drivers/dri/r600/evergreen_chip.c index 1050c77..5287a98 100644 --- a/src/mesa/drivers/dri/r600/evergreen_chip.c +++ b/src/mesa/drivers/dri/r600/evergreen_chip.c @@ -1415,9 +1415,17 @@ static void evergreenSendCB(GLcontext *ctx, struct radeon_state_atom *atom) R600_OUT_BATCH(evergreen-render_target[id].CB_COLOR0_VIEW.u32All); END_BATCH(); -BEGIN_BATCH_NO_AUTOSTATE(4); -EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_ATTRIB, 2); +BEGIN_BATCH_NO_AUTOSTATE(3 + 2); +EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_ATTRIB, 1); R600_OUT_BATCH(evergreen-render_target[id].CB_COLOR0_ATTRIB.u32All); +R600_OUT_BATCH_RELOC(0, +rrb-bo, +0, +0, RADEON_GEM_DOMAIN_VRAM, 0); +END_BATCH(); + +BEGIN_BATCH_NO_AUTOSTATE(3); +EVERGREEN_OUT_BATCH_REGSEQ(EG_CB_COLOR0_DIM, 1); R600_OUT_BATCH(evergreen-render_target[id].CB_COLOR0_DIM.u32All); /* R600_OUT_BATCH(evergreen-render_target[id].CB_COLOR0_CMASK.u32All); @@ -1523,7 +1531,7 @@ void evergreenInitAtoms(context_t *context) EVERGREEN_ALLOC_STATE(sx,always,9, evergreenSendSX); EVERGREEN_ALLOC_STATE(tx,evergreen_tx, (R700_TEXTURE_NUMBERUNITS * (21+5) + 6), evergreenSendTexState); /* 21 for resource, 5 for sampler */ EVERGREEN_ALLOC_STATE(db,always,65, evergreenSendDB); -EVERGREEN_ALLOC_STATE(cb,always,33, evergreenSendCB); +EVERGREEN_ALLOC_STATE(cb,always,37, evergreenSendCB); EVERGREEN_ALLOC_STATE(vgt, always,29, evergreenSendVGT); evergreen_init_query_stateobj(context-radeon, 6 * 2); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: realign evergreen code with r600 code.
Module: Mesa
Branch: master
Commit: 35cfe286d69206d3108c7a8702bd4be6521b5706
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=35cfe286d69206d3108c7a8702bd4be6521b5706
Author: Dave Airlie airl...@redhat.com
Date: Fri Oct 1 11:13:02 2010 +1000
r600g: realign evergreen code with r600 code.
fixes segfault in depth-tex-modes-glsl and OA startup.
---
src/gallium/drivers/r600/evergreen_state.c |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 55eede9..06dc840 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1341,14 +1341,13 @@ void evergreen_draw(struct pipe_context *ctx, const
struct pipe_draw_info *info)
struct r600_pipe_state vgt;
struct r600_drawl draw;
- assert(info-index_bias == 0);
-
if (rctx-any_user_vbs) {
r600_upload_user_buffers(rctx);
rctx-any_user_vbs = FALSE;
}
memset(draw, 0, sizeof(struct r600_drawl));
+ draw.ctx = ctx;
draw.mode = info-mode;
draw.start = info-start;
draw.count = info-count;
@@ -1364,7 +1363,7 @@ void evergreen_draw(struct pipe_context *ctx, const
struct pipe_draw_info *info)
info-count);
draw.index_size = rctx-index_buffer.index_size;
- draw.index_buffer = rctx-index_buffer.buffer;
+ pipe_resource_reference(draw.index_buffer,
rctx-index_buffer.buffer);
draw.index_buffer_offset = draw.start * draw.index_size;
draw.start = 0;
r600_upload_index_buffer(rctx, draw);
@@ -1505,6 +1504,8 @@ void evergreen_draw(struct pipe_context *ctx, const
struct pipe_draw_info *info)
rdraw.indices_bo_offset = draw.index_buffer_offset;
}
evergreen_context_draw(rctx-ctx, rdraw);
+
+ pipe_resource_reference(draw.index_buffer, NULL);
}
void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct
r600_pipe_shader *shader)
___
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Mesa (master): glsl: Add a lowering pass for texture projection.
Module: Mesa
Branch: master
Commit: aae338104fa6022b8b1d6b22c7ad1115b252b9b6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aae338104fa6022b8b1d6b22c7ad1115b252b9b6
Author: Eric Anholt e...@anholt.net
Date: Thu Sep 30 20:07:27 2010 -0700
glsl: Add a lowering pass for texture projection.
---
src/glsl/Makefile |1 +
src/glsl/ir_optimization.h|1 +
src/glsl/lower_texture_projection.cpp | 100 +
3 files changed, 102 insertions(+), 0 deletions(-)
diff --git a/src/glsl/Makefile b/src/glsl/Makefile
index 47ac426..83869b1 100644
--- a/src/glsl/Makefile
+++ b/src/glsl/Makefile
@@ -76,6 +76,7 @@ CXX_SOURCES = \
loop_controls.cpp \
loop_unroll.cpp \
lower_noise.cpp \
+ lower_texture_projection.cpp \
lower_variable_index_to_cond_assign.cpp \
opt_redundant_jumps.cpp \
s_expression.cpp
diff --git a/src/glsl/ir_optimization.h b/src/glsl/ir_optimization.h
index 6a37e16..ffdc66b 100644
--- a/src/glsl/ir_optimization.h
+++ b/src/glsl/ir_optimization.h
@@ -44,6 +44,7 @@ bool do_div_to_mul_rcp(exec_list *instructions);
bool do_explog_to_explog2(exec_list *instructions);
bool do_function_inlining(exec_list *instructions);
bool do_lower_jumps(exec_list *instructions, bool pull_out_jumps = true, bool
lower_sub_return = true, bool lower_main_return = false, bool lower_continue =
false, bool lower_break = false);
+bool do_lower_texture_projection(exec_list *instructions);
bool do_if_simplification(exec_list *instructions);
bool do_if_to_cond_assign(exec_list *instructions);
bool do_mat_op_to_vec(exec_list *instructions);
diff --git a/src/glsl/lower_texture_projection.cpp
b/src/glsl/lower_texture_projection.cpp
new file mode 100644
index 000..f82ca0a
--- /dev/null
+++ b/src/glsl/lower_texture_projection.cpp
@@ -0,0 +1,100 @@
+/*
+ * Copyright © 2010 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+/**
+ * \file lower_texture_projection.cpp
+ *
+ * IR lower pass to perform the division of texture coordinates by the texture
+ * projector if present.
+ *
+ * Many GPUs have a texture sampling opcode that takes the projector
+ * and does the divide internally, thus the presence of the projector
+ * in the IR. For GPUs that don't, this saves the driver needing the
+ * logic for handling the divide.
+ *
+ * \author Eric Anholt e...@anholt.net
+ */
+
+#include ir.h
+#include ir_rvalue_visitor.h
+
+class lower_texture_projection_visitor : public ir_hierarchical_visitor {
+public:
+ lower_texture_projection_visitor()
+ {
+ progress = false;
+ }
+
+ ir_visitor_status visit_leave(ir_texture *ir);
+
+ bool progress;
+};
+
+ir_visitor_status
+lower_texture_projection_visitor::visit_leave(ir_texture *ir)
+{
+ if (!ir-projector)
+ return visit_continue;
+
+ void *mem_ctx = talloc_parent(ir);
+
+ ir_variable *var = new(mem_ctx) ir_variable(ir-projector-type,
+ projector, ir_var_auto);
+ base_ir-insert_before(var);
+ ir_dereference *deref = new(mem_ctx) ir_dereference_variable(var);
+ ir_expression *expr = new(mem_ctx) ir_expression(ir_unop_rcp,
+ ir-projector-type,
+ ir-projector,
+ NULL);
+ ir_assignment *assign = new(mem_ctx) ir_assignment(deref, expr, NULL);
+ base_ir-insert_before(assign);
+
+ deref = new(mem_ctx) ir_dereference_variable(var);
+ ir-coordinate = new(mem_ctx) ir_expression(ir_binop_mul,
+ ir-coordinate-type,
+ ir-coordinate,
+ deref);
+
+ if (ir-shadow_comparitor) {
+ deref = new(mem_ctx) ir_dereference_variable(var);
+
Mesa (master): i965: Use the lowering pass for texture projection.
Module: Mesa
Branch: master
Commit: 5f237a1ccb28399fbbceecea694f5d18ebba9938
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f237a1ccb28399fbbceecea694f5d18ebba9938
Author: Eric Anholt e...@anholt.net
Date: Thu Sep 30 20:09:53 2010 -0700
i965: Use the lowering pass for texture projection.
We should end up with the same code, but anyone else with this issue
could share the handling (which I got wrong for shadow comparisons in
the driver before).
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 19 +++
1 files changed, 3 insertions(+), 16 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 0a77b5a..c49b27b 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -138,6 +138,7 @@ brw_link_shader(GLcontext *ctx, struct gl_shader_program
*prog)
do_div_to_mul_rcp(shader-ir);
do_sub_to_add_neg(shader-ir);
do_explog_to_explog2(shader-ir);
+do_lower_texture_projection(shader-ir);
do {
progress = false;
@@ -1229,22 +1230,8 @@ fs_visitor::visit(ir_texture *ir)
ir-coordinate-accept(this);
fs_reg coordinate = this-result;
- if (ir-projector) {
- fs_reg inv_proj = fs_reg(this, glsl_type::float_type);
-
- ir-projector-accept(this);
- emit(fs_inst(FS_OPCODE_RCP, inv_proj, this-result));
-
- fs_reg proj_coordinate = fs_reg(this, ir-coordinate-type);
- for (unsigned int i = 0; i ir-coordinate-type-vector_elements; i++)
{
-emit(fs_inst(BRW_OPCODE_MUL, proj_coordinate, coordinate, inv_proj));
-coordinate.reg_offset++;
-proj_coordinate.reg_offset++;
- }
- proj_coordinate.reg_offset = 0;
-
- coordinate = proj_coordinate;
- }
+ /* Should be lowered by do_lower_texture_projection */
+ assert(!ir-projector);
for (mlen = 0; mlen ir-coordinate-type-vector_elements; mlen++) {
emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), coordinate));
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Mesa (master): i965: Split the gen4 and gen5 sampler handling apart.
Module: Mesa
Branch: master
Commit: 1d073cb2d920d1c0b8c6d598055b14048fedc96e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d073cb2d920d1c0b8c6d598055b14048fedc96e
Author: Eric Anholt e...@anholt.net
Date: Thu Sep 30 19:18:25 2010 -0700
i965: Split the gen4 and gen5 sampler handling apart.
Trying to track the insanity of the different argument layouts for
normal/shadow crossed with normal/lod/bias one generation at a time is
enough.
Fixes: glsl1-texture2D() with bias.
(first test passing in this code that doesn't pass without it!)
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 126 +++--
1 files changed, 103 insertions(+), 23 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index c49b27b..78cdfed 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -469,6 +469,8 @@ public:
void emit_fragcoord_interpolation(ir_variable *ir);
void emit_general_interpolation(ir_variable *ir);
void emit_interpolation_setup();
+ fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, int base_mrf);
+ fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, int base_mrf);
void emit_fb_writes();
void emit_assignment_writes(fs_reg l, fs_reg r,
const glsl_type *type, bool predicated);
@@ -1220,48 +1222,93 @@ fs_visitor::visit(ir_assignment *ir)
}
}
-void
-fs_visitor::visit(ir_texture *ir)
+fs_inst *
+fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, int base_mrf)
{
- int base_mrf = 2;
- fs_inst *inst = NULL;
- unsigned int mlen = 0;
+ /* gen4's SIMD8 sampler always has the slots for u,v,r present. */
+ int mlen = 3;
- ir-coordinate-accept(this);
- fs_reg coordinate = this-result;
+ if (ir-shadow_comparitor) {
+ if (ir-op == ir_tex) {
+/* There's no plain shadow compare message, so we use shadow
+ * compare with a bias of 0.0.
+ */
+emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
+ fs_reg(0.0f)));
+mlen++;
+ } else if (ir-op == ir_txb) {
+ir-lod_info.bias-accept(this);
+emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
+ this-result));
+mlen++;
+ } else {
+assert(ir-op == ir_txl);
+ir-lod_info.lod-accept(this);
+emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
+ this-result));
+mlen++;
+ }
- /* Should be lowered by do_lower_texture_projection */
- assert(!ir-projector);
+ ir-shadow_comparitor-accept(this);
+ emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
this-result));
+ mlen++;
+ } else {
+ /* Oh joy. gen4 doesn't have SIMD8 non-shadow-compare sampler
+ * instructions. We'll need to do SIMD16 here.
+ */
+ abort();
+ }
- for (mlen = 0; mlen ir-coordinate-type-vector_elements; mlen++) {
- emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen), coordinate));
- coordinate.reg_offset++;
+ fs_inst *inst = NULL;
+ switch (ir-op) {
+ case ir_tex:
+ inst = emit(fs_inst(FS_OPCODE_TEX, dst, fs_reg(MRF, base_mrf)));
+ break;
+ case ir_txb:
+ inst = emit(fs_inst(FS_OPCODE_TXB, dst, fs_reg(MRF, base_mrf)));
+ break;
+ case ir_txl:
+ inst = emit(fs_inst(FS_OPCODE_TXL, dst, fs_reg(MRF, base_mrf)));
+ break;
+ case ir_txd:
+ case ir_txf:
+ assert(!GLSL 1.30 features unsupported);
+ break;
}
+ inst-mlen = mlen;
- /* Pre-Ironlake, the 8-wide sampler always took u,v,r. */
- if (intel-gen 5)
- mlen = 3;
+ return inst;
+}
+
+fs_inst *
+fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, int base_mrf)
+{
+ /* gen5's SIMD8 sampler has slots for u, v, r, array index, then
+* optional parameters like shadow comparitor or LOD bias. If
+* optional parameters aren't present, those base slots are
+* optional and don't need to be included in the message.
+*
+* We don't fill in the unnecessary slots regardless, which may
+* look surprising in the disassembly.
+*/
+ int mlen = ir-coordinate-type-vector_elements;
if (ir-shadow_comparitor) {
- /* For shadow comparisons, we have to supply u,v,r. */
- mlen = 3;
+ mlen = MAX2(mlen, 4);
ir-shadow_comparitor-accept(this);
emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf + mlen),
this-result));
mlen++;
}
- /* Do we ever want to handle writemasking on texture samples? Is it
-* performance relevant?
-*/
- fs_reg dst = fs_reg(this, glsl_type::vec4_type);
-
+ fs_inst *inst = NULL;
switch (ir-op) {
case ir_tex:
inst = emit(fs_inst(FS_OPCODE_TEX, dst, fs_reg(MRF, base_mrf)));
break;
case ir_txb:
ir-lod_info.bias-accept(this);
+ mlen = MAX2(mlen, 4);
emit(fs_inst(BRW_OPCODE_MOV, fs_reg(MRF, base_mrf +
Mesa (master): r600g: add assembler support for other vtx fetch fields.
Module: Mesa
Branch: master
Commit: e973221538d5edfad62abedf5b37a4fb774d71fc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e973221538d5edfad62abedf5b37a4fb774d71fc
Author: Dave Airlie airl...@redhat.com
Date: Fri Oct 1 11:38:40 2010 +1000
r600g: add assembler support for other vtx fetch fields.
this shouldn't change behaviour, just push the choice of what
to do out to the shader.
---
src/gallium/drivers/r600/r600_asm.c|6 +-
src/gallium/drivers/r600/r600_asm.h|5 +
src/gallium/drivers/r600/r600_shader.c |1 +
3 files changed, 11 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index dc8dc9f..f07af81 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -601,7 +601,11 @@ static int r600_bc_vtx_build(struct r600_bc *bc, struct
r600_bc_vtx *vtx, unsign
S_SQ_VTX_WORD1_DST_SEL_Y(vtx-dst_sel_y) |
S_SQ_VTX_WORD1_DST_SEL_Z(vtx-dst_sel_z) |
S_SQ_VTX_WORD1_DST_SEL_W(vtx-dst_sel_w) |
- S_SQ_VTX_WORD1_USE_CONST_FIELDS(1) |
+
S_SQ_VTX_WORD1_USE_CONST_FIELDS(vtx-use_const_fields) |
+ S_SQ_VTX_WORD1_DATA_FORMAT(vtx-data_format) |
+
S_SQ_VTX_WORD1_NUM_FORMAT_ALL(vtx-num_format_all) |
+
S_SQ_VTX_WORD1_FORMAT_COMP_ALL(vtx-format_comp_all) |
+ S_SQ_VTX_WORD1_SRF_MODE_ALL(vtx-srf_mode_all) |
S_SQ_VTX_WORD1_GPR_DST_GPR(vtx-dst_gpr);
bc-bytecode[id++] = S_SQ_VTX_WORD2_MEGA_FETCH(1);
bc-bytecode[id++] = 0;
diff --git a/src/gallium/drivers/r600/r600_asm.h
b/src/gallium/drivers/r600/r600_asm.h
index cf67ca2..cbf46a8 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -101,6 +101,11 @@ struct r600_bc_vtx {
unsigneddst_sel_y;
unsigneddst_sel_z;
unsigneddst_sel_w;
+ unsigneduse_const_fields;
+ unsigneddata_format;
+ unsignednum_format_all;
+ unsignedformat_comp_all;
+ unsignedsrf_mode_all;
};
struct r600_bc_output {
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index a2091db..d35a990 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -439,6 +439,7 @@ static int tgsi_declaration(struct r600_shader_ctx *ctx)
vtx.dst_sel_y = 1;
vtx.dst_sel_z = 2;
vtx.dst_sel_w = 3;
+ vtx.use_const_fields = 1;
r = r600_bc_add_vtx(ctx-bc, vtx);
if (r)
return r;
___
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Mesa (master): r600g: fixup vertex format picking.
Module: Mesa
Branch: master
Commit: d662195f00fe60349cdda368eeb065910764842f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d662195f00fe60349cdda368eeb065910764842f
Author: Dave Airlie airl...@redhat.com
Date: Fri Oct 1 13:09:09 2010 +1000
r600g: fixup vertex format picking.
there are some vertex formats defined in r600c not in the docs.
---
src/gallium/drivers/r600/eg_state_inlines.h | 188 ++---
src/gallium/drivers/r600/evergreen_state.c| 36 ++---
src/gallium/drivers/r600/evergreend.h | 73 +-
src/gallium/drivers/r600/r600_state.c | 23 ++--
src/gallium/drivers/r600/r600_state_inlines.h | 158 ++---
src/gallium/drivers/r600/r600d.h | 73 +-
6 files changed, 407 insertions(+), 144 deletions(-)
diff --git a/src/gallium/drivers/r600/eg_state_inlines.h
b/src/gallium/drivers/r600/eg_state_inlines.h
index 497865a..c93b9d9 100644
--- a/src/gallium/drivers/r600/eg_state_inlines.h
+++ b/src/gallium/drivers/r600/eg_state_inlines.h
@@ -453,25 +453,6 @@ static INLINE uint32_t r600_translate_colorformat(enum
pipe_format format)
}
}
-static INLINE void r600_translate_vertex_num_format(enum pipe_format format,
uint32_t *num_format_p,
- uint32_t *format_comp_p)
-{
- uint32_t num_format = 0, format_comp = 0;
- switch (format) {
- case PIPE_FORMAT_R16G16B16A16_SSCALED:
- case PIPE_FORMAT_R16G16B16_SSCALED:
- case PIPE_FORMAT_R16G16_SSCALED:
- case PIPE_FORMAT_R32G32_SSCALED:
- num_format = V_030008_SQ_NUM_FORMAT_SCALED;
- format_comp = 1;
- break;
- default:
- break;
- }
- *num_format_p = num_format;
- *format_comp_p = format_comp;
-}
-
static INLINE boolean r600_is_sampler_format_supported(enum pipe_format format)
{
return r600_translate_texformat(format, NULL, NULL, NULL) != ~0;
@@ -493,4 +474,173 @@ static INLINE boolean
r600_is_vertex_format_supported(enum pipe_format format)
return r600_translate_colorformat(format) != ~0;
}
+static INLINE uint32_t r600_translate_vertex_data_type(enum pipe_format format)
+{
+ uint32_t result = 0;
+ const struct util_format_description *desc;
+ unsigned i;
+
+ desc = util_format_description(format);
+ if (desc-layout != UTIL_FORMAT_LAYOUT_PLAIN) {
+ goto out_unknown;
+ }
+
+ /* Find the first non-VOID channel. */
+ for (i = 0; i 4; i++) {
+ if (desc-channel[i].type != UTIL_FORMAT_TYPE_VOID) {
+ break;
+ }
+ }
+
+ switch (desc-channel[i].type) {
+ /* Half-floats, floats, doubles */
+case UTIL_FORMAT_TYPE_FLOAT:
+ switch (desc-channel[i].size) {
+case 16:
+ switch (desc-nr_channels) {
+ case 1:
+ result = V_030008_FMT_16_FLOAT;
+ break;
+ case 2:
+ result = V_030008_FMT_16_16_FLOAT;
+ break;
+ case 3:
+ result = V_030008_FMT_16_16_16_FLOAT;
+ break;
+ case 4:
+ result = V_030008_FMT_16_16_16_16_FLOAT;
+ break;
+ }
+ break;
+case 32:
+ switch (desc-nr_channels) {
+ case 1:
+ result = V_030008_FMT_32_FLOAT;
+ break;
+ case 2:
+ result = V_030008_FMT_32_32_FLOAT;
+ break;
+ case 3:
+ result = V_030008_FMT_32_32_32_FLOAT;
+ break;
+ case 4:
+ result = V_030008_FMT_32_32_32_32_FLOAT;
+ break;
+ }
+ break;
+default:
+ goto out_unknown;
+ }
+ break;
+ /* Unsigned ints */
+case UTIL_FORMAT_TYPE_UNSIGNED:
+ /* Signed ints */
+case UTIL_FORMAT_TYPE_SIGNED:
+ switch (desc-channel[i].size) {
+case 8:
+ switch (desc-nr_channels) {
+ case 1:
+ result = V_030008_FMT_8;
+ break;
+ case 2:
+ result = V_030008_FMT_8_8;
+ break;
+ case 3:
+ // result =
Mesa (master): r600g: sync vertex/texture cache on resources on evergreen
Module: Mesa
Branch: master
Commit: ac225c76a6a7c98d7e9afa50880db2480be6951f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac225c76a6a7c98d7e9afa50880db2480be6951f
Author: Dave Airlie airl...@redhat.com
Date: Fri Oct 1 13:48:10 2010 +1000
r600g: sync vertex/texture cache on resources on evergreen
this gets rid of lots of the instability on evergreen,
which isn't surprising since it really broken not to flush caches.
---
src/gallium/winsys/r600/drm/evergreen_hw_context.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index 3af299c..1b2c265 100644
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -431,8 +431,8 @@ static int evergreen_state_resource_init(struct
r600_context *ctx, u32 offset)
struct r600_reg r600_shader_resource[] = {
{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET,
R_03_RESOURCE0_WORD0, 0, 0},
{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET,
R_030004_RESOURCE0_WORD1, 0, 0},
- {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET,
R_030008_RESOURCE0_WORD2, 1, 0},
- {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET,
R_03000C_RESOURCE0_WORD3, 1, 0},
+ {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET,
R_030008_RESOURCE0_WORD2, 1, S_0085F0_TC_ACTION_ENA(1) |
S_0085F0_VC_ACTION_ENA(1)},
+ {PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET,
R_03000C_RESOURCE0_WORD3, 1, S_0085F0_TC_ACTION_ENA(1) |
S_0085F0_VC_ACTION_ENA(1)},
{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET,
R_030010_RESOURCE0_WORD4, 0, 0},
{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET,
R_030014_RESOURCE0_WORD5, 0, 0},
{PKT3_SET_RESOURCE, EVERGREEN_RESOURCE_OFFSET,
R_030018_RESOURCE0_WORD6, 0, 0},
___
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Mesa (master): r600g: fix evergreen draw-buffers
Module: Mesa
Branch: master
Commit: b67aa5311fa5d4130cf150c9004946fb30a15fae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b67aa5311fa5d4130cf150c9004946fb30a15fae
Author: Dave Airlie airl...@redhat.com
Date: Fri Oct 1 14:24:14 2010 +1000
r600g: fix evergreen draw-buffers
just a typo in the register headers.
---
src/gallium/drivers/r600/evergreend.h |2 +-
src/gallium/winsys/r600/drm/evergreen_hw_context.c |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreend.h
b/src/gallium/drivers/r600/evergreend.h
index 3cb9e63..e265348 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -1740,7 +1740,7 @@
#define R_028CA8_CB_COLOR1_VIEW 0x00028CA8
#define R_028CAC_CB_COLOR1_INFO 0x00028CAC
#define R_028CB0_CB_COLOR1_ATTRIB0x00028CB0
-#define R_028CB8_CB_COLOR1_DIM 0x00028CB8
+#define R_028CB4_CB_COLOR1_DIM 0x00028CB4
#define R_028CD8_CB_COLOR2_BASE 0x00028CD8
#define R_028CDC_CB_COLOR2_PITCH 0x00028CDC
#define R_028CE0_CB_COLOR2_SLICE 0x00028CE0
diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index 88db69c..557751e 100644
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -342,7 +342,7 @@ static const struct r600_reg evergreen_context_reg_list[] =
{
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028CA8_CB_COLOR1_VIEW, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028CAC_CB_COLOR1_INFO, 1, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028CB0_CB_COLOR1_ATTRIB, 1, 0},
- {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028CB8_CB_COLOR1_DIM, 0, 0},
+ {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028CB4_CB_COLOR1_DIM, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
GROUP_FORCE_NEW_BLOCK, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028CD8_CB_COLOR2_BASE, 1, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028CDC_CB_COLOR2_PITCH, 0, 0},
___
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Mesa (master): r600g: add cb flushing for extra buffers + depth buffer on r600/evergreen
Module: Mesa
Branch: master
Commit: 14c95bb4eec4417887ae882c39fead47624f0fda
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=14c95bb4eec4417887ae882c39fead47624f0fda
Author: Dave Airlie airl...@redhat.com
Date: Fri Oct 1 14:00:27 2010 +1000
r600g: add cb flushing for extra buffers + depth buffer on r600/evergreen
---
src/gallium/drivers/r600/evergreend.h | 15 +--
src/gallium/winsys/r600/drm/evergreen_hw_context.c | 25 +--
src/gallium/winsys/r600/drm/r600_hw_context.c | 15
3 files changed, 49 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreend.h
b/src/gallium/drivers/r600/evergreend.h
index f9328c6..3cb9e63 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -1865,9 +1865,18 @@
#define S_0085F0_DB_DEST_BASE_ENA(x) (((x) 0x1) 14)
#define G_0085F0_DB_DEST_BASE_ENA(x) (((x) 14) 0x1)
#define C_0085F0_DB_DEST_BASE_ENA0xBFFF
-#define S_0085F0_CR_DEST_BASE_ENA(x) (((x) 0x1) 15)
-#define G_0085F0_CR_DEST_BASE_ENA(x) (((x) 15) 0x1)
-#define C_0085F0_CR_DEST_BASE_ENA0x7FFF
+#define S_0085F0_CB8_DEST_BASE_ENA(x)(((x) 0x1) 15)
+#define G_0085F0_CB8_DEST_BASE_ENA(x)(((x) 15) 0x1)
+
+#define S_0085F0_CB9_DEST_BASE_ENA(x)(((x) 0x1) 16)
+#define G_0085F0_CB9_DEST_BASE_ENA(x)(((x) 16) 0x1)
+
+#define S_0085F0_CB10_DEST_BASE_ENA(x) (((x) 0x1) 17)
+#define G_0085F0_CB10_DEST_BASE_ENA(x) (((x) 17) 0x1)
+
+#define S_0085F0_CB11_DEST_BASE_ENA(x) (((x) 0x1) 18)
+#define G_0085F0_CB11_DEST_BASE_ENA(x) (((x) 18) 0x1)
+
#define S_0085F0_TC_ACTION_ENA(x)(((x) 0x1) 23)
#define G_0085F0_TC_ACTION_ENA(x)(((x) 23) 0x1)
#define C_0085F0_TC_ACTION_ENA 0xFF7F
diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index 1b2c265..88db69c 100644
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -727,6 +727,7 @@ void evergreen_context_pipe_state_set_vs_sampler(struct
r600_context *ctx, struc
void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw
*draw)
{
struct radeon_bo *cb[12];
+ struct radeon_bo *db;
unsigned ndwords = 9;
if (draw-indices) {
@@ -738,6 +739,7 @@ void evergreen_context_draw(struct r600_context *ctx, const
struct r600_draw *dr
}
/* find number of color buffer */
+ db = r600_context_reg_bo(ctx, R_028048_DB_Z_READ_BASE);
cb[0] = r600_context_reg_bo(ctx, R_028C60_CB_COLOR0_BASE);
cb[1] = r600_context_reg_bo(ctx, R_028C9C_CB_COLOR1_BASE);
cb[2] = r600_context_reg_bo(ctx, R_028CD8_CB_COLOR2_BASE);
@@ -755,6 +757,8 @@ void evergreen_context_draw(struct r600_context *ctx, const
struct r600_draw *dr
ndwords += 7;
}
}
+ if (db)
+ ndwords += 7;
/* queries need some special values */
if (ctx-num_query_running) {
@@ -808,11 +812,15 @@ void evergreen_context_draw(struct r600_context *ctx,
const struct r600_draw *dr
ctx-pm4[ctx-pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
/* flush color buffer */
- for (int i = 0; i 8; i++) {
+ for (int i = 0; i 12; i++) {
if (cb[i]) {
ctx-pm4[ctx-pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC,
3);
- ctx-pm4[ctx-pm4_cdwords++] =
(S_0085F0_CB0_DEST_BASE_ENA(1) i) |
-
S_0085F0_CB_ACTION_ENA(1);
+ if (i 7)
+ ctx-pm4[ctx-pm4_cdwords++] =
(S_0085F0_CB8_DEST_BASE_ENA(1) (i - 8)) |
+ S_0085F0_CB_ACTION_ENA(1);
+ else
+ ctx-pm4[ctx-pm4_cdwords++] =
(S_0085F0_CB0_DEST_BASE_ENA(1) i) |
+ S_0085F0_CB_ACTION_ENA(1);
ctx-pm4[ctx-pm4_cdwords++] = (cb[i]-size + 255) 8;
ctx-pm4[ctx-pm4_cdwords++] = 0x;
ctx-pm4[ctx-pm4_cdwords++] = 0x000A;
@@ -821,6 +829,17 @@ void evergreen_context_draw(struct r600_context *ctx,
const struct r600_draw *dr
r600_context_bo_reloc(ctx, ctx-pm4[ctx-pm4_cdwords -
1], cb[i]);
}
}
+ if (db) {
+ ctx-pm4[ctx-pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3);
+ ctx-pm4[ctx-pm4_cdwords++] = S_0085F0_DB_DEST_BASE_ENA(1) |
+ S_0085F0_DB_ACTION_ENA(1);
+
Mesa (master): r600g: flush SH cache on constant change on evergreen
Module: Mesa
Branch: master
Commit: 539a2978ed7f8d1756591061252d081f0f39fb9c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=539a2978ed7f8d1756591061252d081f0f39fb9c
Author: Dave Airlie airl...@redhat.com
Date: Fri Oct 1 14:43:02 2010 +1000
r600g: flush SH cache on constant change on evergreen
---
src/gallium/winsys/r600/drm/evergreen_hw_context.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index 557751e..129f571 100644
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -282,8 +282,8 @@ static const struct r600_reg evergreen_context_reg_list[] =
{
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028920_SQ_GS_VERT_ITEMSIZE_1, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028924_SQ_GS_VERT_ITEMSIZE_2, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028928_SQ_GS_VERT_ITEMSIZE_3, 0, 0},
- {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028940_ALU_CONST_CACHE_PS_0, 1, 0},
- {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028980_ALU_CONST_CACHE_VS_0, 1, 0},
+ {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028940_ALU_CONST_CACHE_PS_0, 1, S_0085F0_SH_ACTION_ENA(1)},
+ {PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028980_ALU_CONST_CACHE_VS_0, 1, S_0085F0_SH_ACTION_ENA(1)},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028A00_PA_SU_POINT_SIZE, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028A04_PA_SU_POINT_MINMAX, 0, 0},
{PKT3_SET_CONTEXT_REG, EVERGREEN_CONTEXT_REG_OFFSET,
R_028A08_PA_SU_LINE_CNTL, 0, 0},
___
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Mesa (master): r600c: pull over 6xx/7xx vertex fixes for evergreen
Module: Mesa
Branch: master
Commit: 0c39a53aa6b9ef47152e3d44f94fa4486a11831b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c39a53aa6b9ef47152e3d44f94fa4486a11831b
Author: Alex Deucher alexdeuc...@gmail.com
Date: Thu Sep 30 23:13:50 2010 -0400
r600c: pull over 6xx/7xx vertex fixes for evergreen
---
src/mesa/drivers/dri/r600/evergreen_chip.c | 28 +-
src/mesa/drivers/dri/r600/evergreen_render.c | 66 +---
src/mesa/drivers/dri/r600/evergreen_vertprog.c |6 +-
3 files changed, 42 insertions(+), 58 deletions(-)
diff --git a/src/mesa/drivers/dri/r600/evergreen_chip.c
b/src/mesa/drivers/dri/r600/evergreen_chip.c
index 5287a98..1662741 100644
--- a/src/mesa/drivers/dri/r600/evergreen_chip.c
+++ b/src/mesa/drivers/dri/r600/evergreen_chip.c
@@ -275,7 +275,6 @@ static void evergreenSetupVTXConstants(GLcontext * ctx,
{
context_t *context = EVERGREEN_CONTEXT(ctx);
struct radeon_aos * paos = (struct radeon_aos *)pAos;
-unsigned int nVBsize;
BATCH_LOCALS(context-radeon);
unsigned int uSQ_VTX_CONSTANT_WORD0_0;
@@ -289,21 +288,11 @@ static void evergreenSetupVTXConstants(GLcontext * ctx,
r700SyncSurf(context, paos-bo, RADEON_GEM_DOMAIN_GTT, 0,
VC_ACTION_ENA_bit);
-if(0 == pStreamDesc-stride)
-{
-nVBsize = paos-count * pStreamDesc-size *
getTypeSize(pStreamDesc-type);
-}
-else
-{
-nVBsize = (paos-count - 1) * pStreamDesc-stride
- + pStreamDesc-size * getTypeSize(pStreamDesc-type);
-}
-
//uSQ_VTX_CONSTANT_WORD0_0
uSQ_VTX_CONSTANT_WORD0_0 = paos-offset;
//uSQ_VTX_CONSTANT_WORD1_0
-uSQ_VTX_CONSTANT_WORD1_0 = nVBsize;
+uSQ_VTX_CONSTANT_WORD1_0 = paos-bo-size - paos-offset - 1;
//uSQ_VTX_CONSTANT_WORD2_0
SETfield(uSQ_VTX_CONSTANT_WORD2_0,
@@ -391,17 +380,6 @@ static void evergreenSendVTX(GLcontext *ctx, struct
radeon_state_atom *atom)
if (context-radeon.tcl.aos_count == 0)
return;
-BEGIN_BATCH_NO_AUTOSTATE(6);
-R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
-R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
-R600_OUT_BATCH(0);
-
-R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
-R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
-R600_OUT_BATCH(0);
-END_BATCH();
-COMMIT_BATCH();
-
for(i=0; iVERT_ATTRIB_MAX; i++) {
if(vp-mesa_program-Base.InputsRead (1 i))
{
@@ -410,7 +388,7 @@ static void evergreenSendVTX(GLcontext *ctx, struct
radeon_state_atom *atom)
(context-stream_desc[j]));
j++;
}
-}
+}
}
static void evergreenSendPA(GLcontext *ctx, struct radeon_state_atom *atom)
{
@@ -1522,7 +1500,7 @@ void evergreenInitAtoms(context_t *context)
context-radeon.hw.atomlist.name = atom-list;
EVERGREEN_ALLOC_STATE(init, always, 19, evergreenSendSQConfig);
-EVERGREEN_ALLOC_STATE(vtx, evergreen_vtx, (6 + (VERT_ATTRIB_MAX *
12)), evergreenSendVTX);
+EVERGREEN_ALLOC_STATE(vtx, evergreen_vtx, (VERT_ATTRIB_MAX * 12),
evergreenSendVTX);
EVERGREEN_ALLOC_STATE(pa,always,124, evergreenSendPA);
EVERGREEN_ALLOC_STATE(tp,always,0, evergreenSendTP);
EVERGREEN_ALLOC_STATE(sq,always,86, evergreenSendSQ); /*
85 */
diff --git a/src/mesa/drivers/dri/r600/evergreen_render.c
b/src/mesa/drivers/dri/r600/evergreen_render.c
index 85b2f9d..27089bf 100644
--- a/src/mesa/drivers/dri/r600/evergreen_render.c
+++ b/src/mesa/drivers/dri/r600/evergreen_render.c
@@ -148,7 +148,8 @@ static int evergreenNumVerts(int num_verts, int prim) //same
return num_verts - verts_off;
}
-static void evergreenRunRenderPrimitive(GLcontext * ctx, int start, int end,
int prim) //same
+static void evergreenRunRenderPrimitive(GLcontext * ctx, int start, int end,
int prim,
+ GLint basevertex) //same
{
context_t *context = EVERGREEN_CONTEXT(ctx);
BATCH_LOCALS(context-radeon);
@@ -186,6 +187,7 @@ static void evergreenRunRenderPrimitive(GLcontext * ctx,
int start, int end, int
total_emit = 3 /* VGT_PRIMITIVE_TYPE */
+ 2 /* VGT_INDEX_TYPE */
+ 2 /* NUM_INSTANCES */
++ 4 /* VTX_BASE_VTX_LOC + VTX_START_INST_LOC */
+ 5 + 2; /* DRAW_INDEX */
BEGIN_BATCH_NO_AUTOSTATE(total_emit);
@@ -198,6 +200,11 @@ static void evergreenRunRenderPrimitive(GLcontext * ctx,
int start, int end, int
// num instances
R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
R600_OUT_BATCH(1);
+/* offset */
+R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 2));
+R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
+R600_OUT_BATCH(basevertex); //VTX_BASE_VTX_LOC
+R600_OUT_BATCH(0); //VTX_START_INST_LOC
//
Mesa (7.9): r600c: pull over 6xx/7xx vertex fixes for evergreen
Module: Mesa
Branch: 7.9
Commit: d6e2b707baecb7655cd09d64080fc944cc5704a6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6e2b707baecb7655cd09d64080fc944cc5704a6
Author: Alex Deucher alexdeuc...@gmail.com
Date: Thu Sep 30 23:13:50 2010 -0400
r600c: pull over 6xx/7xx vertex fixes for evergreen
---
src/mesa/drivers/dri/r600/evergreen_chip.c | 28 +-
src/mesa/drivers/dri/r600/evergreen_render.c | 66 +---
src/mesa/drivers/dri/r600/evergreen_vertprog.c |6 +-
3 files changed, 42 insertions(+), 58 deletions(-)
diff --git a/src/mesa/drivers/dri/r600/evergreen_chip.c
b/src/mesa/drivers/dri/r600/evergreen_chip.c
index 5287a98..1662741 100644
--- a/src/mesa/drivers/dri/r600/evergreen_chip.c
+++ b/src/mesa/drivers/dri/r600/evergreen_chip.c
@@ -275,7 +275,6 @@ static void evergreenSetupVTXConstants(GLcontext * ctx,
{
context_t *context = EVERGREEN_CONTEXT(ctx);
struct radeon_aos * paos = (struct radeon_aos *)pAos;
-unsigned int nVBsize;
BATCH_LOCALS(context-radeon);
unsigned int uSQ_VTX_CONSTANT_WORD0_0;
@@ -289,21 +288,11 @@ static void evergreenSetupVTXConstants(GLcontext * ctx,
r700SyncSurf(context, paos-bo, RADEON_GEM_DOMAIN_GTT, 0,
VC_ACTION_ENA_bit);
-if(0 == pStreamDesc-stride)
-{
-nVBsize = paos-count * pStreamDesc-size *
getTypeSize(pStreamDesc-type);
-}
-else
-{
-nVBsize = (paos-count - 1) * pStreamDesc-stride
- + pStreamDesc-size * getTypeSize(pStreamDesc-type);
-}
-
//uSQ_VTX_CONSTANT_WORD0_0
uSQ_VTX_CONSTANT_WORD0_0 = paos-offset;
//uSQ_VTX_CONSTANT_WORD1_0
-uSQ_VTX_CONSTANT_WORD1_0 = nVBsize;
+uSQ_VTX_CONSTANT_WORD1_0 = paos-bo-size - paos-offset - 1;
//uSQ_VTX_CONSTANT_WORD2_0
SETfield(uSQ_VTX_CONSTANT_WORD2_0,
@@ -391,17 +380,6 @@ static void evergreenSendVTX(GLcontext *ctx, struct
radeon_state_atom *atom)
if (context-radeon.tcl.aos_count == 0)
return;
-BEGIN_BATCH_NO_AUTOSTATE(6);
-R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
-R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
-R600_OUT_BATCH(0);
-
-R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 1));
-R600_OUT_BATCH(mmSQ_VTX_START_INST_LOC - ASIC_CTL_CONST_BASE_INDEX);
-R600_OUT_BATCH(0);
-END_BATCH();
-COMMIT_BATCH();
-
for(i=0; iVERT_ATTRIB_MAX; i++) {
if(vp-mesa_program-Base.InputsRead (1 i))
{
@@ -410,7 +388,7 @@ static void evergreenSendVTX(GLcontext *ctx, struct
radeon_state_atom *atom)
(context-stream_desc[j]));
j++;
}
-}
+}
}
static void evergreenSendPA(GLcontext *ctx, struct radeon_state_atom *atom)
{
@@ -1522,7 +1500,7 @@ void evergreenInitAtoms(context_t *context)
context-radeon.hw.atomlist.name = atom-list;
EVERGREEN_ALLOC_STATE(init, always, 19, evergreenSendSQConfig);
-EVERGREEN_ALLOC_STATE(vtx, evergreen_vtx, (6 + (VERT_ATTRIB_MAX *
12)), evergreenSendVTX);
+EVERGREEN_ALLOC_STATE(vtx, evergreen_vtx, (VERT_ATTRIB_MAX * 12),
evergreenSendVTX);
EVERGREEN_ALLOC_STATE(pa,always,124, evergreenSendPA);
EVERGREEN_ALLOC_STATE(tp,always,0, evergreenSendTP);
EVERGREEN_ALLOC_STATE(sq,always,86, evergreenSendSQ); /*
85 */
diff --git a/src/mesa/drivers/dri/r600/evergreen_render.c
b/src/mesa/drivers/dri/r600/evergreen_render.c
index 85b2f9d..27089bf 100644
--- a/src/mesa/drivers/dri/r600/evergreen_render.c
+++ b/src/mesa/drivers/dri/r600/evergreen_render.c
@@ -148,7 +148,8 @@ static int evergreenNumVerts(int num_verts, int prim) //same
return num_verts - verts_off;
}
-static void evergreenRunRenderPrimitive(GLcontext * ctx, int start, int end,
int prim) //same
+static void evergreenRunRenderPrimitive(GLcontext * ctx, int start, int end,
int prim,
+ GLint basevertex) //same
{
context_t *context = EVERGREEN_CONTEXT(ctx);
BATCH_LOCALS(context-radeon);
@@ -186,6 +187,7 @@ static void evergreenRunRenderPrimitive(GLcontext * ctx,
int start, int end, int
total_emit = 3 /* VGT_PRIMITIVE_TYPE */
+ 2 /* VGT_INDEX_TYPE */
+ 2 /* NUM_INSTANCES */
++ 4 /* VTX_BASE_VTX_LOC + VTX_START_INST_LOC */
+ 5 + 2; /* DRAW_INDEX */
BEGIN_BATCH_NO_AUTOSTATE(total_emit);
@@ -198,6 +200,11 @@ static void evergreenRunRenderPrimitive(GLcontext * ctx,
int start, int end, int
// num instances
R600_OUT_BATCH(CP_PACKET3(R600_IT_NUM_INSTANCES, 0));
R600_OUT_BATCH(1);
+/* offset */
+R600_OUT_BATCH(CP_PACKET3(R600_IT_SET_CTL_CONST, 2));
+R600_OUT_BATCH(mmSQ_VTX_BASE_VTX_LOC - ASIC_CTL_CONST_BASE_INDEX);
+R600_OUT_BATCH(basevertex); //VTX_BASE_VTX_LOC
+R600_OUT_BATCH(0); //VTX_START_INST_LOC
// draw
