Mesa (master): intel: Protect against waiting on a NULL render target bo
Module: Mesa
Branch: master
Commit: a2029a78c39427f9bd7e24bbe5a5ff124f9d446b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a2029a78c39427f9bd7e24bbe5a5ff124f9d446b
Author: Chris Wilson ch...@chris-wilson.co.uk
Date: Thu Feb 24 10:12:37 2011 +
intel: Protect against waiting on a NULL render target bo
If we fall back to software rendering due to the render target being
absent (GPU hang or other error in creating the named target), then we
do not need to nor should we wait upon the results.
Reported-by: Magnus Kessler magnus.kess...@gmx.net
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34656
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
src/mesa/drivers/dri/intel/intel_context.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_context.c
b/src/mesa/drivers/dri/intel/intel_context.c
index d22fa27..c2e2a98 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -581,7 +581,7 @@ intelFinish(struct gl_context * ctx)
irb = intel_renderbuffer(fb-_ColorDrawBuffers[i]);
- if (irb irb-region)
+ if (irb irb-region irb-region-buffer)
drm_intel_bo_wait_rendering(irb-region-buffer);
}
if (fb-_DepthBuffer) {
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Mesa (master): i965: Unmap the correct pointer after discontiguous upload
Module: Mesa
Branch: master
Commit: 135ccb2daecb7792dfb17e66ab0acb79a97f78c8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=135ccb2daecb7792dfb17e66ab0acb79a97f78c8
Author: Chris Wilson ch...@chris-wilson.co.uk
Date: Thu Feb 24 10:58:22 2011 +
i965: Unmap the correct pointer after discontiguous upload
Fixes piglit/fbo-depth-sample-compare:
==14722== Invalid free() / delete / delete[]
==14722==at 0x4C240FD: free (vg_replace_malloc.c:366)
==14722==by 0x84FBBFD: intel_upload_unmap (intel_buffer_objects.c:695)
==14722==by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457)
==14722==by 0x852F975: brw_validate_state (brw_state_upload.c:394)
==14722==by 0x851FA24: brw_draw_prims (brw_draw.c:365)
==14722==by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389)
==14722==by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543)
==14722==by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973)
==14722==by 0x86D6A16: _mesa_set_enable (enable.c:351)
==14722==by 0x42CAD1: render_to_fbo (in
/home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722==by 0x42CEE3: piglit_display (in
/home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722==by 0x42F508: display (in
/home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722== Address 0xc606310 is 0 bytes after a block of size 18,720 alloc'd
==14722==at 0x4C244E8: malloc (vg_replace_malloc.c:236)
==14722==by 0x85202AB: copy_array_to_vbo_array (brw_draw_upload.c:256)
==14722==by 0x85205BC: brw_prepare_vertices (brw_draw_upload.c:457)
==14722==by 0x852F975: brw_validate_state (brw_state_upload.c:394)
==14722==by 0x851FA24: brw_draw_prims (brw_draw.c:365)
==14722==by 0x85F2221: vbo_exec_vtx_flush (vbo_exec_draw.c:389)
==14722==by 0x85EF443: vbo_exec_FlushVertices_internal (vbo_exec_api.c:543)
==14722==by 0x85EF49B: vbo_exec_FlushVertices (vbo_exec_api.c:973)
==14722==by 0x86D6A16: _mesa_set_enable (enable.c:351)
==14722==by 0x42CAD1: render_to_fbo (in
/home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722==by 0x42CEE3: piglit_display (in
/home/ickle/git/piglit/bin/fbo-depth-sample-compare)
==14722==by 0x42F508: display (in
/home/ickle/git/piglit/bin/fbo-depth-sample-compare)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34604
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
src/mesa/drivers/dri/i965/brw_draw_upload.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 140fb4e..4efb3cd 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -253,7 +253,8 @@ copy_array_to_vbo_array( struct brw_context *brw,
buffer-bo, buffer-offset);
} else {
const unsigned char *src = element-glarray-Ptr;
- char *dst = intel_upload_map(brw-intel, size, dst_stride);
+ char *map = intel_upload_map(brw-intel, size, dst_stride);
+ char *dst = map;
int i;
for (i = 0; i element-count; i++) {
@@ -261,7 +262,7 @@ copy_array_to_vbo_array( struct brw_context *brw,
src += element-glarray-StrideB;
dst += dst_stride;
}
- intel_upload_unmap(brw-intel, dst, size, dst_stride,
+ intel_upload_unmap(brw-intel, map, size, dst_stride,
buffer-bo, buffer-offset);
}
}
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Mesa (master): intel: Reset the buffer offset after releasing reference to packed upload
Module: Mesa
Branch: master
Commit: 5ce0f7f10908a0636900bae783cb426a6c607673
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ce0f7f10908a0636900bae783cb426a6c607673
Author: Chris Wilson ch...@chris-wilson.co.uk
Date: Thu Feb 24 12:29:51 2011 +
intel: Reset the buffer offset after releasing reference to packed upload
Fixes oglc/vbo(basic.bufferdata)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34603
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
src/mesa/drivers/dri/i965/brw_draw_upload.c |1 +
src/mesa/drivers/dri/intel/intel_buffer_objects.c | 134 -
2 files changed, 77 insertions(+), 58 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 4efb3cd..7234ce2 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -338,6 +338,7 @@ static void brw_prepare_vertices(struct brw_context *brw)
}
if (k == i) {
struct brw_vertex_buffer *buffer = brw-vb.buffers[j];
+
/* Named buffer object: Just reference its contents directly. */
buffer-bo = intel_bufferobj_source(intel, intel_buffer,
buffer-offset);
diff --git a/src/mesa/drivers/dri/intel/intel_buffer_objects.c
b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
index bc57803..2f750a7 100644
--- a/src/mesa/drivers/dri/intel/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/intel/intel_buffer_objects.c
@@ -53,6 +53,15 @@ intel_bufferobj_alloc_buffer(struct intel_context *intel,
intel_obj-Base.Size, 64);
}
+static void
+release_buffer(struct intel_buffer_object *intel_obj)
+{
+ drm_intel_bo_unreference(intel_obj-buffer);
+ intel_obj-buffer = NULL;
+ intel_obj-offset = 0;
+ intel_obj-source = 0;
+}
+
/**
* There is some duplication between mesa's bufferobjects and our
* bufmgr buffers. Both have an integer handle and a hashtable to
@@ -81,8 +90,7 @@ intel_bufferobj_release_region(struct intel_context *intel,
intel_obj-region-pbo = NULL;
intel_obj-region = NULL;
- drm_intel_bo_unreference(intel_obj-buffer);
- intel_obj-buffer = NULL;
+ release_buffer(intel_obj);
}
/* Break the COW tie to the region. Both the pbo and the region end
@@ -152,11 +160,9 @@ intel_bufferobj_data(struct gl_context * ctx,
if (intel_obj-region)
intel_bufferobj_release_region(intel, intel_obj);
- if (intel_obj-buffer != NULL) {
- drm_intel_bo_unreference(intel_obj-buffer);
- intel_obj-buffer = NULL;
- intel_obj-source = 0;
- }
+ if (intel_obj-buffer != NULL)
+ release_buffer(intel_obj);
+
free(intel_obj-sys_buffer);
intel_obj-sys_buffer = NULL;
@@ -204,6 +210,7 @@ intel_bufferobj_subdata(struct gl_context * ctx,
{
struct intel_context *intel = intel_context(ctx);
struct intel_buffer_object *intel_obj = intel_buffer_object(obj);
+ bool busy;
if (size == 0)
return;
@@ -213,47 +220,53 @@ intel_bufferobj_subdata(struct gl_context * ctx,
if (intel_obj-region)
intel_bufferobj_cow(intel, intel_obj);
+ /* If we have a single copy in system memory, update that */
if (intel_obj-sys_buffer) {
- if (intel_obj-buffer) {
-drm_intel_bo_unreference(intel_obj-buffer);
-intel_obj-buffer = NULL;
-intel_obj-source = 0;
+ if (intel_obj-source)
+release_buffer(intel_obj);
+
+ if (intel_obj-buffer == NULL) {
+memcpy((char *)intel_obj-sys_buffer + offset, data, size);
+return;
}
- memcpy((char *)intel_obj-sys_buffer + offset, data, size);
- } else {
- bool busy =
-drm_intel_bo_busy(intel_obj-buffer) ||
-drm_intel_bo_references(intel-batch.bo, intel_obj-buffer);
- /* replace the current busy bo with fresh data */
- if (busy size == intel_obj-Base.Size) {
-drm_intel_bo_unreference(intel_obj-buffer);
-intel_bufferobj_alloc_buffer(intel, intel_obj);
-drm_intel_bo_subdata(intel_obj-buffer, 0, size, data);
- } else if (intel-gen 6) {
-if (busy) {
- drm_intel_bo *temp_bo;
+ free(intel_obj-sys_buffer);
+ intel_obj-sys_buffer = NULL;
+ }
- temp_bo = drm_intel_bo_alloc(intel-bufmgr, subdata temp, size,
64);
+ /* Otherwise we need to update the copy in video memory. */
+ busy =
+ drm_intel_bo_busy(intel_obj-buffer) ||
+ drm_intel_bo_references(intel-batch.bo, intel_obj-buffer);
- drm_intel_bo_subdata(temp_bo, 0, size, data);
+ /* replace the current busy bo with fresh data */
+ if (busy size == intel_obj-Base.Size) {
+ drm_intel_bo_unreference(intel_obj-buffer);
+ intel_bufferobj_alloc_buffer(intel, intel_obj);
+ drm_intel_bo_subdata(intel_obj-buffer, 0, size, data);
+ } else if (intel-gen 6) {
+ if (busy) {
+drm_intel_bo
Mesa (master): i965: Remember to pack the constant blend color as floats into the batch
Module: Mesa Branch: master Commit: f19439940c43aa9d937716c6f1ee70cc26799e08 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f19439940c43aa9d937716c6f1ee70cc26799e08 Author: Chris Wilson ch...@chris-wilson.co.uk Date: Thu Feb 24 12:59:52 2011 + i965: Remember to pack the constant blend color as floats into the batch Fixes regression from aac120977d1ead319141d48d65c9bba626ec03b8. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34597 Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk --- src/mesa/drivers/dri/i965/brw_cc.c |8 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_cc.c b/src/mesa/drivers/dri/i965/brw_cc.c index b7048ec..412d82a 100644 --- a/src/mesa/drivers/dri/i965/brw_cc.c +++ b/src/mesa/drivers/dri/i965/brw_cc.c @@ -238,10 +238,10 @@ static void upload_blend_constant_color(struct brw_context *brw) BEGIN_BATCH(5); OUT_BATCH(_3DSTATE_BLEND_CONSTANT_COLOR 16 | (5-2)); - OUT_BATCH(ctx-Color.BlendColor[0]); - OUT_BATCH(ctx-Color.BlendColor[1]); - OUT_BATCH(ctx-Color.BlendColor[2]); - OUT_BATCH(ctx-Color.BlendColor[3]); + OUT_BATCH_F(ctx-Color.BlendColor[0]); + OUT_BATCH_F(ctx-Color.BlendColor[1]); + OUT_BATCH_F(ctx-Color.BlendColor[2]); + OUT_BATCH_F(ctx-Color.BlendColor[3]); CACHED_BATCH(); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): svga: Ensure rendertargets and textures are always rebound at every command buffer start .
Module: Mesa
Branch: master
Commit: 369ece170257ef687ca609cacd1d66d186274eb3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=369ece170257ef687ca609cacd1d66d186274eb3
Author: José Fonseca jfons...@vmware.com
Date: Wed Feb 23 13:32:37 2011 +
svga: Ensure rendertargets and textures are always rebound at every command
buffer start.
The svga_update_state() mechanism is inadequate as it will always end up
flushing the primitives before processing the SVGA_NEW_COMMAND_BUFFER
dirty state flag.
---
src/gallium/drivers/svga/svga_context.c | 16
src/gallium/drivers/svga/svga_state.h |4 +
src/gallium/drivers/svga/svga_state_framebuffer.c | 49 +
src/gallium/drivers/svga/svga_state_tss.c | 78 ++---
4 files changed, 138 insertions(+), 9 deletions(-)
diff --git a/src/gallium/drivers/svga/svga_context.c
b/src/gallium/drivers/svga/svga_context.c
index 9b737a1..f0f875b 100644
--- a/src/gallium/drivers/svga/svga_context.c
+++ b/src/gallium/drivers/svga/svga_context.c
@@ -204,6 +204,7 @@ void svga_context_flush( struct svga_context *svga,
{
struct svga_screen *svgascreen = svga_screen(svga-pipe.screen);
struct pipe_fence_handle *fence = NULL;
+ enum pipe_error ret;
svga-curr.nr_fbs = 0;
@@ -223,6 +224,21 @@ void svga_context_flush( struct svga_context *svga,
*/
svga-dirty |= SVGA_NEW_COMMAND_BUFFER;
+ /*
+* We must reemit the surface bindings here, because svga_update_state
+* will always flush the primitives before processing the
+* SVGA_NEW_COMMAND_BUFFER state change.
+*
+* TODO: Refactor this.
+*/
+ ret = svga_reemit_framebuffer_bindings(svga);
+ assert(ret == PIPE_OK);
+
+ ret = svga_reemit_tss_bindings(svga);
+ assert(ret == PIPE_OK);
+
+ svga-dirty = ~SVGA_NEW_COMMAND_BUFFER;
+
if (SVGA_DEBUG DEBUG_SYNC) {
if (fence)
svga-pipe.screen-fence_finish( svga-pipe.screen, fence, 0);
diff --git a/src/gallium/drivers/svga/svga_state.h
b/src/gallium/drivers/svga/svga_state.h
index 22d5a6d..7f239e7 100644
--- a/src/gallium/drivers/svga/svga_state.h
+++ b/src/gallium/drivers/svga/svga_state.h
@@ -92,4 +92,8 @@ void svga_update_state_retry( struct svga_context *svga,
enum pipe_error svga_emit_initial_state( struct svga_context *svga );
+enum pipe_error svga_reemit_framebuffer_bindings( struct svga_context *svga );
+
+enum pipe_error svga_reemit_tss_bindings( struct svga_context *svga );
+
#endif
diff --git a/src/gallium/drivers/svga/svga_state_framebuffer.c
b/src/gallium/drivers/svga/svga_state_framebuffer.c
index fcbb35e..cdadb20 100644
--- a/src/gallium/drivers/svga/svga_state_framebuffer.c
+++ b/src/gallium/drivers/svga/svga_state_framebuffer.c
@@ -93,6 +93,55 @@ static int emit_framebuffer( struct svga_context *svga,
}
+/*
+ * Rebind rendertargets.
+ *
+ * Similar to emit_framebuffer, but without any state checking/update.
+ *
+ * Called at the beginning of every new command buffer to ensure that
+ * non-dirty rendertargets are properly paged-in.
+ */
+enum pipe_error
+svga_reemit_framebuffer_bindings(struct svga_context *svga)
+{
+ struct pipe_framebuffer_state *hw = svga-state.hw_clear.framebuffer;
+ unsigned i;
+ enum pipe_error ret;
+
+ for (i = 0; i MIN2(PIPE_MAX_COLOR_BUFS, 8); ++i) {
+ if (hw-cbufs[i]) {
+ ret = SVGA3D_SetRenderTarget(svga-swc, SVGA3D_RT_COLOR0 + i,
hw-cbufs[i]);
+ if (ret != PIPE_OK) {
+return ret;
+ }
+ }
+ }
+
+ if (hw-zsbuf) {
+ ret = SVGA3D_SetRenderTarget(svga-swc, SVGA3D_RT_DEPTH, hw-zsbuf);
+ if (ret != PIPE_OK) {
+ return ret;
+ }
+
+ if (hw-zsbuf
+ hw-zsbuf-format == PIPE_FORMAT_S8_USCALED_Z24_UNORM) {
+ ret = SVGA3D_SetRenderTarget(svga-swc, SVGA3D_RT_STENCIL, hw-zsbuf);
+ if (ret != PIPE_OK) {
+return ret;
+ }
+ }
+ else {
+ ret = SVGA3D_SetRenderTarget(svga-swc, SVGA3D_RT_STENCIL, NULL);
+ if (ret != PIPE_OK) {
+return ret;
+ }
+ }
+ }
+
+ return PIPE_OK;
+}
+
+
struct svga_tracked_state svga_hw_framebuffer =
{
hw framebuffer state,
diff --git a/src/gallium/drivers/svga/svga_state_tss.c
b/src/gallium/drivers/svga/svga_state_tss.c
index f8b269a..c502506 100644
--- a/src/gallium/drivers/svga/svga_state_tss.c
+++ b/src/gallium/drivers/svga/svga_state_tss.c
@@ -52,6 +52,16 @@ void svga_cleanup_tss_binding(struct svga_context *svga)
}
+struct bind_queue {
+ struct {
+ unsigned unit;
+ struct svga_hw_view_state *view;
+ } bind[PIPE_MAX_SAMPLERS];
+
+ unsigned bind_count;
+};
+
+
static int
update_tss_binding(struct svga_context *svga,
unsigned dirty )
@@ -63,15 +73,7 @@ update_tss_binding(struct svga_context *svga,
unsigned min_lod;
unsigned max_lod;
-
- struct {
- struct {
- unsigned unit;
- struct svga_hw_view_state *view;
-
Mesa (master): gallium/utils: Fix vertex element setup
Module: Mesa
Branch: master
Commit: 728695b4353c8b74b30310cd2d87071f662fdb63
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=728695b4353c8b74b30310cd2d87071f662fdb63
Author: Fabian Bieler der.f...@gmx.net
Date: Thu Feb 24 10:56:16 2011 +0100
gallium/utils: Fix vertex element setup
Check if element was translated per element instead of per buffer.
---
src/gallium/auxiliary/util/u_vbuf_mgr.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_vbuf_mgr.c
b/src/gallium/auxiliary/util/u_vbuf_mgr.c
index 096392f..dec8dd7 100644
--- a/src/gallium/auxiliary/util/u_vbuf_mgr.c
+++ b/src/gallium/auxiliary/util/u_vbuf_mgr.c
@@ -156,7 +156,7 @@ static void u_vbuf_translate_begin(struct u_vbuf_mgr_priv
*mgr,
{
struct translate_key key;
struct translate_element *te;
- unsigned tr_elem_index[PIPE_MAX_ATTRIBS] = {0};
+ unsigned tr_elem_index[PIPE_MAX_ATTRIBS];
struct translate *tr;
boolean vb_translated[PIPE_MAX_ATTRIBS] = {0};
uint8_t *vb_map[PIPE_MAX_ATTRIBS] = {0}, *out_map;
@@ -166,6 +166,7 @@ static void u_vbuf_translate_begin(struct u_vbuf_mgr_priv
*mgr,
struct pipe_vertex_element new_velems[PIPE_MAX_ATTRIBS];
memset(key, 0, sizeof(key));
+ memset(tr_elem_index, 0xff, sizeof(tr_elem_index));
/* Initialize the translate key, i.e. the recipe how vertices should be
* translated. */
@@ -281,7 +282,7 @@ static void u_vbuf_translate_begin(struct u_vbuf_mgr_priv
*mgr,
/* Setup new vertex elements. */
for (i = 0; i mgr-ve-count; i++) {
- if (vb_translated[mgr-ve-ve[i].vertex_buffer_index]) {
+ if (tr_elem_index[i] key.nr_elements) {
te = key.element[tr_elem_index[i]];
new_velems[i].instance_divisor = mgr-ve-ve[i].instance_divisor;
new_velems[i].src_format = te-output_format;
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Mesa (master): nvc0: don't overwrite phi sources at the end of a loop
Module: Mesa
Branch: master
Commit: 3d190e44dec40650d88256cb074a12ca74d7c31e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d190e44dec40650d88256cb074a12ca74d7c31e
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Sat Feb 19 14:14:40 2011 +0100
nvc0: don't overwrite phi sources at the end of a loop
Except the reference to its own result.
---
src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c |6 +-
1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c
b/src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c
index 687def0..e2838a0 100644
--- a/src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c
+++ b/src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c
@@ -465,6 +465,7 @@ bld_loop_end(struct bld_context *bld, struct nv_basic_block
*bb)
reg = (struct bld_register *)phi-target;
phi-target = NULL;
+ /* start with s == 1, src[0] is from outside the loop */
for (s = 1, n = 0; n bb-num_in; ++n) {
if (bb-in_kind[n] != CFG_EDGE_BACK)
continue;
@@ -476,8 +477,11 @@ bld_loop_end(struct bld_context *bld, struct
nv_basic_block *bb)
for (i = 0; i 4; ++i)
if (phi-src[i] phi-src[i]-value == val)
break;
- if (i == 4)
+ if (i == 4) {
+/* skip values we do not want to replace */
+for (; phi-src[s] phi-src[s]-value != phi-def[0]; ++s);
nv_reference(bld-pc, phi, s++, val);
+ }
}
bld-pc-current_block = save;
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Mesa (master): nvc0: don' t visit target blocks of a loop break multiple times
Module: Mesa
Branch: master
Commit: 88066d62ae7ec9c715e195f8ff65a0dc5b64c25e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=88066d62ae7ec9c715e195f8ff65a0dc5b64c25e
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Sat Feb 19 14:18:28 2011 +0100
nvc0: don't visit target blocks of a loop break multiple times
---
src/gallium/drivers/nvc0/nvc0_pc.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_pc.c
b/src/gallium/drivers/nvc0/nvc0_pc.c
index e0cba05..3a3a00f 100644
--- a/src/gallium/drivers/nvc0/nvc0_pc.c
+++ b/src/gallium/drivers/nvc0/nvc0_pc.c
@@ -189,7 +189,10 @@ nvc0_pc_pass_in_order(struct nv_basic_block *root,
nv_pc_pass_func f,
bb[p++] = b-out[j];
break;
case CFG_EDGE_LOOP_LEAVE:
-bbb[pp++] = b-out[j];
+if (!b-out[j]-priv) {
+ bbb[pp++] = b-out[j];
+ b-out[j]-priv = 1;
+}
break;
default:
assert(0);
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Mesa (master): nvc0: fix SSG
Module: Mesa
Branch: master
Commit: 7d8ff54feb0b590048184bb41e214a511770fd20
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7d8ff54feb0b590048184bb41e214a511770fd20
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Sat Feb 19 20:26:29 2011 +0100
nvc0: fix SSG
---
src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c | 10 +-
1 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c
b/src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c
index e2838a0..18ae0e0 100644
--- a/src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c
+++ b/src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c
@@ -1825,11 +1825,11 @@ bld_instruction(struct bld_context *bld,
case TGSI_OPCODE_SSG:
FOR_EACH_DST0_ENABLED_CHANNEL(c, insn) { /* XXX: set lt, set gt, sub */
src0 = emit_fetch(bld, insn, 0, c);
- src1 = bld_setp(bld, NV_OP_SET_F32, NV_CC_EQ, src0, bld-zero);
- temp = bld_insn_2(bld, NV_OP_AND, src0, bld_imm_u32(bld, 0x8000));
- temp = bld_insn_2(bld, NV_OP_OR, temp, bld_imm_f32(bld, 1.0f));
- dst0[c] = bld_insn_1(bld, NV_OP_MOV, temp);
- bld_src_predicate(bld, dst0[c]-insn, 1, src1);
+ src1 = bld_insn_2(bld, NV_OP_FSET_F32, src0, bld-zero);
+ src2 = bld_insn_2(bld, NV_OP_FSET_F32, src0, bld-zero);
+ src1-insn-set_cond = NV_CC_GT;
+ src2-insn-set_cond = NV_CC_LT;
+ dst0[c] = bld_insn_2(bld, NV_OP_SUB_F32, src1, src2);
}
break;
case TGSI_OPCODE_SUB:
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Mesa (master): nvc0: multiply polygon offset units by 2
Module: Mesa Branch: master Commit: 1579017b08f28d460e17de65bcc8ba17ba695c37 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1579017b08f28d460e17de65bcc8ba17ba695c37 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Sat Feb 19 20:26:49 2011 +0100 nvc0: multiply polygon offset units by 2 Wasn't sure if this still was necessary because the piglit test started to fail at some point on nv50 where we already do this. --- src/gallium/drivers/nvc0/nvc0_state.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/gallium/drivers/nvc0/nvc0_state.c b/src/gallium/drivers/nvc0/nvc0_state.c index 666e380..aa43719 100644 --- a/src/gallium/drivers/nvc0/nvc0_state.c +++ b/src/gallium/drivers/nvc0/nvc0_state.c @@ -238,7 +238,7 @@ nvc0_rasterizer_state_create(struct pipe_context *pipe, SB_BEGIN_3D(so, POLYGON_OFFSET_FACTOR, 1); SB_DATA(so, fui(cso-offset_scale)); SB_BEGIN_3D(so, POLYGON_OFFSET_UNITS, 1); -SB_DATA(so, fui(cso-offset_units)); /* XXX: multiply by 2 ? */ +SB_DATA(so, fui(cso-offset_units * 2.0f)); } assert(so-size (sizeof(so-state) / sizeof(so-state[0]))); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nvc0: values for undefined outputs must have file GPR
Module: Mesa
Branch: master
Commit: 410a13c5ce799fe97a4e4503190d0f66fb2559a3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=410a13c5ce799fe97a4e4503190d0f66fb2559a3
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Sun Feb 20 15:10:02 2011 +0100
nvc0: values for undefined outputs must have file GPR
---
src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c | 11 ---
1 files changed, 4 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c
b/src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c
index 18ae0e0..5e208e8 100644
--- a/src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c
+++ b/src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c
@@ -133,13 +133,10 @@ struct bld_context {
static INLINE ubyte
bld_register_file(struct bld_context *bld, struct bld_register *reg)
{
- if (reg bld-avs[0][0]) return NV_FILE_GPR;
- else
- if (reg bld-pvs[0][0]) return NV_FILE_GPR;
- else
- if (reg bld-ovs[0][0]) return NV_FILE_PRED;
- else
- return NV_FILE_MEM_V;
+ if (reg = bld-pvs[0][0]
+ reg bld-ovs[0][0])
+ return NV_FILE_PRED;
+ return NV_FILE_GPR;
}
static INLINE struct nv_value *
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Mesa (master): nvc0: improve userspace fencing
Module: Mesa
Branch: master
Commit: a6ea37da4bd02241ce3bf522b93dd7ff0757f959
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a6ea37da4bd02241ce3bf522b93dd7ff0757f959
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Sun Feb 20 17:57:47 2011 +0100
nvc0: improve userspace fencing
Before, there were situations in which we never checked the fences
for completion (some loading screens for example) and thus never
released memory.
---
src/gallium/drivers/nvc0/nvc0_context.c | 22 +--
src/gallium/drivers/nvc0/nvc0_context.h |2 +
src/gallium/drivers/nvc0/nvc0_fence.c | 36 ++-
src/gallium/drivers/nvc0/nvc0_fence.h |3 +-
src/gallium/drivers/nvc0/nvc0_screen.h |3 +-
src/gallium/drivers/nvc0/nvc0_vbo.c |6 +++-
6 files changed, 46 insertions(+), 26 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_context.c
b/src/gallium/drivers/nvc0/nvc0_context.c
index 20c1a31..f02de4d 100644
--- a/src/gallium/drivers/nvc0/nvc0_context.c
+++ b/src/gallium/drivers/nvc0/nvc0_context.c
@@ -47,15 +47,12 @@ nvc0_flush(struct pipe_context *pipe, unsigned flags,
OUT_RING (chan, 0);
}
- if (fence) {
- nvc0_screen_fence_new(nvc0-screen, (struct nvc0_fence **)fence, TRUE);
- }
+ if (fence)
+ nvc0_fence_reference((struct nvc0_fence **)fence,
+ nvc0-screen-fence.current);
- if (flags (PIPE_FLUSH_SWAPBUFFERS | PIPE_FLUSH_FRAME)) {
+ if (flags (PIPE_FLUSH_SWAPBUFFERS | PIPE_FLUSH_FRAME))
FIRE_RING(chan);
-
- nvc0_screen_fence_next(nvc0-screen);
- }
}
static void
@@ -71,6 +68,16 @@ nvc0_destroy(struct pipe_context *pipe)
FREE(nvc0);
}
+void
+nvc0_default_flush_notify(struct nouveau_channel *chan)
+{
+ struct nvc0_context *nvc0 = chan-user_private;
+
+ nvc0_screen_fence_update(nvc0-screen, TRUE);
+
+ nvc0_screen_fence_next(nvc0-screen);
+}
+
struct pipe_context *
nvc0_create(struct pipe_screen *pscreen, void *priv)
{
@@ -95,6 +102,7 @@ nvc0_create(struct pipe_screen *pscreen, void *priv)
nvc0-pipe.flush = nvc0_flush;
screen-base.channel-user_private = nvc0;
+ screen-base.channel-flush_notify = nvc0_default_flush_notify;
nvc0_init_query_functions(nvc0);
nvc0_init_surface_functions(nvc0);
diff --git a/src/gallium/drivers/nvc0/nvc0_context.h
b/src/gallium/drivers/nvc0/nvc0_context.h
index a082ad4..3722f35 100644
--- a/src/gallium/drivers/nvc0/nvc0_context.h
+++ b/src/gallium/drivers/nvc0/nvc0_context.h
@@ -156,6 +156,8 @@ nvc0_surface(struct pipe_surface *ps)
/* nvc0_context.c */
struct pipe_context *nvc0_create(struct pipe_screen *, void *);
+void nvc0_default_flush_notify(struct nouveau_channel *);
+
void nvc0_bufctx_emit_relocs(struct nvc0_context *);
void nvc0_bufctx_add_resident(struct nvc0_context *, int ctx,
struct nvc0_resource *, uint32_t flags);
diff --git a/src/gallium/drivers/nvc0/nvc0_fence.c
b/src/gallium/drivers/nvc0/nvc0_fence.c
index 3a3dd75..f2d4b14 100644
--- a/src/gallium/drivers/nvc0/nvc0_fence.c
+++ b/src/gallium/drivers/nvc0/nvc0_fence.c
@@ -84,7 +84,8 @@ nvc0_fence_del(struct nvc0_fence *fence)
struct nvc0_fence *it;
struct nvc0_screen *screen = fence-screen;
- if (fence-state == NVC0_FENCE_STATE_EMITTED) {
+ if (fence-state == NVC0_FENCE_STATE_EMITTED ||
+ fence-state == NVC0_FENCE_STATE_FLUSHED) {
if (fence == screen-fence.head) {
screen-fence.head = fence-next;
if (!screen-fence.head)
@@ -119,8 +120,8 @@ nvc0_fence_trigger_release_buffers(struct nvc0_fence *fence)
fence-buffers = NULL;
}
-static void
-nvc0_screen_fence_update(struct nvc0_screen *screen)
+void
+nvc0_screen_fence_update(struct nvc0_screen *screen, boolean flushed)
{
struct nvc0_fence *fence;
struct nvc0_fence *next = NULL;
@@ -147,38 +148,43 @@ nvc0_screen_fence_update(struct nvc0_screen *screen)
screen-fence.head = next;
if (!next)
screen-fence.tail = NULL;
-}
-#define NVC0_FENCE_MAX_SPINS (1 17)
+ if (flushed) {
+ for (fence = next; fence; fence = fence-next)
+ fence-state = NVC0_FENCE_STATE_FLUSHED;
+ }
+}
boolean
nvc0_fence_signalled(struct nvc0_fence *fence)
{
struct nvc0_screen *screen = fence-screen;
- if (fence-state == NVC0_FENCE_STATE_EMITTED)
- nvc0_screen_fence_update(screen);
+ if (fence-state = NVC0_FENCE_STATE_EMITTED)
+ nvc0_screen_fence_update(screen, FALSE);
return fence-state == NVC0_FENCE_STATE_SIGNALLED;
}
+#define NVC0_FENCE_MAX_SPINS (1 31)
+
boolean
nvc0_fence_wait(struct nvc0_fence *fence)
{
struct nvc0_screen *screen = fence-screen;
- int spins = 0;
+ uint32_t spins = 0;
- if (fence-state == NVC0_FENCE_STATE_AVAILABLE) {
+ if (fence-state NVC0_FENCE_STATE_EMITTED) {
nvc0_fence_emit(fence);
- FIRE_RING(screen-base.channel);
-
if (fence == screen-fence.current)
Mesa (master): nvc0: sync textures with render targets ourselves
Module: Mesa
Branch: master
Commit: 67c7aefea33a7935e42ede30463eb7ca5009b068
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=67c7aefea33a7935e42ede30463eb7ca5009b068
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Thu Feb 24 17:04:49 2011 +0100
nvc0: sync textures with render targets ourselves
Fixes for example piglit/fbo-flushing and nexuiz' bloom effect.
---
src/gallium/drivers/nvc0/nvc0_buffer.c |6 +++---
src/gallium/drivers/nvc0/nvc0_resource.h |5 +++--
src/gallium/drivers/nvc0/nvc0_screen.h |5 +
src/gallium/drivers/nvc0/nvc0_state_validate.c | 16
src/gallium/drivers/nvc0/nvc0_tex.c|7 +++
src/gallium/drivers/nvc0/nvc0_winsys.h |2 +-
6 files changed, 35 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_buffer.c
b/src/gallium/drivers/nvc0/nvc0_buffer.c
index f16671a..aa949bd 100644
--- a/src/gallium/drivers/nvc0/nvc0_buffer.c
+++ b/src/gallium/drivers/nvc0/nvc0_buffer.c
@@ -117,7 +117,7 @@ nvc0_buffer_download(struct nvc0_context *nvc0, struct
nvc0_resource *buf,
memcpy(buf-data + start, bounce-map, size);
nouveau_bo_unmap(bounce);
- buf-status = ~NVC0_BUFFER_STATUS_DIRTY;
+ buf-status = ~NVC0_BUFFER_STATUS_GPU_WRITING;
nouveau_bo_ref(NULL, bounce);
if (mm)
@@ -156,7 +156,7 @@ nvc0_buffer_upload(struct nvc0_context *nvc0, struct
nvc0_resource *buf,
release_allocation(mm, nvc0-screen-fence.current);
if (start == 0 size == buf-base.width0)
- buf-status = ~NVC0_BUFFER_STATUS_DIRTY;
+ buf-status = ~NVC0_BUFFER_STATUS_GPU_WRITING;
return TRUE;
}
@@ -179,7 +179,7 @@ nvc0_buffer_transfer_get(struct pipe_context *pipe,
if (buf-domain == NOUVEAU_BO_VRAM) {
if (usage PIPE_TRANSFER_READ) {
- if (buf-status NVC0_BUFFER_STATUS_DIRTY)
+ if (buf-status NVC0_BUFFER_STATUS_GPU_WRITING)
nvc0_buffer_download(nvc0_context(pipe), buf, 0, buf-base.width0);
}
}
diff --git a/src/gallium/drivers/nvc0/nvc0_resource.h
b/src/gallium/drivers/nvc0/nvc0_resource.h
index 709e615..599823c 100644
--- a/src/gallium/drivers/nvc0/nvc0_resource.h
+++ b/src/gallium/drivers/nvc0/nvc0_resource.h
@@ -24,7 +24,8 @@ struct nvc0_context;
* USER_MEMORY: resource-data is a pointer to client memory and may change
* between GL calls
*/
-#define NVC0_BUFFER_STATUS_DIRTY (1 0)
+#define NVC0_BUFFER_STATUS_GPU_READING (1 0)
+#define NVC0_BUFFER_STATUS_GPU_WRITING (1 1)
#define NVC0_BUFFER_STATUS_USER_MEMORY (1 7)
/* Resources, if mapped into the GPU's address space, are guaranteed to
@@ -90,7 +91,7 @@ nvc0_resource_map_offset(struct nvc0_context *nvc0,
nvc0_buffer_adjust_score(nvc0, res, -250);
if ((res-domain == NOUVEAU_BO_VRAM)
- (res-status NVC0_BUFFER_STATUS_DIRTY))
+ (res-status NVC0_BUFFER_STATUS_GPU_WRITING))
nvc0_buffer_download(nvc0, res, 0, res-base.width0);
if ((res-domain != NOUVEAU_BO_GART) ||
diff --git a/src/gallium/drivers/nvc0/nvc0_screen.h
b/src/gallium/drivers/nvc0/nvc0_screen.h
index 5af96cb..d952ff1 100644
--- a/src/gallium/drivers/nvc0/nvc0_screen.h
+++ b/src/gallium/drivers/nvc0/nvc0_screen.h
@@ -131,6 +131,11 @@ nvc0_resource_validate(struct nvc0_resource *res, uint32_t
flags)
if (likely(res-bo)) {
nouveau_bo_validate(screen-base.channel, res-bo, flags);
+ if (flags NOUVEAU_BO_WR)
+ res-status |= NVC0_BUFFER_STATUS_GPU_WRITING;
+ if (flags NOUVEAU_BO_RD)
+ res-status |= NVC0_BUFFER_STATUS_GPU_READING;
+
nvc0_resource_fence(res, flags);
}
}
diff --git a/src/gallium/drivers/nvc0/nvc0_state_validate.c
b/src/gallium/drivers/nvc0/nvc0_state_validate.c
index 96c1198..0cc0a0c 100644
--- a/src/gallium/drivers/nvc0/nvc0_state_validate.c
+++ b/src/gallium/drivers/nvc0/nvc0_state_validate.c
@@ -58,6 +58,7 @@ nvc0_validate_fb(struct nvc0_context *nvc0)
struct nouveau_channel *chan = nvc0-screen-base.channel;
struct pipe_framebuffer_state *fb = nvc0-framebuffer;
unsigned i;
+boolean serialize = FALSE;
nvc0_bufctx_reset(nvc0, NVC0_BUFCTX_FRAME);
@@ -86,6 +87,11 @@ nvc0_validate_fb(struct nvc0_context *nvc0)
OUT_RING (chan, sf-depth);
OUT_RING (chan, mt-layer_stride 2);
+if (mt-base.status NVC0_BUFFER_STATUS_GPU_READING)
+ serialize = TRUE;
+mt-base.status |= NVC0_BUFFER_STATUS_GPU_WRITING;
+mt-base.status = ~NVC0_BUFFER_STATUS_GPU_READING;
+
nvc0_bufctx_add_resident(nvc0, NVC0_BUFCTX_FRAME, mt-base,
NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
}
@@ -111,12 +117,22 @@ nvc0_validate_fb(struct nvc0_context *nvc0)
OUT_RING (chan, sf-height);
OUT_RING (chan, (unk 16) | sf-depth);
+if (mt-base.status NVC0_BUFFER_STATUS_GPU_READING)
+ serialize = TRUE;
+mt-base.status |= NVC0_BUFFER_STATUS_GPU_WRITING;
+
Mesa (master): nvc0: correct allocation of constrained registers
Module: Mesa
Branch: master
Commit: 4377657f8e204fe2c7b6af194293dd3bea63fca8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4377657f8e204fe2c7b6af194293dd3bea63fca8
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Thu Feb 24 17:08:23 2011 +0100
nvc0: correct allocation of constrained registers
In linear scan we can't allocate multiple values with different
live ranges at the same time to assign them consecutive regs.
Maybe we should just switch to graph coloring for all values ...
---
src/gallium/drivers/nvc0/nvc0_pc_regalloc.c | 221 +++
1 files changed, 154 insertions(+), 67 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_pc_regalloc.c
b/src/gallium/drivers/nvc0/nvc0_pc_regalloc.c
index 718943b..d721394 100644
--- a/src/gallium/drivers/nvc0/nvc0_pc_regalloc.c
+++ b/src/gallium/drivers/nvc0/nvc0_pc_regalloc.c
@@ -39,6 +39,30 @@ struct register_set {
struct nv_pc *pc;
};
+/* aliasing is allowed */
+static void
+intersect_register_sets(struct register_set *dst,
+struct register_set *src1, struct register_set *src2)
+{
+ int i;
+
+ for (i = 0; i NVC0_NUM_REGISTER_FILES; ++i) {
+ dst-bits[i][0] = src1-bits[i][0] | src2-bits[i][0];
+ dst-bits[i][1] = src1-bits[i][1] | src2-bits[i][1];
+ }
+}
+
+static void
+mask_register_set(struct register_set *set, uint32_t mask, uint32_t umask)
+{
+ int i;
+
+ for (i = 0; i NVC0_NUM_REGISTER_FILES; ++i) {
+ set-bits[i][0] = (set-bits[i][0] | mask) umask;
+ set-bits[i][1] = (set-bits[i][1] | mask) umask;
+ }
+}
+
struct nv_pc_pass {
struct nv_pc *pc;
struct nv_instruction **insns;
@@ -327,14 +351,14 @@ do_join_values(struct nv_pc_pass *ctx, struct nv_value
*a, struct nv_value *b)
assert(b-join == a-join);
}
-static INLINE void
+static INLINE boolean
try_join_values(struct nv_pc_pass *ctx, struct nv_value *a, struct nv_value *b)
{
if (!join_allowed(ctx, a, b)) {
#ifdef NVC0_RA_DEBUG_JOIN
debug_printf(cannot join %i to %i: not allowed\n, b-n, a-n);
#endif
- return;
+ return FALSE;
}
if (livei_have_overlap(a-join, b-join)) {
#ifdef NVC0_RA_DEBUG_JOIN
@@ -342,10 +366,27 @@ try_join_values(struct nv_pc_pass *ctx, struct nv_value
*a, struct nv_value *b)
livei_print(a);
livei_print(b);
#endif
- return;
+ return FALSE;
}
do_join_values(ctx, a, b);
+
+ return TRUE;
+}
+
+static void
+join_values_nofail(struct nv_pc_pass *ctx,
+ struct nv_value *a, struct nv_value *b, boolean type_only)
+{
+ if (type_only) {
+ assert(join_allowed(ctx, a, b));
+ do_join_values(ctx, a, b);
+ } else {
+ boolean ok = try_join_values(ctx, a, b);
+ if (!ok) {
+ NOUVEAU_ERR(failed to coalesce values\n);
+ }
+ }
}
static INLINE boolean
@@ -474,8 +515,13 @@ pass_generate_phi_movs(struct nv_pc_pass *ctx, struct
nv_basic_block *b)
return 0;
}
+#define JOIN_MASK_PHI(1 0)
+#define JOIN_MASK_SELECT (1 1)
+#define JOIN_MASK_MOV(1 2)
+#define JOIN_MASK_BIND (1 3)
+
static int
-pass_join_values(struct nv_pc_pass *ctx, int iter)
+pass_join_values(struct nv_pc_pass *ctx, unsigned mask)
{
int c, n;
@@ -484,29 +530,28 @@ pass_join_values(struct nv_pc_pass *ctx, int iter)
switch (i-opcode) {
case NV_OP_PHI:
- if (iter != 2)
+ if (!(mask JOIN_MASK_PHI))
break;
for (c = 0; c 6 i-src[c]; ++c)
-try_join_values(ctx, i-def[0], i-src[c]-value);
+join_values_nofail(ctx, i-def[0], i-src[c]-value, FALSE);
break;
case NV_OP_MOV:
- if ((iter == 2) i-src[0]-value-insn
- !nv_is_vector_op(i-src[0]-value-join-insn-opcode))
+ if (!(mask JOIN_MASK_MOV))
+break;
+ if (i-src[0]-value-insn !i-src[0]-value-insn-def[1])
try_join_values(ctx, i-def[0], i-src[0]-value);
break;
case NV_OP_SELECT:
- if (iter != 1)
+ if (!(mask JOIN_MASK_SELECT))
break;
- for (c = 0; c 6 i-src[c]; ++c) {
-assert(join_allowed(ctx, i-def[0], i-src[c]-value));
-do_join_values(ctx, i-def[0], i-src[c]-value);
- }
+ for (c = 0; c 6 i-src[c]; ++c)
+join_values_nofail(ctx, i-def[0], i-src[c]-value, TRUE);
break;
case NV_OP_BIND:
- if (iter)
+ if (!(mask JOIN_MASK_BIND))
break;
for (c = 0; c 4 i-src[c]; ++c)
-do_join_values(ctx, i-def[c], i-src[c]-value);
+join_values_nofail(ctx, i-def[c], i-src[c]-value, TRUE);
break;
case NV_OP_TEX:
case NV_OP_TXB:
@@ -743,21 +788,6 @@ nvc0_ctor_register_set(struct nv_pc *pc, struct
register_set *set)
set-pc = pc;
}
-/* We allocate registers for all defs of a vector instruction at once.
- * Since we'll encounter all of them in the allocation loop,
Mesa (master): nvc0: kick out empty live ranges
Module: Mesa
Branch: master
Commit: f01748355360ac98c772ce8b82ca0e6c2f94629a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f01748355360ac98c772ce8b82ca0e6c2f94629a
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Tue Feb 22 21:50:17 2011 +0100
nvc0: kick out empty live ranges
They affect overlap tests even though they're actually empty.
---
src/gallium/drivers/nvc0/nvc0_pc_regalloc.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_pc_regalloc.c
b/src/gallium/drivers/nvc0/nvc0_pc_regalloc.c
index d721394..f4afe08 100644
--- a/src/gallium/drivers/nvc0/nvc0_pc_regalloc.c
+++ b/src/gallium/drivers/nvc0/nvc0_pc_regalloc.c
@@ -87,6 +87,9 @@ add_range_ex(struct nv_value *val, int bgn, int end, struct
nv_range *new_range)
{
struct nv_range *range, **nextp = val-livei;
+ if (bgn == end) /* [a, a) is invalid / empty */
+ return TRUE;
+
for (range = val-livei; range; range = range-next) {
if (end range-bgn)
break; /* insert before */
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Mesa (master): nvc0: presin and preex2 can load from const space
Module: Mesa
Branch: master
Commit: 96121399077787a9701c173dbb3ce0d1f30f00a9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=96121399077787a9701c173dbb3ce0d1f30f00a9
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Thu Feb 24 17:23:23 2011 +0100
nvc0: presin and preex2 can load from const space
---
src/gallium/drivers/nvc0/nvc0_pc_print.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_pc_print.c
b/src/gallium/drivers/nvc0/nvc0_pc_print.c
index 7840078..4088a55 100644
--- a/src/gallium/drivers/nvc0/nvc0_pc_print.c
+++ b/src/gallium/drivers/nvc0/nvc0_pc_print.c
@@ -353,8 +353,8 @@ struct nv_op_info nvc0_op_info_table[NV_OP_COUNT + 1] =
{ NV_OP_SIN, sin, NV_TYPE_F32, 0, 0, 0, 0, 1, 0, 0, 0 },
{ NV_OP_COS, cos, NV_TYPE_F32, 0, 0, 0, 0, 1, 0, 0, 0 },
{ NV_OP_EX2, ex2, NV_TYPE_F32, 0, 0, 0, 0, 1, 0, 0, 0 },
- { NV_OP_PRESIN, presin, NV_TYPE_F32, NV_MOD_SGN, 0, 0, 0, 1, 0, 0, 0 },
- { NV_OP_PREEX2, preex2, NV_TYPE_F32, NV_MOD_SGN, 0, 0, 0, 1, 0, 0, 0 },
+ { NV_OP_PRESIN, presin, NV_TYPE_F32, NV_MOD_SGN, 0, 0, 0, 1, 0, 0, 1 },
+ { NV_OP_PREEX2, preex2, NV_TYPE_F32, NV_MOD_SGN, 0, 0, 0, 1, 0, 0, 1 },
{ NV_OP_SAT, sat, NV_TYPE_F32, 0, 0, 0, 0, 1, 0, 0, 0 },
{ NV_OP_SET_F32_AND, and set, NV_TYPE_F32, 0, 0, 0, 0, 1, 0, 0, 0 },
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Mesa (master): nvc0: fix new_value calls using type instead of size
Module: Mesa
Branch: master
Commit: 9dd7d0803e5a881510d05a61908d6a7ffc04d16b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9dd7d0803e5a881510d05a61908d6a7ffc04d16b
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Thu Feb 24 15:28:04 2011 +0100
nvc0: fix new_value calls using type instead of size
---
src/gallium/drivers/nvc0/nvc0_pc_optimize.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_pc_optimize.c
b/src/gallium/drivers/nvc0/nvc0_pc_optimize.c
index 8d4d0f3..8b56aa4 100644
--- a/src/gallium/drivers/nvc0/nvc0_pc_optimize.c
+++ b/src/gallium/drivers/nvc0/nvc0_pc_optimize.c
@@ -592,7 +592,7 @@ constant_operand(struct nv_pc *pc,
} else
if (u.s32 0 u.s32 == (1 shift)) {
nvi-opcode = NV_OP_SHL;
- (val = new_value(pc, NV_FILE_IMM, NV_TYPE_U32))-reg.imm.s32 = shift;
+ (val = new_value(pc, NV_FILE_IMM, 4))-reg.imm.s32 = shift;
nv_reference(pc, nvi, 0, nvi-src[t]-value);
nv_reference(pc, nvi, 1, val);
break;
@@ -600,14 +600,14 @@ constant_operand(struct nv_pc *pc,
break;
case NV_OP_RCP:
u.f32 = 1.0f / u.f32;
- (val = new_value(pc, NV_FILE_IMM, NV_TYPE_F32))-reg.imm.f32 = u.f32;
+ (val = new_value(pc, NV_FILE_IMM, 4))-reg.imm.f32 = u.f32;
nvi-opcode = NV_OP_MOV;
assert(s == 0);
nv_reference(pc, nvi, 0, val);
break;
case NV_OP_RSQ:
u.f32 = 1.0f / sqrtf(u.f32);
- (val = new_value(pc, NV_FILE_IMM, NV_TYPE_F32))-reg.imm.f32 = u.f32;
+ (val = new_value(pc, NV_FILE_IMM, 4))-reg.imm.f32 = u.f32;
nvi-opcode = NV_OP_MOV;
assert(s == 0);
nv_reference(pc, nvi, 0, val);
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Mesa (master): nvc0: set local memory usage info in shader header
Module: Mesa
Branch: master
Commit: 1a8297139396ec2a6415ef803a3901e1ecef485c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a8297139396ec2a6415ef803a3901e1ecef485c
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Thu Feb 24 17:26:44 2011 +0100
nvc0: set local memory usage info in shader header
Before this, l[] access was a no-op.
---
src/gallium/drivers/nvc0/nvc0_context.h |1 +
src/gallium/drivers/nvc0/nvc0_program.c |9 -
src/gallium/drivers/nvc0/nvc0_program.h |1 +
src/gallium/drivers/nvc0/nvc0_screen.c |8 ++--
src/gallium/drivers/nvc0/nvc0_shader_state.c | 15 +++
src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c |3 +++
6 files changed, 34 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_context.h
b/src/gallium/drivers/nvc0/nvc0_context.h
index 3722f35..1ce5554 100644
--- a/src/gallium/drivers/nvc0/nvc0_context.h
+++ b/src/gallium/drivers/nvc0/nvc0_context.h
@@ -81,6 +81,7 @@ struct nvc0_context {
uint8_t num_vtxelts;
uint8_t num_textures[5];
uint8_t num_samplers[5];
+ uint8_t tls_required; /* bitmask of shader types using l[] */
uint16_t scissor;
uint32_t uniform_buffer_bound[5];
} state;
diff --git a/src/gallium/drivers/nvc0/nvc0_program.c
b/src/gallium/drivers/nvc0/nvc0_program.c
index f7ea97d..0685a84 100644
--- a/src/gallium/drivers/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nvc0/nvc0_program.c
@@ -301,9 +301,11 @@ prog_decl(struct nvc0_translation_info *ti,
ti-sysval_loc[i] = nvc0_system_value_location(sn, si,
ti-sysval_in[i]);
assert(first == last);
break;
+ case TGSI_FILE_TEMPORARY:
+ ti-temp128_nr = MAX2(ti-temp128_nr, last + 1);
+ break;
case TGSI_FILE_NULL:
case TGSI_FILE_CONSTANT:
- case TGSI_FILE_TEMPORARY:
case TGSI_FILE_SAMPLER:
case TGSI_FILE_ADDRESS:
case TGSI_FILE_IMMEDIATE:
@@ -644,6 +646,11 @@ nvc0_prog_scan(struct nvc0_translation_info *ti)
break;
}
+ if (ti-require_stores) {
+ prog-hdr[0] |= 1 26;
+ prog-hdr[1] |= ti-temp128_nr * 16; /* l[] size */
+ }
+
assert(!ret);
return ret;
}
diff --git a/src/gallium/drivers/nvc0/nvc0_program.h
b/src/gallium/drivers/nvc0/nvc0_program.h
index 3450cec..f6fea29 100644
--- a/src/gallium/drivers/nvc0/nvc0_program.h
+++ b/src/gallium/drivers/nvc0/nvc0_program.h
@@ -76,6 +76,7 @@ struct nvc0_translation_info {
uint32_t *immd32;
ubyte *immd32_ty;
unsigned immd32_nr;
+ unsigned temp128_nr;
ubyte edgeflag_out;
struct nvc0_subroutine *subr;
unsigned num_subrs;
diff --git a/src/gallium/drivers/nvc0/nvc0_screen.c
b/src/gallium/drivers/nvc0/nvc0_screen.c
index 321d86b..f7f1fd0 100644
--- a/src/gallium/drivers/nvc0/nvc0_screen.c
+++ b/src/gallium/drivers/nvc0/nvc0_screen.c
@@ -475,7 +475,7 @@ nvc0_screen_create(struct pipe_winsys *ws, struct
nouveau_device *dev)
OUT_RING (chan, (15 4) | 1);
}
- screen-tls_size = 4 * 4 * 32 * 128 * 4;
+ screen-tls_size = (16 * 32) * (NVC0_CAP_MAX_PROGRAM_TEMPS * 16);
ret = nouveau_bo_new(dev, NOUVEAU_BO_VRAM, 1 17,
screen-tls_size, screen-tls);
if (ret)
@@ -489,6 +489,8 @@ nvc0_screen_create(struct pipe_winsys *ws, struct
nouveau_device *dev)
OUT_RELOCl(chan, screen-tls, 0, NOUVEAU_BO_VRAM | NOUVEAU_BO_RDWR);
OUT_RING (chan, screen-tls_size 32);
OUT_RING (chan, screen-tls_size);
+ BEGIN_RING(chan, RING_3D_(0x07a0), 1);
+ OUT_RING (chan, 0);
BEGIN_RING(chan, RING_3D(LOCAL_BASE), 1);
OUT_RING (chan, 0);
@@ -642,8 +644,10 @@ nvc0_screen_make_buffers_resident(struct nvc0_screen
*screen)
nouveau_bo_validate(chan, screen-text, flags);
nouveau_bo_validate(chan, screen-uniforms, flags);
nouveau_bo_validate(chan, screen-txc, flags);
- nouveau_bo_validate(chan, screen-tls, flags);
nouveau_bo_validate(chan, screen-mp_stack_bo, flags);
+
+ if (screen-cur_ctx screen-cur_ctx-state.tls_required)
+ nouveau_bo_validate(chan, screen-tls, flags);
}
int
diff --git a/src/gallium/drivers/nvc0/nvc0_shader_state.c
b/src/gallium/drivers/nvc0/nvc0_shader_state.c
index 6336417..357f8b8 100644
--- a/src/gallium/drivers/nvc0/nvc0_shader_state.c
+++ b/src/gallium/drivers/nvc0/nvc0_shader_state.c
@@ -27,6 +27,16 @@
#include nvc0_context.h
+static INLINE void
+nvc0_program_update_context_state(struct nvc0_context *nvc0,
+ struct nvc0_program *prog, int stage)
+{
+ if (prog-hdr[1])
+ nvc0-state.tls_required |= 1 stage;
+ else
+ nvc0-state.tls_required = ~(1 stage);
+}
+
static boolean
nvc0_program_validate(struct nvc0_context *nvc0, struct nvc0_program *prog)
{
@@ -77,6 +87,7 @@ nvc0_vertprog_validate(struct nvc0_context *nvc0)
if (!nvc0_program_validate(nvc0, vp))
return;
+ nvc0_program_update_context_state(nvc0, vp, 0);
BEGIN_RING(chan, RING_3D(SP_SELECT(1)), 2);
Mesa (master): nvc0: sprite coord enable is per GENERIC, not overall index
Module: Mesa
Branch: master
Commit: b0bf4ee85f01e9cbe240e49e67a947d052daa3f3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0bf4ee85f01e9cbe240e49e67a947d052daa3f3
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Wed Feb 23 15:00:26 2011 +0100
nvc0: sprite coord enable is per GENERIC, not overall index
---
src/gallium/drivers/nvc0/nvc0_state_validate.c |8 +++-
1 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_state_validate.c
b/src/gallium/drivers/nvc0/nvc0_state_validate.c
index 0cc0a0c..70c418f 100644
--- a/src/gallium/drivers/nvc0/nvc0_state_validate.c
+++ b/src/gallium/drivers/nvc0/nvc0_state_validate.c
@@ -302,14 +302,12 @@ nvc0_validate_sprite_coords(struct nvc0_context *nvc0)
if (nvc0-rast-pipe.point_quad_rasterization) {
uint32_t en = nvc0-rast-pipe.sprite_coord_enable;
- int i;
- struct nvc0_program *prog = nvc0-fragprog;
while (en) {
- i = ffs(en) - 1;
+ int i = ffs(en) - 1;
en = ~(1 i);
- if (prog-fp.in_pos[i] = 0xc0 prog-fp.in_pos[i] 0xe0)
-reg |= 8 ((prog-fp.in_pos[i] - 0xc0) / 4);
+ if (i = 0 i 8)
+reg |= 8 i;
}
}
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Mesa (master): nvc0: change TGSI CMP translation to use slct
Module: Mesa
Branch: master
Commit: d0caaba370cb70f426180a46e5475bf8a05ac19b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d0caaba370cb70f426180a46e5475bf8a05ac19b
Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date: Wed Feb 23 17:29:02 2011 +0100
nvc0: change TGSI CMP translation to use slct
Saves us the explicit compare instruction needed with selp.
---
src/gallium/drivers/nvc0/nvc0_pc_optimize.c | 13 ++---
src/gallium/drivers/nvc0/nvc0_pc_print.c|6 +++---
src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c |4 ++--
3 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/nvc0/nvc0_pc_optimize.c
b/src/gallium/drivers/nvc0/nvc0_pc_optimize.c
index 8b56aa4..c5a7367 100644
--- a/src/gallium/drivers/nvc0/nvc0_pc_optimize.c
+++ b/src/gallium/drivers/nvc0/nvc0_pc_optimize.c
@@ -245,7 +245,9 @@ check_swap_src_0_1(struct nv_instruction *nvi)
struct nv_ref *src0 = nvi-src[0];
struct nv_ref *src1 = nvi-src[1];
- if (!nv_op_commutative(nvi-opcode) NV_BASEOP(nvi-opcode) != NV_OP_SET)
+ if (!nv_op_commutative(nvi-opcode)
+ NV_BASEOP(nvi-opcode) != NV_OP_SET
+ NV_BASEOP(nvi-opcode) != NV_OP_SLCT)
return;
assert(src0 src1 src0-value src1-value);
@@ -266,8 +268,13 @@ check_swap_src_0_1(struct nv_instruction *nvi)
}
}
- if (nvi-src[0] != src0 NV_BASEOP(nvi-opcode) == NV_OP_SET)
- nvi-set_cond = (nvi-set_cond ~7) | cc_swapped[nvi-set_cond 7];
+ if (nvi-src[0] != src0) {
+ if (NV_BASEOP(nvi-opcode) == NV_OP_SET)
+ nvi-set_cond = (nvi-set_cond ~7) | cc_swapped[nvi-set_cond 7];
+ else
+ if (NV_BASEOP(nvi-opcode) == NV_OP_SLCT)
+ nvi-set_cond = NV_CC_INVERSE(nvi-set_cond);
+ }
}
static void
diff --git a/src/gallium/drivers/nvc0/nvc0_pc_print.c
b/src/gallium/drivers/nvc0/nvc0_pc_print.c
index 4088a55..90c669c 100644
--- a/src/gallium/drivers/nvc0/nvc0_pc_print.c
+++ b/src/gallium/drivers/nvc0/nvc0_pc_print.c
@@ -363,9 +363,9 @@ struct nv_op_info nvc0_op_info_table[NV_OP_COUNT + 1] =
{ NV_OP_SELP, selp, NV_TYPE_U32, 0, 0, 0, 0, 1, 0, 0, 0 },
- { NV_OP_SLCT_F32, slct, NV_TYPE_F32, 0, 0, 0, 0, 1, 0, 0, 0 },
- { NV_OP_SLCT_F32, slct, NV_TYPE_S32, 0, 0, 0, 0, 1, 0, 0, 0 },
- { NV_OP_SLCT_F32, slct, NV_TYPE_U32, 0, 0, 0, 0, 1, 0, 0, 0 },
+ { NV_OP_SLCT, slct, NV_TYPE_F32, 0, 0, 0, 0, 1, 0, 2, 2 },
+ { NV_OP_SLCT, slct, NV_TYPE_S32, 0, 0, 0, 0, 1, 0, 2, 2 },
+ { NV_OP_SLCT, slct, NV_TYPE_U32, 0, 0, 0, 0, 1, 0, 2, 2 },
{ NV_OP_ADD, sub, NV_TYPE_F32, 0, 0, 0, 0, 1, 0, 1, 0 },
diff --git a/src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c
b/src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c
index f7dff59..a44d330 100644
--- a/src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c
+++ b/src/gallium/drivers/nvc0/nvc0_tgsi_to_nc.c
@@ -1493,10 +1493,10 @@ bld_instruction(struct bld_context *bld,
case TGSI_OPCODE_CMP:
FOR_EACH_DST0_ENABLED_CHANNEL(c, insn) {
src0 = emit_fetch(bld, insn, 0, c);
- src0 = bld_setp(bld, NV_OP_SET_F32, NV_CC_LT, src0, bld-zero);
src1 = emit_fetch(bld, insn, 1, c);
src2 = emit_fetch(bld, insn, 2, c);
- dst0[c] = bld_insn_3(bld, NV_OP_SELP, src1, src2, src0);
+ dst0[c] = bld_insn_3(bld, NV_OP_SLCT_F32, src1, src2, src0);
+ dst0[c]-insn-set_cond = NV_CC_LT;
}
break;
case TGSI_OPCODE_COS:
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Mesa (master): nvc0: fix PointCoord enable in FP header
Module: Mesa Branch: master Commit: 11b9f4439c56045a8f718e483844135dd9fbcb58 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=11b9f4439c56045a8f718e483844135dd9fbcb58 Author: Christoph Bumiller e0425...@student.tuwien.ac.at Date: Wed Feb 23 14:54:25 2011 +0100 nvc0: fix PointCoord enable in FP header --- src/gallium/drivers/nvc0/nvc0_program.c |7 +-- 1 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nvc0/nvc0_program.c b/src/gallium/drivers/nvc0/nvc0_program.c index 0685a84..899fe14 100644 --- a/src/gallium/drivers/nvc0/nvc0_program.c +++ b/src/gallium/drivers/nvc0/nvc0_program.c @@ -535,8 +535,11 @@ nvc0_fp_gen_header(struct nvc0_program *fp, struct nvc0_translation_info *ti) a = ti-input_loc[i][c] / 2; if (ti-input_loc[i][c] = 0x2c0) a -= 32; - if ((a ~7) == 0x70/2) -fp-hdr[5] |= 1 (28 + (a 7) / 2); /* FRAG_COORD_UMASK */ + if (ti-input_loc[i][0] == 0x70) +fp-hdr[5] |= 1 (28 + c); /* FRAG_COORD_UMASK */ + else + if (ti-input_loc[i][0] == 0x2e0) +fp-hdr[14] |= 1 (24 + c); /* POINT_COORD */ else fp-hdr[4 + a / 32] |= m (a % 32); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Try using glCopyTexSubImage2D in _mesa_meta_BlitFramebuffer
Module: Mesa
Branch: master
Commit: c0ad70ae31ee5501281b434d56e389fc92b13a3a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0ad70ae31ee5501281b434d56e389fc92b13a3a
Author: Neil Roberts n...@linux.intel.com
Date: Sat Feb 5 10:21:11 2011 +
intel: Try using glCopyTexSubImage2D in _mesa_meta_BlitFramebuffer
In the case where glBlitFramebuffer is being used to copy to a texture
without scaling it is faster if we can use the hardware to do a blit
rather than having to do a texture render. In most of the drivers
glCopyTexSubImage2D will use a blit so this patch makes it check for
when glBlitFramebuffer is doing a simple copy and then divert to
glCopyTexSubImage2D.
This was originally proposed as an extension to the common meta-ops.
However, it was rejected as using the BLT is only advantageous for Intel
hardware.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33934
Signed-off-by: Chris Wilson ch...@chris-wilson.co.uk
---
src/mesa/drivers/dri/intel/intel_fbo.c | 81 ++-
src/mesa/drivers/dri/intel/intel_tex.h |8 +++
src/mesa/drivers/dri/intel/intel_tex_copy.c | 41 +++---
3 files changed, 108 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index 886b25c..8b57eb1 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -34,6 +34,7 @@
#include main/framebuffer.h
#include main/renderbuffer.h
#include main/context.h
+#include main/teximage.h
#include main/texrender.h
#include drivers/common/meta.h
@@ -647,6 +648,84 @@ intel_validate_framebuffer(struct gl_context *ctx, struct
gl_framebuffer *fb)
}
}
+/**
+ * Try to do a glBlitFramebuffer using glCopyTexSubImage2D
+ * We can do this when the dst renderbuffer is actually a texture and
+ * there is no scaling, mirroring or scissoring.
+ *
+ * \return new buffer mask indicating the buffers left to blit using the
+ * normal path.
+ */
+static GLbitfield
+intel_blit_framebuffer_copy_tex_sub_image(struct gl_context *ctx,
+ GLint srcX0, GLint srcY0,
+ GLint srcX1, GLint srcY1,
+ GLint dstX0, GLint dstY0,
+ GLint dstX1, GLint dstY1,
+ GLbitfield mask, GLenum filter)
+{
+ if (mask GL_COLOR_BUFFER_BIT) {
+ const struct gl_framebuffer *drawFb = ctx-DrawBuffer;
+ const struct gl_framebuffer *readFb = ctx-ReadBuffer;
+ const struct gl_renderbuffer_attachment *drawAtt =
+ drawFb-Attachment[drawFb-_ColorDrawBufferIndexes[0]];
+
+ /* If the source and destination are the same size with no
+ mirroring, the rectangles are within the size of the
+ texture and there is no scissor then we can use
+ glCopyTexSubimage2D to implement the blit. This will end
+ up as a fast hardware blit on some drivers */
+ if (drawAtt drawAtt-Texture
+ srcX0 - srcX1 == dstX0 - dstX1
+ srcY0 - srcY1 == dstY0 - dstY1
+ srcX1 = srcX0
+ srcY1 = srcY0
+ srcX0 = 0 srcX1 = readFb-Width
+ srcY0 = 0 srcY1 = readFb-Height
+ dstX0 = 0 dstX1 = drawFb-Width
+ dstY0 = 0 dstY1 = drawFb-Height
+ !ctx-Scissor.Enabled) {
+ const struct gl_texture_object *texObj = drawAtt-Texture;
+ const GLuint dstLevel = drawAtt-TextureLevel;
+ const GLenum target = texObj-Target;
+
+ struct gl_texture_image *texImage =
+_mesa_select_tex_image(ctx, texObj, target, dstLevel);
+ GLenum internalFormat = texImage-InternalFormat;
+
+ if (intel_copy_texsubimage(intel_context(ctx), target,
+intel_texture_image(texImage),
+internalFormat,
+dstX0, dstY0,
+srcX0, srcY0,
+srcX1 - srcX0, /* width */
+srcY1 - srcY0))
+mask = ~GL_COLOR_BUFFER_BIT;
+ }
+ }
+
+ return mask;
+}
+
+static void
+intel_blit_framebuffer(struct gl_context *ctx,
+ GLint srcX0, GLint srcY0, GLint srcX1, GLint srcY1,
+ GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
+ GLbitfield mask, GLenum filter)
+{
+ /* Try faster, glCopyTexSubImage2D approach first which uses the BLT. */
+ mask = intel_blit_framebuffer_copy_tex_sub_image(ctx,
+srcX0, srcY0, srcX1, srcY1,
+dstX0, dstY0, dstX1, dstY1,
+mask, filter);
+ if (mask == 0x0)
+ return;
+
+ _mesa_meta_BlitFramebuffer(ctx,
+
Mesa (master): i965: Increase Sandybridge point size clamp in the clip state.
Module: Mesa Branch: master Commit: e6e5c1f46d374015d924522ed0b2bf2443c3e6d4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6e5c1f46d374015d924522ed0b2bf2443c3e6d4 Author: Kenneth Graunke kenn...@whitecape.org Date: Thu Feb 24 11:17:02 2011 -0800 i965: Increase Sandybridge point size clamp in the clip state. 255.875 matches the hardware documentation. Presumably this was a typo. NOTE: This is a candidate for the 7.10 branch, along with commit 2bfc23fb86964e4153f57f2a56248760f6066033. Reviewed-by: Eric Anholt e...@anholt.net --- src/mesa/drivers/dri/i965/gen6_clip_state.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_clip_state.c b/src/mesa/drivers/dri/i965/gen6_clip_state.c index 38c98f3..d6c1f1c 100644 --- a/src/mesa/drivers/dri/i965/gen6_clip_state.c +++ b/src/mesa/drivers/dri/i965/gen6_clip_state.c @@ -68,7 +68,7 @@ upload_clip_state(struct brw_context *brw) depth_clamp | provoking); OUT_BATCH(U_FIXED(0.125, 3) GEN6_CLIP_MIN_POINT_WIDTH_SHIFT | - U_FIXED(225.875, 3) GEN6_CLIP_MAX_POINT_WIDTH_SHIFT | + U_FIXED(255.875, 3) GEN6_CLIP_MAX_POINT_WIDTH_SHIFT | GEN6_CLIP_FORCE_ZERO_RTAINDEX); ADVANCE_BATCH(); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r300g: explicit sign bits on RGTC textures
Module: Mesa
Branch: master
Commit: 79ad6f5375253faff89bbc7eb6dc5949ba63e0ef
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=79ad6f5375253faff89bbc7eb6dc5949ba63e0ef
Author: Dave Airlie airl...@redhat.com
Date: Fri Feb 25 09:14:53 2011 +1000
r300g: explicit sign bits on RGTC textures
---
src/gallium/drivers/r300/r300_texture.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r300/r300_texture.c
b/src/gallium/drivers/r300/r300_texture.c
index 354144c..2db5ab9 100644
--- a/src/gallium/drivers/r300/r300_texture.c
+++ b/src/gallium/drivers/r300/r300_texture.c
@@ -214,11 +214,13 @@ uint32_t r300_translate_texformat(enum pipe_format format,
/* RGTC formats. */
if (desc-layout == UTIL_FORMAT_LAYOUT_RGTC) {
switch (format) {
-case PIPE_FORMAT_RGTC1_UNORM:
case PIPE_FORMAT_RGTC1_SNORM:
+result |= sign_bit[0];
+case PIPE_FORMAT_RGTC1_UNORM:
return R500_TX_FORMAT_ATI1N | result;
-case PIPE_FORMAT_RGTC2_UNORM:
case PIPE_FORMAT_RGTC2_SNORM:
+result |= sign_bit[0] | sign_bit[1];
+case PIPE_FORMAT_RGTC2_UNORM:
return R400_TX_FORMAT_ATI2N | result;
default:
return ~0; /* Unsupported/unknown. */
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Mesa (master): r600g: bc 4/5 or rgtc textures need to be tiled as well.
Module: Mesa
Branch: master
Commit: c9bca01819ef0fa3c64a28e26bd63953cf7f1364
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c9bca01819ef0fa3c64a28e26bd63953cf7f1364
Author: Dave Airlie airl...@redhat.com
Date: Thu Feb 24 13:55:25 2011 +1000
r600g: bc 4/5 or rgtc textures need to be tiled as well.
Make the s3tc upload code more generic.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/r600/r600_blit.c| 16
src/gallium/drivers/r600/r600_texture.c |4 ++--
2 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_blit.c
b/src/gallium/drivers/r600/r600_blit.c
index 9865ea1..04408a5 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -225,7 +225,7 @@ struct texture_orig_info {
unsigned height0;
};
-static void r600_s3tc_to_blittable(struct pipe_resource *tex,
+static void r600_compressed_to_blittable(struct pipe_resource *tex,
unsigned level,
struct texture_orig_info *orig)
{
@@ -253,7 +253,7 @@ static void r600_s3tc_to_blittable(struct pipe_resource
*tex,
}
-static void r600_reset_blittable_to_s3tc(struct pipe_resource *tex,
+static void r600_reset_blittable_to_compressed(struct pipe_resource *tex,
unsigned level,
struct texture_orig_info *orig)
{
@@ -282,13 +282,13 @@ static void r600_resource_copy_region(struct pipe_context
*ctx,
restore_orig[0] = restore_orig[1] = FALSE;
- if (util_format_is_s3tc(src-format)) {
- r600_s3tc_to_blittable(src, src_level, orig_info[0]);
+ if (util_format_is_compressed(src-format)) {
+ r600_compressed_to_blittable(src, src_level, orig_info[0]);
restore_orig[0] = TRUE;
}
- if (util_format_is_s3tc(dst-format)) {
- r600_s3tc_to_blittable(dst, dst_level, orig_info[1]);
+ if (util_format_is_compressed(dst-format)) {
+ r600_compressed_to_blittable(dst, dst_level, orig_info[1]);
restore_orig[1] = TRUE;
/* translate the dst box as well */
dstx = util_format_get_nblocksx(orig_info[1].format, dstx);
@@ -299,10 +299,10 @@ static void r600_resource_copy_region(struct pipe_context
*ctx,
src, src_level, src_box);
if (restore_orig[0])
- r600_reset_blittable_to_s3tc(src, src_level, orig_info[0]);
+ r600_reset_blittable_to_compressed(src, src_level,
orig_info[0]);
if (restore_orig[1])
- r600_reset_blittable_to_s3tc(dst, dst_level, orig_info[1]);
+ r600_reset_blittable_to_compressed(dst, dst_level,
orig_info[1]);
}
void r600_init_blit_functions(struct r600_pipe_context *rctx)
diff --git a/src/gallium/drivers/r600/r600_texture.c
b/src/gallium/drivers/r600/r600_texture.c
index 095558d..87143ee 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -292,7 +292,7 @@ static boolean permit_hardware_blit(struct pipe_screen
*screen,
bind = PIPE_BIND_RENDER_TARGET;
/* hackaround for S3TC */
- if (util_format_is_s3tc(res-format))
+ if (util_format_is_compressed(res-format))
return TRUE;
if (!screen-is_format_supported(screen,
@@ -424,7 +424,7 @@ struct pipe_resource *r600_texture_create(struct
pipe_screen *screen,
}
if (!(templ-flags R600_RESOURCE_FLAG_TRANSFER)
- util_format_is_s3tc(templ-format))
+ util_format_is_compressed(templ-format))
array_mode = V_038000_ARRAY_1D_TILED_THIN1;
return (struct pipe_resource *)r600_texture_create_object(screen,
templ, array_mode,
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Mesa (master): r600g: explicity set sign bits for RGTC
Module: Mesa
Branch: master
Commit: b2413de91682e3908d8ab1635956a290f603681c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b2413de91682e3908d8ab1635956a290f603681c
Author: Dave Airlie airl...@redhat.com
Date: Fri Feb 25 09:13:14 2011 +1000
r600g: explicity set sign bits for RGTC
---
src/gallium/drivers/r600/r600_texture.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_texture.c
b/src/gallium/drivers/r600/r600_texture.c
index 87143ee..3a85a25 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -878,12 +878,14 @@ uint32_t r600_translate_texformat(enum pipe_format format,
goto out_unknown;
switch (format) {
- case PIPE_FORMAT_RGTC1_UNORM:
case PIPE_FORMAT_RGTC1_SNORM:
+ word4 |= sign_bit[0];
+ case PIPE_FORMAT_RGTC1_UNORM:
result = FMT_BC4;
goto out_word4;
- case PIPE_FORMAT_RGTC2_UNORM:
case PIPE_FORMAT_RGTC2_SNORM:
+ word4 |= sign_bit[0] | sign_bit[1];
+ case PIPE_FORMAT_RGTC2_UNORM:
result = FMT_BC5;
goto out_word4;
default:
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Mesa (master): scons: Reduce all Cygwin platform names to 'cygwin'.
Module: Mesa
Branch: master
Commit: eb1780238621c7be0342d9129eb639e4892c004d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb1780238621c7be0342d9129eb639e4892c004d
Author: Vinson Lee v...@vmware.com
Date: Thu Feb 24 19:49:37 2011 -0800
scons: Reduce all Cygwin platform names to 'cygwin'.
platform.system in SCons on Cygwin includes the OS version number.
Windows XP - CYGWIN_NT-5.1
Windows Vista - CYGWIN_NT-6.0
Windows 7 - CYGWIN_NT-6.1
Reduce all Cygwin platform variants to just 'cygwin' so anything
downstream can simply use 'cygwin' instead of the different full
platform names.
---
common.py |4 +++-
scons/gallium.py |2 ++
src/gallium/winsys/sw/xlib/SConscript |2 +-
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/common.py b/common.py
index b44f20e..1d0c6a7 100644
--- a/common.py
+++ b/common.py
@@ -15,6 +15,8 @@ import SCons.Script.SConscript
# Defaults
host_platform = _platform.system().lower()
+if host_platform.startswith('cygwin'):
+host_platform = 'cygwin'
# Search sys.argv[] for a platform=foo argument since we don't have
# an 'env' variable at this point.
@@ -81,7 +83,7 @@ def AddOptions(opts):
opts.Add(EnumOption('machine', 'use machine-specific assembly code',
default_machine,
allowed_values=('generic', 'ppc', 'x86', 'x86_64')))
opts.Add(EnumOption('platform', 'target platform', host_platform,
-
allowed_values=('linux', 'cell', 'windows', 'winddk', 'wince',
'darwin', 'embedded', 'cygwin_nt-5.1', 'cygwin_nt-6.1', 'sunos5', 'freebsd8')))
+
allowed_values=('linux', 'cell', 'windows', 'winddk', 'wince',
'darwin', 'embedded', 'cygwin', 'sunos5', 'freebsd8')))
opts.Add('toolchain', 'compiler toolchain', default_toolchain)
opts.Add(BoolOption('gles', 'EXPERIMENTAL: enable OpenGL ES support',
'no'))
opts.Add(BoolOption('llvm', 'use LLVM', default_llvm))
diff --git a/scons/gallium.py b/scons/gallium.py
index 9118257..112f6c8 100755
--- a/scons/gallium.py
+++ b/scons/gallium.py
@@ -195,6 +195,8 @@ def generate(env):
# Determine whether we are cross compiling; in particular, whether we need
# to compile code generators with a different compiler as the target code.
host_platform = _platform.system().lower()
+if host_platform.startswith('cygwin'):
+host_platform = 'cygwin'
host_machine = os.environ.get('PROCESSOR_ARCHITEW6432',
os.environ.get('PROCESSOR_ARCHITECTURE', _platform.machine()))
host_machine = {
'x86': 'x86',
diff --git a/src/gallium/winsys/sw/xlib/SConscript
b/src/gallium/winsys/sw/xlib/SConscript
index f6c4741..df01a9e 100644
--- a/src/gallium/winsys/sw/xlib/SConscript
+++ b/src/gallium/winsys/sw/xlib/SConscript
@@ -4,7 +4,7 @@
Import('*')
-if env['platform'] in ('cygwin_nt-5.1', 'cygwin_nt-6.1', 'linux'):
+if env['platform'] in ('cygwin', 'linux'):
env = env.Clone()
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Mesa (master): gallium/util: add 1d/2d mipmap generation support
Module: Mesa
Branch: master
Commit: 179ff0551c4938e59f4b57fec0a10d63f012d7c6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=179ff0551c4938e59f4b57fec0a10d63f012d7c6
Author: Dave Airlie airl...@redhat.com
Date: Fri Feb 25 14:37:06 2011 +1000
gallium/util: add 1d/2d mipmap generation support
so far only hw mipmap generation is testing on softpipe,
passes test added to piglit.
this requires another patch to mesa to let array textures mipmaps
even start to happen.
---
src/gallium/auxiliary/util/u_gen_mipmap.c | 43 +
1 files changed, 37 insertions(+), 6 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_gen_mipmap.c
b/src/gallium/auxiliary/util/u_gen_mipmap.c
index 3b6342a..3698be7 100644
--- a/src/gallium/auxiliary/util/u_gen_mipmap.c
+++ b/src/gallium/auxiliary/util/u_gen_mipmap.c
@@ -67,7 +67,7 @@ struct gen_mipmap_state
struct pipe_vertex_element velem[2];
void *vs;
- void *fs1d, *fs2d, *fs3d, *fsCube;
+ void *fs1d, *fs2d, *fs3d, *fsCube, *fs1da, *fs2da;
struct pipe_resource *vbuf; /** quad vertices */
unsigned vbuf_slot;
@@ -1321,6 +1321,11 @@ util_create_gen_mipmap(struct pipe_context *pipe,
TGSI_INTERPOLATE_LINEAR);
ctx-fsCube = util_make_fragment_tex_shader(pipe, TGSI_TEXTURE_CUBE,
TGSI_INTERPOLATE_LINEAR);
+ ctx-fs1da = util_make_fragment_tex_shader(pipe, TGSI_TEXTURE_1D_ARRAY,
+ TGSI_INTERPOLATE_LINEAR);
+ ctx-fs2da = util_make_fragment_tex_shader(pipe, TGSI_TEXTURE_2D_ARRAY,
+ TGSI_INTERPOLATE_LINEAR);
+
/* vertex data that doesn't change */
for (i = 0; i 4; i++) {
@@ -1390,8 +1395,25 @@ set_vertex_data(struct gen_mipmap_state *ctx,
util_map_texcoords2d_onto_cubemap(layer, st[0][0], 2,
ctx-vertices[0][1][0], 8);
}
- else {
- /* 1D/2D/3D */
+ else if (tex_target == PIPE_TEXTURE_1D_ARRAY) {
+ /* 1D texture array */
+ ctx-vertices[0][1][0] = 0.0f; /*s*/
+ ctx-vertices[0][1][1] = r; /*t*/
+ ctx-vertices[0][1][2] = 0.0f;/*r*/
+
+ ctx-vertices[1][1][0] = 1.0f;
+ ctx-vertices[1][1][1] = r;
+ ctx-vertices[1][1][2] = 0.0f;
+
+ ctx-vertices[2][1][0] = 1.0f;
+ ctx-vertices[2][1][1] = r;
+ ctx-vertices[2][1][2] = 0.0f;
+
+ ctx-vertices[3][1][0] = 0.0f;
+ ctx-vertices[3][1][1] = r;
+ ctx-vertices[3][1][2] = 0.0f;
+ } else {
+ /* 1D/2D/3D/2D array */
ctx-vertices[0][1][0] = 0.0f; /*s*/
ctx-vertices[0][1][1] = 0.0f; /*t*/
ctx-vertices[0][1][2] = r;/*r*/
@@ -1427,6 +1449,8 @@ util_destroy_gen_mipmap(struct gen_mipmap_state *ctx)
{
struct pipe_context *pipe = ctx-pipe;
+ pipe-delete_fs_state(pipe, ctx-fs2da);
+ pipe-delete_fs_state(pipe, ctx-fs1da);
pipe-delete_fs_state(pipe, ctx-fsCube);
pipe-delete_fs_state(pipe, ctx-fs3d);
pipe-delete_fs_state(pipe, ctx-fs2d);
@@ -1499,7 +1523,11 @@ util_gen_mipmap(struct gen_mipmap_state *ctx,
fs = ctx-fsCube;
break;
case PIPE_TEXTURE_1D_ARRAY:
+ fs = ctx-fs1da;
+ break;
case PIPE_TEXTURE_2D_ARRAY:
+ fs = ctx-fs2da;
+ break;
default:
assert(0);
fs = ctx-fs2d;
@@ -1555,6 +1583,8 @@ util_gen_mipmap(struct gen_mipmap_state *ctx,
if (pt-target == PIPE_TEXTURE_3D)
nr_layers = u_minify(pt-depth0, dstLevel);
+ else if (pt-target == PIPE_TEXTURE_2D_ARRAY || pt-target ==
PIPE_TEXTURE_1D_ARRAY)
+nr_layers = pt-array_size;
else
nr_layers = 1;
@@ -1564,11 +1594,12 @@ util_gen_mipmap(struct gen_mipmap_state *ctx,
/* in theory with geom shaders and driver with full layer support
could do that in one go. */
layer = i;
-offset = 1.0f / (float)(nr_layers * 2);
/* XXX hmm really? */
rcoord = (float)layer / (float)nr_layers + 1.0f /
(float)(nr_layers * 2);
- }
- else
+ } else if (pt-target == PIPE_TEXTURE_2D_ARRAY || pt-target ==
PIPE_TEXTURE_1D_ARRAY) {
+ layer = i;
+ rcoord = (float)layer;
+} else
layer = face;
memset(surf_templ, 0, sizeof(surf_templ));
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