Mesa (8.0): 42 new commits
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=869c34527a51c2797effd4ba1169dcb57d4bbffd Author: Anuj Phogat Date: Mon Feb 27 11:09:29 2012 -0800 intel: Fix a case when mapping large texture fails This is a squash of: intel: Fix a case when mapping large texture fails This patch handles a case when mapping a large texture fails in drm_intel_gem_bo_map_gtt(). These changes avoid assertion failure later in the driver as reported in following bugs: https://bugs.freedesktop.org/show_bug.cgi?id=44970 https://bugs.freedesktop.org/show_bug.cgi?id=46303 Testing: No regressions in piglit quick.tests Signed-off-by: Anuj Phogat (cherry picked from commit cdcfd5d1d60179e60e3a0a47dda71bfe91083105) and: intel: fix un-blanced map_refcount issue This is a regression introduced by commit cdcfd5, which forget to increase the map_refcount for successfully-mapped region. Thus caused a wrong non-blanced map_refcount. This would fix the regression found in the two following webglc testcase on Pineview platform: texture-npot.html gl-max-texture-dimensions.html Cc: Anuj Phogat Signed-off-by: Yuanhan Liu Reviewed-by: Anuj Phogat (cherry picked from commit 9cb777eb71dde895ca0ad3454a9b44252e9b402e) URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e7f09910897cad2c07d5009c334c42e6bb56723 Author: Anuj Phogat Date: Mon Mar 12 10:39:48 2012 -0700 mesa: Fix the cause of piglit test fbo-array failure Handle the special case of glFramebufferTextureLayer() for which we pass teximage = 0 internally in framebuffer_texture(). This patch makes failing piglit test fbo-array, fbo-depth-array to pass. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=47126 V4: Removed the duplicated code. Note: This is a candidate for the stable branches. Signed-off-by: Anuj Phogat Reviewed-by: Brian Paul (cherry picked from commit cc5b0ffae048824a6bdcaf43e0c8c2dd4a7ff14b) URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc2413c889c40225ef705f6762ee1e389744f879 Author: Kenneth Graunke Date: Thu Mar 8 11:06:42 2012 -0800 drirc: Add force_glsl_extensions_warn workaround for Unigine Heaven. Unfortunately, Unigine Heaven 3.0 still needs this. NOTE: This is a candidate for the 8.0 branch. Signed-off-by: Kenneth Graunke Reviewed-by: Eric Anholt (cherry picked from commit 60218b604ae3422983dd1cd24f5d913e18f73ac0) URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1ebdf48dcbad59859ea0f98ce53a51f44b24 Author: Anuj Phogat Date: Fri Mar 2 12:00:51 2012 -0800 mesa: Fix valid texture target test in _mesa_GetTexLevelParameteriv() _mesa_max_texture_levels() is also used to test valid texture target in _mesa_GetTexLevelParameteriv(). GL_TEXTURE_CUBE_MAP is not allowed as texture target in glGetTexLevelParameter(). So, this should throw GL_INVALID_ENUM error. Few other functions which use _mesa_max_texture_levels() like getcompressedteximage_error_check() and getteximage_error_check() also don't accept GL_TEXTURE_CUBE_MAP. Above fix makes piglit fbo-cubemap test to fail. This is because of incorrect texture target passed to _mesa_max_texture_levels() in framebuffer_texture(). Fixing that as well Note: This is a candidate for the stable branches Signed-off-by: Anuj Phogat Reviewed-by: Brian Paul (cherry picked from commit a9523af0e88017d683c19ff238bfc5eb7cb88fd0) URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a3f6e8f4316d78caed3cfffdb63c157d0e1fa987 Author: Kurt Roeckx Date: Fri Mar 2 17:31:23 2012 -0800 i915: Fix i830 polygon stipple from PBOs. This is a direct port of the i915 patch in a856da63247a4b403f6350914f732e14d1530ed1. Fixes glean's pbo test. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41372 Reviewed-by: Eric Anholt NOTE: This is a candidate for release branches. (cherry picked from commit 489ac8e73a2432d29597a62cd83f09b9d1848533) URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5696077656299d8617d4e71efcc5f8b0632a969c Author: Kurt Roeckx Date: Fri Mar 2 15:34:45 2012 -0800 i915: Compute maximum number of verts using the actual batchbuffer size. We were looking at the size of batch.map for how big the batchbuffer was, but on 865 we just use a single-page batchbuffer due to hardware limits. v2: Removed check for sizeof map < bo->size, since that's always false. [change by anholt] NOTE: This is a candidate for release branches. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=41495 (cherry picked from commit 024ece7523f1735d2fca0067c0a3bdcf53fde8f9
Mesa (master): gallium/tgsi/text: Ensure ret is initialized in parse_immediate_data.
Module: Mesa
Branch: master
Commit: e8a86d36f3b007ae6fca9353a3a4cda1456ae1d4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e8a86d36f3b007ae6fca9353a3a4cda1456ae1d4
Author: Vinson Lee
Date: Wed May 16 23:44:53 2012 -0700
gallium/tgsi/text: Ensure ret is initialized in parse_immediate_data.
Fix uninitialized scalar variable defect reported by Coverity.
Signed-off-by: Vinson Lee
Reviewed-by: Brian Paul
---
src/gallium/auxiliary/tgsi/tgsi_text.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_text.c
b/src/gallium/auxiliary/tgsi/tgsi_text.c
index 279a046..f2bf49e 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_text.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_text.c
@@ -1007,6 +1007,10 @@ static boolean parse_immediate_data(struct translate_ctx
*ctx, unsigned type,
case TGSI_IMM_INT32:
ret = parse_int(&ctx->cur, &values[i].Int);
break;
+ default:
+ assert(0);
+ ret = FALSE;
+ break;
}
if (!ret) {
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Mesa (master): radeon/llvm: Add DAG nodes for MIN instructions
Module: Mesa
Branch: master
Commit: 7e3cd8df183448e2cc01a8f2645a001b0972f4ab
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e3cd8df183448e2cc01a8f2645a001b0972f4ab
Author: Tom Stellard
Date: Thu May 17 18:21:24 2012 -0400
radeon/llvm: Add DAG nodes for MIN instructions
Also, remove the AMDIL MIN* instruction defs.
---
src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl |2 +-
src/gallium/drivers/radeon/AMDGPUISelLowering.cpp | 12
src/gallium/drivers/radeon/AMDGPUISelLowering.h |3 +++
src/gallium/drivers/radeon/AMDGPUInstrInfo.td | 15 +++
src/gallium/drivers/radeon/AMDILInstructions.td |6 --
src/gallium/drivers/radeon/R600Instructions.td| 14 +++---
6 files changed, 38 insertions(+), 14 deletions(-)
diff --git a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
index 52b79bd..2b83273 100644
--- a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
+++ b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
@@ -55,7 +55,7 @@ my $FILE_TYPE = $ARGV[0];
open AMDIL, '<', 'AMDILInstructions.td';
-my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32',
'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'BINARY_OR_i32',
'BINARY_NOT_i32', 'MIN_f32');
+my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32',
'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'BINARY_OR_i32',
'BINARY_NOT_i32');
while () {
if ($_ =~ /defm\s+([A-Z_]+)\s+:\s+([A-Za-z0-9]+);
+
+// out = min(a, b) a and b are floats
+def AMDGPUfmin : SDNode<"AMDGPUISD::FMIN", SDTFPBinOp,
+ [SDNPCommutative, SDNPAssociative]
+>;
+
+// out = min(a, b) a snd b are signed ints
+def AMDGPUsmin : SDNode<"AMDGPUISD::SMIN", SDTIntBinOp,
+ [SDNPCommutative, SDNPAssociative]
+>;
+
+// out = min(a, b) a and b are unsigned ints
+def AMDGPUumin : SDNode<"AMDGPUISD::UMIN", SDTIntBinOp,
+ [SDNPCommutative, SDNPAssociative]
+>;
diff --git a/src/gallium/drivers/radeon/AMDILInstructions.td
b/src/gallium/drivers/radeon/AMDILInstructions.td
index 629a2c0..8f22d66 100644
--- a/src/gallium/drivers/radeon/AMDILInstructions.td
+++ b/src/gallium/drivers/radeon/AMDILInstructions.td
@@ -102,7 +102,6 @@ defm IMAD24 : TernaryIntrinsicInt;
}
defm CARRY : BinaryIntrinsicInt;
defm BORROW : BinaryIntrinsicInt;
-defm IMIN : BinaryIntrinsicInt;
defm IMAX : BinaryIntrinsicInt;
defm IBIT_EXTRACT : TernaryIntrinsicInt;
@@ -137,7 +136,6 @@ defm UBIT_REVERSE : UnaryIntrinsicInt;
defm UMULHI24 : BinaryIntrinsicInt;
defm UMUL24 : BinaryIntrinsicInt;
-defm UMIN : BinaryIntrinsicInt;
defm UMAX : BinaryIntrinsicInt;
defm UBIT_EXTRACT : TernaryIntrinsicInt;
@@ -169,8 +167,6 @@ def LADD: TwoInOneOut;
-defm IMIN64 : BinaryIntrinsicLong;
-defm UMIN64 : BinaryIntrinsicLong;
defm IMAX64 : BinaryIntrinsicLong;
defm UMAX64 : BinaryIntrinsicLong;
}
@@ -250,7 +246,6 @@ defm POW : BinaryIntrinsicFloat;
let hasIEEEFlag = 1 in {
let mayLoad = 0, mayStore=0 in {
-defm MIN : BinaryIntrinsicFloat;
}
defm MOD : BinaryOpMCf32;
}
@@ -367,7 +362,6 @@ def NEG_v2f64 : OneInOneOut;
let mayLoad = 0, mayStore=0 in {
-defm MIN : BinaryIntrinsicDouble;
defm MAX : BinaryIntrinsicDouble;
defm DIV : BinaryIntrinsicDouble;
defm MAD : TernaryIntrinsicDouble;
diff --git a/src/gallium/drivers/radeon/R600Instructions.td
b/src/gallium/drivers/radeon/R600Instructions.td
index 459010c..a42d917 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -265,9 +265,8 @@ def MAX : R600_2OP <
def MIN : R600_2OP <
0x4, "MIN",
- [(set R600_Reg32:$dst, (int_AMDIL_min R600_Reg32:$src0, R600_Reg32:$src1))]>
{
- let AMDILOp = AMDILInst.MIN_f32;
-}
+ [(set R600_Reg32:$dst, (AMDGPUfmin R600_Reg32:$src0, R600_Reg32:$src1))]
+>;
/* For the SET* instructions there is a naming conflict in
TargetSelectionDAG.td,
* so some of the instruction names don't match the asm string.
@@ -372,16 +371,17 @@ def MAX_INT : R600_2OP <
def MIN_INT : R600_2OP <
0x37, "MIN_INT",
- [(set R600_Reg32:$dst, (int_AMDGPU_imin R600_Reg32:$src0,
R600_Reg32:$src1))]>;
+ [(set R600_Reg32:$dst, (AMDGPUsmin R600_Reg32:$src0, R600_Reg32:$src1))]>;
def MAX_UINT : R600_2OP <
0x38, "MAX_UINT",
- [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]>;
+ [(set R600_Reg32:$dst, (AMDGPUsmax R600_Reg32:$src0, R600_Reg32:$src1))]
+>;
def MIN_UINT : R600_2OP <
0x39, "MIN_UINT",
- [(set R600_Reg32:$dst, (int_AMDGPU_umin R600_Reg32:$src0,
R600_Reg32:$src1))]>;
-
+ [(set R600_Reg32:$dst, (AMDGPUumin R600_Reg32:$src0, R600_Reg32:$src1))]
+>;
def SETE_INT : R600_2OP <
0x3A, "SETE_INT",
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Mesa (master): radeon/llvm: Fix segfault while lowering lrp intrinsic
Module: Mesa
Branch: master
Commit: c20e7417992380871261699c2b0123819e7d51fc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c20e7417992380871261699c2b0123819e7d51fc
Author: Tom Stellard
Date: Thu May 17 20:39:54 2012 -0400
radeon/llvm: Fix segfault while lowering lrp intrinsic
---
src/gallium/drivers/radeon/AMDGPUISelLowering.cpp |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
index b447e67..8df8035 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
@@ -91,8 +91,9 @@ SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
{
DebugLoc DL = Op.getDebugLoc();
EVT VT = Op.getValueType();
- SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT, DAG.getConstant(1, VT),
- Op.getOperand(1));
+ SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT,
+DAG.getConstantFP(1.0f, MVT::f32),
+Op.getOperand(1));
SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
Op.getOperand(3));
return DAG.getNode(AMDILISD::MAD, DL, VT, Op.getOperand(1),
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Mesa (master): llvmpipe: Avoid adding floating point zero to flat inputs.
Module: Mesa
Branch: master
Commit: 3f7a5ffac7e78bca47fa58849f5666fb334b3ab1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f7a5ffac7e78bca47fa58849f5666fb334b3ab1
Author: José Fonseca
Date: Fri May 18 01:03:13 2012 +0100
llvmpipe: Avoid adding floating point zero to flat inputs.
Which could clobber integer inputs, if the addition is not optimized away
(e.g., if optimizations are disabled for debugging purposes).
---
src/gallium/drivers/llvmpipe/lp_bld_interp.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/llvmpipe/lp_bld_interp.c
b/src/gallium/drivers/llvmpipe/lp_bld_interp.c
index 0608ab0..0d51ccb 100644
--- a/src/gallium/drivers/llvmpipe/lp_bld_interp.c
+++ b/src/gallium/drivers/llvmpipe/lp_bld_interp.c
@@ -239,7 +239,10 @@ coeffs_init(struct lp_build_interp_soa_context *bld,
* Compute the attrib values on the upper-left corner of each quad.
*/
-a = LLVMBuildFAdd(builder, a, dadq2, "");
+if (interp != LP_INTERP_CONSTANT &&
+interp != LP_INTERP_FACING) {
+ a = LLVMBuildFAdd(builder, a, dadq2, "");
+ }
#if PERSPECTIVE_DIVIDE_PER_QUAD
/*
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Mesa (master): Fix fetching integer inputs.
Module: Mesa
Branch: master
Commit: 00eb74b275e21d567a0ab8a6731181e005208634
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=00eb74b275e21d567a0ab8a6731181e005208634
Author: José Fonseca
Date: Fri May 18 00:55:13 2012 +0100
Fix fetching integer inputs.
---
src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
index a9d69a3..412dc0c 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
@@ -704,7 +704,15 @@ emit_fetch_input(
res = bld->inputs[reg->Register.Index][swizzle];
}
}
+
assert(res);
+
+ if (stype == TGSI_TYPE_UNSIGNED) {
+ res = LLVMBuildBitCast(builder, res, bld_base->uint_bld.vec_type, "");
+ } else if (stype == TGSI_TYPE_SIGNED) {
+ res = LLVMBuildBitCast(builder, res, bld_base->int_bld.vec_type, "");
+ }
+
return res;
}
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Mesa (master): llvmpipe: Implement TXQ.
Module: Mesa
Branch: master
Commit: 5d10d757276a599a60a68b88b21087b5824a8df7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d10d757276a599a60a68b88b21087b5824a8df7
Author: Olivier Galibert
Date: Thu May 17 16:48:54 2012 +0200
llvmpipe: Implement TXQ.
Piglits test for fragment shaders pass, vertex shaders fail. The
actual failure seems to be in the interpolators, and not the
textureSize query.
Signed-off-by: Olivier Galibert
Reviewed-by: Roland Scheidegger
Reviewed-by: José Fonseca
---
src/gallium/auxiliary/draw/draw_llvm_sample.c | 23 ++
src/gallium/auxiliary/gallivm/lp_bld_sample.c |7 +--
src/gallium/auxiliary/gallivm/lp_bld_sample.h | 14
src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c | 73 +
src/gallium/auxiliary/gallivm/lp_bld_tgsi.h |7 ++
src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c | 86 +
src/gallium/drivers/llvmpipe/lp_tex_sample.c | 23 ++
7 files changed, 227 insertions(+), 6 deletions(-)
diff --git a/src/gallium/auxiliary/draw/draw_llvm_sample.c
b/src/gallium/auxiliary/draw/draw_llvm_sample.c
index 8af3461..0a8b3bc 100644
--- a/src/gallium/auxiliary/draw/draw_llvm_sample.c
+++ b/src/gallium/auxiliary/draw/draw_llvm_sample.c
@@ -195,6 +195,28 @@ draw_llvm_sampler_soa_emit_fetch_texel(const struct
lp_build_sampler_soa *base,
}
+/**
+ * Fetch the texture size.
+ */
+static void
+draw_llvm_sampler_soa_emit_size_query(const struct lp_build_sampler_soa *base,
+ struct gallivm_state *gallivm,
+ unsigned unit,
+ LLVMValueRef explicit_lod, /* optional */
+ LLVMValueRef *sizes_out)
+{
+ struct draw_llvm_sampler_soa *sampler = (struct draw_llvm_sampler_soa
*)base;
+
+ assert(unit < PIPE_MAX_VERTEX_SAMPLERS);
+
+ lp_build_size_query_soa(gallivm,
+ &sampler->dynamic_state.static_state[unit],
+ &sampler->dynamic_state.base,
+ unit,
+ explicit_lod,
+ sizes_out);
+}
+
struct lp_build_sampler_soa *
draw_llvm_sampler_soa_create(const struct lp_sampler_static_state
*static_state,
LLVMValueRef context_ptr)
@@ -207,6 +229,7 @@ draw_llvm_sampler_soa_create(const struct
lp_sampler_static_state *static_state,
sampler->base.destroy = draw_llvm_sampler_soa_destroy;
sampler->base.emit_fetch_texel = draw_llvm_sampler_soa_emit_fetch_texel;
+ sampler->base.emit_size_query = draw_llvm_sampler_soa_emit_size_query;
sampler->dynamic_state.base.width = draw_llvm_texture_width;
sampler->dynamic_state.base.height = draw_llvm_texture_height;
sampler->dynamic_state.base.depth = draw_llvm_texture_depth;
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample.c
b/src/gallium/auxiliary/gallivm/lp_bld_sample.c
index c6d4f1b..2ffd9b8 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample.c
@@ -51,11 +51,6 @@
*/
#define BRILINEAR_FACTOR 2
-static LLVMValueRef
-lp_build_minify(struct lp_build_context *bld,
-LLVMValueRef base_size,
-LLVMValueRef level);
-
/**
* Does the given texture wrap mode allow sampling the texture border color?
* XXX maybe move this into gallium util code.
@@ -670,7 +665,7 @@ lp_build_get_const_mipmap_level(struct
lp_build_sample_context *bld,
* Codegen equivalent for u_minify().
* Return max(1, base_size >> level);
*/
-static LLVMValueRef
+LLVMValueRef
lp_build_minify(struct lp_build_context *bld,
LLVMValueRef base_size,
LLVMValueRef level)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample.h
b/src/gallium/auxiliary/gallivm/lp_bld_sample.h
index a71e656..8ccba2c 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_sample.h
+++ b/src/gallium/auxiliary/gallivm/lp_bld_sample.h
@@ -405,8 +405,22 @@ lp_build_sample_soa(struct gallivm_state *gallivm,
LLVMValueRef texel_out[4]);
void
+lp_build_size_query_soa(struct gallivm_state *gallivm,
+const struct lp_sampler_static_state *static_state,
+struct lp_sampler_dynamic_state *dynamic_state,
+unsigned unit,
+LLVMValueRef explicit_lod,
+LLVMValueRef *sizes_out);
+
+void
lp_build_sample_nop(struct gallivm_state *gallivm, struct lp_type type,
LLVMValueRef texel_out[4]);
+LLVMValueRef
+lp_build_minify(struct lp_build_context *bld,
+LLVMValueRef base_size,
+LLVMValueRef level);
+
+
#endif /* LP_BLD_SAMPLE_H */
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
b/src/gallium/auxiliary/gallivm/lp_bld_sample_soa.c
index 4ea7b4b..73dc3e7 100644
--- a/src/gallium/au
Mesa (master): llvmpipe: Don' t mess with the provoking vertex when inverting a triangle.
Module: Mesa
Branch: master
Commit: 1ec421823b1263a7b482adf48a15b186ea91efd2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1ec421823b1263a7b482adf48a15b186ea91efd2
Author: Olivier Galibert
Date: Thu May 17 09:32:31 2012 +0200
llvmpipe: Don't mess with the provoking vertex when inverting a triangle.
Fixes a bunch of piglit tests related to flat interpolation of floats.
Signed-off-by: Olivier Galibert
Signed-off-by: José Fonseca
---
src/gallium/drivers/llvmpipe/lp_setup_tri.c | 45 ---
1 files changed, 40 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/llvmpipe/lp_setup_tri.c
b/src/gallium/drivers/llvmpipe/lp_setup_tri.c
index 9916101..97a76d8 100644
--- a/src/gallium/drivers/llvmpipe/lp_setup_tri.c
+++ b/src/gallium/drivers/llvmpipe/lp_setup_tri.c
@@ -815,10 +815,35 @@ calc_fixed_position( struct lp_setup_context *setup,
/**
* Rotate a triangle, flipping its clockwise direction,
+ * Swaps values for xy[0] and xy[1]
+ */
+static INLINE void
+rotate_fixed_position_01( struct fixed_position* position )
+{
+ int x, y;
+
+ x = position->x[1];
+ y = position->y[1];
+ position->x[1] = position->x[0];
+ position->y[1] = position->y[0];
+ position->x[0] = x;
+ position->y[0] = y;
+
+ position->dx01 = -position->dx01;
+ position->dy01 = -position->dy01;
+ position->dx20 = position->x[2] - position->x[0];
+ position->dy20 = position->y[2] - position->y[0];
+
+ position->area = -position->area;
+}
+
+
+/**
+ * Rotate a triangle, flipping its clockwise direction,
* Swaps values for xy[1] and xy[2]
*/
static INLINE void
-rotate_fixed_position( struct fixed_position* position )
+rotate_fixed_position_12( struct fixed_position* position )
{
int x, y;
@@ -852,8 +877,13 @@ static void triangle_cw( struct lp_setup_context *setup,
calc_fixed_position(setup, &position, v0, v1, v2);
if (position.area < 0) {
- rotate_fixed_position(&position);
- retry_triangle_ccw(setup, &position, v0, v2, v1,
!setup->ccw_is_frontface);
+ if (setup->flatshade_first) {
+ rotate_fixed_position_12(&position);
+ retry_triangle_ccw(setup, &position, v0, v2, v1,
!setup->ccw_is_frontface);
+ } else {
+ rotate_fixed_position_01(&position);
+ retry_triangle_ccw(setup, &position, v1, v0, v2,
!setup->ccw_is_frontface);
+ }
}
}
@@ -893,8 +923,13 @@ static void triangle_both( struct lp_setup_context *setup,
if (position.area > 0)
retry_triangle_ccw( setup, &position, v0, v1, v2,
setup->ccw_is_frontface );
else if (position.area < 0) {
- rotate_fixed_position( &position );
- retry_triangle_ccw( setup, &position, v0, v2, v1,
!setup->ccw_is_frontface );
+ if (setup->flatshade_first) {
+ rotate_fixed_position_12( &position );
+ retry_triangle_ccw( setup, &position, v0, v2, v1,
!setup->ccw_is_frontface );
+ } else {
+ rotate_fixed_position_01( &position );
+ retry_triangle_ccw( setup, &position, v1, v0, v2,
!setup->ccw_is_frontface );
+ }
}
}
___
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Mesa (master): radeon/llvm: Lower lrp intrinsic during ISel
Module: Mesa
Branch: master
Commit: c6c8a05c509b30600d2ccb4be635f05cd71c68a4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c6c8a05c509b30600d2ccb4be635f05cd71c68a4
Author: Tom Stellard
Date: Thu May 17 13:36:12 2012 -0400
radeon/llvm: Lower lrp intrinsic during ISel
---
src/gallium/drivers/radeon/AMDGPUISelLowering.cpp | 18 ++
src/gallium/drivers/radeon/AMDGPUISelLowering.h |1 +
src/gallium/drivers/radeon/R600Instructions.td|7 ---
3 files changed, 19 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
index 53f04c5..0417273 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
@@ -45,6 +45,8 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue
Op,
default: return Op;
case AMDGPUIntrinsic::AMDIL_abs:
return LowerIntrinsicIABS(Op, DAG);
+case AMDGPUIntrinsic::AMDGPU_lrp:
+ return LowerIntrinsicLRP(Op, DAG);
case AMDGPUIntrinsic::AMDIL_mad:
return DAG.getNode(AMDILISD::MAD, DL, VT, Op.getOperand(1),
Op.getOperand(2), Op.getOperand(3));
@@ -73,6 +75,22 @@ SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
}
+/// Linear Interpolation
+/// LRP(a, b, c) = muladd(a, b, (1 - a) * c)
+SDValue AMDGPUTargetLowering::LowerIntrinsicLRP(SDValue Op,
+SelectionDAG &DAG) const
+{
+ DebugLoc DL = Op.getDebugLoc();
+ EVT VT = Op.getValueType();
+ SDValue OneSubA = DAG.getNode(ISD::FSUB, DL, VT, DAG.getConstant(1, VT),
+ Op.getOperand(1));
+ SDValue OneSubAC = DAG.getNode(ISD::FMUL, DL, VT, OneSubA,
+Op.getOperand(3));
+ return DAG.getNode(AMDILISD::MAD, DL, VT, Op.getOperand(1),
+ Op.getOperand(2),
+ OneSubAC);
+}
+
void AMDGPUTargetLowering::addLiveIn(MachineInstr * MI,
MachineFunction * MF, MachineRegisterInfo & MRI,
const TargetInstrInfo * TII, unsigned reg) const
diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.h
b/src/gallium/drivers/radeon/AMDGPUISelLowering.h
index e4c7787..3e5e81b 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.h
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.h
@@ -41,6 +41,7 @@ public:
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerIntrinsicLRP(SDValue Op, SelectionDAG &DAG) const;
virtual const char* getTargetNodeName(unsigned Opcode) const;
};
diff --git a/src/gallium/drivers/radeon/R600Instructions.td
b/src/gallium/drivers/radeon/R600Instructions.td
index df2d56b..459010c 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -672,11 +672,6 @@ class DIV_Common : Pat<
(MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
>;
-class LRP_Common : Pat <
- (int_AMDGPU_lrp R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2),
- (muladd R600_Reg32:$src0, R600_Reg32:$src1, (MUL (SUB_f32 ONE,
R600_Reg32:$src0), R600_Reg32:$src2))
->;
-
class SSG_Common : Pat <
(int_AMDGPU_ssg R600_Reg32:$src),
(cndgt R600_Reg32:$src, (f32 ONE), (cndge R600_Reg32:$src, (f32 ZERO), (f32
NEG_ONE)))
@@ -725,7 +720,6 @@ let Gen = AMDGPUGen.R600 in {
} // End AMDGPUGen.R600
def DIV_r600 : DIV_Common;
- def LRP_r600 : LRP_Common;
def POW_r600 : POW_Common;
def SSG_r600 : SSG_Common;
def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common;
@@ -904,7 +898,6 @@ let Gen = AMDGPUGen.EG_CAYMAN in {
} // End AMDGPUGen.EG_CAYMAN
def DIV_eg : DIV_Common;
- def LRP_eg : LRP_Common;
def POW_eg : POW_Common;
def SSG_eg : SSG_Common;
def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common;
___
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Mesa (master): radeon/llvm: Remove AMDIL MAD instruction defs
Module: Mesa
Branch: master
Commit: ef8e66bc165ea2ef9987ab6406268ce195f74eb0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef8e66bc165ea2ef9987ab6406268ce195f74eb0
Author: Tom Stellard
Date: Thu May 17 14:34:40 2012 -0400
radeon/llvm: Remove AMDIL MAD instruction defs
---
src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl |1 -
src/gallium/drivers/radeon/AMDGPUISelLowering.cpp |3 +++
src/gallium/drivers/radeon/AMDILInstructions.td |2 --
src/gallium/drivers/radeon/R600Instructions.td|6 +++---
src/gallium/drivers/radeon/SIInstrInfo.cpp|1 -
src/gallium/drivers/radeon/SIInstructions.td |8
6 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
index df532eb..52b79bd 100644
--- a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
+++ b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
@@ -34,7 +34,6 @@ use strict;
my @F32_MULTICLASSES = qw {
UnaryIntrinsicFloat
UnaryIntrinsicFloatScalar
- TernaryIntrinsicFloat
};
my @I32_MULTICLASSES = qw {
diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
index 921daa6..53f04c5 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
@@ -45,6 +45,9 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue
Op,
default: return Op;
case AMDGPUIntrinsic::AMDIL_abs:
return LowerIntrinsicIABS(Op, DAG);
+case AMDGPUIntrinsic::AMDIL_mad:
+ return DAG.getNode(AMDILISD::MAD, DL, VT, Op.getOperand(1),
+ Op.getOperand(2), Op.getOperand(3));
case AMDGPUIntrinsic::AMDIL_max:
return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
Op.getOperand(2));
diff --git a/src/gallium/drivers/radeon/AMDILInstructions.td
b/src/gallium/drivers/radeon/AMDILInstructions.td
index 725ac29..629a2c0 100644
--- a/src/gallium/drivers/radeon/AMDILInstructions.td
+++ b/src/gallium/drivers/radeon/AMDILInstructions.td
@@ -251,7 +251,6 @@ defm POW : BinaryIntrinsicFloat;
let hasIEEEFlag = 1 in {
let mayLoad = 0, mayStore=0 in {
defm MIN : BinaryIntrinsicFloat;
-defm MAD : TernaryIntrinsicFloat;
}
defm MOD : BinaryOpMCf32;
}
@@ -270,7 +269,6 @@ defm LERP : TernaryIntrinsicFloat;
}
defm SUB : BinaryOpMCf32;
defm FABS : UnaryOpMCf32;
-defm FMAD : TernaryOpMCf32;
defm NEAR : UnaryOpMCf32;
defm RND_Z : UnaryOpMCf32;
diff --git a/src/gallium/drivers/radeon/R600Instructions.td
b/src/gallium/drivers/radeon/R600Instructions.td
index 75ccca2..df2d56b 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -521,9 +521,9 @@ class MUL_LIT_Common inst> : R600_3OP <
class MULADD_Common inst> : R600_3OP <
inst, "MULADD",
- []> {
- let AMDILOp = AMDILInst.MAD_f32;
-}
+ [(set (f32 R600_Reg32:$dst),
+ (IL_mad R600_Reg32:$src0, R600_Reg32:$src1, R600_Reg32:$src2))]
+>;
class CNDE_Common inst> : R600_3OP <
inst, "CNDE",
diff --git a/src/gallium/drivers/radeon/SIInstrInfo.cpp
b/src/gallium/drivers/radeon/SIInstrInfo.cpp
index 0cb9764..553ac36 100644
--- a/src/gallium/drivers/radeon/SIInstrInfo.cpp
+++ b/src/gallium/drivers/radeon/SIInstrInfo.cpp
@@ -106,7 +106,6 @@ MachineInstr * SIInstrInfo::convertToISA(MachineInstr & MI,
MachineFunction &MF,
unsigned SIInstrInfo::getISAOpcode(unsigned AMDILopcode) const
{
switch (AMDILopcode) {
- case AMDIL::MAD_f32: return AMDIL::V_MAD_LEGACY_F32;
//XXX We need a better way of detecting end of program
case AMDIL::RETURN: return AMDIL::S_ENDPGM;
default: return AMDGPUInstrInfo::getISAOpcode(AMDILopcode);
diff --git a/src/gallium/drivers/radeon/SIInstructions.td
b/src/gallium/drivers/radeon/SIInstructions.td
index c1c9699..1818e47 100644
--- a/src/gallium/drivers/radeon/SIInstructions.td
+++ b/src/gallium/drivers/radeon/SIInstructions.td
@@ -964,4 +964,12 @@ def : Pat <
/* XXX: We are using IEEE MUL, not the 0 * anything = 0 MUL, is this correct?
*/
def : POW_Common ;
+/** == **/
+/** VOP3 Patterns**/
+/** == **/
+
+def : Pat <(f32 (IL_mad AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2)),
+ (V_MAD_LEGACY_F32 AllReg_32:$src0, AllReg_32:$src1, AllReg_32:$src2,
+0, 0, 0, 0)>;
+
} // End isSI predicate
___
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Mesa (master): radeon/llvm: Remove AMDIL MUL_IEEE* instructions
Module: Mesa
Branch: master
Commit: d07473fcf4126c740802e6458452e82cc5c799ba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d07473fcf4126c740802e6458452e82cc5c799ba
Author: Tom Stellard
Date: Thu May 17 13:41:21 2012 -0400
radeon/llvm: Remove AMDIL MUL_IEEE* instructions
---
src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl |2 +-
src/gallium/drivers/radeon/AMDILInstructions.td |3 ---
src/gallium/drivers/radeon/R600Instructions.td|5 ++---
3 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
index 498ef13..df532eb 100644
--- a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
+++ b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
@@ -56,7 +56,7 @@ my $FILE_TYPE = $ARGV[0];
open AMDIL, '<', 'AMDILInstructions.td';
-my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32',
'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'BINARY_OR_i32',
'BINARY_NOT_i32', 'MIN_f32', 'MUL_IEEE_f32');
+my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32',
'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'BINARY_OR_i32',
'BINARY_NOT_i32', 'MIN_f32');
while () {
if ($_ =~ /defm\s+([A-Z_]+)\s+:\s+([A-Za-z0-9]+);
-}
//===-===//
// float math instructions start here
//===-===//
diff --git a/src/gallium/drivers/radeon/R600Instructions.td
b/src/gallium/drivers/radeon/R600Instructions.td
index c66d62d..75ccca2 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -255,9 +255,8 @@ def MUL : R600_2OP <
def MUL_IEEE : R600_2OP <
0x2, "MUL_IEEE",
- [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))]> {
- let AMDILOp = AMDILInst.MUL_IEEE_f32;
-}
+ [(set R600_Reg32:$dst, (fmul R600_Reg32:$src0, R600_Reg32:$src1))]
+>;
def MAX : R600_2OP <
0x3, "MAX",
___
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Mesa (master): r600g: Handle MUL_IEEE in r600_bytecode_get_num_operands
Module: Mesa Branch: master Commit: 5187948bc2b16df70ee6696a8702a898b38a2d63 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5187948bc2b16df70ee6696a8702a898b38a2d63 Author: Tom Stellard Date: Thu May 17 14:31:36 2012 -0400 r600g: Handle MUL_IEEE in r600_bytecode_get_num_operands --- src/gallium/drivers/r600/r600_asm.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/gallium/drivers/r600/r600_asm.c b/src/gallium/drivers/r600/r600_asm.c index 5a10bd9..b73bbb3 100644 --- a/src/gallium/drivers/r600/r600_asm.c +++ b/src/gallium/drivers/r600/r600_asm.c @@ -54,6 +54,7 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode * case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE: case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE: case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL: + case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE: case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT: case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT: case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT: @@ -133,6 +134,7 @@ static inline unsigned int r600_bytecode_get_num_operands(struct r600_bytecode * case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLGE: case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_KILLNE: case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL: + case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE: case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_INT: case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULLO_INT: case EG_V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MULHI_UINT: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeon/llvm: Expand fsub during ISel
Module: Mesa
Branch: master
Commit: 1fe70c6ae12e85cdb5967ba6d72fca8a9e5c3ec3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1fe70c6ae12e85cdb5967ba6d72fca8a9e5c3ec3
Author: Tom Stellard
Date: Thu May 17 13:13:17 2012 -0400
radeon/llvm: Expand fsub during ISel
---
src/gallium/drivers/radeon/R600ISelLowering.cpp|2 ++
.../drivers/radeon/R600LowerInstructions.cpp | 11 ---
2 files changed, 2 insertions(+), 11 deletions(-)
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp
b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index 4db40f7..1fffb99 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -34,6 +34,8 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Legal);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
+
+ setOperationAction(ISD::FSUB, MVT::f32, Expand);
}
MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter(
diff --git a/src/gallium/drivers/radeon/R600LowerInstructions.cpp
b/src/gallium/drivers/radeon/R600LowerInstructions.cpp
index 19c3aae..a5f57cc 100644
--- a/src/gallium/drivers/radeon/R600LowerInstructions.cpp
+++ b/src/gallium/drivers/radeon/R600LowerInstructions.cpp
@@ -303,17 +303,6 @@ bool
R600LowerInstructionsPass::runOnMachineFunction(MachineFunction &MF)
break;
}
- case AMDIL::SUB_f32:
-{
- MI.getOperand(2).addTargetFlag(MO_FLAG_NEG);
- BuildMI(MBB, I, MBB.findDebugLoc(I),
- TII->get(TII->getISAOpcode(AMDIL::ADD)))
- .addOperand(MI.getOperand(0))
- .addOperand(MI.getOperand(1))
- .addOperand(MI.getOperand(2));
- break;
-}
-
case AMDIL::ULT:
BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::SETGT_UINT))
.addOperand(MI.getOperand(0))
___
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Mesa (master): radeon/llvm: Remove AMDIL CMOVLOG* instruction defs
Module: Mesa
Branch: master
Commit: 91484de22dd5143cef5f2fe7786f96abfbc795c8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=91484de22dd5143cef5f2fe7786f96abfbc795c8
Author: Tom Stellard
Date: Thu May 17 12:54:43 2012 -0400
radeon/llvm: Remove AMDIL CMOVLOG* instruction defs
---
src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl |2 +-
src/gallium/drivers/radeon/AMDILInstructions.td|5 -
src/gallium/drivers/radeon/R600Instructions.td |9 +
.../drivers/radeon/R600LowerInstructions.cpp | 16
4 files changed, 6 insertions(+), 26 deletions(-)
diff --git a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
index ddff399..a6a7627 100644
--- a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
+++ b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
@@ -57,7 +57,7 @@ my $FILE_TYPE = $ARGV[0];
open AMDIL, '<', 'AMDILInstructions.td';
-my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32',
'FTOI', 'ITOF', 'CMOVLOG_f32', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ',
'BINARY_OR_i32', 'BINARY_NOT_i32', 'MIN_f32');
+my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32',
'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'BINARY_OR_i32',
'BINARY_NOT_i32', 'MIN_f32');
while () {
if ($_ =~ /defm\s+([A-Z_]+)\s+:\s+([A-Za-z0-9]+);
defm CMOV : BinaryOpMC;
defm DIV_INF: BinaryOpMC;
defm SMAX : BinaryOpMCInt;
-// This opcode has custom swizzle pattern encoded in Swizzle Encoder for 64bit
-// instructions
-defm CMOVLOG: TernaryOpMC;
// This opcode has a custom swizzle pattern in the Swizzle Encoder and
// should never be selected in ISel. It should only be generated in the
// I/O expansion code. These are different from the CMOVLOG instruction
@@ -107,8 +104,6 @@ defm CARRY : BinaryIntrinsicInt;
defm BORROW : BinaryIntrinsicInt;
defm IMIN : BinaryIntrinsicInt;
defm IMAX : BinaryIntrinsicInt;
-defm CMOV_LOG : TernaryIntrinsicInt;
defm IBIT_EXTRACT : TernaryIntrinsicInt;
defm IMAD : TernaryIntrinsicInt;
diff --git a/src/gallium/drivers/radeon/R600Instructions.td
b/src/gallium/drivers/radeon/R600Instructions.td
index c3643b6..f7fe34b 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -421,7 +421,8 @@ def SETGE_UINT : R600_2OP <
def CNDE_INT : R600_3OP <
0x1C, "CNDE_INT",
- []
+ [(set (i32 R600_Reg32:$dst),
+ (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
>;
/* Texture instructions */
@@ -527,9 +528,9 @@ class MULADD_Common inst> : R600_3OP <
class CNDE_Common inst> : R600_3OP <
inst, "CNDE",
- []> {
- let AMDILOp = AMDILInst.CMOVLOG_f32;
-}
+ [(set (f32 R600_Reg32:$dst),
+ (IL_cmov_logical R600_Reg32:$src0, R600_Reg32:$src2, R600_Reg32:$src1))]
+>;
class CNDGT_Common inst> : R600_3OP <
inst, "CNDGT",
diff --git a/src/gallium/drivers/radeon/R600LowerInstructions.cpp
b/src/gallium/drivers/radeon/R600LowerInstructions.cpp
index 2edae32..5a0f1d9 100644
--- a/src/gallium/drivers/radeon/R600LowerInstructions.cpp
+++ b/src/gallium/drivers/radeon/R600LowerInstructions.cpp
@@ -114,22 +114,6 @@ bool
R600LowerInstructionsPass::runOnMachineFunction(MachineFunction &MF)
.addReg(tmp2);
break;
}
- case AMDIL::CMOVLOG_f32:
-BuildMI(MBB, I, MBB.findDebugLoc(I),
TM.getInstrInfo()->get(MI.getOpcode()))
-.addOperand(MI.getOperand(0))
-.addOperand(MI.getOperand(1))
-.addOperand(MI.getOperand(3))
-.addOperand(MI.getOperand(2));
-break;
-
- case AMDIL::CMOVLOG_i32:
-BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::CNDE_INT))
-.addOperand(MI.getOperand(0))
-.addOperand(MI.getOperand(1))
-.addOperand(MI.getOperand(3))
-.addOperand(MI.getOperand(2));
-break;
-
case AMDIL::CLAMP_f32:
{
MachineOperand lowOp = MI.getOperand(2);
___
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Mesa (master): radeon/llvm: Remove AMDIL floating-point ADD instruction defs
Module: Mesa
Branch: master
Commit: 9916f2d2af18a26f32efb85aff5c11e1b998e19c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9916f2d2af18a26f32efb85aff5c11e1b998e19c
Author: Tom Stellard
Date: Thu May 17 13:05:07 2012 -0400
radeon/llvm: Remove AMDIL floating-point ADD instruction defs
---
src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl |3 +--
src/gallium/drivers/radeon/AMDILInstructions.td|1 -
src/gallium/drivers/radeon/R600Instructions.td |6 +++---
.../drivers/radeon/R600LowerInstructions.cpp |2 +-
src/gallium/drivers/radeon/SIInstructions.td |5 -
5 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
index a6a7627..498ef13 100644
--- a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
+++ b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
@@ -35,7 +35,6 @@ my @F32_MULTICLASSES = qw {
UnaryIntrinsicFloat
UnaryIntrinsicFloatScalar
TernaryIntrinsicFloat
- BinaryOpMCFloat
};
my @I32_MULTICLASSES = qw {
@@ -57,7 +56,7 @@ my $FILE_TYPE = $ARGV[0];
open AMDIL, '<', 'AMDILInstructions.td';
-my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32',
'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'BINARY_OR_i32',
'BINARY_NOT_i32', 'MIN_f32');
+my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32',
'FTOI', 'ITOF', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ', 'BINARY_OR_i32',
'BINARY_NOT_i32', 'MIN_f32', 'MUL_IEEE_f32');
while () {
if ($_ =~ /defm\s+([A-Z_]+)\s+:\s+([A-Za-z0-9]+);
}
-defm ADD : BinaryOpMCFloat;
//===-===//
// float math instructions start here
//===-===//
diff --git a/src/gallium/drivers/radeon/R600Instructions.td
b/src/gallium/drivers/radeon/R600Instructions.td
index f7fe34b..c66d62d 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -244,9 +244,9 @@ let Gen = AMDGPUGen.R600_CAYMAN in {
def ADD : R600_2OP <
0x0, "ADD",
- [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))] > {
- let AMDILOp = AMDILInst.ADD_f32;
-}
+ [(set R600_Reg32:$dst, (fadd R600_Reg32:$src0, R600_Reg32:$src1))]
+>;
+
// Non-IEEE MUL: 0 * anything = 0
def MUL : R600_2OP <
0x1, "MUL NON-IEEE",
diff --git a/src/gallium/drivers/radeon/R600LowerInstructions.cpp
b/src/gallium/drivers/radeon/R600LowerInstructions.cpp
index 5a0f1d9..19c3aae 100644
--- a/src/gallium/drivers/radeon/R600LowerInstructions.cpp
+++ b/src/gallium/drivers/radeon/R600LowerInstructions.cpp
@@ -307,7 +307,7 @@ bool
R600LowerInstructionsPass::runOnMachineFunction(MachineFunction &MF)
{
MI.getOperand(2).addTargetFlag(MO_FLAG_NEG);
BuildMI(MBB, I, MBB.findDebugLoc(I),
- TII->get(TII->getISAOpcode(AMDIL::ADD_f32)))
+ TII->get(TII->getISAOpcode(AMDIL::ADD)))
.addOperand(MI.getOperand(0))
.addOperand(MI.getOperand(1))
.addOperand(MI.getOperand(2));
diff --git a/src/gallium/drivers/radeon/SIInstructions.td
b/src/gallium/drivers/radeon/SIInstructions.td
index 4efc093..c1c9699 100644
--- a/src/gallium/drivers/radeon/SIInstructions.td
+++ b/src/gallium/drivers/radeon/SIInstructions.td
@@ -590,7 +590,10 @@ def V_CNDMASK_B32 : VOP2_Helper <
defm V_READLANE_B32 : VOP2_32 <0x0001, "V_READLANE_B32", []>;
defm V_WRITELANE_B32 : VOP2_32 <0x0002, "V_WRITELANE_B32", []>;
-defm V_ADD_F32 : VOP2_32 <0x0003, "V_ADD_F32", [], AMDILInst.ADD_f32>;
+defm V_ADD_F32 : VOP2_32 <
+ 0x0003, "V_ADD_F32",
+ [(set VReg_32:$dst, (fadd AllReg_32:$src0, VReg_32:$src1))]
+>;
defm V_SUB_F32 : VOP2_32 <0x0004, "V_SUB_F32", []>;
defm V_SUBREV_F32 : VOP2_32 <0x0005, "V_SUBREV_F32", []>;
___
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Mesa (master): radeon/llvm: Move lowering of ABS_i32 to ISel
Module: Mesa
Branch: master
Commit: 9a020092aedc6310d5bfc72b2aa6fc4348fe5c32
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a020092aedc6310d5bfc72b2aa6fc4348fe5c32
Author: Tom Stellard
Date: Thu May 17 12:08:21 2012 -0400
radeon/llvm: Move lowering of ABS_i32 to ISel
---
src/gallium/drivers/radeon/AMDGPUISelLowering.cpp | 15 +++
src/gallium/drivers/radeon/AMDGPUISelLowering.h|1 +
src/gallium/drivers/radeon/AMDILInstructions.td|1 -
.../drivers/radeon/R600LowerInstructions.cpp | 16
4 files changed, 16 insertions(+), 17 deletions(-)
diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
index 9d1042e..921daa6 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
@@ -43,6 +43,8 @@ SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue
Op,
switch (IntrinsicID) {
default: return Op;
+case AMDGPUIntrinsic::AMDIL_abs:
+ return LowerIntrinsicIABS(Op, DAG);
case AMDGPUIntrinsic::AMDIL_max:
return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
Op.getOperand(2));
@@ -55,6 +57,19 @@ SDValue
AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
}
}
+///IABS(a) = SMAX(sub(0, a), a)
+SDValue AMDGPUTargetLowering::LowerIntrinsicIABS(SDValue Op,
+SelectionDAG &DAG) const
+{
+
+ DebugLoc DL = Op.getDebugLoc();
+ EVT VT = Op.getValueType();
+ SDValue Neg = DAG.getNode(ISD::SUB, DL, VT, DAG.getConstant(0, VT),
+ Op.getOperand(1));
+
+ return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Neg, Op.getOperand(1));
+}
+
void AMDGPUTargetLowering::addLiveIn(MachineInstr * MI,
MachineFunction * MF, MachineRegisterInfo & MRI,
const TargetInstrInfo * TII, unsigned reg) const
diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.h
b/src/gallium/drivers/radeon/AMDGPUISelLowering.h
index b67f30b..e4c7787 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.h
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.h
@@ -40,6 +40,7 @@ public:
AMDGPUTargetLowering(TargetMachine &TM);
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
+ SDValue LowerIntrinsicIABS(SDValue Op, SelectionDAG &DAG) const;
virtual const char* getTargetNodeName(unsigned Opcode) const;
};
diff --git a/src/gallium/drivers/radeon/AMDILInstructions.td
b/src/gallium/drivers/radeon/AMDILInstructions.td
index f03ec6b..3ee7836 100644
--- a/src/gallium/drivers/radeon/AMDILInstructions.td
+++ b/src/gallium/drivers/radeon/AMDILInstructions.td
@@ -92,7 +92,6 @@ def ADDri : TwoInOneOut;
defm IFFB_LO: UnaryOpMCi32;
let mayLoad = 0, mayStore = 0 in {
-defm ABS : UnaryIntrinsicInt;
defm BITCOUNT : UnaryIntrinsicInt;
defm FFB_LO : UnaryIntrinsicInt;
defm FFB_HI : UnaryIntrinsicInt;
diff --git a/src/gallium/drivers/radeon/R600LowerInstructions.cpp
b/src/gallium/drivers/radeon/R600LowerInstructions.cpp
index 42c9766..2edae32 100644
--- a/src/gallium/drivers/radeon/R600LowerInstructions.cpp
+++ b/src/gallium/drivers/radeon/R600LowerInstructions.cpp
@@ -88,22 +88,6 @@ bool
R600LowerInstructionsPass::runOnMachineFunction(MachineFunction &MF)
.addOperand(MI.getOperand(1));
break;
- case AMDIL::ABS_i32:
-{
- unsigned neg = MRI->createVirtualRegister(
- &AMDIL::R600_TReg32RegClass);
- BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::SUB_INT),neg)
- .addReg(AMDIL::ZERO)
- .addOperand(MI.getOperand(1));
-
- BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDIL::MAX_INT))
- .addOperand(MI.getOperand(0))
- .addOperand(MI.getOperand(1))
- .addReg(neg);
-
- break;
-}
-
/* XXX: We could propagate the ABS flag to all of the uses of Operand0
and
* remove the ABS instruction.*/
case AMDIL::FABS_f32:
___
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Mesa (master): radeon/llvm: Remove sub patterns from AMDILInstrPatterns.td
Module: Mesa Branch: master Commit: 89b945591bb5d434518cea481209b1ea7a435861 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=89b945591bb5d434518cea481209b1ea7a435861 Author: Tom Stellard Date: Thu May 17 11:46:19 2012 -0400 radeon/llvm: Remove sub patterns from AMDILInstrPatterns.td --- src/gallium/drivers/radeon/AMDILInstrPatterns.td | 20 src/gallium/drivers/radeon/R600Instructions.td |2 +- 2 files changed, 1 insertions(+), 21 deletions(-) diff --git a/src/gallium/drivers/radeon/AMDILInstrPatterns.td b/src/gallium/drivers/radeon/AMDILInstrPatterns.td index 51181b2..0314598 100644 --- a/src/gallium/drivers/radeon/AMDILInstrPatterns.td +++ b/src/gallium/drivers/radeon/AMDILInstrPatterns.td @@ -30,26 +30,6 @@ def ULTOF : Pat<(f32 (uint_to_fp GPRI64:$src)), def LTOF : Pat<(f32 (sint_to_fp GPRI64:$src)), (ITOF (LLO GPRI64:$src))>; -// integer subtraction -// a - b ==> a + (-b) -def SUB_i8 : Pat<(sub GPRI8:$src0, GPRI8:$src1), -(ADD_i8 GPRI8:$src0, (NEGATE_i8 GPRI8:$src1))>; -def SUB_v2i8 : Pat<(sub GPRV2I8:$src0, GPRV2I8:$src1), -(ADD_v2i8 GPRV2I8:$src0, (NEGATE_v2i8 GPRV2I8:$src1))>; -def SUB_v4i8 : Pat<(sub GPRV4I8:$src0, GPRV4I8:$src1), -(ADD_v4i8 GPRV4I8:$src0, (NEGATE_v4i8 GPRV4I8:$src1))>; -def SUB_i16 : Pat<(sub GPRI16:$src0, GPRI16:$src1), -(ADD_i16 GPRI16:$src0, (NEGATE_i16 GPRI16:$src1))>; -def SUB_v2i16 : Pat<(sub GPRV2I16:$src0, GPRV2I16:$src1), -(ADD_v2i16 GPRV2I16:$src0, (NEGATE_v2i16 GPRV2I16:$src1))>; -def SUB_v4i16 : Pat<(sub GPRV4I16:$src0, GPRV4I16:$src1), -(ADD_v4i16 GPRV4I16:$src0, (NEGATE_v4i16 GPRV4I16:$src1))>; -def SUB_i32 : Pat<(sub GPRI32:$src0, GPRI32:$src1), -(ADD_i32 GPRI32:$src0, (NEGATE_i32 GPRI32:$src1))>; -def SUB_v2i32 : Pat<(sub GPRV2I32:$src0, GPRV2I32:$src1), -(ADD_v2i32 GPRV2I32:$src0, (NEGATE_v2i32 GPRV2I32:$src1))>; -def SUB_v4i32 : Pat<(sub GPRV4I32:$src0, GPRV4I32:$src1), -(ADD_v4i32 GPRV4I32:$src0, (NEGATE_v4i32 GPRV4I32:$src1))>; // LLVM isn't lowering this correctly, so writing a pattern that // matches it isntead. def : Pat<(build_vector (i32 imm:$src)), diff --git a/src/gallium/drivers/radeon/R600Instructions.td b/src/gallium/drivers/radeon/R600Instructions.td index ca2af73..c3643b6 100644 --- a/src/gallium/drivers/radeon/R600Instructions.td +++ b/src/gallium/drivers/radeon/R600Instructions.td @@ -364,7 +364,7 @@ def ADD_INT : R600_2OP < def SUB_INT : R600_2OP < 0x35, "SUB_INT", - [] + [(set R600_Reg32:$dst, (sub R600_Reg32:$src0, R600_Reg32:$src1))] >; def MAX_INT : R600_2OP < ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeon/llvm: Add custom SDNodes for MAX
Module: Mesa
Branch: master
Commit: 431bb79a41bd5e7402954385daea1594c3e750ab
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=431bb79a41bd5e7402954385daea1594c3e750ab
Author: Tom Stellard
Date: Thu May 17 07:35:15 2012 -0400
radeon/llvm: Add custom SDNodes for MAX
We now lower the various intrinsics for max to SDNodes and then use
tablegen patterns to lower the SDNodes to instructions.
---
src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl |3 +-
src/gallium/drivers/radeon/AMDGPUISelLowering.cpp | 45 +
src/gallium/drivers/radeon/AMDGPUISelLowering.h | 21 ++
src/gallium/drivers/radeon/AMDGPUInstrInfo.td | 31 ++
src/gallium/drivers/radeon/AMDIL.td |1 +
src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp |1 +
src/gallium/drivers/radeon/AMDILISelLowering.h|1 +
src/gallium/drivers/radeon/AMDILInstructions.td |1 -
src/gallium/drivers/radeon/R600Instructions.td|9 ++--
src/gallium/drivers/radeon/SIInstructions.td |5 +-
10 files changed, 108 insertions(+), 10 deletions(-)
diff --git a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
index 130eaac..ddff399 100644
--- a/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
+++ b/src/gallium/drivers/radeon/AMDGPUGenInstrEnums.pl
@@ -34,7 +34,6 @@ use strict;
my @F32_MULTICLASSES = qw {
UnaryIntrinsicFloat
UnaryIntrinsicFloatScalar
- BinaryIntrinsicFloat
TernaryIntrinsicFloat
BinaryOpMCFloat
};
@@ -58,7 +57,7 @@ my $FILE_TYPE = $ARGV[0];
open AMDIL, '<', 'AMDILInstructions.td';
-my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32',
'FTOI', 'ITOF', 'CMOVLOG_f32', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ',
'BINARY_OR_i32', 'BINARY_NOT_i32');
+my @INST_ENUMS = ('NONE', 'FEQ', 'FGE', 'FLT', 'FNE', 'MOVE_f32', 'MOVE_i32',
'FTOI', 'ITOF', 'CMOVLOG_f32', 'UGT', 'IGE', 'INE', 'UGE', 'IEQ',
'BINARY_OR_i32', 'BINARY_NOT_i32', 'MIN_f32');
while () {
if ($_ =~ /defm\s+([A-Z_]+)\s+:\s+([A-Za-z0-9]+)(Op.getOperand(0))->getZExtValue();
+ DebugLoc DL = Op.getDebugLoc();
+ EVT VT = Op.getValueType();
+
+ switch (IntrinsicID) {
+default: return Op;
+case AMDGPUIntrinsic::AMDIL_max:
+ return DAG.getNode(AMDGPUISD::FMAX, DL, VT, Op.getOperand(1),
+ Op.getOperand(2));
+case AMDGPUIntrinsic::AMDGPU_imax:
+ return DAG.getNode(AMDGPUISD::SMAX, DL, VT, Op.getOperand(1),
+ Op.getOperand(2));
+case AMDGPUIntrinsic::AMDGPU_umax:
+ return DAG.getNode(AMDGPUISD::UMAX, DL, VT, Op.getOperand(1),
+ Op.getOperand(2));
+ }
}
void AMDGPUTargetLowering::addLiveIn(MachineInstr * MI,
@@ -29,3 +62,15 @@ void AMDGPUTargetLowering::addLiveIn(MachineInstr * MI,
AMDGPU::utilAddLiveIn(MF, MRI, TII, reg, MI->getOperand(0).getReg());
}
+#define NODE_NAME_CASE(node) case AMDGPUISD::node: return #node;
+
+const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const
+{
+ switch (Opcode) {
+ default: return AMDILTargetLowering::getTargetNodeName(Opcode);
+
+ NODE_NAME_CASE(FMAX)
+ NODE_NAME_CASE(SMAX)
+ NODE_NAME_CASE(UMAX)
+ }
+}
diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.h
b/src/gallium/drivers/radeon/AMDGPUISelLowering.h
index 16adf1b..b67f30b 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.h
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.h
@@ -21,6 +21,9 @@ namespace llvm {
class AMDGPUTargetLowering : public AMDILTargetLowering
{
+private:
+ SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
+
protected:
/// addLiveIn - This functions adds reg to the live in list of the entry
block
@@ -36,8 +39,26 @@ protected:
public:
AMDGPUTargetLowering(TargetMachine &TM);
+ virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
+ virtual const char* getTargetNodeName(unsigned Opcode) const;
+
};
+namespace AMDGPUISD
+{
+
+enum
+{
+ AMDGPU_FIRST = AMDILISD::LAST_NON_MEMORY_OPCODE,
+ FMAX,
+ SMAX,
+ UMAX,
+ LAST_AMDGPU_ISD_NUMBER
+};
+
+
+} // End namespace AMDGPUISD
+
} // End namespace llvm
#endif // AMDGPUISELLOWERING_H
diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.td
b/src/gallium/drivers/radeon/AMDGPUInstrInfo.td
new file mode 100644
index 000..abb1ebe
--- /dev/null
+++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.td
@@ -0,0 +1,31 @@
+//===-- AMDGPUInstrInfo.td - AMDGPU DAG nodes --*- tablegen
-*-===//
+//
+// The LLVM Compiler Infrastructure
+//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
+//===--===//
+//
+// This file contains DAG node defintions for the AMDGPU target.
+//
+//===
Mesa (master): state_tracker: remove sw_primitive_restart from st_context
Module: Mesa
Branch: master
Commit: 602913192db1beadd9cc4252ec9ec633cfe7a21b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=602913192db1beadd9cc4252ec9ec633cfe7a21b
Author: Jordan Justen
Date: Mon May 7 16:17:31 2012 -0700
state_tracker: remove sw_primitive_restart from st_context
The VBO module now can handle primitive restart in software
if required.
Signed-off-by: Jordan Justen
Reviewed-by: Ian Romanick
---
src/mesa/state_tracker/st_context.h|1 -
src/mesa/state_tracker/st_extensions.c |1 -
2 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/src/mesa/state_tracker/st_context.h
b/src/mesa/state_tracker/st_context.h
index 00a405b..55ae65b 100644
--- a/src/mesa/state_tracker/st_context.h
+++ b/src/mesa/state_tracker/st_context.h
@@ -79,7 +79,6 @@ struct st_context
struct draw_stage *feedback_stage; /**< For GL_FEEDBACK rendermode */
struct draw_stage *selection_stage; /**< For GL_SELECT rendermode */
struct draw_stage *rastpos_stage; /**< For glRasterPos */
- GLboolean sw_primitive_restart;
GLboolean clamp_frag_color_in_shader;
GLboolean clamp_vert_color_in_shader;
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index d0f392b..953155f 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -601,7 +601,6 @@ void st_init_extensions(struct st_context *st)
ctx->Extensions.NV_primitive_restart = GL_TRUE;
if (!screen->get_param(screen, PIPE_CAP_PRIMITIVE_RESTART)) {
- st->sw_primitive_restart = GL_TRUE;
ctx->Const.PrimitiveRestartInSoftware = GL_TRUE;
}
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Mesa (master): state_tracker: remove software handling of primitive restart
Module: Mesa
Branch: master
Commit: eef193560e5d59b1e38e01e2387e4b1897e05216
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eef193560e5d59b1e38e01e2387e4b1897e05216
Author: Jordan Justen
Date: Mon May 7 16:11:55 2012 -0700
state_tracker: remove software handling of primitive restart
The VBO module now can handle primitive restart in software
if required. Therefore this support is no londer required.
Signed-off-by: Jordan Justen
Reviewed-by: Ian Romanick
---
src/mesa/state_tracker/st_draw.c | 180 +-
1 files changed, 2 insertions(+), 178 deletions(-)
diff --git a/src/mesa/state_tracker/st_draw.c b/src/mesa/state_tracker/st_draw.c
index a8c20f4..6150e46 100644
--- a/src/mesa/state_tracker/st_draw.c
+++ b/src/mesa/state_tracker/st_draw.c
@@ -638,175 +638,6 @@ check_uniforms(struct gl_context *ctx)
}
-/*
- * Notes on primitive restart:
- * The code below is used when the gallium driver does not support primitive
- * restart itself. We map the index buffer, find the restart indexes, unmap
- * the index buffer then draw the sub-primitives delineated by the restarts.
- * A couple possible optimizations:
- * 1. Save the list of sub-primitive (start, count) values in a list attached
- *to the index buffer for re-use in subsequent draws. The list would be
- *invalidated when the contents of the buffer changed.
- * 2. If drawing triangle strips or quad strips, create a new index buffer
- *that uses duplicated vertices to render the disjoint strips as one
- *long strip. We'd have to be careful to avoid using too much memory
- *for this.
- * Finally, some apps might perform better if they don't use primitive restart
- * at all rather than this fallback path. Set MESA_EXTENSION_OVERRIDE to
- * "-GL_NV_primitive_restart" to test that.
- */
-
-
-struct sub_primitive
-{
- unsigned start, count;
-};
-
-
-/**
- * Scan the elements array to find restart indexes. Return a list
- * of primitive (start,count) pairs to indicate how to draw the sub-
- * primitives delineated by the restart index.
- */
-static struct sub_primitive *
-find_sub_primitives(const void *elements, unsigned element_size,
-unsigned start, unsigned end, unsigned restart_index,
-unsigned *num_sub_prims)
-{
- const unsigned max_prims = end - start;
- struct sub_primitive *sub_prims;
- unsigned i, cur_start, cur_count, num;
-
- sub_prims = (struct sub_primitive *)
- malloc(max_prims * sizeof(struct sub_primitive));
-
- if (!sub_prims) {
- *num_sub_prims = 0;
- return NULL;
- }
-
- cur_start = start;
- cur_count = 0;
- num = 0;
-
-#define SCAN_ELEMENTS(TYPE) \
- for (i = start; i < end; i++) { \
- if (((const TYPE *) elements)[i] == restart_index) { \
- if (cur_count > 0) { \
-assert(num < max_prims); \
-sub_prims[num].start = cur_start; \
-sub_prims[num].count = cur_count; \
-num++; \
- } \
- cur_start = i + 1; \
- cur_count = 0; \
- } \
- else { \
- cur_count++; \
- } \
- } \
- if (cur_count > 0) { \
- assert(num < max_prims); \
- sub_prims[num].start = cur_start; \
- sub_prims[num].count = cur_count; \
- num++; \
- }
-
- switch (element_size) {
- case 1:
- SCAN_ELEMENTS(ubyte);
- break;
- case 2:
- SCAN_ELEMENTS(ushort);
- break;
- case 4:
- SCAN_ELEMENTS(uint);
- break;
- default:
- assert(0 && "bad index_size in find_sub_primitives()");
- }
-
-#undef SCAN_ELEMENTS
-
- *num_sub_prims = num;
-
- return sub_prims;
-}
-
-
-/**
- * For gallium drivers that don't support the primitive restart
- * feature, handle it here by breaking up the indexed primitive into
- * sub-primitives.
- */
-static void
-handle_fallback_primitive_restart(struct cso_context *cso,
- struct pipe_context *pipe,
- const struct _mesa_index_buffer *ib,
- struct pipe_index_buffer *ibuffer,
- struct pipe_draw_info *orig_info)
-{
- const unsigned start = orig_info->start;
- const unsigned count = orig_info->count;
- struct pipe_draw_info info = *orig_info;
- struct pipe_transfer *transfer = NULL;
- unsigned instance, i;
- const void *ptr = NULL;
- struct sub_primitive *sub_prims;
- unsigned num_sub_prims;
-
- assert(info.indexed);
- assert(ibuffer->buffer || ibuffer->user_buffer);
- assert(ib);
-
- if (!ibuffer->buffer || !ibuffer->user_buffer || !ib)
- return;
-
- info.primitive_restart = FALSE;
- info.instance_count = 1;
-
- if (_mesa_is_bufferobj(ib->obj)) {
- ptr = pipe_buffer_map_range(pipe, ibuffer->buffer,
- start * ibuffer->index_size, /* start */
- count * ibuffer->index_size, /* length */
-
Mesa (master): state_tracker: set PrimitiveRestartInSoftware if needed
Module: Mesa
Branch: master
Commit: f16b39f05ce5aa2bc1bba01885d0061d9e63
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f16b39f05ce5aa2bc1bba01885d0061d9e63
Author: Jordan Justen
Date: Mon May 7 15:44:34 2012 -0700
state_tracker: set PrimitiveRestartInSoftware if needed
If the PIPE_CAP_PRIMITIVE_RESTART screen param is not set, then enable
PrimitiveRestartInSoftware to enable software primitive restart
support in the VBO module.
Signed-off-by: Jordan Justen
Reviewed-by: Ian Romanick
---
src/mesa/state_tracker/st_extensions.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index 1b4bca6..d0f392b 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -602,6 +602,7 @@ void st_init_extensions(struct st_context *st)
ctx->Extensions.NV_primitive_restart = GL_TRUE;
if (!screen->get_param(screen, PIPE_CAP_PRIMITIVE_RESTART)) {
st->sw_primitive_restart = GL_TRUE;
+ ctx->Const.PrimitiveRestartInSoftware = GL_TRUE;
}
if (screen->get_param(screen, PIPE_CAP_VERTEX_COLOR_UNCLAMPED)) {
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Mesa (master): vbo: use software primitive restart in the VBO module
Module: Mesa
Branch: master
Commit: 862667b6d96022d75046c765aa1e9d8846b9d313
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=862667b6d96022d75046c765aa1e9d8846b9d313
Author: Jordan Justen
Date: Mon May 7 15:50:21 2012 -0700
vbo: use software primitive restart in the VBO module
When PrimitiveRestartInSoftware is set, the VBO module will handle
primitive restart scenarios before calling the vbo->draw_prims
drawing function.
Signed-off-by: Jordan Justen
Reviewed-by: Ian Romanick
Reviewed-by: Kenneth Graunke
---
src/mesa/vbo/vbo_exec_array.c | 43 +++-
1 files changed, 37 insertions(+), 6 deletions(-)
diff --git a/src/mesa/vbo/vbo_exec_array.c b/src/mesa/vbo/vbo_exec_array.c
index 9303ad7..3fb7c64 100644
--- a/src/mesa/vbo/vbo_exec_array.c
+++ b/src/mesa/vbo/vbo_exec_array.c
@@ -543,6 +543,37 @@ vbo_bind_arrays(struct gl_context *ctx)
/**
+ * Handle a draw case that potentially has primitive restart enabled.
+ *
+ * If primitive restart is enabled, and PrimitiveRestartInSoftware is
+ * set, then vbo_sw_primitive_restart is used to handle the primitive
+ * restart case in software.
+ */
+static void
+vbo_handle_primitive_restart(struct gl_context *ctx,
+ const struct _mesa_prim *prim,
+ GLuint nr_prims,
+ const struct _mesa_index_buffer *ib,
+ GLboolean index_bounds_valid,
+ GLuint min_index,
+ GLuint max_index)
+{
+ struct vbo_context *vbo = vbo_context(ctx);
+
+ if ((ib != NULL) &&
+ ctx->Const.PrimitiveRestartInSoftware &&
+ ctx->Array.PrimitiveRestart) {
+ /* Handle primitive restart in software */
+ vbo_sw_primitive_restart(ctx, prim, nr_prims, ib);
+ } else {
+ /* Call driver directly for draw_prims */
+ vbo->draw_prims(ctx, prim, nr_prims, ib,
+ index_bounds_valid, min_index, max_index, NULL);
+ }
+}
+
+
+/**
* Helper function called by the other DrawArrays() functions below.
* This is where we handle primitive restart for drawing non-indexed
* arrays. If primitive restart is enabled, it typically means
@@ -805,8 +836,8 @@ vbo_validated_drawrangeelements(struct gl_context *ctx,
GLenum mode,
*/
check_buffers_are_unmapped(exec->array.inputs);
- vbo->draw_prims( ctx, prim, 1, &ib,
- index_bounds_valid, start, end, NULL );
+ vbo_handle_primitive_restart(ctx, prim, 1, &ib,
+index_bounds_valid, start, end);
if (MESA_DEBUG_FLAGS & DEBUG_ALWAYS_FLUSH) {
_mesa_flush(ctx);
@@ -1104,8 +1135,8 @@ vbo_validated_multidrawelements(struct gl_context *ctx,
GLenum mode,
}
check_buffers_are_unmapped(exec->array.inputs);
- vbo->draw_prims(ctx, prim, primcount, &ib,
- GL_FALSE, ~0, ~0, NULL);
+ vbo_handle_primitive_restart(ctx, prim, primcount, &ib,
+ GL_FALSE, ~0, ~0);
} else {
/* render one prim at a time */
for (i = 0; i < primcount; i++) {
@@ -1129,8 +1160,8 @@ vbo_validated_multidrawelements(struct gl_context *ctx,
GLenum mode,
prim[0].basevertex = 0;
check_buffers_are_unmapped(exec->array.inputs);
- vbo->draw_prims(ctx, prim, 1, &ib,
- GL_FALSE, ~0, ~0, NULL);
+ vbo_handle_primitive_restart(ctx, prim, 1, &ib,
+ GL_FALSE, ~0, ~0);
}
}
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Mesa (master): mesa: add PrimitiveRestartInSoftware to gl_context.Const
Module: Mesa Branch: master Commit: fc22fde9d8ba633f9f13ea0c46baa1c826d1377f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc22fde9d8ba633f9f13ea0c46baa1c826d1377f Author: Jordan Justen Date: Mon May 7 15:39:31 2012 -0700 mesa: add PrimitiveRestartInSoftware to gl_context.Const If set, then the VBO module will handle all primitive restart scenarios before calling the driver draw_prims. Software primitive restart support is disabled by default. Signed-off-by: Jordan Justen Reviewed-by: Ian Romanick Reviewed-by: Kenneth Graunke --- src/mesa/main/context.c |3 +++ src/mesa/main/mtypes.h |5 + 2 files changed, 8 insertions(+), 0 deletions(-) diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c index bafd250..df0452c 100644 --- a/src/mesa/main/context.c +++ b/src/mesa/main/context.c @@ -662,6 +662,9 @@ _mesa_init_constants(struct gl_context *ctx) /* GL_ARB_robustness */ ctx->Const.ResetStrategy = GL_NO_RESET_NOTIFICATION_ARB; + + /* PrimitiveRestart */ + ctx->Const.PrimitiveRestartInSoftware = GL_FALSE; } diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h index c306ac6..aa1a8ef 100644 --- a/src/mesa/main/mtypes.h +++ b/src/mesa/main/mtypes.h @@ -2845,6 +2845,11 @@ struct gl_constants */ GLboolean GLSLSkipStrictMaxVaryingLimitCheck; GLboolean GLSLSkipStrictMaxUniformLimitCheck; + + /** +* Force software support for primitive restart in the VBO module. +*/ + GLboolean PrimitiveRestartInSoftware; }; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): vbo: add software primitive restart support
Module: Mesa
Branch: master
Commit: bc8e0f5b0ff82c919ed1ee67e4fad55705937b30
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bc8e0f5b0ff82c919ed1ee67e4fad55705937b30
Author: Jordan Justen
Date: Mon May 7 15:50:21 2012 -0700
vbo: add software primitive restart support
vbo_sw_primitive_restart implements primitive restart in software
by splitting primitive draws apart.
This is based on similar support in mesa/state_tracker/st_draw.c.
Signed-off-by: Jordan Justen
Reviewed-by: Ian Romanick
Reviewed-by: Kenneth Graunke
---
src/mesa/SConscript |1 +
src/mesa/sources.mak |1 +
src/mesa/vbo/vbo.h |6 +
src/mesa/vbo/vbo_primitive_restart.c | 233 ++
4 files changed, 241 insertions(+), 0 deletions(-)
diff --git a/src/mesa/SConscript b/src/mesa/SConscript
index dc37a67..d7932c7 100644
--- a/src/mesa/SConscript
+++ b/src/mesa/SConscript
@@ -215,6 +215,7 @@ vbo_sources = [
'vbo/vbo_exec_draw.c',
'vbo/vbo_exec_eval.c',
'vbo/vbo_noop.c',
+'vbo/vbo_primitive_restart.c',
'vbo/vbo_rebase.c',
'vbo/vbo_split.c',
'vbo/vbo_split_copy.c',
diff --git a/src/mesa/sources.mak b/src/mesa/sources.mak
index c746b8a..19a05ec 100644
--- a/src/mesa/sources.mak
+++ b/src/mesa/sources.mak
@@ -184,6 +184,7 @@ VBO_SOURCES = \
vbo/vbo_exec_draw.c \
vbo/vbo_exec_eval.c \
vbo/vbo_noop.c \
+ vbo/vbo_primitive_restart.c \
vbo/vbo_rebase.c \
vbo/vbo_split.c \
vbo/vbo_split_copy.c \
diff --git a/src/mesa/vbo/vbo.h b/src/mesa/vbo/vbo.h
index 3cff898..4387e10 100644
--- a/src/mesa/vbo/vbo.h
+++ b/src/mesa/vbo/vbo.h
@@ -157,6 +157,12 @@ void vbo_bind_arrays(struct gl_context *ctx);
size_t
count_tessellated_primitives(const struct _mesa_prim *prim);
+void
+vbo_sw_primitive_restart(struct gl_context *ctx,
+ const struct _mesa_prim *prim,
+ GLuint nr_prims,
+ const struct _mesa_index_buffer *ib);
+
void GLAPIENTRY
_es_Color4f(GLfloat r, GLfloat g, GLfloat b, GLfloat a);
diff --git a/src/mesa/vbo/vbo_primitive_restart.c
b/src/mesa/vbo/vbo_primitive_restart.c
new file mode 100644
index 000..18d851c
--- /dev/null
+++ b/src/mesa/vbo/vbo_primitive_restart.c
@@ -0,0 +1,233 @@
+/*
+ * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
+ * All Rights Reserved.
+ *
+ * Copyright © 2012 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ *
+ * Authors:
+ *Jordan Justen
+ *
+ */
+
+#include "main/imports.h"
+#include "main/bufferobj.h"
+#include "main/macros.h"
+
+#include "vbo.h"
+#include "vbo_context.h"
+
+#define UPDATE_MIN2(a, b) (a) = MIN2((a), (b))
+#define UPDATE_MAX2(a, b) (a) = MAX2((a), (b))
+
+/*
+ * Notes on primitive restart:
+ * The code below is used when the driver does not support primitive
+ * restart itself. (ctx->Const.PrimitiveRestartInSoftware == GL_TRUE)
+ *
+ * We map the index buffer, find the restart indexes, unmap
+ * the index buffer then draw the sub-primitives delineated by the restarts.
+ *
+ * A couple possible optimizations:
+ * 1. Save the list of sub-primitive (start, count) values in a list attached
+ *to the index buffer for re-use in subsequent draws. The list would be
+ *invalidated when the contents of the buffer changed.
+ * 2. If drawing triangle strips or quad strips, create a new index buffer
+ *that uses duplicated vertices to render the disjoint strips as one
+ *long strip. We'd have to be careful to avoid using too much memory
+ *for this.
+ *
+ * Finally, some apps might perform better if they don't use primitive restart
+ * at all rather than this fallback path. Set MESA_EXTENSION_OVERRIDE to
+ * "-GL_NV_primitive_restart" to test that.
+ */
+
+
+struct sub_primitive
+{
+ GLuint start;
+ GLuint count;
+ GLuint
Mesa (master): mesa: Check for framebuffer completeness before looking at the rb.
Module: Mesa
Branch: master
Commit: 5a827d9a2b5d698fed98a5d62ff0292b48bdd6c7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a827d9a2b5d698fed98a5d62ff0292b48bdd6c7
Author: Eric Anholt
Date: Mon May 14 10:18:23 2012 -0700
mesa: Check for framebuffer completeness before looking at the rb.
Otherwise, an incomplete framebuffer could have a NULL
_ColorReadBuffer and we'd deref that.
Reviewed-by: Brian Paul
Reviewed-by: Kenneth Graunke
Reviewed-by: Ian Romanick
---
src/mesa/main/readpix.c | 12 ++--
1 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c
index 31acfcb..1381110 100644
--- a/src/mesa/main/readpix.c
+++ b/src/mesa/main/readpix.c
@@ -701,6 +701,12 @@ _mesa_ReadnPixelsARB( GLint x, GLint y, GLsizei width,
GLsizei height,
return;
}
+ if (ctx->ReadBuffer->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) {
+ _mesa_error(ctx, GL_INVALID_FRAMEBUFFER_OPERATION_EXT,
+ "glReadPixels(incomplete framebuffer)" );
+ return;
+ }
+
/* Check that the destination format and source buffer are both
* integer-valued or both non-integer-valued.
*/
@@ -715,12 +721,6 @@ _mesa_ReadnPixelsARB( GLint x, GLint y, GLsizei width,
GLsizei height,
}
}
- if (ctx->ReadBuffer->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) {
- _mesa_error(ctx, GL_INVALID_FRAMEBUFFER_OPERATION_EXT,
- "glReadPixels(incomplete framebuffer)" );
- return;
- }
-
if (ctx->ReadBuffer->Name != 0 && ctx->ReadBuffer->Visual.samples > 0) {
_mesa_error(ctx, GL_INVALID_OPERATION, "glReadPixels(multisample FBO)");
return;
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Mesa (master): mesa: Fix assertion failure when a cube face is not present.
Module: Mesa
Branch: master
Commit: 8b7ba92605c0f21cf6292a1bc2e16e379c0b3be8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b7ba92605c0f21cf6292a1bc2e16e379c0b3be8
Author: Eric Anholt
Date: Mon May 14 10:15:52 2012 -0700
mesa: Fix assertion failure when a cube face is not present.
Reviewed-by: Brian Paul
Reviewed-by: Kenneth Graunke
Reviewed-by: Ian Romanick
---
src/mesa/main/texobj.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/mesa/main/texobj.c b/src/mesa/main/texobj.c
index 365169d..a471bad 100644
--- a/src/mesa/main/texobj.c
+++ b/src/mesa/main/texobj.c
@@ -558,7 +558,8 @@ _mesa_test_texobj_completeness( const struct gl_context
*ctx,
GLuint face;
assert(baseImage->Width2 == baseImage->Height);
for (face = 1; face < 6; face++) {
- assert(t->Image[face][baseLevel]->Width2 ==
+ assert(t->Image[face][baseLevel] == NULL ||
+t->Image[face][baseLevel]->Width2 ==
t->Image[face][baseLevel]->Height2);
if (t->Image[face][baseLevel] == NULL ||
t->Image[face][baseLevel]->Width2 != baseImage->Width2) {
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Mesa (master): glsl: Drop the extra NULL specifiction on ir_assignment constructors.
Module: Mesa Branch: master Commit: aa5ec137757323b424d0f2638c50c93b9b06 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=aa5ec137757323b424d0f2638c50c93b9b06 Author: Eric Anholt Date: Mon May 14 09:14:54 2012 -0700 glsl: Drop the extra NULL specifiction on ir_assignment constructors. It's an implied argument, and I don't think being explicit about it helps. Reviewed-by: Kenneth Graunke Reviewed-by: Ian Romanick --- src/glsl/ast_to_hir.cpp | 35 ++- 1 files changed, 14 insertions(+), 21 deletions(-) diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp index 998f8dd..e23718b 100644 --- a/src/glsl/ast_to_hir.cpp +++ b/src/glsl/ast_to_hir.cpp @@ -760,13 +760,11 @@ do_assignment(exec_list *instructions, struct _mesa_glsl_parse_state *state, ir_var_temporary); ir_dereference_variable *deref_var = new(ctx) ir_dereference_variable(var); instructions->push_tail(var); - instructions->push_tail(new(ctx) ir_assignment(deref_var, - rhs, - NULL)); + instructions->push_tail(new(ctx) ir_assignment(deref_var, rhs)); deref_var = new(ctx) ir_dereference_variable(var); if (!error_emitted) - instructions->push_tail(new(ctx) ir_assignment(lhs, deref_var, NULL)); + instructions->push_tail(new(ctx) ir_assignment(lhs, deref_var)); return new(ctx) ir_dereference_variable(var); } @@ -783,7 +781,7 @@ get_lvalue_copy(exec_list *instructions, ir_rvalue *lvalue) var->mode = ir_var_auto; instructions->push_tail(new(ctx) ir_assignment(new(ctx) ir_dereference_variable(var), - lvalue, NULL)); + lvalue)); return new(ctx) ir_dereference_variable(var); } @@ -1223,12 +1221,12 @@ ast_expression::hir(exec_list *instructions, stmt->then_instructions.append_list(&rhs_instructions); ir_dereference *const then_deref = new(ctx) ir_dereference_variable(tmp); ir_assignment *const then_assign = - new(ctx) ir_assignment(then_deref, op[1], NULL); + new(ctx) ir_assignment(then_deref, op[1]); stmt->then_instructions.push_tail(then_assign); ir_dereference *const else_deref = new(ctx) ir_dereference_variable(tmp); ir_assignment *const else_assign = - new(ctx) ir_assignment(else_deref, new(ctx) ir_constant(false), NULL); + new(ctx) ir_assignment(else_deref, new(ctx) ir_constant(false)); stmt->else_instructions.push_tail(else_assign); result = new(ctx) ir_dereference_variable(tmp); @@ -1258,13 +1256,13 @@ ast_expression::hir(exec_list *instructions, ir_dereference *const then_deref = new(ctx) ir_dereference_variable(tmp); ir_assignment *const then_assign = - new(ctx) ir_assignment(then_deref, new(ctx) ir_constant(true), NULL); + new(ctx) ir_assignment(then_deref, new(ctx) ir_constant(true)); stmt->then_instructions.push_tail(then_assign); stmt->else_instructions.append_list(&rhs_instructions); ir_dereference *const else_deref = new(ctx) ir_dereference_variable(tmp); ir_assignment *const else_assign = - new(ctx) ir_assignment(else_deref, op[1], NULL); + new(ctx) ir_assignment(else_deref, op[1]); stmt->else_instructions.push_tail(else_assign); result = new(ctx) ir_dereference_variable(tmp); @@ -1452,14 +1450,14 @@ ast_expression::hir(exec_list *instructions, ir_dereference *const then_deref = new(ctx) ir_dereference_variable(tmp); ir_assignment *const then_assign = - new(ctx) ir_assignment(then_deref, op[1], NULL); + new(ctx) ir_assignment(then_deref, op[1]); stmt->then_instructions.push_tail(then_assign); else_instructions.move_nodes_to(& stmt->else_instructions); ir_dereference *const else_deref = new(ctx) ir_dereference_variable(tmp); ir_assignment *const else_assign = - new(ctx) ir_assignment(else_deref, op[2], NULL); + new(ctx) ir_assignment(else_deref, op[2]); stmt->else_instructions.push_tail(else_assign); result = new(ctx) ir_dereference_variable(tmp); @@ -3438,9 +3436,7 @@ ast_jump_statement::hir(exec_list *instructions, new(ctx) ir_dereference_variable(is_break_var); ir_constant *const true_val = new(ctx) ir_constant(true); ir_assignment *const set_break_var = - new(ctx) ir_assignment(deref_is_break_var, - true_val, - NULL); + new(ctx) ir_assignment(deref_is_break_var, true_val); instructions->push_tail(set_break_var); } @@ -3554,8 +3550,7 @@ ast_switch
Mesa (master): glsl: Fix assertion failure on handling switch on uint expressions.
Module: Mesa Branch: master Commit: 9c4e9ce051bb43861adb4f8cd8e88a733c2f3ed1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9c4e9ce051bb43861adb4f8cd8e88a733c2f3ed1 Author: Eric Anholt Date: Mon May 14 08:51:03 2012 -0700 glsl: Fix assertion failure on handling switch on uint expressions. Fixes piglit glsl-1.30/execution/switch/fs-uint. Reviewed-by: Kenneth Graunke Reviewed-by: Ian Romanick --- src/glsl/ast_to_hir.cpp |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp index c59e5e6..998f8dd 100644 --- a/src/glsl/ast_to_hir.cpp +++ b/src/glsl/ast_to_hir.cpp @@ -3599,7 +3599,7 @@ ast_switch_statement::test_to_hir(exec_list *instructions, test_expression->hir(instructions, state); - state->switch_state.test_var = new(ctx) ir_variable(glsl_type::int_type, + state->switch_state.test_var = new(ctx) ir_variable(test_val->type, "switch_test_tmp", ir_var_temporary); ir_dereference_variable *deref_test_var = ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl: Reject non-scalar switch expressions.
Module: Mesa
Branch: master
Commit: bbbc7c7d566905920967f56648fc26abcb37f4a1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bbbc7c7d566905920967f56648fc26abcb37f4a1
Author: Eric Anholt
Date: Mon May 14 08:45:59 2012 -0700
glsl: Reject non-scalar switch expressions.
The comment quotes spec saying that only scalar integers are allowed,
but we only checked for integer.
Fixes piglit switch-expression-const-ivec2.vert
Reviewed-by: Kenneth Graunke
Reviewed-by: Ian Romanick
---
src/glsl/ast_to_hir.cpp |6 ++
1 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 513908a..c59e5e6 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -3521,11 +3521,9 @@ ast_switch_statement::hir(exec_list *instructions,
*
*"The type of init-expression in a switch statement must be a
* scalar integer."
-*
-* The checks are separated so that higher quality diagnostics can be
-* generated for cases where the rule is violated.
*/
- if (!test_expression->type->is_integer()) {
+ if (!test_expression->type->is_scalar() ||
+ !test_expression->type->is_integer()) {
YYLTYPE loc = this->test_expression->get_location();
_mesa_glsl_error(& loc,
___
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Mesa (master): glsl: Let the constructor figure out the types of switch-related expressions.
Module: Mesa Branch: master Commit: 5d6ea16dfe99e1aba61c25a897b66951faab1a39 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d6ea16dfe99e1aba61c25a897b66951faab1a39 Author: Eric Anholt Date: Mon May 14 08:39:54 2012 -0700 glsl: Let the constructor figure out the types of switch-related expressions. I noticed this while unindenting the code. Reviewed-by: Kenneth Graunke Reviewed-by: Ian Romanick --- src/glsl/ast_to_hir.cpp |5 + 1 files changed, 1 insertions(+), 4 deletions(-) diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp index 9252df1..513908a 100644 --- a/src/glsl/ast_to_hir.cpp +++ b/src/glsl/ast_to_hir.cpp @@ -3731,7 +3731,6 @@ ast_case_label::hir(exec_list *instructions, new(ctx) ir_dereference_variable(state->switch_state.test_var); ir_rvalue *const test_cond = new(ctx) ir_expression(ir_binop_all_equal, - glsl_type::bool_type, label_const, deref_test_var); @@ -3788,9 +3787,7 @@ ast_iteration_statement::condition_to_hir(ir_loop *stmt, * like 'if (!condition) break;' as the loop termination condition. */ ir_rvalue *const not_cond = - new(ctx) ir_expression(ir_unop_logic_not, glsl_type::bool_type, - cond, - NULL); + new(ctx) ir_expression(ir_unop_logic_not, cond); ir_if *const if_stmt = new(ctx) ir_if(not_cond); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl: Fix indentation of switch code.
Module: Mesa
Branch: master
Commit: 5462f3679ab7217d3a3be48365750801c7771237
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5462f3679ab7217d3a3be48365750801c7771237
Author: Eric Anholt
Date: Mon May 14 08:37:50 2012 -0700
glsl: Fix indentation of switch code.
I managed to completely trash it in 22d81f15.
Reviewed-by: Kenneth Graunke
Reviewed-by: Ian Romanick
---
src/glsl/ast_to_hir.cpp | 547 +++
1 files changed, 264 insertions(+), 283 deletions(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 86bb874..9252df1 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -3576,7 +3576,7 @@ ast_switch_statement::hir(exec_list *instructions,
/* Cache test expression.
*/
test_to_hir(instructions, state);
-
+
/* Emit code for body of switch stmt.
*/
body->hir(instructions, state);
@@ -3585,290 +3585,271 @@ ast_switch_statement::hir(exec_list *instructions,
state->switch_state = saved;
- /* Switch statements do not have r-values.
- */
- return NULL;
- }
-
-
- void
- ast_switch_statement::test_to_hir(exec_list *instructions,
- struct _mesa_glsl_parse_state *state)
- {
- void *ctx = state;
-
- /* Cache value of test expression.
- */
- ir_rvalue *const test_val =
- test_expression->hir(instructions,
-state);
-
- state->switch_state.test_var = new(ctx) ir_variable(glsl_type::int_type,
-"switch_test_tmp",
-ir_var_temporary);
- ir_dereference_variable *deref_test_var =
- new(ctx) ir_dereference_variable(state->switch_state.test_var);
-
- instructions->push_tail(state->switch_state.test_var);
- instructions->push_tail(new(ctx) ir_assignment(deref_test_var,
- test_val,
- NULL));
- }
-
-
- ir_rvalue *
- ast_switch_body::hir(exec_list *instructions,
- struct _mesa_glsl_parse_state *state)
- {
- if (stmts != NULL)
- stmts->hir(instructions, state);
-
- /* Switch bodies do not have r-values.
- */
- return NULL;
- }
-
-
- ir_rvalue *
- ast_case_statement_list::hir(exec_list *instructions,
- struct _mesa_glsl_parse_state *state)
- {
- foreach_list_typed (ast_case_statement, case_stmt, link, & this->cases)
- case_stmt->hir(instructions, state);
-
- /* Case statements do not have r-values.
- */
- return NULL;
- }
-
-
- ir_rvalue *
- ast_case_statement::hir(exec_list *instructions,
- struct _mesa_glsl_parse_state *state)
- {
- labels->hir(instructions, state);
-
- /* Conditionally set fallthru state based on break state.
- */
- ir_constant *const false_val = new(state) ir_constant(false);
- ir_dereference_variable *const deref_is_fallthru_var =
- new(state) ir_dereference_variable(state->switch_state.is_fallthru_var);
- ir_dereference_variable *const deref_is_break_var =
- new(state) ir_dereference_variable(state->switch_state.is_break_var);
- ir_assignment *const reset_fallthru_on_break =
- new(state) ir_assignment(deref_is_fallthru_var,
-false_val,
-deref_is_break_var);
- instructions->push_tail(reset_fallthru_on_break);
-
- /* Guard case statements depending on fallthru state.
- */
- ir_dereference_variable *const deref_fallthru_guard =
- new(state) ir_dereference_variable(state->switch_state.is_fallthru_var);
- ir_if *const test_fallthru = new(state) ir_if(deref_fallthru_guard);
-
- foreach_list_typed (ast_node, stmt, link, & this->stmts)
- stmt->hir(& test_fallthru->then_instructions, state);
-
- instructions->push_tail(test_fallthru);
-
- /* Case statements do not have r-values.
- */
- return NULL;
- }
-
-
- ir_rvalue *
- ast_case_label_list::hir(exec_list *instructions,
- struct _mesa_glsl_parse_state *state)
- {
- foreach_list_typed (ast_case_label, label, link, & this->labels)
- label->hir(instructions, state);
-
- /* Case labels do not have r-values.
- */
- return NULL;
- }
-
-
- ir_rvalue *
- ast_case_label::hir(exec_list *instructions,
- struct _mesa_glsl_parse_state *state)
- {
- void *ctx = state;
-
- ir_dereference_variable *deref_fallthru_var =
- new(ctx) ir_dereference_variable(state->switch_state.is_fallthru_var);
-
- ir_rvalue *const true_val = new(ctx) ir_constant(true);
-
- /* If not default case, ...
- */
- if (this->test_value != NULL) {
- /* Conditionally set fallthru state based on
-* comparison of cached test expression value to
Mesa (master): i965/vs: Fix up swizzle for dereference_array of matrices.
Module: Mesa Branch: master Commit: aa02884c4fdcbc20cf7ac89ec50f9d6c8d1e1682 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=aa02884c4fdcbc20cf7ac89ec50f9d6c8d1e1682 Author: Eric Anholt Date: Thu May 10 15:38:11 2012 -0700 i965/vs: Fix up swizzle for dereference_array of matrices. Fixes assertion failure in piglit: vs-mat2-struct-assignment.shader_test vs-mat2-array-assignment.shader_test Reviewed-by: Kenneth Graunke Reviewed-by: Ian Romanick --- src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp index a7d71b3..c2b1033 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp @@ -1454,7 +1454,7 @@ vec4_visitor::visit(ir_dereference_array *ir) } /* If the type is smaller than a vec4, replicate the last channel out. */ - if (ir->type->is_scalar() || ir->type->is_vector()) + if (ir->type->is_scalar() || ir->type->is_vector() || ir->type->is_matrix()) src.swizzle = swizzle_for_size(ir->type->vector_elements); else src.swizzle = BRW_SWIZZLE_NOOP; @@ -1479,7 +1479,7 @@ vec4_visitor::visit(ir_dereference_record *ir) } /* If the type is smaller than a vec4, replicate the last channel out. */ - if (ir->type->is_scalar() || ir->type->is_vector()) + if (ir->type->is_scalar() || ir->type->is_vector() || ir->type->is_matrix()) this->result.swizzle = swizzle_for_size(ir->type->vector_elements); else this->result.swizzle = BRW_SWIZZLE_NOOP; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa: Throw error on glGetActiveUniform inside Begin/End.
Module: Mesa Branch: master Commit: ef691885c92abcd085d89fc30feeda87961773ab URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef691885c92abcd085d89fc30feeda87961773ab Author: Eric Anholt Date: Thu May 10 14:56:48 2012 -0700 mesa: Throw error on glGetActiveUniform inside Begin/End. Fixes piglit GL_ARB_shader_objeccts/getactiveuniform-beginend. Reviewed-by: Brian Paul Reviewed-by: Kenneth Graunke Reviewed-by: Ian Romanick --- src/mesa/main/uniform_query.cpp |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp index 08d330a..f5d998f 100644 --- a/src/mesa/main/uniform_query.cpp +++ b/src/mesa/main/uniform_query.cpp @@ -46,6 +46,8 @@ _mesa_GetActiveUniformARB(GLhandleARB program, GLuint index, struct gl_shader_program *shProg = _mesa_lookup_shader_program_err(ctx, program, "glGetActiveUniform"); + ASSERT_OUTSIDE_BEGIN_END(ctx); + if (!shProg) return; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl: Improve the local dead code optimization to eliminate unused channels.
Module: Mesa
Branch: master
Commit: 05c200bac049ed4760f0af6786e463e2520b9c9c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=05c200bac049ed4760f0af6786e463e2520b9c9c
Author: Eric Anholt
Date: Thu Feb 23 11:51:04 2012 -0800
glsl: Improve the local dead code optimization to eliminate unused channels.
Total instructions: 261582 -> 261316
135/2147 programs affected (6.3%)
36752 -> 36486 instructions in affected programs (0.7% reduction)
This excludes a tropics shader that now gets 16-wide mode and throws
off the numbers. 5 shaders are hurt: two extra MOVs in 4 tropics
shaders it looks like because we don't split register names according
to independent webs, and one gstreamer shader where it looks like
try_rewrite_rhs_to_dst() is falling on its face.
This should also help avoid a regression in VSes from idr's ARB
programs to GLSL work.
---
src/glsl/opt_dead_code_local.cpp | 147 --
1 files changed, 125 insertions(+), 22 deletions(-)
diff --git a/src/glsl/opt_dead_code_local.cpp b/src/glsl/opt_dead_code_local.cpp
index a81a38f..4af78a7 100644
--- a/src/glsl/opt_dead_code_local.cpp
+++ b/src/glsl/opt_dead_code_local.cpp
@@ -43,16 +43,20 @@ static bool debug = false;
class assignment_entry : public exec_node
{
public:
- assignment_entry(ir_variable *lhs, ir_instruction *ir)
+ assignment_entry(ir_variable *lhs, ir_assignment *ir)
{
assert(lhs);
assert(ir);
this->lhs = lhs;
this->ir = ir;
+ this->available = ir->write_mask;
}
ir_variable *lhs;
- ir_instruction *ir;
+ ir_assignment *ir;
+
+ /* bitmask of xyzw channels written that haven't been used so far. */
+ int available;
};
class kill_for_derefs_visitor : public ir_hierarchical_visitor {
@@ -62,23 +66,52 @@ public:
this->assignments = assignments;
}
- virtual ir_visitor_status visit(ir_dereference_variable *ir)
+ void kill_channels(ir_variable *const var, int used)
{
- ir_variable *const var = ir->variable_referenced();
-
foreach_iter(exec_list_iterator, iter, *this->assignments) {
assignment_entry *entry = (assignment_entry *)iter.get();
if (entry->lhs == var) {
- if (debug)
- printf("kill %s\n", entry->lhs->name);
- entry->remove();
+ if (var->type->is_scalar() || var->type->is_vector()) {
+ if (debug)
+ printf("kill %s (0x%01x - 0x%01x)\n", entry->lhs->name,
+entry->available, used);
+ entry->available &= ~used;
+ if (!entry->available)
+ entry->remove();
+ } else {
+ if (debug)
+ printf("kill %s\n", entry->lhs->name);
+ entry->remove();
+ }
}
}
+ }
+
+ virtual ir_visitor_status visit(ir_dereference_variable *ir)
+ {
+ kill_channels(ir->var, ~0);
return visit_continue;
}
+ virtual ir_visitor_status visit(ir_swizzle *ir)
+ {
+ ir_dereference_variable *deref = ir->val->as_dereference_variable();
+ if (!deref)
+return visit_continue;
+
+ int used = 0;
+ used |= 1 << ir->mask.x;
+ used |= 1 << ir->mask.y;
+ used |= 1 << ir->mask.z;
+ used |= 1 << ir->mask.w;
+
+ kill_channels(deref->var, used);
+
+ return visit_continue_with_parent;
+ }
+
private:
exec_list *assignments;
};
@@ -130,21 +163,91 @@ process_assignment(void *ctx, ir_assignment *ir,
exec_list *assignments)
assert(var);
/* Now, check if we did a whole-variable assignment. */
- if (!ir->condition && (ir->whole_variable_written() != NULL)) {
- /* We did a whole-variable assignment. So, any instruction in
- * the assignment list with the same LHS is dead.
- */
- if (debug)
-printf("looking for %s to remove\n", var->name);
- foreach_iter(exec_list_iterator, iter, *assignments) {
-assignment_entry *entry = (assignment_entry *)iter.get();
+ if (!ir->condition) {
+ ir_dereference_variable *deref_var = ir->lhs->as_dereference_variable();
-if (entry->lhs == var) {
- if (debug)
- printf("removing %s\n", var->name);
- entry->ir->remove();
- entry->remove();
- progress = true;
+ /* If it's a vector type, we can do per-channel elimination of
+ * use of the RHS.
+ */
+ if (deref_var && (deref_var->var->type->is_scalar() ||
+ deref_var->var->type->is_vector())) {
+
+if (debug)
+ printf("looking for %s.0x%01x to remove\n", var->name,
+ ir->write_mask);
+
+foreach_iter(exec_list_iterator, iter, *assignments) {
+ assignment_entry *entry = (assignment_entry *)iter.get();
+
+ if (entry->lhs != var)
+ continue;
+
+ int remove = entry->available & ir->write_mask;
+ if (debug) {
+
Mesa (master): i965/fs: Do more register coalescing by using the interference graph.
Module: Mesa
Branch: master
Commit: f220f73b9c5aca16ca21ea8f8718703b12cf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f220f73b9c5aca16ca21ea8f8718703b12cf
Author: Eric Anholt
Date: Tue May 8 10:18:20 2012 -0700
i965/fs: Do more register coalescing by using the interference graph.
By using the live variables code for determining interference, we can
handle coalescing in the presence of control flow, which the other
register coalescing path couldn't.
Total instructions: 207184 -> 206990
74/1246 programs affected (5.9%)
33993 -> 33799 instructions in affected programs (0.6% reduction)
There is a newerth shader that loses out, because of some extra MOVs
that now get their dead-code nature obscured by coalescing. This
should be fixed by doing better at dead code elimination.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 61 ++
src/mesa/drivers/dri/i965/brw_fs.h |1 +
2 files changed, 62 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 7176d40..313e720 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1218,6 +1218,66 @@ fs_visitor::dead_code_eliminate()
return progress;
}
+/**
+ * Implements a second type of register coalescing: This one checks if
+ * the two regs involved in a raw move don't interfere, in which case
+ * they can both by stored in the same place and the MOV removed.
+ */
+bool
+fs_visitor::register_coalesce_2()
+{
+ bool progress = false;
+
+ calculate_live_intervals();
+
+ foreach_list_safe(node, &this->instructions) {
+ fs_inst *inst = (fs_inst *)node;
+
+ if (inst->opcode != BRW_OPCODE_MOV ||
+ inst->predicated ||
+ inst->saturate ||
+ inst->src[0].file != GRF ||
+ inst->src[0].negate ||
+ inst->src[0].abs ||
+ inst->src[0].smear != -1 ||
+ inst->dst.file != GRF ||
+ inst->dst.type != inst->src[0].type ||
+ virtual_grf_sizes[inst->src[0].reg] != 1 ||
+ virtual_grf_interferes(inst->dst.reg, inst->src[0].reg)) {
+continue;
+ }
+
+ int reg_from = inst->src[0].reg;
+ assert(inst->src[0].reg_offset == 0);
+ int reg_to = inst->dst.reg;
+ int reg_to_offset = inst->dst.reg_offset;
+
+ foreach_list_safe(node, &this->instructions) {
+fs_inst *scan_inst = (fs_inst *)node;
+
+if (scan_inst->dst.file == GRF &&
+scan_inst->dst.reg == reg_from) {
+ scan_inst->dst.reg = reg_to;
+ scan_inst->dst.reg_offset = reg_to_offset;
+}
+for (int i = 0; i < 3; i++) {
+ if (scan_inst->src[i].file == GRF &&
+ scan_inst->src[i].reg == reg_from) {
+ scan_inst->src[i].reg = reg_to;
+ scan_inst->src[i].reg_offset = reg_to_offset;
+ }
+}
+ }
+
+ inst->remove();
+ live_intervals_valid = false;
+ progress = true;
+ continue;
+ }
+
+ return progress;
+}
+
bool
fs_visitor::register_coalesce()
{
@@ -1684,6 +1744,7 @@ fs_visitor::run()
progress = opt_cse() || progress;
progress = opt_copy_propagate() || progress;
progress = register_coalesce() || progress;
+progress = register_coalesce_2() || progress;
progress = compute_to_mrf() || progress;
progress = dead_code_eliminate() || progress;
} while (progress);
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index f04c6fc..d7fd9a4 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -495,6 +495,7 @@ public:
bool opt_copy_propagate_local(void *mem_ctx, fs_bblock *block,
exec_list *acp);
bool register_coalesce();
+ bool register_coalesce_2();
bool compute_to_mrf();
bool dead_code_eliminate();
bool remove_dead_constants();
___
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Mesa (8.0): intel: add PCI IDs for Ivy Bridge GT2 server variant
Module: Mesa Branch: 8.0 Commit: bf7407f631424d55354369cc66a9d27fcf888068 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf7407f631424d55354369cc66a9d27fcf888068 Author: Eugeni Dodonov Date: Sat Mar 31 12:38:59 2012 -0300 intel: add PCI IDs for Ivy Bridge GT2 server variant Those IDs are used by Bromolow. Reviewed-by: Kenneth Graunke Signed-off-by: Eugeni Dodonov (cherry picked from commit a45247fb1b8c30c5be21c3baf84943920ae17bfb) Conflicts: include/pci_ids/i965_pci_ids.h --- include/pci_ids/i965_pci_ids.h |1 + src/mesa/drivers/dri/intel/intel_chipset.h |4 +++- src/mesa/drivers/dri/intel/intel_context.c |1 + 3 files changed, 5 insertions(+), 1 deletions(-) diff --git a/include/pci_ids/i965_pci_ids.h b/include/pci_ids/i965_pci_ids.h index d37a2ee..7a54018 100644 --- a/include/pci_ids/i965_pci_ids.h +++ b/include/pci_ids/i965_pci_ids.h @@ -25,3 +25,4 @@ CHIPSET(0x0162, IVYBRIDGE_GT2, ivb_gt2) CHIPSET(0x0156, IVYBRIDGE_M_GT1, ivb_gt1) CHIPSET(0x0166, IVYBRIDGE_M_GT2, ivb_gt2) CHIPSET(0x015a, IVYBRIDGE_S_GT1, ivb_gt1) +CHIPSET(0x016a, IVYBRIDGE_S_GT2, ivb_gt2) diff --git a/src/mesa/drivers/dri/intel/intel_chipset.h b/src/mesa/drivers/dri/intel/intel_chipset.h index 2e9fb2d..1739abe 100644 --- a/src/mesa/drivers/dri/intel/intel_chipset.h +++ b/src/mesa/drivers/dri/intel/intel_chipset.h @@ -85,6 +85,7 @@ #define PCI_CHIP_IVYBRIDGE_M_GT10x0156 /* Mobile */ #define PCI_CHIP_IVYBRIDGE_M_GT20x0166 #define PCI_CHIP_IVYBRIDGE_S_GT10x015a /* Server */ +#define PCI_CHIP_IVYBRIDGE_S_GT20x016a #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ devid == PCI_CHIP_I915_GM || \ @@ -147,7 +148,8 @@ devid == PCI_CHIP_IVYBRIDGE_S_GT1) #define IS_IVB_GT2(devid) (devid == PCI_CHIP_IVYBRIDGE_GT2 || \ -devid == PCI_CHIP_IVYBRIDGE_M_GT2) +devid == PCI_CHIP_IVYBRIDGE_M_GT2 || \ +devid == PCI_CHIP_IVYBRIDGE_S_GT2) #define IS_IVYBRIDGE(devid) (IS_IVB_GT1(devid) || IS_IVB_GT2(devid)) diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c index 9cdd804..faf81ee 100644 --- a/src/mesa/drivers/dri/intel/intel_context.c +++ b/src/mesa/drivers/dri/intel/intel_context.c @@ -183,6 +183,7 @@ intelGetString(struct gl_context * ctx, GLenum name) chipset = "Intel(R) Ivybridge Mobile"; break; case PCI_CHIP_IVYBRIDGE_S_GT1: + case PCI_CHIP_IVYBRIDGE_S_GT2: chipset = "Intel(R) Ivybridge Server"; break; default: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nouveau: place static buffers in VRAM if preferred by the driver
Module: Mesa
Branch: master
Commit: 1befacc7647f51344f5cfbfa86b62e53625a436f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1befacc7647f51344f5cfbfa86b62e53625a436f
Author: Christoph Bumiller
Date: Thu May 17 14:43:47 2012 +0200
nouveau: place static buffers in VRAM if preferred by the driver
---
src/gallium/drivers/nouveau/nouveau_buffer.c | 29 ++---
src/gallium/drivers/nouveau/nouveau_screen.c | 10 +
src/gallium/drivers/nouveau/nouveau_screen.h |8 ++-
src/gallium/drivers/nv30/nv30_screen.c | 10 ++--
src/gallium/drivers/nv50/nv50_screen.c | 10 +++-
src/gallium/drivers/nvc0/nvc0_screen.c |7 -
6 files changed, 62 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nouveau_buffer.c
b/src/gallium/drivers/nouveau/nouveau_buffer.c
index c396e3c..d04ac2f 100644
--- a/src/gallium/drivers/nouveau/nouveau_buffer.c
+++ b/src/gallium/drivers/nouveau/nouveau_buffer.c
@@ -363,10 +363,31 @@ nouveau_buffer_create(struct pipe_screen *pscreen,
pipe_reference_init(&buffer->base.reference, 1);
buffer->base.screen = pscreen;
- if ((buffer->base.bind & screen->sysmem_bindings) ==
screen->sysmem_bindings)
- ret = nouveau_buffer_allocate(screen, buffer, 0);
- else
- ret = nouveau_buffer_allocate(screen, buffer, NOUVEAU_BO_GART);
+ if (buffer->base.bind &
+ (screen->vidmem_bindings & screen->sysmem_bindings)) {
+ switch (buffer->base.usage) {
+ case PIPE_USAGE_DEFAULT:
+ case PIPE_USAGE_IMMUTABLE:
+ case PIPE_USAGE_STATIC:
+ buffer->domain = NOUVEAU_BO_VRAM;
+ break;
+ case PIPE_USAGE_DYNAMIC:
+ case PIPE_USAGE_STAGING:
+ case PIPE_USAGE_STREAM:
+ buffer->domain = NOUVEAU_BO_GART;
+ break;
+ default:
+ assert(0);
+ break;
+ }
+ } else {
+ if (buffer->base.bind & screen->vidmem_bindings)
+ buffer->domain = NOUVEAU_BO_VRAM;
+ else
+ if (buffer->base.bind & screen->sysmem_bindings)
+ buffer->domain = NOUVEAU_BO_GART;
+ }
+ ret = nouveau_buffer_allocate(screen, buffer, buffer->domain);
if (ret == FALSE)
goto fail;
diff --git a/src/gallium/drivers/nouveau/nouveau_screen.c
b/src/gallium/drivers/nouveau/nouveau_screen.c
index 7437779..9baa68c 100644
--- a/src/gallium/drivers/nouveau/nouveau_screen.c
+++ b/src/gallium/drivers/nouveau/nouveau_screen.c
@@ -148,6 +148,16 @@ nouveau_screen_init(struct nouveau_screen *screen, struct
nouveau_device *dev)
util_format_s3tc_init();
+ screen->lowmem_bindings = PIPE_BIND_GLOBAL; /* gallium limit */
+ screen->vidmem_bindings =
+ PIPE_BIND_RENDER_TARGET | PIPE_BIND_DEPTH_STENCIL |
+ PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_CURSOR
|
+ PIPE_BIND_SAMPLER_VIEW |
+ PIPE_BIND_SHADER_RESOURCE | PIPE_BIND_COMPUTE_RESOURCE |
+ PIPE_BIND_GLOBAL;
+ screen->sysmem_bindings =
+ PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_STREAM_OUTPUT;
+
memset(&mm_config, 0, sizeof(mm_config));
screen->mm_GART = nouveau_mm_create(dev,
diff --git a/src/gallium/drivers/nouveau/nouveau_screen.h
b/src/gallium/drivers/nouveau/nouveau_screen.h
index 4ca286b..5a3cfab 100644
--- a/src/gallium/drivers/nouveau/nouveau_screen.h
+++ b/src/gallium/drivers/nouveau/nouveau_screen.h
@@ -17,7 +17,13 @@ struct nouveau_screen {
struct nouveau_client *client;
struct nouveau_pushbuf *pushbuf;
- unsigned sysmem_bindings;
+ unsigned vidmem_bindings; /* PIPE_BIND_* where VRAM placement is
desired */
+ unsigned sysmem_bindings; /* PIPE_BIND_* where GART placement is
desired */
+ unsigned lowmem_bindings; /* PIPE_BIND_* that require an address < 4
GiB */
+ /*
+* For bindings with (vidmem & sysmem) bits set set, PIPE_USAGE_*
decides
+* placement.
+*/
uint16_t class_3d;
diff --git a/src/gallium/drivers/nv30/nv30_screen.c
b/src/gallium/drivers/nv30/nv30_screen.c
index f5120e7..67de8c0 100644
--- a/src/gallium/drivers/nv30/nv30_screen.c
+++ b/src/gallium/drivers/nv30/nv30_screen.c
@@ -371,14 +371,18 @@ nv30_screen_create(struct nouveau_device *dev)
screen->base.fence.emit = nv30_screen_fence_emit;
screen->base.fence.update = nv30_screen_fence_update;
- screen->base.sysmem_bindings = PIPE_BIND_CONSTANT_BUFFER;
- if (oclass != NV40_3D_CLASS)
- screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
ret = nouveau_screen_init(&screen->base, dev);
if (ret)
FAIL_SCREEN_INIT("nv30_screen_init failed: %d\n", ret);
+ screen->base.vidmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
+ screen->base.sysmem_bindings |= PIPE_BIND_VERTEX_BUFFER;
+ if (oclass == NV40_3D_CLASS) {
+ screen->base.vidmem_bindings |= PIPE_BIND_INDEX_BUFFER;
+ screen->base.sysmem_bindings |= PIPE_BIND_INDEX_BUFFER;
+ }
+
fi
Mesa (master): nv50,nvc0: handle user index buffers
Module: Mesa
Branch: master
Commit: ef7bb281292c17b762b57779306e874704c87328
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef7bb281292c17b762b57779306e874704c87328
Author: Christoph Bumiller
Date: Wed May 16 20:54:23 2012 +0200
nv50,nvc0: handle user index buffers
---
src/gallium/drivers/nv50/nv50_push.c | 12
src/gallium/drivers/nv50/nv50_screen.c|2 +-
src/gallium/drivers/nv50/nv50_state.c |9 ++---
src/gallium/drivers/nv50/nv50_vbo.c | 25 ++---
src/gallium/drivers/nvc0/nvc0_screen.c|2 +-
src/gallium/drivers/nvc0/nvc0_state.c | 11 ---
src/gallium/drivers/nvc0/nvc0_vbo.c | 23 ---
src/gallium/drivers/nvc0/nvc0_vbo_translate.c | 12 +++-
8 files changed, 49 insertions(+), 47 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_push.c
b/src/gallium/drivers/nv50/nv50_push.c
index 3abe189..1f7bc76 100644
--- a/src/gallium/drivers/nv50/nv50_push.c
+++ b/src/gallium/drivers/nv50/nv50_push.c
@@ -13,7 +13,7 @@
struct push_context {
struct nouveau_pushbuf *push;
- void *idxbuf;
+ const void *idxbuf;
float edgeflag;
int edgeflag_attr;
@@ -234,9 +234,13 @@ nv50_push_vbo(struct nv50_context *nv50, const struct
pipe_draw_info *info)
}
if (info->indexed) {
- ctx.idxbuf = nouveau_resource_map_offset(&nv50->base,
-
nv04_resource(nv50->idxbuf.buffer),
- nv50->idxbuf.offset,
NOUVEAU_BO_RD);
+ if (nv50->idxbuf.buffer) {
+ ctx.idxbuf = nouveau_resource_map_offset(&nv50->base,
+nv04_resource(nv50->idxbuf.buffer), nv50->idxbuf.offset,
+NOUVEAU_BO_RD);
+ } else {
+ ctx.idxbuf = nv50->idxbuf.user_buffer;
+ }
if (!ctx.idxbuf)
return;
index_size = nv50->idxbuf.index_size;
diff --git a/src/gallium/drivers/nv50/nv50_screen.c
b/src/gallium/drivers/nv50/nv50_screen.c
index 9f356ff..1874f3e 100644
--- a/src/gallium/drivers/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nv50/nv50_screen.c
@@ -152,9 +152,9 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
case PIPE_CAP_TGSI_CAN_COMPACT_VARYINGS:
case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
case PIPE_CAP_USER_VERTEX_BUFFERS:
- case PIPE_CAP_USER_INDEX_BUFFERS:
return 0; /* state trackers will know better */
case PIPE_CAP_USER_CONSTANT_BUFFERS:
+ case PIPE_CAP_USER_INDEX_BUFFERS:
return 1;
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
return 256;
diff --git a/src/gallium/drivers/nv50/nv50_state.c
b/src/gallium/drivers/nv50/nv50_state.c
index eea3ffd..1e7d17a 100644
--- a/src/gallium/drivers/nv50/nv50_state.c
+++ b/src/gallium/drivers/nv50/nv50_state.c
@@ -911,12 +911,15 @@ nv50_set_index_buffer(struct pipe_context *pipe,
if (nv50->idxbuf.buffer)
nouveau_bufctx_reset(nv50->bufctx_3d, NV50_BIND_INDEX);
- if (ib && ib->buffer) {
+ if (ib) {
pipe_resource_reference(&nv50->idxbuf.buffer, ib->buffer);
- nv50->idxbuf.offset = ib->offset;
nv50->idxbuf.index_size = ib->index_size;
- if (nouveau_resource_mapped_by_gpu(ib->buffer))
+ if (ib->buffer) {
+ nv50->idxbuf.offset = ib->offset;
BCTX_REFN(nv50->bufctx_3d, INDEX, nv04_resource(ib->buffer), RD);
+ } else {
+ nv50->idxbuf.user_buffer = ib->user_buffer;
+ }
} else {
pipe_resource_reference(&nv50->idxbuf.buffer, NULL);
}
diff --git a/src/gallium/drivers/nv50/nv50_vbo.c
b/src/gallium/drivers/nv50/nv50_vbo.c
index 323677e..d21d699 100644
--- a/src/gallium/drivers/nv50/nv50_vbo.c
+++ b/src/gallium/drivers/nv50/nv50_vbo.c
@@ -454,7 +454,7 @@ nv50_draw_arrays(struct nv50_context *nv50,
}
static void
-nv50_draw_elements_inline_u08(struct nouveau_pushbuf *push, uint8_t *map,
+nv50_draw_elements_inline_u08(struct nouveau_pushbuf *push, const uint8_t *map,
unsigned start, unsigned count)
{
map += start;
@@ -480,7 +480,7 @@ nv50_draw_elements_inline_u08(struct nouveau_pushbuf *push,
uint8_t *map,
}
static void
-nv50_draw_elements_inline_u16(struct nouveau_pushbuf *push, uint16_t *map,
+nv50_draw_elements_inline_u16(struct nouveau_pushbuf *push, const uint16_t
*map,
unsigned start, unsigned count)
{
map += start;
@@ -503,7 +503,7 @@ nv50_draw_elements_inline_u16(struct nouveau_pushbuf *push,
uint16_t *map,
}
static void
-nv50_draw_elements_inline_u32(struct nouveau_pushbuf *push, uint32_t *map,
+nv50_draw_elements_inline_u32(struct nouveau_pushbuf *push, const uint32_t
*map,
unsigned start, unsigned count)
{
map += start;
@@ -520,7 +520,8 @@ nv50_draw_elements_inline_u32(struct nouveau_pushbuf *push,
uint32_t *map,
}
static void
-nv50_draw_elements_inline_u32_short(struct nouveau_
Mesa (master): nv50/ir: fix reversed order of lane ops in quadops
Module: Mesa
Branch: master
Commit: 717f55d79d9709a31e0f85a87f076ac13446701d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=717f55d79d9709a31e0f85a87f076ac13446701d
Author: Christoph Bumiller
Date: Wed May 9 20:32:44 2012 +0200
nv50/ir: fix reversed order of lane ops in quadops
---
.../drivers/nv50/codegen/nv50_ir_lowering_nv50.cpp |5 +++--
.../drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp |5 +++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/nv50/codegen/nv50_ir_lowering_nv50.cpp
b/src/gallium/drivers/nv50/codegen/nv50_ir_lowering_nv50.cpp
index 16bba0e..39e0cfa 100644
--- a/src/gallium/drivers/nv50/codegen/nv50_ir_lowering_nv50.cpp
+++ b/src/gallium/drivers/nv50/codegen/nv50_ir_lowering_nv50.cpp
@@ -109,9 +109,10 @@ expandIntegerMUL(BuildUtil *bld, Instruction *mul)
#define QOP_SUB 2
#define QOP_MOV2 3
+// UL UR LL LR
#define QUADOP(q, r, s, t)\
- ((QOP_##q << 0) | (QOP_##r << 2) | \
-(QOP_##s << 4) | (QOP_##t << 6))
+ ((QOP_##q << 6) | (QOP_##r << 4) | \
+(QOP_##s << 2) | (QOP_##t << 0))
class NV50LegalizePostRA : public Pass
{
diff --git a/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
b/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
index 900e998..8fd4541 100644
--- a/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp
@@ -34,9 +34,10 @@ namespace nv50_ir {
#define QOP_SUB 2
#define QOP_MOV2 3
+// UL UR LL LR
#define QUADOP(q, r, s, t) \
- ((QOP_##q << 0) | (QOP_##r << 2) | \
-(QOP_##s << 4) | (QOP_##t << 6))
+ ((QOP_##q << 6) | (QOP_##r << 4) | \
+(QOP_##s << 2) | (QOP_##t << 0))
class NVC0LegalizeSSA : public Pass
{
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Mesa (master): nv50,nvc0: handle user vertex buffers
Module: Mesa
Branch: master
Commit: e6caafd9d7fbfcb5906d22be9d6a3c1714e078ac
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6caafd9d7fbfcb5906d22be9d6a3c1714e078ac
Author: Christoph Bumiller
Date: Wed May 16 21:08:37 2012 +0200
nv50,nvc0: handle user vertex buffers
And restructure VBO validation a little in the process.
---
src/gallium/drivers/nouveau/nouveau_buffer.c | 20 +-
src/gallium/drivers/nouveau/nouveau_buffer.h |9 +-
src/gallium/drivers/nv50/nv50_context.h |3 +
src/gallium/drivers/nv50/nv50_push.c | 20 +-
src/gallium/drivers/nv50/nv50_screen.c|2 +-
src/gallium/drivers/nv50/nv50_state.c | 15 +-
src/gallium/drivers/nv50/nv50_stateobj.h |3 +-
src/gallium/drivers/nv50/nv50_vbo.c | 242
src/gallium/drivers/nvc0/nvc0_context.h |2 +
src/gallium/drivers/nvc0/nvc0_screen.c|2 +-
src/gallium/drivers/nvc0/nvc0_state.c | 25 ++-
src/gallium/drivers/nvc0/nvc0_stateobj.h |4 +-
src/gallium/drivers/nvc0/nvc0_vbo.c | 377 +++--
src/gallium/drivers/nvc0/nvc0_vbo_translate.c |7 +-
14 files changed, 423 insertions(+), 308 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nouveau_buffer.c
b/src/gallium/drivers/nouveau/nouveau_buffer.c
index 936e2bf..c396e3c 100644
--- a/src/gallium/drivers/nouveau/nouveau_buffer.c
+++ b/src/gallium/drivers/nouveau/nouveau_buffer.c
@@ -604,30 +604,28 @@ nouveau_scratch_more(struct nouveau_context *nv, unsigned
min_size)
return ret;
}
-/* Upload data to scratch memory and update buffer address.
- * Returns the bo the data resides in, if successful.
- */
-struct nouveau_bo *
+
+/* Copy data to a scratch buffer and return address & bo the data resides in.
*/
+uint64_t
nouveau_scratch_data(struct nouveau_context *nv,
- struct nv04_resource *buf, unsigned base, unsigned size)
+ const void *data, unsigned base, unsigned size,
+ struct nouveau_bo **bo)
{
- struct nouveau_bo *bo;
unsigned bgn = MAX2(base, nv->scratch.offset);
unsigned end = bgn + size;
if (end >= nv->scratch.end) {
end = base + size;
if (!nouveau_scratch_more(nv, end))
- return NULL;
+ return 0;
bgn = base;
}
nv->scratch.offset = align(end, 4);
- memcpy(nv->scratch.map + bgn, buf->data + base, size);
+ memcpy(nv->scratch.map + bgn, (const uint8_t *)data + base, size);
- bo = nv->scratch.current;
- buf->address = bo->offset + (bgn - base);
- return bo;
+ *bo = nv->scratch.current;
+ return (*bo)->offset + (bgn - base);
}
void *
diff --git a/src/gallium/drivers/nouveau/nouveau_buffer.h
b/src/gallium/drivers/nouveau/nouveau_buffer.h
index 19255a3..3b8ee72 100644
--- a/src/gallium/drivers/nouveau/nouveau_buffer.h
+++ b/src/gallium/drivers/nouveau/nouveau_buffer.h
@@ -89,11 +89,12 @@ boolean
nouveau_user_buffer_upload(struct nouveau_context *, struct nv04_resource *,
unsigned base, unsigned size);
-/* Copy data to a scratch buffer, update buffer address.
- * Returns the bo the data resides in, or NULL on failure.
+/* Copy data to a scratch buffer and return address & bo the data resides in.
+ * Returns 0 on failure.
*/
-struct nouveau_bo *
+uint64_t
nouveau_scratch_data(struct nouveau_context *,
- struct nv04_resource *, unsigned base, unsigned size);
+ const void *data, unsigned base, unsigned size,
+ struct nouveau_bo **);
#endif
diff --git a/src/gallium/drivers/nv50/nv50_context.h
b/src/gallium/drivers/nv50/nv50_context.h
index 8f5363b..5da0473 100644
--- a/src/gallium/drivers/nv50/nv50_context.h
+++ b/src/gallium/drivers/nv50/nv50_context.h
@@ -123,8 +123,11 @@ struct nv50_context {
struct pipe_index_buffer idxbuf;
uint32_t vbo_fifo; /* bitmask of vertex elements to be pushed to FIFO */
uint32_t vbo_user; /* bitmask of vertex buffers pointing to user memory */
+ uint32_t vbo_constant; /* bitmask of user buffers with stride 0 */
uint32_t vb_elt_first; /* from pipe_draw_info, for vertex upload */
uint32_t vb_elt_limit; /* max - min element (count - 1) */
+ uint32_t instance_off; /* base vertex for instanced arrays */
+ uint32_t instance_max; /* max instance for current draw call */
struct pipe_sampler_view *textures[3][PIPE_MAX_SAMPLERS];
unsigned num_textures[3];
diff --git a/src/gallium/drivers/nv50/nv50_push.c
b/src/gallium/drivers/nv50/nv50_push.c
index 1f7bc76..eb6bfbc 100644
--- a/src/gallium/drivers/nv50/nv50_push.c
+++ b/src/gallium/drivers/nv50/nv50_push.c
@@ -220,15 +220,17 @@ nv50_push_vbo(struct nv50_context *nv50, const struct
pipe_draw_info *info)
ctx.vertex_words = nv50->vertex->vertex_size;
for (i = 0; i < nv50->num_vtxbufs; ++i) {
- uint8_t *data;
- struct pipe_vertex_buffer *vb = &nv50->vtxbuf[i];
- struc
Mesa (master): nv50,nvc0: handle user constbufs without wrapping them in a resource
Module: Mesa
Branch: master
Commit: fcb28682101dfa127486373411043d5d97a0ff8f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fcb28682101dfa127486373411043d5d97a0ff8f
Author: Christoph Bumiller
Date: Wed May 16 20:52:41 2012 +0200
nv50,nvc0: handle user constbufs without wrapping them in a resource
---
src/gallium/drivers/nv50/nv50_context.c|5 +-
src/gallium/drivers/nv50/nv50_context.h| 17 -
src/gallium/drivers/nv50/nv50_screen.c |7 +-
src/gallium/drivers/nv50/nv50_screen.h |3 +
src/gallium/drivers/nv50/nv50_shader_state.c | 109 +++-
src/gallium/drivers/nv50/nv50_state.c | 42 ++
src/gallium/drivers/nv50/nv50_stateobj.h | 10 ++
src/gallium/drivers/nvc0/nvc0_context.c|5 +-
src/gallium/drivers/nvc0/nvc0_context.h| 19 -
src/gallium/drivers/nvc0/nvc0_screen.c |2 +-
src/gallium/drivers/nvc0/nvc0_screen.h |3 +
src/gallium/drivers/nvc0/nvc0_state.c | 45 +--
src/gallium/drivers/nvc0/nvc0_state_validate.c | 89
src/gallium/drivers/nvc0/nvc0_stateobj.h | 10 ++
14 files changed, 201 insertions(+), 165 deletions(-)
diff --git a/src/gallium/drivers/nv50/nv50_context.c
b/src/gallium/drivers/nv50/nv50_context.c
index 558fe0b..1e6bbaf 100644
--- a/src/gallium/drivers/nv50/nv50_context.c
+++ b/src/gallium/drivers/nv50/nv50_context.c
@@ -86,8 +86,9 @@ nv50_context_unreference_resources(struct nv50_context *nv50)
for (i = 0; i < nv50->num_textures[s]; ++i)
pipe_sampler_view_reference(&nv50->textures[s][i], NULL);
- for (i = 0; i < 16; ++i)
- pipe_resource_reference(&nv50->constbuf[s][i], NULL);
+ for (i = 0; i < NV50_MAX_PIPE_CONSTBUFS; ++i)
+ if (!nv50->constbuf[s][i].user)
+pipe_resource_reference(&nv50->constbuf[s][i].u.buf, NULL);
}
}
diff --git a/src/gallium/drivers/nv50/nv50_context.h
b/src/gallium/drivers/nv50/nv50_context.h
index 44a0ba0..8f5363b 100644
--- a/src/gallium/drivers/nv50/nv50_context.h
+++ b/src/gallium/drivers/nv50/nv50_context.h
@@ -90,6 +90,7 @@ struct nv50_context {
uint32_t semantic_color;
uint32_t semantic_psize;
int32_t index_bias;
+ boolean uniform_buffer_bound[3];
boolean prim_restart;
boolean point_sprite;
boolean rt_serialize;
@@ -113,7 +114,7 @@ struct nv50_context {
struct nv50_program *gmtyprog;
struct nv50_program *fragprog;
- struct pipe_resource *constbuf[3][16];
+ struct nv50_constbuf constbuf[3][NV50_MAX_PIPE_CONSTBUFS];
uint16_t constbuf_dirty[3];
uint16_t constbuf_valid[3];
@@ -163,6 +164,20 @@ nv50_context_screen(struct nv50_context *nv50)
return nv50_screen(&nv50->base.screen->base);
}
+/* return index used in nv50_context arrays for a specific shader type */
+static INLINE unsigned
+nv50_context_shader_stage(unsigned pipe)
+{
+ switch (pipe) {
+ case PIPE_SHADER_VERTEX: return 0;
+ case PIPE_SHADER_FRAGMENT: return 1;
+ case PIPE_SHADER_GEOMETRY: return 2;
+ case PIPE_SHADER_COMPUTE: return 3;
+ default:
+ assert(!"invalid/unhandled shader type");
+ return 0;
+ }
+}
/* nv50_context.c */
struct pipe_context *nv50_create(struct pipe_screen *, void *);
diff --git a/src/gallium/drivers/nv50/nv50_screen.c
b/src/gallium/drivers/nv50/nv50_screen.c
index c96e028..9f356ff 100644
--- a/src/gallium/drivers/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nv50/nv50_screen.c
@@ -196,7 +196,7 @@ nv50_screen_get_shader_param(struct pipe_screen *pscreen,
unsigned shader,
case PIPE_SHADER_CAP_MAX_CONSTS:
return 65536 / 16;
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
- return 14;
+ return NV50_MAX_PIPE_CONSTBUFS;
case PIPE_SHADER_CAP_MAX_ADDRS:
return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
@@ -437,10 +437,7 @@ nv50_screen_init_hwctx(struct nv50_screen *screen,
unsigned tls_space)
PUSH_DATA (push, screen->uniforms->offset + (3 << 16));
PUSH_DATA (push, (NV50_CB_AUX << 16) | 0x0200);
- BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 6);
- PUSH_DATA (push, (NV50_CB_PVP << 12) | 0x001);
- PUSH_DATA (push, (NV50_CB_PGP << 12) | 0x021);
- PUSH_DATA (push, (NV50_CB_PFP << 12) | 0x031);
+ BEGIN_NI04(push, NV50_3D(SET_PROGRAM_CB), 3);
PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf01);
PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf21);
PUSH_DATA (push, (NV50_CB_AUX << 12) | 0xf31);
diff --git a/src/gallium/drivers/nv50/nv50_screen.h
b/src/gallium/drivers/nv50/nv50_screen.h
index 9eae08e..4292f7f 100644
--- a/src/gallium/drivers/nv50/nv50_screen.h
+++ b/src/gallium/drivers/nv50/nv50_screen.h
@@ -12,6 +12,9 @@
#define NV50_TIC_MAX_ENTRIES 2048
#define NV50_TSC_MAX_ENTRIES 2048
+/* doesn't count reserved slots (for auxiliary constants, immediates, etc.) */
+#define NV50_MAX_PIPE_CONSTBUFS 14
+
struct nv50_context;
#define NV50_CODE_BO_SIZE_LOG2 19
di
Mesa (master): st/mesa: set PIPE_BIND_STREAM_OUTPUT for TFB target in st_bufferobj_data
Module: Mesa Branch: master Commit: 07323a80a258372875e61f73a4f745374bea6bda URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=07323a80a258372875e61f73a4f745374bea6bda Author: Christoph Bumiller Date: Sun May 13 21:32:47 2012 +0200 st/mesa: set PIPE_BIND_STREAM_OUTPUT for TFB target in st_bufferobj_data --- src/mesa/state_tracker/st_cb_bufferobjects.c |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/src/mesa/state_tracker/st_cb_bufferobjects.c b/src/mesa/state_tracker/st_cb_bufferobjects.c index 6534a43..b47a2d8 100644 --- a/src/mesa/state_tracker/st_cb_bufferobjects.c +++ b/src/mesa/state_tracker/st_cb_bufferobjects.c @@ -195,6 +195,9 @@ st_bufferobj_data(struct gl_context *ctx, case GL_ELEMENT_ARRAY_BUFFER_ARB: bind = PIPE_BIND_INDEX_BUFFER; break; + case GL_TRANSFORM_FEEDBACK_BUFFER: + bind = PIPE_BIND_STREAM_OUTPUT; + break; default: bind = 0; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
