Mesa (master): r600g/llvm: Workaround for wrong tex.offset_*

2013-04-04 Thread Vincent Lejeune 
Module: Mesa
Branch: master
Commit: 92769612233dade9b7d45d5058dc86efc18d7710
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=92769612233dade9b7d45d5058dc86efc18d7710

Author: Vincent Lejeune v...@ovi.com
Date:   Wed Apr  3 21:19:22 2013 +0200

r600g/llvm: Workaround for wrong tex.offset_*

---

 src/gallium/drivers/r600/r600_shader.c |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index d24d8e7..a5d224f 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -511,6 +511,9 @@ static unsigned r600_tex_from_byte_stream(struct 
r600_shader_ctx *ctx,
tex.src_sel_y = G_SQ_TEX_WORD2_SRC_SEL_Y(word2);
tex.src_sel_z = G_SQ_TEX_WORD2_SRC_SEL_Z(word2);
tex.src_sel_w = G_SQ_TEX_WORD2_SRC_SEL_W(word2);
+   tex.offset_x = 1;
+   tex.offset_y = 1;
+   tex.offset_z = 1;
 
tex.inst_mod = 0;
 

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Mesa (master): gallium/hud: replace malloc w/ MALLOC

2013-04-04 Thread Brian Paul 
Module: Mesa
Branch: master
Commit: a408ea96920984ad2c5bf81f799cbb583f264105
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a408ea96920984ad2c5bf81f799cbb583f264105

Author: Brian Paul bri...@vmware.com
Date:   Wed Apr  3 13:33:38 2013 -0600

gallium/hud: replace malloc w/ MALLOC

To match the FREE() called used later.  Fixes things on Windows.

Reviewed-by: Marek Olšák mar...@gmail.com

---

 src/gallium/auxiliary/hud/hud_context.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/gallium/auxiliary/hud/hud_context.c 
b/src/gallium/auxiliary/hud/hud_context.c
index 5511f8e..b417f5d 100644
--- a/src/gallium/auxiliary/hud/hud_context.c
+++ b/src/gallium/auxiliary/hud/hud_context.c
@@ -621,7 +621,7 @@ hud_pane_add_graph(struct hud_pane *pane, struct hud_graph 
*gr)
}
 
assert(pane-num_graphs  Elements(colors));
-   gr-vertices = malloc(pane-max_num_vertices * sizeof(float) * 2);
+   gr-vertices = MALLOC(pane-max_num_vertices * sizeof(float) * 2);
gr-color[0] = colors[pane-num_graphs][0];
gr-color[1] = colors[pane-num_graphs][1];
gr-color[2] = colors[pane-num_graphs][2];

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Mesa (master): util: add debug_memory_check_block(), debug_memory_tag()

2013-04-04 Thread Brian Paul 
Module: Mesa
Branch: master
Commit: 92e5e45ff1147232699be9e517c70146e6ed0291
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=92e5e45ff1147232699be9e517c70146e6ed0291

Author: Brian Paul bri...@vmware.com
Date:   Wed Apr  3 13:36:50 2013 -0600

util: add debug_memory_check_block(), debug_memory_tag()

The former just checks that the given block is valid by checking
the header and footer.

The later sets the memory block's tag.  With extra debug code, we
can use that for monitoring/checking particular allocations.

Reviewed-by: José Fonseca jfons...@vmware.com

---

 src/gallium/auxiliary/os/os_memory_debug.h  |6 +++
 src/gallium/auxiliary/util/u_debug_memory.c |   55 +++
 2 files changed, 61 insertions(+), 0 deletions(-)

diff --git a/src/gallium/auxiliary/os/os_memory_debug.h 
b/src/gallium/auxiliary/os/os_memory_debug.h
index 36b8fc6..9a487de 100644
--- a/src/gallium/auxiliary/os/os_memory_debug.h
+++ b/src/gallium/auxiliary/os/os_memory_debug.h
@@ -60,6 +60,12 @@ void *
 debug_realloc(const char *file, unsigned line, const char *function,
   void *old_ptr, size_t old_size, size_t new_size );
 
+void
+debug_memory_tag(void *ptr, unsigned tag);
+
+void
+debug_memory_check_block(void *ptr);
+
 void 
 debug_memory_check(void);
 
diff --git a/src/gallium/auxiliary/util/u_debug_memory.c 
b/src/gallium/auxiliary/util/u_debug_memory.c
index 4bf26a5..4723547 100644
--- a/src/gallium/auxiliary/util/u_debug_memory.c
+++ b/src/gallium/auxiliary/util/u_debug_memory.c
@@ -76,6 +76,7 @@ struct debug_memory_header
 #endif
 
unsigned magic;
+   unsigned tag;
 };
 
 struct debug_memory_footer
@@ -140,6 +141,7 @@ debug_malloc(const char *file, unsigned line, const char 
*function,
hdr-function = function;
hdr-size = size;
hdr-magic = DEBUG_MEMORY_MAGIC;
+   hdr-tag = 0;
 #if DEBUG_FREED_MEMORY
hdr-freed = FALSE;
 #endif
@@ -263,6 +265,7 @@ debug_realloc(const char *file, unsigned line, const char 
*function,
new_hdr-function = old_hdr-function;
new_hdr-size = new_size;
new_hdr-magic = DEBUG_MEMORY_MAGIC;
+   new_hdr-tag = 0;
 #if DEBUG_FREED_MEMORY
new_hdr-freed = FALSE;
 #endif
@@ -348,6 +351,58 @@ debug_memory_end(unsigned long start_no)
 
 
 /**
+ * Put a tag (arbitrary integer) on a memory block.
+ * Can be useful for debugging.
+ */
+void
+debug_memory_tag(void *ptr, unsigned tag)
+{
+   struct debug_memory_header *hdr;
+   
+   if (!ptr)
+  return;
+   
+   hdr = header_from_data(ptr);
+   if (hdr-magic != DEBUG_MEMORY_MAGIC) {
+  debug_printf(%s corrupted memory at %p\n, __FUNCTION__, ptr);
+  debug_assert(0);
+   }
+
+   hdr-tag = tag;
+}
+
+
+/**
+ * Check the given block of memory for validity/corruption.
+ */
+void
+debug_memory_check_block(void *ptr)
+{
+   struct debug_memory_header *hdr;
+   struct debug_memory_footer *ftr;
+   
+   if (!ptr)
+  return;
+   
+   hdr = header_from_data(ptr);
+   ftr = footer_from_header(hdr);
+
+   if (hdr-magic != DEBUG_MEMORY_MAGIC) {
+  debug_printf(%s:%u:%s: bad or corrupted memory %p\n,
+   hdr-file, hdr-line, hdr-function, ptr);
+  debug_assert(0);
+   }
+
+   if (ftr-magic != DEBUG_MEMORY_MAGIC) {
+  debug_printf(%s:%u:%s: buffer overflow %p\n,
+   hdr-file, hdr-line, hdr-function, ptr);
+  debug_assert(0);
+   }
+}
+
+
+
+/**
  * We can periodically call this from elsewhere to do a basic sanity
  * check of the heap memory we've allocated.
  */

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Mesa (master): st/wgl: make stw_current_context() non-static

2013-04-04 Thread Brian Paul 
Module: Mesa
Branch: master
Commit: 0c1dcf906d81f0ceb7d117ef67b51194cdbeeebe
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c1dcf906d81f0ceb7d117ef67b51194cdbeeebe

Author: Brian Paul bri...@vmware.com
Date:   Wed Apr  3 13:45:47 2013 -0600

st/wgl: make stw_current_context() non-static

Reviewed-by: José Fonseca jfons...@vmware.com

---

 src/gallium/state_trackers/wgl/stw_context.c |2 +-
 src/gallium/state_trackers/wgl/stw_context.h |2 ++
 2 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/src/gallium/state_trackers/wgl/stw_context.c 
b/src/gallium/state_trackers/wgl/stw_context.c
index 1488bee..5e5b41f 100644
--- a/src/gallium/state_trackers/wgl/stw_context.c
+++ b/src/gallium/state_trackers/wgl/stw_context.c
@@ -48,7 +48,7 @@
 #include stw_tls.h
 
 
-static INLINE struct stw_context *
+struct stw_context *
 stw_current_context(void)
 {
struct st_context_iface *st;
diff --git a/src/gallium/state_trackers/wgl/stw_context.h 
b/src/gallium/state_trackers/wgl/stw_context.h
index 07a5c7d..18f3c4a 100644
--- a/src/gallium/state_trackers/wgl/stw_context.h
+++ b/src/gallium/state_trackers/wgl/stw_context.h
@@ -48,6 +48,8 @@ DHGLRC stw_create_context_attribs( HDC hdc, INT iLayerPlane, 
DHGLRC hShareContex
 
 DHGLRC stw_get_current_context( void );
 
+struct stw_context *stw_current_context(void);
+
 HDC stw_get_current_dc( void );
 
 BOOL stw_make_current( HDC hdc, DHGLRC dhglrc );

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Mesa (master): st/wgl: add HUD support

2013-04-04 Thread Brian Paul 
Module: Mesa
Branch: master
Commit: e95514c0eaeb44b9664ff00d0d7b10144cf3f219
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e95514c0eaeb44b9664ff00d0d7b10144cf3f219

Author: Brian Paul bri...@vmware.com
Date:   Wed Apr  3 13:46:40 2013 -0600

st/wgl: add HUD support

v2: fix a few minor issues spotted by Jose.

Reviewed-by: José Fonseca jfons...@vmware.com

---

 src/gallium/state_trackers/wgl/stw_context.c |   12 
 src/gallium/state_trackers/wgl/stw_context.h |3 +++
 src/gallium/state_trackers/wgl/stw_framebuffer.c |   10 ++
 src/gallium/state_trackers/wgl/stw_st.c  |   13 +
 src/gallium/state_trackers/wgl/stw_st.h  |4 
 5 files changed, 42 insertions(+), 0 deletions(-)

diff --git a/src/gallium/state_trackers/wgl/stw_context.c 
b/src/gallium/state_trackers/wgl/stw_context.c
index 5e5b41f..f3773ed 100644
--- a/src/gallium/state_trackers/wgl/stw_context.c
+++ b/src/gallium/state_trackers/wgl/stw_context.c
@@ -38,6 +38,7 @@
 #include util/u_memory.h
 #include util/u_atomic.h
 #include state_tracker/st_api.h
+#include hud/hud_context.h
 
 #include stw_icd.h
 #include stw_device.h
@@ -217,6 +218,10 @@ stw_create_context_attribs(
 
ctx-st-st_manager_private = (void *) ctx;
 
+   if (ctx-st-cso_context) {
+  ctx-hud = hud_create(ctx-st-pipe, ctx-st-cso_context);
+   }
+
pipe_mutex_lock( stw_dev-ctx_mutex );
ctx-dhglrc = handle_table_add(stw_dev-ctx_table, ctx);
pipe_mutex_unlock( stw_dev-ctx_mutex );
@@ -226,6 +231,9 @@ stw_create_context_attribs(
return ctx-dhglrc;
 
 no_hglrc:
+   if (ctx-hud) {
+  hud_destroy(ctx-hud);
+   }
ctx-st-destroy(ctx-st);
 no_st_ctx:
FREE(ctx);
@@ -255,6 +263,10 @@ DrvDeleteContext(
   if (curctx == ctx)
  stw_dev-stapi-make_current(stw_dev-stapi, NULL, NULL, NULL);
 
+  if (ctx-hud) {
+ hud_destroy(ctx-hud);
+  }
+
   ctx-st-destroy(ctx-st);
   FREE(ctx);
 
diff --git a/src/gallium/state_trackers/wgl/stw_context.h 
b/src/gallium/state_trackers/wgl/stw_context.h
index 18f3c4a..72e112a 100644
--- a/src/gallium/state_trackers/wgl/stw_context.h
+++ b/src/gallium/state_trackers/wgl/stw_context.h
@@ -30,6 +30,7 @@
 
 #include windows.h
 
+struct hud_context;
 struct stw_framebuffer;
 struct st_context_iface;
 
@@ -41,6 +42,8 @@ struct stw_context
HDC hdc;
 
struct stw_framebuffer *current_framebuffer;
+
+   struct hud_context *hud;
 };
 
 DHGLRC stw_create_context_attribs( HDC hdc, INT iLayerPlane, DHGLRC 
hShareContext,
diff --git a/src/gallium/state_trackers/wgl/stw_framebuffer.c 
b/src/gallium/state_trackers/wgl/stw_framebuffer.c
index 449c537..c22e0f1 100644
--- a/src/gallium/state_trackers/wgl/stw_framebuffer.c
+++ b/src/gallium/state_trackers/wgl/stw_framebuffer.c
@@ -31,6 +31,7 @@
 #include pipe/p_screen.h
 #include util/u_format.h
 #include util/u_memory.h
+#include hud/hud_context.h
 #include state_tracker/st_api.h
 
 #include stw_icd.h
@@ -593,6 +594,7 @@ BOOL APIENTRY
 DrvSwapBuffers(
HDC hdc )
 {
+   struct stw_context *ctx;
struct stw_framebuffer *fb;
 
if (!stw_dev)
@@ -607,6 +609,14 @@ DrvSwapBuffers(
   return TRUE;
}
 
+   /* Display the HUD */
+   ctx = stw_current_context();
+   if (ctx  ctx-hud) {
+  struct pipe_resource *back =
+ stw_get_framebuffer_resource(fb-stfb, ST_ATTACHMENT_BACK_LEFT);
+  hud_draw(ctx-hud, back);
+   }
+
stw_flush_current_locked(fb);
 
return stw_st_swap_framebuffer_locked(hdc, fb-stfb);
diff --git a/src/gallium/state_trackers/wgl/stw_st.c 
b/src/gallium/state_trackers/wgl/stw_st.c
index dcf9587..3acf266 100644
--- a/src/gallium/state_trackers/wgl/stw_st.c
+++ b/src/gallium/state_trackers/wgl/stw_st.c
@@ -263,6 +263,19 @@ stw_st_swap_framebuffer_locked(HDC hdc, struct 
st_framebuffer_iface *stfb)
return stw_st_framebuffer_present_locked(hdc, stwfb-base, front);
 }
 
+
+/**
+ * Return the pipe_resource that correspond to given buffer.
+ */
+struct pipe_resource *
+stw_get_framebuffer_resource(struct st_framebuffer_iface *stfb,
+ enum st_attachment_type att)
+{
+   struct stw_st_framebuffer *stwfb = stw_st_framebuffer(stfb);
+   return stwfb-textures[att];
+}
+
+
 /**
  * Create an st_api of the state tracker.
  */
diff --git a/src/gallium/state_trackers/wgl/stw_st.h 
b/src/gallium/state_trackers/wgl/stw_st.h
index 945d350..c2473c7 100644
--- a/src/gallium/state_trackers/wgl/stw_st.h
+++ b/src/gallium/state_trackers/wgl/stw_st.h
@@ -46,4 +46,8 @@ stw_st_destroy_framebuffer_locked(struct st_framebuffer_iface 
*stfb);
 boolean
 stw_st_swap_framebuffer_locked(HDC hdc, struct st_framebuffer_iface *stfb);
 
+struct pipe_resource *
+stw_get_framebuffer_resource(struct st_framebuffer_iface *stfb,
+ enum st_attachment_type att);
+
 #endif /* STW_ST_H */

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Mesa (master): freedreno: document debug flag

2013-04-04 Thread Brian Paul 
Module: Mesa
Branch: master
Commit: 456f40e18d39d35a6fabedf6ac4cc3d46126a517
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=456f40e18d39d35a6fabedf6ac4cc3d46126a517

Author: Erik Faye-Lund kusmab...@gmail.com
Date:   Tue Mar 26 14:48:45 2013 +0100

freedreno: document debug flag

Signed-off-by: Erik Faye-Lund kusmab...@gmail.com
Signed-off-by: Brian Paul bri...@vmware.com

---

 src/gallium/docs/source/debugging.rst |4 
 1 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/src/gallium/docs/source/debugging.rst 
b/src/gallium/docs/source/debugging.rst
index e081cbf..dc308e5 100644
--- a/src/gallium/docs/source/debugging.rst
+++ b/src/gallium/docs/source/debugging.rst
@@ -81,6 +81,10 @@ Debug :ref:`flags` for the llvmpipe driver.
 
 Number of threads that the llvmpipe driver should use.
 
+.. envvar:: FD_MESA_DEBUG flags (0x0)
+
+Debug :ref:`flags` for the freedreno driver.
+
 
 .. _flags:
 

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Mesa (9.1): nv50: fix 3D render target setup

2013-04-04 Thread Maarten Lankhorst 
Module: Mesa
Branch: 9.1
Commit: 7410ba12657fa3652d05c99d44eda68231b9c100
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7410ba12657fa3652d05c99d44eda68231b9c100

Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date:   Mon Mar 25 19:41:18 2013 +0100

nv50: fix 3D render target setup

---

 src/gallium/drivers/nv50/nv50_state_validate.c |   12 ++--
 1 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/nv50/nv50_state_validate.c 
b/src/gallium/drivers/nv50/nv50_state_validate.c
index a95e96d..f5e7b36 100644
--- a/src/gallium/drivers/nv50/nv50_state_validate.c
+++ b/src/gallium/drivers/nv50/nv50_state_validate.c
@@ -9,6 +9,7 @@ nv50_validate_fb(struct nv50_context *nv50)
struct pipe_framebuffer_state *fb = nv50-framebuffer;
unsigned i;
unsigned ms_mode = NV50_3D_MULTISAMPLE_MODE_MS1;
+   uint32_t array_size = 0x, array_mode = 0;
 
nouveau_bufctx_reset(nv50-bufctx_3d, NV50_BIND_FB);
 
@@ -23,6 +24,13 @@ nv50_validate_fb(struct nv50_context *nv50)
   struct nv50_surface *sf = nv50_surface(fb-cbufs[i]);
   struct nouveau_bo *bo = mt-base.bo;
 
+  array_size = MIN2(array_size, sf-depth);
+  if (mt-layout_3d)
+ array_mode = NV50_3D_RT_ARRAY_MODE_MODE_3D; /* 1  16 */
+
+  /* can't mix 3D with ARRAY or have RTs of different depth/array_size */
+  assert(mt-layout_3d || !array_mode || array_size == 1);
+
   BEGIN_NV04(push, NV50_3D(RT_ADDRESS_HIGH(i)), 5);
   PUSH_DATAh(push, bo-offset + sf-offset);
   PUSH_DATA (push, bo-offset + sf-offset);
@@ -34,7 +42,7 @@ nv50_validate_fb(struct nv50_context *nv50)
  PUSH_DATA (push, sf-width);
  PUSH_DATA (push, sf-height);
  BEGIN_NV04(push, NV50_3D(RT_ARRAY_MODE), 1);
- PUSH_DATA (push, sf-depth);
+ PUSH_DATA (push, array_mode | array_size);
   } else {
  PUSH_DATA (push, 0);
  PUSH_DATA (push, 0);
@@ -63,7 +71,7 @@ nv50_validate_fb(struct nv50_context *nv50)
   struct nv50_miptree *mt = nv50_miptree(fb-zsbuf-texture);
   struct nv50_surface *sf = nv50_surface(fb-zsbuf);
   struct nouveau_bo *bo = mt-base.bo;
-  int unk = mt-base.base.target == PIPE_TEXTURE_2D;
+  int unk = mt-base.base.target == PIPE_TEXTURE_3D || sf-depth == 1;
 
   BEGIN_NV04(push, NV50_3D(ZETA_ADDRESS_HIGH), 5);
   PUSH_DATAh(push, bo-offset + sf-offset);

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Mesa (9.1): nv50, nvc0: disable DEPTH_RANGE_NEAR/FAR clipping during blit

2013-04-04 Thread Maarten Lankhorst 
Module: Mesa
Branch: 9.1
Commit: 5ba62ee2011b44e8a40bab6435a8edaf03cda612
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ba62ee2011b44e8a40bab6435a8edaf03cda612

Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date:   Sun Mar 31 22:10:02 2013 +0200

nv50,nvc0: disable DEPTH_RANGE_NEAR/FAR clipping during blit

We send position.z == 0, DEPTH_RANGE may be some arbitrary range
not including 0 (for exmaple in piglit's hiz tests).

---

 src/gallium/drivers/nv50/nv50_surface.c |2 ++
 src/gallium/drivers/nvc0/nvc0_3d.xml.h  |2 +-
 src/gallium/drivers/nvc0/nvc0_surface.c |2 ++
 3 files changed, 5 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/nv50/nv50_surface.c 
b/src/gallium/drivers/nv50/nv50_surface.c
index 7a0470c..b1b5cb3 100644
--- a/src/gallium/drivers/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nv50/nv50_surface.c
@@ -977,6 +977,8 @@ nv50_blit_3d(struct nv50_context *nv50, const struct 
pipe_blit_info *info)
 
BEGIN_NV04(push, NV50_3D(VIEWPORT_TRANSFORM_EN), 1);
PUSH_DATA (push, 0);
+   BEGIN_NV04(push, NV50_3D(VIEW_VOLUME_CLIP_CTRL), 1);
+   PUSH_DATA (push, 0x1);
 
/* Draw a large triangle in screen coordinates covering the whole
 * render target, with scissors defining the destination region.
diff --git a/src/gallium/drivers/nvc0/nvc0_3d.xml.h 
b/src/gallium/drivers/nvc0/nvc0_3d.xml.h
index 1cf1f96..bd3de58 100644
--- a/src/gallium/drivers/nvc0/nvc0_3d.xml.h
+++ b/src/gallium/drivers/nvc0/nvc0_3d.xml.h
@@ -1041,7 +1041,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 
SOFTWARE.
 #define NVC0_3D_VIEWPORT_TRANSFORM_EN  0x192c
 
 #define NVC0_3D_VIEW_VOLUME_CLIP_CTRL  0x193c
-#define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK0 0x0001
+#define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_RANGE_0_1  0x0001
 #define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1__MASK   0x0006
 #define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1__SHIFT  1
 #define NVC0_3D_VIEW_VOLUME_CLIP_CTRL_UNK1_UNK0
0x
diff --git a/src/gallium/drivers/nvc0/nvc0_surface.c 
b/src/gallium/drivers/nvc0/nvc0_surface.c
index 281d740..94ac241 100644
--- a/src/gallium/drivers/nvc0/nvc0_surface.c
+++ b/src/gallium/drivers/nvc0/nvc0_surface.c
@@ -859,6 +859,8 @@ nvc0_blit_3d(struct nvc0_context *nvc0, const struct 
pipe_blit_info *info)
   z += 0.5f * dz;
 
IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 0);
+   IMMED_NVC0(push, NVC0_3D(VIEW_VOLUME_CLIP_CTRL), 0x2 |
+  NVC0_3D_VIEW_VOLUME_CLIP_CTRL_DEPTH_RANGE_0_1);
BEGIN_NVC0(push, NVC0_3D(VIEWPORT_HORIZ(0)), 2);
PUSH_DATA (push, nvc0-framebuffer.width  16);
PUSH_DATA (push, nvc0-framebuffer.height  16);

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Mesa (9.1): nvc0: fix for 2d engine R source formats writing RRR1 and not R001

2013-04-04 Thread Maarten Lankhorst 
Module: Mesa
Branch: 9.1
Commit: 923bb2d8edbcda9f4a293a0efd04d533382978e0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=923bb2d8edbcda9f4a293a0efd04d533382978e0

Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date:   Sat Mar 30 21:28:30 2013 +0100

nvc0: fix for 2d engine R source formats writing RRR1 and not R001

---

 src/gallium/drivers/nv50/nv50_blit.h|   40 ++
 src/gallium/drivers/nv50/nv50_surface.c |   71 
 src/gallium/drivers/nvc0/nvc0_surface.c |   89 +--
 3 files changed, 148 insertions(+), 52 deletions(-)

diff --git a/src/gallium/drivers/nv50/nv50_blit.h 
b/src/gallium/drivers/nv50/nv50_blit.h
index d409f21..bdd6a63 100644
--- a/src/gallium/drivers/nv50/nv50_blit.h
+++ b/src/gallium/drivers/nv50/nv50_blit.h
@@ -180,4 +180,44 @@ nv50_blit_eng2d_get_mask(const struct pipe_blit_info *info)
return mask;
 }
 
+#if NOUVEAU_DRIVER == 0xc0
+# define nv50_format_table nvc0_format_table
+#endif
+
+/* return TRUE for formats that can be converted among each other by NVC0_2D */
+static INLINE boolean
+nv50_2d_dst_format_faithful(enum pipe_format format)
+{
+   const uint64_t mask =
+   NV50_ENG2D_SUPPORTED_FORMATS 
+  ~NV50_ENG2D_NOCONVERT_FORMATS;
+   uint8_t id = nv50_format_table[format].rt;
+   return (id = 0xc0)  (mask  (1ULL  (id - 0xc0)));
+}
+static INLINE boolean
+nv50_2d_src_format_faithful(enum pipe_format format)
+{
+   const uint64_t mask =
+  NV50_ENG2D_SUPPORTED_FORMATS 
+~(NV50_ENG2D_LUMINANCE_FORMATS | NV50_ENG2D_INTENSITY_FORMATS);
+   uint8_t id = nv50_format_table[format].rt;
+   return (id = 0xc0)  (mask  (1ULL  (id - 0xc0)));
+}
+
+static INLINE boolean
+nv50_2d_format_supported(enum pipe_format format)
+{
+   uint8_t id = nv50_format_table[format].rt;
+   return (id = 0xc0) 
+  (NV50_ENG2D_SUPPORTED_FORMATS  (1ULL  (id - 0xc0)));
+}
+
+static INLINE boolean
+nv50_2d_dst_format_ops_supported(enum pipe_format format)
+{
+   uint8_t id = nv50_format_table[format].rt;
+   return (id = 0xc0) 
+  (NV50_ENG2D_OPERATION_FORMATS  (1ULL  (id - 0xc0)));
+}
+
 #endif /* __NV50_BLIT_H__ */
diff --git a/src/gallium/drivers/nv50/nv50_surface.c 
b/src/gallium/drivers/nv50/nv50_surface.c
index 16f77cd..3a780f6 100644
--- a/src/gallium/drivers/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nv50/nv50_surface.c
@@ -35,25 +35,22 @@
 
 #include nv50_context.h
 #include nv50_resource.h
-#include nv50_blit.h
 
 #include nv50_defs.xml.h
 #include nv50_texture.xml.h
 
+/* these are used in nv50_blit.h */
 #define NV50_ENG2D_SUPPORTED_FORMATS 0xff0843e080608409ULL
+#define NV50_ENG2D_NOCONVERT_FORMATS 0x00084020ULL
+#define NV50_ENG2D_LUMINANCE_FORMATS 0x00084020ULL
+#define NV50_ENG2D_INTENSITY_FORMATS 0xULL
+#define NV50_ENG2D_OPERATION_FORMATS 0x060001c000608000ULL
 
-/* return TRUE for formats that can be converted among each other by NV50_2D */
-static INLINE boolean
-nv50_2d_format_faithful(enum pipe_format format)
-{
-   uint8_t id = nv50_format_table[format].rt;
-
-   return (id = 0xc0) 
-  (NV50_ENG2D_SUPPORTED_FORMATS  (1ULL  (id - 0xc0)));
-}
+#define NOUVEAU_DRIVER 0x50
+#include nv50_blit.h
 
 static INLINE uint8_t
-nv50_2d_format(enum pipe_format format)
+nv50_2d_format(enum pipe_format format, boolean dst, boolean dst_src_equal)
 {
uint8_t id = nv50_format_table[format].rt;
 
@@ -62,6 +59,7 @@ nv50_2d_format(enum pipe_format format)
 */
if ((id = 0xc0)  (NV50_ENG2D_SUPPORTED_FORMATS  (1ULL  (id - 0xc0
   return id;
+   assert(dst_src_equal);
 
switch (util_format_get_blocksize(format)) {
case 1:
@@ -78,7 +76,7 @@ nv50_2d_format(enum pipe_format format)
 static int
 nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
 struct nv50_miptree *mt, unsigned level, unsigned layer,
-enum pipe_format pformat)
+enum pipe_format pformat, boolean dst_src_pformat_equal)
 {
struct nouveau_bo *bo = mt-base.bo;
uint32_t width, height, depth;
@@ -86,7 +84,7 @@ nv50_2d_texture_set(struct nouveau_pushbuf *push, int dst,
uint32_t mthd = dst ? NV50_2D_DST_FORMAT : NV50_2D_SRC_FORMAT;
uint32_t offset = mt-level[level].offset;
 
-   format = nv50_2d_format(pformat);
+   format = nv50_2d_format(pformat, dst, dst_src_pformat_equal);
if (!format) {
   NOUVEAU_ERR(invalid/unsupported surface format: %s\n,
   util_format_name(pformat));
@@ -155,15 +153,16 @@ nv50_2d_texture_do_copy(struct nouveau_pushbuf *push,
const enum pipe_format dfmt = dst-base.base.format;
const enum pipe_format sfmt = src-base.base.format;
int ret;
+   boolean eqfmt = dfmt == sfmt;
 
if (!PUSH_SPACE(push, 2 * 16 + 32))
   return PIPE_ERROR;
 
-   ret = nv50_2d_texture_set(push, 1, dst, dst_level, dz, dfmt);
+   ret = nv50_2d_texture_set(push, 1, dst, dst_level, dz, dfmt, eqfmt);
if (ret)
   return ret;
 
-   ret =

Mesa (9.1): nv50,nvc0: fix 3d blits, restore viewport after blit

2013-04-04 Thread Maarten Lankhorst 
Module: Mesa
Branch: 9.1
Commit: ac4be462795590019c262161f6147f6108e796ff
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac4be462795590019c262161f6147f6108e796ff

Author: Christoph Bumiller e0425...@student.tuwien.ac.at
Date:   Fri Mar 22 13:49:40 2013 +0100

nv50,nvc0: fix 3d blits, restore viewport after blit

Conflicts:
src/gallium/drivers/nvc0/nvc0_surface.c

---

 src/gallium/drivers/nv50/nv50_surface.c |8 -
 src/gallium/drivers/nvc0/nvc0_surface.c |   42 +++---
 2 files changed, 32 insertions(+), 18 deletions(-)

diff --git a/src/gallium/drivers/nv50/nv50_surface.c 
b/src/gallium/drivers/nv50/nv50_surface.c
index b1b5cb3..16f77cd 100644
--- a/src/gallium/drivers/nv50/nv50_surface.c
+++ b/src/gallium/drivers/nv50/nv50_surface.c
@@ -936,7 +936,7 @@ nv50_blit_3d(struct nv50_context *nv50, const struct 
pipe_blit_info *info)
nv50_blit_select_fp(blit, info);
nv50_blitctx_pre_blit(blit);
 
-   nv50_blit_set_dst(blit, dst, info-dst.level,  0, info-dst.format);
+   nv50_blit_set_dst(blit, dst, info-dst.level, -1, info-dst.format);
nv50_blit_set_src(blit, src, info-src.level, -1, info-src.format,
  blit-filter);
 
@@ -1226,10 +1226,14 @@ nv50_blit(struct pipe_context *pipe, const struct 
pipe_blit_info *info)
   debug_printf(blit: cannot filter array or cube textures in z 
direction);
}
 
-   if (!eng3d  info-dst.format != info-src.format)
+   if (!eng3d  info-dst.format != info-src.format) {
   if (!nv50_2d_format_faithful(info-dst.format) ||
   !nv50_2d_format_faithful(info-src.format))
  eng3d = TRUE;
+  if (info-dst.format == PIPE_FORMAT_R8_UNORM ||
+  info-dst.format == PIPE_FORMAT_R16_UNORM)
+ eng3d = TRUE;
+   }
 
if (info-src.resource-nr_samples == 8 
info-dst.resource-nr_samples = 1)
diff --git a/src/gallium/drivers/nvc0/nvc0_surface.c 
b/src/gallium/drivers/nvc0/nvc0_surface.c
index 94ac241..80f6f6f 100644
--- a/src/gallium/drivers/nvc0/nvc0_surface.c
+++ b/src/gallium/drivers/nvc0/nvc0_surface.c
@@ -490,19 +490,19 @@ nvc0_blitter_make_vp(struct nvc0_blitter *blit)
 {
static const uint32_t code_nvc0[] =
{
-  0xfff01c66, 0x0680, /* vfetch b128 { $r0 $r1 $r2 $r3 } a[0x80] */
-  0xfff11c26, 0x0690, /* vfetch b96 { $r4 $r5 $r6 } a[0x90]*/
-  0x03f01c66, 0x0a7e0070, /* export b128 o[0x70] { $r0 $r1 $r2 $r3 } */
-  0x13f01c26, 0x0a7e0080, /* export b96 o[0x80] { $r4 $r5 $r6 } */
+  0xfff11c26, 0x0680, /* vfetch b64 $r4:$r5 a[0x80] */
+  0xfff01c46, 0x0690, /* vfetch b96 $r0:$r1:$r2 a[0x90] */
+  0x13f01c26, 0x0a7e0070, /* export b64 o[0x70] $r4:$r5 */
+  0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
   0x1de7, 0x8000, /* exit */
};
static const uint32_t code_nve4[] =
{
   0x0007, 0x2000, /* sched */
-  0xfff01c66, 0x0680, /* vfetch b128 { $r0 $r1 $r2 $r3 } a[0x80] */
-  0xfff11c46, 0x0690, /* vfetch b96 { $r4 $r5 $r6 } a[0x90]*/
-  0x03f01c66, 0x0a7e0070, /* export b128 o[0x70] { $r0 $r1 $r2 $r3 } */
-  0x13f01c46, 0x0a7e0080, /* export b96 o[0x80] { $r4 $r5 $r6 } */
+  0xfff11c26, 0x0680, /* vfetch b64 $r4:$r5 a[0x80] */
+  0xfff01c46, 0x0690, /* vfetch b96 $r0:$r1:$r2 a[0x90] */
+  0x13f01c26, 0x0a7e0070, /* export b64 o[0x70] $r4:$r5 */
+  0x03f01c46, 0x0a7e0080, /* export b96 o[0x80] $r0:$r1:$r2 */
   0x1de7, 0x8000, /* exit */
};
 
@@ -515,13 +515,13 @@ nvc0_blitter_make_vp(struct nvc0_blitter *blit)
   blit-vp.code = (uint32_t *)code_nvc0; /* const_cast */
   blit-vp.code_size = sizeof(code_nvc0);
}
-   blit-vp.max_gpr = 7;
+   blit-vp.max_gpr = 6;
blit-vp.vp.edgeflag = PIPE_MAX_ATTRIBS;
 
blit-vp.hdr[0]  = 0x00020461; /* vertprog magic */
blit-vp.hdr[4]  = 0x000ff000; /* no outputs read */
-   blit-vp.hdr[6]  = 0x003f; /* a[0x80], a[0x90] */
-   blit-vp.hdr[13] = 0x0003f000; /* o[0x70], o[0x80] */
+   blit-vp.hdr[6]  = 0x0073; /* a[0x80].xy, a[0x90].xyz */
+   blit-vp.hdr[13] = 0x00073000; /* o[0x70].xy, o[0x80].xyz */
 }
 
 static void
@@ -820,7 +820,7 @@ nvc0_blit_3d(struct nvc0_context *nvc0, const struct 
pipe_blit_info *info)
nvc0_blit_select_fp(blit, info);
nvc0_blitctx_pre_blit(blit);
 
-   nvc0_blit_set_dst(blit, dst, info-dst.level,  0, info-dst.format);
+   nvc0_blit_set_dst(blit, dst, info-dst.level, -1, info-dst.format);
nvc0_blit_set_src(blit, src, info-src.level, -1, info-src.format,
  blit-filter);
 
@@ -927,11 +927,14 @@ nvc0_blit_3d(struct nvc0_context *nvc0, const struct 
pipe_blit_info *info)
if (info-dst.box.z + info-dst.box.depth - 1)
   IMMED_NVC0(push, NVC0_3D(LAYER), 0);
 
-   /* re-enable normally constant state */
+   nvc0_blitctx_post_blit(blit);
 
-   IMMED_NVC0(push, NVC0_3D(VIEWPORT_TRANSFORM_EN), 1);
+   /* restore viewport */
 
-   nvc0_blitctx_post_blit(blit);
+   BEGIN_NVC0(push,

Mesa (master): llvmpipe: implement ucmp

2013-04-04 Thread Zack Rusin 
Module: Mesa
Branch: master
Commit: be9a42e980d9555f4f4c6c4a248dc269766085d9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=be9a42e980d9555f4f4c6c4a248dc269766085d9

Author: Zack Rusin za...@vmware.com
Date:   Wed Apr  3 21:15:13 2013 -0700

llvmpipe: implement ucmp

and add a test for it

Signed-off-by: Zack Rusin za...@vmware.com
Reviewed-by: José Fonseca jfons...@vmware.com

---

 src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c |   21 
 .../tests/graw/fragment-shader/frag-ucmp.sh|   11 ++
 2 files changed, 32 insertions(+), 0 deletions(-)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c 
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
index dfe581d..f3ae7b6 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
@@ -986,6 +986,26 @@ cmp_emit_cpu(
 cond, emit_data-args[1], emit_data-args[2]);
 }
 
+/* TGSI_OPCODE_UCMP (CPU Only) */
+static void
+ucmp_emit_cpu(
+   const struct lp_build_tgsi_action * action,
+   struct lp_build_tgsi_context * bld_base,
+   struct lp_build_emit_data * emit_data)
+{
+   LLVMBuilderRef builder = bld_base-base.gallivm-builder;
+   struct lp_build_context *uint_bld = bld_base-uint_bld;
+   LLVMValueRef unsigned_cond = 
+  LLVMBuildBitCast(builder, emit_data-args[0], uint_bld-vec_type, );
+   LLVMValueRef cond = lp_build_cmp(uint_bld, PIPE_FUNC_NOTEQUAL,
+unsigned_cond,
+uint_bld-zero);
+   emit_data-output[emit_data-chan] =
+  lp_build_select(bld_base-base,
+  cond, emit_data-args[1], emit_data-args[2]);
+}
+
+
 /* TGSI_OPCODE_CND (CPU Only) */
 static void
 cnd_emit_cpu(
@@ -1701,6 +1721,7 @@ lp_set_default_actions_cpu(
bld_base-sqrt_action.emit = sqrt_emit_cpu;
 
bld_base-op_actions[TGSI_OPCODE_UADD].emit = uadd_emit_cpu;
+   bld_base-op_actions[TGSI_OPCODE_UCMP].emit = ucmp_emit_cpu;
bld_base-op_actions[TGSI_OPCODE_UDIV].emit = udiv_emit_cpu;
bld_base-op_actions[TGSI_OPCODE_UMAX].emit = umax_emit_cpu;
bld_base-op_actions[TGSI_OPCODE_UMIN].emit = umin_emit_cpu;
diff --git a/src/gallium/tests/graw/fragment-shader/frag-ucmp.sh 
b/src/gallium/tests/graw/fragment-shader/frag-ucmp.sh
new file mode 100644
index 000..fa4ea25
--- /dev/null
+++ b/src/gallium/tests/graw/fragment-shader/frag-ucmp.sh
@@ -0,0 +1,11 @@
+FRAG
+DCL IN[0], COLOR, LINEAR
+DCL OUT[0], COLOR
+DCL TEMP[0]
+IMM[0] FLT32 {   10., 1., 0., 0.}
+IMM[1] UINT32 {1, 0, 0, 0}
+0: MUL TEMP[0].x, IN[0]., IMM[0].
+1: F2U TEMP[0].x, TEMP[0].
+2: AND TEMP[0].x, TEMP[0]., IMM[1].
+3: UCMP OUT[0], TEMP[0]., IMM[0].yzzz, IMM[0].yyyz
+4: END

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Mesa (master): i965: Ask the register allocator to round-robin through registers.

2013-04-04 Thread Eric Anholt 
Module: Mesa
Branch: master
Commit: b6e9b54d066d29d250c4502e0005b317589dd8b3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b6e9b54d066d29d250c4502e0005b317589dd8b3

Author: Eric Anholt e...@anholt.net
Date:   Fri Nov 30 16:34:09 2012 -0800

i965: Ask the register allocator to round-robin through registers.

The way we were allocating registers before, packing into low register
numbers for Ironlake, resulted in an overly-constrained dependency graph
for instruction scheduling.  Improves GLBenchmark 2.1 performance by
4.5% +/- 0.7% (n=26).  No difference on my old GLSL demo (n=20).  No
difference on nexuiz (n=15).

v2: Fix off-by-one bug that made the change only work for 16-wide on i965.
Reviewed-by: Matt Turner matts...@gmail.com
Reviewed-by: Kenneth Graunke kenn...@whitecape.org

---

 src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp |2 +
 src/mesa/program/register_allocate.c  |   31 +++--
 src/mesa/program/register_allocate.h  |1 +
 3 files changed, 31 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 4ee7bbc..b9b0303 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -108,6 +108,8 @@ brw_alloc_reg_set(struct brw_context *brw, int reg_width)
 
uint8_t *ra_reg_to_grf = ralloc_array(brw, uint8_t, ra_reg_count);
struct ra_regs *regs = ra_alloc_reg_set(brw, ra_reg_count);
+   if (intel-gen = 6)
+  ra_set_allocate_round_robin(regs);
int *classes = ralloc_array(brw, int, class_count);
int aligned_pairs_class = -1;
 
diff --git a/src/mesa/program/register_allocate.c 
b/src/mesa/program/register_allocate.c
index a9064c3..2c826fc 100644
--- a/src/mesa/program/register_allocate.c
+++ b/src/mesa/program/register_allocate.c
@@ -70,6 +70,7 @@
  * this during ra_set_finalize().
  */
 
+#include stdbool.h
 #include ralloc.h
 
 #include main/imports.h
@@ -93,6 +94,8 @@ struct ra_regs {
 
struct ra_class **classes;
unsigned int class_count;
+
+   bool round_robin;
 };
 
 struct ra_class {
@@ -185,6 +188,22 @@ ra_alloc_reg_set(void *mem_ctx, unsigned int count)
return regs;
 }
 
+/**
+ * The register allocator by default prefers to allocate low register numbers,
+ * since it was written for hardware (gen4/5 Intel) that is limited in its
+ * multithreadedness by the number of registers used in a given shader.
+ *
+ * However, for hardware without that restriction, densely packed register
+ * allocation can put serious constraints on instruction scheduling.  This
+ * function tells the allocator to rotate around the registers if possible as
+ * it allocates the nodes.
+ */
+void
+ra_set_allocate_round_robin(struct ra_regs *regs)
+{
+   regs-round_robin = true;
+}
+
 static void
 ra_add_conflict_list(struct ra_regs *regs, unsigned int r1, unsigned int r2)
 {
@@ -436,16 +455,19 @@ GLboolean
 ra_select(struct ra_graph *g)
 {
int i;
+   int start_search_reg = 0;
 
while (g-stack_count != 0) {
-  unsigned int r;
+  unsigned int ri;
+  unsigned int r = -1;
   int n = g-stack[g-stack_count - 1];
   struct ra_class *c = g-regs-classes[g-nodes[n].class];
 
   /* Find the lowest-numbered reg which is not used by a member
* of the graph adjacent to us.
*/
-  for (r = 0; r  g-regs-count; r++) {
+  for (ri = 0; ri  g-regs-count; ri++) {
+ r = (start_search_reg + ri) % g-regs-count;
 if (!c-regs[r])
continue;
 
@@ -461,12 +483,15 @@ ra_select(struct ra_graph *g)
 if (i == g-nodes[n].adjacency_count)
break;
   }
-  if (r == g-regs-count)
+  if (ri == g-regs-count)
 return GL_FALSE;
 
   g-nodes[n].reg = r;
   g-nodes[n].in_stack = GL_FALSE;
   g-stack_count--;
+
+  if (g-regs-round_robin)
+ start_search_reg = r + 1;
}
 
return GL_TRUE;
diff --git a/src/mesa/program/register_allocate.h 
b/src/mesa/program/register_allocate.h
index 2a9d611..fa119e3 100644
--- a/src/mesa/program/register_allocate.h
+++ b/src/mesa/program/register_allocate.h
@@ -37,6 +37,7 @@ struct ra_regs;
  * two real registers from which they are composed.
  */
 struct ra_regs *ra_alloc_reg_set(void *mem_ctx, unsigned int count);
+void ra_set_allocate_round_robin(struct ra_regs *regs);
 unsigned int ra_alloc_reg_class(struct ra_regs *regs);
 void ra_add_reg_conflict(struct ra_regs *regs,
 unsigned int r1, unsigned int r2);

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Mesa (master): mesa: Add new ctx-Stencil._WriteEnabled derived state flag.

2013-04-04 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: 1e3235d36e45ee7565d322971dfa179f48d79767
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e3235d36e45ee7565d322971dfa179f48d79767

Author: Kenneth Graunke kenn...@whitecape.org
Date:   Tue Apr  2 10:22:18 2013 -0700

mesa: Add new ctx-Stencil._WriteEnabled derived state flag.

i965 needs to know whether stencil writes are enabled in several places,
and gets the test wrong sometimes.  While we could create a function to
compute this, it seems generally useful enough to warrant a new piece of
derived state.  Also, all the plumbing is already in place.

NOTE: This is a candidate for stable branches.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Paul Berry stereotype...@gmail.com

---

 src/mesa/main/mtypes.h  |1 +
 src/mesa/main/stencil.c |5 +
 2 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index ace6938..e731fe3 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -1015,6 +1015,7 @@ struct gl_stencil_attrib
GLboolean TestTwoSide;  /** GL_EXT_stencil_two_side */
GLubyte ActiveFace; /** GL_EXT_stencil_two_side (0 or 2) */
GLboolean _Enabled;  /** Enabled and stencil buffer present */
+   GLboolean _WriteEnabled; /** _Enabled and non-zero writemasks */
GLboolean _TestTwoSide;
GLubyte _BackFace;   /** Current back stencil state (1 or 2) */
GLenum Function[3]; /** Stencil function */
diff --git a/src/mesa/main/stencil.c b/src/mesa/main/stencil.c
index c161808..3308417 100644
--- a/src/mesa/main/stencil.c
+++ b/src/mesa/main/stencil.c
@@ -551,6 +551,11 @@ _mesa_update_stencil(struct gl_context *ctx)
ctx-Stencil.Ref[0] != ctx-Stencil.Ref[face] ||
ctx-Stencil.ValueMask[0] != ctx-Stencil.ValueMask[face] ||
ctx-Stencil.WriteMask[0] != ctx-Stencil.WriteMask[face]);
+
+   ctx-Stencil._WriteEnabled =
+  ctx-Stencil._Enabled 
+  (ctx-Stencil.WriteMask[0] != 0 ||
+   (ctx-Stencil._TestTwoSide  ctx-Stencil.WriteMask[face] != 0));
 }
 
 

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Mesa (master): i965: Fix stencil write enable flag in 3DSTATE_DEPTH_BUFFER on Gen7+.

2013-04-04 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: 01bd29d681c68c8b5b23dfc8f92a3ff25c51a069
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=01bd29d681c68c8b5b23dfc8f92a3ff25c51a069

Author: Kenneth Graunke kenn...@whitecape.org
Date:   Tue Apr  2 10:29:37 2013 -0700

i965: Fix stencil write enable flag in 3DSTATE_DEPTH_BUFFER on Gen7+.

ctx-Stencil.WriteMask is a statically sized array of 3 elements.
Checking it against 0 actually is a NULL check, and can never fail,
which meant that we always said stencil writes were enabled.

Use the new core Mesa derived state flag to fix this.

NOTE: This is a candidate for stable branches.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Paul Berry stereotype...@gmail.com

---

 src/mesa/drivers/dri/i965/gen7_misc_state.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c 
b/src/mesa/drivers/dri/i965/gen7_misc_state.c
index 2009070..1d3677d 100644
--- a/src/mesa/drivers/dri/i965/gen7_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c
@@ -50,7 +50,7 @@ gen7_emit_depth_stencil_hiz(struct brw_context *brw,
OUT_BATCH((depth_mt ? depth_mt-region-pitch - 1 : 0) |
  (depthbuffer_format  18) |
  ((hiz_mt ? 1 : 0)  22) |
- ((stencil_mt != NULL  ctx-Stencil.WriteMask != 0)  27) |
+ ((stencil_mt != NULL  ctx-Stencil._WriteEnabled)  27) |
  ((ctx-Depth.Mask != 0)  28) |
  (depth_surface_type  29));
 

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Mesa (master): i965: Use ctx-Stencil._WriteEnabled in DEPTH_STENCIL_STATE.

2013-04-04 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: 32726b1af6adbde9d6512ef2400c34d544fa02a8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=32726b1af6adbde9d6512ef2400c34d544fa02a8

Author: Kenneth Graunke kenn...@whitecape.org
Date:   Tue Apr  2 10:28:07 2013 -0700

i965: Use ctx-Stencil._WriteEnabled in DEPTH_STENCIL_STATE.

This is the same computation as the _WriteEnabled flag, so we may as
well use it.

Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Paul Berry stereotype...@gmail.com

---

 src/mesa/drivers/dri/i965/gen6_depthstencil.c |6 +-
 1 files changed, 1 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c 
b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
index 4ea517f..940d91f 100644
--- a/src/mesa/drivers/dri/i965/gen6_depthstencil.c
+++ b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
@@ -74,11 +74,7 @@ gen6_upload_depth_stencil_state(struct brw_context *brw)
 ds-ds1.bf_stencil_test_mask = ctx-Stencil.ValueMask[back];
   }
 
-  /* Not really sure about this:
-   */
-  if (ctx-Stencil.WriteMask[0] ||
- (ctx-Stencil._TestTwoSide  ctx-Stencil.WriteMask[back]))
-ds-ds0.stencil_write_enable = 1;
+  ds-ds0.stencil_write_enable = ctx-Stencil._WriteEnabled;
}
 
/* _NEW_DEPTH */

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Mesa (master): i965: Remove fixed-function texture projection avoidance optimization.

2013-04-04 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: 7183568869a0ce856b2f3d4cd9e1d7bd63ff9092
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7183568869a0ce856b2f3d4cd9e1d7bd63ff9092

Author: Kenneth Graunke kenn...@whitecape.org
Date:   Tue Mar 12 21:09:19 2013 -0700

i965: Remove fixed-function texture projection avoidance optimization.

This optimization attempts to avoid extra attribute interpolation
instructions for texture coordinates where the W-component is 1.0.

Unfortunately, it requires a lot of complexity: the brw_wm_input_sizes
state atom (all the brw_vs_constval.c code) needs to run on each draw.
It computes the input_size_masks array, then uses that to compute
proj_attrib_mask.  Differences in proj_attrib_mask can cause
state-dependent fragment shader recompiles.  We also often fail to guess
proj_attrib_mask for the fragment shader precompile, causing us to
needlessly compile it twice.

Furthermore, this optimization only applies to fixed-function programs;
it does not help modern GLSL-based programs at all.  Generally, older
fixed-function programs run fine on modern hardware anyway.

The optimization has existed in some form since the initial commit.  When
we rewrote the fragment shader backend, we dropped it for a while.  Eric
readded it in commit eb30820f268608cf451da32de69723036dddbc62 as part of
an attempt to cure a ~1% performance regression caused by converting the
fixed-function fragment shader generation code from Mesa IR to GLSL IR.
However, no performance data was included in the commit message, so it's
unclear whether or not it was successful.

Time has passed, so I decided to re-measure this.  Surprisingly,
Eric's OpenArena timedemo actually runs /faster/ after removing this and
the brw_wm_input_sizes atom.  On Ivybridge at 1024x768, I measured a
1.39532% +/- 0.91833% increase in FPS (n = 55).  On Ironlake, there was
no statistically significant difference (n = 37).

Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Eric Anholt e...@anholt.net

---

 src/mesa/drivers/dri/i965/brw_fs.cpp |   43 ++---
 1 files changed, 18 insertions(+), 25 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 42c6ab4..1dc08bf 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -1039,31 +1039,24 @@ fs_visitor::emit_general_interpolation(ir_variable *ir)
* attribute, as well as making brw_vs_constval.c
* handle varyings other than gl_TexCoord.
*/
-  if (location = VARYING_SLOT_TEX0 
-  location = VARYING_SLOT_TEX7 
-  k == 3  !(c-key.proj_attrib_mask
-BITFIELD64_BIT(location))) {
- emit(BRW_OPCODE_MOV, attr, fs_reg(1.0f));
-  } else {
- struct brw_reg interp = interp_reg(location, k);
-  emit_linterp(attr, fs_reg(interp), interpolation_mode,
-   ir-centroid);
-  if (brw-needs_unlit_centroid_workaround  ir-centroid) {
- /* Get the pixel/sample mask into f0 so that we know
-  * which pixels are lit.  Then, for each channel that is
-  * unlit, replace the centroid data with non-centroid
-  * data.
-  */
- emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS, attr);
- fs_inst *inst = emit_linterp(attr, fs_reg(interp),
-  interpolation_mode, false);
- inst-predicate = BRW_PREDICATE_NORMAL;
- inst-predicate_inverse = true;
-  }
- if (intel-gen  6) {
-emit(BRW_OPCODE_MUL, attr, attr, this-pixel_w);
- }
-  }
+   struct brw_reg interp = interp_reg(location, k);
+   emit_linterp(attr, fs_reg(interp), interpolation_mode,
+ir-centroid);
+   if (brw-needs_unlit_centroid_workaround  ir-centroid) {
+  /* Get the pixel/sample mask into f0 so that we know
+   * which pixels are lit.  Then, for each channel that is
+   * unlit, replace the centroid data with non-centroid
+   * data.
+   */
+  emit(FS_OPCODE_MOV_DISPATCH_TO_FLAGS, attr);
+  fs_inst *inst = emit_linterp(attr, fs_reg(interp),
+   interpolation_mode, false);
+  inst-predicate = BRW_PREDICATE_NORMAL;
+  inst-predicate_inverse = true;
+   }
+   if (intel-gen  6) {
+  emit(BRW_OPCODE_MUL, attr, attr, this-pixel_w);
+   }
   attr.reg_offset++;
}

Mesa (master): i965: Remove now dead brw_wm_prog_key:: proj_attrib_mask field.

2013-04-04 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: 705c8247fa0eb50587b6c19561eb31e4d3a1b876
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=705c8247fa0eb50587b6c19561eb31e4d3a1b876

Author: Kenneth Graunke kenn...@whitecape.org
Date:   Tue Mar 12 21:09:35 2013 -0700

i965: Remove now dead brw_wm_prog_key::proj_attrib_mask field.

The previous commit removed the last user of this field, so there's no
longer any point in setting it.  Removing this should eliminate
state-dependent recompiles, and make the precompile more reliable.

Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Eric Anholt e...@anholt.net

---

 src/mesa/drivers/dri/i965/brw_fs.cpp |   12 
 src/mesa/drivers/dri/i965/brw_wm.c   |   15 ---
 src/mesa/drivers/dri/i965/brw_wm.h   |2 --
 3 files changed, 0 insertions(+), 29 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 1dc08bf..c12ba45 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2972,15 +2972,6 @@ brw_fs_precompile(struct gl_context *ctx, struct 
gl_shader_program *prog)
   key.iz_lookup |= IZ_DEPTH_WRITE_ENABLE_BIT;
}
 
-   if (prog-Name != 0)
-  key.proj_attrib_mask = ~(GLbitfield64) 0;
-   else {
-  /* Bit VARYING_BIT_POS of key.proj_attrib_mask is never used, so to
-   * avoid unnecessary recompiles, always set it to 1.
-   */
-  key.proj_attrib_mask |= VARYING_BIT_POS;
-   }
-
if (intel-gen  6)
   key.input_slots_valid |= BITFIELD64_BIT(VARYING_SLOT_POS);
 
@@ -2988,9 +2979,6 @@ brw_fs_precompile(struct gl_context *ctx, struct 
gl_shader_program *prog)
   if (!(fp-Base.InputsRead  BITFIELD64_BIT(i)))
 continue;
 
-  if (prog-Name == 0)
- key.proj_attrib_mask |= BITFIELD64_BIT(i);
-
   if (intel-gen  6) {
  if (_mesa_varying_slot_in_fs((gl_varying_slot) i))
 key.input_slots_valid |= BITFIELD64_BIT(i);
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c 
b/src/mesa/drivers/dri/i965/brw_wm.c
index 895619a..35d6876 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -285,8 +285,6 @@ brw_wm_debug_recompile(struct brw_context *brw,
   old_key-clamp_fragment_color, 
key-clamp_fragment_color);
found |= key_debug(intel, line smoothing,
   old_key-line_aa, key-line_aa);
-   found |= key_debug(intel, proj_attrib_mask,
-  old_key-proj_attrib_mask, key-proj_attrib_mask);
found |= key_debug(intel, renderbuffer height,
   old_key-drawable_height, key-drawable_height);
found |= key_debug(intel, input slots valid,
@@ -423,19 +421,6 @@ static void brw_wm_populate_key( struct brw_context *brw,
if (intel-gen  6)
   key-stats_wm = brw-intel.stats_wm;
 
-   /* BRW_NEW_WM_INPUT_DIMENSIONS */
-   /* Only set this for fixed function.  The optimization it enables isn't
-* useful for programs using shaders.
-*/
-   if (ctx-Shader.CurrentFragmentProgram)
-  key-proj_attrib_mask = ~(GLbitfield64) 0;
-   else {
-  /* Bit VARYING_BIT_POS of key.proj_attrib_mask is never used, so to
-   * avoid unnecessary recompiles, always set it to 1.
-   */
-  key-proj_attrib_mask = brw-wm.input_size_masks[4-1] | VARYING_BIT_POS;
-   }
-
/* _NEW_LIGHT */
key-flat_shade = (ctx-Light.ShadeModel == GL_FLAT);
 
diff --git a/src/mesa/drivers/dri/i965/brw_wm.h 
b/src/mesa/drivers/dri/i965/brw_wm.h
index f43d42c..28e8734 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.h
+++ b/src/mesa/drivers/dri/i965/brw_wm.h
@@ -67,8 +67,6 @@ struct brw_wm_prog_key {
GLuint clamp_fragment_color:1;
GLuint line_aa:2;
 
-   GLbitfield64 proj_attrib_mask; /** one bit per fragment program attribute 
*/
-
GLushort drawable_height;
GLbitfield64 input_slots_valid;
GLuint program_string_id:32;

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Mesa (master): i965: Delete brw_vs_constval. c and the brw_wm_input_sizes atom.

2013-04-04 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: d198546bac26256d92d6d4e1f2b0b12206416881
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d198546bac26256d92d6d4e1f2b0b12206416881

Author: Kenneth Graunke kenn...@whitecape.org
Date:   Tue Mar 12 21:12:08 2013 -0700

i965: Delete brw_vs_constval.c and the brw_wm_input_sizes atom.

This was only used to compute proj_attrib_mask, which was removed by the
previous commit.  That makes this dead code.

Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Eric Anholt e...@anholt.net

---

 src/mesa/drivers/dri/i965/Makefile.sources   |1 -
 src/mesa/drivers/dri/i965/brw_context.h  |5 -
 src/mesa/drivers/dri/i965/brw_state.h|1 -
 src/mesa/drivers/dri/i965/brw_state_upload.c |3 -
 src/mesa/drivers/dri/i965/brw_vs_constval.c  |  269 --
 5 files changed, 0 insertions(+), 279 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 59bf7b7..be8d630 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -91,7 +91,6 @@ i965_FILES = \
brw_vec4_visitor.cpp \
brw_vec4_vp.cpp \
brw_vs.c \
-   brw_vs_constval.c \
brw_vs_state.c \
brw_vs_surface_state.c \
brw_vtbl.c \
diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index ea5b62a..32ff30e 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1002,11 +1002,6 @@ struct brw_context
struct {
   struct brw_wm_prog_data *prog_data;
 
-  /** Input sizes, calculated from active vertex program.
-   * One bit per fragment program input attribute.
-   */
-  GLbitfield64 input_size_masks[4];
-
   /** offsets in the batch to sampler default colors (texture border color)
*/
   uint32_t sdc_offset[BRW_MAX_TEX_UNIT];
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index 0914cdd..9c956f8 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -72,7 +72,6 @@ extern const struct brw_tracked_state brw_vertex_state;
 extern const struct brw_tracked_state brw_vs_prog;
 extern const struct brw_tracked_state brw_vs_ubo_surfaces;
 extern const struct brw_tracked_state brw_vs_unit;
-extern const struct brw_tracked_state brw_wm_input_sizes;
 extern const struct brw_tracked_state brw_wm_prog;
 extern const struct brw_tracked_state brw_renderbuffer_surfaces;
 extern const struct brw_tracked_state brw_texture_surfaces;
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 5c5c05e..6488d40 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -38,7 +38,6 @@
 
 static const struct brw_tracked_state *gen4_atoms[] =
 {
-   brw_wm_input_sizes,
brw_vs_prog, /* must do before GS prog, state base address. */
brw_gs_prog, /* must do before state base address */
brw_clip_prog, /* must do before state base address */
@@ -103,7 +102,6 @@ static const struct brw_tracked_state *gen4_atoms[] =
 
 static const struct brw_tracked_state *gen6_atoms[] =
 {
-   brw_wm_input_sizes,
brw_vs_prog, /* must do before state base address */
brw_gs_prog, /* must do before state base address */
brw_wm_prog, /* must do before state base address */
@@ -175,7 +173,6 @@ static const struct brw_tracked_state *gen6_atoms[] =
 
 static const struct brw_tracked_state *gen7_atoms[] =
 {
-   brw_wm_input_sizes,
brw_vs_prog,
brw_wm_prog,
 
diff --git a/src/mesa/drivers/dri/i965/brw_vs_constval.c 
b/src/mesa/drivers/dri/i965/brw_vs_constval.c
deleted file mode 100644
index 13e8f70..000
--- a/src/mesa/drivers/dri/i965/brw_vs_constval.c
+++ /dev/null
@@ -1,269 +0,0 @@
-/*
- Copyright (C) Intel Corp.  2006.  All Rights Reserved.
- Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to
- develop this 3D driver.
- 
- Permission is hereby granted, free of charge, to any person obtaining
- a copy of this software and associated documentation files (the
- Software), to deal in the Software without restriction, including
- without limitation the rights to use, copy, modify, merge, publish,
- distribute, sublicense, and/or sell copies of the Software, and to
- permit persons to whom the Software is furnished to do so, subject to
- the following conditions:
- 
- The above copyright notice and this permission notice (including the
- next paragraph) shall be included in all copies or substantial
- portions of the Software.
- 
- THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND,
- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
- LIABLE

Mesa (master): i965: Remove BRW_NEW_WM_INPUT_DIMENSIONS dirty bit.

2013-04-04 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: b99ad7f02c5561b179d59418a64c2756c1d77f16
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b99ad7f02c5561b179d59418a64c2756c1d77f16

Author: Kenneth Graunke kenn...@whitecape.org
Date:   Tue Mar 12 22:16:37 2013 -0700

i965: Remove BRW_NEW_WM_INPUT_DIMENSIONS dirty bit.

This was only produced by the brw_wm_input_dimensions atom, which was
removed in the previous commit.  So there's no need for the dirty bit.

Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Eric Anholt e...@anholt.net

---

 src/mesa/drivers/dri/i965/brw_context.h  |2 --
 src/mesa/drivers/dri/i965/brw_state_upload.c |1 -
 src/mesa/drivers/dri/i965/brw_wm.c   |1 -
 3 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 32ff30e..ad19a0f 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -137,7 +137,6 @@ enum brw_state_id {
BRW_STATE_REDUCED_PRIMITIVE,
BRW_STATE_PRIMITIVE,
BRW_STATE_CONTEXT,
-   BRW_STATE_WM_INPUT_DIMENSIONS,
BRW_STATE_PSP,
BRW_STATE_SURFACES,
BRW_STATE_VS_BINDING_TABLE,
@@ -164,7 +163,6 @@ enum brw_state_id {
 #define BRW_NEW_REDUCED_PRIMITIVE   (1  BRW_STATE_REDUCED_PRIMITIVE)
 #define BRW_NEW_PRIMITIVE   (1  BRW_STATE_PRIMITIVE)
 #define BRW_NEW_CONTEXT (1  BRW_STATE_CONTEXT)
-#define BRW_NEW_WM_INPUT_DIMENSIONS (1  BRW_STATE_WM_INPUT_DIMENSIONS)
 #define BRW_NEW_PSP (1  BRW_STATE_PSP)
 #define BRW_NEW_SURFACES   (1  BRW_STATE_SURFACES)
 #define BRW_NEW_VS_BINDING_TABLE   (1  BRW_STATE_VS_BINDING_TABLE)
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 6488d40..c0e6959 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -359,7 +359,6 @@ static struct dirty_bit_map brw_bits[] = {
DEFINE_BIT(BRW_NEW_REDUCED_PRIMITIVE),
DEFINE_BIT(BRW_NEW_PRIMITIVE),
DEFINE_BIT(BRW_NEW_CONTEXT),
-   DEFINE_BIT(BRW_NEW_WM_INPUT_DIMENSIONS),
DEFINE_BIT(BRW_NEW_PSP),
DEFINE_BIT(BRW_NEW_SURFACES),
DEFINE_BIT(BRW_NEW_VS_BINDING_TABLE),
diff --git a/src/mesa/drivers/dri/i965/brw_wm.c 
b/src/mesa/drivers/dri/i965/brw_wm.c
index 35d6876..9b30ba1 100644
--- a/src/mesa/drivers/dri/i965/brw_wm.c
+++ b/src/mesa/drivers/dri/i965/brw_wm.c
@@ -508,7 +508,6 @@ const struct brw_tracked_state brw_wm_prog = {
_NEW_TEXTURE |
_NEW_MULTISAMPLE),
   .brw   = (BRW_NEW_FRAGMENT_PROGRAM |
-   BRW_NEW_WM_INPUT_DIMENSIONS |
BRW_NEW_REDUCED_PRIMITIVE |
 BRW_NEW_VUE_MAP_GEOM_OUT)
},

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Mesa (master): i965: Turn brw-urb.vs_size and gs_size into local variables .

2013-04-04 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: 8cdb2d32ecd636a6d68840a68504c1fe1b14426b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8cdb2d32ecd636a6d68840a68504c1fe1b14426b

Author: Kenneth Graunke kenn...@whitecape.org
Date:   Tue Apr  2 21:11:50 2013 -0700

i965: Turn brw-urb.vs_size and gs_size into local variables.

These variables are only used within a single function, so we may as
well make them local variables.

Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Paul Berry stereotype...@gmail.com

---

 src/mesa/drivers/dri/i965/brw_context.h |9 -
 src/mesa/drivers/dri/i965/gen6_urb.c|   18 +-
 src/mesa/drivers/dri/i965/gen7_urb.c|7 +++
 3 files changed, 12 insertions(+), 22 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index ad19a0f..9ac5856 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -857,15 +857,6 @@ struct brw_context
   GLuint nr_sf_entries;
   GLuint nr_cs_entries;
 
-  /* gen6:
-   * The length of each URB entry owned by the VS (or GS), as
-   * a number of 1024-bit (128-byte) rows.  Should be = 1.
-   *
-   * gen7: Same meaning, but in 512-bit (64-byte) rows.
-   */
-  GLuint vs_size;
-  GLuint gs_size;
-
   GLuint vs_start;
   GLuint gs_start;
   GLuint clip_start;
diff --git a/src/mesa/drivers/dri/i965/gen6_urb.c 
b/src/mesa/drivers/dri/i965/gen6_urb.c
index 2d69cbe..aa985de 100644
--- a/src/mesa/drivers/dri/i965/gen6_urb.c
+++ b/src/mesa/drivers/dri/i965/gen6_urb.c
@@ -54,7 +54,7 @@ gen6_upload_urb( struct brw_context *brw )
int total_urb_size = brw-urb.size * 1024; /* in bytes */
 
/* CACHE_NEW_VS_PROG */
-   brw-urb.vs_size = MAX2(brw-vs.prog_data-urb_entry_size, 1);
+   unsigned vs_size = MAX2(brw-vs.prog_data-urb_entry_size, 1);
 
/* We use the same VUE layout for VS outputs and GS outputs (as it's what
 * the SF and Clipper expect), so we can simply make the GS URB entry size
@@ -62,14 +62,14 @@ gen6_upload_urb( struct brw_context *brw )
 * where we have few vertex attributes and a lot of varyings, since the VS
 * size is determined by the larger of the two.  For now, it's safe.
 */
-   brw-urb.gs_size = brw-urb.vs_size;
+   unsigned gs_size = vs_size;
 
/* Calculate how many entries fit in each stage's section of the URB */
if (brw-gs.prog_active) {
-  nr_vs_entries = (total_urb_size/2) / (brw-urb.vs_size * 128);
-  nr_gs_entries = (total_urb_size/2) / (brw-urb.gs_size * 128);
+  nr_vs_entries = (total_urb_size/2) / (vs_size * 128);
+  nr_gs_entries = (total_urb_size/2) / (gs_size * 128);
} else {
-  nr_vs_entries = total_urb_size / (brw-urb.vs_size * 128);
+  nr_vs_entries = total_urb_size / (vs_size * 128);
   nr_gs_entries = 0;
}
 
@@ -87,14 +87,14 @@ gen6_upload_urb( struct brw_context *brw )
assert(brw-urb.nr_vs_entries = 24);
assert(brw-urb.nr_vs_entries % 4 == 0);
assert(brw-urb.nr_gs_entries % 4 == 0);
-   assert(brw-urb.vs_size  5);
-   assert(brw-urb.gs_size  5);
+   assert(vs_size  5);
+   assert(gs_size  5);
 
BEGIN_BATCH(3);
OUT_BATCH(_3DSTATE_URB  16 | (3 - 2));
-   OUT_BATCH(((brw-urb.vs_size - 1)  GEN6_URB_VS_SIZE_SHIFT) |
+   OUT_BATCH(((vs_size - 1)  GEN6_URB_VS_SIZE_SHIFT) |
 ((brw-urb.nr_vs_entries)  GEN6_URB_VS_ENTRIES_SHIFT));
-   OUT_BATCH(((brw-urb.gs_size - 1)  GEN6_URB_GS_SIZE_SHIFT) |
+   OUT_BATCH(((gs_size - 1)  GEN6_URB_GS_SIZE_SHIFT) |
 ((brw-urb.nr_gs_entries)  GEN6_URB_GS_ENTRIES_SHIFT));
ADVANCE_BATCH();
 
diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c 
b/src/mesa/drivers/dri/i965/gen7_urb.c
index 481497b..dafe1ad 100644
--- a/src/mesa/drivers/dri/i965/gen7_urb.c
+++ b/src/mesa/drivers/dri/i965/gen7_urb.c
@@ -82,9 +82,9 @@ gen7_upload_urb(struct brw_context *brw)
int handle_region_size = (brw-urb.size - 16) * 1024; /* bytes */
 
/* CACHE_NEW_VS_PROG */
-   brw-urb.vs_size = MAX2(brw-vs.prog_data-urb_entry_size, 1);
+   unsigned vs_size = MAX2(brw-vs.prog_data-urb_entry_size, 1);
 
-   int nr_vs_entries = handle_region_size / (brw-urb.vs_size * 64);
+   int nr_vs_entries = handle_region_size / (vs_size * 64);
if (nr_vs_entries  brw-urb.max_vs_entries)
   nr_vs_entries = brw-urb.max_vs_entries;
 
@@ -100,8 +100,7 @@ gen7_upload_urb(struct brw_context *brw)
assert(!brw-gs.prog_active);
 
gen7_emit_vs_workaround_flush(intel);
-   gen7_emit_urb_state(brw, brw-urb.nr_vs_entries, brw-urb.vs_size,
-   brw-urb.vs_start);
+   gen7_emit_urb_state(brw, brw-urb.nr_vs_entries, vs_size, 
brw-urb.vs_start);
 }
 
 void

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Mesa (master): glsl: Add an optimization pass to flatten simple nested if blocks.

2013-04-04 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: edc52a8f280db8d9dc9a04314741319ea8b83e67
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=edc52a8f280db8d9dc9a04314741319ea8b83e67

Author: Kenneth Graunke kenn...@whitecape.org
Date:   Wed Apr  3 23:56:57 2013 -0700

glsl: Add an optimization pass to flatten simple nested if blocks.

GLBenchmark 2.7's shaders contain conditional blocks like:

if (x) {
if (y) {
...
}
}

where the outer conditional's then clause contains exactly one statement
(the nested if) and there are no else clauses.  This can easily be
optimized into:

if (x  y) {
...
}

This saves a few instructions in GLBenchmark 2.7:

total instructions in shared programs: 11833 - 11649 (-1.55%)
instructions in affected programs: 8234 - 8050 (-2.23%)

It also helps CS:GO slightly (-0.05%/-0.22%).  More importantly,
however, it simplifies the control flow graph, which could enable other
optimizations.

Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Matt Turner matts...@gmail.com
Reviewed-by: Eric Anholt e...@anholt.net

---

 src/glsl/Makefile.sources |1 +
 src/glsl/glsl_parser_extras.cpp   |1 +
 src/glsl/ir_optimization.h|1 +
 src/glsl/opt_flatten_nested_if_blocks.cpp |  103 +
 4 files changed, 106 insertions(+), 0 deletions(-)

diff --git a/src/glsl/Makefile.sources b/src/glsl/Makefile.sources
index c294aa4..b5282a6 100644
--- a/src/glsl/Makefile.sources
+++ b/src/glsl/Makefile.sources
@@ -80,6 +80,7 @@ LIBGLSL_FILES = \
$(GLSL_SRCDIR)/opt_dead_code.cpp \
$(GLSL_SRCDIR)/opt_dead_code_local.cpp \
$(GLSL_SRCDIR)/opt_dead_functions.cpp \
+   $(GLSL_SRCDIR)/opt_flatten_nested_if_blocks.cpp \
$(GLSL_SRCDIR)/opt_function_inlining.cpp \
$(GLSL_SRCDIR)/opt_if_simplification.cpp \
$(GLSL_SRCDIR)/opt_noop_swizzle.cpp \
diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp
index 9740903..0992294 100644
--- a/src/glsl/glsl_parser_extras.cpp
+++ b/src/glsl/glsl_parser_extras.cpp
@@ -1218,6 +1218,7 @@ do_common_optimization(exec_list *ir, bool linked,
   progress = do_structure_splitting(ir) || progress;
}
progress = do_if_simplification(ir) || progress;
+   progress = opt_flatten_nested_if_blocks(ir) || progress;
progress = do_copy_propagation(ir) || progress;
progress = do_copy_propagation_elements(ir) || progress;
if (linked)
diff --git a/src/glsl/ir_optimization.h b/src/glsl/ir_optimization.h
index 2454bbe..a8885d7 100644
--- a/src/glsl/ir_optimization.h
+++ b/src/glsl/ir_optimization.h
@@ -82,6 +82,7 @@ bool do_function_inlining(exec_list *instructions);
 bool do_lower_jumps(exec_list *instructions, bool pull_out_jumps = true, bool 
lower_sub_return = true, bool lower_main_return = false, bool lower_continue = 
false, bool lower_break = false);
 bool do_lower_texture_projection(exec_list *instructions);
 bool do_if_simplification(exec_list *instructions);
+bool opt_flatten_nested_if_blocks(exec_list *instructions);
 bool do_discard_simplification(exec_list *instructions);
 bool lower_if_to_cond_assign(exec_list *instructions, unsigned max_depth = 0);
 bool do_mat_op_to_vec(exec_list *instructions);
diff --git a/src/glsl/opt_flatten_nested_if_blocks.cpp 
b/src/glsl/opt_flatten_nested_if_blocks.cpp
new file mode 100644
index 000..c702102
--- /dev/null
+++ b/src/glsl/opt_flatten_nested_if_blocks.cpp
@@ -0,0 +1,103 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+/**
+ * \file opt_flatten_nested_if_blocks.cpp
+ *
+ * Flattens nested if blocks such as:
+ *
+ * if (x) {
+ *if (y) {
+ *   ...
+ *}
+ * }
+ *
+ * into a single if block with a combined condition:
+ *
+ * if (x  y) {
+ *...
+ * }
+ */
+
+#include ir.h
+#include ir_builder.h
+
+using namespace

Mesa (master): gallium/hud: initialize sampler state

2013-04-04 Thread Brian Paul 
Module: Mesa
Branch: master
Commit: 6211c45186745e58e7722f33562c028d4fe2cee3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6211c45186745e58e7722f33562c028d4fe2cee3

Author: Brian Paul bri...@vmware.com
Date:   Thu Apr  4 16:24:40 2013 -0600

gallium/hud: initialize sampler state

The default wrap mode (PIPE_TEX_WRAP_REPEAT) is incompatible with
unnormalized texcoords (at least for softpipe).

v2: use PIPE_TEX_WRAP_CLAMP_TO_EDGE

Reviewed-by: Marek Olšák mar...@gmail.com

---

 src/gallium/auxiliary/hud/hud_context.c |6 ++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/src/gallium/auxiliary/hud/hud_context.c 
b/src/gallium/auxiliary/hud/hud_context.c
index b417f5d..bbefdd2 100644
--- a/src/gallium/auxiliary/hud/hud_context.c
+++ b/src/gallium/auxiliary/hud/hud_context.c
@@ -1018,6 +1018,12 @@ hud_create(struct pipe_context *pipe, struct cso_context 
*cso)
hud-font_sampler_view = pipe-create_sampler_view(pipe, hud-font.texture,
   view_templ);
 
+   /* sampler state (for font drawing) */
+   hud-font_sampler_state.wrap_s = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
+   hud-font_sampler_state.wrap_t = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
+   hud-font_sampler_state.wrap_r = PIPE_TEX_WRAP_CLAMP_TO_EDGE;
+   hud-font_sampler_state.normalized_coords = 0;
+
/* constants */
hud-constbuf.buffer_size = sizeof(hud-constants);
hud-constbuf.user_buffer = hud-constants;

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Mesa (master): gallium/hud: add GALLIUM_HUD_PERIOD env var

2013-04-04 Thread Brian Paul 
Module: Mesa
Branch: master
Commit: f5071783c112d516ac3a130e86f689323208b143
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5071783c112d516ac3a130e86f689323208b143

Author: Brian Paul bri...@vmware.com
Date:   Thu Apr  4 16:37:56 2013 -0600

gallium/hud: add GALLIUM_HUD_PERIOD env var

To set the graph update rate, in seconds.  The default update rate
has also been changed to 1/2 second.

Reviewed-by: Marek Olšák mar...@gmail.com

---

 src/gallium/auxiliary/hud/hud_context.c |   17 -
 1 files changed, 16 insertions(+), 1 deletions(-)

diff --git a/src/gallium/auxiliary/hud/hud_context.c 
b/src/gallium/auxiliary/hud/hud_context.c
index bbefdd2..983f057 100644
--- a/src/gallium/auxiliary/hud/hud_context.c
+++ b/src/gallium/auxiliary/hud/hud_context.c
@@ -703,12 +703,27 @@ hud_parse_env_var(struct hud_context *hud, const char 
*env)
struct hud_pane *pane = NULL;
unsigned x = 10, y = 10;
unsigned width = 251, height = 100;
+   unsigned period = 500 * 1000;  /* default period (1/2 second) */
+   const char *period_env;
+
+   /*
+* The GALLIUM_HUD_PERIOD env var sets the graph update rate.
+* The env var is in seconds (a float).
+* Zero means update after every frame.
+*/
+   period_env = getenv(GALLIUM_HUD_PERIOD);
+   if (period_env) {
+  float p = atof(period_env);
+  if (p = 0.0) {
+ period = (unsigned) (p * 1000 * 1000);
+  }
+   }
 
while ((num = parse_string(env, name)) != 0) {
   env += num;
 
   if (!pane) {
- pane = hud_pane_create(x, y, x + width, y + height, 4, 10);
+ pane = hud_pane_create(x, y, x + width, y + height, period, 10);
  if (!pane)
 return;
   }

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