Mesa (master): ilo: access bo size directly
Module: Mesa
Branch: master
Commit: 6fe0453c339b6e894e0ee8d2200e7638a43ed21e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6fe0453c339b6e894e0ee8d2200e7638a43ed21e
Author: Chia-I Wu
Date: Tue Jun 11 19:00:32 2013 +0800
ilo: access bo size directly
buf->bo_size is readily avaiable, no need to go via buf->bo->get_size().
---
src/gallium/drivers/ilo/ilo_gpe_gen6.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/ilo/ilo_gpe_gen6.c
b/src/gallium/drivers/ilo/ilo_gpe_gen6.c
index 6f9a354..536dbf8 100644
--- a/src/gallium/drivers/ilo/ilo_gpe_gen6.c
+++ b/src/gallium/drivers/ilo/ilo_gpe_gen6.c
@@ -767,7 +767,7 @@ gen6_emit_3DSTATE_VERTEX_BUFFERS(const struct ilo_dev_info
*dev,
if (vb->buffer && vb->stride <= 2048) {
const struct ilo_buffer *buf = ilo_buffer(vb->buffer);
const uint32_t start_offset = vb->buffer_offset;
- const uint32_t end_offset = buf->bo->get_size(buf->bo) - 1;
+ const uint32_t end_offset = buf->bo_size - 1;
dw |= vb->stride << BRW_VB0_PITCH_SHIFT;
@@ -1040,7 +1040,7 @@ gen6_emit_3DSTATE_INDEX_BUFFER(const struct ilo_dev_info
*dev,
}
/* end_offset must also be aligned */
- end_offset = buf->bo->get_size(buf->bo);
+ end_offset = buf->bo_size;
end_offset -= (end_offset % ib->index_size);
/* it is inclusive */
end_offset -= 1;
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Mesa (master): ilo: remove unnecessary tex_set_bo/buf_set_bo
Module: Mesa
Branch: master
Commit: 3f79188854fd7f63ad1eb0d4ab1fc24117fd0d78
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f79188854fd7f63ad1eb0d4ab1fc24117fd0d78
Author: Chia-I Wu
Date: Tue Jun 11 18:51:22 2013 +0800
ilo: remove unnecessary tex_set_bo/buf_set_bo
Merge the bodies to tex_create_bo/buf_create_bo respectively.
---
src/gallium/drivers/ilo/ilo_resource.c | 60 +--
1 files changed, 18 insertions(+), 42 deletions(-)
diff --git a/src/gallium/drivers/ilo/ilo_resource.c
b/src/gallium/drivers/ilo/ilo_resource.c
index 270724c..85cff90 100644
--- a/src/gallium/drivers/ilo/ilo_resource.c
+++ b/src/gallium/drivers/ilo/ilo_resource.c
@@ -861,8 +861,8 @@ tex_alloc_slices(struct ilo_texture *tex)
return true;
}
-static struct intel_bo *
-tex_create_bo(const struct ilo_texture *tex,
+static bool
+tex_create_bo(struct ilo_texture *tex,
const struct winsys_handle *handle)
{
struct ilo_screen *is = ilo_screen(tex->base.screen);
@@ -909,12 +909,9 @@ tex_create_bo(const struct ilo_texture *tex,
tex->tiling, tex->bo_flags);
}
- return bo;
-}
+ if (!bo)
+ return false;
-static void
-tex_set_bo(struct ilo_texture *tex, struct intel_bo *bo)
-{
if (tex->bo)
tex->bo->unreference(tex->bo);
@@ -923,6 +920,8 @@ tex_set_bo(struct ilo_texture *tex, struct intel_bo *bo)
/* winsys may decide to use a different tiling */
tex->tiling = tex->bo->get_tiling(tex->bo);
tex->bo_stride = tex->bo->get_pitch(tex->bo);
+
+ return true;
}
static void
@@ -943,7 +942,6 @@ tex_create(struct pipe_screen *screen,
{
struct tex_layout layout;
struct ilo_texture *tex;
- struct intel_bo *bo;
tex = CALLOC_STRUCT(ilo_texture);
if (!tex)
@@ -1003,15 +1001,12 @@ tex_create(struct pipe_screen *screen,
tex_layout_apply(&layout, tex);
- bo = tex_create_bo(tex, handle);
- if (!bo) {
+ if (!tex_create_bo(tex, handle)) {
tex_free_slices(tex);
FREE(tex);
return NULL;
}
- tex_set_bo(tex, bo);
-
/* allocate separate stencil resource */
if (layout.separate_stencil) {
struct pipe_resource s8_templ = *layout.templ;
@@ -1074,11 +1069,12 @@ tex_estimate_size(struct pipe_screen *screen,
return tex_layout_estimate_size(&layout);
}
-static struct intel_bo *
-buf_create_bo(const struct ilo_buffer *buf)
+static bool
+buf_create_bo(struct ilo_buffer *buf)
{
struct ilo_screen *is = ilo_screen(buf->base.screen);
const char *name;
+ struct intel_bo *bo;
switch (buf->base.bind) {
case PIPE_BIND_VERTEX_BUFFER:
@@ -1098,17 +1094,17 @@ buf_create_bo(const struct ilo_buffer *buf)
break;
}
- return is->winsys->alloc_buffer(is->winsys,
+ bo = is->winsys->alloc_buffer(is->winsys,
name, buf->bo_size, buf->bo_flags);
-}
+ if (!bo)
+ return false;
-static void
-buf_set_bo(struct ilo_buffer *buf, struct intel_bo *bo)
-{
if (buf->bo)
buf->bo->unreference(buf->bo);
buf->bo = bo;
+
+ return true;
}
static void
@@ -1122,7 +1118,6 @@ static struct pipe_resource *
buf_create(struct pipe_screen *screen, const struct pipe_resource *templ)
{
struct ilo_buffer *buf;
- struct intel_bo *bo;
buf = CALLOC_STRUCT(ilo_buffer);
if (!buf)
@@ -1135,14 +1130,11 @@ buf_create(struct pipe_screen *screen, const struct
pipe_resource *templ)
buf->bo_size = templ->width0;
buf->bo_flags = 0;
- bo = buf_create_bo(buf);
- if (!bo) {
+ if (!buf_create_bo(buf)) {
FREE(buf);
return NULL;
}
- buf_set_bo(buf, bo);
-
return &buf->base;
}
@@ -1224,33 +1216,17 @@ ilo_init_resource_functions(struct ilo_screen *is)
bool
ilo_buffer_alloc_bo(struct ilo_buffer *buf)
{
- struct intel_bo *bo;
-
- bo = buf_create_bo(buf);
- if (!bo)
- return false;
-
- buf_set_bo(buf, bo);
-
- return true;
+ return buf_create_bo(buf);
}
bool
ilo_texture_alloc_bo(struct ilo_texture *tex)
{
- struct intel_bo *bo;
-
/* a shared bo cannot be reallocated */
if (tex->imported)
return false;
- bo = tex_create_bo(tex, NULL);
- if (!bo)
- return false;
-
- tex_set_bo(tex, bo);
-
- return true;
+ return tex_create_bo(tex, NULL);
}
/**
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Mesa (master): ilo: update winsys interface
Module: Mesa
Branch: master
Commit: 39226705b7ee79504b5b09669e5420cd7c374713
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=39226705b7ee79504b5b09669e5420cd7c374713
Author: Chia-I Wu
Date: Wed Jun 12 16:38:38 2013 +0800
ilo: update winsys interface
The motivation is to kill tiling and pitch in struct intel_bo. That requires
us to make tiling and pitch not queryable, and be passed around as function
parameters.
---
src/gallium/drivers/ilo/ilo_resource.c | 21 +--
src/gallium/winsys/intel/drm/intel_drm_winsys.c | 68 +++
src/gallium/winsys/intel/intel_winsys.h | 40 +++---
3 files changed, 66 insertions(+), 63 deletions(-)
diff --git a/src/gallium/drivers/ilo/ilo_resource.c
b/src/gallium/drivers/ilo/ilo_resource.c
index 1b29100..8824b97 100644
--- a/src/gallium/drivers/ilo/ilo_resource.c
+++ b/src/gallium/drivers/ilo/ilo_resource.c
@@ -868,6 +868,8 @@ tex_create_bo(struct ilo_texture *tex,
struct ilo_screen *is = ilo_screen(tex->base.screen);
const char *name;
struct intel_bo *bo;
+ enum intel_tiling_mode tiling;
+ unsigned long pitch;
switch (tex->base.target) {
case PIPE_TEXTURE_1D:
@@ -900,13 +902,16 @@ tex_create_bo(struct ilo_texture *tex,
}
if (handle) {
- bo = intel_winsys_import_handle(is->winsys, name,
-tex->bo_width, tex->bo_height, tex->bo_cpp, handle);
+ bo = intel_winsys_import_handle(is->winsys, name, handle,
+tex->bo_width, tex->bo_height, tex->bo_cpp,
+&tiling, &pitch);
}
else {
- bo = intel_winsys_alloc(is->winsys, name,
+ bo = intel_winsys_alloc_texture(is->winsys, name,
tex->bo_width, tex->bo_height, tex->bo_cpp,
-tex->tiling, tex->bo_flags);
+tex->tiling, tex->bo_flags, &pitch);
+
+ tiling = tex->tiling;
}
if (!bo)
@@ -916,8 +921,8 @@ tex_create_bo(struct ilo_texture *tex,
intel_bo_unreference(tex->bo);
tex->bo = bo;
- tex->tiling = intel_bo_get_tiling(bo);
- tex->bo_stride = intel_bo_get_pitch(bo);
+ tex->tiling = tiling;
+ tex->bo_stride = pitch;
return true;
}
@@ -1034,9 +1039,11 @@ tex_create(struct pipe_screen *screen,
static bool
tex_get_handle(struct ilo_texture *tex, struct winsys_handle *handle)
{
+ struct ilo_screen *is = ilo_screen(tex->base.screen);
int err;
- err = intel_bo_export_handle(tex->bo, handle);
+ err = intel_winsys_export_handle(is->winsys, tex->bo,
+ tex->tiling, tex->bo_stride, handle);
return !err;
}
diff --git a/src/gallium/winsys/intel/drm/intel_drm_winsys.c
b/src/gallium/winsys/intel/drm/intel_drm_winsys.c
index e75eb4f..d441138 100644
--- a/src/gallium/winsys/intel/drm/intel_drm_winsys.c
+++ b/src/gallium/winsys/intel/drm/intel_drm_winsys.c
@@ -59,12 +59,14 @@ struct intel_bo {
struct pipe_reference reference;
drm_intel_bo *bo;
- enum intel_tiling_mode tiling;
- unsigned long pitch;
};
int
-intel_bo_export_handle(struct intel_bo *bo, struct winsys_handle *handle)
+intel_winsys_export_handle(struct intel_winsys *winsys,
+ struct intel_bo *bo,
+ enum intel_tiling_mode tiling,
+ unsigned long pitch,
+ struct winsys_handle *handle)
{
int err = 0;
@@ -100,7 +102,7 @@ intel_bo_export_handle(struct intel_bo *bo, struct
winsys_handle *handle)
if (err)
return err;
- handle->stride = bo->pitch;
+ handle->stride = pitch;
return 0;
}
@@ -176,10 +178,13 @@ intel_bo_map_unsynchronized(struct intel_bo *bo)
return drm_intel_gem_bo_map_unsynchronized(bo->bo);
}
-int
+void
intel_bo_unmap(struct intel_bo *bo)
{
- return drm_intel_bo_unmap(bo->bo);
+ int err;
+
+ err = drm_intel_bo_unmap(bo->bo);
+ assert(!err);
}
int
@@ -214,18 +219,6 @@ intel_bo_get_virtual(const struct intel_bo *bo)
return bo->bo->virtual;
}
-enum intel_tiling_mode
-intel_bo_get_tiling(const struct intel_bo *bo)
-{
- return bo->tiling;
-}
-
-unsigned long
-intel_bo_get_pitch(const struct intel_bo *bo)
-{
- return bo->pitch;
-}
-
void
intel_bo_reference(struct intel_bo *bo)
{
@@ -251,36 +244,38 @@ create_bo(void)
return NULL;
pipe_reference_init(&bo->reference, 1);
- bo->tiling = INTEL_TILING_NONE;
- bo->pitch = 0;
return bo;
}
struct intel_bo *
-intel_winsys_alloc(struct intel_winsys *winsys,
- const char *name,
- int width, int height, int cpp,
- enum intel_tiling_mode tiling,
- unsigned long flags)
+intel_winsys_alloc_texture(struct intel_winsys *winsys,
+ const char *name,
+ int width, int height, int cpp,
+ enum intel_tiling_mode tiling,
+ unsigned long flags,
+ unsigned long *pitch)
{
struct intel_bo *bo;
Mesa (master): winsys/intel: make struct intel_bo alias drm_intel_bo
Module: Mesa
Branch: master
Commit: adf324ad28ccd9c6fdb8461661b95c2b5d49b6f7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=adf324ad28ccd9c6fdb8461661b95c2b5d49b6f7
Author: Chia-I Wu
Date: Wed Jun 12 17:05:26 2013 +0800
winsys/intel: make struct intel_bo alias drm_intel_bo
There is really nothing in struct intel_bo, and having it alias drm_intel_bo
makes the winsys impose almost zero overhead.
We can make the overhead gone completely by making the functions static
inline, if needed.
---
src/gallium/winsys/intel/drm/intel_drm_winsys.c | 172 +++
1 files changed, 50 insertions(+), 122 deletions(-)
diff --git a/src/gallium/winsys/intel/drm/intel_drm_winsys.c
b/src/gallium/winsys/intel/drm/intel_drm_winsys.c
index f4e8bd4..4d121bb 100644
--- a/src/gallium/winsys/intel/drm/intel_drm_winsys.c
+++ b/src/gallium/winsys/intel/drm/intel_drm_winsys.c
@@ -47,18 +47,9 @@
struct intel_winsys {
int fd;
drm_intel_bufmgr *bufmgr;
- struct drm_intel_decode *decode;
-
struct intel_winsys_info info;
- drm_intel_bo **drm_bo_array;
- int array_size;
-};
-
-struct intel_bo {
- struct pipe_reference reference;
-
- drm_intel_bo *bo;
+ struct drm_intel_decode *decode;
};
static bool
@@ -164,7 +155,6 @@ intel_winsys_destroy(struct intel_winsys *winsys)
drm_intel_decode_context_free(winsys->decode);
drm_intel_bufmgr_destroy(winsys->bufmgr);
- FREE(winsys->drm_bo_array);
FREE(winsys);
}
@@ -201,20 +191,6 @@ intel_winsys_read_reg(struct intel_winsys *winsys,
return drm_intel_reg_read(winsys->bufmgr, reg, val);
}
-static struct intel_bo *
-create_bo(void)
-{
- struct intel_bo *bo;
-
- bo = CALLOC_STRUCT(intel_bo);
- if (!bo)
- return NULL;
-
- pipe_reference_init(&bo->reference, 1);
-
- return bo;
-}
-
struct intel_bo *
intel_winsys_alloc_buffer(struct intel_winsys *winsys,
const char *name,
@@ -222,27 +198,18 @@ intel_winsys_alloc_buffer(struct intel_winsys *winsys,
unsigned long flags)
{
const int alignment = 4096; /* always page-aligned */
- struct intel_bo *bo;
-
- bo = create_bo();
- if (!bo)
- return NULL;
+ drm_intel_bo *bo;
if (flags == INTEL_ALLOC_FOR_RENDER) {
- bo->bo = drm_intel_bo_alloc_for_render(winsys->bufmgr,
+ bo = drm_intel_bo_alloc_for_render(winsys->bufmgr,
name, size, alignment);
}
else {
assert(!flags);
- bo->bo = drm_intel_bo_alloc(winsys->bufmgr, name, size, alignment);
+ bo = drm_intel_bo_alloc(winsys->bufmgr, name, size, alignment);
}
- if (!bo->bo) {
- FREE(bo);
- return NULL;
- }
-
- return bo;
+ return (struct intel_bo *) bo;
}
struct intel_bo *
@@ -254,27 +221,20 @@ intel_winsys_alloc_texture(struct intel_winsys *winsys,
unsigned long *pitch)
{
uint32_t real_tiling = tiling;
- struct intel_bo *bo;
-
- bo = create_bo();
- if (!bo)
- return NULL;
+ drm_intel_bo *bo;
- bo->bo = drm_intel_bo_alloc_tiled(winsys->bufmgr, name,
+ bo = drm_intel_bo_alloc_tiled(winsys->bufmgr, name,
width, height, cpp, &real_tiling, pitch, flags);
- if (!bo->bo) {
- FREE(bo);
+ if (!bo)
return NULL;
- }
if (real_tiling != tiling) {
assert(!"tiling mismatch");
- drm_intel_bo_unreference(bo->bo);
- FREE(bo);
+ drm_intel_bo_unreference(bo);
return NULL;
}
- return bo;
+ return (struct intel_bo *) bo;
}
struct intel_bo *
@@ -285,51 +245,45 @@ intel_winsys_import_handle(struct intel_winsys *winsys,
enum intel_tiling_mode *tiling,
unsigned long *pitch)
{
- struct intel_bo *bo;
uint32_t real_tiling, swizzle;
+ drm_intel_bo *bo;
int err;
- bo = create_bo();
- if (!bo)
- return NULL;
-
switch (handle->type) {
case DRM_API_HANDLE_TYPE_SHARED:
{
const uint32_t gem_name = handle->handle;
- bo->bo = drm_intel_bo_gem_create_from_name(winsys->bufmgr,
+ bo = drm_intel_bo_gem_create_from_name(winsys->bufmgr,
name, gem_name);
}
break;
#if 0
- case DRM_API_HANDLE_TYPE_PRIME:
+ case DRM_API_HANDLE_TYPE_FD:
{
const int fd = (int) handle->handle;
- bo->bo = drm_intel_bo_gem_create_from_prime(winsys->bufmgr,
+ bo = drm_intel_bo_gem_create_from_prime(winsys->bufmgr,
fd, height * handle->stride);
}
break;
#endif
default:
+ bo = NULL;
break;
}
- if (!bo->bo) {
- FREE(bo);
+ if (!bo)
return NULL;
- }
- err = drm_intel_bo_get_tiling(bo->bo, &real_tiling, &swizzle);
+ err = drm_intel_bo_get_tiling(bo, &real_tiling, &swizzle);
if (err) {
- drm_intel_bo_unreference(bo->bo);
- FREE(bo);
+ drm_intel_bo_unreference(bo);
return NULL;
}
*tiling = real_tiling;
*pitch = ha
Mesa (master): ilo: get rid of function tables in winsys
Module: Mesa Branch: master Commit: cdfb2163c4cf6b54b6d8ba61f5460a29f58e3184 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cdfb2163c4cf6b54b6d8ba61f5460a29f58e3184 Author: Chia-I Wu Date: Wed Jun 12 16:21:00 2013 +0800 ilo: get rid of function tables in winsys We are moving toward making struct intel_bo alias drm_intel_bo. As a first step, we cannot have function tables. --- src/gallium/drivers/ilo/Android.mk |2 +- src/gallium/drivers/ilo/Makefile.am |2 +- src/gallium/drivers/ilo/ilo_3d.c| 18 +- src/gallium/drivers/ilo/ilo_3d_pipeline.c |6 +- src/gallium/drivers/ilo/ilo_3d_pipeline_dump.c |6 +- src/gallium/drivers/ilo/ilo_blit.c |6 +- src/gallium/drivers/ilo/ilo_context.c |8 +- src/gallium/drivers/ilo/ilo_cp.c| 32 +- src/gallium/drivers/ilo/ilo_cp.h|4 +- src/gallium/drivers/ilo/ilo_query.c |8 +- src/gallium/drivers/ilo/ilo_resource.c | 22 +- src/gallium/drivers/ilo/ilo_screen.c| 16 +- src/gallium/drivers/ilo/ilo_shader.c|8 +- src/gallium/drivers/ilo/ilo_transfer.c | 40 +- src/gallium/targets/dri-ilo/target.c|7 +- src/gallium/targets/egl-static/egl_pipe.c |4 +- src/gallium/winsys/intel/drm/intel_drm_public.h | 35 -- src/gallium/winsys/intel/drm/intel_drm_winsys.c | 501 +-- src/gallium/winsys/intel/drm/intel_winsys.h | 227 -- src/gallium/winsys/intel/intel_winsys.h | 261 20 files changed, 557 insertions(+), 656 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=cdfb2163c4cf6b54b6d8ba61f5460a29f58e3184 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): winsys/intel: reorganize functions
Module: Mesa
Branch: master
Commit: e7a14eea1616e597215f037708a56f8ad5850815
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e7a14eea1616e597215f037708a56f8ad5850815
Author: Chia-I Wu
Date: Wed Jun 12 16:56:49 2013 +0800
winsys/intel: reorganize functions
Move functions around to match the order of the declarations in the header.
---
src/gallium/winsys/intel/drm/intel_drm_winsys.c | 498 +++---
1 files changed, 249 insertions(+), 249 deletions(-)
diff --git a/src/gallium/winsys/intel/drm/intel_drm_winsys.c
b/src/gallium/winsys/intel/drm/intel_drm_winsys.c
index d441138..f4e8bd4 100644
--- a/src/gallium/winsys/intel/drm/intel_drm_winsys.c
+++ b/src/gallium/winsys/intel/drm/intel_drm_winsys.c
@@ -61,177 +61,144 @@ struct intel_bo {
drm_intel_bo *bo;
};
-int
-intel_winsys_export_handle(struct intel_winsys *winsys,
- struct intel_bo *bo,
- enum intel_tiling_mode tiling,
- unsigned long pitch,
- struct winsys_handle *handle)
+static bool
+get_param(struct intel_winsys *winsys, int param, int *value)
{
- int err = 0;
+ struct drm_i915_getparam gp;
+ int err;
- switch (handle->type) {
- case DRM_API_HANDLE_TYPE_SHARED:
- {
- uint32_t name;
+ *value = 0;
- err = drm_intel_bo_flink(bo->bo, &name);
- if (!err)
-handle->handle = name;
- }
- break;
- case DRM_API_HANDLE_TYPE_KMS:
- handle->handle = bo->bo->handle;
- break;
-#if 0
- case DRM_API_HANDLE_TYPE_PRIME:
- {
- int fd;
+ memset(&gp, 0, sizeof(gp));
+ gp.param = param;
+ gp.value = value;
- err = drm_intel_bo_gem_export_to_prime(bo->bo, &fd);
- if (!err)
-handle->handle = fd;
- }
-#endif
- break;
- default:
- err = -EINVAL;
- break;
+ err = drmCommandWriteRead(winsys->fd, DRM_I915_GETPARAM, &gp, sizeof(gp));
+ if (err) {
+ *value = 0;
+ return false;
}
- if (err)
- return err;
-
- handle->stride = pitch;
-
- return 0;
+ return true;
}
-int
-intel_bo_exec(struct intel_bo *bo, int used,
- struct intel_context *ctx, unsigned long flags)
+static bool
+test_address_swizzling(struct intel_winsys *winsys)
{
- if (ctx) {
- return drm_intel_gem_bo_context_exec(bo->bo,
-(drm_intel_context *) ctx, used, flags);
+ drm_intel_bo *bo;
+ uint32_t tiling = I915_TILING_X, swizzle;
+ unsigned long pitch;
+
+ bo = drm_intel_bo_alloc_tiled(winsys->bufmgr,
+ "address swizzling test", 64, 64, 4, &tiling, &pitch, 0);
+ if (bo) {
+ drm_intel_bo_get_tiling(bo, &tiling, &swizzle);
+ drm_intel_bo_unreference(bo);
}
else {
- return drm_intel_bo_mrb_exec(bo->bo, used, NULL, 0, 0, flags);
+ swizzle = I915_BIT_6_SWIZZLE_NONE;
}
+
+ return (swizzle != I915_BIT_6_SWIZZLE_NONE);
}
-int
-intel_bo_wait(struct intel_bo *bo, int64_t timeout)
+static bool
+init_info(struct intel_winsys *winsys)
{
- int err;
+ struct intel_winsys_info *info = &winsys->info;
+ int val;
- err = drm_intel_gem_bo_wait(bo->bo, timeout);
- /* consider the bo idle on errors */
- if (err && err != -ETIME)
- err = 0;
+ /* follow the classic driver here */
+ get_param(winsys, I915_PARAM_HAS_RELAXED_DELTA, &val);
+ if (!val) {
+ debug_error("kernel 2.6.39 required");
+ return false;
+ }
- return err;
-}
+ info->devid = drm_intel_bufmgr_gem_get_devid(winsys->bufmgr);
-int
-intel_bo_emit_reloc(struct intel_bo *bo, uint32_t offset,
-struct intel_bo *target_bo, uint32_t target_offset,
-uint32_t read_domains, uint32_t write_domain)
-{
- return drm_intel_bo_emit_reloc(bo->bo, offset,
- target_bo->bo, target_offset, read_domains, write_domain);
-}
+ get_param(winsys, I915_PARAM_HAS_LLC, &val);
+ info->has_llc = val;
-int
-intel_bo_get_reloc_count(struct intel_bo *bo)
-{
- return drm_intel_gem_bo_get_reloc_count(bo->bo);
-}
+ get_param(winsys, I915_PARAM_HAS_GEN7_SOL_RESET, &val);
+ info->has_gen7_sol_reset = val;
-void
-intel_bo_clear_relocs(struct intel_bo *bo, int start)
-{
- return drm_intel_gem_bo_clear_relocs(bo->bo, start);
-}
+ info->has_address_swizzling = test_address_swizzling(winsys);
-bool
-intel_bo_references(struct intel_bo *bo, struct intel_bo *target_bo)
-{
- return drm_intel_bo_references(bo->bo, target_bo->bo);
+ return true;
}
-int
-intel_bo_map(struct intel_bo *bo, bool write_enable)
+struct intel_winsys *
+intel_winsys_create_for_fd(int fd)
{
- return drm_intel_bo_map(bo->bo, write_enable);
-}
+ struct intel_winsys *winsys;
-int
-intel_bo_map_gtt(struct intel_bo *bo)
-{
- return drm_intel_gem_bo_map_gtt(bo->bo);
-}
+ winsys = CALLOC_STRUCT(intel_winsys);
+ if (!winsys)
+ return NULL;
-int
-intel_bo_map_unsynchronized(struct intel_bo *bo)
-{
- return drm_i
Demos (master): util: generalize linking geometry shaders, allow cxx inclusion
Module: Demos
Branch: master
Commit: d7004ec9ae0366a3a47a232a4362f20b9ad5247d
URL:
http://cgit.freedesktop.org/mesa/demos/commit/?id=d7004ec9ae0366a3a47a232a4362f20b9ad5247d
Author: RALOVICH, Kristóf
Date: Wed Jun 12 11:32:15 2013 +0200
util: generalize linking geometry shaders, allow cxx inclusion
Reviewed-by: Brian Paul
---
src/util/shaderutil.c | 43 +++
src/util/shaderutil.h | 12
2 files changed, 55 insertions(+), 0 deletions(-)
diff --git a/src/util/shaderutil.c b/src/util/shaderutil.c
index 0fa300b..954f949 100644
--- a/src/util/shaderutil.c
+++ b/src/util/shaderutil.c
@@ -221,6 +221,49 @@ LinkShaders3(GLuint vertShader, GLuint geomShader, GLuint
fragShader)
}
+GLuint
+LinkShaders3WithGeometryInfo(GLuint vertShader, GLuint geomShader, GLuint
fragShader,
+ GLint verticesOut, GLenum inputType, GLenum
outputType)
+{
+ GLuint program = CreateProgram();
+ GLdouble t0, t1;
+
+ assert(vertShader || fragShader);
+
+ if (vertShader)
+AttachShader(program, vertShader);
+ if (geomShader) {
+AttachShader(program, geomShader);
+glProgramParameteriARB(program, GL_GEOMETRY_VERTICES_OUT_ARB, verticesOut);
+glProgramParameteriARB(program, GL_GEOMETRY_INPUT_TYPE_ARB, inputType);
+glProgramParameteriARB(program, GL_GEOMETRY_OUTPUT_TYPE_ARB, outputType);
+ }
+ if (fragShader)
+AttachShader(program, fragShader);
+
+ t0 = glutGet(GLUT_ELAPSED_TIME) * 0.001;
+ LinkProgram(program);
+ t1 = glutGet(GLUT_ELAPSED_TIME) * 0.001;
+
+ LinkTime = t1 - t0;
+
+ /* check link */
+ {
+GLint stat;
+GetProgramiv(program, GL_LINK_STATUS, &stat);
+if (!stat) {
+ GLchar log[1000];
+ GLsizei len;
+ GetProgramInfoLog(program, 1000, &len, log);
+ fprintf(stderr, "Shader link error:\n%s\n", log);
+ return 0;
+}
+ }
+
+ return program;
+}
+
+
GLboolean
ValidateShaderProgram(GLuint program)
{
diff --git a/src/util/shaderutil.h b/src/util/shaderutil.h
index 7af6a31..300a35b 100644
--- a/src/util/shaderutil.h
+++ b/src/util/shaderutil.h
@@ -2,6 +2,10 @@
#define SHADER_UTIL_H
+#ifdef __cplusplus
+extern "C" {
+#endif
+
struct uniform_info
{
@@ -39,6 +43,10 @@ LinkShaders(GLuint vertShader, GLuint fragShader);
extern GLuint
LinkShaders3(GLuint vertShader, GLuint geomShader, GLuint fragShader);
+extern GLuint
+LinkShaders3WithGeometryInfo(GLuint vertShader, GLuint geomShader, GLuint
fragShader,
+ GLint verticesOut, GLenum inputType, GLenum
outputType);
+
extern GLboolean
ValidateShaderProgram(GLuint program);
@@ -86,4 +94,8 @@ extern PFNGLUNIFORM4FVPROC Uniform4fv;
extern PFNGLGETACTIVEATTRIBPROC GetActiveAttrib;
extern PFNGLGETATTRIBLOCATIONPROC GetAttribLocation;
+#ifdef __cplusplus
+}
+#endif
+
#endif /* SHADER_UTIL_H */
___
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Demos (master): cmake: Use static runtime for MSVC builds too.
Module: Demos
Branch: master
Commit: 93c987197a8aa41acf6dcf4f818f94ef48959bb2
URL:
http://cgit.freedesktop.org/mesa/demos/commit/?id=93c987197a8aa41acf6dcf4f818f94ef48959bb2
Author: José Fonseca
Date: Wed Jun 12 16:27:31 2013 +0100
cmake: Use static runtime for MSVC builds too.
Just like for MinGW. So that we don't need to install MSVC
redistributables when running the demos on a fresh installed machine.
---
CMakeLists.txt | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 9340b4e..2402d1f 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -108,6 +108,17 @@ if (MSVC)
add_definitions (-D_CRT_SECURE_NO_DEPRECATE -D_CRT_SECURE_NO_WARNINGS
-D_CRT_NONSTDC_NO_WARNINGS)
add_definitions (-D_SCL_SECURE_NO_DEPRECATE -D_SCL_SECURE_NO_WARNINGS)
add_definitions (-wd4244) # conversion' conversion from 'type1' to
'type2', possible loss of data
+
+ # Use static runtime
+ #
http://www.cmake.org/Wiki/CMake_FAQ#How_can_I_build_my_MSVC_application_with_a_static_runtime.3F
+ foreach (flag_var
+ CMAKE_C_FLAGS CMAKE_C_FLAGS_DEBUG CMAKE_C_FLAGS_RELEASE
CMAKE_C_FLAGS_MINSIZEREL CMAKE_C_FLAGS_RELWITHDEBINFO
+ CMAKE_CXX_FLAGS CMAKE_CXX_FLAGS_DEBUG CMAKE_CXX_FLAGS_RELEASE
CMAKE_CXX_FLAGS_MINSIZEREL CMAKE_CXX_FLAGS_RELWITHDEBINFO
+ )
+ if (${flag_var} MATCHES "/MD")
+ string (REGEX REPLACE "/MD" "/MT" ${flag_var}
"${${flag_var}}")
+ endif ()
+ endforeach (flag_var)
endif (MSVC)
if (MINGW)
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Mesa (master): intel: Conditionally compile mcs-related code for i965 only.
Module: Mesa
Branch: master
Commit: 8f5147c199748ae129c527322823c2b40fb36941
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8f5147c199748ae129c527322823c2b40fb36941
Author: Paul Berry
Date: Mon May 20 13:29:39 2013 -0700
intel: Conditionally compile mcs-related code for i965 only.
This patch ifdefs out intel_mipmap_tree::mcs_mt when building the i915
(pre-Gen4) driver (MCS buffers aren't supported until Gen7, so there
is no need for this field in the i915 driver). This should make it a
bit easier to implement fast color clears without undue risk to i915.
Reviewed-by: Eric Anholt
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c |8 +++-
src/mesa/drivers/dri/intel/intel_mipmap_tree.h |2 ++
2 files changed, 9 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 08b5d42..ee763e5 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -671,7 +671,9 @@ intel_miptree_release(struct intel_mipmap_tree **mt)
intel_region_release(&((*mt)->region));
intel_miptree_release(&(*mt)->stencil_mt);
intel_miptree_release(&(*mt)->hiz_mt);
+#ifndef I915
intel_miptree_release(&(*mt)->mcs_mt);
+#endif
intel_miptree_release(&(*mt)->singlesample_mt);
intel_resolve_map_clear(&(*mt)->hiz_map);
@@ -1012,8 +1014,11 @@ intel_miptree_alloc_mcs(struct intel_context *intel,
struct intel_mipmap_tree *mt,
GLuint num_samples)
{
- assert(mt->mcs_mt == NULL);
assert(intel->gen >= 7); /* MCS only used on Gen7+ */
+#ifdef I915
+ return false;
+#else
+ assert(mt->mcs_mt == NULL);
/* Choose the correct format for the MCS buffer. All that really matters
* is that we allocate the right buffer size, since we'll always be
@@ -1070,6 +1075,7 @@ intel_miptree_alloc_mcs(struct intel_context *intel,
intel_miptree_unmap_raw(intel, mt->mcs_mt);
return mt->mcs_mt;
+#endif
}
/**
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
index cac518c..639d4be 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
@@ -373,6 +373,7 @@ struct intel_mipmap_tree
*/
struct intel_mipmap_tree *stencil_mt;
+#ifndef I915
/**
* \brief MCS miptree for multisampled textures.
*
@@ -381,6 +382,7 @@ struct intel_mipmap_tree
* (INTEL_MSAA_FORMAT_CMS).
*/
struct intel_mipmap_tree *mcs_mt;
+#endif
/* These are also refcounted:
*/
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Mesa (master): i965/gen7+: Create helper functions for single-sample MCS buffers.
Module: Mesa
Branch: master
Commit: dd3f950115218c69c9118436a5110a1ee6a2dda5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd3f950115218c69c9118436a5110a1ee6a2dda5
Author: Paul Berry
Date: Tue Apr 30 18:51:51 2013 -0700
i965/gen7+: Create helper functions for single-sample MCS buffers.
Reviewed-by: Eric Anholt
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 119
src/mesa/drivers/dri/intel/intel_mipmap_tree.h |9 ++
2 files changed, 128 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 601666c..a75ac81 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -124,6 +124,125 @@ compute_msaa_layout(struct intel_context *intel,
gl_format format, GLenum target
/**
+ * For single-sampled render targets ("non-MSRT"), the MCS buffer is a
+ * scaled-down bitfield representation of the color buffer which is capable of
+ * recording when blocks of the color buffer are equal to the clear value.
+ * This function returns the block size that will be used by the MCS buffer
+ * corresponding to a certain color miptree.
+ *
+ * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
+ * beneath the "Fast Color Clear" bullet (p327):
+ *
+ * The following table describes the RT alignment
+ *
+ * Pixels Lines
+ * TiledY RT CL
+ * bpp
+ * 32 8 4
+ * 64 4 4
+ * 128 2 4
+ * TiledX RT CL
+ * bpp
+ * 32 16 2
+ * 64 8 2
+ * 128 4 2
+ *
+ * This alignment has the following uses:
+ *
+ * - For figuring out the size of the MCS buffer. Each 4k tile in the MCS
+ * buffer contains 128 blocks horizontally and 256 blocks vertically.
+ *
+ * - For figuring out alignment restrictions for a fast clear operation. Fast
+ * clear operations must always clear aligned multiples of 16 blocks
+ * horizontally and 32 blocks vertically.
+ *
+ * - For scaling down the coordinates sent through the render pipeline during
+ * a fast clear. X coordinates must be scaled down by 8 times the block
+ * width, and Y coordinates by 16 times the block height.
+ *
+ * - For scaling down the coordinates sent through the render pipeline during
+ * a "Render Target Resolve" operation. X coordinates must be scaled down
+ * by half the block width, and Y coordinates by half the block height.
+ */
+void
+intel_get_non_msrt_mcs_alignment(struct intel_context *intel,
+ struct intel_mipmap_tree *mt,
+ unsigned *width_px, unsigned *height)
+{
+ switch (mt->region->tiling) {
+ default:
+ assert(!"Non-MSRT MCS requires X or Y tiling");
+ /* In release builds, fall through */
+ case I915_TILING_Y:
+ *width_px = 32 / mt->cpp;
+ *height = 4;
+ break;
+ case I915_TILING_X:
+ *width_px = 64 / mt->cpp;
+ *height = 2;
+ }
+}
+
+
+/**
+ * For a single-sampled render target ("non-MSRT"), determine if an MCS buffer
+ * can be used.
+ *
+ * From the Ivy Bridge PRM, Vol2 Part1 11.7 "MCS Buffer for Render Target(s)",
+ * beneath the "Fast Color Clear" bullet (p326):
+ *
+ * - Support is limited to tiled render targets.
+ * - Support is for non-mip-mapped and non-array surface types only.
+ *
+ * And then later, on p327:
+ *
+ * - MCS buffer for non-MSRT is supported only for RT formats 32bpp,
+ * 64bpp, and 128bpp.
+ */
+bool
+intel_is_non_msrt_mcs_buffer_supported(struct intel_context *intel,
+ struct intel_mipmap_tree *mt)
+{
+#ifdef I915
+ /* MCS is not supported on the i915 (pre-Gen4) driver */
+ return false;
+#else
+ struct brw_context *brw = brw_context(&intel->ctx);
+
+ /* MCS support does not exist prior to Gen7 */
+ if (intel->gen < 7)
+ return false;
+
+ /* MCS is only supported for color buffers */
+ switch (_mesa_get_format_base_format(mt->format)) {
+ case GL_DEPTH_COMPONENT:
+ case GL_DEPTH_STENCIL:
+ case GL_STENCIL_INDEX:
+ return false;
+ }
+
+ if (mt->region->tiling != I915_TILING_X &&
+ mt->region->tiling != I915_TILING_Y)
+ return false;
+ if (mt->cpp != 4 && mt->cpp != 8 && mt->cpp != 16)
+ return false;
+ if (mt->first_level != 0 || mt->last_level != 0)
+ return false;
+ if (mt->physical_depth0 != 1)
+ return false;
+
+ /* There's no point in using an MCS buffer if the surface isn't in a
+* renderable format.
+*/
+ if (!brw->format_supported_as_render_target[mt->format])
+ return false;
+
+ return true;
+#endif
+}
+
+
+/**
* @param for_bo Indicates that the caller is
*intel_miptree_create_for_bo(). If true, then do not create
*
Mesa (master): intel: Keep region name in intel_miptree_create_for_dri2_buffer().
Module: Mesa Branch: master Commit: a5efdca7b70a237b8786c595453f4599e38263ea URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5efdca7b70a237b8786c595453f4599e38263ea Author: Paul Berry Date: Tue May 28 13:29:53 2013 -0700 intel: Keep region name in intel_miptree_create_for_dri2_buffer(). When processing a buffer received from the X server, intel_process_dri2_buffer() examines intel_region::name to determine whether it's received a brand new buffer, or the same buffer it received from the X server the last time it made a request. However, this didn't work properly, because in the call to intel_miptree_create_for_dri2_buffer(), we create a fresh intel_region object to represent the buffer, and this was causing us to forget the buffer's previous name. This patch fixes things by copying over the region name when creating the fresh intel_region object. At the moment, this is just a minor performance optimization. However, when fast color clears are added, it will be necessary to ensure that the fast color clear state for a buffer doesn't get discarded the next time we receive that buffer from the X server. Reviewed-by: Eric Anholt --- src/mesa/drivers/dri/intel/intel_mipmap_tree.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index c336c46..08b5d42 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -575,6 +575,7 @@ intel_miptree_create_for_dri2_buffer(struct intel_context *intel, region->tiling); if (!singlesample_mt) return NULL; + singlesample_mt->region->name = region->name; if (num_samples == 0) return singlesample_mt; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/gen7+: Implement fast color clear operation in BLORP.
Module: Mesa
Branch: master
Commit: 5e5d4e021f7dde12fb0f4dfaf40fbbd4d119f4ab
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e5d4e021f7dde12fb0f4dfaf40fbbd4d119f4ab
Author: Paul Berry
Date: Wed May 1 08:04:12 2013 -0700
i965/gen7+: Implement fast color clear operation in BLORP.
Since we defer allocation of the MCS miptree until the time of the
fast clear operation, this patch also implements creation of the MCS
miptree.
In addition, this patch adds the field
intel_mipmap_tree::fast_clear_color_value, which holds the most recent
fast color clear value, if any. We use it to set the SURFACE_STATE's
clear color for render targets.
v2: Flag BRW_NEW_SURFACES when allocating the MCS miptree. Generate a
perf_debug message if clearing to a color that isn't compatible with
fast color clear. Fix "control reaches end of non-void function"
build warning.
Reviewed-by: Eric Anholt
---
src/mesa/drivers/dri/i965/brw_blorp.cpp |1 +
src/mesa/drivers/dri/i965/brw_blorp.h | 11 ++-
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 149 -
src/mesa/drivers/dri/i965/brw_clear.c |2 +-
src/mesa/drivers/dri/i965/brw_defines.h |2 +
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 18 ++-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 10 +-
src/mesa/drivers/dri/intel/intel_mipmap_tree.c| 48 +++
src/mesa/drivers/dri/intel/intel_mipmap_tree.h| 13 ++
9 files changed, 240 insertions(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index a2d02bf..9c9a4a7 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -145,6 +145,7 @@ brw_blorp_params::brw_blorp_params()
y1(0),
depth_format(0),
hiz_op(GEN6_HIZ_OP_NONE),
+ fast_clear_op(GEN7_FAST_CLEAR_OP_NONE),
num_samples(0),
use_wm_prog(false)
{
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 51b23db..0808206 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -47,7 +47,8 @@ brw_blorp_blit_miptrees(struct intel_context *intel,
bool mirror_x, bool mirror_y);
bool
-brw_blorp_clear_color(struct intel_context *intel, struct gl_framebuffer *fb);
+brw_blorp_clear_color(struct intel_context *intel, struct gl_framebuffer *fb,
+ bool partial_clear);
#ifdef __cplusplus
} /* end extern "C" */
@@ -192,6 +193,13 @@ struct brw_blorp_prog_data
bool persample_msaa_dispatch;
};
+
+enum gen7_fast_clear_op {
+ GEN7_FAST_CLEAR_OP_NONE,
+ GEN7_FAST_CLEAR_OP_FAST_CLEAR,
+};
+
+
class brw_blorp_params
{
public:
@@ -209,6 +217,7 @@ public:
brw_blorp_surface_info src;
brw_blorp_surface_info dst;
enum gen6_hiz_op hiz_op;
+ enum gen7_fast_clear_op fast_clear_op;
unsigned num_samples;
bool use_wm_prog;
brw_blorp_wm_push_constants wm_push_consts;
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index b626659..1f98360 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -49,7 +49,8 @@ public:
brw_blorp_clear_params(struct brw_context *brw,
struct gl_framebuffer *fb,
struct gl_renderbuffer *rb,
- GLubyte *color_mask);
+ GLubyte *color_mask,
+ bool partial_clear);
virtual uint32_t get_wm_prog(struct brw_context *brw,
brw_blorp_prog_data **prog_data) const;
@@ -105,10 +106,53 @@ brw_blorp_clear_program::~brw_blorp_clear_program()
ralloc_free(mem_ctx);
}
+
+/**
+ * Determine if fast color clear supports the given clear color.
+ *
+ * Fast color clear can only clear to color values of 1.0 or 0.0. At the
+ * moment we only support floating point, unorm, and snorm buffers.
+ */
+static bool
+is_color_fast_clear_compatible(struct intel_context *intel,
+ gl_format format,
+ const union gl_color_union *color)
+{
+ if (_mesa_is_format_integer_color(format))
+ return false;
+
+ for (int i = 0; i < 4; i++) {
+ if (color->f[i] != 0.0 && color->f[i] != 1.0) {
+ perf_debug("Clear color unsupported by fast color clear. "
+"Falling back to slow clear.");
+ return false;
+ }
+ }
+ return true;
+}
+
+
+/**
+ * Convert the given color to a bitfield suitable for ORing into DWORD 7 of
+ * SURFACE_STATE.
+ */
+static uint32_t
+compute_fast_clear_color_bits(const union gl_color_union *color)
+{
+ uint32_t bits = 0;
+ for (int i = 0; i < 4; i++) {
+ if (color->f[i] != 0.0)
+ bits |= 1 << (GEN7_SURFACE_CLEAR_COLOR_SHIFT + (3 - i));
+ }
+ return bits
Mesa (master): i965/blorp: Expand clear class hierarchy to prepare for RT resolves.
Module: Mesa
Branch: master
Commit: fac32c0bd31601c37f3aa01d69b655e0f75bbdef
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fac32c0bd31601c37f3aa01d69b655e0f75bbdef
Author: Paul Berry
Date: Mon May 6 09:38:42 2013 -0700
i965/blorp: Expand clear class hierarchy to prepare for RT resolves.
The fragment shaders that to do color clears will be re-used to
perform so-called "render target resolves" (the resolves associated
with fast color clears). To prepare for that, this patch expands the
class hierarchy for blorp params by adding
brw_blorp_const_color_params (which will be used for all blorp
operations where the fragment shader outputs a constant color).
Some other data structures and functions were also renamed to use
"const_color" nomenclature where appropriate.
Reviewed-by: Eric Anholt
---
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 58 ++--
src/mesa/drivers/dri/i965/brw_context.h |2 +-
2 files changed, 35 insertions(+), 25 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 1f98360..8df493e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -37,13 +37,28 @@ extern "C" {
#include "brw_eu.h"
#include "brw_state.h"
-struct brw_blorp_clear_prog_key
+struct brw_blorp_const_color_prog_key
{
bool use_simd16_replicated_data;
bool pad[3];
};
-class brw_blorp_clear_params : public brw_blorp_params
+/**
+ * Parameters for a blorp operation where the fragment shader outputs a
+ * constant color. This is used for both fast color clears and color
+ * resolves.
+ */
+class brw_blorp_const_color_params : public brw_blorp_params
+{
+public:
+ virtual uint32_t get_wm_prog(struct brw_context *brw,
+brw_blorp_prog_data **prog_data) const;
+
+protected:
+ brw_blorp_const_color_prog_key wm_prog_key;
+};
+
+class brw_blorp_clear_params : public brw_blorp_const_color_params
{
public:
brw_blorp_clear_params(struct brw_context *brw,
@@ -51,20 +66,14 @@ public:
struct gl_renderbuffer *rb,
GLubyte *color_mask,
bool partial_clear);
-
- virtual uint32_t get_wm_prog(struct brw_context *brw,
-brw_blorp_prog_data **prog_data) const;
-
-private:
- brw_blorp_clear_prog_key wm_prog_key;
};
-class brw_blorp_clear_program
+class brw_blorp_const_color_program
{
public:
- brw_blorp_clear_program(struct brw_context *brw,
- const brw_blorp_clear_prog_key *key);
- ~brw_blorp_clear_program();
+ brw_blorp_const_color_program(struct brw_context *brw,
+ const brw_blorp_const_color_prog_key *key);
+ ~brw_blorp_const_color_program();
const GLuint *compile(struct brw_context *brw, GLuint *program_size);
@@ -75,7 +84,7 @@ private:
void *mem_ctx;
struct brw_context *brw;
- const brw_blorp_clear_prog_key *key;
+ const brw_blorp_const_color_prog_key *key;
struct brw_compile func;
/* Thread dispatch header */
@@ -91,9 +100,9 @@ private:
GLuint base_mrf;
};
-brw_blorp_clear_program::brw_blorp_clear_program(
+brw_blorp_const_color_program::brw_blorp_const_color_program(
struct brw_context *brw,
- const brw_blorp_clear_prog_key *key)
+ const brw_blorp_const_color_prog_key *key)
: mem_ctx(ralloc_context(NULL)),
brw(brw),
key(key)
@@ -101,7 +110,7 @@ brw_blorp_clear_program::brw_blorp_clear_program(
brw_init_compile(brw, &func, mem_ctx);
}
-brw_blorp_clear_program::~brw_blorp_clear_program()
+brw_blorp_const_color_program::~brw_blorp_const_color_program()
{
ralloc_free(mem_ctx);
}
@@ -258,17 +267,18 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct
brw_context *brw,
}
uint32_t
-brw_blorp_clear_params::get_wm_prog(struct brw_context *brw,
- brw_blorp_prog_data **prog_data) const
+brw_blorp_const_color_params::get_wm_prog(struct brw_context *brw,
+ brw_blorp_prog_data **prog_data)
+ const
{
uint32_t prog_offset;
- if (!brw_search_cache(&brw->cache, BRW_BLORP_CLEAR_PROG,
+ if (!brw_search_cache(&brw->cache, BRW_BLORP_CONST_COLOR_PROG,
&this->wm_prog_key, sizeof(this->wm_prog_key),
&prog_offset, prog_data)) {
- brw_blorp_clear_program prog(brw, &this->wm_prog_key);
+ brw_blorp_const_color_program prog(brw, &this->wm_prog_key);
GLuint program_size;
const GLuint *program = prog.compile(brw, &program_size);
- brw_upload_cache(&brw->cache, BRW_BLORP_CLEAR_PROG,
+ brw_upload_cache(&brw->cache, BRW_BLORP_CONST_COLOR_PROG,
&this->wm_prog_key, sizeof(this->wm_prog_key),
program, program_size,
&prog.prog
Mesa (master): i965/gen7+: Disable fast color clears on shared regions.
Module: Mesa
Branch: master
Commit: ef9142d4a37c28bf6ae3527f71b9aa1b57ba9eb0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef9142d4a37c28bf6ae3527f71b9aa1b57ba9eb0
Author: Paul Berry
Date: Tue May 21 14:21:44 2013 -0700
i965/gen7+: Disable fast color clears on shared regions.
In certain circumstances the memory region underlying a miptree is
shared with other miptrees, or with other code outside Mesa's control.
This happens, for instance, when an extension like GL_OES_EGL_image or
GLX_EXT_texture_from_pixmap extension is used to associate a miptree
with an image existing outside of Mesa.
When this happens, we need to disable fast color clears on the miptree
in question, since there's no good synchronization mechanism to ensure
that deferred clear writes get performed by the time the buffer is
examined from the other miptree, or from outside of Mesa.
Fortunately, this should not be a performance hit for most
applications, since most applications that use these extensions use
them for importing textures into Mesa, rather than for exporting
rendered images out of Mesa. So most of the time the miptrees
involved will never experience a clear.
v2: Rework based on the fact that we have decided not to use an
accessor function to protect access to the region.
Reviewed-by: Eric Anholt
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 34
src/mesa/drivers/dri/intel/intel_mipmap_tree.h |4 +++
src/mesa/drivers/dri/intel/intel_screen.c |3 ++
src/mesa/drivers/dri/intel/intel_tex_image.c |1 +
4 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 4c98e90..5b767df 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -1475,6 +1475,40 @@ intel_miptree_resolve_color(struct intel_context *intel,
/**
+ * Make it possible to share the region backing the given miptree with another
+ * process or another miptree.
+ *
+ * Fast color clears are unsafe with shared buffers, so we need to resolve and
+ * then discard the MCS buffer, if present. We also set the mcs_state to
+ * INTEL_MCS_STATE_NONE to ensure that no MCS buffer gets allocated in the
+ * future.
+ */
+void
+intel_miptree_make_shareable(struct intel_context *intel,
+ struct intel_mipmap_tree *mt)
+{
+#ifdef I915
+ /* Nothing needs to be done for I915 */
+ (void) intel;
+ (void) mt;
+#else
+ /* MCS buffers are also used for multisample buffers, but we can't resolve
+* away a multisample MCS buffer because it's an integral part of how the
+* pixel data is stored. Fortunately this code path should never be
+* reached for multisample buffers.
+*/
+ assert(mt->msaa_layout == INTEL_MSAA_LAYOUT_NONE);
+
+ if (mt->mcs_mt) {
+ intel_miptree_resolve_color(intel, mt);
+ intel_miptree_release(&mt->mcs_mt);
+ mt->mcs_state = INTEL_MCS_STATE_NONE;
+ }
+#endif
+}
+
+
+/**
* \brief Get pointer offset into stencil buffer.
*
* The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
index 8ea1bef..6dab092 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
@@ -723,6 +723,10 @@ intel_miptree_resolve_color(struct intel_context *intel,
struct intel_mipmap_tree *mt);
void
+intel_miptree_make_shareable(struct intel_context *intel,
+ struct intel_mipmap_tree *mt);
+
+void
intel_miptree_downsample(struct intel_context *intel,
struct intel_mipmap_tree *mt);
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
b/src/mesa/drivers/dri/intel/intel_screen.c
index b4758f9..60a69a6 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -300,6 +300,8 @@ intel_setup_image_from_mipmap_tree(struct intel_context
*intel, __DRIimage *imag
unsigned int draw_x, draw_y;
uint32_t mask_x, mask_y;
+ intel_miptree_make_shareable(intel, mt);
+
intel_miptree_check_level_layer(mt, level, zoffset);
intel_region_get_tile_masks(mt->region, &mask_x, &mask_y, false);
@@ -396,6 +398,7 @@ intel_create_image_from_renderbuffer(__DRIcontext *context,
}
irb = intel_renderbuffer(rb);
+ intel_miptree_make_shareable(intel, irb->mt);
image = calloc(1, sizeof *image);
if (image == NULL)
return NULL;
diff --git a/src/mesa/drivers/dri/intel/intel_tex_image.c
b/src/mesa/drivers/dri/intel/intel_tex_image.c
index fba02c2..b91b2b5 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_image.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_image.c
@@ -342,6 +342,7 @@ intelSetTexBuffer2(__DRIcontext *pDRICtx, GLint target,
_mesa_lock_textu
Mesa (master): i965/gen7+: Set up MCS in SURFACE_STATE whenever MCS is present.
Module: Mesa
Branch: master
Commit: 460b7bc7a103d7a7518b4187f0c1dfc452f75137
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=460b7bc7a103d7a7518b4187f0c1dfc452f75137
Author: Paul Berry
Date: Wed May 1 07:16:52 2013 -0700
i965/gen7+: Set up MCS in SURFACE_STATE whenever MCS is present.
On Gen7+, MCS buffers are used both for compressed multisampled color
buffers and for "fast clear" of single-sampled color buffers.
Previous to this patch series, we didn't support fast clear, so we
only used MCS with multisampled bolor buffers.
As a first step to implementing fast clears, this patch modifies the
code that sets up SURFACE_STATE so that it configures the MCS buffer
whenever it is present, regardless of whether we are multisampling or
not.
Reviewed-by: Eric Anholt
---
src/mesa/drivers/dri/i965/gen7_blorp.cpp |2 +-
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |2 +-
src/mesa/drivers/dri/intel/intel_mipmap_tree.h|8 +---
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 68c7ca1..208c66a 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -194,7 +194,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
surf[3] = pitch_bytes - 1;
surf[4] = gen7_surface_msaa_bits(surface->num_samples,
surface->msaa_layout);
- if (surface->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+ if (surface->mt->mcs_mt) {
gen7_set_surface_mcs_info(brw, surf, wm_surf_offset, surface->mt->mcs_mt,
is_render_target);
}
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index 6a7c8de..3164f99 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -609,7 +609,7 @@ gen7_update_renderbuffer_surface(struct brw_context *brw,
min_array_element << GEN7_SURFACE_MIN_ARRAY_ELEMENT_SHIFT |
(depth - 1) << GEN7_SURFACE_RENDER_TARGET_VIEW_EXTENT_SHIFT;
- if (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) {
+ if (irb->mt->mcs_mt) {
gen7_set_surface_mcs_info(brw, surf, brw->wm.surf_offset[unit],
irb->mt->mcs_mt, true /* is RT */);
}
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
index d66d0b5..e2a7fe8 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h
@@ -443,11 +443,13 @@ struct intel_mipmap_tree
#ifndef I915
/**
-* \brief MCS miptree for multisampled textures.
+* \brief MCS miptree.
*
* This miptree contains the "multisample control surface", which stores
-* the necessary information to implement compressed MSAA on Gen7+
-* (INTEL_MSAA_FORMAT_CMS).
+* the necessary information to implement compressed MSAA
+* (INTEL_MSAA_FORMAT_CMS) and "fast color clear" behaviour on Gen7+.
+*
+* NULL if no MCS miptree is in use for this surface.
*/
struct intel_mipmap_tree *mcs_mt;
___
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Mesa (master): i965/gen7+: Create an enum for keeping track of fast color clear state.
Module: Mesa Branch: master Commit: 7e5cb4bc4c8dfc96019b815e2c9a62af12e1f958 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e5cb4bc4c8dfc96019b815e2c9a62af12e1f958 Author: Paul Berry Date: Tue May 7 14:04:29 2013 -0700 i965/gen7+: Create an enum for keeping track of fast color clear state. This patch includes code to update the fast color clear state appropriately when rendering occurs. The state will also need to be updated when a fast clear or a resolve operation is performed; those state updates will be added when the fast clear and resolve operations are added. v2: Create a new function, intel_miptree_used_for_rendering() to handle updating the fast color clear state when rendering occurs. Reviewed-by: Eric Anholt --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c |2 + src/mesa/drivers/dri/i965/gen6_blorp.cpp |1 + src/mesa/drivers/dri/i965/gen7_blorp.cpp |1 + src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |2 + src/mesa/drivers/dri/intel/intel_mipmap_tree.c|4 + src/mesa/drivers/dri/intel/intel_mipmap_tree.h| 94 + 6 files changed, 104 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 4d4d300..ceabedb 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -1346,6 +1346,8 @@ brw_update_renderbuffer_surface(struct brw_context *brw, } } + intel_miptree_used_for_rendering(irb->mt); + region = irb->mt->region; surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index bb87f6b..3ccd90e 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -1075,6 +1075,7 @@ gen6_blorp_exec(struct intel_context *intel, uint32_t wm_surf_offset_texture = 0; uint32_t sampler_offset; wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params); + intel_miptree_used_for_rendering(params->dst.mt); wm_surf_offset_renderbuffer = gen6_blorp_emit_surface_state(brw, params, ¶ms->dst, I915_GEM_DOMAIN_RENDER, diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index aa9a3ef..68c7ca1 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp @@ -862,6 +862,7 @@ gen7_blorp_exec(struct intel_context *intel, uint32_t wm_surf_offset_renderbuffer; uint32_t wm_surf_offset_texture = 0; wm_push_const_offset = gen6_blorp_emit_wm_constants(brw, params); + intel_miptree_used_for_rendering(params->dst.mt); wm_surf_offset_renderbuffer = gen7_blorp_emit_surface_state(brw, params, ¶ms->dst, I915_GEM_DOMAIN_RENDER, diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 22ceaa5..6a7c8de 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -545,6 +545,8 @@ gen7_update_renderbuffer_surface(struct brw_context *brw, 8 * 4, 32, &brw->wm.surf_offset[unit]); memset(surf, 0, 8 * 4); + intel_miptree_used_for_rendering(irb->mt); + /* Render targets can't use IMS layout */ assert(irb->mt->msaa_layout != INTEL_MSAA_LAYOUT_IMS); diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index ee763e5..601666c 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -154,6 +154,9 @@ intel_miptree_create_layout(struct intel_context *intel, mt->logical_width0 = width0; mt->logical_height0 = height0; mt->logical_depth0 = depth0; +#ifndef I915 + mt->mcs_state = INTEL_MCS_STATE_NONE; +#endif /* The cpp is bytes per (1, blockheight)-sized block for compressed * textures. This is why you'll see divides by blockheight all over @@ -1048,6 +1051,7 @@ intel_miptree_alloc_mcs(struct intel_context *intel, * * "The MCS surface must be stored as Tile Y." */ + mt->mcs_state = INTEL_MCS_STATE_MSAA; mt->mcs_mt = intel_miptree_create(intel, mt->target, format, diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h index 639d4be..d66d0b5 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.h +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.h @@ -200,6 +200,74 @@ enum intel_msaa_layout INTEL_MSAA_LAYOUT_CMS, }; + +#ifndef I915 +/** + * Enum for keeping track of the state of an MCS buffer associated with a + * miptree
Mesa (master): i965/gen7+: Ensure that front/ back buffers are fast-clear resolved.
Module: Mesa
Branch: master
Commit: e9dfcb38e97ac05023759b749fb6f8f56ab28f57
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9dfcb38e97ac05023759b749fb6f8f56ab28f57
Author: Paul Berry
Date: Tue May 7 15:38:45 2013 -0700
i965/gen7+: Ensure that front/back buffers are fast-clear resolved.
We already had code in intel_downsample_for_dri2_flush() for
downsampling front and back buffers when multisampling was in use.
This patch extends that function to perform fast color clear resolves
when necessary.
To account for the additional functionality, the function is renamed
to simply intel_resolve_for_dri2_flush().
Reviewed-by: Eric Anholt
---
src/mesa/drivers/dri/intel/intel_context.c | 21 -
src/mesa/drivers/dri/intel/intel_context.h |4 ++--
src/mesa/drivers/dri/intel/intel_screen.c |2 +-
3 files changed, 15 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_context.c
b/src/mesa/drivers/dri/intel/intel_context.c
index 09b33b1..f669ae0 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -95,12 +95,12 @@ intelGetString(struct gl_context * ctx, GLenum name)
}
void
-intel_downsample_for_dri2_flush(struct intel_context *intel,
-__DRIdrawable *drawable)
+intel_resolve_for_dri2_flush(struct intel_context *intel,
+ __DRIdrawable *drawable)
{
if (intel->gen < 6) {
- /* MSAA is not supported, so don't waste time checking for
- * a multisample buffer.
+ /* MSAA and fast color clear are not supported, so don't waste time
+ * checking whether a resolve is needed.
*/
return;
}
@@ -120,7 +120,10 @@ intel_downsample_for_dri2_flush(struct intel_context
*intel,
rb = intel_get_renderbuffer(fb, buffers[i]);
if (rb == NULL || rb->mt == NULL)
continue;
- intel_miptree_downsample(intel, rb->mt);
+ if (rb->mt->num_samples <= 1)
+ intel_miptree_resolve_color(intel, rb->mt);
+ else
+ intel_miptree_downsample(intel, rb->mt);
}
}
@@ -137,14 +140,14 @@ intel_flush_front(struct gl_context *ctx)
driDrawable &&
driDrawable->loaderPrivate) {
- /* Downsample before flushing FAKE_FRONT_LEFT to FRONT_LEFT.
+ /* Resolve before flushing FAKE_FRONT_LEFT to FRONT_LEFT.
*
- * This potentially downsamples both front and back buffer. It
- * is unnecessary to downsample the back, but harms nothing except
+ * This potentially resolves both front and back buffer. It
+ * is unnecessary to resolve the back, but harms nothing except
* performance. And no one cares about front-buffer render
* performance.
*/
- intel_downsample_for_dri2_flush(intel, driDrawable);
+ intel_resolve_for_dri2_flush(intel, driDrawable);
screen->dri2.loader->flushFrontBuffer(driDrawable,
driDrawable->loaderPrivate);
diff --git a/src/mesa/drivers/dri/intel/intel_context.h
b/src/mesa/drivers/dri/intel/intel_context.h
index 5420e76..552b9cf 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -615,8 +615,8 @@ void intel_update_renderbuffers(__DRIcontext *context,
void intel_prepare_render(struct intel_context *intel);
void
-intel_downsample_for_dri2_flush(struct intel_context *intel,
-__DRIdrawable *drawable);
+intel_resolve_for_dri2_flush(struct intel_context *intel,
+ __DRIdrawable *drawable);
void i915_set_buf_info_for_region(uint32_t *state, struct intel_region *region,
uint32_t buffer_id);
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c
b/src/mesa/drivers/dri/intel/intel_screen.c
index 325304d..b4758f9 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -170,7 +170,7 @@ intelDRI2Flush(__DRIdrawable *drawable)
if (intel->gen < 4)
INTEL_FIREVERTICES(intel);
- intel_downsample_for_dri2_flush(intel, drawable);
+ intel_resolve_for_dri2_flush(intel, drawable);
intel->need_throttle = true;
if (intel->batch.used)
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Mesa (master): i965/blorp: Write blorp code to do render target resolves.
Module: Mesa
Branch: master
Commit: 418aecea7d626d57da8987c062aeb3d046c6dd9a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=418aecea7d626d57da8987c062aeb3d046c6dd9a
Author: Paul Berry
Date: Mon May 6 10:37:04 2013 -0700
i965/blorp: Write blorp code to do render target resolves.
This patch implements the "render target resolve" blorp operation.
This will be needed when a buffer that has experienced a fast color
clear is later used for a purpose other than as a render target
(texturing, glReadPixels, or swapped to the screen). It resolves any
remaining deferred clear operation that was not taken care of during
normal rendering.
Fortunately not much work is necessary; all we need to do is scale
down the size of the rectangle primitive being emitted, run the
fragment shader with the "Render Target Resolve Enable" bit set, and
ensure that the fragment shader writes to the render target using the
"replicated color" message. We already have a fragment shader that
does that (the shader that we use for fast color clears), so for
simplicity we re-use it.
Reviewed-by: Eric Anholt
---
src/mesa/drivers/dri/i965/brw_blorp.h |5 ++
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 60
src/mesa/drivers/dri/i965/brw_defines.h|1 +
src/mesa/drivers/dri/i965/gen7_blorp.cpp |3 +
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 23 +
src/mesa/drivers/dri/intel/intel_mipmap_tree.h |4 ++
6 files changed, 96 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 0808206..ffc27cc 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -50,6 +50,10 @@ bool
brw_blorp_clear_color(struct intel_context *intel, struct gl_framebuffer *fb,
bool partial_clear);
+void
+brw_blorp_resolve_color(struct intel_context *intel,
+struct intel_mipmap_tree *mt);
+
#ifdef __cplusplus
} /* end extern "C" */
@@ -197,6 +201,7 @@ struct brw_blorp_prog_data
enum gen7_fast_clear_op {
GEN7_FAST_CLEAR_OP_NONE,
GEN7_FAST_CLEAR_OP_FAST_CLEAR,
+ GEN7_FAST_CLEAR_OP_RESOLVE,
};
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 8df493e..1e2205e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -68,6 +68,20 @@ public:
bool partial_clear);
};
+
+/**
+ * Parameters for a blorp operation that performs a "render target resolve".
+ * This is used to resolve pending fast clear pixels before a color buffer is
+ * used for texturing, ReadPixels, or scanout.
+ */
+class brw_blorp_rt_resolve_params : public brw_blorp_const_color_params
+{
+public:
+ brw_blorp_rt_resolve_params(struct brw_context *brw,
+ struct intel_mipmap_tree *mt);
+};
+
+
class brw_blorp_const_color_program
{
public:
@@ -266,6 +280,43 @@ brw_blorp_clear_params::brw_blorp_clear_params(struct
brw_context *brw,
}
}
+
+brw_blorp_rt_resolve_params::brw_blorp_rt_resolve_params(
+ struct brw_context *brw,
+ struct intel_mipmap_tree *mt)
+{
+ dst.set(brw, mt, 0 /* level */, 0 /* layer */);
+
+ /* From the Ivy Bridge PRM, Vol2 Part1 11.9 "Render Target Resolve":
+*
+* A rectangle primitive must be scaled down by the following factors
+* with respect to render target being resolved.
+*
+* The scaledown factors in the table that follows are related to the
+* alignment size returned by intel_get_non_msrt_mcs_alignment(), but with
+* X and Y alignment each divided by 2.
+*/
+ unsigned x_align, y_align;
+ intel_get_non_msrt_mcs_alignment(&brw->intel, mt, &x_align, &y_align);
+ unsigned x_scaledown = x_align / 2;
+ unsigned y_scaledown = y_align / 2;
+ x0 = y0 = 0;
+ x1 = ALIGN(mt->logical_width0, x_scaledown) / x_scaledown;
+ y1 = ALIGN(mt->logical_height0, y_scaledown) / y_scaledown;
+
+ fast_clear_op = GEN7_FAST_CLEAR_OP_RESOLVE;
+
+ /* Note: there is no need to initialize push constants because it doesn't
+* matter what data gets dispatched to the render target. However, we must
+* ensure that the fragment shader delivers the data using the "replicated
+* color" message.
+*/
+ use_wm_prog = true;
+ memset(&wm_prog_key, 0, sizeof(wm_prog_key));
+ wm_prog_key.use_simd16_replicated_data = true;
+}
+
+
uint32_t
brw_blorp_const_color_params::get_wm_prog(struct brw_context *brw,
brw_blorp_prog_data **prog_data)
@@ -452,4 +503,13 @@ brw_blorp_clear_color(struct intel_context *intel, struct
gl_framebuffer *fb,
return true;
}
+void
+brw_blorp_resolve_color(struct intel_context *intel, struct intel_mipmap_tree
*mt)
+{
+ struct brw_context *brw = brw_context(&intel->ctx);
+ brw_blorp_rt_resolve_pa
Mesa (master): i965/gen7: Enable support for fast color clears.
Module: Mesa Branch: master Commit: b09a75407886fba476bb79d65b408ffc08876a75 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b09a75407886fba476bb79d65b408ffc08876a75 Author: Paul Berry Date: Tue May 21 11:58:38 2013 -0700 i965/gen7: Enable support for fast color clears. This patch adds code to place mcs_state into INTEL_MCS_STATE_RESOLVED for miptrees that are capable of supporting fast color clears. This will have no effect on buffers that don't undergo a fast color clear; however, for buffers that do undergo a fast color clear, an MCS miptree will be allocated (at the time of the first fast clear), and will be used thereafter. Reviewed-by: Eric Anholt --- src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 20 1 files changed, 20 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c index 5b767df..1776a4b 100644 --- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c @@ -608,6 +608,16 @@ intel_miptree_create(struct intel_context *intel, return NULL; } +#ifndef I915 + /* If this miptree is capable of supporting fast color clears, set +* mcs_state appropriately to ensure that fast clears will occur. +* Allocation of the MCS miptree will be deferred until the first fast +* clear actually occurs. +*/ + if (intel_is_non_msrt_mcs_buffer_supported(intel, mt)) + mt->mcs_state = INTEL_MCS_STATE_RESOLVED; +#endif + return mt; } @@ -699,6 +709,16 @@ intel_miptree_create_for_dri2_buffer(struct intel_context *intel, return NULL; singlesample_mt->region->name = region->name; +#ifndef I915 + /* If this miptree is capable of supporting fast color clears, set +* mcs_state appropriately to ensure that fast clears will occur. +* Allocation of the MCS miptree will be deferred until the first fast +* clear actually occurs. +*/ + if (intel_is_non_msrt_mcs_buffer_supported(intel, singlesample_mt)) + singlesample_mt->mcs_state = INTEL_MCS_STATE_RESOLVED; +#endif + if (num_samples == 0) return singlesample_mt; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/gen7+: Resolve color buffers when necessary.
Module: Mesa
Branch: master
Commit: 67cd0f97030a358777c01ee6ad79926717dfdf42
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=67cd0f97030a358777c01ee6ad79926717dfdf42
Author: Paul Berry
Date: Tue May 7 14:55:42 2013 -0700
i965/gen7+: Resolve color buffers when necessary.
Resolve color buffers that have been fast-color cleared:
1. before texturing from the buffer (brw_predraw_resolve_buffers())
2. before using the buffer as the source in a blorp blit
(brw_blorp_blit_miptrees())
3. before mapping the buffer's miptree (intel_miptree_map_raw(),
intel_texsubimage_tiled_memcpy())
4. before accessing the buffer using the hardware blitter
(intel_miptree_blit(), do_blit_bitmap())
v2: Rework based on the fact that we have decided not to use an
accessor function to protect access to the region.
Reviewed-by: Eric Anholt
---
src/mesa/drivers/dri/i965/brw_blorp_blit.cpp|7 +++
src/mesa/drivers/dri/i965/brw_blorp_clear.cpp |1 +
src/mesa/drivers/dri/i965/brw_draw.c|6 +-
src/mesa/drivers/dri/intel/intel_blit.c | 11 +--
src/mesa/drivers/dri/intel/intel_mipmap_tree.c |5 +
src/mesa/drivers/dri/intel/intel_pixel_bitmap.c |5 +
src/mesa/drivers/dri/intel/intel_tex_subimage.c |5 +
7 files changed, 37 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
index a6b2bbf..7b063ff 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit.cpp
@@ -134,6 +134,13 @@ brw_blorp_blit_miptrees(struct intel_context *intel,
float dst_x1, float dst_y1,
bool mirror_x, bool mirror_y)
{
+ /* Get ready to blit. This includes depth resolving the src and dst
+* buffers if necessary. Note: it's not necessary to do a color resolve on
+* the destination buffer because we use the standard render path to render
+* to destination color buffers, and the standard render path is
+* fast-color-aware.
+*/
+ intel_miptree_resolve_color(intel, src_mt);
intel_miptree_slice_resolve_depth(intel, src_mt, src_level, src_layer);
intel_miptree_slice_resolve_depth(intel, dst_mt, dst_level, dst_layer);
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
index 1e2205e..85449bd 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
@@ -507,6 +507,7 @@ void
brw_blorp_resolve_color(struct intel_context *intel, struct intel_mipmap_tree
*mt)
{
struct brw_context *brw = brw_context(&intel->ctx);
+
brw_blorp_rt_resolve_params params(brw, mt);
brw_blorp_exec(intel, ¶ms);
mt->mcs_state = INTEL_MCS_STATE_RESOLVED;
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 657d6ee..5730eed 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -41,6 +41,7 @@
#include "swrast_setup/swrast_setup.h"
#include "drivers/common/meta.h"
+#include "brw_blorp.h"
#include "brw_draw.h"
#include "brw_defines.h"
#include "brw_context.h"
@@ -310,7 +311,9 @@ brw_predraw_resolve_buffers(struct brw_context *brw)
if (depth_irb)
intel_renderbuffer_resolve_hiz(intel, depth_irb);
- /* Resolve depth buffer of each enabled depth texture. */
+ /* Resolve depth buffer of each enabled depth texture, and color buffer of
+* each fast-clear-enabled color texture.
+*/
for (int i = 0; i < BRW_MAX_TEX_UNIT; i++) {
if (!ctx->Texture.Unit[i]._ReallyEnabled)
continue;
@@ -318,6 +321,7 @@ brw_predraw_resolve_buffers(struct brw_context *brw)
if (!tex_obj || !tex_obj->mt)
continue;
intel_miptree_all_slices_resolve_depth(intel, tex_obj->mt);
+ intel_miptree_resolve_color(intel, tex_obj->mt);
}
}
diff --git a/src/mesa/drivers/dri/intel/intel_blit.c
b/src/mesa/drivers/dri/intel/intel_blit.c
index 1f6ad09..fffbef4 100644
--- a/src/mesa/drivers/dri/intel/intel_blit.c
+++ b/src/mesa/drivers/dri/intel/intel_blit.c
@@ -140,11 +140,13 @@ intel_miptree_blit(struct intel_context *intel,
return false;
}
- /* The blitter has no idea about HiZ, so we need to get the real depth
-* data into the two miptrees before we do anything.
+ /* The blitter has no idea about HiZ or fast color clears, so we need to
+* resolve the miptrees before we do anything.
*/
intel_miptree_slice_resolve_depth(intel, src_mt, src_level, src_slice);
intel_miptree_slice_resolve_depth(intel, dst_mt, dst_level, dst_slice);
+ intel_miptree_resolve_color(intel, src_mt);
+ intel_miptree_resolve_color(intel, dst_mt);
if (src_flip)
src_y = src_mt->level[src_level].height - src_y - height;
@@ -368,6 +370,11 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
Mesa (master): gallivm: (trivial) remove duplicated code block ( including comment)
Module: Mesa
Branch: master
Commit: 957c040eb86495da2a693c831e13342a81ac1a2e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=957c040eb86495da2a693c831e13342a81ac1a2e
Author: Roland Scheidegger
Date: Thu Jun 13 00:40:24 2013 +0200
gallivm: (trivial) remove duplicated code block (including comment)
---
src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c |7 ---
1 files changed, 0 insertions(+), 7 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
index 066f64a..0bbc408 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
@@ -1784,13 +1784,6 @@ emit_sample(struct lp_build_tgsi_soa_context *bld,
return;
}
- /*
-* unlike old-style tex opcodes the texture/sampler indices
-* always come from src1 and src2 respectively.
-*/
- texture_unit = inst->Src[1].Register.Index;
- sampler_unit = inst->Src[2].Register.Index;
-
if (modifier == LP_BLD_TEX_MODIFIER_LOD_BIAS) {
lod_bias = lp_build_emit_fetch( &bld->bld_base, inst, 3, 0 );
explicit_lod = NULL;
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Mesa (master): util: new util_fill_box helper
Module: Mesa
Branch: master
Commit: 4cce4efaa38e95c121343565de5e517345d6a9dd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4cce4efaa38e95c121343565de5e517345d6a9dd
Author: Roland Scheidegger
Date: Thu Jun 13 00:40:34 2013 +0200
util: new util_fill_box helper
Use new util_fill_box helper for util_clear_render_target.
(Also fix off-by-one map error.)
v2: handle non-zero z correctly in new helper
Reviewed-by: Jose Fonseca
---
src/gallium/auxiliary/util/u_surface.c | 40 +--
src/gallium/auxiliary/util/u_surface.h |7
src/gallium/drivers/llvmpipe/lp_rast.c | 54 +++-
3 files changed, 62 insertions(+), 39 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_surface.c
b/src/gallium/auxiliary/util/u_surface.c
index 77d04ba..17591f1 100644
--- a/src/gallium/auxiliary/util/u_surface.c
+++ b/src/gallium/auxiliary/util/u_surface.c
@@ -214,6 +214,30 @@ util_fill_rect(ubyte * dst,
}
+void
+util_fill_box(ubyte * dst,
+ enum pipe_format format,
+ unsigned stride,
+ unsigned layer_stride,
+ unsigned x,
+ unsigned y,
+ unsigned z,
+ unsigned width,
+ unsigned height,
+ unsigned depth,
+ union util_color *uc)
+{
+ unsigned layer;
+ dst += z * layer_stride;
+ for (layer = z; layer < depth; layer++) {
+ util_fill_rect(dst, format,
+ stride,
+ x, y, width, height, uc);
+ dst += layer_stride;
+ }
+}
+
+
/**
* Fallback function for pipe->resource_copy_region().
* Note: (X,Y)=(0,0) is always the upper-left corner.
@@ -319,7 +343,7 @@ util_clear_render_target(struct pipe_context *pipe,
struct pipe_transfer *dst_trans;
ubyte *dst_map;
union util_color uc;
- unsigned max_layer, layer;
+ unsigned max_layer;
assert(dst->texture);
if (!dst->texture)
@@ -349,7 +373,7 @@ util_clear_render_target(struct pipe_context *pipe,
dst->u.tex.level,
PIPE_TRANSFER_WRITE,
dstx, dsty, dst->u.tex.first_layer,
- width, height, max_layer, &dst_trans);
+ width, height, max_layer + 1, &dst_trans);
}
assert(dst_map);
@@ -376,12 +400,9 @@ util_clear_render_target(struct pipe_context *pipe,
util_pack_color(color->f, dst->format, &uc);
}
- for (layer = 0; layer <= max_layer; layer++) {
- util_fill_rect(dst_map, dst->format,
-dst_trans->stride,
-0, 0, width, height, &uc);
- dst_map += dst_trans->layer_stride;
- }
+ util_fill_box(dst_map, dst->format,
+dst_trans->stride, dst_trans->layer_stride,
+0, 0, 0, width, height, max_layer + 1, &uc);
pipe->transfer_unmap(pipe, dst_trans);
}
@@ -430,8 +451,7 @@ util_clear_depth_stencil(struct pipe_context *pipe,
if (dst_map) {
unsigned dst_stride = dst_trans->stride;
- uint64_t zstencil = util_pack64_z_stencil(format,
-depth, stencil);
+ uint64_t zstencil = util_pack64_z_stencil(format, depth, stencil);
ubyte *dst_layer = dst_map;
unsigned i, j;
assert(dst_trans->stride > 0);
diff --git a/src/gallium/auxiliary/util/u_surface.h
b/src/gallium/auxiliary/util/u_surface.h
index d6184ac..bfd8f40 100644
--- a/src/gallium/auxiliary/util/u_surface.h
+++ b/src/gallium/auxiliary/util/u_surface.h
@@ -65,6 +65,13 @@ util_fill_rect(ubyte * dst, enum pipe_format format,
unsigned dst_stride, unsigned dst_x, unsigned dst_y,
unsigned width, unsigned height, union util_color *uc);
+extern void
+util_fill_box(ubyte * dst, enum pipe_format format,
+ unsigned stride, unsigned layer_stride,
+ unsigned x, unsigned y, unsigned z,
+ unsigned width, unsigned height, unsigned depth,
+ union util_color *uc);
+
extern void
util_resource_copy_region(struct pipe_context *pipe,
diff --git a/src/gallium/drivers/llvmpipe/lp_rast.c
b/src/gallium/drivers/llvmpipe/lp_rast.c
index dcd66ab..79d4c58 100644
--- a/src/gallium/drivers/llvmpipe/lp_rast.c
+++ b/src/gallium/drivers/llvmpipe/lp_rast.c
@@ -135,8 +135,6 @@ lp_rast_clear_color(struct lp_rasterizer_task *task,
for (i = 0; i < scene->fb.nr_cbufs; i++) {
enum pipe_format format = scene->fb.cbufs[i]->format;
-unsigned layer;
-uint8_t *map_layer = scene->cbufs[i].map;
if (util_format_is_pure_sint(format)) {
util_format_write_4i(format, arg.clear_color.i, 0, &uc, 0, 0,
0, 1, 1);
@@ -146,17 +144,17 @@ lp_rast_clear_color(struct lp_rasterizer_task *task,
util_format_write_4ui(format, arg.cle
Mesa (master): glsl: Add gl_shader_program::UniformLocationBaseScale
Module: Mesa
Branch: master
Commit: 26d86d26f9f972b19c7040bdb1b1daf48537ef3e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=26d86d26f9f972b19c7040bdb1b1daf48537ef3e
Author: Ian Romanick
Date: Mon Jun 10 10:35:05 2013 -0700
glsl: Add gl_shader_program::UniformLocationBaseScale
This is used by _mesa_uniform_merge_location_offset and
_mesa_uniform_split_location_offset to determine how the base and offset
are packed. Previously, this value was hard coded as (1U<<16) in those
functions via the shift and mask contained therein. The value is still
(1U<<16), but it can be changed in the future.
The next patch dynamically generates this value.
NOTE: This is a candidate for stable release branches.
Signed-off-by: Ian Romanick
Reviewed-by: Brian Paul
Reviewed-and-tested-by: Chad Versace
---
src/glsl/link_uniforms.cpp |2 ++
src/mesa/main/mtypes.h | 15 +++
src/mesa/main/shaderobj.c |1 +
src/mesa/main/uniforms.h |8 +---
4 files changed, 23 insertions(+), 3 deletions(-)
diff --git a/src/glsl/link_uniforms.cpp b/src/glsl/link_uniforms.cpp
index 010296b..84680be 100644
--- a/src/glsl/link_uniforms.cpp
+++ b/src/glsl/link_uniforms.cpp
@@ -739,6 +739,8 @@ link_assign_uniform_locations(struct gl_shader_program
*prog)
sizeof(prog->_LinkedShaders[i]->SamplerTargets));
}
+ prog->UniformLocationBaseScale = (1U<<16);
+
#ifndef NDEBUG
for (unsigned i = 0; i < num_user_uniforms; i++) {
assert(uniforms[i].storage != NULL);
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 92a70f4..cd8650c 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2333,6 +2333,21 @@ struct gl_shader_program
unsigned NumUniformBlocks;
/**
+* Scale factor for the uniform base location
+*
+* This is used to generate locations (returned by \c glGetUniformLocation)
+* of uniforms. The base location of the uniform is multiplied by this
+* value, and the array index is added.
+*
+* \note
+* Must be >= 1.
+*
+* \sa
+* _mesa_uniform_merge_location_offset, _mesa_uniform_split_location_offset
+*/
+ unsigned UniformLocationBaseScale;
+
+ /**
* Indices into the _LinkedShaders's UniformBlocks[] array for each stage
* they're used in, or -1.
*
diff --git a/src/mesa/main/shaderobj.c b/src/mesa/main/shaderobj.c
index a60d8f3..a62ad04 100644
--- a/src/mesa/main/shaderobj.c
+++ b/src/mesa/main/shaderobj.c
@@ -283,6 +283,7 @@ _mesa_clear_shader_program_data(struct gl_context *ctx,
ralloc_free(shProg->UniformStorage);
shProg->NumUserUniformStorage = 0;
shProg->UniformStorage = NULL;
+ shProg->UniformLocationBaseScale = 0;
}
if (shProg->UniformHash) {
diff --git a/src/mesa/main/uniforms.h b/src/mesa/main/uniforms.h
index d718b0f..14fe26d 100644
--- a/src/mesa/main/uniforms.h
+++ b/src/mesa/main/uniforms.h
@@ -272,7 +272,9 @@ static inline GLint
_mesa_uniform_merge_location_offset(const struct gl_shader_program *prog,
unsigned base_location, unsigned offset)
{
- return (base_location << 16) | offset;
+ assert(prog->UniformLocationBaseScale >= 0);
+ assert(offset < prog->UniformLocationBaseScale);
+ return (base_location * prog->UniformLocationBaseScale) + offset;
}
/**
@@ -283,8 +285,8 @@ _mesa_uniform_split_location_offset(const struct
gl_shader_program *prog,
GLint location, unsigned *base_location,
unsigned *offset)
{
- *offset = location & 0x;
- *base_location = location >> 16;
+ *offset = location % prog->UniformLocationBaseScale;
+ *base_location = location / prog->UniformLocationBaseScale;
}
/*@}*/
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Mesa (master): glsl: Generate smaller values for uniform locations
Module: Mesa
Branch: master
Commit: cfa3c5ad828f56559a6cc2de299f993b8e748ea4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cfa3c5ad828f56559a6cc2de299f993b8e748ea4
Author: Ian Romanick
Date: Mon Jun 10 10:39:28 2013 -0700
glsl: Generate smaller values for uniform locations
Previously we would generate uniform locations as (slot << 16) +
array_index. We do this to handle applications that assume the location
of a[2] will be +1 from the location of a[1]. This resulted in every
uniform location being at least 0x1. The OpenGL 4.3 spec was
amended to require this behavior, but previous versions did not require
locations of array (or structure) members be sequential.
We've now encountered two applications that assume uniform values will
be "small." As far as we can tell, these applications store the GLint
returned by glGetUniformLocation in a int16_t or possibly an int8_t.
THIS BEHAVIOR IS NOT GUARANTEED OR IMPLIED BY ANY VERSION OF OpenGL.
Other implementations happen to have both these behaviors (sequential
array elements and small values) since OpenGL 2.0, so let's just match
their behavior.
Fixes "3D Bowling" on Android.
NOTE: This is a candidate for stable release branches.
Signed-off-by: Ian Romanick
Reviewed-by: Brian Paul
Reviewed-and-tested-by: Chad Versace
---
src/glsl/link_uniforms.cpp | 14 +-
1 files changed, 13 insertions(+), 1 deletions(-)
diff --git a/src/glsl/link_uniforms.cpp b/src/glsl/link_uniforms.cpp
index 84680be..208778e 100644
--- a/src/glsl/link_uniforms.cpp
+++ b/src/glsl/link_uniforms.cpp
@@ -739,7 +739,19 @@ link_assign_uniform_locations(struct gl_shader_program
*prog)
sizeof(prog->_LinkedShaders[i]->SamplerTargets));
}
- prog->UniformLocationBaseScale = (1U<<16);
+ /* Determine the size of the largest uniform array queryable via
+* glGetUniformLocation. Using this as the location scale guarantees that
+* there is enough "room" for the array index to be stored in the low order
+* part of the uniform location. It also makes the locations be more
+* tightly packed.
+*/
+ unsigned max_array_size = 1;
+ for (unsigned i = 0; i < num_user_uniforms; i++) {
+ if (uniforms[i].array_elements > max_array_size)
+ max_array_size = uniforms[i].array_elements;
+ }
+
+ prog->UniformLocationBaseScale = max_array_size;
#ifndef NDEBUG
for (unsigned i = 0; i < num_user_uniforms; i++) {
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Mesa (master): glsl: Add a gl_shader_program parameter to _mesa_uniform_{merge, split}_location_offset
Module: Mesa
Branch: master
Commit: 5097f358419c067a71e96e39764b3bb0a716bdbb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5097f358419c067a71e96e39764b3bb0a716bdbb
Author: Ian Romanick
Date: Mon Jun 10 10:33:59 2013 -0700
glsl: Add a gl_shader_program parameter to
_mesa_uniform_{merge,split}_location_offset
This will be used in the next commit.
NOTE: This is a candidate for stable release branches.
Signed-off-by: Ian Romanick
Reviewed-by: Brian Paul
Reviewed-and-tested-by: Chad Versace
---
src/mesa/main/uniform_query.cpp|2 +-
src/mesa/main/uniforms.c |2 +-
src/mesa/main/uniforms.h |6 --
src/mesa/state_tracker/st_glsl_to_tgsi.cpp |2 +-
4 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp
index ec31049..296f80f 100644
--- a/src/mesa/main/uniform_query.cpp
+++ b/src/mesa/main/uniform_query.cpp
@@ -235,7 +235,7 @@ validate_uniform_parameters(struct gl_context *ctx,
return false;
}
- _mesa_uniform_split_location_offset(location, loc, array_index);
+ _mesa_uniform_split_location_offset(shProg, location, loc, array_index);
if (*loc >= shProg->NumUserUniformStorage) {
_mesa_error(ctx, GL_INVALID_OPERATION, "%s(location=%d)",
diff --git a/src/mesa/main/uniforms.c b/src/mesa/main/uniforms.c
index 6d79df6..17e6240 100644
--- a/src/mesa/main/uniforms.c
+++ b/src/mesa/main/uniforms.c
@@ -538,7 +538,7 @@ _mesa_GetUniformLocation(GLhandleARB programObj, const
GLcharARB *name)
if (shProg->UniformStorage[index].block_index != -1)
return -1;
- return _mesa_uniform_merge_location_offset(index, offset);
+ return _mesa_uniform_merge_location_offset(shProg, index, offset);
}
GLuint GLAPIENTRY
diff --git a/src/mesa/main/uniforms.h b/src/mesa/main/uniforms.h
index 5ebd5e4..d718b0f 100644
--- a/src/mesa/main/uniforms.h
+++ b/src/mesa/main/uniforms.h
@@ -269,7 +269,8 @@ struct gl_builtin_uniform_desc {
* Combine the uniform's base location and the offset
*/
static inline GLint
-_mesa_uniform_merge_location_offset(unsigned base_location, unsigned offset)
+_mesa_uniform_merge_location_offset(const struct gl_shader_program *prog,
+unsigned base_location, unsigned offset)
{
return (base_location << 16) | offset;
}
@@ -278,7 +279,8 @@ _mesa_uniform_merge_location_offset(unsigned base_location,
unsigned offset)
* Separate the uniform base location and parameter offset
*/
static inline void
-_mesa_uniform_split_location_offset(GLint location, unsigned *base_location,
+_mesa_uniform_split_location_offset(const struct gl_shader_program *prog,
+GLint location, unsigned *base_location,
unsigned *offset)
{
*offset = location & 0x;
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index f8176eb..d6796d7 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -3096,7 +3096,7 @@ set_uniform_initializer(struct gl_context *ctx, void
*mem_ctx,
"Couldn't find uniform for initializer %s\n", name);
return;
}
- int loc = _mesa_uniform_merge_location_offset(index, offset);
+ int loc = _mesa_uniform_merge_location_offset(shader_program, index,
offset);
for (unsigned int i = 0; i < (type->is_array() ? type->length : 1); i++) {
ir_constant *element;
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Mesa (master): mesa: fix OES_EGL_image_external being partially allowed in the core profile
Module: Mesa
Branch: master
Commit: 45595d506646f560ab16af58acdea2fc563e942b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=45595d506646f560ab16af58acdea2fc563e942b
Author: Marek Olšák
Date: Wed May 29 17:32:44 2013 +0200
mesa: fix OES_EGL_image_external being partially allowed in the core profile
Reviewed-by: Chad Versace
---
src/glsl/glcpp/glcpp-parse.y | 14 +++---
src/mesa/drivers/common/meta.c |3 ++-
src/mesa/main/ff_fragment_shader.cpp |3 ++-
src/mesa/main/teximage.c |5 +++--
src/mesa/state_tracker/st_extensions.c |3 +--
5 files changed, 15 insertions(+), 13 deletions(-)
diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y
index fe36c12..6cb5009 100644
--- a/src/glsl/glcpp/glcpp-parse.y
+++ b/src/glsl/glcpp/glcpp-parse.y
@@ -1184,14 +1184,14 @@ glcpp_parser_create (const struct gl_extensions
*extensions, int api)
parser->is_gles = false;
/* Add pre-defined macros. */
- if (extensions != NULL) {
- if (extensions->OES_EGL_image_external)
- add_builtin_define(parser, "GL_OES_EGL_image_external", 1);
- }
-
if (api == API_OPENGLES2) {
- parser->is_gles = true;
- add_builtin_define(parser, "GL_ES", 1);
+ parser->is_gles = true;
+ add_builtin_define(parser, "GL_ES", 1);
+
+ if (extensions != NULL) {
+ if (extensions->OES_EGL_image_external)
+ add_builtin_define(parser, "GL_OES_EGL_image_external", 1);
+ }
} else {
add_builtin_define(parser, "GL_ARB_draw_buffers", 1);
add_builtin_define(parser, "GL_ARB_texture_rectangle", 1);
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 373e8f5..ce5b87b 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -654,7 +654,8 @@ _mesa_meta_begin(struct gl_context *ctx, GLbitfield state)
_mesa_set_enable(ctx, GL_TEXTURE_2D, GL_FALSE);
if (ctx->Extensions.ARB_texture_cube_map)
_mesa_set_enable(ctx, GL_TEXTURE_CUBE_MAP, GL_FALSE);
- if (ctx->Extensions.OES_EGL_image_external)
+ if (_mesa_is_gles(ctx) &&
+ ctx->Extensions.OES_EGL_image_external)
_mesa_set_enable(ctx, GL_TEXTURE_EXTERNAL_OES, GL_FALSE);
if (ctx->API == API_OPENGL_COMPAT) {
diff --git a/src/mesa/main/ff_fragment_shader.cpp
b/src/mesa/main/ff_fragment_shader.cpp
index 91c425b..d162da8 100644
--- a/src/mesa/main/ff_fragment_shader.cpp
+++ b/src/mesa/main/ff_fragment_shader.cpp
@@ -31,6 +31,7 @@ extern "C" {
#include "glheader.h"
#include "imports.h"
#include "mtypes.h"
+#include "main/context.h"
#include "main/uniforms.h"
#include "main/macros.h"
#include "main/samplerobj.h"
@@ -1309,7 +1310,7 @@ create_new_program(struct gl_context *ctx, struct
state_key *key)
state->language_version = 130;
state->es_shader = false;
- if (ctx->Extensions.OES_EGL_image_external)
+ if (_mesa_is_gles(ctx) && ctx->Extensions.OES_EGL_image_external)
state->OES_EGL_image_external_enable = true;
_mesa_glsl_initialize_types(state);
_mesa_glsl_initialize_variables(p.instructions, state);
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 9aaa63f..6f7fbc0 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -798,7 +798,7 @@ _mesa_select_tex_object(struct gl_context *ctx,
ctx->Extensions.ARB_texture_buffer_object ?
texUnit->CurrentTex[TEXTURE_BUFFER_INDEX] : NULL;
case GL_TEXTURE_EXTERNAL_OES:
- return ctx->Extensions.OES_EGL_image_external
+ return _mesa_is_gles(ctx) && ctx->Extensions.OES_EGL_image_external
? texUnit->CurrentTex[TEXTURE_EXTERNAL_INDEX] : NULL;
case GL_TEXTURE_2D_MULTISAMPLE:
return ctx->Extensions.ARB_texture_multisample
@@ -3243,7 +3243,8 @@ _mesa_EGLImageTargetTexture2DOES (GLenum target,
GLeglImageOES image)
valid_target = ctx->Extensions.OES_EGL_image;
break;
case GL_TEXTURE_EXTERNAL_OES:
- valid_target = ctx->Extensions.OES_EGL_image_external;
+ valid_target =
+ _mesa_is_gles(ctx) ? ctx->Extensions.OES_EGL_image_external : false;
break;
default:
valid_target = false;
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index ddae956..966722c 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -573,8 +573,7 @@ void st_init_extensions(struct st_context *st)
ctx->Extensions.NV_texture_rectangle = GL_TRUE;
ctx->Extensions.OES_EGL_image = GL_TRUE;
- if (ctx->API != API_OPENGL_COMPAT)
- ctx->Extensions.OES_EGL_image_external = GL_TRUE;
+ ctx->Extensions.OES_EGL_image_external = GL_TRUE;
ctx->Extensions.OES_draw_texture =
Mesa (master): gallium/util: make WRITES_ALL_CBUFS optional in the passthrough fragment shader
Module: Mesa
Branch: master
Commit: de1c38299ceb3160ed0c163d4dd8944ec6589a7f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=de1c38299ceb3160ed0c163d4dd8944ec6589a7f
Author: Marek Olšák
Date: Wed May 29 14:11:58 2013 +0200
gallium/util: make WRITES_ALL_CBUFS optional in the passthrough fragment shader
Reviewed-by: Brian Paul
---
src/gallium/auxiliary/hud/hud_context.c |3 ++-
src/gallium/auxiliary/util/u_simple_shaders.c |9 ++---
src/gallium/auxiliary/util/u_simple_shaders.h |3 ++-
src/gallium/state_trackers/vega/renderer.c|3 ++-
src/gallium/tests/trivial/tri.c |2 +-
src/mesa/state_tracker/st_atom_shader.c |3 ++-
src/mesa/state_tracker/st_cb_clear.c |3 ++-
7 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/src/gallium/auxiliary/hud/hud_context.c
b/src/gallium/auxiliary/hud/hud_context.c
index de032b6..cbd00a9 100644
--- a/src/gallium/auxiliary/hud/hud_context.c
+++ b/src/gallium/auxiliary/hud/hud_context.c
@@ -959,7 +959,8 @@ hud_create(struct pipe_context *pipe, struct cso_context
*cso)
hud->fs_color =
util_make_fragment_passthrough_shader(pipe,
TGSI_SEMANTIC_COLOR,
- TGSI_INTERPOLATE_CONSTANT);
+ TGSI_INTERPOLATE_CONSTANT,
+ TRUE);
{
/* Read a texture and do . swizzling. */
diff --git a/src/gallium/auxiliary/util/u_simple_shaders.c
b/src/gallium/auxiliary/util/u_simple_shaders.c
index c53c2d0..6ca073d 100644
--- a/src/gallium/auxiliary/util/u_simple_shaders.c
+++ b/src/gallium/auxiliary/util/u_simple_shaders.c
@@ -322,11 +322,12 @@ util_make_fragment_tex_shader_writestencil(struct
pipe_context *pipe,
void *
util_make_fragment_passthrough_shader(struct pipe_context *pipe,
int input_semantic,
- int input_interpolate)
+ int input_interpolate,
+ boolean write_all_cbufs)
{
static const char shader_templ[] =
"FRAG\n"
- "PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1\n"
+ "%s"
"DCL IN[0], %s[0], %s\n"
"DCL OUT[0], COLOR[0]\n"
@@ -337,7 +338,9 @@ util_make_fragment_passthrough_shader(struct pipe_context
*pipe,
struct tgsi_token tokens[1000];
struct pipe_shader_state state = {tokens};
- sprintf(text, shader_templ, tgsi_semantic_names[input_semantic],
+ sprintf(text, shader_templ,
+ write_all_cbufs ? "PROPERTY FS_COLOR0_WRITES_ALL_CBUFS 1\n" : "",
+ tgsi_semantic_names[input_semantic],
tgsi_interpolate_names[input_interpolate]);
if (!tgsi_text_translate(text, tokens, Elements(tokens))) {
diff --git a/src/gallium/auxiliary/util/u_simple_shaders.h
b/src/gallium/auxiliary/util/u_simple_shaders.h
index 22b9cee..06da249 100644
--- a/src/gallium/auxiliary/util/u_simple_shaders.h
+++ b/src/gallium/auxiliary/util/u_simple_shaders.h
@@ -89,7 +89,8 @@ util_make_fragment_tex_shader_writestencil(struct
pipe_context *pipe,
extern void *
util_make_fragment_passthrough_shader(struct pipe_context *pipe,
int input_semantic,
- int input_interpolate);
+ int input_interpolate,
+ boolean write_all_cbufs);
extern void *
diff --git a/src/gallium/state_trackers/vega/renderer.c
b/src/gallium/state_trackers/vega/renderer.c
index b823278..35795fc 100644
--- a/src/gallium/state_trackers/vega/renderer.c
+++ b/src/gallium/state_trackers/vega/renderer.c
@@ -309,7 +309,8 @@ static void renderer_set_fs(struct renderer *r, RendererFs
id)
switch (id) {
case RENDERER_FS_COLOR:
fs = util_make_fragment_passthrough_shader(r->pipe,
- TGSI_SEMANTIC_COLOR, TGSI_INTERPOLATE_PERSPECTIVE);
+ TGSI_SEMANTIC_COLOR, TGSI_INTERPOLATE_PERSPECTIVE,
+ TRUE);
break;
case RENDERER_FS_TEXTURE:
fs = util_make_fragment_tex_shader(r->pipe,
diff --git a/src/gallium/tests/trivial/tri.c b/src/gallium/tests/trivial/tri.c
index 9131bb5..f93c3f7 100644
--- a/src/gallium/tests/trivial/tri.c
+++ b/src/gallium/tests/trivial/tri.c
@@ -218,7 +218,7 @@ static void init_prog(struct program *p)
/* fragment shader */
p->fs = util_make_fragment_passthrough_shader(p->pipe,
-TGSI_SEMANTIC_COLOR, TGSI_INTERPOLATE_PERSPECTIVE);
+TGSI_SEMANTIC_COLOR, TGSI_INTERPOLATE_PERSPECTIVE, TRUE);
}
static void close_prog(struct program *p)
diff --git a/src/mesa/state_tracker/st_atom_shader.c
b/src/mesa/state_tracker/st_atom_shader.c
index c0239e9..e228997 100644
--- a/src/mesa/state_tracker
Mesa (master): gallium/u_blitter: make clearing independent of the number of bound colorbuffers
Module: Mesa
Branch: master
Commit: 17350ea979b883662573dac136cd9efb49938210
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=17350ea979b883662573dac136cd9efb49938210
Author: Marek Olšák
Date: Wed May 29 15:35:38 2013 +0200
gallium/u_blitter: make clearing independent of the number of bound colorbuffers
We can use the fragment shader TGSI property WRITES_ALL_CBUFS.
Reviewed-by: Brian Paul
---
src/gallium/auxiliary/util/u_blitter.c| 80 -
src/gallium/auxiliary/util/u_blitter.h|1 -
src/gallium/auxiliary/util/u_simple_shaders.c | 12
src/gallium/auxiliary/util/u_simple_shaders.h |4 +
src/gallium/drivers/r300/r300_blit.c |1 -
src/gallium/drivers/r600/r600_blit.c |2 +-
src/gallium/drivers/radeonsi/r600_blit.c |2 +-
7 files changed, 43 insertions(+), 59 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_blitter.c
b/src/gallium/auxiliary/util/u_blitter.c
index 8c871fd..4ce2bfb 100644
--- a/src/gallium/auxiliary/util/u_blitter.c
+++ b/src/gallium/auxiliary/util/u_blitter.c
@@ -67,9 +67,9 @@ struct blitter_context_priv
void *vs_pos_only; /**< Vertex shader which passes pos to the output.*/
/* Fragment shaders. */
- /* The shader at index i outputs color to color buffers 0,1,...,i-1. */
- void *fs_col[PIPE_MAX_COLOR_BUFS+1];
- void *fs_col_int[PIPE_MAX_COLOR_BUFS+1];
+ void *fs_empty;
+ void *fs_write_one_cbuf;
+ void *fs_write_all_cbufs;
/* FS which outputs a color from a texture,
where the index is PIPE_TEXTURE_* to be sampled. */
@@ -301,7 +301,16 @@ struct blitter_context *util_blitter_create(struct
pipe_context *pipe)
}
}
- /* fragment shaders are created on-demand */
+ /* Fragment shaders are created on-demand, except these.
+* The interpolation must be constant for integer texture clearing to work.
+*/
+ ctx->fs_empty = util_make_empty_fragment_shader(pipe);
+ ctx->fs_write_one_cbuf =
+ util_make_fragment_passthrough_shader(pipe, TGSI_SEMANTIC_GENERIC,
+TGSI_INTERPOLATE_CONSTANT, FALSE);
+ ctx->fs_write_all_cbufs =
+ util_make_fragment_passthrough_shader(pipe, TGSI_SEMANTIC_GENERIC,
+TGSI_INTERPOLATE_CONSTANT, TRUE);
/* vertex shaders */
{
@@ -379,13 +388,9 @@ void util_blitter_destroy(struct blitter_context *blitter)
if (ctx->fs_texfetch_stencil[i])
ctx->delete_fs_state(pipe, ctx->fs_texfetch_stencil[i]);
}
-
- for (i = 0; i <= PIPE_MAX_COLOR_BUFS; i++) {
- if (ctx->fs_col[i])
- ctx->delete_fs_state(pipe, ctx->fs_col[i]);
- if (ctx->fs_col_int[i])
- ctx->delete_fs_state(pipe, ctx->fs_col_int[i]);
- }
+ ctx->delete_fs_state(pipe, ctx->fs_empty);
+ ctx->delete_fs_state(pipe, ctx->fs_write_one_cbuf);
+ ctx->delete_fs_state(pipe, ctx->fs_write_all_cbufs);
pipe->delete_sampler_state(pipe, ctx->sampler_state_rect_linear);
pipe->delete_sampler_state(pipe, ctx->sampler_state_rect);
@@ -732,30 +737,6 @@ static void blitter_set_dst_dimensions(struct
blitter_context_priv *ctx,
ctx->dst_height = height;
}
-static void *blitter_get_fs_col(struct blitter_context_priv *ctx,
-unsigned num_cbufs, boolean int_format)
-{
- struct pipe_context *pipe = ctx->base.pipe;
-
- assert(num_cbufs <= PIPE_MAX_COLOR_BUFS);
-
- if (int_format) {
- if (!ctx->fs_col_int[num_cbufs])
- ctx->fs_col_int[num_cbufs] =
-util_make_fragment_cloneinput_shader(pipe, num_cbufs,
- TGSI_SEMANTIC_GENERIC,
- TGSI_INTERPOLATE_CONSTANT);
- return ctx->fs_col_int[num_cbufs];
- } else {
- if (!ctx->fs_col[num_cbufs])
- ctx->fs_col[num_cbufs] =
-util_make_fragment_cloneinput_shader(pipe, num_cbufs,
- TGSI_SEMANTIC_GENERIC,
- TGSI_INTERPOLATE_LINEAR);
- return ctx->fs_col[num_cbufs];
- }
-}
-
static void *blitter_get_fs_texfetch_col(struct blitter_context_priv *ctx,
enum pipe_texture_target target,
unsigned nr_samples)
@@ -910,22 +891,15 @@ void util_blitter_cache_all_shaders(struct
blitter_context *blitter)
{
struct blitter_context_priv *ctx = (struct blitter_context_priv*)blitter;
struct pipe_screen *screen = blitter->pipe->screen;
- unsigned num_cbufs, i, target, max_samples;
+ unsigned i, target, max_samples;
boolean has_arraytex, has_cubearraytex;
- num_cbufs = MAX2(screen->get_param(screen,
- PIPE_CAP_MAX_RENDER_TARGETS), 1);
max_samples = ctx->has_texture_multisample ? 2 : 1;
has_arraytex = screen->get_param(screen,
Mesa (master): gallium/u_blitter: make clearing independent of the colorbuffer format
Module: Mesa
Branch: master
Commit: d6d4a9a2e87d9ed2c5b3a6acee771ff55a903e47
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6d4a9a2e87d9ed2c5b3a6acee771ff55a903e47
Author: Marek Olšák
Date: Wed May 29 15:51:20 2013 +0200
gallium/u_blitter: make clearing independent of the colorbuffer format
There isn't any difference between 32_FLOAT and 32_*INT in vertex fetching.
Both of them don't do any format conversion.
Reviewed-by: Brian Paul
---
src/gallium/auxiliary/util/u_blitter.c | 46 ++---
src/gallium/auxiliary/util/u_blitter.h |1 -
src/gallium/drivers/r300/r300_blit.c |3 +-
src/gallium/drivers/r600/r600_blit.c |3 +-
src/gallium/drivers/radeonsi/r600_blit.c |3 +-
5 files changed, 7 insertions(+), 49 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_blitter.c
b/src/gallium/auxiliary/util/u_blitter.c
index 4ce2bfb..e9ac170 100644
--- a/src/gallium/auxiliary/util/u_blitter.c
+++ b/src/gallium/auxiliary/util/u_blitter.c
@@ -98,8 +98,6 @@ struct blitter_context_priv
/* Vertex elements states. */
void *velem_state;
- void *velem_uint_state;
- void *velem_sint_state;
void *velem_state_readbuf[4]; /**< X, XY, XYZ, XYZW */
/* Sampler state. */
@@ -119,7 +117,6 @@ struct blitter_context_priv
unsigned dst_height;
boolean has_geometry_shader;
- boolean vertex_has_integers;
boolean has_stream_out;
boolean has_stencil_export;
boolean has_texture_multisample;
@@ -171,9 +168,6 @@ struct blitter_context *util_blitter_create(struct
pipe_context *pipe)
ctx->has_geometry_shader =
pipe->screen->get_shader_param(pipe->screen, PIPE_SHADER_GEOMETRY,
PIPE_SHADER_CAP_MAX_INSTRUCTIONS) > 0;
- ctx->vertex_has_integers =
- pipe->screen->get_shader_param(pipe->screen, PIPE_SHADER_VERTEX,
- PIPE_SHADER_CAP_INTEGERS);
ctx->has_stream_out =
pipe->screen->get_param(pipe->screen,
PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS) != 0;
@@ -265,26 +259,6 @@ struct blitter_context *util_blitter_create(struct
pipe_context *pipe)
}
ctx->velem_state = pipe->create_vertex_elements_state(pipe, 2, &velem[0]);
- if (ctx->vertex_has_integers) {
- memset(&velem[0], 0, sizeof(velem[0]) * 2);
- velem[0].src_offset = 0;
- velem[0].src_format = PIPE_FORMAT_R32G32B32A32_FLOAT;
- velem[0].vertex_buffer_index = ctx->base.vb_slot;
- velem[1].src_offset = 4 * sizeof(float);
- velem[1].src_format = PIPE_FORMAT_R32G32B32A32_SINT;
- velem[1].vertex_buffer_index = ctx->base.vb_slot;
- ctx->velem_sint_state = pipe->create_vertex_elements_state(pipe, 2,
&velem[0]);
-
- memset(&velem[0], 0, sizeof(velem[0]) * 2);
- velem[0].src_offset = 0;
- velem[0].src_format = PIPE_FORMAT_R32G32B32A32_FLOAT;
- velem[0].vertex_buffer_index = ctx->base.vb_slot;
- velem[1].src_offset = 4 * sizeof(float);
- velem[1].src_format = PIPE_FORMAT_R32G32B32A32_UINT;
- velem[1].vertex_buffer_index = ctx->base.vb_slot;
- ctx->velem_uint_state = pipe->create_vertex_elements_state(pipe, 2,
&velem[0]);
- }
-
if (ctx->has_stream_out) {
static enum pipe_format formats[4] = {
PIPE_FORMAT_R32_UINT,
@@ -368,10 +342,6 @@ void util_blitter_destroy(struct blitter_context *blitter)
if (ctx->vs_pos_only)
pipe->delete_vs_state(pipe, ctx->vs_pos_only);
pipe->delete_vertex_elements_state(pipe, ctx->velem_state);
- if (ctx->vertex_has_integers) {
- pipe->delete_vertex_elements_state(pipe, ctx->velem_sint_state);
- pipe->delete_vertex_elements_state(pipe, ctx->velem_uint_state);
- }
for (i = 0; i < 4; i++) {
if (ctx->velem_state_readbuf[i]) {
pipe->delete_vertex_elements_state(pipe, ctx->velem_state_readbuf[i]);
@@ -982,7 +952,6 @@ void util_blitter_draw_rectangle(struct blitter_context
*blitter,
static void util_blitter_clear_custom(struct blitter_context *blitter,
unsigned width, unsigned height,
unsigned clear_buffers,
- enum pipe_format cbuf_format,
const union pipe_color_union *color,
double depth, unsigned stencil,
void *custom_blend, void *custom_dsa)
@@ -1020,13 +989,7 @@ static void util_blitter_clear_custom(struct
blitter_context *blitter,
sr.ref_value[0] = stencil & 0xff;
pipe->set_stencil_ref(pipe, &sr);
- if (util_format_is_pure_sint(cbuf_format)) {
- pipe->bind_vertex_elements_state(pipe, ctx->velem_sint_state);
- } else if (util_format_is_pure_uint(cbuf_format)) {
- pipe->bind_vertex_elements_state(pipe, ctx->velem_uint_state);
- } else {
- pipe->bind_vertex_elements_state(pipe, ctx->velem_state);
- }
+ pipe->bind_vert
Mesa (master): r600g: upsample and downsample MSAA resources for transfers
Module: Mesa
Branch: master
Commit: 4d59258856a3601fb7fbb4c4d80f64491f0cb5c7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4d59258856a3601fb7fbb4c4d80f64491f0cb5c7
Author: Marek Olšák
Date: Wed May 29 20:12:27 2013 +0200
r600g: upsample and downsample MSAA resources for transfers
We did downsample (=resolve) MSAA resources to make ReadPixels work with MSAA
GLX visuals, which was enough for read-only color-only transfers.
This commit makes write color transfers and depth-stencil transfers work
in a similar manner. It does downsampling in transfer_map and upsampling
in transfer_unmap.
Reviewed-by: Brian Paul
---
src/gallium/drivers/r600/r600_texture.c | 220 ---
1 files changed, 141 insertions(+), 79 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_texture.c
b/src/gallium/drivers/r600/r600_texture.c
index 19afd65..60d8c36 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -33,6 +33,40 @@
#include "util/u_memory.h"
+/* Same as resource_copy_region, except that both upsampling and downsampling
are allowed. */
+static void r600_copy_region_with_blit(struct pipe_context *pipe,
+ struct pipe_resource *dst,
+ unsigned dst_level,
+ unsigned dstx, unsigned dsty, unsigned
dstz,
+ struct pipe_resource *src,
+ unsigned src_level,
+ const struct pipe_box *src_box)
+{
+ struct pipe_blit_info blit;
+
+ memset(&blit, 0, sizeof(blit));
+ blit.src.resource = src;
+ blit.src.format = src->format;
+ blit.src.level = src_level;
+ blit.src.box = *src_box;
+ blit.dst.resource = dst;
+ blit.dst.format = dst->format;
+ blit.dst.level = dst_level;
+ blit.dst.box.x = dstx;
+ blit.dst.box.y = dsty;
+ blit.dst.box.z = dstz;
+ blit.dst.box.width = src_box->width;
+ blit.dst.box.height = src_box->height;
+ blit.dst.box.depth = src_box->depth;
+ blit.mask = util_format_get_mask(src->format) &
+ util_format_get_mask(dst->format);
+ blit.filter = PIPE_TEX_FILTER_NEAREST;
+
+ if (blit.mask) {
+ pipe->blit(pipe, &blit);
+ }
+}
+
/* Copy from a full GPU texture to a transfer's staging one. */
static void r600_copy_to_staging_texture(struct pipe_context *ctx, struct
r600_transfer *rtransfer)
{
@@ -41,32 +75,17 @@ static void r600_copy_to_staging_texture(struct
pipe_context *ctx, struct r600_t
struct pipe_resource *dst = &rtransfer->staging->b.b;
struct pipe_resource *src = transfer->resource;
- if (src->nr_samples <= 1) {
- if (!rctx->screen->dma_blit(ctx, dst, 0, 0, 0, 0,
- src, transfer->level,
- &transfer->box)) {
- /* async dma could not be use */
- ctx->resource_copy_region(ctx, dst, 0, 0, 0, 0,
- src, transfer->level,
&transfer->box);
- }
- } else {
- /* Resolve the resource. */
- struct pipe_blit_info blit;
-
- memset(&blit, 0, sizeof(blit));
- blit.src.resource = src;
- blit.src.format = src->format;
- blit.src.level = transfer->level;
- blit.src.box = transfer->box;
- blit.dst.resource = dst;
- blit.dst.format = dst->format;
- blit.dst.box.width = transfer->box.width;
- blit.dst.box.height = transfer->box.height;
- blit.dst.box.depth = transfer->box.depth;
- blit.mask = PIPE_MASK_RGBA;
- blit.filter = PIPE_TEX_FILTER_NEAREST;
-
- ctx->blit(ctx, &blit);
+ if (src->nr_samples > 1) {
+ r600_copy_region_with_blit(ctx, dst, 0, 0, 0, 0,
+ src, transfer->level,
&transfer->box);
+ return;
+ }
+
+ if (!rctx->screen->dma_blit(ctx, dst, 0, 0, 0, 0,
+ src, transfer->level,
+ &transfer->box)) {
+ ctx->resource_copy_region(ctx, dst, 0, 0, 0, 0,
+ src, transfer->level, &transfer->box);
}
}
@@ -75,19 +94,25 @@ static void r600_copy_from_staging_texture(struct
pipe_context *ctx, struct r600
{
struct r600_context *rctx = (struct r600_context*)ctx;
struct pipe_transfer *transfer = (struct pipe_transfer*)rtransfer;
- struct pipe_resource *texture = transfer->resource;
+ struct pipe_resource *dst = transfer->resource;
+ struct pipe_resource *src = &rtransfer->staging->b.b;
Mesa (master): gallium/u_format: add a new helper for initializing pipe_blit_info::mask
Module: Mesa
Branch: master
Commit: 72a086b8b2a58044be1a66dc09d9cb8b0d3da719
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=72a086b8b2a58044be1a66dc09d9cb8b0d3da719
Author: Marek Olšák
Date: Wed May 29 19:26:56 2013 +0200
gallium/u_format: add a new helper for initializing pipe_blit_info::mask
Reviewed-by: Brian Paul
---
src/gallium/auxiliary/util/u_format.h | 28
src/gallium/auxiliary/util/u_surface.c | 26 +-
2 files changed, 29 insertions(+), 25 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_format.h
b/src/gallium/auxiliary/util/u_format.h
index e4b9c36..4cace6a 100644
--- a/src/gallium/auxiliary/util/u_format.h
+++ b/src/gallium/auxiliary/util/u_format.h
@@ -31,6 +31,7 @@
#include "pipe/p_format.h"
+#include "pipe/p_defines.h"
#include "util/u_debug.h"
union pipe_color_union;
@@ -520,6 +521,33 @@ util_format_is_depth_and_stencil(enum pipe_format format)
util_format_has_stencil(desc);
}
+/**
+ * Return whether this is an RGBA, Z, S, or combined ZS format.
+ * Useful for initializing pipe_blit_info::mask.
+ */
+static INLINE unsigned
+util_format_get_mask(enum pipe_format format)
+{
+ const struct util_format_description *desc =
+ util_format_description(format);
+
+ if (!desc)
+ return 0;
+
+ if (util_format_has_depth(desc)) {
+ if (util_format_has_stencil(desc)) {
+ return PIPE_MASK_ZS;
+ } else {
+ return PIPE_MASK_Z;
+ }
+ } else {
+ if (util_format_has_stencil(desc)) {
+ return PIPE_MASK_S;
+ } else {
+ return PIPE_MASK_RGBA;
+ }
+ }
+}
/**
* Give the RGBA colormask of the channels that can be represented in this
diff --git a/src/gallium/auxiliary/util/u_surface.c
b/src/gallium/auxiliary/util/u_surface.c
index 17591f1..07997d2 100644
--- a/src/gallium/auxiliary/util/u_surface.c
+++ b/src/gallium/auxiliary/util/u_surface.c
@@ -548,30 +548,6 @@ util_clear_depth_stencil(struct pipe_context *pipe,
}
-/* Return whether this is an RGBA, Z, S, or combined ZS format.
- */
-static unsigned
-get_format_mask(enum pipe_format format)
-{
- const struct util_format_description *desc =
util_format_description(format);
-
- assert(desc);
-
- if (util_format_has_depth(desc)) {
- if (util_format_has_stencil(desc)) {
- return PIPE_MASK_ZS;
- } else {
- return PIPE_MASK_Z;
- }
- } else {
- if (util_format_has_stencil(desc)) {
- return PIPE_MASK_S;
- } else {
- return PIPE_MASK_RGBA;
- }
- }
-}
-
/* Return if the box is totally inside the resource.
*/
static boolean
@@ -654,7 +630,7 @@ boolean
util_try_blit_via_copy_region(struct pipe_context *ctx,
const struct pipe_blit_info *blit)
{
- unsigned mask = get_format_mask(blit->dst.format);
+ unsigned mask = util_format_get_mask(blit->dst.format);
/* No format conversions. */
if (blit->src.resource->format != blit->src.format ||
___
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mesa-commit@lists.freedesktop.org
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Mesa (master): st/mesa: rework blit_copy_pixels to use pipe->blit
Module: Mesa
Branch: master
Commit: 79e421260a2caf18cd5f11514b3439d9846c743e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=79e421260a2caf18cd5f11514b3439d9846c743e
Author: Marek Olšák
Date: Thu May 30 21:34:06 2013 +0200
st/mesa: rework blit_copy_pixels to use pipe->blit
There were 2 issues with it:
- resource_copy_region doesn't allow different sample counts of both src
and dst, which can occur if we blit between a window and a FBO, and
the window has an MSAA colorbuffer and the FBO doesn't.
(this was the main motivation for using pipe->blit)
- blitting from or to a non-zero layer/slice/face was broken, because
rtt_face and rtt_slice were ignored.
blit_copy_pixels is now used even if the formats and orientation of
framebuffers don't match.
Reviewed-by: Brian Paul
---
src/mesa/state_tracker/st_cb_drawpixels.c | 114 -
1 files changed, 79 insertions(+), 35 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c
b/src/mesa/state_tracker/st_cb_drawpixels.c
index 68359e8..16ff307 100644
--- a/src/mesa/state_tracker/st_cb_drawpixels.c
+++ b/src/mesa/state_tracker/st_cb_drawpixels.c
@@ -1308,29 +1308,38 @@ st_get_color_read_renderbuffer(struct gl_context *ctx)
}
-/** Do the src/dest regions overlap? */
-static GLboolean
-regions_overlap(GLint srcX, GLint srcY, GLint dstX, GLint dstY,
-GLsizei width, GLsizei height)
+/**
+ * \return TRUE if two regions overlap, FALSE otherwise
+ */
+static boolean
+regions_overlap(int srcX0, int srcY0,
+int srcX1, int srcY1,
+int dstX0, int dstY0,
+int dstX1, int dstY1)
{
- if (srcX + width <= dstX ||
- dstX + width <= srcX ||
- srcY + height <= dstY ||
- dstY + height <= srcY)
- return GL_FALSE;
- else
- return GL_TRUE;
+ if (MAX2(srcX0, srcX1) < MIN2(dstX0, dstX1))
+ return FALSE; /* src completely left of dst */
+
+ if (MAX2(dstX0, dstX1) < MIN2(srcX0, srcX1))
+ return FALSE; /* dst completely left of src */
+
+ if (MAX2(srcY0, srcY1) < MIN2(dstY0, dstY1))
+ return FALSE; /* src completely above dst */
+
+ if (MAX2(dstY0, dstY1) < MIN2(srcY0, srcY1))
+ return FALSE; /* dst completely above src */
+
+ return TRUE; /* some overlap */
}
/**
* Try to do a glCopyPixels for simple cases with a blit by calling
- * pipe->resource_copy_region().
+ * pipe->blit().
*
* We can do this when we're copying color pixels (depth/stencil
* eventually) with no pixel zoom, no pixel transfer ops, no
- * per-fragment ops, the src/dest regions don't overlap and the
- * src/dest pixel formats are the same.
+ * per-fragment ops, and the src/dest regions don't overlap.
*/
static GLboolean
blit_copy_pixels(struct gl_context *ctx, GLint srcx, GLint srcy,
@@ -1339,8 +1348,9 @@ blit_copy_pixels(struct gl_context *ctx, GLint srcx,
GLint srcy,
{
struct st_context *st = st_context(ctx);
struct pipe_context *pipe = st->pipe;
+ struct pipe_screen *screen = pipe->screen;
struct gl_pixelstore_attrib pack, unpack;
- GLint readX, readY, readW, readH;
+ GLint readX, readY, readW, readH, drawX, drawY, drawW, drawH;
if (type == GL_COLOR &&
ctx->Pixel.ZoomX == 1.0 &&
@@ -1354,11 +1364,9 @@ blit_copy_pixels(struct gl_context *ctx, GLint srcx,
GLint srcy,
!ctx->FragmentProgram.Enabled &&
!ctx->VertexProgram.Enabled &&
!ctx->Shader.CurrentFragmentProgram &&
- st_fb_orientation(ctx->ReadBuffer) ==
st_fb_orientation(ctx->DrawBuffer) &&
ctx->DrawBuffer->_NumColorDrawBuffers == 1 &&
!ctx->Query.CondRenderQuery) {
struct st_renderbuffer *rbRead, *rbDraw;
- GLint drawX, drawY;
/*
* Clip the read region against the src buffer bounds.
@@ -1385,29 +1393,65 @@ blit_copy_pixels(struct gl_context *ctx, GLint srcx,
GLint srcy,
readX = readX - pack.SkipPixels + unpack.SkipPixels;
readY = readY - pack.SkipRows + unpack.SkipRows;
+ drawW = readW;
+ drawH = readH;
+
rbRead = st_get_color_read_renderbuffer(ctx);
rbDraw = st_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[0]);
- if ((rbRead != rbDraw ||
- !regions_overlap(readX, readY, drawX, drawY, readW, readH)) &&
- rbRead->Base.Format == rbDraw->Base.Format) {
- struct pipe_box srcBox;
-
- /* flip src/dst position if needed */
- if (st_fb_orientation(ctx->ReadBuffer) == Y_0_TOP) {
-/* both buffers will have the same orientation */
-readY = ctx->ReadBuffer->Height - readY - readH;
-drawY = ctx->DrawBuffer->Height - drawY - readH;
- }
+ /* Flip src/dst position depending on the orientation of buffers. */
+ if (st_fb_orientation(ctx->ReadBuffer) == Y_0_TOP) {
+ readY = rbRead->Base.Height - readY;
+ readH = -readH;
+ }
- u_box_2d(readX, readY, readW, readH, &srcBox);
+ if (st_fb_orie
Mesa (master): st/mesa: make generic CopyPixels path work with MSAA visuals
Module: Mesa
Branch: master
Commit: 526ebfa278554f167ba02377a3da672551d58b25
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=526ebfa278554f167ba02377a3da672551d58b25
Author: Marek Olšák
Date: Fri May 31 20:26:39 2013 +0200
st/mesa: make generic CopyPixels path work with MSAA visuals
We have to use pipe->blit, not resource_copy_region, so that the read buffer
is resolved if it's multisampled. I also removed the CPU-based copying,
which just did format conversion (obsoleted by the blit).
Also, the layer/slice/face of the read buffer is taken into account (this was
ignored).
Last but not least, the format choosing is improved to take float and integer
read buffers into account.
Reviewed-by: Brian Paul
---
src/mesa/state_tracker/st_cb_drawpixels.c | 162 +
1 files changed, 70 insertions(+), 92 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c
b/src/mesa/state_tracker/st_cb_drawpixels.c
index eb75500..1c26315 100644
--- a/src/mesa/state_tracker/st_cb_drawpixels.c
+++ b/src/mesa/state_tracker/st_cb_drawpixels.c
@@ -1474,10 +1474,9 @@ st_CopyPixels(struct gl_context *ctx, GLint srcx, GLint
srcy,
struct pipe_sampler_view *sv[2];
int num_sampler_view = 1;
GLfloat *color;
- enum pipe_format srcFormat, texFormat;
+ enum pipe_format srcFormat;
GLboolean invertTex = GL_FALSE;
GLint readX, readY, readW, readH;
- GLuint sample_count;
struct gl_pixelstore_attrib pack = ctx->DefaultPacking;
struct st_fp_variant *fpv;
@@ -1539,35 +1538,51 @@ st_CopyPixels(struct gl_context *ctx, GLint srcx, GLint
srcy,
/* update fragment program constants */
st_upload_constants(st, fpv->parameters, PIPE_SHADER_FRAGMENT);
- sample_count = rbRead->texture->nr_samples;
- /* I believe this would be legal, presumably would need to do a resolve
- for color, and for depth/stencil spec says to just use one of the
- depth/stencil samples per pixel? Need some transfer clarifications. */
- assert(sample_count < 2);
-
+ /* Choose the format for the temporary texture. */
srcFormat = rbRead->texture->format;
- if (screen->is_format_supported(screen, srcFormat, st->internal_target,
- sample_count,
- PIPE_BIND_SAMPLER_VIEW)) {
- texFormat = srcFormat;
- }
- else {
- /* srcFormat can't be used as a texture format */
+ if (!screen->is_format_supported(screen, srcFormat, st->internal_target, 0,
+PIPE_BIND_SAMPLER_VIEW |
+(type == GL_COLOR ? PIPE_BIND_RENDER_TARGET
+ : PIPE_BIND_DEPTH_STENCIL))) {
if (type == GL_DEPTH) {
- texFormat = st_choose_format(st, GL_DEPTH_COMPONENT,
- GL_NONE, GL_NONE, st->internal_target,
- sample_count, PIPE_BIND_DEPTH_STENCIL,
- FALSE);
- assert(texFormat != PIPE_FORMAT_NONE);
+ srcFormat = st_choose_format(st, GL_DEPTH_COMPONENT, GL_NONE,
+ GL_NONE, st->internal_target, 0,
+ PIPE_BIND_SAMPLER_VIEW |
+ PIPE_BIND_DEPTH_STENCIL, FALSE);
}
else {
- /* default color format */
- texFormat = st_choose_format(st, GL_RGBA,
- GL_NONE, GL_NONE, st->internal_target,
- sample_count, PIPE_BIND_SAMPLER_VIEW,
- FALSE);
- assert(texFormat != PIPE_FORMAT_NONE);
+ assert(type == GL_COLOR);
+
+ if (util_format_is_float(srcFormat)) {
+srcFormat = st_choose_format(st, GL_RGBA32F, GL_NONE,
+ GL_NONE, st->internal_target, 0,
+ PIPE_BIND_SAMPLER_VIEW |
+ PIPE_BIND_RENDER_TARGET, FALSE);
+ }
+ else if (util_format_is_pure_sint(srcFormat)) {
+srcFormat = st_choose_format(st, GL_RGBA32I, GL_NONE,
+ GL_NONE, st->internal_target, 0,
+ PIPE_BIND_SAMPLER_VIEW |
+ PIPE_BIND_RENDER_TARGET, FALSE);
+ }
+ else if (util_format_is_pure_uint(srcFormat)) {
+srcFormat = st_choose_format(st, GL_RGBA32UI, GL_NONE,
+ GL_NONE, st->internal_target, 0,
+ PIPE_BIND_SAMPLER_VIEW |
+ PIPE_BIND_RENDER_TARGET, FALSE);
+ }
+ else {
+srcFormat = st_choose_format(st, GL_RGBA, GL_NONE,
+ GL_NONE, st->internal_target, 0,
+
Mesa (master): st/mesa: don' t use blit_copy_pixels if an occlusion query is active
Module: Mesa
Branch: master
Commit: 9ef44e6eb791192894cbaa6fd302b2d4fc9c2571
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ef44e6eb791192894cbaa6fd302b2d4fc9c2571
Author: Marek Olšák
Date: Fri May 31 15:13:46 2013 +0200
st/mesa: don't use blit_copy_pixels if an occlusion query is active
CopyPixels, just as DrawPixels, should count the samples that passed
depth test.
Reviewed-by: Brian Paul
---
src/mesa/state_tracker/st_cb_drawpixels.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c
b/src/mesa/state_tracker/st_cb_drawpixels.c
index 16ff307..eb75500 100644
--- a/src/mesa/state_tracker/st_cb_drawpixels.c
+++ b/src/mesa/state_tracker/st_cb_drawpixels.c
@@ -1365,7 +1365,8 @@ blit_copy_pixels(struct gl_context *ctx, GLint srcx,
GLint srcy,
!ctx->VertexProgram.Enabled &&
!ctx->Shader.CurrentFragmentProgram &&
ctx->DrawBuffer->_NumColorDrawBuffers == 1 &&
- !ctx->Query.CondRenderQuery) {
+ !ctx->Query.CondRenderQuery &&
+ !ctx->Query.CurrentOcclusionObject) {
struct st_renderbuffer *rbRead, *rbDraw;
/*
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Mesa (master): st/dri: manually swap MSAA front and back buffers in SwapBuffers
Module: Mesa
Branch: master
Commit: 3b525036b94f041ebae192b9737b93c8c264befa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b525036b94f041ebae192b9737b93c8c264befa
Author: Marek Olšák
Date: Fri May 31 22:48:48 2013 +0200
st/dri: manually swap MSAA front and back buffers in SwapBuffers
Reviewed-by: Brian Paul
---
.../state_trackers/dri/common/dri_drawable.c | 25
1 files changed, 25 insertions(+), 0 deletions(-)
diff --git a/src/gallium/state_trackers/dri/common/dri_drawable.c
b/src/gallium/state_trackers/dri/common/dri_drawable.c
index ff04d57..1c2bad4 100644
--- a/src/gallium/state_trackers/dri/common/dri_drawable.c
+++ b/src/gallium/state_trackers/dri/common/dri_drawable.c
@@ -414,6 +414,7 @@ dri_flush(__DRIcontext *cPriv,
struct dri_context *ctx = dri_context(cPriv);
struct dri_drawable *drawable = dri_drawable(dPriv);
unsigned flush_flags;
+ boolean swap_msaa_buffers = FALSE;
if (!ctx) {
assert(0);
@@ -440,6 +441,12 @@ dri_flush(__DRIcontext *cPriv,
drawable->textures[ST_ATTACHMENT_BACK_LEFT],
drawable->msaa_textures[ST_ATTACHMENT_BACK_LEFT]);
+ if (reason == __DRI2_THROTTLE_SWAPBUFFER &&
+ drawable->msaa_textures[ST_ATTACHMENT_FRONT_LEFT] &&
+ drawable->msaa_textures[ST_ATTACHMENT_BACK_LEFT]) {
+swap_msaa_buffers = TRUE;
+ }
+
/* FRONT_LEFT is resolved in drawable->flush_frontbuffer. */
}
@@ -494,6 +501,24 @@ dri_flush(__DRIcontext *cPriv,
if (drawable) {
drawable->flushing = FALSE;
}
+
+ /* Swap the MSAA front and back buffers, so that reading
+* from the front buffer after SwapBuffers returns what was
+* in the back buffer.
+*/
+ if (swap_msaa_buffers) {
+ struct pipe_resource *tmp =
+ drawable->msaa_textures[ST_ATTACHMENT_FRONT_LEFT];
+
+ drawable->msaa_textures[ST_ATTACHMENT_FRONT_LEFT] =
+ drawable->msaa_textures[ST_ATTACHMENT_BACK_LEFT];
+ drawable->msaa_textures[ST_ATTACHMENT_BACK_LEFT] = tmp;
+
+ /* Now that we have swapped the buffers, this tells the state
+ * tracker to revalidate the framebuffer.
+ */
+ p_atomic_inc(&drawable->base.stamp);
+ }
}
/**
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Mesa (master): st/dri: fix MSAA resolving of buffers with height > width
Module: Mesa Branch: master Commit: 683b065320dc6e15383be931648c6e7cbe175b40 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=683b065320dc6e15383be931648c6e7cbe175b40 Author: Marek Olšák Date: Wed May 29 23:08:11 2013 +0200 st/dri: fix MSAA resolving of buffers with height > width Reviewed-by: Brian Paul --- .../state_trackers/dri/common/dri_drawable.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/state_trackers/dri/common/dri_drawable.c b/src/gallium/state_trackers/dri/common/dri_drawable.c index cd4a36a..f784ee6 100644 --- a/src/gallium/state_trackers/dri/common/dri_drawable.c +++ b/src/gallium/state_trackers/dri/common/dri_drawable.c @@ -374,12 +374,12 @@ dri_msaa_resolve(struct dri_context *ctx, memset(&blit, 0, sizeof(blit)); blit.dst.resource = dst; blit.dst.box.width = dst->width0; - blit.dst.box.height = dst->width0; + blit.dst.box.height = dst->height0; blit.dst.box.depth = 1; blit.dst.format = util_format_linear(dst->format); blit.src.resource = src; blit.src.box.width = src->width0; - blit.src.box.height = src->width0; + blit.src.box.height = src->height0; blit.src.box.depth = 1; blit.src.format = util_format_linear(src->format); blit.mask = PIPE_MASK_RGBA; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): st/dri: reuse depth-stencil and MSAA resources after DRI2 invalidate event
Module: Mesa
Branch: master
Commit: 6c6cfc02c90663973e1a07f0596d1550bd35a38c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6c6cfc02c90663973e1a07f0596d1550bd35a38c
Author: Marek Olšák
Date: Sat Jun 1 02:04:56 2013 +0200
st/dri: reuse depth-stencil and MSAA resources after DRI2 invalidate event
Page flipping generates an invalidate event every frame, causing reallocations
of all private resources (MSAA and depth-stencil).
Reusing the resources may improve performance (especially under memory
pressure).
Reviewed-by: Brian Paul
---
src/gallium/state_trackers/dri/drm/dri2.c | 104 +---
1 files changed, 78 insertions(+), 26 deletions(-)
diff --git a/src/gallium/state_trackers/dri/drm/dri2.c
b/src/gallium/state_trackers/dri/drm/dri2.c
index 1839b16..4117a9f 100644
--- a/src/gallium/state_trackers/dri/drm/dri2.c
+++ b/src/gallium/state_trackers/dri/drm/dri2.c
@@ -179,7 +179,7 @@ dri2_drawable_process_buffers(struct dri_drawable *drawable,
struct pipe_resource templ;
struct winsys_handle whandle;
boolean alloc_depthstencil = FALSE;
- unsigned i, bind;
+ unsigned i, j, bind;
if (drawable->old_num == buffer_count &&
drawable->old_w == dri_drawable->w &&
@@ -187,10 +187,41 @@ dri2_drawable_process_buffers(struct dri_drawable
*drawable,
memcmp(drawable->old, buffers, sizeof(__DRIbuffer) * buffer_count) == 0)
return;
- for (i = 0; i < ST_ATTACHMENT_COUNT; i++)
+ /* See if we need a depth-stencil buffer. */
+ for (i = 0; i < att_count; i++) {
+ if (atts[i] == ST_ATTACHMENT_DEPTH_STENCIL) {
+ alloc_depthstencil = TRUE;
+ break;
+ }
+ }
+
+ /* Delete the resources we won't need. */
+ for (i = 0; i < ST_ATTACHMENT_COUNT; i++) {
+ /* Don't delete the depth-stencil buffer, we can reuse it. */
+ if (i == ST_ATTACHMENT_DEPTH_STENCIL && alloc_depthstencil)
+ continue;
+
pipe_resource_reference(&drawable->textures[i], NULL);
- for (i = 0; i < ST_ATTACHMENT_COUNT; i++)
- pipe_resource_reference(&drawable->msaa_textures[i], NULL);
+ }
+
+ if (drawable->stvis.samples > 1) {
+ for (i = 0; i < ST_ATTACHMENT_COUNT; i++) {
+ boolean del = TRUE;
+
+ /* Don't delete MSAA resources for the attachments which are enabled,
+ * we can reuse them. */
+ for (j = 0; j < att_count; j++) {
+if (i == atts[j]) {
+ del = FALSE;
+ break;
+}
+ }
+
+ if (del) {
+pipe_resource_reference(&drawable->msaa_textures[i], NULL);
+ }
+ }
+ }
memset(&templ, 0, sizeof(templ));
templ.target = screen->target;
@@ -244,53 +275,74 @@ dri2_drawable_process_buffers(struct dri_drawable
*drawable,
for (i = 0; i < att_count; i++) {
enum st_attachment_type att = atts[i];
+ if (att == ST_ATTACHMENT_DEPTH_STENCIL)
+continue;
+
if (drawable->textures[att]) {
templ.format = drawable->textures[att]->format;
templ.bind = drawable->textures[att]->bind;
templ.nr_samples = drawable->stvis.samples;
-drawable->msaa_textures[att] =
- screen->base.screen->resource_create(screen->base.screen,
-&templ);
-assert(drawable->msaa_textures[att]);
+/* Try to reuse the resource.
+ * (the other resource parameters should be constant)
+ */
+if (!drawable->msaa_textures[att] ||
+drawable->msaa_textures[att]->width0 != templ.width0 ||
+drawable->msaa_textures[att]->height0 != templ.height0) {
+ /* Allocate a new one. */
+ pipe_resource_reference(&drawable->msaa_textures[att], NULL);
+
+ drawable->msaa_textures[att] =
+ screen->base.screen->resource_create(screen->base.screen,
+ &templ);
+ assert(drawable->msaa_textures[att]);
+}
+ }
+ else {
+pipe_resource_reference(&drawable->msaa_textures[att], NULL);
}
- }
- }
-
- /* See if we need a depth-stencil buffer. */
- for (i = 0; i < att_count; i++) {
- if (atts[i] == ST_ATTACHMENT_DEPTH_STENCIL) {
- alloc_depthstencil = TRUE;
- break;
}
}
/* Allocate a private depth-stencil buffer. */
if (alloc_depthstencil) {
+ enum st_attachment_type att = ST_ATTACHMENT_DEPTH_STENCIL;
+ struct pipe_resource **zsbuf;
enum pipe_format format;
unsigned bind;
- dri_drawable_get_format(drawable, ST_ATTACHMENT_DEPTH_STENCIL,
- &format, &bind);
+ dri_drawable_get_format(drawable, att, &format, &bind);
+
if (format) {
templ.format = format;
templ.bind = bind;
if (drawable->stvis.sam
Mesa (master): st/dri: refactor dri_msaa_resolve
Module: Mesa
Branch: master
Commit: fdf9d234e2aa46f865a59ec15b2d4167bebbc35b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fdf9d234e2aa46f865a59ec15b2d4167bebbc35b
Author: Marek Olšák
Date: Fri May 31 21:43:50 2013 +0200
st/dri: refactor dri_msaa_resolve
The generic blit will be used by the following commit.
Reviewed-by: Brian Paul
---
.../state_trackers/dri/common/dri_drawable.c | 16
.../state_trackers/dri/common/dri_drawable.h |6 +++---
src/gallium/state_trackers/dri/drm/dri2.c |5 -
3 files changed, 15 insertions(+), 12 deletions(-)
diff --git a/src/gallium/state_trackers/dri/common/dri_drawable.c
b/src/gallium/state_trackers/dri/common/dri_drawable.c
index f784ee6..ff04d57 100644
--- a/src/gallium/state_trackers/dri/common/dri_drawable.c
+++ b/src/gallium/state_trackers/dri/common/dri_drawable.c
@@ -359,13 +359,10 @@ swap_fences_unref(struct dri_drawable *draw)
}
void
-dri_msaa_resolve(struct dri_context *ctx,
- struct dri_drawable *drawable,
- enum st_attachment_type att)
+dri_pipe_blit(struct pipe_context *pipe,
+ struct pipe_resource *dst,
+ struct pipe_resource *src)
{
- struct pipe_context *pipe = ctx->st->pipe;
- struct pipe_resource *dst = drawable->textures[att];
- struct pipe_resource *src = drawable->msaa_textures[att];
struct pipe_blit_info blit;
if (!dst || !src)
@@ -437,9 +434,12 @@ dri_flush(__DRIcontext *cPriv,
/* Flush the drawable. */
if ((flags & __DRI2_FLUSH_DRAWABLE) &&
drawable->textures[ST_ATTACHMENT_BACK_LEFT]) {
- /* Resolve MSAA buffers. */
if (drawable->stvis.samples > 1) {
- dri_msaa_resolve(ctx, drawable, ST_ATTACHMENT_BACK_LEFT);
+ /* Resolve the MSAA back buffer. */
+ dri_pipe_blit(ctx->st->pipe,
+ drawable->textures[ST_ATTACHMENT_BACK_LEFT],
+ drawable->msaa_textures[ST_ATTACHMENT_BACK_LEFT]);
+
/* FRONT_LEFT is resolved in drawable->flush_frontbuffer. */
}
diff --git a/src/gallium/state_trackers/dri/common/dri_drawable.h
b/src/gallium/state_trackers/dri/common/dri_drawable.h
index 56f8a40..50e5cc4 100644
--- a/src/gallium/state_trackers/dri/common/dri_drawable.h
+++ b/src/gallium/state_trackers/dri/common/dri_drawable.h
@@ -110,9 +110,9 @@ dri_drawable_get_format(struct dri_drawable *drawable,
unsigned *bind);
void
-dri_msaa_resolve(struct dri_context *ctx,
- struct dri_drawable *drawable,
- enum st_attachment_type att);
+dri_pipe_blit(struct pipe_context *pipe,
+ struct pipe_resource *dst,
+ struct pipe_resource *src);
void
dri_flush(__DRIcontext *cPriv,
diff --git a/src/gallium/state_trackers/dri/drm/dri2.c
b/src/gallium/state_trackers/dri/drm/dri2.c
index 4117a9f..50628a6 100644
--- a/src/gallium/state_trackers/dri/drm/dri2.c
+++ b/src/gallium/state_trackers/dri/drm/dri2.c
@@ -470,7 +470,10 @@ dri2_flush_frontbuffer(struct dri_context *ctx,
if (drawable->stvis.samples > 1) {
struct pipe_context *pipe = ctx->st->pipe;
- dri_msaa_resolve(ctx, drawable, ST_ATTACHMENT_FRONT_LEFT);
+ /* Resolve the front buffer. */
+ dri_pipe_blit(ctx->st->pipe,
+drawable->textures[ST_ATTACHMENT_FRONT_LEFT],
+drawable->msaa_textures[ST_ATTACHMENT_FRONT_LEFT]);
pipe->flush(pipe, NULL, 0);
}
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Mesa (master): st/dri: if flushing a drawable, don't set reason=SWAPBUFFERS
Module: Mesa
Branch: master
Commit: 3475b2213381cdbda7a620d4c0c7708f6969f489
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3475b2213381cdbda7a620d4c0c7708f6969f489
Author: Marek Olšák
Date: Sat Jun 1 03:19:21 2013 +0200
st/dri: if flushing a drawable, don't set reason=SWAPBUFFERS
0 means SWAPBUFFERS.
Reviewed-by: Brian Paul
---
src/gallium/state_trackers/dri/drm/dri2.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/gallium/state_trackers/dri/drm/dri2.c
b/src/gallium/state_trackers/dri/drm/dri2.c
index a0b29d3..1dcc1f7 100644
--- a/src/gallium/state_trackers/dri/drm/dri2.c
+++ b/src/gallium/state_trackers/dri/drm/dri2.c
@@ -45,7 +45,7 @@
static void
dri2_flush_drawable(__DRIdrawable *dPriv)
{
- dri_flush(dPriv->driContextPriv, dPriv, __DRI2_FLUSH_DRAWABLE, 0);
+ dri_flush(dPriv->driContextPriv, dPriv, __DRI2_FLUSH_DRAWABLE, -1);
}
static void
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Mesa (master): st/dri: resolve the back buffer only in SwapBuffers
Module: Mesa
Branch: master
Commit: a713d7b1b962129c4d480c56e7d29bc82f511a1f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a713d7b1b962129c4d480c56e7d29bc82f511a1f
Author: Marek Olšák
Date: Sat Jun 1 03:18:04 2013 +0200
st/dri: resolve the back buffer only in SwapBuffers
Reviewed-by: Brian Paul
---
.../state_trackers/dri/common/dri_drawable.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/state_trackers/dri/common/dri_drawable.c
b/src/gallium/state_trackers/dri/common/dri_drawable.c
index 1c2bad4..18d8d89 100644
--- a/src/gallium/state_trackers/dri/common/dri_drawable.c
+++ b/src/gallium/state_trackers/dri/common/dri_drawable.c
@@ -435,14 +435,14 @@ dri_flush(__DRIcontext *cPriv,
/* Flush the drawable. */
if ((flags & __DRI2_FLUSH_DRAWABLE) &&
drawable->textures[ST_ATTACHMENT_BACK_LEFT]) {
- if (drawable->stvis.samples > 1) {
+ if (drawable->stvis.samples > 1 &&
+ reason == __DRI2_THROTTLE_SWAPBUFFER) {
/* Resolve the MSAA back buffer. */
dri_pipe_blit(ctx->st->pipe,
drawable->textures[ST_ATTACHMENT_BACK_LEFT],
drawable->msaa_textures[ST_ATTACHMENT_BACK_LEFT]);
- if (reason == __DRI2_THROTTLE_SWAPBUFFER &&
- drawable->msaa_textures[ST_ATTACHMENT_FRONT_LEFT] &&
+ if (drawable->msaa_textures[ST_ATTACHMENT_FRONT_LEFT] &&
drawable->msaa_textures[ST_ATTACHMENT_BACK_LEFT]) {
swap_msaa_buffers = TRUE;
}
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Mesa (master): st/dri: always copy new DRI front and back buffers to corresponding MSAA buffers
Module: Mesa
Branch: master
Commit: b77316ad7594fa5873717992b6986cb4c0179d23
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b77316ad7594fa5873717992b6986cb4c0179d23
Author: Marek Olšák
Date: Fri May 31 21:52:01 2013 +0200
st/dri: always copy new DRI front and back buffers to corresponding MSAA buffers
This commit fixes these piglit tests with an MSAA visual forced on:
- read-front
- glx-copy-sub-buffer
Reviewed-by: Brian Paul
---
src/gallium/state_trackers/dri/drm/dri2.c | 27 +++
1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/src/gallium/state_trackers/dri/drm/dri2.c
b/src/gallium/state_trackers/dri/drm/dri2.c
index 50628a6..a0b29d3 100644
--- a/src/gallium/state_trackers/dri/drm/dri2.c
+++ b/src/gallium/state_trackers/dri/drm/dri2.c
@@ -180,6 +180,8 @@ dri2_drawable_process_buffers(struct dri_drawable *drawable,
struct winsys_handle whandle;
boolean alloc_depthstencil = FALSE;
unsigned i, j, bind;
+ struct pipe_screen *pscreen = screen->base.screen;
+ struct pipe_context *pipe = NULL;
if (drawable->old_num == buffer_count &&
drawable->old_w == dri_drawable->w &&
@@ -296,6 +298,26 @@ dri2_drawable_process_buffers(struct dri_drawable
*drawable,
screen->base.screen->resource_create(screen->base.screen,
&templ);
assert(drawable->msaa_textures[att]);
+
+ /* If there are any MSAA resources, we should initialize them
+* such that they contain the same data as the single-sample
+* resources we just got from the X server.
+*
+* The reason for this is that the state tracker (and
+* therefore the app) can access the MSAA resources only.
+* The single-sample resources are not exposed
+* to the state tracker.
+*
+* We don't have a context here, so create one temporarily.
+* We may need to create a persistent context if creation and
+* destruction of the context becomes a bottleneck.
+*/
+ if (!pipe)
+ pipe = pscreen->context_create(pscreen, NULL);
+
+ dri_pipe_blit(pipe,
+ drawable->msaa_textures[att],
+ drawable->textures[att]);
}
}
else {
@@ -349,6 +371,11 @@ dri2_drawable_process_buffers(struct dri_drawable
*drawable,
drawable->old_w = dri_drawable->w;
drawable->old_h = dri_drawable->h;
memcpy(drawable->old, buffers, sizeof(__DRIbuffer) * buffer_count);
+
+ if (pipe) {
+ pipe->flush(pipe, NULL, 0);
+ pipe->destroy(pipe);
+ }
}
static __DRIbuffer *
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Mesa (master): mesa: Fix bug in unclamped float to ubyte conversion.
Module: Mesa
Branch: master
Commit: bf2c074a2fb122bafbbe0f3c7978b89685f2698b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf2c074a2fb122bafbbe0f3c7978b89685f2698b
Author: Manfred Ernst
Date: Wed Jun 12 20:03:02 2013 -0700
mesa: Fix bug in unclamped float to ubyte conversion.
Problem: The IEEE float optimized version of UNCLAMPED_FLOAT_TO_UBYTE
in macros.h computed incorrect results for inputs in the range
0x3f7f (=0.99609375) to 0x3f7f7f80 (=0.99803924560546875)
inclusive. 0x3f7f7f80 is the IEEE float value that results in 254.5
when multiplied by 255. With rounding mode "round to closest even
integer", this is the largest float in the range 0.0-1.0 that is
converted to 254 by the generic implementation of
UNCLAMPED_FLOAT_TO_UBYTE. The IEEE float optimized version
incorrectly defined the cut-off for mapping to 255 as 0x3f7f
(=255.0/256.0). The same bug was present in the function
float_to_ubyte in u_math.h.
Fix: The proposed fix replaces the incorrect cut-off value by
0x3f80, which is the IEEE float representation of 1.0f. 0x3f7f7f81
(or any value in between) would also work, but 1.0f is probably
cleaner.
The patch does not regress piglit on llvmpipe and on i965 on sandy
bridge.
Tested-by Stéphane Marchesin
Reviewed-by Stéphane Marchesin
Reviewed-by: Brian Paul
---
src/gallium/auxiliary/util/u_math.h |3 +--
src/mesa/main/macros.h |3 +--
2 files changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_math.h
b/src/gallium/auxiliary/util/u_math.h
index 607fbec..64d16cb 100644
--- a/src/gallium/auxiliary/util/u_math.h
+++ b/src/gallium/auxiliary/util/u_math.h
@@ -540,14 +540,13 @@ ubyte_to_float(ubyte ub)
static INLINE ubyte
float_to_ubyte(float f)
{
- const int ieee_0996 = 0x3f7f; /* 0.996 or so */
union fi tmp;
tmp.f = f;
if (tmp.i < 0) {
return (ubyte) 0;
}
- else if (tmp.i >= ieee_0996) {
+ else if (tmp.i >= 0x3f80 /* 1.0f */) {
return (ubyte) 255;
}
else {
diff --git a/src/mesa/main/macros.h b/src/mesa/main/macros.h
index ac02438..ddfeee2 100644
--- a/src/mesa/main/macros.h
+++ b/src/mesa/main/macros.h
@@ -141,7 +141,6 @@ extern GLfloat _mesa_ubyte_to_float_color_tab[256];
*** CLAMPED_FLOAT_TO_UBYTE: map float known to be in [0,1] to ubyte in [0,255]
***/
#if defined(USE_IEEE) && !defined(DEBUG)
-#define IEEE_0996 0x3f7f /* 0.996 or so */
/* This function/macro is sensitive to precision. Test very carefully
* if you change it!
*/
@@ -151,7 +150,7 @@ extern GLfloat _mesa_ubyte_to_float_color_tab[256];
__tmp.f = (F); \
if (__tmp.i < 0)\
UB = (GLubyte) 0;
\
- else if (__tmp.i >= IEEE_0996) \
+ else if (__tmp.i >= IEEE_ONE) \
UB = (GLubyte) 255; \
else { \
__tmp.f = __tmp.f * (255.0F/256.0F) + 32768.0F; \
___
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Mesa (master): ilo: fix for util_blitter_clear() changes
Module: Mesa Branch: master Commit: b65bdc61bd3d694d26ccae165b12f7d6d41327f9 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b65bdc61bd3d694d26ccae165b12f7d6d41327f9 Author: Chia-I Wu Date: Thu Jun 13 12:57:07 2013 +0800 ilo: fix for util_blitter_clear() changes It has been broken since 17350ea979b883662573dac136cd9efb49938210. --- src/gallium/drivers/ilo/ilo_blit.c |5 + 1 files changed, 1 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/ilo/ilo_blit.c b/src/gallium/drivers/ilo/ilo_blit.c index 39c4773..147dbe4 100644 --- a/src/gallium/drivers/ilo/ilo_blit.c +++ b/src/gallium/drivers/ilo/ilo_blit.c @@ -602,10 +602,7 @@ ilo_clear(struct pipe_context *pipe, util_blitter_clear(ilo->blitter, ilo->fb.state.width, ilo->fb.state.height, - ilo->fb.state.nr_cbufs, buffers, - (ilo->fb.state.nr_cbufs) ? ilo->fb.state.cbufs[0]->format : -PIPE_FORMAT_NONE, - color, depth, stencil); + buffers, color, depth, stencil); ilo_blitter_end(ilo); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): ilo: re-emit states that involve resources
Module: Mesa
Branch: master
Commit: 6057d7b7b58102bf7c3c4ecb08c1b7261f299efa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6057d7b7b58102bf7c3c4ecb08c1b7261f299efa
Author: Chia-I Wu
Date: Thu Jun 13 10:10:17 2013 +0800
ilo: re-emit states that involve resources
Even with hardware contexts, since we do not pin resources, we have to re-emit
the states so that the resources are referenced (by cp->bo) and their offsets
are updated in case they are moved. This also allows us to elimiate cp flush
in is_bo_busy().
---
src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c | 23 +++
src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.h |1 +
src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c | 12 +++-
src/gallium/drivers/ilo/ilo_transfer.c |8
4 files changed, 23 insertions(+), 21 deletions(-)
diff --git a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c
b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c
index e4315df..c60fc01 100644
--- a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c
+++ b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.c
@@ -210,7 +210,8 @@ gen6_pipeline_common_base_address(struct ilo_3d_pipeline *p,
struct gen6_pipeline_session *session)
{
/* STATE_BASE_ADDRESS */
- if (session->state_bo_changed || session->instruction_bo_changed) {
+ if (session->state_bo_changed || session->instruction_bo_changed ||
+ session->batch_bo_changed) {
if (p->dev->gen == ILO_GEN(6))
gen6_wa_pipe_control_post_sync(p, false);
@@ -396,13 +397,14 @@ gen6_pipeline_vf(struct ilo_3d_pipeline *p,
struct gen6_pipeline_session *session)
{
/* 3DSTATE_INDEX_BUFFER */
- if (DIRTY(INDEX_BUFFER)) {
+ if (DIRTY(INDEX_BUFFER) || session->batch_bo_changed) {
p->gen6_3DSTATE_INDEX_BUFFER(p->dev,
&ilo->ib.state, session->info->primitive_restart, p->cp);
}
/* 3DSTATE_VERTEX_BUFFERS */
- if (DIRTY(VERTEX_BUFFERS) || DIRTY(VERTEX_ELEMENTS)) {
+ if (DIRTY(VERTEX_BUFFERS) || DIRTY(VERTEX_ELEMENTS) ||
+ session->batch_bo_changed) {
p->gen6_3DSTATE_VERTEX_BUFFERS(p->dev,
ilo->vb.states, ilo->vb.enabled_mask, ilo->ve, p->cp);
}
@@ -714,7 +716,7 @@ gen6_pipeline_wm_depth(struct ilo_3d_pipeline *p,
struct gen6_pipeline_session *session)
{
/* 3DSTATE_DEPTH_BUFFER and 3DSTATE_CLEAR_PARAMS */
- if (DIRTY(FRAMEBUFFER)) {
+ if (DIRTY(FRAMEBUFFER) || session->batch_bo_changed) {
if (p->dev->gen == ILO_GEN(6)) {
gen6_wa_pipe_control_post_sync(p, false);
gen6_wa_pipe_control_wm_depth_flush(p);
@@ -1298,11 +1300,24 @@ gen6_pipeline_prepare(const struct ilo_3d_pipeline *p,
if (session->hw_ctx_changed) {
/* these should be enough to make everything uploaded */
+ session->batch_bo_changed = true;
session->state_bo_changed = true;
session->instruction_bo_changed = true;
session->prim_changed = true;
}
else {
+ /*
+ * Any state that involves resources needs to be re-emitted when the
+ * batch bo changed. This is because we do not pin the resources and
+ * their offsets (or existence) may change between batch buffers.
+ *
+ * Since we messed around with ILO_3D_PIPELINE_INVALIDATE_BATCH_BO in
+ * handle_invalid_batch_bo(), use ILO_3D_PIPELINE_INVALIDATE_STATE_BO as
+ * a temporary workaround.
+ */
+ session->batch_bo_changed =
+ (p->invalidate_flags & ILO_3D_PIPELINE_INVALIDATE_STATE_BO);
+
session->state_bo_changed =
(p->invalidate_flags & ILO_3D_PIPELINE_INVALIDATE_STATE_BO);
session->instruction_bo_changed =
diff --git a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.h
b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.h
index 34d4320..18d9309 100644
--- a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.h
+++ b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen6.h
@@ -42,6 +42,7 @@ struct gen6_pipeline_session {
int init_cp_space;
bool hw_ctx_changed;
+ bool batch_bo_changed;
bool state_bo_changed;
bool instruction_bo_changed;
bool prim_changed;
diff --git a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c
b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c
index 2811edf..96e2e18 100644
--- a/src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c
+++ b/src/gallium/drivers/ilo/ilo_3d_pipeline_gen7.c
@@ -394,7 +394,8 @@ gen7_pipeline_sol(struct ilo_3d_pipeline *p,
gen6_pipeline_update_max_svbi(p, ilo, session);
/* 3DSTATE_SO_BUFFER */
- if ((DIRTY(STREAM_OUTPUT_TARGETS) || dirty_sh) && ilo->so.enabled) {
+ if ((DIRTY(STREAM_OUTPUT_TARGETS) || dirty_sh ||
+session->batch_bo_changed) && ilo->so.enabled) {
int i;
for (i = 0; i < ilo->so.count; i++) {
@@ -529,15 +530,8 @@ gen7_pipeline_wm(struct ilo_3d_pipeline *p,
gen7_wa_pipe_control_wm_depth_stall(p, emit_3dstate_depth_buffer);
}
- /*
-* glCopyPix
