Mesa (master): radeonsi: Also set the depth component mask bit for stencil-only exports
Module: Mesa Branch: master Commit: 46fd81e586f0c1a76ab66b9a7558783c481f111e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=46fd81e586f0c1a76ab66b9a7558783c481f111e Author: Michel Dänzer michel.daen...@amd.com Date: Fri Aug 23 14:55:45 2013 +0200 radeonsi: Also set the depth component mask bit for stencil-only exports The stencil values come out wrong without this for some reason. 50 more little piglits. Cc: mesa-sta...@lists.freedesktop.org --- src/gallium/drivers/radeonsi/radeonsi_shader.c |5 - 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c b/src/gallium/drivers/radeonsi/radeonsi_shader.c index a1dec17..2b1928a 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_shader.c +++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c @@ -826,7 +826,10 @@ handle_semantic: args[7] = args[8] = args[6] = LLVMBuildLoad(base-gallivm-builder, out_ptr, ); - mask |= 0x2; + /* Only setting the stencil component bit (0x2) here +* breaks some stencil piglit tests +*/ + mask |= 0x3; if (depth_index 0) args[5] = args[6]; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Don' t try to fall back when creating unrecognized program targets.
Module: Mesa Branch: master Commit: 4bf91ca791844c16fda48f54386f1b30f6acefca URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4bf91ca791844c16fda48f54386f1b30f6acefca Author: Paul Berry stereotype...@gmail.com Date: Fri Aug 23 11:43:26 2013 -0700 i965: Don't try to fall back when creating unrecognized program targets. If brwNewProgram is asked to create a program for an unrecognized target, don't bother falling back on _mesa_new_program(). That just hides bugs. Reviewed-by: Matt Turner matts...@gmail.com Reviewed-by: Anuj Phogat anuj.pho...@gmail.com v2: Use assert() rather than _mesa_problem(). Reviewed-by: Kenneth Graunke kenn...@whitecape.org Reviewed-by: Chad Versace chad.vers...@linux.intel.com --- src/mesa/drivers/dri/i965/brw_program.c |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_program.c b/src/mesa/drivers/dri/i965/brw_program.c index c40d506..9a517be 100644 --- a/src/mesa/drivers/dri/i965/brw_program.c +++ b/src/mesa/drivers/dri/i965/brw_program.c @@ -114,7 +114,8 @@ static struct gl_program *brwNewProgram( struct gl_context *ctx, } default: - return _mesa_new_program(ctx, target, id); + assert(!Unsupported target in brwNewProgram()); + return NULL; } } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Remove redundant (and uninitialized) field vec4_generator::ctx.
Module: Mesa
Branch: master
Commit: 612226c43b072eb45dc3ed21484054824e1c863c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=612226c43b072eb45dc3ed21484054824e1c863c
Author: Paul Berry stereotype...@gmail.com
Date: Thu Aug 22 17:15:04 2013 -0700
i965: Remove redundant (and uninitialized) field vec4_generator::ctx.
We never noticed that this field was uninitialized because it is only
used in an error path that reports internal Mesa errors.
But it's silly to have it around anyway because brw-ctx is
equivalent.
Should fix Coverity defect CID 1063351: Uninitialized pointer field
(UNINIT_CTOR) /src/mesa/drivers/dri/i965/brw_vec4_emit.cpp: 148
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i965/brw_vec4.h|1 -
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp |4 ++--
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 5d8f0bf..a39dc50 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -659,7 +659,6 @@ private:
void mark_surface_used(unsigned surf_index);
struct brw_context *brw;
- struct gl_context *ctx;
struct brw_compile *p;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index 8d3696c..1f00260 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -1014,10 +1014,10 @@
vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
default:
if (inst-opcode (int) ARRAY_SIZE(opcode_descs)) {
- _mesa_problem(ctx, Unsupported opcode in `%s' in VS\n,
+ _mesa_problem(brw-ctx, Unsupported opcode in `%s' in VS\n,
opcode_descs[inst-opcode].name);
} else {
- _mesa_problem(ctx, Unsupported opcode %d in VS, inst-opcode);
+ _mesa_problem(brw-ctx, Unsupported opcode %d in VS, inst-opcode);
}
abort();
}
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Mesa (9.2): mesa: Set query-EverBound in glQueryCounter().
Module: Mesa
Branch: 9.2
Commit: f31a1d9f8d4e0b36f62beb4dcb2ff1207e8cf476
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f31a1d9f8d4e0b36f62beb4dcb2ff1207e8cf476
Author: Kenneth Graunke kenn...@whitecape.org
Date: Fri Aug 23 10:35:34 2013 -0700
mesa: Set query-EverBound in glQueryCounter().
glIsQuery is supposed to return false for names returned by glGenQueries
until their first use. BeginQuery is a use, but QueryCounter is also a
use.
From the ARB_timer_query spec:
A timer query object is created with the command
void QueryCounter(uint id, enum target);
[...] If id is an unused query object name, the
name is marked as used [...]
Fixes Piglit's spec/ARB_timer_query/query-lifetime.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Chad Versace chad.vers...@linux.intel.com
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit 7950315583244f03a58ac00d7b0516860475914c)
---
src/mesa/main/queryobj.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/src/mesa/main/queryobj.c b/src/mesa/main/queryobj.c
index b74898c..60356b8 100644
--- a/src/mesa/main/queryobj.c
+++ b/src/mesa/main/queryobj.c
@@ -485,6 +485,7 @@ _mesa_QueryCounter(GLuint id, GLenum target)
q-Target = target;
q-Result = 0;
q-Ready = GL_FALSE;
+ q-EverBound = GL_TRUE;
if (ctx-Driver.QueryCounter) {
ctx-Driver.QueryCounter(ctx, q);
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Mesa (9.2): nv30: add forgotten PIPE_CAP_CUBE_MAP_ARRAY cap to list
Module: Mesa Branch: 9.2 Commit: 3370dfdf3ebd14b0864be680971d006d8df047af URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3370dfdf3ebd14b0864be680971d006d8df047af Author: Ilia Mirkin imir...@alum.mit.edu Date: Mon Aug 19 06:49:45 2013 -0400 nv30: add forgotten PIPE_CAP_CUBE_MAP_ARRAY cap to list Signed-off-by: Ilia Mirkin imir...@alum.mit.edu Cc: 9.2 mesa-sta...@lists.freedesktop.org (cherry picked from commit bac6efe8e33115263fc7f1637671b303ea0b4243) --- src/gallium/drivers/nv30/nv30_screen.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/gallium/drivers/nv30/nv30_screen.c b/src/gallium/drivers/nv30/nv30_screen.c index 3d55d6f..34b0e62 100644 --- a/src/gallium/drivers/nv30/nv30_screen.c +++ b/src/gallium/drivers/nv30/nv30_screen.c @@ -113,6 +113,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_BARRIER: case PIPE_CAP_SEAMLESS_CUBE_MAP: case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: + case PIPE_CAP_CUBE_MAP_ARRAY: case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (9.2): radeonsi: Also set the depth component mask bit for stencil-only exports
Module: Mesa Branch: 9.2 Commit: 59781051eb714c3b74616bcba6376cbbea0f8470 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=59781051eb714c3b74616bcba6376cbbea0f8470 Author: Michel Dänzer michel.daen...@amd.com Date: Fri Aug 23 14:55:45 2013 +0200 radeonsi: Also set the depth component mask bit for stencil-only exports The stencil values come out wrong without this for some reason. 50 more little piglits. Cc: mesa-sta...@lists.freedesktop.org (cherry picked from commit 46fd81e586f0c1a76ab66b9a7558783c481f111e) --- src/gallium/drivers/radeonsi/radeonsi_shader.c |5 - 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c b/src/gallium/drivers/radeonsi/radeonsi_shader.c index 3d64324..6c89963 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_shader.c +++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c @@ -804,7 +804,10 @@ handle_semantic: args[7] = args[8] = args[6] = LLVMBuildLoad(base-gallivm-builder, out_ptr, ); - mask |= 0x2; + /* Only setting the stencil component bit (0x2) here +* breaks some stencil piglit tests +*/ + mask |= 0x3; if (depth_index 0) args[5] = args[6]; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Allow C++ type safety in the use of enum brw_urb_write_flags.
Module: Mesa
Branch: master
Commit: cfe39ea14edc8db13c549b853b214e676f8276f1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cfe39ea14edc8db13c549b853b214e676f8276f1
Author: Paul Berry stereotype...@gmail.com
Date: Fri Aug 23 13:19:19 2013 -0700
i965: Allow C++ type safety in the use of enum brw_urb_write_flags.
(From a suggestion by Francisco Jerez)
If an enum represents a bitfield of flags, e.g.:
enum E {
A = 1,
B = 2,
C = 4,
D = 8,
};
then C++ normally prohibits statements like this:
enum E x = A | B;
because A and B are implicitly converted to ints before OR-ing them,
and an int can't be stored in an enum without a type cast. C, on the
other hand, allows an int to be implicitly converted to an enum
without casting.
In the past we've dealt with this situation by storing flag bitfields
as ints. This avoids ugly casting at the expense of some type safety
that C++ would normally have offered (e.g. we get no warning if we
accidentally use the wrong enum type).
However, we can get the best of both worlds if we override the |
operator. The ugly casting is confined to the operator overload, and
we still get the benefit of C++ making sure we don't use the wrong
enum type.
v2: Remove unnecessary comment and unnecessary use of enum keyword.
Use static_cast.
Reviewed-by: Chad Versace chad.vers...@linux.intel.com
Reviewed-by: Francisco Jerez curroje...@riseup.net
---
src/mesa/drivers/dri/i965/brw_clip.h |2 +-
src/mesa/drivers/dri/i965/brw_clip_util.c |2 +-
src/mesa/drivers/dri/i965/brw_eu.h | 16 +++-
src/mesa/drivers/dri/i965/brw_eu_emit.c|4 ++--
src/mesa/drivers/dri/i965/brw_sf_emit.c| 12
src/mesa/drivers/dri/i965/brw_vec4.h |2 +-
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |3 ++-
7 files changed, 30 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clip.h
b/src/mesa/drivers/dri/i965/brw_clip.h
index 5af0ad3..41f5c75 100644
--- a/src/mesa/drivers/dri/i965/brw_clip.h
+++ b/src/mesa/drivers/dri/i965/brw_clip.h
@@ -173,7 +173,7 @@ void brw_clip_init_planes( struct brw_clip_compile *c );
void brw_clip_emit_vue(struct brw_clip_compile *c,
struct brw_indirect vert,
- unsigned flags,
+ enum brw_urb_write_flags flags,
GLuint header);
void brw_clip_kill_thread(struct brw_clip_compile *c);
diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c
b/src/mesa/drivers/dri/i965/brw_clip_util.c
index d5c50d7..24d053e 100644
--- a/src/mesa/drivers/dri/i965/brw_clip_util.c
+++ b/src/mesa/drivers/dri/i965/brw_clip_util.c
@@ -313,7 +313,7 @@ void brw_clip_interp_vertex( struct brw_clip_compile *c,
void brw_clip_emit_vue(struct brw_clip_compile *c,
struct brw_indirect vert,
- unsigned flags,
+ enum brw_urb_write_flags flags,
GLuint header)
{
struct brw_compile *p = c-func;
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
b/src/mesa/drivers/dri/i965/brw_eu.h
index 9053ea2..387450b 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -229,6 +229,8 @@ void brw_set_dp_write_message(struct brw_compile *p,
GLuint send_commit_msg);
enum brw_urb_write_flags {
+ BRW_URB_WRITE_NO_FLAGS = 0,
+
/**
* Causes a new URB entry to be allocated, and its address stored in the
* destination register (gen 7).
@@ -271,11 +273,23 @@ enum brw_urb_write_flags {
BRW_URB_WRITE_ALLOCATE | BRW_URB_WRITE_COMPLETE,
};
+#ifdef __cplusplus
+/**
+ * Allow brw_urb_write_flags enums to be ORed together.
+ */
+inline brw_urb_write_flags
+operator|(brw_urb_write_flags x, brw_urb_write_flags y)
+{
+ return static_castbrw_urb_write_flags(static_castint(x) |
+ static_castint(y));
+}
+#endif
+
void brw_urb_WRITE(struct brw_compile *p,
struct brw_reg dest,
GLuint msg_reg_nr,
struct brw_reg src0,
- unsigned flags,
+ enum brw_urb_write_flags flags,
GLuint msg_length,
GLuint response_length,
GLuint offset,
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index b55b57e..ecf8597 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -515,7 +515,7 @@ static void brw_set_ff_sync_message(struct brw_compile *p,
static void brw_set_urb_message( struct brw_compile *p,
struct brw_instruction *insn,
- unsigned flags,
+ enum brw_urb_write_flags flags,
GLuint msg_length,
GLuint
Mesa (master): i965/vs: Move base_reg_count computation to brw_alloc_reg_set().
Module: Mesa
Branch: master
Commit: a149f744d9dfc116860c04ce30256f7bed96e323
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a149f744d9dfc116860c04ce30256f7bed96e323
Author: Kenneth Graunke kenn...@whitecape.org
Date: Wed Aug 21 22:06:15 2013 -0700
i965/vs: Move base_reg_count computation to brw_alloc_reg_set().
We're soon going to be calling brw_alloc_reg_set() from outside of the
visitor, where we don't have the precomputed max_grf variable handy.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Paul Berry stereotype...@gmail.com
---
.../drivers/dri/i965/brw_vec4_reg_allocate.cpp |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index 091d5c1..fbd79d0 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -97,8 +97,10 @@ vec4_visitor::reg_allocate_trivial()
}
static void
-brw_alloc_reg_set(struct brw_context *brw, int base_reg_count)
+brw_alloc_reg_set(struct brw_context *brw)
{
+ int base_reg_count = brw-gen = 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
+
/* After running split_virtual_grfs(), almost all VGRFs will be of size 1.
* SEND-from-GRF sources cannot be split, so we also need classes for each
* potential message length.
@@ -177,7 +179,6 @@ vec4_visitor::reg_allocate()
{
unsigned int hw_reg_mapping[virtual_grf_count];
int payload_reg_count = this-first_non_payload_grf;
- int base_reg_count = max_grf;
/* Using the trivial allocator can be useful in debugging undefined
* register access as a result of broken optimization passes.
@@ -187,7 +188,7 @@ vec4_visitor::reg_allocate()
calculate_live_intervals();
- brw_alloc_reg_set(brw, base_reg_count);
+ brw_alloc_reg_set(brw);
int node_count = virtual_grf_count;
int first_payload_node = node_count;
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Mesa (master): i965/vs: Expose the payload registers to the register allocator.
Module: Mesa
Branch: master
Commit: 78bc8fb851a4783292a5e1ffdfeda2451dae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=78bc8fb851a4783292a5e1ffdfeda2451dae
Author: Kenneth Graunke kenn...@whitecape.org
Date: Wed Aug 21 21:55:40 2013 -0700
i965/vs: Expose the payload registers to the register allocator.
For now, nothing else can get allocated over them. That may change at
some point in the future.
This also means that base_reg_count can be computed without knowing the
number of registers used for the payload, which is required if we want
to allocate the register set once at context creation time.
See commit 551e1cd44f6857f7e29ea4c8f892da5a97844377, which implemented
virtually identical code in the FS backend.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Paul Berry stereotype...@gmail.com
---
src/mesa/drivers/dri/i965/brw_vec4.h |2 +
.../drivers/dri/i965/brw_vec4_reg_allocate.cpp | 40 +---
2 files changed, 36 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 1f9cb95..6be15fe 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -537,6 +537,8 @@ public:
protected:
void emit_vertex();
void lower_attributes_to_hw_regs(const int *attribute_map);
+ void setup_payload_interference(struct ra_graph *g, int first_payload_node,
+ int reg_node_count);
virtual dst_reg *make_reg_for_system_value(ir_variable *ir) = 0;
virtual void setup_payload() = 0;
virtual void emit_prolog() = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index ab75a17..091d5c1 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -148,12 +148,36 @@ brw_alloc_reg_set(struct brw_context *brw, int
base_reg_count)
ra_set_finalize(brw-vs.regs, NULL);
}
+void
+vec4_visitor::setup_payload_interference(struct ra_graph *g,
+ int first_payload_node,
+ int reg_node_count)
+{
+ int payload_node_count = this-first_non_payload_grf;
+
+ for (int i = 0; i payload_node_count; i++) {
+ /* Mark each payload reg node as being allocated to its physical
register.
+ *
+ * The alternative would be to have per-physical register classes, which
+ * would just be silly.
+ */
+ ra_set_node_reg(g, first_payload_node + i, i);
+
+ /* For now, just mark each payload node as interfering with every other
+ * node to be allocated.
+ */
+ for (int j = 0; j reg_node_count; j++) {
+ ra_add_node_interference(g, first_payload_node + i, j);
+ }
+ }
+}
+
bool
vec4_visitor::reg_allocate()
{
unsigned int hw_reg_mapping[virtual_grf_count];
- int first_assigned_grf = this-first_non_payload_grf;
- int base_reg_count = max_grf - first_assigned_grf;
+ int payload_reg_count = this-first_non_payload_grf;
+ int base_reg_count = max_grf;
/* Using the trivial allocator can be useful in debugging undefined
* register access as a result of broken optimization passes.
@@ -165,8 +189,10 @@ vec4_visitor::reg_allocate()
brw_alloc_reg_set(brw, base_reg_count);
- struct ra_graph *g = ra_alloc_interference_graph(brw-vs.regs,
- virtual_grf_count);
+ int node_count = virtual_grf_count;
+ int first_payload_node = node_count;
+ node_count += payload_reg_count;
+ struct ra_graph *g = ra_alloc_interference_graph(brw-vs.regs, node_count);
for (int i = 0; i virtual_grf_count; i++) {
int size = this-virtual_grf_sizes[i];
@@ -181,6 +207,8 @@ vec4_visitor::reg_allocate()
}
}
+ setup_payload_interference(g, first_payload_node, node_count);
+
if (!ra_allocate_no_spills(g)) {
/* Failed to allocate registers. Spill a reg, and the caller will
* loop back into here to try again.
@@ -199,11 +227,11 @@ vec4_visitor::reg_allocate()
* regs in the register classes back down to real hardware reg
* numbers.
*/
- prog_data-total_grf = first_assigned_grf;
+ prog_data-total_grf = payload_reg_count;
for (int i = 0; i virtual_grf_count; i++) {
int reg = ra_get_node_reg(g, i);
- hw_reg_mapping[i] = first_assigned_grf + brw-vs.ra_reg_to_grf[reg];
+ hw_reg_mapping[i] = brw-vs.ra_reg_to_grf[reg];
prog_data-total_grf = MAX2(prog_data-total_grf,
hw_reg_mapping[i] + virtual_grf_sizes[i]);
}
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Mesa (master): i965/vs: Use a fixed set of register classes.
Module: Mesa
Branch: master
Commit: 528d70d0b5fd2722bc32d42d8859865081cf0730
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=528d70d0b5fd2722bc32d42d8859865081cf0730
Author: Kenneth Graunke kenn...@whitecape.org
Date: Wed Aug 21 16:01:45 2013 -0700
i965/vs: Use a fixed set of register classes.
Arrays, structures, and matrices use large VGRFs of arbitrary sizes.
However, split_virtual_grfs() breaks those down into VGRFs of size 1.
For reference, commit 5d90b988791e51cfb6413109271ad102fd7a304c is the
analogous change to the FS backend.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Paul Berry stereotype...@gmail.com
---
.../drivers/dri/i965/brw_vec4_reg_allocate.cpp | 50 +--
1 files changed, 13 insertions(+), 37 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index 0b27383..ab75a17 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -97,11 +97,15 @@ vec4_visitor::reg_allocate_trivial()
}
static void
-brw_alloc_reg_set_for_classes(struct brw_context *brw,
- int *class_sizes,
- int class_count,
- int base_reg_count)
+brw_alloc_reg_set(struct brw_context *brw, int base_reg_count)
{
+ /* After running split_virtual_grfs(), almost all VGRFs will be of size 1.
+* SEND-from-GRF sources cannot be split, so we also need classes for each
+* potential message length.
+*/
+ const int class_count = 2;
+ const int class_sizes[class_count] = {1, 2};
+
/* Compute the total number of registers across all classes. */
int ra_reg_count = 0;
for (int i = 0; i class_count; i++) {
@@ -150,8 +154,6 @@ vec4_visitor::reg_allocate()
unsigned int hw_reg_mapping[virtual_grf_count];
int first_assigned_grf = this-first_non_payload_grf;
int base_reg_count = max_grf - first_assigned_grf;
- int class_sizes[base_reg_count];
- int class_count = 0;
/* Using the trivial allocator can be useful in debugging undefined
* register access as a result of broken optimization passes.
@@ -161,42 +163,16 @@ vec4_visitor::reg_allocate()
calculate_live_intervals();
- /* Set up the register classes.
-*
-* The base registers store a vec4. However, we'll need larger
-* storage for arrays, structures, and matrices, which will be sets
-* of contiguous registers.
-*/
- class_sizes[class_count++] = 1;
-
- for (int r = 0; r virtual_grf_count; r++) {
- int i;
-
- for (i = 0; i class_count; i++) {
-if (class_sizes[i] == this-virtual_grf_sizes[r])
- break;
- }
- if (i == class_count) {
-if (this-virtual_grf_sizes[r] = base_reg_count) {
- fail(Object too large to register allocate.\n);
-}
-
-class_sizes[class_count++] = this-virtual_grf_sizes[r];
- }
- }
-
- brw_alloc_reg_set_for_classes(brw, class_sizes, class_count,
base_reg_count);
+ brw_alloc_reg_set(brw, base_reg_count);
struct ra_graph *g = ra_alloc_interference_graph(brw-vs.regs,
virtual_grf_count);
for (int i = 0; i virtual_grf_count; i++) {
- for (int c = 0; c class_count; c++) {
-if (class_sizes[c] == this-virtual_grf_sizes[i]) {
- ra_set_node_class(g, i, brw-vs.classes[c]);
- break;
-}
- }
+ int size = this-virtual_grf_sizes[i];
+ assert(size = 1 size = 2
+ Register allocation relies on split_virtual_grfs().);
+ ra_set_node_class(g, i, brw-vs.classes[size - 1]);
for (int j = 0; j i; j++) {
if (virtual_grf_interferes(i, j)) {
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Mesa (master): i965/vs: Allocate register set once at context creation.
Module: Mesa
Branch: master
Commit: d65e3c082a02bd2e838d34b2ee9b87d36f6a2d25
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d65e3c082a02bd2e838d34b2ee9b87d36f6a2d25
Author: Kenneth Graunke kenn...@whitecape.org
Date: Wed Aug 21 16:27:11 2013 -0700
i965/vs: Allocate register set once at context creation.
Now that we use a fixed set of register classes, we can set up the
register set and conflict graphs once, at context creation, rather than
on every VS compile. This is obviously less expensive, and also what
we already do in the FS backend.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Paul Berry stereotype...@gmail.com
---
src/mesa/drivers/dri/i965/brw_context.c|1 +
src/mesa/drivers/dri/i965/brw_context.h|3 +++
.../drivers/dri/i965/brw_vec4_reg_allocate.cpp |6 ++
3 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 6308446..2321076 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -476,6 +476,7 @@ brwCreateContext(int api,
}
brw_fs_alloc_reg_sets(brw);
+ brw_vec4_alloc_reg_set(brw);
if (INTEL_DEBUG DEBUG_SHADER_TIME)
brw_init_shader_time(brw);
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 98a59fd..c456e61 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1413,6 +1413,9 @@ void brw_upload_cs_urb_state(struct brw_context *brw);
*/
void brw_fs_alloc_reg_sets(struct brw_context *brw);
+/* brw_vec4_reg_allocate.cpp */
+void brw_vec4_alloc_reg_set(struct brw_context *brw);
+
/* brw_disasm.c */
int brw_disasm (FILE *file, struct brw_instruction *inst, int gen);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index fbd79d0..7984203 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
@@ -96,8 +96,8 @@ vec4_visitor::reg_allocate_trivial()
return true;
}
-static void
-brw_alloc_reg_set(struct brw_context *brw)
+extern C void
+brw_vec4_alloc_reg_set(struct brw_context *brw)
{
int base_reg_count = brw-gen = 7 ? GEN7_MRF_HACK_START : BRW_MAX_GRF;
@@ -188,8 +188,6 @@ vec4_visitor::reg_allocate()
calculate_live_intervals();
- brw_alloc_reg_set(brw);
-
int node_count = virtual_grf_count;
int first_payload_node = node_count;
node_count += payload_reg_count;
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Mesa (master): glsl: init limit=0 to silence uninitialized var warning
Module: Mesa
Branch: master
Commit: f91f6ef739185086b3bbfbf67a15edb1d9a304f4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f91f6ef739185086b3bbfbf67a15edb1d9a304f4
Author: Brian Paul bri...@vmware.com
Date: Fri Aug 23 15:12:07 2013 -0600
glsl: init limit=0 to silence uninitialized var warning
Reviewed-by: Paul Berry stereotype...@gmail.com
---
src/glsl/ast_to_hir.cpp |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index feff586..0db6b45 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -1922,7 +1922,7 @@ validate_binding_qualifier(struct _mesa_glsl_parse_state
*state,
* with an array of size N, all elements of the array from binding
* through binding + N - 1 must be within this range.
*/
- unsigned limit;
+ unsigned limit = 0;
switch (state-target) {
case vertex_shader:
limit = ctx-Const.VertexProgram.MaxTextureImageUnits;
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Mesa (master): swrast: init i0, i1 values to silence warnings
Module: Mesa Branch: master Commit: 5e7ac28ebfd309782185d44813f0f86659a680cf URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e7ac28ebfd309782185d44813f0f86659a680cf Author: Brian Paul bri...@vmware.com Date: Fri Aug 23 15:33:14 2013 -0600 swrast: init i0, i1 values to silence warnings Reviewed-by: Chad Versace chad.vers...@linux.intel.com --- src/mesa/swrast/s_texfilter.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/mesa/swrast/s_texfilter.c b/src/mesa/swrast/s_texfilter.c index 0920a64..312b9ce 100644 --- a/src/mesa/swrast/s_texfilter.c +++ b/src/mesa/swrast/s_texfilter.c @@ -274,6 +274,7 @@ linear_texel_locations(GLenum wrapMode, break; default: _mesa_problem(NULL, Bad wrap mode); + *i0 = *i1 = 0; u = 0.0F; break; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa: init dst values in COPY_CLEAN_4V_TYPE_AS_FLOAT()
Module: Mesa Branch: master Commit: ef47ab520d5f4b50073cb05df0504daaf4b6fcf2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef47ab520d5f4b50073cb05df0504daaf4b6fcf2 Author: Brian Paul bri...@vmware.com Date: Fri Aug 23 15:32:28 2013 -0600 mesa: init dst values in COPY_CLEAN_4V_TYPE_AS_FLOAT() to silence gcc 4.8.1 warnings. And improve the ASSERT(0) call. Reviewed-by: Chad Versace chad.vers...@linux.intel.com --- src/mesa/main/macros.h |3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/src/mesa/main/macros.h b/src/mesa/main/macros.h index ddfeee2..1052f75 100644 --- a/src/mesa/main/macros.h +++ b/src/mesa/main/macros.h @@ -607,7 +607,8 @@ COPY_CLEAN_4V_TYPE_AS_FLOAT(GLfloat dst[4], int sz, const GLfloat src[4], UINT_AS_FLT(0), UINT_AS_FLT(1)); break; default: - ASSERT(0); + ASSIGN_4V(dst, 0.0f, 0.0f, 0.0f, 1.0f); /* silence warnings */ + ASSERT(!Unexpected type in COPY_CLEAN_4V_TYPE_AS_FLOAT macro); } COPY_SZ_4V(dst, sz, src); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): svga: replace 0 with PIPE_OK in a few places
Module: Mesa
Branch: master
Commit: 92cbfded6a3000e19385191bcf30f57e2eb933b6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=92cbfded6a3000e19385191bcf30f57e2eb933b6
Author: Brian Paul bri...@vmware.com
Date: Mon Aug 26 15:49:16 2013 -0600
svga: replace 0 with PIPE_OK in a few places
---
src/gallium/drivers/svga/svga_state_need_swtnl.c |2 +-
src/gallium/drivers/svga/svga_state_tss.c|2 +-
src/gallium/drivers/svga/svga_swtnl_state.c |6 +++---
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/svga/svga_state_need_swtnl.c
b/src/gallium/drivers/svga/svga_state_need_swtnl.c
index 38ed77c..c0bfd2c 100644
--- a/src/gallium/drivers/svga/svga_state_need_swtnl.c
+++ b/src/gallium/drivers/svga/svga_state_need_swtnl.c
@@ -74,7 +74,7 @@ update_need_swvfetch(struct svga_context *svga, unsigned
dirty)
if (!svga-curr.velems) {
/* No vertex elements bound. */
- return 0;
+ return PIPE_OK;
}
for (i = 0; i svga-curr.velems-count; i++) {
diff --git a/src/gallium/drivers/svga/svga_state_tss.c
b/src/gallium/drivers/svga/svga_state_tss.c
index 861a0df..137e208 100644
--- a/src/gallium/drivers/svga/svga_state_tss.c
+++ b/src/gallium/drivers/svga/svga_state_tss.c
@@ -164,7 +164,7 @@ update_tss_binding(struct svga_context *svga,
svga-rebind.texture_samplers = FALSE;
- return 0;
+ return PIPE_OK;
fail:
return PIPE_ERROR_OUT_OF_MEMORY;
diff --git a/src/gallium/drivers/svga/svga_swtnl_state.c
b/src/gallium/drivers/svga/svga_swtnl_state.c
index d60af3f..d66f1a1 100644
--- a/src/gallium/drivers/svga/svga_swtnl_state.c
+++ b/src/gallium/drivers/svga/svga_swtnl_state.c
@@ -125,7 +125,7 @@ update_swtnl_draw( struct svga_context *svga,
draw_set_mrd(svga-swtnl.draw,
svga-curr.depthscale);
- return 0;
+ return PIPE_OK;
}
@@ -223,12 +223,12 @@ svga_swtnl_update_vdecl( struct svga_context *svga )
vdecl[i].array.stride = offset;
if (memcmp(svga_render-vdecl, vdecl, sizeof(vdecl)) == 0)
- return 0;
+ return PIPE_OK;
memcpy(svga_render-vdecl, vdecl, sizeof(vdecl));
svga-swtnl.new_vdecl = TRUE;
- return 0;
+ return PIPE_OK;
}
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Mesa (master): tgsi_build: fix order of arguments for ind register build
Module: Mesa
Branch: master
Commit: 4763a032a0a483702d651c539ecf4566ce3fd68b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4763a032a0a483702d651c539ecf4566ce3fd68b
Author: Dave Airlie airl...@redhat.com
Date: Tue Aug 13 10:13:12 2013 +1000
tgsi_build: fix order of arguments for ind register build
This was broken when arrayid was added.
Reviewed-by: Brian Paul bri...@vmware.com
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/auxiliary/tgsi/tgsi_build.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_build.c
b/src/gallium/auxiliary/tgsi/tgsi_build.c
index fa18462..f4add02 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_build.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_build.c
@@ -876,8 +876,8 @@ static struct tgsi_ind_register
tgsi_build_ind_register(
unsigned file,
unsigned swizzle,
- unsigned arrayid,
int index,
+ unsigned arrayid,
struct tgsi_instruction *instruction,
struct tgsi_header *header )
{
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Mesa (master): tgsi: finish declaration parsing for arrays.
Module: Mesa
Branch: master
Commit: 81204d0e9cb52d05352df1b416e4e661701296e6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=81204d0e9cb52d05352df1b416e4e661701296e6
Author: Dave Airlie airl...@redhat.com
Date: Mon Aug 12 17:34:27 2013 +1000
tgsi: finish declaration parsing for arrays.
I previously fixed this partly in 9e8400f4c95bde1f955c7977066583b507159a10,
however I didn't go far enough in testing it, now when I parse a TGSI shader
with arrays in it my iterator can see the ArrayID set to the proper value.
Reviewed-by: Brian Paul bri...@vmware.com
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/auxiliary/tgsi/tgsi_build.c | 32 ++-
1 files changed, 31 insertions(+), 1 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_build.c
b/src/gallium/auxiliary/tgsi/tgsi_build.c
index 523430b..fa18462 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_build.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_build.c
@@ -124,6 +124,7 @@ tgsi_build_declaration(
unsigned semantic,
unsigned invariant,
unsigned local,
+ unsigned array,
struct tgsi_header *header )
{
struct tgsi_declaration declaration;
@@ -139,7 +140,7 @@ tgsi_build_declaration(
declaration.Semantic = semantic;
declaration.Invariant = invariant;
declaration.Local = local;
-
+ declaration.Array = array;
header_bodysize_grow( header );
return declaration;
@@ -339,6 +340,21 @@ tgsi_default_declaration_array( void )
return a;
}
+static struct tgsi_declaration_array
+tgsi_build_declaration_array(unsigned arrayid,
+ struct tgsi_declaration *declaration,
+ struct tgsi_header *header)
+{
+ struct tgsi_declaration_array da;
+
+ da = tgsi_default_declaration_array();
+ da.ArrayID = arrayid;
+
+ declaration_grow(declaration, header);
+
+ return da;
+}
+
struct tgsi_full_declaration
tgsi_default_full_declaration( void )
{
@@ -379,6 +395,7 @@ tgsi_build_full_declaration(
full_decl-Declaration.Semantic,
full_decl-Declaration.Invariant,
full_decl-Declaration.Local,
+ full_decl-Declaration.Array,
header );
if (maxsize = size)
@@ -472,6 +489,19 @@ tgsi_build_full_declaration(
header);
}
+ if (full_decl-Declaration.Array) {
+ struct tgsi_declaration_array *da;
+
+ if (maxsize = size) {
+ return 0;
+ }
+ da = (struct tgsi_declaration_array *)tokens[size];
+ size++;
+ *da = tgsi_build_declaration_array(
+ full_decl-Array.ArrayID,
+ declaration,
+ header);
+ }
return size;
}
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Mesa (master): clover: Don' t use PIPE_TRANSFER_UNSYNCHRONIZED for blocking copies
Module: Mesa
Branch: master
Commit: f3e86d4a68c27f0e86d64a98469a48756c445498
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f3e86d4a68c27f0e86d64a98469a48756c445498
Author: Tom Stellard thomas.stell...@amd.com
Date: Mon Aug 26 17:52:47 2013 -0700
clover: Don't use PIPE_TRANSFER_UNSYNCHRONIZED for blocking copies
CC: 9.2 mesa-sta...@lists.freedesktop.org
Reviewed-by: Francisco Jerez curroje...@riseup.net
---
.../state_trackers/clover/core/resource.cpp|2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/gallium/state_trackers/clover/core/resource.cpp
b/src/gallium/state_trackers/clover/core/resource.cpp
index 6d348e6..3b003e9 100644
--- a/src/gallium/state_trackers/clover/core/resource.cpp
+++ b/src/gallium/state_trackers/clover/core/resource.cpp
@@ -174,7 +174,7 @@ mapping::mapping(command_queue q, resource r,
pctx(q.pipe) {
unsigned usage = ((flags CL_MAP_WRITE ? PIPE_TRANSFER_WRITE : 0 ) |
(flags CL_MAP_READ ? PIPE_TRANSFER_READ : 0 ) |
- (blocking ? PIPE_TRANSFER_UNSYNCHRONIZED : 0));
+ (!blocking ? PIPE_TRANSFER_UNSYNCHRONIZED : 0));
p = pctx-transfer_map(pctx, r.pipe, 0, usage,
box(origin + r.offset, region), pxfer);
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Mesa (master): st/clover: Profiling support
Module: Mesa
Branch: master
Commit: 4a3505d5487fbdab773f5c91edd39e8aea6e90af
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a3505d5487fbdab773f5c91edd39e8aea6e90af
Author: Niels Ole Salscheider niels_...@salscheider-online.de
Date: Fri Aug 9 11:59:25 2013 +0200
st/clover: Profiling support
Signed-off-by: Niels Ole Salscheider niels_...@salscheider-online.de
Acked-by: Francisco Jerez curroje...@riseup.net
---
src/gallium/state_trackers/clover/api/event.cpp | 26 +-
src/gallium/state_trackers/clover/core/event.cpp | 116 +++---
src/gallium/state_trackers/clover/core/event.hpp | 18 +++-
3 files changed, 142 insertions(+), 18 deletions(-)
diff --git a/src/gallium/state_trackers/clover/api/event.cpp
b/src/gallium/state_trackers/clover/api/event.cpp
index 39a647b..ea1576c 100644
--- a/src/gallium/state_trackers/clover/api/event.cpp
+++ b/src/gallium/state_trackers/clover/api/event.cpp
@@ -217,7 +217,31 @@ clEnqueueWaitForEvents(cl_command_queue q, cl_uint num_evs,
PUBLIC cl_int
clGetEventProfilingInfo(cl_event ev, cl_profiling_info param,
size_t size, void *buf, size_t *size_ret) {
- return CL_PROFILING_INFO_NOT_AVAILABLE;
+ hard_event *hev = dynamic_casthard_event *(ev);
+ soft_event *sev = dynamic_castsoft_event *(ev);
+
+ if (!hev !sev)
+ return CL_INVALID_EVENT;
+ if (!hev || !(hev-queue()-props() CL_QUEUE_PROFILING_ENABLE) ||
+ hev-status() != CL_COMPLETE)
+ return CL_PROFILING_INFO_NOT_AVAILABLE;
+
+ switch (param) {
+ case CL_PROFILING_COMMAND_QUEUED:
+ return scalar_propertycl_ulong(buf, size, size_ret, hev-ts_queued());
+
+ case CL_PROFILING_COMMAND_SUBMIT:
+ return scalar_propertycl_ulong(buf, size, size_ret, hev-ts_submit());
+
+ case CL_PROFILING_COMMAND_START:
+ return scalar_propertycl_ulong(buf, size, size_ret, hev-ts_start());
+
+ case CL_PROFILING_COMMAND_END:
+ return scalar_propertycl_ulong(buf, size, size_ret, hev-ts_end());
+
+ default:
+ return CL_INVALID_VALUE;
+ }
}
PUBLIC cl_int
diff --git a/src/gallium/state_trackers/clover/core/event.cpp
b/src/gallium/state_trackers/clover/core/event.cpp
index 93d3b58..de21f0c 100644
--- a/src/gallium/state_trackers/clover/core/event.cpp
+++ b/src/gallium/state_trackers/clover/core/event.cpp
@@ -38,18 +38,6 @@ _cl_event::~_cl_event() {
}
void
-_cl_event::trigger() {
- if (!--wait_count) {
- action_ok(*this);
-
- while (!__chain.empty()) {
- __chain.back()-trigger();
- __chain.pop_back();
- }
- }
-}
-
-void
_cl_event::abort(cl_int status) {
__status = status;
action_fail(*this);
@@ -77,14 +65,61 @@ _cl_event::chain(clover::event *ev) {
hard_event::hard_event(clover::command_queue q, cl_command_type command,
std::vectorclover::event * deps, action action) :
_cl_event(q.ctx, deps, action, [](event ev){}),
- __queue(q), __command(command), __fence(NULL) {
+ __queue(q), __command(command), __fence(NULL),
+ __query_start(NULL), __query_end(NULL) {
q.sequence(this);
+
+ if(q.props() CL_QUEUE_PROFILING_ENABLE) {
+ pipe_screen *screen = q.dev.pipe;
+ __ts_queued = screen-get_timestamp(screen);
+ }
+
trigger();
}
hard_event::~hard_event() {
pipe_screen *screen = queue()-dev.pipe;
+ pipe_context *pipe = queue()-pipe;
screen-fence_reference(screen, __fence, NULL);
+
+ if(__query_start) {
+ pipe-destroy_query(pipe, __query_start);
+ __query_start = 0;
+ }
+
+ if(__query_end) {
+ pipe-destroy_query(pipe, __query_end);
+ __query_end = 0;
+ }
+}
+
+void
+hard_event::trigger() {
+ if (!--wait_count) {
+ /* XXX: Currently, a timestamp query gives wrong results for memory
+* transfers. This is, because we use memcpy instead of the DMA engines. */
+
+ if(queue()-props() CL_QUEUE_PROFILING_ENABLE) {
+ pipe_context *pipe = queue()-pipe;
+ __query_start = pipe-create_query(pipe, PIPE_QUERY_TIMESTAMP);
+ pipe-end_query(queue()-pipe, __query_start);
+ }
+
+ action_ok(*this);
+
+ if(queue()-props() CL_QUEUE_PROFILING_ENABLE) {
+ pipe_context *pipe = queue()-pipe;
+ pipe_screen *screen = queue()-dev.pipe;
+ __query_end = pipe-create_query(pipe, PIPE_QUERY_TIMESTAMP);
+ pipe-end_query(pipe, __query_end);
+ __ts_submit = screen-get_timestamp(screen);
+ }
+
+ while (!__chain.empty()) {
+ __chain.back()-trigger();
+ __chain.pop_back();
+ }
+ }
}
cl_int
@@ -126,6 +161,49 @@ hard_event::wait() const {
throw error(CL_EXEC_STATUS_ERROR_FOR_EVENTS_IN_WAIT_LIST);
}
+cl_ulong
+hard_event::ts_queued() const {
+ return __ts_queued;
+}
+
+cl_ulong
+hard_event::ts_submit() const {
+ return __ts_submit;
+}
+
+cl_ulong
+hard_event::ts_start() {
+ get_query_results();
+ return __ts_start;
+}
+
+cl_ulong
+hard_event::ts_end() {
+ get_query_results();
+
Mesa (master): st/clover: Add event to deps even if it has been triggered
Module: Mesa
Branch: master
Commit: ef6ed7220af51d7ae2ee132829f46a8b08d9796b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef6ed7220af51d7ae2ee132829f46a8b08d9796b
Author: Niels Ole Salscheider niels_...@salscheider-online.de
Date: Fri Aug 9 11:59:26 2013 +0200
st/clover: Add event to deps even if it has been triggered
The command is submitted once the event has been triggered, but it might not
have completed yet. Therefore, we have to add it to deps in order to wait on it.
Signed-off-by: Niels Ole Salscheider niels_...@salscheider-online.de
Reviewed-by: Francisco Jerez curroje...@riseup.net
---
src/gallium/state_trackers/clover/core/event.cpp |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/gallium/state_trackers/clover/core/event.cpp
b/src/gallium/state_trackers/clover/core/event.cpp
index de21f0c..cbb97bf 100644
--- a/src/gallium/state_trackers/clover/core/event.cpp
+++ b/src/gallium/state_trackers/clover/core/event.cpp
@@ -58,8 +58,8 @@ _cl_event::chain(clover::event *ev) {
if (wait_count) {
ev-wait_count++;
__chain.push_back(ev);
- ev-deps.push_back(this);
}
+ ev-deps.push_back(this);
}
hard_event::hard_event(clover::command_queue q, cl_command_type command,
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Mesa (master): i915: Optimize SEQ and SNE when two operands are uniforms
Module: Mesa
Branch: master
Commit: d127a0343d7a1ab44bbdf6b4f664daebe6b297d8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d127a0343d7a1ab44bbdf6b4f664daebe6b297d8
Author: Ian Romanick ian.d.roman...@intel.com
Date: Wed Aug 21 19:37:30 2013 -0700
i915: Optimize SEQ and SNE when two operands are uniforms
SEQ and SNE are not native i915 instructions, so they each generate at
least 3 instructions. If both operands are uniforms or constants, we
get 5 instructions like:
U[1] = MOV CONST[1]
U[0].xyz = SGE CONST[0]., U[1]
U[1] = MOV CONST[1].-x-y-z-w
R[0].xyz = SGE CONST[0].-x-x-x-x, U[1]
R[0].xyz = MUL R[0], U[0]
This code is stupid. Instead of having the individual calls to
i915_emit_arith generate the moves to utemps, do it in the caller. This
results in code like:
U[1] = MOV CONST[1]
U[0].xyz = SGE CONST[0]., U[1]
R[0].xyz = SGE CONST[0].-x-x-x-x, U[1].-x-y-z-w
R[0].xyz = MUL R[0], U[0]
This allows fs-temp-array-mat2-index-col-wr and
fs-temp-array-mat2-index-row-wr to fit in hardware limits (instead of
falling back to software rasterization).
NOTE: Without pending patches to the piglit tests, these tests will now
fail. This is an unrelated, pre-existing issue.
v2: Copy most of the body of the commit message into comments in the
code. Suggested by Eric.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/dri/i915/i915_fragprog.c | 82
1 files changed, 70 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c
b/src/mesa/drivers/dri/i915/i915_fragprog.c
index 930c2b8..67eff76 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -817,23 +817,52 @@ upload_program(struct i915_fragment_program *p)
flags = get_result_flags(inst);
dst = get_result_vector(p, inst);
+ /* If both operands are uniforms or constants, we get 5 instructions
+ * like:
+ *
+ * U[1] = MOV CONST[1]
+ * U[0].xyz = SGE CONST[0]., U[1]
+ * U[1] = MOV CONST[1].-x-y-z-w
+ * R[0].xyz = SGE CONST[0].-x-x-x-x, U[1]
+ * R[0].xyz = MUL R[0], U[0]
+ *
+ * This code is stupid. Instead of having the individual calls to
+ * i915_emit_arith generate the moves to utemps, do it in the caller.
+ * This results in code like:
+ *
+ * U[1] = MOV CONST[1]
+ * U[0].xyz = SGE CONST[0]., U[1]
+ * R[0].xyz = SGE CONST[0].-x-x-x-x, U[1].-x-y-z-w
+ * R[0].xyz = MUL R[0], U[0]
+ */
+ src0 = src_vector(p, inst-SrcReg[0], program);
+ src1 = src_vector(p, inst-SrcReg[1], program);
+
+ if (GET_UREG_TYPE(src0) == REG_TYPE_CONST
+ GET_UREG_TYPE(src1) == REG_TYPE_CONST) {
+unsigned tmp = i915_get_utemp(p);
+
+i915_emit_arith(p, A0_MOV, tmp, A0_DEST_CHANNEL_ALL, 0,
+src1, 0, 0);
+
+src1 = tmp;
+ }
+
/* tmp = src1 = src2 */
i915_emit_arith(p,
A0_SGE,
tmp,
flags, 0,
-src_vector(p, inst-SrcReg[0], program),
-src_vector(p, inst-SrcReg[1], program),
+src0,
+src1,
0);
/* dst = src1 = src2 */
i915_emit_arith(p,
A0_SGE,
dst,
flags, 0,
-negate(src_vector(p, inst-SrcReg[0], program),
- 1, 1, 1, 1),
-negate(src_vector(p, inst-SrcReg[1], program),
- 1, 1, 1, 1),
+negate(src0, 1, 1, 1, 1),
+negate(src1, 1, 1, 1, 1),
0);
/* dst = tmp dst */
i915_emit_arith(p,
@@ -966,23 +995,52 @@ upload_program(struct i915_fragment_program *p)
flags = get_result_flags(inst);
dst = get_result_vector(p, inst);
+ /* If both operands are uniforms or constants, we get 5 instructions
+ * like:
+ *
+ * U[1] = MOV CONST[1]
+ * U[0].xyz = SLT CONST[0]., U[1]
+ * U[1] = MOV CONST[1].-x-y-z-w
+ * R[0].xyz = SLT CONST[0].-x-x-x-x, U[1]
+ * R[0].xyz = MUL R[0], U[0]
+ *
+ * This code is stupid. Instead of having the individual calls to
+ * i915_emit_arith generate the moves to utemps, do it in the caller.
+ * This results in code like:
+ *
+ * U[1] = MOV CONST[1]
+
Mesa (master): Fixed and/or order mistake, resulting in compiling llvmpipe without llvm installed
Module: Mesa Branch: master Commit: cec7b5c5bc300d4a415939bc6a913d441c687e47 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cec7b5c5bc300d4a415939bc6a913d441c687e47 Author: Kristian Lehmann em...@zero-io.net Date: Mon Aug 26 21:19:50 2013 +0200 Fixed and/or order mistake, resulting in compiling llvmpipe without llvm installed Cc: 9.2 mesa-sta...@lists.freedesktop.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68544 Reviewed-by: Matt Turner matts...@gmail.com --- configure.ac |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configure.ac b/configure.ac index 40e052c..e20a228 100644 --- a/configure.ac +++ b/configure.ac @@ -1925,8 +1925,8 @@ AM_CONDITIONAL(NEED_GALLIUM_SOFTPIPE_DRIVER, test x$HAVE_GALLIUM_SVGA = xyes - x$HAVE_GALLIUM_I915 = xyes -o \ x$HAVE_GALLIUM_SOFTPIPE = xyes) AM_CONDITIONAL(NEED_GALLIUM_LLVMPIPE_DRIVER, test x$HAVE_GALLIUM_I915 = xyes -o \ - x$HAVE_GALLIUM_SOFTPIPE = xyes -a \ - x$MESA_LLVM = x1) + x$HAVE_GALLIUM_SOFTPIPE = xyes \ + test x$MESA_LLVM = x1) if test x$enable_gallium_loader = xyes; then GALLIUM_WINSYS_DIRS=$GALLIUM_WINSYS_DIRS sw/null ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (9.2): clover: Don' t use PIPE_TRANSFER_UNSYNCHRONIZED for blocking copies
Module: Mesa
Branch: 9.2
Commit: 1a9bda1f3467fb01c598ed2216064801f5a2cf0f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a9bda1f3467fb01c598ed2216064801f5a2cf0f
Author: Tom Stellard thomas.stell...@amd.com
Date: Mon Aug 26 17:52:47 2013 -0700
clover: Don't use PIPE_TRANSFER_UNSYNCHRONIZED for blocking copies
CC: 9.2 mesa-sta...@lists.freedesktop.org
Reviewed-by: Francisco Jerez curroje...@riseup.net
(cherry picked from commit f3e86d4a68c27f0e86d64a98469a48756c445498)
---
.../state_trackers/clover/core/resource.cpp|2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/gallium/state_trackers/clover/core/resource.cpp
b/src/gallium/state_trackers/clover/core/resource.cpp
index 6d348e6..3b003e9 100644
--- a/src/gallium/state_trackers/clover/core/resource.cpp
+++ b/src/gallium/state_trackers/clover/core/resource.cpp
@@ -174,7 +174,7 @@ mapping::mapping(command_queue q, resource r,
pctx(q.pipe) {
unsigned usage = ((flags CL_MAP_WRITE ? PIPE_TRANSFER_WRITE : 0 ) |
(flags CL_MAP_READ ? PIPE_TRANSFER_READ : 0 ) |
- (blocking ? PIPE_TRANSFER_UNSYNCHRONIZED : 0));
+ (!blocking ? PIPE_TRANSFER_UNSYNCHRONIZED : 0));
p = pctx-transfer_map(pctx, r.pipe, 0, usage,
box(origin + r.offset, region), pxfer);
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Mesa (9.2): Fixed and/or order mistake, resulting in compiling llvmpipe without llvm installed
Module: Mesa Branch: 9.2 Commit: c0abf6499f416ff65005cbe5393c4601de5b6633 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0abf6499f416ff65005cbe5393c4601de5b6633 Author: Kristian Lehmann em...@zero-io.net Date: Mon Aug 26 21:19:50 2013 +0200 Fixed and/or order mistake, resulting in compiling llvmpipe without llvm installed Cc: 9.2 mesa-sta...@lists.freedesktop.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=68544 Reviewed-by: Matt Turner matts...@gmail.com (cherry picked from commit cec7b5c5bc300d4a415939bc6a913d441c687e47) --- configure.ac |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/configure.ac b/configure.ac index d42afba..11a711f 100644 --- a/configure.ac +++ b/configure.ac @@ -1925,8 +1925,8 @@ AM_CONDITIONAL(NEED_GALLIUM_SOFTPIPE_DRIVER, test x$HAVE_GALLIUM_SVGA = xyes - x$HAVE_GALLIUM_I915 = xyes -o \ x$HAVE_GALLIUM_SOFTPIPE = xyes) AM_CONDITIONAL(NEED_GALLIUM_LLVMPIPE_DRIVER, test x$HAVE_GALLIUM_I915 = xyes -o \ - x$HAVE_GALLIUM_SOFTPIPE = xyes -a \ - x$MESA_LLVM = x1) + x$HAVE_GALLIUM_SOFTPIPE = xyes \ + test x$MESA_LLVM = x1) if test x$enable_gallium_loader = xyes; then GALLIUM_WINSYS_DIRS=$GALLIUM_WINSYS_DIRS sw/null ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
