Mesa (master): freedreno/ir3: add debug flag to disable cp
Module: Mesa
Branch: master
Commit: 4f17e026bb99c173444ff5ca7d0b782ed89ee604
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f17e026bb99c173444ff5ca7d0b782ed89ee604
Author: Rob Clark robcl...@freedesktop.org
Date: Sun Oct 19 14:55:32 2014 -0400
freedreno/ir3: add debug flag to disable cp
FD_MESA_DEBUG=nocp will disable copy propagation pass.
Signed-off-by: Rob Clark robcl...@freedesktop.org
---
src/gallium/drivers/freedreno/freedreno_screen.c |1 +
src/gallium/drivers/freedreno/freedreno_util.h |1 +
src/gallium/drivers/freedreno/ir3/ir3_cmdline.c |7 +++
src/gallium/drivers/freedreno/ir3/ir3_compiler.c |2 +-
4 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c
b/src/gallium/drivers/freedreno/freedreno_screen.c
index bc6ff78..ddc7302 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -70,6 +70,7 @@ static const struct debug_named_value debug_options[] = {
{optmsgs, FD_DBG_OPTMSGS,Enable optimizater debug
messages},
{optdump, FD_DBG_OPTDUMP,Dump shader DAG to .dot files},
{glsl130, FD_DBG_GLSL130,Temporary flag to enable GLSL 130
on a3xx+},
+ {nocp, FD_DBG_NOCP, Disable copy-propagation},
DEBUG_NAMED_VALUE_END
};
diff --git a/src/gallium/drivers/freedreno/freedreno_util.h
b/src/gallium/drivers/freedreno/freedreno_util.h
index f1a1e6e..36a5995 100644
--- a/src/gallium/drivers/freedreno/freedreno_util.h
+++ b/src/gallium/drivers/freedreno/freedreno_util.h
@@ -66,6 +66,7 @@ enum adreno_stencil_op fd_stencil_op(unsigned op);
#define FD_DBG_OPTMSGS 0x0400
#define FD_DBG_OPTDUMP 0x0800
#define FD_DBG_GLSL130 0x1000
+#define FD_DBG_NOCP 0x2000
extern int fd_mesa_debug;
extern bool fd_binning_enabled;
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
index 86239b4..652ec16 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_cmdline.c
@@ -133,6 +133,7 @@ static void print_usage(void)
printf(--saturate-s MASK - bitmask of samplers to saturate S
coord\n);
printf(--saturate-t MASK - bitmask of samplers to saturate T
coord\n);
printf(--saturate-r MASK - bitmask of samplers to saturate R
coord\n);
+ printf(--nocp- disable copy propagation\n);
printf(--help- show this message\n);
}
@@ -199,6 +200,12 @@ int main(int argc, char **argv)
continue;
}
+ if (!strcmp(argv[n], --nocp)) {
+ fd_mesa_debug |= FD_DBG_NOCP;
+ n++;
+ continue;
+ }
+
if (!strcmp(argv[n], --help)) {
print_usage();
return 0;
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
index dc4f985..233f174 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
@@ -3175,7 +3175,7 @@ ir3_compile_shader(struct ir3_shader_variant *so,
ir3_dump_instr_list(block-head);
}
- if (cp)
+ if (cp !(fd_mesa_debug FD_DBG_NOCP))
ir3_block_cp(block);
if (fd_mesa_debug FD_DBG_OPTDUMP)
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Mesa (master): freedreno/a3xx: disable early-z when we have kill's
Module: Mesa
Branch: master
Commit: 3fcb0212018e52c374f937e806abeca07e938d28
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3fcb0212018e52c374f937e806abeca07e938d28
Author: Rob Clark robcl...@freedesktop.org
Date: Sat Oct 18 16:52:44 2014 -0400
freedreno/a3xx: disable early-z when we have kill's
Signed-off-by: Rob Clark robcl...@freedesktop.org
---
src/gallium/drivers/freedreno/a3xx/fd3_emit.c|3 +++
src/gallium/drivers/freedreno/ir3/ir3_compiler.c |4
src/gallium/drivers/freedreno/ir3/ir3_shader.h |3 +++
3 files changed, 10 insertions(+)
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
index 8300a55..5bf41b1 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
@@ -454,6 +454,9 @@ fd3_emit_state(struct fd_context *ctx, struct fd_ringbuffer
*ring,
val |= A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z;
val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
}
+ if (fp-has_kill) {
+ val |= A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE;
+ }
OUT_PKT0(ring, REG_A3XX_RB_DEPTH_CONTROL, 1);
OUT_RING(ring, val);
}
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
index 8c4ec88..dc4f985 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
@@ -2047,6 +2047,8 @@ trans_kill(const struct instr_translater *t,
ir3_reg_create(instr, 0, IR3_REG_SSA)-instr = cond;
ctx-kill[ctx-kill_count++] = instr;
+
+ ctx-so-has_kill = true;
}
/*
@@ -2081,6 +2083,8 @@ trans_killif(const struct instr_translater *t,
ctx-kill[ctx-kill_count++] = instr;
+ ctx-so-has_kill = true;
+
}
/*
* I2F / U2F / F2I / F2U
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_shader.h
b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
index 628c09e..a26dab2 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_shader.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3_shader.h
@@ -171,6 +171,9 @@ struct ir3_shader_variant {
/* do we have one or more texture sample instructions: */
bool has_samp;
+ /* do we have kill instructions: */
+ bool has_kill;
+
/* const reg # of first immediate, ie. 1 == c1
* (not regid, because TGSI thinks in terms of vec4 registers,
* not scalar registers)
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Mesa (master): freedreno/a3xx: more layer/level fixes
Module: Mesa
Branch: master
Commit: 74069e324e559a9361ebe631d1b819ff6e675c8f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=74069e324e559a9361ebe631d1b819ff6e675c8f
Author: Rob Clark robcl...@freedesktop.org
Date: Wed Oct 15 17:15:06 2014 -0400
freedreno/a3xx: more layer/level fixes
Signed-off-by: Rob Clark robcl...@freedesktop.org
---
src/gallium/drivers/freedreno/a3xx/fd3_emit.c |9 +++--
src/gallium/drivers/freedreno/a3xx/fd3_gmem.c |7 +--
src/gallium/drivers/freedreno/freedreno_resource.c |6 ++
3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
index 050530e..0439dc7 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
@@ -282,8 +282,13 @@ void
fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring, struct pipe_surface
*psurf)
{
struct fd_resource *rsc = fd_resource(psurf-texture);
+ unsigned lvl = psurf-u.tex.level;
+ struct fd_resource_slice *slice = rsc-slices[lvl];
+ uint32_t layer_offset = slice-size0 * psurf-u.tex.first_layer;
enum pipe_format format = fd3_gmem_restore_format(psurf-format);
+ debug_assert(psurf-u.tex.first_layer == psurf-u.tex.last_layer);
+
/* output sampler state: */
OUT_PKT3(ring, CP_LOAD_STATE, 4);
OUT_RING(ring, CP_LOAD_STATE_0_DST_OFF(FRAG_TEX_OFF) |
@@ -314,7 +319,7 @@ fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
struct pipe_surface *psurf
OUT_RING(ring, A3XX_TEX_CONST_1_FETCHSIZE(TFETCH_DISABLE) |
A3XX_TEX_CONST_1_WIDTH(psurf-width) |
A3XX_TEX_CONST_1_HEIGHT(psurf-height));
- OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(rsc-slices[0].pitch * rsc-cpp) |
+ OUT_RING(ring, A3XX_TEX_CONST_2_PITCH(slice-pitch * rsc-cpp) |
A3XX_TEX_CONST_2_INDX(0));
OUT_RING(ring, 0x);
@@ -326,7 +331,7 @@ fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
struct pipe_surface *psurf
CP_LOAD_STATE_0_NUM_UNIT(1));
OUT_RING(ring, CP_LOAD_STATE_1_STATE_TYPE(ST_CONSTANTS) |
CP_LOAD_STATE_1_EXT_SRC_ADDR(0));
- OUT_RELOC(ring, rsc-bo, 0, 0, 0);
+ OUT_RELOC(ring, rsc-bo, layer_offset, 0, 0);
}
void
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
index 219c9e0..2eefa91 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
@@ -609,8 +609,11 @@ fd3_emit_sysmem_prep(struct fd_context *ctx)
struct fd_ringbuffer *ring = ctx-ring;
uint32_t pitch = 0;
- if (pfb-cbufs[0])
- pitch = fd_resource(pfb-cbufs[0]-texture)-slices[0].pitch;
+ if (pfb-cbufs[0]) {
+ struct pipe_surface *psurf = pfb-cbufs[0];
+ unsigned lvl = psurf-u.tex.level;
+ pitch = fd_resource(psurf-texture)-slices[lvl].pitch;
+ }
fd3_emit_restore(ctx);
diff --git a/src/gallium/drivers/freedreno/freedreno_resource.c
b/src/gallium/drivers/freedreno/freedreno_resource.c
index b6b39f0..49ae517 100644
--- a/src/gallium/drivers/freedreno/freedreno_resource.c
+++ b/src/gallium/drivers/freedreno/freedreno_resource.c
@@ -199,9 +199,8 @@ setup_slices(struct fd_resource *rsc)
for (level = 0; level = prsc-last_level; level++) {
struct fd_resource_slice *slice = fd_resource_slice(rsc, level);
- uint32_t aligned_width = align(width, 32);
- slice-pitch = aligned_width;
+ slice-pitch = align(width, 32);
slice-offset = size;
slice-size0 = slice-pitch * height * rsc-cpp;
@@ -229,9 +228,8 @@ setup_slices_array(struct fd_resource *rsc)
for (level = 0; level = prsc-last_level; level++) {
struct fd_resource_slice *slice = fd_resource_slice(rsc, level);
- uint32_t aligned_width = align(width, 32);
- slice-pitch = aligned_width;
+ slice-pitch = align(width, 32);
slice-offset = size;
slice-size0 = align(slice-pitch * height * rsc-cpp, 4096);
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Mesa (master): freedreno/a3xx: only emit dirty consts
Module: Mesa Branch: master Commit: 94bb33617d1e8978dc52b8aaa4eb41bfb6703f79 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=94bb33617d1e8978dc52b8aaa4eb41bfb6703f79 Author: Rob Clark robcl...@freedesktop.org Date: Fri Oct 17 08:57:16 2014 -0400 freedreno/a3xx: only emit dirty consts If app only updates (for example) vertex uniforms, it would be nice to only re-emit those and not also frag uniforms. Means we need to mark the first frag shader const buffer dirty after a clear. Signed-off-by: Rob Clark robcl...@freedesktop.org --- src/gallium/drivers/freedreno/a3xx/fd3_draw.c | 10 +- src/gallium/drivers/freedreno/a3xx/fd3_emit.c |4 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_draw.c b/src/gallium/drivers/freedreno/a3xx/fd3_draw.c index 7cc24e5..e168d97 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_draw.c +++ b/src/gallium/drivers/freedreno/a3xx/fd3_draw.c @@ -136,14 +136,21 @@ fd3_draw(struct fd_context *ctx, const struct pipe_draw_info *info) }, .rasterflat = ctx-rasterizer ctx-rasterizer-flatshade, }; - unsigned dirty; + uint32_t dirty, vconst; fixup_shader_state(ctx, emit.key); + /* save/restore vertex const state too, so that vertex +* shader consts also get emitted for render pass: +*/ + vconst = ctx-constbuf[PIPE_SHADER_VERTEX].dirty_mask; + dirty = ctx-dirty; emit.dirty = dirty ~(FD_DIRTY_BLEND); draw_impl(ctx, ctx-binning_ring, emit); + ctx-constbuf[PIPE_SHADER_VERTEX].dirty_mask = vconst; + /* and now regular (non-binning) pass: */ emit.key.binning_pass = false; emit.dirty = dirty; @@ -312,6 +319,7 @@ fd3_clear(struct fd_context *ctx, unsigned buffers, fd3_emit_vertex_bufs(ring, emit); + ctx-constbuf[PIPE_SHADER_FRAGMENT].dirty_mask = ~0; fd3_emit_constant(ring, SB_FRAG_SHADER, 0, 0, 4, color-ui, NULL); OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1); diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c index 0439dc7..8300a55 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c +++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c @@ -93,10 +93,6 @@ emit_constants(struct fd_ringbuffer *ring, uint32_t first_immediate; uint32_t base = 0; - // XXX TODO only emit dirty consts.. but we need to keep track if - // they are clobbered by a clear, gmem2mem, or mem2gmem.. - constbuf-dirty_mask = enabled_mask; - /* in particular, with binning shader we may end up with unused * consts, ie. we could end up w/ constlen that is smaller * than first_immediate. In that case truncate the user consts ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): freedreno/ir3: comment + better fxn name
Module: Mesa
Branch: master
Commit: ab33a240890a7ef147d4b8cf35c27ae1932a1dbe
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ab33a240890a7ef147d4b8cf35c27ae1932a1dbe
Author: Rob Clark robcl...@freedesktop.org
Date: Sat Oct 18 14:46:35 2014 -0400
freedreno/ir3: comment + better fxn name
Signed-off-by: Rob Clark robcl...@freedesktop.org
---
src/gallium/drivers/freedreno/ir3/ir3_sched.c |8 +---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_sched.c
b/src/gallium/drivers/freedreno/ir3/ir3_sched.c
index cf09cea..24d7c63 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_sched.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_sched.c
@@ -162,7 +162,8 @@ static void schedule(struct ir3_sched_ctx *ctx,
* Delay-slot calculation. Follows fanin/fanout.
*/
-static unsigned delay_calc2(struct ir3_sched_ctx *ctx,
+/* calculate delay for specified src: */
+static unsigned delay_calc_srcn(struct ir3_sched_ctx *ctx,
struct ir3_instruction *assigner,
struct ir3_instruction *consumer, unsigned srcn)
{
@@ -173,7 +174,7 @@ static unsigned delay_calc2(struct ir3_sched_ctx *ctx,
for (i = 1; i assigner-regs_count; i++) {
struct ir3_register *reg = assigner-regs[i];
if (reg-flags IR3_REG_SSA) {
- unsigned d = delay_calc2(ctx, reg-instr,
+ unsigned d = delay_calc_srcn(ctx, reg-instr,
consumer, srcn);
delay = MAX2(delay, d);
}
@@ -186,6 +187,7 @@ static unsigned delay_calc2(struct ir3_sched_ctx *ctx,
return delay;
}
+/* calculate delay for instruction (maximum of delay for all srcs): */
static unsigned delay_calc(struct ir3_sched_ctx *ctx,
struct ir3_instruction *instr)
{
@@ -194,7 +196,7 @@ static unsigned delay_calc(struct ir3_sched_ctx *ctx,
for (i = 1; i instr-regs_count; i++) {
struct ir3_register *reg = instr-regs[i];
if (reg-flags IR3_REG_SSA) {
- unsigned d = delay_calc2(ctx, reg-instr,
+ unsigned d = delay_calc_srcn(ctx, reg-instr,
instr, i - 1);
delay = MAX2(delay, d);
}
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Mesa (master): freedreno: positions come out as integers, not half-integers
Module: Mesa Branch: master Commit: f0ca26725e48e6d85a9e2749caaf122e7bb8d6e6 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0ca26725e48e6d85a9e2749caaf122e7bb8d6e6 Author: Ilia Mirkin imir...@alum.mit.edu Date: Fri Oct 3 16:23:19 2014 -0400 freedreno: positions come out as integers, not half-integers Signed-off-by: Ilia Mirkin imir...@alum.mit.edu Signed-off-by: Rob Clark robcl...@freedesktop.org --- src/gallium/drivers/freedreno/freedreno_screen.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 24f360b..bc6ff78 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -161,7 +161,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: - case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: + case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: case PIPE_CAP_SEAMLESS_CUBE_MAP: case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION: @@ -205,7 +205,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_DEPTH_CLIP_DISABLE: case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE: case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT: - case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER: + case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS: case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: case PIPE_CAP_VERTEX_COLOR_CLAMPED: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): freedreno/ir3: fix potential gpu lockup with kill
Module: Mesa
Branch: master
Commit: 8a0ffedd8de51eaf980855283c4525dba6dc5847
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a0ffedd8de51eaf980855283c4525dba6dc5847
Author: Rob Clark robcl...@freedesktop.org
Date: Sat Oct 18 15:28:16 2014 -0400
freedreno/ir3: fix potential gpu lockup with kill
It seems like the hardware is unhappy if we execute a kill instruction
prior to last input (ei). Probably the shader thread stops executing
and the end-input flag is never set.
Signed-off-by: Rob Clark robcl...@freedesktop.org
---
src/gallium/drivers/freedreno/ir3/ir3.c | 11 +++
src/gallium/drivers/freedreno/ir3/ir3.h | 10 ++
src/gallium/drivers/freedreno/ir3/ir3_depth.c | 16 +--
src/gallium/drivers/freedreno/ir3/ir3_sched.c | 26 +
4 files changed, 61 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/freedreno/ir3/ir3.c
b/src/gallium/drivers/freedreno/ir3/ir3.c
index 70d37ff..60d4e4a 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3.c
@@ -81,6 +81,8 @@ void ir3_destroy(struct ir3 *shader)
shader-chunk = chunk-next;
free(chunk);
}
+ free(shader-instrs);
+ free(shader-baryfs);
free(shader);
}
@@ -596,6 +598,15 @@ static void insert_instr(struct ir3 *shader,
shader-instrs_sz * sizeof(shader-instrs[0]));
}
shader-instrs[shader-instrs_count++] = instr;
+
+ if (is_input(instr)) {
+ if (shader-baryfs_count == shader-baryfs_sz) {
+ shader-baryfs_sz = MAX2(2 * shader-baryfs_sz, 16);
+ shader-baryfs = realloc(shader-baryfs,
+ shader-baryfs_sz *
sizeof(shader-baryfs[0]));
+ }
+ shader-baryfs[shader-baryfs_count++] = instr;
+ }
}
struct ir3_block * ir3_block_create(struct ir3 *shader,
diff --git a/src/gallium/drivers/freedreno/ir3/ir3.h
b/src/gallium/drivers/freedreno/ir3/ir3.h
index d2d3dca..21992f6 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3.h
+++ b/src/gallium/drivers/freedreno/ir3/ir3.h
@@ -210,7 +210,11 @@ struct ir3_instruction {
* result of moving a const to a reg would have a low cost, so
to
* it could make sense to duplicate the instruction at various
* points where the result is needed to reduce register
footprint.
+*
+* DEPTH_UNUSED used to mark unused instructions after depth
+* calculation pass.
*/
+#define DEPTH_UNUSED ~0
unsigned depth;
};
struct ir3_instruction *next;
@@ -224,6 +228,8 @@ struct ir3_heap_chunk;
struct ir3 {
unsigned instrs_count, instrs_sz;
struct ir3_instruction **instrs;
+ unsigned baryfs_count, baryfs_sz;
+ struct ir3_instruction **baryfs;
unsigned heap_idx;
struct ir3_heap_chunk *chunk;
};
@@ -272,6 +278,10 @@ static inline void ir3_clear_mark(struct ir3 *shader)
/* TODO would be nice to drop the instruction array.. for
* new compiler, _clear_mark() is all we use it for, and
* we could probably manage a linked list instead..
+*
+* Also, we'll probably want to mark instructions within
+* a block, so tracking the list of instrs globally is
+* unlikely to be what we want.
*/
unsigned i;
for (i = 0; i shader-instrs_count; i++) {
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_depth.c
b/src/gallium/drivers/freedreno/ir3/ir3_depth.c
index dcc0362..76413d4 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_depth.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_depth.c
@@ -150,10 +150,22 @@ void ir3_block_depth(struct ir3_block *block)
if (block-outputs[i])
ir3_instr_depth(block-outputs[i]);
- /* at this point, any unvisited input is unused: */
+ /* mark un-used instructions: */
+ for (i = 0; i block-shader-instrs_count; i++) {
+ struct ir3_instruction *instr = block-shader-instrs[i];
+
+ /* just consider instructions within this block: */
+ if (instr-block != block)
+ continue;
+
+ if (!ir3_instr_check_mark(instr))
+ instr-depth = DEPTH_UNUSED;
+ }
+
+ /* cleanup unused inputs: */
for (i = 0; i block-ninputs; i++) {
struct ir3_instruction *in = block-inputs[i];
- if (in !ir3_instr_check_mark(in))
+ if (in (in-depth == DEPTH_UNUSED))
block-inputs[i] = NULL;
}
}
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_sched.c
b/src/gallium/drivers/freedreno/ir3/ir3_sched.c
index 24d7c63..b2ef811 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_sched.c
+++
Mesa (master): vc4: Don' t look at back stencil state unless two-sided stencil is enabled.
Module: Mesa
Branch: master
Commit: 48f6351940ff62c29fff618cec722e845acc86d5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=48f6351940ff62c29fff618cec722e845acc86d5
Author: Eric Anholt e...@anholt.net
Date: Mon Oct 20 22:53:07 2014 +0100
vc4: Don't look at back stencil state unless two-sided stencil is enabled.
Fixes regressions in the next bugfix, because gallium util stuff leaves
the back stencil state as 0 if !back-enabled.
---
src/gallium/drivers/vc4/vc4_state.c |8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/vc4/vc4_state.c
b/src/gallium/drivers/vc4/vc4_state.c
index 31f2424..99b5b3c 100644
--- a/src/gallium/drivers/vc4/vc4_state.c
+++ b/src/gallium/drivers/vc4/vc4_state.c
@@ -203,12 +203,16 @@ vc4_create_depth_stencil_alpha_state(struct pipe_context
*pctx,
uint8_t front_writemask_bits =
tlb_stencil_setup_writemask(front-writemask);
-uint8_t back_writemask_bits =
-tlb_stencil_setup_writemask(back-writemask);
+uint8_t back_writemask = front-writemask;
+uint8_t back_writemask_bits = front_writemask_bits;
so-stencil_uniforms[0] =
tlb_stencil_setup_bits(front, front_writemask_bits);
if (back-enabled) {
+back_writemask = back-writemask;
+back_writemask_bits =
+tlb_stencil_setup_writemask(back-writemask);
+
so-stencil_uniforms[0] |= (1 30);
so-stencil_uniforms[1] =
tlb_stencil_setup_bits(back,
back_writemask_bits);
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Mesa (master): vc4: Fix stencil writemask handling.
Module: Mesa
Branch: master
Commit: cc298023c9b302a7a24ee01fe2da1c93f5b44666
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc298023c9b302a7a24ee01fe2da1c93f5b44666
Author: Eric Anholt e...@anholt.net
Date: Mon Oct 20 21:14:57 2014 +0100
vc4: Fix stencil writemask handling.
If the writemask doesn't compress, then we want to put in the uncompressed
writemask, not the compressed writemask failure value (all-on).
Fixes glean's stencil2 and fbo-clear-formats on stencil.
---
src/gallium/drivers/vc4/vc4_state.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/vc4/vc4_state.c
b/src/gallium/drivers/vc4/vc4_state.c
index 99b5b3c..73d 100644
--- a/src/gallium/drivers/vc4/vc4_state.c
+++ b/src/gallium/drivers/vc4/vc4_state.c
@@ -223,8 +223,8 @@ vc4_create_depth_stencil_alpha_state(struct pipe_context
*pctx,
if (front_writemask_bits == 0xff ||
back_writemask_bits == 0xff) {
-so-stencil_uniforms[2] = (front_writemask_bits |
- (back_writemask_bits 8));
+so-stencil_uniforms[2] = (front-writemask |
+ (back_writemask 8));
}
}
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Mesa (master): vc4: Fix SRC_ALPHA_SATURATE blending.
Module: Mesa
Branch: master
Commit: ef280c95f2623357452f5ca8e65367b7ac30699f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef280c95f2623357452f5ca8e65367b7ac30699f
Author: Eric Anholt e...@anholt.net
Date: Tue Oct 21 15:46:48 2014 +0100
vc4: Fix SRC_ALPHA_SATURATE blending.
Fixes glean blendFunc.
---
src/gallium/drivers/vc4/vc4_program.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/vc4/vc4_program.c
b/src/gallium/drivers/vc4/vc4_program.c
index 7a2a975..c6d9fb3 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -1308,9 +1308,17 @@ vc4_blend_channel(struct vc4_compile *c,
case PIPE_BLENDFACTOR_DST_COLOR:
return qir_FMUL(c, val, dst[channel]);
case PIPE_BLENDFACTOR_SRC_ALPHA_SATURATE:
-return qir_FMIN(c, src[3], qir_FSUB(c,
-qir_uniform_f(c, 1.0),
-dst[3]));
+if (channel != 3) {
+return qir_FMUL(c,
+val,
+qir_FMIN(c,
+ src[3],
+ qir_FSUB(c,
+ qir_uniform_f(c,
1.0),
+ dst[3])));
+} else {
+return val;
+}
case PIPE_BLENDFACTOR_CONST_COLOR:
return qir_FMUL(c, val,
get_temp_for_uniform(c,
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Demos (master): cmake: Define HAVE_FREEGLUT when glutInitContextProfile symbol is present.
Module: Demos
Branch: master
Commit: d01490215409f0bea1a159cb1375ba6bd04d
URL:
http://cgit.freedesktop.org/mesa/demos/commit/?id=d01490215409f0bea1a159cb1375ba6bd04d
Author: José Fonseca jose.r.fons...@gmail.com
Date: Tue Oct 21 20:26:04 2014 +0100
cmake: Define HAVE_FREEGLUT when glutInitContextProfile symbol is present.
Just like the configure.ac does.
Trivial.
---
CMakeLists.txt |9 +
1 file changed, 9 insertions(+)
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 88a8b88..c3e217f 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -4,6 +4,7 @@ project (mesademos)
include (FindPkgConfig)
include (CheckCCompilerFlag)
+include (CheckSymbolExists)
find_package (OpenGL REQUIRED)
find_package (GLUT REQUIRED)
@@ -25,6 +26,14 @@ if (PKG_CONFIG_FOUND AND NOT WIN32)
pkg_check_modules (VG vg)
endif ()
+# Check for FreeGLUT 2.6 or later
+set (CMAKE_REQUIRED_INCLUDES ${GLUT_INCLUDE_DIR})
+set (CMAKE_REQUIRED_LIBRARIES ${GLUT_glut_LIBRARY})
+check_symbol_exists (glutInitContextProfile GL/glut.h;GL/freeglut.h
HAVE_FREEGLUT)
+if (HAVE_FREEGLUT)
+ add_definitions (-DHAVE_FREEGLUT)
+endif ()
+
if (UNIX)
link_libraries(m)
endif (UNIX)
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Mesa (master): radeonsi: inline si_pm4_alloc_state
Module: Mesa
Branch: master
Commit: 139bde061a6968671c7119ce78837f144a169abf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=139bde061a6968671c7119ce78837f144a169abf
Author: Marek Olšák marek.ol...@amd.com
Date: Tue Oct 14 17:31:00 2014 +0200
radeonsi: inline si_pm4_alloc_state
It seemed like the function needed a context pointer. Let's remove it
to make it less confusing.
Reviewed-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/si_pm4.c|5 -
src/gallium/drivers/radeonsi/si_pm4.h|1 -
src/gallium/drivers/radeonsi/si_state.c | 14 +++---
src/gallium/drivers/radeonsi/si_state_draw.c | 20 ++--
4 files changed, 17 insertions(+), 23 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pm4.c
b/src/gallium/drivers/radeonsi/si_pm4.c
index 0b872b8..954eb6e 100644
--- a/src/gallium/drivers/radeonsi/si_pm4.c
+++ b/src/gallium/drivers/radeonsi/si_pm4.c
@@ -120,11 +120,6 @@ void si_pm4_free_state(struct si_context *sctx,
FREE(state);
}
-struct si_pm4_state * si_pm4_alloc_state(struct si_context *sctx)
-{
- return CALLOC_STRUCT(si_pm4_state);
-}
-
unsigned si_pm4_dirty_dw(struct si_context *sctx)
{
unsigned count = 0;
diff --git a/src/gallium/drivers/radeonsi/si_pm4.h
b/src/gallium/drivers/radeonsi/si_pm4.h
index f234286..8680a9e 100644
--- a/src/gallium/drivers/radeonsi/si_pm4.h
+++ b/src/gallium/drivers/radeonsi/si_pm4.h
@@ -74,7 +74,6 @@ void si_pm4_add_bo(struct si_pm4_state *state,
void si_pm4_free_state(struct si_context *sctx,
struct si_pm4_state *state,
unsigned idx);
-struct si_pm4_state * si_pm4_alloc_state(struct si_context *sctx);
unsigned si_pm4_dirty_dw(struct si_context *sctx);
void si_pm4_emit(struct si_context *sctx, struct si_pm4_state *state);
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 0ef6d97..54151eb 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -225,7 +225,7 @@ static void si_update_fb_blend_state(struct si_context
*sctx)
if (blend == NULL)
return;
- pm4 = si_pm4_alloc_state(sctx);
+ pm4 = CALLOC_STRUCT(si_pm4_state);
if (pm4 == NULL)
return;
@@ -406,7 +406,7 @@ static void si_set_blend_color(struct pipe_context *ctx,
const struct pipe_blend_color *state)
{
struct si_context *sctx = (struct si_context *)ctx;
- struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
+ struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
if (pm4 == NULL)
return;
@@ -427,7 +427,7 @@ static void si_set_clip_state(struct pipe_context *ctx,
const struct pipe_clip_state *state)
{
struct si_context *sctx = (struct si_context *)ctx;
- struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
+ struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
struct pipe_constant_buffer cb;
if (pm4 == NULL)
@@ -530,7 +530,7 @@ static void si_update_fb_rs_state(struct si_context *sctx)
return;
}
- pm4 = si_pm4_alloc_state(sctx);
+ pm4 = CALLOC_STRUCT(si_pm4_state);
if (pm4 == NULL)
return;
@@ -696,7 +696,7 @@ static void si_delete_rs_state(struct pipe_context *ctx,
void *state)
*/
static void si_update_dsa_stencil_ref(struct si_context *sctx)
{
- struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
+ struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
struct pipe_stencil_ref *ref = sctx-stencil_ref;
struct si_state_dsa *dsa = sctx-queued.named.dsa;
@@ -2834,7 +2834,7 @@ static void si_set_border_colors(struct si_context *sctx,
unsigned count,
}
if (border_color_table) {
- struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
+ struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
uint64_t va_offset = sctx-border_color_table-gpu_address;
@@ -3081,7 +3081,7 @@ void si_init_state_functions(struct si_context *sctx)
void si_init_config(struct si_context *sctx)
{
- struct si_pm4_state *pm4 = si_pm4_alloc_state(sctx);
+ struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
if (pm4 == NULL)
return;
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index f2dc22f..2b27007 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -48,7 +48,7 @@ static void si_shader_es(struct pipe_context *ctx, struct
si_shader *shader)
uint64_t va;
si_pm4_delete_state(sctx, es, shader-pm4);
- pm4 = shader-pm4 = si_pm4_alloc_state(sctx);
+ pm4 = shader-pm4 = CALLOC_STRUCT(si_pm4_state);
if (pm4
Mesa (master): glsl_to_tgsi: use _mesa_copy_linked_program_data
Module: Mesa Branch: master Commit: 013850a1b7d6605e32883f2e93fa3d51cd3eb218 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=013850a1b7d6605e32883f2e93fa3d51cd3eb218 Author: Marek Olšák marek.ol...@amd.com Date: Mon Oct 6 21:12:14 2014 +0200 glsl_to_tgsi: use _mesa_copy_linked_program_data This deduplicates some code. --- src/mesa/state_tracker/st_glsl_to_tgsi.cpp |5 + 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index 21f4cb8..a6ce033 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -5214,6 +5214,7 @@ get_mesa_program(struct gl_context *ctx, v-have_sqrt = pscreen-get_shader_param(pscreen, ptarget, PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED); + _mesa_copy_linked_program_data(shader-Stage, shader_program, prog); _mesa_generate_parameters_list_for_uniforms(shader_program, shader, prog-Parameters); @@ -5319,10 +5320,6 @@ get_mesa_program(struct gl_context *ctx, case GL_GEOMETRY_SHADER: stgp = (struct st_geometry_program *)prog; stgp-glsl_to_tgsi = v; - stgp-Base.InputType = shader_program-Geom.InputType; - stgp-Base.OutputType = shader_program-Geom.OutputType; - stgp-Base.VerticesOut = shader_program-Geom.VerticesOut; - stgp-Base.Invocations = shader_program-Geom.Invocations; break; default: assert(!should not be reached); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl_to_tgsi: fix the value of gl_FrontFacing with native integers
Module: Mesa
Branch: master
Commit: 9ec305ead7750c7f91c79b043584c1997bacd9a7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ec305ead7750c7f91c79b043584c1997bacd9a7
Author: Marek Olšák marek.ol...@amd.com
Date: Thu Oct 16 16:21:54 2014 +0200
glsl_to_tgsi: fix the value of gl_FrontFacing with native integers
We must convert it to boolean from the DX9 float encoding that Gallium
specifies.
Later, we should probably define that FACE should be 0 or ~0 if native
integers are supported.
Cc: 10.2 10.3 mesa-sta...@lists.freedesktop.org
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index a0da9f6..21f4cb8 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -4781,15 +4781,19 @@ emit_wpos(struct st_context *st,
* saturating the value to [0,1] does the job.
*/
static void
-emit_face_var(struct st_translate *t)
+emit_face_var(struct gl_context *ctx, struct st_translate *t)
{
struct ureg_program *ureg = t-ureg;
struct ureg_dst face_temp = ureg_DECL_temporary(ureg);
struct ureg_src face_input = t-inputs[t-inputMapping[VARYING_SLOT_FACE]];
- /* MOV_SAT face_temp, input[face] */
- face_temp = ureg_saturate(face_temp);
- ureg_MOV(ureg, face_temp, face_input);
+ if (ctx-Const.NativeIntegers) {
+ ureg_FSGE(ureg, face_temp, face_input, ureg_imm1f(ureg, 0));
+ }
+ else {
+ /* MOV_SAT face_temp, input[face] */
+ ureg_MOV(ureg, ureg_saturate(face_temp), face_input);
+ }
/* Use face_temp as face input from here on: */
t-inputs[t-inputMapping[VARYING_SLOT_FACE]] = ureg_src(face_temp);
@@ -4909,7 +4913,7 @@ st_translate_program(
}
if (proginfo-InputsRead VARYING_BIT_FACE)
- emit_face_var(t);
+ emit_face_var(ctx, t);
/*
* Declare output attributes.
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Mesa (master): r300g: replace r300_get_num_samples with a util variant
Module: Mesa
Branch: master
Commit: 22c5886f3f2eabe19fda314b4d69d8075caacaae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=22c5886f3f2eabe19fda314b4d69d8075caacaae
Author: Marek Olšák marek.ol...@amd.com
Date: Mon Oct 20 15:41:42 2014 +0200
r300g: replace r300_get_num_samples with a util variant
---
src/gallium/drivers/r300/r300_state.c | 26 +-
1 file changed, 1 insertion(+), 25 deletions(-)
diff --git a/src/gallium/drivers/r300/r300_state.c
b/src/gallium/drivers/r300/r300_state.c
index 7d83576..fd67e35 100644
--- a/src/gallium/drivers/r300/r300_state.c
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -942,30 +942,6 @@ void r300_mark_fb_state_dirty(struct r300_context *r300,
/* The size of the rest of atoms stays the same. */
}
-static unsigned r300_get_num_samples(struct r300_context *r300)
-{
-struct pipe_framebuffer_state* fb =
-(struct pipe_framebuffer_state*)r300-fb_state.state;
-unsigned i, num_samples;
-
-if (!fb-nr_cbufs !fb-zsbuf)
-return 1;
-
-num_samples = 6;
-
-for (i = 0; i fb-nr_cbufs; i++)
-if (fb-cbufs[i])
-num_samples = MIN2(num_samples, fb-cbufs[i]-texture-nr_samples);
-
-if (fb-zsbuf)
-num_samples = MIN2(num_samples, fb-zsbuf-texture-nr_samples);
-
-if (!num_samples)
-num_samples = 1;
-
-return num_samples;
-}
-
static void
r300_set_framebuffer_state(struct pipe_context* pipe,
const struct pipe_framebuffer_state* state)
@@ -1073,7 +1049,7 @@ r300_set_framebuffer_state(struct pipe_context* pipe,
}
}
-r300-num_samples = r300_get_num_samples(r300);
+r300-num_samples = util_framebuffer_get_num_samples(state);
/* Set up AA config. */
if (r300-num_samples 1) {
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Mesa (master): radeonsi: generate shader pm4 states right after shader compilation
Module: Mesa
Branch: master
Commit: b9b0973db206bc3d376781e2d06001f2f48dc865
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9b0973db206bc3d376781e2d06001f2f48dc865
Author: Marek Olšák marek.ol...@amd.com
Date: Tue Oct 14 17:48:52 2014 +0200
radeonsi: generate shader pm4 states right after shader compilation
Reviewed-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/si_state.c |1 +
src/gallium/drivers/radeonsi/si_state.h |2 ++
src/gallium/drivers/radeonsi/si_state_draw.c | 38 ++
3 files changed, 24 insertions(+), 17 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 54151eb..c845df1 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2283,6 +2283,7 @@ int si_shader_select(struct pipe_context *ctx,
FREE(shader);
return r;
}
+ si_shader_init_pm4_state(shader);
sel-num_shaders++;
}
diff --git a/src/gallium/drivers/radeonsi/si_state.h
b/src/gallium/drivers/radeonsi/si_state.h
index f70bddf..4f5140c 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -31,6 +31,7 @@
#include radeon/r600_pipe_common.h
struct si_screen;
+struct si_shader;
struct si_state_blend {
struct si_pm4_state pm4;
@@ -270,6 +271,7 @@ unsigned si_tile_mode_index(struct r600_texture *rtex,
unsigned level, bool sten
/* si_state_draw.c */
extern const struct r600_atom si_atom_cache_flush;
extern const struct r600_atom si_atom_msaa_config;
+void si_shader_init_pm4_state(struct si_shader *shader);
void si_emit_cache_flush(struct r600_common_context *sctx, struct r600_atom
*atom);
void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *dinfo);
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index eb7ed40..707e234 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -300,6 +300,27 @@ static void si_shader_ps(struct si_shader *shader)
S_00B02C_USER_SGPR(num_user_sgprs));
}
+void si_shader_init_pm4_state(struct si_shader *shader)
+{
+ switch (shader-selector-type) {
+ case PIPE_SHADER_VERTEX:
+ if (shader-key.vs.as_es)
+ si_shader_es(shader);
+ else
+ si_shader_vs(shader);
+ break;
+ case PIPE_SHADER_GEOMETRY:
+ si_shader_gs(shader);
+ si_shader_vs(shader-gs_copy_shader);
+ break;
+ case PIPE_SHADER_FRAGMENT:
+ si_shader_ps(shader);
+ break;
+ default:
+ assert(0);
+ }
+}
+
/*
* Drawing
*/
@@ -598,22 +619,12 @@ static void si_update_derived_state(struct si_context
*sctx)
if (sctx-gs_shader) {
si_shader_select(ctx, sctx-gs_shader);
-
- if (!sctx-gs_shader-current-pm4) {
- si_shader_gs(sctx-gs_shader-current);
- si_shader_vs(sctx-gs_shader-current-gs_copy_shader);
- }
-
si_pm4_bind_state(sctx, gs, sctx-gs_shader-current-pm4);
si_pm4_bind_state(sctx, vs,
sctx-gs_shader-current-gs_copy_shader-pm4);
sctx-b.streamout.stride_in_dw = sctx-gs_shader-so.stride;
si_shader_select(ctx, sctx-vs_shader);
-
- if (!sctx-vs_shader-current-pm4)
- si_shader_es(sctx-vs_shader-current);
-
si_pm4_bind_state(sctx, es, sctx-vs_shader-current-pm4);
if (!sctx-gs_rings)
@@ -639,10 +650,6 @@ static void si_update_derived_state(struct si_context
*sctx)
si_pm4_bind_state(sctx, gs_onoff, sctx-gs_on);
} else {
si_shader_select(ctx, sctx-vs_shader);
-
- if (!sctx-vs_shader-current-pm4)
- si_shader_vs(sctx-vs_shader-current);
-
si_pm4_bind_state(sctx, vs, sctx-vs_shader-current-pm4);
sctx-b.streamout.stride_in_dw = sctx-vs_shader-so.stride;
@@ -671,9 +678,6 @@ static void si_update_derived_state(struct si_context *sctx)
sctx-ps_shader-current = sel-current;
}
- if (!sctx-ps_shader-current-pm4)
- si_shader_ps(sctx-ps_shader-current);
-
si_pm4_bind_state(sctx, ps, sctx-ps_shader-current-pm4);
if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs)) {
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Mesa (master): radeonsi: revert hack for random failures in glsl-max-varyings
Module: Mesa
Branch: master
Commit: a18f803a860767be3604369d865b6c0df0d15f2a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a18f803a860767be3604369d865b6c0df0d15f2a
Author: Marek Olšák marek.ol...@amd.com
Date: Tue Oct 14 22:51:10 2014 +0200
radeonsi: revert hack for random failures in glsl-max-varyings
This reverts commit 032e5548b3d4b5efa52359218725cb8e31b622ad.
I've run glsl-max-varyings 30 times and it always passed.
Reviewed-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/si_state_draw.c |8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 707e234..4f81dac 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -680,14 +680,8 @@ static void si_update_derived_state(struct si_context
*sctx)
si_pm4_bind_state(sctx, ps, sctx-ps_shader-current-pm4);
- if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs)) {
- /* XXX: Emitting the PS state even when only the VS changed
-* fixes random failures with piglit glsl-max-varyings.
-* Not sure why...
-*/
- sctx-emitted.named.ps = NULL;
+ if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs))
si_update_spi_map(sctx);
- }
if (sctx-ps_db_shader_control !=
sctx-ps_shader-current-db_shader_control) {
sctx-ps_db_shader_control =
sctx-ps_shader-current-db_shader_control;
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Mesa (master): radeonsi: clarify shader constant load functions
Module: Mesa
Branch: master
Commit: d78760895772f79f3bd89e2c0ed50366ba75dbf0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d78760895772f79f3bd89e2c0ed50366ba75dbf0
Author: Marek Olšák marek.ol...@amd.com
Date: Fri Sep 26 23:06:32 2014 +0200
radeonsi: clarify shader constant load functions
I'll need indexed loads without the meta data flag for tessellation later.
Also rename load_const to buffer_load_const to distinguish it from indexed
const loads.
v2: add comments
Reviewed-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/si_shader.c | 86 --
1 file changed, 46 insertions(+), 40 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index cd78f66..276c27e 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -182,32 +182,35 @@ static int get_param_index(unsigned semantic_name,
unsigned index,
}
/**
- * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad
- *
- * @param offset The offset parameter specifies the number of
- * elements to offset, not the number of bytes or dwords. An element is the
- * the type pointed to by the base_ptr parameter (e.g. int is the element of
- * an int* pointer)
- *
- * When LLVM lowers the load instruction, it will convert the element offset
- * into a dword offset automatically.
+ * Build an LLVM bytecode indexed load using LLVMBuildGEP + LLVMBuildLoad.
+ * It's equivalent to doing a load from base_ptr[index].
*
+ * \param base_ptr Where the array starts.
+ * \param index The element index into the array.
*/
-static LLVMValueRef build_indexed_load(
- struct si_shader_context * si_shader_ctx,
- LLVMValueRef base_ptr,
- LLVMValueRef offset)
+static LLVMValueRef build_indexed_load(struct si_shader_context *si_shader_ctx,
+ LLVMValueRef base_ptr, LLVMValueRef
index)
{
- struct lp_build_context * base =
si_shader_ctx-radeon_bld.soa.bld_base.base;
+ struct lp_build_tgsi_context *bld_base =
si_shader_ctx-radeon_bld.soa.bld_base;
+ struct gallivm_state *gallivm = bld_base-base.gallivm;
+ LLVMValueRef indices[2], pointer;
- LLVMValueRef indices[2] = {
- LLVMConstInt(LLVMInt64TypeInContext(base-gallivm-context), 0,
false),
- offset
- };
- LLVMValueRef computed_ptr = LLVMBuildGEP(
- base-gallivm-builder, base_ptr, indices, 2, );
+ indices[0] = bld_base-uint_bld.zero;
+ indices[1] = index;
- LLVMValueRef result = LLVMBuildLoad(base-gallivm-builder,
computed_ptr, );
+ pointer = LLVMBuildGEP(gallivm-builder, base_ptr, indices, 2, );
+ return LLVMBuildLoad(gallivm-builder, pointer, );
+}
+
+/**
+ * Do a load from base_ptr[index], but also add a flag that it's loading
+ * a constant.
+ */
+static LLVMValueRef build_indexed_load_const(
+ struct si_shader_context * si_shader_ctx,
+ LLVMValueRef base_ptr, LLVMValueRef index)
+{
+ LLVMValueRef result = build_indexed_load(si_shader_ctx, base_ptr,
index);
LLVMSetMetadata(result, 1, si_shader_ctx-const_md);
return result;
}
@@ -259,7 +262,7 @@ static void declare_input_vs(
t_offset = lp_build_const_int32(gallivm, input_index);
- t_list = build_indexed_load(si_shader_ctx, t_list_ptr, t_offset);
+ t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr, t_offset);
/* Build the attribute offset */
attribute_offset = lp_build_const_int32(gallivm, 0);
@@ -354,7 +357,7 @@ static LLVMValueRef fetch_input_gs(
/* Load the ESGS ring resource descriptor */
t_list_ptr = LLVMGetParam(si_shader_ctx-radeon_bld.main_fn,
SI_PARAM_RW_BUFFERS);
- t_list = build_indexed_load(si_shader_ctx, t_list_ptr,
+ t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr,
lp_build_const_int32(gallivm,
SI_RING_ESGS));
args[0] = t_list;
@@ -562,8 +565,11 @@ static LLVMValueRef get_sample_id(struct
radeon_llvm_context *radeon_bld)
return value;
}
-static LLVMValueRef load_const(LLVMBuilderRef builder, LLVMValueRef resource,
- LLVMValueRef offset, LLVMTypeRef return_type)
+/**
+ * Load a dword from a constant buffer.
+ */
+static LLVMValueRef buffer_load_const(LLVMBuilderRef builder, LLVMValueRef
resource,
+ LLVMValueRef offset, LLVMTypeRef
return_type)
{
LLVMValueRef args[2] = {resource, offset};
@@ -602,15 +608,15 @@ static void declare_system_value(
LLVMBuilderRef builder = gallivm-builder;
LLVMValueRef desc =
LLVMGetParam(si_shader_ctx-radeon_bld.main_fn, SI_PARAM_CONST);
LLVMValueRef buf_index = lp_build_const_int32(gallivm,
SI_DRIVER_STATE_CONST_BUF);
-
Mesa (master): gallium: add PIPE_SHADER_CAP_MAX_OUTPUTS and use it in st/ mesa
Module: Mesa Branch: master Commit: 5f5b83cbba95a7bb8955b09e24df1e9487c10734 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f5b83cbba95a7bb8955b09e24df1e9487c10734 Author: Marek Olšák marek.ol...@amd.com Date: Wed Oct 1 20:28:17 2014 +0200 gallium: add PIPE_SHADER_CAP_MAX_OUTPUTS and use it in st/mesa With 5 shader stages and various combinations of enabled and disabled shaders, the maximum number of outputs in one shader doesn't have to be equal to the maximum number of inputs in the following shader. v2: return 32 for softpipe and llvmpipe --- src/gallium/auxiliary/gallivm/lp_bld_limits.h|2 ++ src/gallium/auxiliary/tgsi/tgsi_exec.h |2 ++ src/gallium/docs/source/screen.rst |2 ++ src/gallium/drivers/freedreno/freedreno_screen.c |1 + src/gallium/drivers/i915/i915_screen.c |2 ++ src/gallium/drivers/ilo/ilo_screen.c |1 + src/gallium/drivers/nouveau/nv30/nv30_screen.c |3 +++ src/gallium/drivers/nouveau/nv50/nv50_screen.c |2 ++ src/gallium/drivers/nouveau/nvc0/nvc0_screen.c |2 ++ src/gallium/drivers/r300/r300_screen.c |4 src/gallium/drivers/r600/r600_pipe.c |2 ++ src/gallium/drivers/radeonsi/si_pipe.c |2 ++ src/gallium/drivers/svga/svga_screen.c |4 src/gallium/drivers/vc4/vc4_screen.c |2 ++ src/gallium/include/pipe/p_defines.h |1 + src/mesa/state_tracker/st_extensions.c |8 16 files changed, 36 insertions(+), 4 deletions(-) diff --git a/src/gallium/auxiliary/gallivm/lp_bld_limits.h b/src/gallium/auxiliary/gallivm/lp_bld_limits.h index a96ab29..8c66f9d 100644 --- a/src/gallium/auxiliary/gallivm/lp_bld_limits.h +++ b/src/gallium/auxiliary/gallivm/lp_bld_limits.h @@ -97,6 +97,8 @@ gallivm_get_shader_param(enum pipe_shader_cap param) return LP_MAX_TGSI_NESTING; case PIPE_SHADER_CAP_MAX_INPUTS: return PIPE_MAX_SHADER_INPUTS; + case PIPE_SHADER_CAP_MAX_OUTPUTS: + return 32; case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: return sizeof(float[4]) * 4096; case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.h b/src/gallium/auxiliary/tgsi/tgsi_exec.h index 4720ec6..cc5a916 100644 --- a/src/gallium/auxiliary/tgsi/tgsi_exec.h +++ b/src/gallium/auxiliary/tgsi/tgsi_exec.h @@ -426,6 +426,8 @@ tgsi_exec_get_shader_param(enum pipe_shader_cap param) return TGSI_EXEC_MAX_NESTING; case PIPE_SHADER_CAP_MAX_INPUTS: return TGSI_EXEC_MAX_INPUT_ATTRIBS; + case PIPE_SHADER_CAP_MAX_OUTPUTS: + return 32; case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: return TGSI_EXEC_MAX_CONST_BUFFER_SIZE; case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst index ba34ec8..88d7e49 100644 --- a/src/gallium/docs/source/screen.rst +++ b/src/gallium/docs/source/screen.rst @@ -267,6 +267,8 @@ support different features. * ``PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS``: The maximum number of texture indirections. * ``PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH``: The maximum nested control flow depth. * ``PIPE_SHADER_CAP_MAX_INPUTS``: The maximum number of input registers. +* ``PIPE_SHADER_CAP_MAX_OUTPUTS``: The maximum number of output registers. + This is valid for all shaders except the fragment shader. * ``PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE``: The maximum size per constant buffer in bytes. * ``PIPE_SHADER_CAP_MAX_CONST_BUFFERS``: Maximum number of constant buffers that can be bound to any shader stage using ``set_constant_buffer``. If 0 or 1, the pipe will diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index ddc7302..90156b4 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -351,6 +351,7 @@ fd_screen_get_shader_param(struct pipe_screen *pscreen, unsigned shader, case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH: return 8; /* XXX */ case PIPE_SHADER_CAP_MAX_INPUTS: +case PIPE_SHADER_CAP_MAX_OUTPUTS: return 16; case PIPE_SHADER_CAP_MAX_TEMPS: return 64; /* Max native temporaries. */ diff --git a/src/gallium/drivers/i915/i915_screen.c b/src/gallium/drivers/i915/i915_screen.c index 9006734..2a6e751 100644 --- a/src/gallium/drivers/i915/i915_screen.c +++ b/src/gallium/drivers/i915/i915_screen.c @@ -130,6 +130,8 @@ i915_get_shader_param(struct pipe_screen *screen, unsigned shader, enum pipe_sha return 0; case PIPE_SHADER_CAP_MAX_INPUTS: return 10; + case PIPE_SHADER_CAP_MAX_OUTPUTS: + return 1; case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE: return 32 * sizeof(float[4]); case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: diff --git a/src/gallium/drivers/ilo/ilo_screen.c
Mesa (master): radeonsi: statically declare resource and sampler arrays
Module: Mesa Branch: master Commit: 55a9b778c8c111a58f801dc20b64d0d0b0477e0d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=55a9b778c8c111a58f801dc20b64d0d0b0477e0d Author: Marek Olšák marek.ol...@amd.com Date: Sun Oct 5 12:38:54 2014 +0200 radeonsi: statically declare resource and sampler arrays Reviewed-by: Michel Dänzer michel.daen...@amd.com --- src/gallium/drivers/radeonsi/si_shader.c | 10 ++ 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 6f2fb7b..cd78f66 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -68,8 +68,8 @@ struct si_shader_context LLVMValueRef const_resource[SI_NUM_CONST_BUFFERS]; LLVMValueRef ddxy_lds; LLVMValueRef *constants[SI_NUM_CONST_BUFFERS]; - LLVMValueRef *resources; - LLVMValueRef *samplers; + LLVMValueRef resources[SI_NUM_SAMPLER_VIEWS]; + LLVMValueRef samplers[SI_NUM_SAMPLER_STATES]; LLVMValueRef so_buffers[4]; LLVMValueRef gs_next_vertex; }; @@ -2435,10 +2435,6 @@ static void preload_samplers(struct si_shader_context *si_shader_ctx) if (num_samplers == 0) return; - /* Allocate space for the values */ - si_shader_ctx-resources = CALLOC(SI_NUM_SAMPLER_VIEWS, sizeof(LLVMValueRef)); - si_shader_ctx-samplers = CALLOC(num_samplers, sizeof(LLVMValueRef)); - res_ptr = LLVMGetParam(si_shader_ctx-radeon_bld.main_fn, SI_PARAM_RESOURCE); samp_ptr = LLVMGetParam(si_shader_ctx-radeon_bld.main_fn, SI_PARAM_SAMPLER); @@ -2790,8 +2786,6 @@ int si_shader_create(struct si_screen *sscreen, struct si_shader *shader) out: for (int i = 0; i SI_NUM_CONST_BUFFERS; i++) FREE(si_shader_ctx.constants[i]); - FREE(si_shader_ctx.resources); - FREE(si_shader_ctx.samplers); return r; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g,radeonsi: convert TGSI shader type to LLVM shader type
Module: Mesa
Branch: master
Commit: 43b243236824ce80daaa5cb4af5db94aaca0855e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=43b243236824ce80daaa5cb4af5db94aaca0855e
Author: Marek Olšák marek.ol...@amd.com
Date: Tue Sep 23 17:17:01 2014 +0200
r600g,radeonsi: convert TGSI shader type to LLVM shader type
The values are hardcoded in the LLVM backend, but the TGSI definitions are
going to be changed with tessellation, e.g. TGSI_PROCESSOR_COMPUTE will be
increased by 2.
We'll use VS for LS and HS, because there's nothing special about them
from the LLVM backend point of view, even though the hardware side is
different. We do the same for ES.
Reviewed-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeon/radeon_llvm_emit.c | 31 -
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeon/radeon_llvm_emit.c
b/src/gallium/drivers/radeon/radeon_llvm_emit.c
index 53694b7..dc871d7 100644
--- a/src/gallium/drivers/radeon/radeon_llvm_emit.c
+++ b/src/gallium/drivers/radeon/radeon_llvm_emit.c
@@ -41,6 +41,16 @@
#define TRIPLE_STRING_LEN 7
/**
+ * Shader types for the LLVM backend.
+ */
+enum radeon_llvm_shader_type {
+ RADEON_LLVM_SHADER_PS = 0,
+ RADEON_LLVM_SHADER_VS = 1,
+ RADEON_LLVM_SHADER_GS = 2,
+ RADEON_LLVM_SHADER_CS = 3,
+};
+
+/**
* Set the shader type we want to compile
*
* @param type shader type to set
@@ -48,7 +58,26 @@
void radeon_llvm_shader_type(LLVMValueRef F, unsigned type)
{
char Str[2];
- sprintf(Str, %1d, type);
+ enum radeon_llvm_shader_type llvm_type;
+
+ switch (type) {
+ case TGSI_PROCESSOR_VERTEX:
+ llvm_type = RADEON_LLVM_SHADER_VS;
+ break;
+ case TGSI_PROCESSOR_GEOMETRY:
+ llvm_type = RADEON_LLVM_SHADER_GS;
+ break;
+ case TGSI_PROCESSOR_FRAGMENT:
+ llvm_type = RADEON_LLVM_SHADER_PS;
+ break;
+ case TGSI_PROCESSOR_COMPUTE:
+ llvm_type = RADEON_LLVM_SHADER_CS;
+ break;
+ default:
+ assert(0);
+ }
+
+ sprintf(Str, %1d, llvm_type);
LLVMAddTargetDependentFunctionAttr(F, ShaderType, Str);
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Mesa (master): st/mesa: add ST_DEBUG= wf option which enables wireframe rendering
Module: Mesa
Branch: master
Commit: e8764a46731aaa20d6c7bc98d227e1a94fafbf5b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e8764a46731aaa20d6c7bc98d227e1a94fafbf5b
Author: Marek Olšák marek.ol...@amd.com
Date: Sun Oct 5 18:55:47 2014 +0200
st/mesa: add ST_DEBUG=wf option which enables wireframe rendering
Useful for tessellation.
---
src/mesa/state_tracker/st_atom_rasterizer.c | 11 +--
src/mesa/state_tracker/st_debug.c |1 +
src/mesa/state_tracker/st_debug.h |1 +
3 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/src/mesa/state_tracker/st_atom_rasterizer.c
b/src/mesa/state_tracker/st_atom_rasterizer.c
index a228538..dfa728b 100644
--- a/src/mesa/state_tracker/st_atom_rasterizer.c
+++ b/src/mesa/state_tracker/st_atom_rasterizer.c
@@ -33,6 +33,7 @@
#include main/macros.h
#include st_context.h
#include st_atom.h
+#include st_debug.h
#include st_program.h
#include pipe/p_context.h
#include pipe/p_defines.h
@@ -119,8 +120,14 @@ static void update_raster_state( struct st_context *st )
/* _NEW_POLYGON
*/
{
- raster-fill_front = translate_fill( ctx-Polygon.FrontMode );
- raster-fill_back = translate_fill( ctx-Polygon.BackMode );
+ if (ST_DEBUG DEBUG_WIREFRAME) {
+ raster-fill_front = PIPE_POLYGON_MODE_LINE;
+ raster-fill_back = PIPE_POLYGON_MODE_LINE;
+ }
+ else {
+ raster-fill_front = translate_fill( ctx-Polygon.FrontMode );
+ raster-fill_back = translate_fill( ctx-Polygon.BackMode );
+ }
/* Simplify when culling is active:
*/
diff --git a/src/mesa/state_tracker/st_debug.c
b/src/mesa/state_tracker/st_debug.c
index 8c15e18..de3e3a9 100644
--- a/src/mesa/state_tracker/st_debug.c
+++ b/src/mesa/state_tracker/st_debug.c
@@ -55,6 +55,7 @@ static const struct debug_named_value st_debug_flags[] = {
{ query,DEBUG_QUERY, NULL },
{ draw, DEBUG_DRAW, NULL },
{ buffer, DEBUG_BUFFER, NULL },
+ { wf, DEBUG_WIREFRAME, NULL },
DEBUG_NAMED_VALUE_END
};
diff --git a/src/mesa/state_tracker/st_debug.h
b/src/mesa/state_tracker/st_debug.h
index c1c4825..49b916f 100644
--- a/src/mesa/state_tracker/st_debug.h
+++ b/src/mesa/state_tracker/st_debug.h
@@ -46,6 +46,7 @@ st_print_current(void);
#define DEBUG_SCREEN0x80
#define DEBUG_DRAW 0x100
#define DEBUG_BUFFER0x200
+#define DEBUG_WIREFRAME 0x400
#ifdef DEBUG
extern int ST_DEBUG;
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Mesa (master): radeonsi: make pm4 state generation for shaders independent of the context
Module: Mesa
Branch: master
Commit: c94af8f0d717c1079327c51d8983b57c09aa2d1b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c94af8f0d717c1079327c51d8983b57c09aa2d1b
Author: Marek Olšák marek.ol...@amd.com
Date: Tue Oct 14 17:36:30 2014 +0200
radeonsi: make pm4 state generation for shaders independent of the context
The si_pm4_delete_state calls became useless, because the pm4 state is
always generated only once.
Reviewed-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/si_state_draw.c | 26 +-
1 file changed, 9 insertions(+), 17 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 2b27007..eb7ed40 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -39,15 +39,13 @@
* Shaders
*/
-static void si_shader_es(struct pipe_context *ctx, struct si_shader *shader)
+static void si_shader_es(struct si_shader *shader)
{
- struct si_context *sctx = (struct si_context *)ctx;
struct si_pm4_state *pm4;
unsigned num_sgprs, num_user_sgprs;
unsigned vgpr_comp_cnt;
uint64_t va;
- si_pm4_delete_state(sctx, es, shader-pm4);
pm4 = shader-pm4 = CALLOC_STRUCT(si_pm4_state);
if (pm4 == NULL)
@@ -77,9 +75,8 @@ static void si_shader_es(struct pipe_context *ctx, struct
si_shader *shader)
S_00B32C_USER_SGPR(num_user_sgprs));
}
-static void si_shader_gs(struct pipe_context *ctx, struct si_shader *shader)
+static void si_shader_gs(struct si_shader *shader)
{
- struct si_context *sctx = (struct si_context *)ctx;
unsigned gs_vert_itemsize = shader-selector-info.num_outputs * (16
2);
unsigned gs_max_vert_out = shader-selector-gs_max_out_vertices;
unsigned gsvs_itemsize = gs_vert_itemsize * gs_max_vert_out;
@@ -91,7 +88,6 @@ static void si_shader_gs(struct pipe_context *ctx, struct
si_shader *shader)
/* The GSVS_RING_ITEMSIZE register takes 15 bits */
assert(gsvs_itemsize (1 15));
- si_pm4_delete_state(sctx, gs, shader-pm4);
pm4 = shader-pm4 = CALLOC_STRUCT(si_pm4_state);
if (pm4 == NULL)
@@ -147,16 +143,14 @@ static void si_shader_gs(struct pipe_context *ctx, struct
si_shader *shader)
S_00B22C_USER_SGPR(num_user_sgprs));
}
-static void si_shader_vs(struct pipe_context *ctx, struct si_shader *shader)
+static void si_shader_vs(struct si_shader *shader)
{
- struct si_context *sctx = (struct si_context *)ctx;
struct tgsi_shader_info *info = shader-selector-info;
struct si_pm4_state *pm4;
unsigned num_sgprs, num_user_sgprs;
unsigned nparams, i, vgpr_comp_cnt;
uint64_t va;
- si_pm4_delete_state(sctx, vs, shader-pm4);
pm4 = shader-pm4 = CALLOC_STRUCT(si_pm4_state);
if (pm4 == NULL)
@@ -226,9 +220,8 @@ static void si_shader_vs(struct pipe_context *ctx, struct
si_shader *shader)
S_00B12C_SO_EN(!!shader-selector-so.num_outputs));
}
-static void si_shader_ps(struct pipe_context *ctx, struct si_shader *shader)
+static void si_shader_ps(struct si_shader *shader)
{
- struct si_context *sctx = (struct si_context *)ctx;
struct tgsi_shader_info *info = shader-selector-info;
struct si_pm4_state *pm4;
unsigned i, spi_ps_in_control;
@@ -236,7 +229,6 @@ static void si_shader_ps(struct pipe_context *ctx, struct
si_shader *shader)
unsigned spi_baryc_cntl = 0, spi_ps_input_ena;
uint64_t va;
- si_pm4_delete_state(sctx, ps, shader-pm4);
pm4 = shader-pm4 = CALLOC_STRUCT(si_pm4_state);
if (pm4 == NULL)
@@ -608,8 +600,8 @@ static void si_update_derived_state(struct si_context *sctx)
si_shader_select(ctx, sctx-gs_shader);
if (!sctx-gs_shader-current-pm4) {
- si_shader_gs(ctx, sctx-gs_shader-current);
- si_shader_vs(ctx,
sctx-gs_shader-current-gs_copy_shader);
+ si_shader_gs(sctx-gs_shader-current);
+ si_shader_vs(sctx-gs_shader-current-gs_copy_shader);
}
si_pm4_bind_state(sctx, gs, sctx-gs_shader-current-pm4);
@@ -620,7 +612,7 @@ static void si_update_derived_state(struct si_context *sctx)
si_shader_select(ctx, sctx-vs_shader);
if (!sctx-vs_shader-current-pm4)
- si_shader_es(ctx, sctx-vs_shader-current);
+ si_shader_es(sctx-vs_shader-current);
si_pm4_bind_state(sctx, es, sctx-vs_shader-current-pm4);
@@ -649,7 +641,7 @@ static void si_update_derived_state(struct si_context *sctx)
si_shader_select(ctx, sctx-vs_shader);
if (!sctx-vs_shader-current-pm4)
- si_shader_vs(ctx, sctx-vs_shader-current);
+
Mesa (master): radeonsi: load ring resource descriptors only once
Module: Mesa
Branch: master
Commit: fc3b3354d7d69b324b63d787cbd925e6a34d5f56
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc3b3354d7d69b324b63d787cbd925e6a34d5f56
Author: Marek Olšák marek.ol...@amd.com
Date: Sun Oct 5 13:33:40 2014 +0200
radeonsi: load ring resource descriptors only once
v2: document the new functions
Reviewed-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/si_shader.c | 77 --
1 file changed, 42 insertions(+), 35 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 276c27e..f8e9fbe 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -71,6 +71,8 @@ struct si_shader_context
LLVMValueRef resources[SI_NUM_SAMPLER_VIEWS];
LLVMValueRef samplers[SI_NUM_SAMPLER_STATES];
LLVMValueRef so_buffers[4];
+ LLVMValueRef esgs_ring;
+ LLVMValueRef gsvs_ring;
LLVMValueRef gs_next_vertex;
};
@@ -312,8 +314,6 @@ static LLVMValueRef fetch_input_gs(
struct gallivm_state *gallivm = base-gallivm;
LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm-context);
LLVMValueRef vtx_offset;
- LLVMValueRef t_list_ptr;
- LLVMValueRef t_list;
LLVMValueRef args[9];
unsigned vtx_offset_param;
struct tgsi_shader_info *info = shader-selector-info;
@@ -354,13 +354,7 @@ static LLVMValueRef fetch_input_gs(
vtx_offset_param),
4);
- /* Load the ESGS ring resource descriptor */
- t_list_ptr = LLVMGetParam(si_shader_ctx-radeon_bld.main_fn,
- SI_PARAM_RW_BUFFERS);
- t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr,
- lp_build_const_int32(gallivm,
SI_RING_ESGS));
-
- args[0] = t_list;
+ args[0] = si_shader_ctx-esgs_ring;
args[1] = vtx_offset;
args[2] = lp_build_const_int32(gallivm,
(get_param_index(semantic_name,
semantic_index,
@@ -1240,17 +1234,9 @@ static void si_llvm_emit_es_epilogue(struct
lp_build_tgsi_context * bld_base)
LLVMTypeRef i32 = LLVMInt32TypeInContext(gallivm-context);
LLVMValueRef soffset = LLVMGetParam(si_shader_ctx-radeon_bld.main_fn,
SI_PARAM_ES2GS_OFFSET);
- LLVMValueRef t_list_ptr;
- LLVMValueRef t_list;
unsigned chan;
int i;
- /* Load the ESGS ring resource descriptor */
- t_list_ptr = LLVMGetParam(si_shader_ctx-radeon_bld.main_fn,
- SI_PARAM_RW_BUFFERS);
- t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr,
- lp_build_const_int32(gallivm,
SI_RING_ESGS));
-
for (i = 0; i info-num_outputs; i++) {
LLVMValueRef *out_ptr =
si_shader_ctx-radeon_bld.soa.outputs[i];
@@ -1265,7 +1251,9 @@ static void si_llvm_emit_es_epilogue(struct
lp_build_tgsi_context * bld_base)
LLVMValueRef out_val = LLVMBuildLoad(gallivm-builder,
out_ptr[chan], );
out_val = LLVMBuildBitCast(gallivm-builder, out_val,
i32, );
- build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
+ build_tbuffer_store(si_shader_ctx,
+ si_shader_ctx-esgs_ring,
+ out_val, 1,
LLVMGetUndef(i32), soffset,
(4 * param_index + chan) * 4,
V_008F0C_BUF_DATA_FORMAT_32,
@@ -2150,18 +2138,10 @@ static void si_llvm_emit_vertex(
SI_PARAM_GS2VS_OFFSET);
LLVMValueRef gs_next_vertex;
LLVMValueRef can_emit, kill;
- LLVMValueRef t_list_ptr;
- LLVMValueRef t_list;
LLVMValueRef args[2];
unsigned chan;
int i;
- /* Load the GSVS ring resource descriptor */
- t_list_ptr = LLVMGetParam(si_shader_ctx-radeon_bld.main_fn,
- SI_PARAM_RW_BUFFERS);
- t_list = build_indexed_load_const(si_shader_ctx, t_list_ptr,
- lp_build_const_int32(gallivm,
SI_RING_GSVS));
-
/* Write vertex attribute values to GSVS ring */
gs_next_vertex = LLVMBuildLoad(gallivm-builder,
si_shader_ctx-gs_next_vertex, );
@@ -2194,7 +2174,9 @@ static void si_llvm_emit_vertex(
out_val = LLVMBuildBitCast(gallivm-builder, out_val,
i32, );
- build_tbuffer_store(si_shader_ctx, t_list, out_val, 1,
+ build_tbuffer_store(si_shader_ctx,
+
Mesa (master): clover: Fix build error with LLVM 3.4.
Module: Mesa
Branch: master
Commit: 1ab6543431b5a4eaf589cdabf2227088dd62ce6f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1ab6543431b5a4eaf589cdabf2227088dd62ce6f
Author: Vinson Lee v...@freedesktop.org
Date: Sun Oct 19 00:13:33 2014 -0700
clover: Fix build error with LLVM 3.4.
DataLayoutPass was added in LLVM 3.5 r202168, commit
57edc9d4ff1648568a5dd7e9958649065b260dca Make DataLayout a plain
object, not a pass..
This patch fixes this build error with LLVM 3.4.
CXX llvm/libclllvm_la-invocation.lo
llvm/invocation.cpp: In function 'void {anonymous}::optimize(llvm::Module*,
unsigned int, const std::vectorllvm::Function*)':
llvm/invocation.cpp:324:18: error: expected type-specifier
PM.add(new llvm::DataLayoutPass(mod));
^
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85189
Signed-off-by: Vinson Lee v...@freedesktop.org
Reviewed-by: Tom Stellard thomas.stell...@amd.com
---
src/gallium/state_trackers/clover/llvm/invocation.cpp |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/gallium/state_trackers/clover/llvm/invocation.cpp
b/src/gallium/state_trackers/clover/llvm/invocation.cpp
index 507daa0..7c31008 100644
--- a/src/gallium/state_trackers/clover/llvm/invocation.cpp
+++ b/src/gallium/state_trackers/clover/llvm/invocation.cpp
@@ -344,7 +344,9 @@ namespace {
llvm::Function *kernel = *I;
export_list.push_back(kernel-getName().data());
}
-#if HAVE_LLVM 0x0306
+#if HAVE_LLVM 0x0305
+ PM.add(new llvm::DataLayout(mod));
+#elif HAVE_LLVM 0x0306
PM.add(new llvm::DataLayoutPass(mod));
#else
PM.add(new llvm::DataLayoutPass());
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Mesa (master): freedreno/a3xx: fix depth/stencil restore format
Module: Mesa
Branch: master
Commit: 36310d9d56510ef50318bbb370f6c3d27ba09ebd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=36310d9d56510ef50318bbb370f6c3d27ba09ebd
Author: Rob Clark robcl...@freedesktop.org
Date: Tue Oct 21 17:08:10 2014 -0400
freedreno/a3xx: fix depth/stencil restore format
Also fix z16 restore format which was completely wrong.
Signed-off-by: Rob Clark robcl...@freedesktop.org
---
src/gallium/drivers/freedreno/a3xx/fd3_util.c |6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_util.c
b/src/gallium/drivers/freedreno/a3xx/fd3_util.c
index c83f65a..f443349 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_util.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_util.c
@@ -264,6 +264,9 @@ fd3_pipe2tex(enum pipe_format format)
case PIPE_FORMAT_I8_UNORM:
return TFMT_NORM_UINT_8;
+ case PIPE_FORMAT_R8G8_UNORM:
+ return TFMT_NORM_UINT_8_8;
+
case PIPE_FORMAT_B8G8R8A8_UNORM:
case PIPE_FORMAT_B8G8R8X8_UNORM:
case PIPE_FORMAT_R8G8B8A8_UNORM:
@@ -378,8 +381,9 @@ fd3_gmem_restore_format(enum pipe_format format)
switch (format) {
case PIPE_FORMAT_Z24X8_UNORM:
case PIPE_FORMAT_Z24_UNORM_S8_UINT:
+ return PIPE_FORMAT_R8G8B8A8_UNORM;
case PIPE_FORMAT_Z16_UNORM:
- return PIPE_FORMAT_B8G8R8A8_UNORM;
+ return PIPE_FORMAT_R8G8_UNORM;
default:
return format;
}
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Mesa (master): freedreno/a3xx: fix viewport state during clear
Module: Mesa
Branch: master
Commit: 2bc2ab66d9c06477cdec6799c24733fbd2d4db3f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2bc2ab66d9c06477cdec6799c24733fbd2d4db3f
Author: Rob Clark robcl...@freedesktop.org
Date: Tue Oct 21 12:25:28 2014 -0400
freedreno/a3xx: fix viewport state during clear
Signed-off-by: Rob Clark robcl...@freedesktop.org
---
src/gallium/drivers/freedreno/a3xx/fd3_draw.c | 20 +++-
1 file changed, 19 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_draw.c
b/src/gallium/drivers/freedreno/a3xx/fd3_draw.c
index e168d97..0fb0625 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_draw.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_draw.c
@@ -158,6 +158,22 @@ fd3_draw(struct fd_context *ctx, const struct
pipe_draw_info *info)
draw_impl(ctx, ctx-ring, emit);
}
+/* clear operations ignore viewport state, so we need to reset it
+ * based on framebuffer state:
+ */
+static void
+reset_viewport(struct fd_ringbuffer *ring, struct pipe_framebuffer_state *pfb)
+{
+ float half_width = pfb-width * 0.5f;
+ float half_height = pfb-height * 0.5f;
+
+ OUT_PKT0(ring, REG_A3XX_GRAS_CL_VPORT_XOFFSET, 4);
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_XOFFSET(half_width - 0.5));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_XSCALE(half_width));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_YOFFSET(half_height - 0.5));
+ OUT_RING(ring, A3XX_GRAS_CL_VPORT_YSCALE(-half_height));
+}
+
/* binning pass cmds for a clear:
* NOTE: newer blob drivers don't use binning for clear, which is probably
* preferable since it is low vtx count. However that doesn't seem to
@@ -183,6 +199,7 @@ fd3_clear_binning(struct fd_context *ctx, unsigned dirty)
fd3_emit_state(ctx, ring, emit);
fd3_emit_vertex_bufs(ring, emit);
+ reset_viewport(ring, ctx-framebuffer);
OUT_PKT0(ring, REG_A3XX_PC_PRIM_VTX_CNTL, 1);
OUT_RING(ring, A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(0) |
@@ -219,7 +236,7 @@ fd3_clear(struct fd_context *ctx, unsigned buffers,
},
};
- dirty = FD_DIRTY_VIEWPORT | FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
+ dirty = FD_DIRTY_FRAMEBUFFER | FD_DIRTY_SCISSOR;
dirty |= FD_DIRTY_PROG;
emit.dirty = dirty;
@@ -227,6 +244,7 @@ fd3_clear(struct fd_context *ctx, unsigned buffers,
/* emit generic state now: */
fd3_emit_state(ctx, ring, emit);
+ reset_viewport(ring, ctx-framebuffer);
OUT_PKT0(ring, REG_A3XX_RB_BLEND_ALPHA, 1);
OUT_RING(ring, A3XX_RB_BLEND_ALPHA_UINT(0xff) |
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Mesa (master): freedreno: mark scissor state dirty when enable bit changes
Module: Mesa
Branch: master
Commit: 3eb8289aa4cb599e9297ee1a1b5cfbae35ee562a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3eb8289aa4cb599e9297ee1a1b5cfbae35ee562a
Author: Rob Clark robcl...@freedesktop.org
Date: Tue Oct 21 11:28:53 2014 -0400
freedreno: mark scissor state dirty when enable bit changes
We don't have a scissor enable bit in hw, so when a raster state change
results in scissor enable bit changing, we need to also mark scissor
state as dirty.
Signed-off-by: Rob Clark robcl...@freedesktop.org
---
src/gallium/drivers/freedreno/freedreno_state.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/gallium/drivers/freedreno/freedreno_state.c
b/src/gallium/drivers/freedreno/freedreno_state.c
index 2786929..6293f43 100644
--- a/src/gallium/drivers/freedreno/freedreno_state.c
+++ b/src/gallium/drivers/freedreno/freedreno_state.c
@@ -237,8 +237,18 @@ static void
fd_rasterizer_state_bind(struct pipe_context *pctx, void *hwcso)
{
struct fd_context *ctx = fd_context(pctx);
+ struct pipe_scissor_state *old_scissor = fd_context_get_scissor(ctx);
+
ctx-rasterizer = hwcso;
ctx-dirty |= FD_DIRTY_RASTERIZER;
+
+ /* if scissor enable bit changed we need to mark scissor
+* state as dirty as well:
+* NOTE: we can do a shallow compare, since we only care
+* if it changed to/from ctx-disable_scissor
+*/
+ if (old_scissor != fd_context_get_scissor(ctx))
+ ctx-dirty |= FD_DIRTY_SCISSOR;
}
static void
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Mesa (master): freedreno: clear vs scissor
Module: Mesa
Branch: master
Commit: 01b757e2b0fb97a146b0ef278b449cecab0d15e8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=01b757e2b0fb97a146b0ef278b449cecab0d15e8
Author: Rob Clark robcl...@freedesktop.org
Date: Tue Oct 21 10:30:49 2014 -0400
freedreno: clear vs scissor
The optimization of avoiding restore (mem2gmem) if there was a clear
falls down a bit if you don't have a fullscreen scissor. We need to
make the decision logic a bit more clever to keep track of *what* was
cleared, so that we can (a) completely skip mem2gmem if entire buffer
was cleared, or (b) skip mem2gmem on a per-tile basis for tiles that
were completely cleared.
Signed-off-by: Rob Clark robcl...@freedesktop.org
---
src/gallium/drivers/freedreno/a2xx/fd2_gmem.c |4 +-
src/gallium/drivers/freedreno/a3xx/fd3_gmem.c |4 +-
src/gallium/drivers/freedreno/freedreno_context.c |4 +-
src/gallium/drivers/freedreno/freedreno_context.h | 14 +-
src/gallium/drivers/freedreno/freedreno_draw.c| 28 ++--
src/gallium/drivers/freedreno/freedreno_gmem.c| 48 -
src/gallium/drivers/freedreno/freedreno_gmem.h|7 ++-
7 files changed, 96 insertions(+), 13 deletions(-)
diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
b/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
index 274b614..e0aae1c 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c
@@ -317,10 +317,10 @@ fd2_emit_tile_mem2gmem(struct fd_context *ctx, struct
fd_tile *tile)
OUT_RING(ring, CP_REG(REG_A2XX_PA_CL_CLIP_CNTL));
OUT_RING(ring, 0x);
- if (ctx-restore (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
+ if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_DEPTH |
FD_BUFFER_STENCIL))
emit_mem2gmem_surf(ctx, bin_w * bin_h, pfb-zsbuf);
- if (ctx-restore FD_BUFFER_COLOR)
+ if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_COLOR))
emit_mem2gmem_surf(ctx, 0, pfb-cbufs[0]);
/* TODO blob driver seems to toss in a CACHE_FLUSH after each
DRAW_INDX.. */
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
index 2eefa91..f454db2 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c
@@ -566,10 +566,10 @@ fd3_emit_tile_mem2gmem(struct fd_context *ctx, struct
fd_tile *tile)
bin_w = gmem-bin_w;
bin_h = gmem-bin_h;
- if (ctx-restore (FD_BUFFER_DEPTH | FD_BUFFER_STENCIL))
+ if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_DEPTH |
FD_BUFFER_STENCIL))
emit_mem2gmem_surf(ctx, depth_base(ctx), pfb-zsbuf, bin_w);
- if (ctx-restore FD_BUFFER_COLOR)
+ if (fd_gmem_needs_restore(ctx, tile, FD_BUFFER_COLOR))
emit_mem2gmem_surf(ctx, 0, pfb-cbufs[0], bin_w);
OUT_PKT0(ring, REG_A3XX_GRAS_SC_CONTROL, 1);
diff --git a/src/gallium/drivers/freedreno/freedreno_context.c
b/src/gallium/drivers/freedreno/freedreno_context.c
index 3a8545f..f7e63fd 100644
--- a/src/gallium/drivers/freedreno/freedreno_context.c
+++ b/src/gallium/drivers/freedreno/freedreno_context.c
@@ -100,7 +100,7 @@ fd_context_render(struct pipe_context *pctx)
if (!ctx-needs_flush)
return;
- fd_gmem_render_tiles(pctx);
+ fd_gmem_render_tiles(ctx);
DBG(%p/%p/%p, ctx-ring-start, ctx-ring-cur, ctx-ring-end);
@@ -111,7 +111,7 @@ fd_context_render(struct pipe_context *pctx)
fd_context_next_rb(pctx);
ctx-needs_flush = false;
- ctx-cleared = ctx-restore = ctx-resolve = 0;
+ ctx-cleared = ctx-partial_cleared = ctx-restore = ctx-resolve = 0;
ctx-gmem_reason = 0;
ctx-num_draws = 0;
diff --git a/src/gallium/drivers/freedreno/freedreno_context.h
b/src/gallium/drivers/freedreno/freedreno_context.h
index be2c263..22d950c 100644
--- a/src/gallium/drivers/freedreno/freedreno_context.h
+++ b/src/gallium/drivers/freedreno/freedreno_context.h
@@ -182,6 +182,10 @@ struct fd_context {
* there was a glClear() that invalidated the entire previous buffer
* contents. Keep track of which buffer(s) are cleared, or needs
* restore. Masks of PIPE_CLEAR_*
+*
+* The 'cleared' bits will be set for buffers which are *entirely*
+* cleared, and 'partial_cleared' bits will be set if you must
+* check cleared_scissor.
*/
enum {
/* align bitmask values w/ PIPE_CLEAR_*.. since that is
convenient.. */
@@ -189,7 +193,7 @@ struct fd_context {
FD_BUFFER_DEPTH = PIPE_CLEAR_DEPTH,
FD_BUFFER_STENCIL = PIPE_CLEAR_STENCIL,
FD_BUFFER_ALL = FD_BUFFER_COLOR | FD_BUFFER_DEPTH |
FD_BUFFER_STENCIL,
- } cleared, restore, resolve;
+ } cleared, partial_cleared, restore, resolve;
bool needs_flush;
@@ -276,6
Mesa (master): glsl: Delete unused gl_uniform_driver_format enum values.
Module: Mesa
Branch: master
Commit: 32364a1fe58a09914daf4eef96674969167665d7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=32364a1fe58a09914daf4eef96674969167665d7
Author: Kenneth Graunke kenn...@whitecape.org
Date: Thu Oct 16 09:28:42 2014 -0700
glsl: Delete unused gl_uniform_driver_format enum values.
A while back, Matt made the uniform upload functions simply upload
ctx-Const.UniformBooleanTrue for boolean values instead of 0/1, which
removed the need to convert it later. We also set UniformBooleanTrue to
1.0f for drivers which want to treat booleans as 0.0/1.0f.
Nothing ever sets these, so they are dead.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Tapani Pälli tapani.pa...@intel.com
Reviewed-by: Matt Turner matts...@gmail.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/glsl/ir_uniform.h | 11 ---
src/mesa/main/uniform_query.cpp | 27 ++-
2 files changed, 2 insertions(+), 36 deletions(-)
diff --git a/src/glsl/ir_uniform.h b/src/glsl/ir_uniform.h
index 2f73528..b9ecf7c 100644
--- a/src/glsl/ir_uniform.h
+++ b/src/glsl/ir_uniform.h
@@ -45,17 +45,6 @@ extern C {
enum PACKED gl_uniform_driver_format {
uniform_native = 0, /** Store data in the native format. */
uniform_int_float, /** Store integer data as floats. */
- uniform_bool_float, /** Store boolean data as floats. */
-
- /**
-* Store boolean data as integer using 1 for \c true.
-*/
- uniform_bool_int_0_1,
-
- /**
-* Store boolean data as integer using ~0 for \c true.
-*/
- uniform_bool_int_0_not0
};
struct gl_uniform_driver_storage {
diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp
index c2776c0..db97d3d 100644
--- a/src/mesa/main/uniform_query.cpp
+++ b/src/mesa/main/uniform_query.cpp
@@ -533,8 +533,7 @@ _mesa_propagate_uniforms_to_driver_storage(struct
gl_uniform_storage *uni,
dst += array_index * store-element_stride;
switch (store-format) {
- case uniform_native:
- case uniform_bool_int_0_1: {
+ case uniform_native: {
unsigned j;
unsigned v;
@@ -550,8 +549,7 @@ _mesa_propagate_uniforms_to_driver_storage(struct
gl_uniform_storage *uni,
break;
}
- case uniform_int_float:
- case uniform_bool_float: {
+ case uniform_int_float: {
const int *isrc = (const int *) src;
unsigned j;
unsigned v;
@@ -572,27 +570,6 @@ _mesa_propagate_uniforms_to_driver_storage(struct
gl_uniform_storage *uni,
break;
}
- case uniform_bool_int_0_not0: {
-const int *isrc = (const int *) src;
-unsigned j;
-unsigned v;
-unsigned c;
-
-for (j = 0; j count; j++) {
- for (v = 0; v vectors; v++) {
- for (c = 0; c components; c++) {
- ((int *) dst)[c] = *isrc == 0 ? 0 : ~0;
- isrc++;
- }
-
- dst += store-vector_stride;
- }
-
- dst += extra_stride;
-}
-break;
- }
-
default:
assert(!Should not get here.);
break;
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Mesa (master): i965/vec4: Generate better code for ir_triop_csel.
Module: Mesa
Branch: master
Commit: 6dc6e6e0d979aa666e2934ae40477195e4d37ceb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6dc6e6e0d979aa666e2934ae40477195e4d37ceb
Author: Kenneth Graunke kenn...@whitecape.org
Date: Wed Oct 15 18:57:07 2014 -0700
i965/vec4: Generate better code for ir_triop_csel.
Previously, we generated an extra CMP instruction:
cmp.ge.f0(8)g61D g10,4,1F 0F
cmp.nz.f0(8)nullg64,4,1D 0D
(+f0) sel(8)g51F g1.40,4,1Fg20,4,1F
The first operand is always a boolean, and we want to predicate the SEL
on that. Rather than producing a boolean value and comparing it against
zero, we can just produce a condition code in the flag register.
Now we generate:
cmp.ge.f0(8)nullg10,4,1F 0F
(+f0) sel(8)g51F g1.40,4,1Fg20,4,1F
No difference in shader-db.
v2: Remember to delete the old code (thanks Matt).
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Matt Turner matts...@gmail.com
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 18 +++---
1 file changed, 15 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index d0587cd..b46879b 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -1277,6 +1277,20 @@ vec4_visitor::visit(ir_expression *ir)
dst_reg result_dst(this, ir-type);
src_reg result_src(result_dst);
+ if (ir-operation == ir_triop_csel) {
+ ir-operands[1]-accept(this);
+ op[1] = this-result;
+ ir-operands[2]-accept(this);
+ op[2] = this-result;
+
+ enum brw_predicate predicate;
+ emit_bool_to_cond_code(ir-operands[0], predicate);
+ inst = emit(BRW_OPCODE_SEL, result_dst, op[1], op[2]);
+ inst-predicate = predicate;
+ this-result = result_src;
+ return;
+ }
+
for (operand = 0; operand ir-get_num_operands(); operand++) {
this-result.file = BAD_FILE;
ir-operands[operand]-accept(this);
@@ -1780,9 +1794,7 @@ vec4_visitor::visit(ir_expression *ir)
break;
case ir_triop_csel:
- emit(CMP(dst_null_d(), op[0], src_reg(0), BRW_CONDITIONAL_NZ));
- inst = emit(BRW_OPCODE_SEL, result_dst, op[1], op[2]);
- inst-predicate = BRW_PREDICATE_NORMAL;
+ unreachable(already handled above);
break;
case ir_triop_bfi:
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Mesa (master): i965/vec4: Simplify visit(ir_expression *)'s result_src/ dst setup.
Module: Mesa
Branch: master
Commit: f5c3f095b97dc5d8997ca448bca67b3db4d5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5c3f095b97dc5d8997ca448bca67b3db4d5
Author: Kenneth Graunke kenn...@whitecape.org
Date: Wed Oct 15 19:17:21 2014 -0700
i965/vec4: Simplify visit(ir_expression *)'s result_src/dst setup.
Using dst_reg(this, ir-type) automatically sets the writemask to the
proper size for the type; src_reg(dst_reg) preserves that. This should
be equivalent, but less code.
Note that src_reg(dst_reg) either uses SWIZZLE_ or SWIZZLE_XYZW, so
the old code did need the manual writemask adjustment, since it
constructed the registers the other way around.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Matt Turner matts...@gmail.com
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 19 ++-
1 file changed, 6 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 0b2b9ca..d0587cd 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -1259,8 +1259,6 @@ vec4_visitor::visit(ir_expression *ir)
{
unsigned int operand;
src_reg op[Elements(ir-operands)];
- src_reg result_src;
- dst_reg result_dst;
vec4_instruction *inst;
if (ir-operation == ir_binop_add) {
@@ -1273,6 +1271,12 @@ vec4_visitor::visit(ir_expression *ir)
return;
}
+ /* Storage for our result. Ideally for an assignment we'd be using
+* the actual storage for the result here, instead.
+*/
+ dst_reg result_dst(this, ir-type);
+ src_reg result_src(result_dst);
+
for (operand = 0; operand ir-get_num_operands(); operand++) {
this-result.file = BAD_FILE;
ir-operands[operand]-accept(this);
@@ -1289,19 +1293,8 @@ vec4_visitor::visit(ir_expression *ir)
assert(!ir-operands[operand]-type-is_matrix());
}
- /* Storage for our result. Ideally for an assignment we'd be using
-* the actual storage for the result here, instead.
-*/
- result_src = src_reg(this, ir-type);
- /* convenience for the emit functions below. */
- result_dst = dst_reg(result_src);
/* If nothing special happens, this is the result. */
this-result = result_src;
- /* Limit writes to the channels that will be used by result_src later.
-* This does limit this temp's use as a temporary for multi-instruction
-* sequences.
-*/
- result_dst.writemask = (1 ir-type-vector_elements) - 1;
switch (ir-operation) {
case ir_unop_logic_not:
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