Mesa (master): Revert "radeon/llvm: enable unsafe math for graphics shaders"
Module: Mesa
Branch: master
Commit: 4db985a5fa9ea985616a726b1770727309502d81
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4db985a5fa9ea985616a726b1770727309502d81
Author: Michel Dänzer
Date: Tue Feb 17 17:03:35 2015 +0900
Revert "radeon/llvm: enable unsafe math for graphics shaders"
This reverts commit 0e9cdedd2e3943bdb7f3543a3508b883b167e427.
It caused the grass to disappear in The Talos Principle.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89069
Cc: "10.5 10.4"
Reviewed-by: Tom Stellard
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeon/radeon_llvm_emit.c |4
1 file changed, 4 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_llvm_emit.c
b/src/gallium/drivers/radeon/radeon_llvm_emit.c
index 0f9dbab..624077c 100644
--- a/src/gallium/drivers/radeon/radeon_llvm_emit.c
+++ b/src/gallium/drivers/radeon/radeon_llvm_emit.c
@@ -80,10 +80,6 @@ void radeon_llvm_shader_type(LLVMValueRef F, unsigned type)
sprintf(Str, "%1d", llvm_type);
LLVMAddTargetDependentFunctionAttr(F, "ShaderType", Str);
-
- if (type != TGSI_PROCESSOR_COMPUTE) {
- LLVMAddTargetDependentFunctionAttr(F, "unsafe-fp-math", "true");
- }
}
static void init_r600_target()
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Demos (master): opengles2: fix building without X11
Module: Demos Branch: master Commit: 6f7ad3f242943242021d1c42c6ed6933b76137fd URL: http://cgit.freedesktop.org/mesa/demos/commit/?id=6f7ad3f242943242021d1c42c6ed6933b76137fd Author: Michael Olbrich Date: Thu Jan 22 18:28:08 2015 + opengles2: fix building without X11 es2_info, es2gears_x11 and es2tri require X11, so don't build them if X11 is disabled. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88618 Reviewed-by: Emil Velikov Reviewed-by: Alex Deucher --- src/egl/opengles2/Makefile.am |5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/egl/opengles2/Makefile.am b/src/egl/opengles2/Makefile.am index 41c1b80..36d6059 100644 --- a/src/egl/opengles2/Makefile.am +++ b/src/egl/opengles2/Makefile.am @@ -36,10 +36,13 @@ AM_LDFLAGS = \ if HAVE_EGL if HAVE_GLESV2 bin_PROGRAMS = \ + es2gears_screen +if HAVE_X11 +bin_PROGRAMS += \ es2_info \ - es2gears_screen \ es2gears_x11 \ es2tri +endif if HAVE_WAYLAND bin_PROGRAMS += es2gears_wayland endif ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): automake: Use AM_DISTCHECK_CONFIGURE_FLAGS
Module: Mesa Branch: master Commit: 3018c4a56aab2ac1d8d5b228e6cbf13eea68b790 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3018c4a56aab2ac1d8d5b228e6cbf13eea68b790 Author: Emil Velikov Date: Thu Feb 12 15:27:28 2015 + automake: Use AM_DISTCHECK_CONFIGURE_FLAGS Currently we use DISTCHECK_CONFIGURE_FLAGS, which is reserved for the user. As with other variables, one should use the AM_ variable within the makefile. Cc: "10.5" Signed-off-by: Emil Velikov Reviewed-by: Matt Turner --- Makefile.am |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile.am b/Makefile.am index ccf9ac9..f4f0912 100644 --- a/Makefile.am +++ b/Makefile.am @@ -21,7 +21,7 @@ SUBDIRS = src -DISTCHECK_CONFIGURE_FLAGS = \ +AM_DISTCHECK_CONFIGURE_FLAGS = \ --enable-dri3 \ --enable-gallium-tests \ --enable-gbm \ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glx: do not leak the dri2 extension information
Module: Mesa Branch: master Commit: b0eada1707f0b7b4346663b98a7fb1a803580327 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0eada1707f0b7b4346663b98a7fb1a803580327 Author: Emil Velikov Date: Thu Jan 22 17:35:40 2015 + glx: do not leak the dri2 extension information The XExtensionInfo is allocated dynamically (if the pointer is NULL) in the XEXT_GENERATE_FIND_DISPLAY macro. On the other hand the macro XEXT_GENERATE_CLOSE_DISPLAY does not check/free the memory. Follow the example set by dri1 and appledri, and use a static variable. Spotted while hunting "still reachable" leaks in Waffle. Signed-off-by: Emil Velikov --- src/glx/dri2.c |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/glx/dri2.c b/src/glx/dri2.c index cc6c164..9ebd00a 100644 --- a/src/glx/dri2.c +++ b/src/glx/dri2.c @@ -53,7 +53,8 @@ static char dri2ExtensionName[] = DRI2_NAME; -static XExtensionInfo *dri2Info; +static XExtensionInfo _dri2Info_data; +static XExtensionInfo *dri2Info = &_dri2Info_data; static XEXT_GENERATE_CLOSE_DISPLAY (DRI2CloseDisplay, dri2Info) static Bool ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): auxiliary/vl: honour the DRI2PROTO_CFLAGS
Module: Mesa Branch: master Commit: 8a71fd8d49c6a086f9b7697bca3b1f3ae035121a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8a71fd8d49c6a086f9b7697bca3b1f3ae035121a Author: Emil Velikov Date: Mon Feb 16 19:11:33 2015 + auxiliary/vl: honour the DRI2PROTO_CFLAGS Otherwise for non-default installations the build will fail to find the headers and error out. Cc: "10.5" Signed-off-by: Emil Velikov --- src/gallium/auxiliary/Makefile.am |1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/auxiliary/Makefile.am b/src/gallium/auxiliary/Makefile.am index 6a628e9..4b62057 100644 --- a/src/gallium/auxiliary/Makefile.am +++ b/src/gallium/auxiliary/Makefile.am @@ -56,6 +56,7 @@ if NEED_GALLIUM_VL COMMON_VL_CFLAGS = \ $(AM_CFLAGS) \ $(VL_CFLAGS) \ + $(DRI2PROTO_CFLAGS) \ $(LIBDRM_CFLAGS) \ $(GALLIUM_PIPE_LOADER_DEFINES) \ -DPIPE_SEARCH_DIR=\"$(libdir)/gallium-pipe\" ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): auxiliary/vl: Build vl_winsys_dri.c only when needed.
Module: Mesa Branch: master Commit: dd7b6670a29ff3ed48ba44a9fecd1890363d914f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd7b6670a29ff3ed48ba44a9fecd1890363d914f Author: Emil Velikov Date: Mon Feb 16 18:22:16 2015 + auxiliary/vl: Build vl_winsys_dri.c only when needed. With commit c39dbfdd0f7(auxiliary/vl: bring back the VL code for the dri targets) we did not fully consider users of dri-swrast alone. Thus we ended up trying to compile the dri2 specific code on platform which lack it - Cygwin for example. Cc: "10.5" Reported-by: Jon TURNEY Signed-off-by: Emil Velikov Reviewed-by: Jon TURNEY --- configure.ac | 10 +- src/gallium/auxiliary/Makefile.am |4 2 files changed, 13 insertions(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 21e396e..beb7a7d 100644 --- a/configure.ac +++ b/configure.ac @@ -1577,11 +1577,19 @@ if test "x$enable_dri" = xyes -o \ "x$enable_vdpau" = xyes -o \ "x$enable_omx" = xyes -o \ "x$enable_va" = xyes; then -PKG_CHECK_MODULES([VL], [x11-xcb xcb xcb-dri2 >= $XCBDRI2_REQUIRED]) need_gallium_vl=yes fi AM_CONDITIONAL(NEED_GALLIUM_VL, test "x$need_gallium_vl" = xyes) +if test "x$enable_xvmc" = xyes -o \ +"x$enable_vdpau" = xyes -o \ +"x$enable_omx" = xyes -o \ +"x$enable_va" = xyes; then +PKG_CHECK_MODULES([VL], [x11-xcb xcb xcb-dri2 >= $XCBDRI2_REQUIRED]) +need_gallium_vl_winsys=yes +fi +AM_CONDITIONAL(NEED_GALLIUM_VL_WINSYS, test "x$need_gallium_vl_winsys" = xyes) + if test "x$enable_xvmc" = xyes; then PKG_CHECK_MODULES([XVMC], [xvmc >= $XVMC_REQUIRED]) enable_gallium_loader=$enable_shared_pipe_drivers diff --git a/src/gallium/auxiliary/Makefile.am b/src/gallium/auxiliary/Makefile.am index 453282a..6a628e9 100644 --- a/src/gallium/auxiliary/Makefile.am +++ b/src/gallium/auxiliary/Makefile.am @@ -74,6 +74,8 @@ libgalliumvl_la_CFLAGS = \ libgalliumvl_la_SOURCES = \ $(VL_SOURCES) +if NEED_GALLIUM_VL_WINSYS + noinst_LTLIBRARIES += libgalliumvlwinsys.la libgalliumvlwinsys_la_CFLAGS = \ @@ -84,6 +86,8 @@ libgalliumvlwinsys_la_SOURCES = \ endif +endif + EXTRA_DIST = \ SConscript \ indices/u_indices.c \ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i915: For the love of all that is holy, stop saying "IGD"
Module: Mesa Branch: master Commit: b290330e3b78405424a907cf6e82cef531c71c50 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b290330e3b78405424a907cf6e82cef531c71c50 Author: Adam Jackson Date: Wed Jan 28 16:28:12 2015 -0500 i915: For the love of all that is holy, stop saying "IGD" a001 and a011 are pineview chips. Say so. Reviewed-by: Matt Turner Signed-off-by: Adam Jackson --- include/pci_ids/i915_pci_ids.h|4 ++-- src/mesa/drivers/dri/i915/intel_chipset.h | 14 +++--- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/include/pci_ids/i915_pci_ids.h b/include/pci_ids/i915_pci_ids.h index 7d51975..1c43c8e 100644 --- a/include/pci_ids/i915_pci_ids.h +++ b/include/pci_ids/i915_pci_ids.h @@ -11,5 +11,5 @@ CHIPSET(0x27AE, I945_GME, "Intel(R) 945GME") CHIPSET(0x29B2, Q35_G,"Intel(R) Q35") CHIPSET(0x29C2, G33_G,"Intel(R) G33") CHIPSET(0x29D2, Q33_G,"Intel(R) Q33") -CHIPSET(0xA011, IGD_GM, "Intel(R) IGD") -CHIPSET(0xA001, IGD_G,"Intel(R) IGD") +CHIPSET(0xA011, PNV_GM, "Intel(R) Pineview M") +CHIPSET(0xA001, PNV_G,"Intel(R) Pineview") diff --git a/src/mesa/drivers/dri/i915/intel_chipset.h b/src/mesa/drivers/dri/i915/intel_chipset.h index 8375a4b..3828085 100644 --- a/src/mesa/drivers/dri/i915/intel_chipset.h +++ b/src/mesa/drivers/dri/i915/intel_chipset.h @@ -46,12 +46,12 @@ #define PCI_CHIP_G33_G 0x29C2 #define PCI_CHIP_Q33_G 0x29D2 -#define PCI_CHIP_IGD_GM0xA011 -#define PCI_CHIP_IGD_G 0xA001 +#define PCI_CHIP_PNV_GM0xA011 +#define PCI_CHIP_PNV_G 0xA001 -#define IS_IGDGM(devid)(devid == PCI_CHIP_IGD_GM) -#define IS_IGDG(devid) (devid == PCI_CHIP_IGD_G) -#define IS_IGD(devid) (IS_IGDG(devid) || IS_IGDGM(devid)) +#define IS_PNVGM(devid)(devid == PCI_CHIP_PNV_GM) +#define IS_PNVG(devid) (devid == PCI_CHIP_PNV_G) +#define IS_PNV(devid) (IS_PNVG(devid) || IS_PNVGM(devid)) #define IS_MOBILE(devid) (devid == PCI_CHIP_I855_GM || \ devid == PCI_CHIP_I915_GM || \ @@ -60,7 +60,7 @@ devid == PCI_CHIP_I965_GM || \ devid == PCI_CHIP_I965_GME || \ devid == PCI_CHIP_GM45_GM || \ -IS_IGD(devid) || \ +IS_PNV(devid) || \ devid == PCI_CHIP_ILM_G) #define IS_915(devid) (devid == PCI_CHIP_I915_G || \ @@ -72,7 +72,7 @@ devid == PCI_CHIP_I945_GME || \ devid == PCI_CHIP_G33_G || \ devid == PCI_CHIP_Q33_G || \ -devid == PCI_CHIP_Q35_G || IS_IGD(devid)) +devid == PCI_CHIP_Q35_G || IS_PNV(devid)) #define IS_9XX(devid) (IS_915(devid) || \ IS_945(devid)) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): ilo: fix compiler warnings
Module: Mesa
Branch: master
Commit: 68573f57eeba1229a7963440428c3229c7ad7ff6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=68573f57eeba1229a7963440428c3229c7ad7ff6
Author: Chia-I Wu
Date: Tue Feb 17 16:10:10 2015 -0700
ilo: fix compiler warnings
Fix -Wmaybe-uninitialized warnings. The change to
ilo_blit_resolve_slices_for_hiz() is a potential bug fix.
---
src/gallium/drivers/ilo/ilo_blit.c | 11 ---
src/gallium/drivers/ilo/ilo_layout.c |7 ++-
src/gallium/drivers/ilo/ilo_layout.h |2 ++
3 files changed, 12 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/ilo/ilo_blit.c
b/src/gallium/drivers/ilo/ilo_blit.c
index ad6aa80..42072c2 100644
--- a/src/gallium/drivers/ilo/ilo_blit.c
+++ b/src/gallium/drivers/ilo/ilo_blit.c
@@ -190,8 +190,9 @@ ilo_blit_resolve_slices_for_hiz(struct ilo_context *ilo,
assert(!(resolve_flags & (other_writers | any_reader)));
if (!(resolve_flags & ILO_TEXTURE_CLEAR)) {
+ const uint32_t first_clear_value = ilo_texture_get_slice(tex,
+ level, first_slice)->clear_value;
bool set_clear_value = false;
- uint32_t first_clear_value;
for (i = 0; i < num_slices; i++) {
const struct ilo_texture_slice *slice =
@@ -200,12 +201,8 @@ ilo_blit_resolve_slices_for_hiz(struct ilo_context *ilo,
if (slice->flags & other_writers) {
ilo_blitter_rectlist_resolve_hiz(ilo->blitter,
res, level, first_slice + i);
-}
-else if (i == 0) {
- first_clear_value = slice->clear_value;
-}
-else if (slice->clear_value != first_clear_value &&
- (slice->flags & ILO_TEXTURE_RENDER_WRITE)) {
+} else if (slice->clear_value != first_clear_value &&
+ (slice->flags & ILO_TEXTURE_RENDER_WRITE)) {
ilo_blitter_rectlist_resolve_z(ilo->blitter,
res, level, first_slice + i);
set_clear_value = true;
diff --git a/src/gallium/drivers/ilo/ilo_layout.c
b/src/gallium/drivers/ilo/ilo_layout.c
index 73db796..881550b 100644
--- a/src/gallium/drivers/ilo/ilo_layout.c
+++ b/src/gallium/drivers/ilo/ilo_layout.c
@@ -656,7 +656,7 @@ layout_init_size_and_format(struct ilo_layout *layout,
{
const struct pipe_resource *templ = params->templ;
enum pipe_format format = templ->format;
- bool require_separate_stencil;
+ bool require_separate_stencil = false;
layout->width0 = templ->width0;
layout->height0 = templ->height0;
@@ -1101,6 +1101,11 @@ layout_calculate_hiz_size(struct ilo_layout *layout,
}
hz_height /= 2;
break;
+ default:
+ assert(!"unknown HiZ walk");
+ hz_width = 0;
+ hz_height = 0;
+ break;
}
/*
diff --git a/src/gallium/drivers/ilo/ilo_layout.h
b/src/gallium/drivers/ilo/ilo_layout.h
index 9aa2ae9..54ba2d8 100644
--- a/src/gallium/drivers/ilo/ilo_layout.h
+++ b/src/gallium/drivers/ilo/ilo_layout.h
@@ -282,6 +282,8 @@ ilo_layout_get_slice_pos(const struct ilo_layout *layout,
}
default:
assert(!"unknown layout walk type");
+ *x = 0;
+ *y = 0;
break;
}
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Mesa (master): ilo: fix PCB alloc asserts on Gen7.5 GT3
Module: Mesa Branch: master Commit: b0e26173b26b60bb3892de9e4b764f608e0e13c7 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0e26173b26b60bb3892de9e4b764f608e0e13c7 Author: Chia-I Wu Date: Wed Feb 18 13:26:29 2015 -0700 ilo: fix PCB alloc asserts on Gen7.5 GT3 GT3 has two slices and all limits are doubled. --- src/gallium/drivers/ilo/ilo_builder_3d_top.h |6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/ilo/ilo_builder_3d_top.h b/src/gallium/drivers/ilo/ilo_builder_3d_top.h index 30c787d..d359252 100644 --- a/src/gallium/drivers/ilo/ilo_builder_3d_top.h +++ b/src/gallium/drivers/ilo/ilo_builder_3d_top.h @@ -90,7 +90,9 @@ gen7_3dstate_push_constant_alloc(struct ilo_builder *builder, GEN6_RENDER_SUBTYPE_3D | subop; const uint8_t cmd_len = 2; - const int slice_count = (ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 2 : 1; + const int slice_count = ((ilo_dev_gen(builder->dev) == ILO_GEN(7.5) && + builder->dev->gt == 3) || +ilo_dev_gen(builder->dev) >= ILO_GEN(8)) ? 2 : 1; uint32_t *dw; int end; @@ -138,6 +140,8 @@ gen7_3dstate_push_constant_alloc(struct ilo_builder *builder, size = 15 * slice_count; } + assert(offset % slice_count == 0 && size % slice_count == 0); + ilo_builder_batch_pointer(builder, cmd_len, &dw); dw[0] = cmd | (cmd_len - 2); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (10.4): Revert "radeon/llvm: enable unsafe math for graphics shaders"
Module: Mesa
Branch: 10.4
Commit: dc16fb196984631d7b5c67348268a008ec988307
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc16fb196984631d7b5c67348268a008ec988307
Author: Michel Dänzer
Date: Tue Feb 17 17:03:35 2015 +0900
Revert "radeon/llvm: enable unsafe math for graphics shaders"
This reverts commit 0e9cdedd2e3943bdb7f3543a3508b883b167e427.
It caused the grass to disappear in The Talos Principle.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89069
Cc: "10.5 10.4"
Reviewed-by: Tom Stellard
Reviewed-by: Marek Olšák
(cherry picked from commit 4db985a5fa9ea985616a726b1770727309502d81)
---
src/gallium/drivers/radeon/radeon_llvm_emit.c |4
1 file changed, 4 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_llvm_emit.c
b/src/gallium/drivers/radeon/radeon_llvm_emit.c
index dc871d7..764c291 100644
--- a/src/gallium/drivers/radeon/radeon_llvm_emit.c
+++ b/src/gallium/drivers/radeon/radeon_llvm_emit.c
@@ -80,10 +80,6 @@ void radeon_llvm_shader_type(LLVMValueRef F, unsigned type)
sprintf(Str, "%1d", llvm_type);
LLVMAddTargetDependentFunctionAttr(F, "ShaderType", Str);
-
- if (type != TGSI_PROCESSOR_COMPUTE) {
- LLVMAddTargetDependentFunctionAttr(F, "unsafe-fp-math", "true");
- }
}
static void init_r600_target()
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Mesa (10.4): r600g, radeonsi: don't append to streamout buffers that haven' t been used yet
Module: Mesa
Branch: 10.4
Commit: 5c623ff07125a6c1cc4d4bfc80fe3201509daf6b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c623ff07125a6c1cc4d4bfc80fe3201509daf6b
Author: Marek Olšák
Date: Sun Feb 1 13:47:01 2015 +0100
r600g,radeonsi: don't append to streamout buffers that haven't been used yet
The FILLED_SIZE counter is uninitialized at the beginning, so we can't use it.
Instead, use offset = 0, which is what we always do when not appending.
This unexpectedly fixes spec/ARB_texture_multisample/sample-position/*.
Yes, the test does use transform feedback.
Cc: 10.3 10.4
Reviewed-by: Glenn Kennard
Reviewed-by: Michel Dänzer
(cherry picked from commit 658f1d4cfeeea84268715c07f871721df8f1b729)
---
src/gallium/drivers/radeon/r600_pipe_common.h |1 +
src/gallium/drivers/radeon/r600_streamout.c |4 +++-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index a699f45..cacf54b 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -294,6 +294,7 @@ struct r600_so_target {
/* The buffer where BUFFER_FILLED_SIZE is stored. */
struct r600_resource*buf_filled_size;
unsignedbuf_filled_size_offset;
+ boolbuf_filled_size_valid;
unsignedstride_in_dw;
};
diff --git a/src/gallium/drivers/radeon/r600_streamout.c
b/src/gallium/drivers/radeon/r600_streamout.c
index e2413c2..945735b 100644
--- a/src/gallium/drivers/radeon/r600_streamout.c
+++ b/src/gallium/drivers/radeon/r600_streamout.c
@@ -237,7 +237,7 @@ static void r600_emit_streamout_begin(struct
r600_common_context *rctx, struct r
}
}
- if (rctx->streamout.append_bitmask & (1 << i)) {
+ if (rctx->streamout.append_bitmask & (1 << i) &&
t[i]->buf_filled_size_valid) {
uint64_t va = t[i]->buf_filled_size->gpu_address +
t[i]->buf_filled_size_offset;
@@ -302,6 +302,8 @@ void r600_emit_streamout_end(struct r600_common_context
*rctx)
* buffer bound. This ensures that the primitives-emitted query
* won't increment. */
r600_write_context_reg(cs, R_028AD0_VGT_STRMOUT_BUFFER_SIZE_0 +
16*i, 0);
+
+ t[i]->buf_filled_size_valid = true;
}
rctx->streamout.begin_emitted = false;
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Mesa (10.4): i965: Use a gl_color_union for sampler border color.
Module: Mesa
Branch: 10.4
Commit: f2663112f6bf6843d5b2d27f4c4cf54abba0a6f4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2663112f6bf6843d5b2d27f4c4cf54abba0a6f4
Author: Kenneth Graunke
Date: Tue May 6 22:56:17 2014 -0700
i965: Use a gl_color_union for sampler border color.
This should have no effect, but will make it easier to implement other
bug fixes.
v2: Eliminate "unsigned one" local; just use the value where necessary.
Signed-off-by: Kenneth Graunke
Reviewed-by: Ian Romanick
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit e1e73443c572b5432ef66a923fe64b73467f411b)
---
src/mesa/drivers/dri/i965/brw_sampler_state.c | 105 -
1 file changed, 52 insertions(+), 53 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c
b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index 8363a48..b764f5e 100644
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -208,7 +208,7 @@ upload_default_color(struct brw_context *brw,
struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
struct gl_texture_object *texObj = texUnit->_Current;
struct gl_texture_image *firstImage = texObj->Image[0][texObj->BaseLevel];
- float color[4];
+ union gl_color_union color;
switch (firstImage->_BaseFormat) {
case GL_DEPTH_COMPONENT:
@@ -216,40 +216,40 @@ upload_default_color(struct brw_context *brw,
* R channel, while the hardware uses A. Spam R into all the
* channels for safety.
*/
- color[0] = sampler->BorderColor.f[0];
- color[1] = sampler->BorderColor.f[0];
- color[2] = sampler->BorderColor.f[0];
- color[3] = sampler->BorderColor.f[0];
+ color.ui[0] = sampler->BorderColor.ui[0];
+ color.ui[1] = sampler->BorderColor.ui[0];
+ color.ui[2] = sampler->BorderColor.ui[0];
+ color.ui[3] = sampler->BorderColor.ui[0];
break;
case GL_ALPHA:
- color[0] = 0.0;
- color[1] = 0.0;
- color[2] = 0.0;
- color[3] = sampler->BorderColor.f[3];
+ color.ui[0] = 0u;
+ color.ui[1] = 0u;
+ color.ui[2] = 0u;
+ color.ui[3] = sampler->BorderColor.ui[3];
break;
case GL_INTENSITY:
- color[0] = sampler->BorderColor.f[0];
- color[1] = sampler->BorderColor.f[0];
- color[2] = sampler->BorderColor.f[0];
- color[3] = sampler->BorderColor.f[0];
+ color.ui[0] = sampler->BorderColor.ui[0];
+ color.ui[1] = sampler->BorderColor.ui[0];
+ color.ui[2] = sampler->BorderColor.ui[0];
+ color.ui[3] = sampler->BorderColor.ui[0];
break;
case GL_LUMINANCE:
- color[0] = sampler->BorderColor.f[0];
- color[1] = sampler->BorderColor.f[0];
- color[2] = sampler->BorderColor.f[0];
- color[3] = 1.0;
+ color.ui[0] = sampler->BorderColor.ui[0];
+ color.ui[1] = sampler->BorderColor.ui[0];
+ color.ui[2] = sampler->BorderColor.ui[0];
+ color.ui[3] = float_as_int(1.0);
break;
case GL_LUMINANCE_ALPHA:
- color[0] = sampler->BorderColor.f[0];
- color[1] = sampler->BorderColor.f[0];
- color[2] = sampler->BorderColor.f[0];
- color[3] = sampler->BorderColor.f[3];
+ color.ui[0] = sampler->BorderColor.ui[0];
+ color.ui[1] = sampler->BorderColor.ui[0];
+ color.ui[2] = sampler->BorderColor.ui[0];
+ color.ui[3] = sampler->BorderColor.ui[3];
break;
default:
- color[0] = sampler->BorderColor.f[0];
- color[1] = sampler->BorderColor.f[1];
- color[2] = sampler->BorderColor.f[2];
- color[3] = sampler->BorderColor.f[3];
+ color.ui[0] = sampler->BorderColor.ui[0];
+ color.ui[1] = sampler->BorderColor.ui[1];
+ color.ui[2] = sampler->BorderColor.ui[2];
+ color.ui[3] = sampler->BorderColor.ui[3];
break;
}
@@ -258,18 +258,17 @@ upload_default_color(struct brw_context *brw,
* the border color alpha to 1.0 in that case.
*/
if (firstImage->_BaseFormat == GL_RGB)
- color[3] = 1.0;
+ color.ui[3] = float_as_int(1.0);
if (brw->gen >= 8) {
/* On Broadwell, the border color is represented as four 32-bit floats,
* integers, or unsigned values, interpreted according to the surface
- * format. This matches the sampler->BorderColor union exactly. Since
- * we use floats both here and in the above reswizzling code, we preserve
- * the original bit pattern. So we actually handle all three formats.
+ * format. This matches the sampler->BorderColor union exactly; just
+ * memcpy the values.
*/
- float *sdc = brw_state_batch(brw, AUB_TRACE_SAMPLER_DEFAULT_COLOR,
- 4 * 4, 64, sdc_offset);
- COPY_4FV(sdc, color);
+ uint32_t *sdc = brw_state_batch(brw, AUB_TRACE_SAMPLER_DEFAULT_COLOR,
+ 4 * 4, 64, sdc_offset);
+ memcpy(sdc, color.ui, 4 * 4);
} else if (brw->gen == 5 || brw->g
Mesa (10.4): glsl: Reduce memory consumption of copy propagation passes.
Module: Mesa
Branch: 10.4
Commit: aaa823569bdc96f1a28ad418bdd3f8a114081937
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aaa823569bdc96f1a28ad418bdd3f8a114081937
Author: Kenneth Graunke
Date: Tue Dec 16 18:33:39 2014 -0800
glsl: Reduce memory consumption of copy propagation passes.
opt_copy_propagation and opt_copy_propagation_elements create new ACP
and Kill sets each time they enter a new control flow block. For if
blocks, they also copy the entire existing ACP set contents into the
new set.
When we exit the control flow block, we discard the new sets. However,
we weren't freeing them - so they lived on until the pass finished.
This can waste a lot of memory (57MB on one pessimal shader).
This patch makes the pass allocate ACP entries using this->acp as the
memory context, and Kill entries out of this->kill. It also steals
kill entries when moving them from the inner kill list to the parent.
It then frees the lists, including their contents.
v2: Move ralloc_free(this->acp) just before this->acp = orig_acp
(suggested by Eric Anholt).
Signed-off-by: Kenneth Graunke
Reviewed-by: Eric Anholt
Reviewed-by: Ian Romanick
Cc: "10.5 10.4"
(cherry picked from commit 76960a55e6656bb0022e9c31ae7542010da130e3)
---
src/glsl/opt_copy_propagation.cpp | 15 ---
src/glsl/opt_copy_propagation_elements.cpp | 16 +---
2 files changed, 25 insertions(+), 6 deletions(-)
diff --git a/src/glsl/opt_copy_propagation.cpp
b/src/glsl/opt_copy_propagation.cpp
index 5c65af6..806027b 100644
--- a/src/glsl/opt_copy_propagation.cpp
+++ b/src/glsl/opt_copy_propagation.cpp
@@ -128,6 +128,9 @@
ir_copy_propagation_visitor::visit_enter(ir_function_signature *ir)
visit_list_elements(this, &ir->body);
+ ralloc_free(this->acp);
+ ralloc_free(this->kills);
+
this->kills = orig_kills;
this->acp = orig_acp;
this->killed_all = orig_killed_all;
@@ -215,7 +218,7 @@ ir_copy_propagation_visitor::handle_if_block(exec_list
*instructions)
/* Populate the initial acp with a copy of the original */
foreach_in_list(acp_entry, a, orig_acp) {
- this->acp->push_tail(new(this->mem_ctx) acp_entry(a->lhs, a->rhs));
+ this->acp->push_tail(new(this->acp) acp_entry(a->lhs, a->rhs));
}
visit_list_elements(this, instructions);
@@ -226,12 +229,15 @@ ir_copy_propagation_visitor::handle_if_block(exec_list
*instructions)
exec_list *new_kills = this->kills;
this->kills = orig_kills;
+ ralloc_free(this->acp);
this->acp = orig_acp;
this->killed_all = this->killed_all || orig_killed_all;
foreach_in_list(kill_entry, k, new_kills) {
kill(k->var);
}
+
+ ralloc_free(new_kills);
}
ir_visitor_status
@@ -269,6 +275,7 @@ ir_copy_propagation_visitor::visit_enter(ir_loop *ir)
exec_list *new_kills = this->kills;
this->kills = orig_kills;
+ ralloc_free(this->acp);
this->acp = orig_acp;
this->killed_all = this->killed_all || orig_killed_all;
@@ -276,6 +283,8 @@ ir_copy_propagation_visitor::visit_enter(ir_loop *ir)
kill(k->var);
}
+ ralloc_free(new_kills);
+
/* already descended into the children. */
return visit_continue_with_parent;
}
@@ -294,7 +303,7 @@ ir_copy_propagation_visitor::kill(ir_variable *var)
/* Add the LHS variable to the list of killed variables in this block.
*/
- this->kills->push_tail(new(this->mem_ctx) kill_entry(var));
+ this->kills->push_tail(new(this->kills) kill_entry(var));
}
/**
@@ -322,7 +331,7 @@ ir_copy_propagation_visitor::add_copy(ir_assignment *ir)
ir->condition = new(ralloc_parent(ir)) ir_constant(false);
this->progress = true;
} else {
-entry = new(this->mem_ctx) acp_entry(lhs_var, rhs_var);
+entry = new(this->acp) acp_entry(lhs_var, rhs_var);
this->acp->push_tail(entry);
}
}
diff --git a/src/glsl/opt_copy_propagation_elements.cpp
b/src/glsl/opt_copy_propagation_elements.cpp
index c3e55bc..353a5c6 100644
--- a/src/glsl/opt_copy_propagation_elements.cpp
+++ b/src/glsl/opt_copy_propagation_elements.cpp
@@ -156,6 +156,9 @@
ir_copy_propagation_elements_visitor::visit_enter(ir_function_signature *ir)
visit_list_elements(this, &ir->body);
+ ralloc_free(this->acp);
+ ralloc_free(this->kills);
+
this->kills = orig_kills;
this->acp = orig_acp;
this->killed_all = orig_killed_all;
@@ -173,9 +176,9 @@
ir_copy_propagation_elements_visitor::visit_leave(ir_assignment *ir)
kill_entry *k;
if (lhs)
-k = new(mem_ctx) kill_entry(var, ir->write_mask);
+k = new(this->kills) kill_entry(var, ir->write_mask);
else
-k = new(mem_ctx) kill_entry(var, ~0);
+k = new(this->kills) kill_entry(var, ~0);
kill(k);
}
@@ -334,7 +337,7 @@
ir_copy_propagation_elements_visitor::handle_if_block(exec_list *instructions)
/* Populate the initial acp with a copy of the original */
foreach_in_list(acp_entr
Mesa (10.4): main: Fixed _mesa_GetCompressedTexImage_sw to copy slices correctly.
Module: Mesa Branch: 10.4 Commit: f57b41758d13b5c6bf9ed2e2a45624210274193b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f57b41758d13b5c6bf9ed2e2a45624210274193b Author: Laura Ekstrand Date: Mon Feb 16 14:29:57 2015 -0800 main: Fixed _mesa_GetCompressedTexImage_sw to copy slices correctly. Previously array textures were not working with GetCompressedTextureImage, leading to failures in the test arb_direct_state_access/getcompressedtextureimage.c. Tested-by: Laura Ekstrand Reviewed-by: Brian Paul Cc: "10.4, 10.5" (cherry picked from commit 92163482bda87216764edc0beca3ca090678038d) --- src/mesa/main/texgetimage.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/main/texgetimage.c b/src/mesa/main/texgetimage.c index cb5f793..5dc2b40 100644 --- a/src/mesa/main/texgetimage.c +++ b/src/mesa/main/texgetimage.c @@ -729,7 +729,7 @@ _mesa_get_compressed_teximage(struct gl_context *ctx, GLubyte *src; /* map src texture buffer */ - ctx->Driver.MapTextureImage(ctx, texImage, 0, + ctx->Driver.MapTextureImage(ctx, texImage, slice, 0, 0, texImage->Width, texImage->Height, GL_MAP_READ_BIT, &src, &srcRowStride); @@ -741,7 +741,7 @@ _mesa_get_compressed_teximage(struct gl_context *ctx, src += srcRowStride; } - ctx->Driver.UnmapTextureImage(ctx, texImage, 0); + ctx->Driver.UnmapTextureImage(ctx, texImage, slice); /* Advance to next slice */ dest += store.TotalBytesPerRow * (store.TotalRowsPerSlice - store.CopyRowsPerSlice); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (10.4): st/mesa: Don' t use PIPE_USAGE_STREAM for GL_PIXEL_UNPACK_BUFFER_ARB
Module: Mesa
Branch: 10.4
Commit: e35e6773c2276b8b0a95b43703f5cdbb144e477f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e35e6773c2276b8b0a95b43703f5cdbb144e477f
Author: Michel Dänzer
Date: Thu Feb 5 12:46:04 2015 +0900
st/mesa: Don't use PIPE_USAGE_STREAM for GL_PIXEL_UNPACK_BUFFER_ARB
The latter currently implies CPU read access, so only PIPE_USAGE_STAGING
can be expected to be fast.
Mesa demos src/tests/streaming_rect on Kaveri (radeonsi):
Unpatched: 42 frames in 1.023 seconds = 41.056 FPS
Patched: 615 frames in 1.000 seconds = 615.000 FPS
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88658
Cc: "10.3 10.4"
Reviewed-by: Marek Olšák
(cherry picked from commit a338dc01866ce50bf7555ee8dc08491c7f63b585)
---
src/mesa/state_tracker/st_cb_bufferobjects.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_bufferobjects.c
b/src/mesa/state_tracker/st_cb_bufferobjects.c
index 55f3644..90f786c 100644
--- a/src/mesa/state_tracker/st_cb_bufferobjects.c
+++ b/src/mesa/state_tracker/st_cb_bufferobjects.c
@@ -256,8 +256,15 @@ st_bufferobj_data(struct gl_context *ctx,
break;
case GL_STREAM_DRAW:
case GL_STREAM_COPY:
- pipe_usage = PIPE_USAGE_STREAM;
- break;
+ /* XXX: Remove this test and fall-through when we have PBO unpacking
+ * acceleration. Right now, PBO unpacking is done by the CPU, so we
+ * have to make sure CPU reads are fast.
+ */
+ if (target != GL_PIXEL_UNPACK_BUFFER_ARB) {
+pipe_usage = PIPE_USAGE_STREAM;
+break;
+ }
+ /* fall through */
case GL_STATIC_READ:
case GL_DYNAMIC_READ:
case GL_STREAM_READ:
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Mesa (10.4): nvc0: allow holes in xfb target lists
Module: Mesa
Branch: 10.4
Commit: f76bcbb4cd3439d73552af9826aacf64069a564c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f76bcbb4cd3439d73552af9826aacf64069a564c
Author: Ilia Mirkin
Date: Sat Feb 14 01:43:31 2015 -0500
nvc0: allow holes in xfb target lists
Tested with a modified xfb-streams test which outputs to streams 0, 2,
and 3.
Signed-off-by: Ilia Mirkin
Cc: "10.4 10.5"
(cherry picked from commit 854eb06bee7d266fc739f984c1b4ebb54dac3b87)
---
src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c |9 -
src/gallium/drivers/nouveau/nvc0/nvc0_state.c|8 +---
2 files changed, 13 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
index 1000d82..516b33b 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
@@ -252,7 +252,12 @@ nvc0_tfb_validate(struct nvc0_context *nvc0)
for (b = 0; b < nvc0->num_tfbbufs; ++b) {
struct nvc0_so_target *targ = nvc0_so_target(nvc0->tfbbuf[b]);
- struct nv04_resource *buf = nv04_resource(targ->pipe.buffer);
+ struct nv04_resource *buf;
+
+ if (!targ) {
+ IMMED_NVC0(push, NVC0_3D(TFB_BUFFER_ENABLE(b)), 0);
+ continue;
+ }
if (tfb)
targ->stride = tfb->stride[b];
@@ -260,6 +265,8 @@ nvc0_tfb_validate(struct nvc0_context *nvc0)
if (!(nvc0->tfbbuf_dirty & (1 << b)))
continue;
+ buf = nv04_resource(targ->pipe.buffer);
+
if (!targ->clean)
nvc0_query_fifo_wait(push, targ->pq);
BEGIN_NVC0(push, NVC0_3D(TFB_BUFFER_ENABLE(b)), 5);
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
index 728618f..fe35302 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_state.c
@@ -1089,9 +1089,11 @@ nvc0_set_transform_feedback_targets(struct pipe_context
*pipe,
pipe_so_target_reference(&nvc0->tfbbuf[i], targets[i]);
}
for (; i < nvc0->num_tfbbufs; ++i) {
- nvc0->tfbbuf_dirty |= 1 << i;
- nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
- pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
+ if (nvc0->tfbbuf[i]) {
+ nvc0->tfbbuf_dirty |= 1 << i;
+ nvc0_so_target_save_offset(pipe, nvc0->tfbbuf[i], i, &serialize);
+ pipe_so_target_reference(&nvc0->tfbbuf[i], NULL);
+ }
}
nvc0->num_tfbbufs = num_targets;
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Mesa (10.4): get-pick-list.sh: Require explicit "10.4" for nominating stable patches
Module: Mesa Branch: 10.4 Commit: b786e6332b8baefa449ced8d81942f0045ba6df4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b786e6332b8baefa449ced8d81942f0045ba6df4 Author: Emil Velikov Date: Wed Feb 18 11:44:20 2015 + get-pick-list.sh: Require explicit "10.4" for nominating stable patches A nomination unadorned with a specific version is now interpreted as being aimed at the 10.5 branch, which was recently opened. Signed-off-by: Emil Velikov --- bin/get-pick-list.sh |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bin/get-pick-list.sh b/bin/get-pick-list.sh index 0902fd0..1a574aa 100755 --- a/bin/get-pick-list.sh +++ b/bin/get-pick-list.sh @@ -14,7 +14,7 @@ git log --reverse --grep="cherry picked from commit" origin/master..HEAD |\ sed -e 's/^[[:space:]]*(cherry picked from commit[[:space:]]*//' -e 's/)//' > already_picked # Grep for commits that were marked as a candidate for the stable tree. -git log --reverse --pretty=%H -i --grep='^\([[:space:]]*NOTE: .*[Cc]andidate\|CC:.*mesa-stable\)' HEAD..origin/master |\ +git log --reverse --pretty=%H -i --grep='^\([[:space:]]*NOTE: .*[Cc]andidate\|CC:.*10\.4.*mesa-stable\)' HEAD..origin/master |\ while read sha do # Check to see whether the patch is on the ignore list. ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (10.4): Revert use of Mesa IR optimizer for ARB_fragment_programs
Module: Mesa Branch: 10.4 Commit: c0ce908a90e23f0ebb9a2861c25bdd38a242134a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0ce908a90e23f0ebb9a2861c25bdd38a242134a Author: Carl Worth Date: Thu Feb 12 10:14:24 2015 -0800 Revert use of Mesa IR optimizer for ARB_fragment_programs Commit f82f2fb3dc770902f1657ab1c22e6004faa3afab added use of the Mesa IR optimizer for both ARB_fragment_program and ARB_vertex_program, but only justified the vertex-program portions with measured performance improvements. Meanwhile, the optimizer was seen to generate hundreds of unused immediates without discarding them, causing failures. Discard the use of the optimizer for now to fix the regression. (In the future, we anticpate things moving from Mesa IR to NIR for better optimization anyway.) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=82477 Reviewed-by: Ian Romanick CC: "10.3 10.4 10.5" (cherry picked from commit 55a57834bf912916a5e07486b32f1778b35657f6) --- src/mesa/program/arbprogparse.c |3 --- 1 file changed, 3 deletions(-) diff --git a/src/mesa/program/arbprogparse.c b/src/mesa/program/arbprogparse.c index 7dec399..53a6f37 100644 --- a/src/mesa/program/arbprogparse.c +++ b/src/mesa/program/arbprogparse.c @@ -85,9 +85,6 @@ _mesa_parse_arb_fragment_program(struct gl_context* ctx, GLenum target, return; } - if ((ctx->_Shader->Flags & GLSL_NO_OPT) == 0) - _mesa_optimize_program(ctx, &prog); - free(program->Base.String); /* Copy the relevant contents of the arb_program struct into the ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (10.4): radeonsi: small fix in SPI state
Module: Mesa
Branch: 10.4
Commit: 53041aecef1bf41ca5f0eeab0d1504f24d7b1c81
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=53041aecef1bf41ca5f0eeab0d1504f24d7b1c81
Author: Marek Olšák
Date: Wed Feb 18 11:57:43 2015 +
radeonsi: small fix in SPI state
Cc: 10.5 10.4
Reviewed-by: Michel Dänzer
(cherry picked from commit a27b74819ad375e8c0bc88e13f42c951d2b5cd6a)
[Emil Velikov: The file was renamed si_state_{shaders,draw}.c]
Signed-off-by: Emil Velikov
Conflicts:
src/gallium/drivers/radeonsi/si_state_shader.c
---
src/gallium/drivers/radeonsi/si_state_draw.c |6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 3a65371..c85b1cc 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -545,8 +545,10 @@ bcolor:
}
if (j == vsinfo->num_outputs) {
- /* No corresponding output found, load defaults into
input */
- tmp |= S_028644_OFFSET(0x20);
+ /* No corresponding output found, load defaults into
input.
+* Don't set any other bits.
+* (FLAT_SHADE=1 completely changes behavior) */
+ tmp = S_028644_OFFSET(0x20);
}
si_pm4_set_reg(pm4,
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Mesa (10.4): i965: Fix integer border color on Haswell.
Module: Mesa
Branch: 10.4
Commit: c83c5f4b69f4716822518c97a0485f217bf461b4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c83c5f4b69f4716822518c97a0485f217bf461b4
Author: Kenneth Graunke
Date: Fri Feb 6 03:39:20 2015 -0800
i965: Fix integer border color on Haswell.
+82 Piglits - 100% of border color tests now pass on Haswell.
Signed-off-by: Kenneth Graunke
Reviewed-by: Jason Ekstrand
Reviewed-by: Chris Forbes
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit 08a06b6b891df456902f5e170f1d82236d0c73d2)
---
src/mesa/drivers/dri/i965/brw_defines.h |1 +
src/mesa/drivers/dri/i965/brw_sampler_state.c | 62 +
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c |3 +
3 files changed, 66 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 53cd75e..6eda719 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -551,6 +551,7 @@
#define BRW_SURFACE_PITCH_MASK INTEL_MASK(19, 3)
#define BRW_SURFACE_TILED (1 << 1)
#define BRW_SURFACE_TILED_Y(1 << 0)
+#define HSW_SURFACE_IS_INTEGER_FORMAT (1 << 18)
/* Surface state DW4 */
#define BRW_SURFACE_MIN_LOD_SHIFT 28
diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c
b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index b764f5e..f9e2de2 100644
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -269,6 +269,68 @@ upload_default_color(struct brw_context *brw,
uint32_t *sdc = brw_state_batch(brw, AUB_TRACE_SAMPLER_DEFAULT_COLOR,
4 * 4, 64, sdc_offset);
memcpy(sdc, color.ui, 4 * 4);
+ } else if (brw->is_haswell && texObj->_IsIntegerFormat) {
+ /* Haswell's integer border color support is completely insane:
+ * SAMPLER_BORDER_COLOR_STATE is 20 DWords. The first four are
+ * for float colors. The next 12 DWords are MBZ and only exist to
+ * pad it out to a 64 byte cacheline boundary. DWords 16-19 then
+ * contain integer colors; these are only used if SURFACE_STATE
+ * has the "Integer Surface Format" bit set. Even then, the
+ * arrangement of the RGBA data devolves into madness.
+ */
+ uint32_t *sdc = brw_state_batch(brw, AUB_TRACE_SAMPLER_DEFAULT_COLOR,
+ 20 * 4, 512, sdc_offset);
+ memset(sdc, 0, 20 * 4);
+ sdc = &sdc[16];
+
+ mesa_format format = firstImage->TexFormat;
+ int bits_per_channel = _mesa_get_format_bits(format, GL_RED_BITS);
+
+ /* From the Haswell PRM, "Command Reference: Structures", Page 36:
+ * "If any color channel is missing from the surface format,
+ * corresponding border color should be programmed as zero and if
+ * alpha channel is missing, corresponding Alpha border color should
+ * be programmed as 1."
+ */
+ unsigned c[4] = { 0, 0, 0, 1 };
+ for (int i = 0; i < 4; i++) {
+ if (_mesa_format_has_color_component(format, i))
+c[i] = color.ui[i];
+ }
+
+ switch (bits_per_channel) {
+ case 8:
+ /* Copy RGBA in order. */
+ for (int i = 0; i < 4; i++)
+((uint8_t *) sdc)[i] = c[i];
+ break;
+ case 10:
+ /* R10G10B10A2_UINT is treated like a 16-bit format. */
+ case 16:
+ ((uint16_t *) sdc)[0] = c[0]; /* R -> DWord 0, bits 15:0 */
+ ((uint16_t *) sdc)[1] = c[1]; /* G -> DWord 0, bits 31:16 */
+ /* DWord 1 is Reserved/MBZ! */
+ ((uint16_t *) sdc)[4] = c[2]; /* B -> DWord 2, bits 15:0 */
+ ((uint16_t *) sdc)[5] = c[3]; /* A -> DWord 3, bits 31:16 */
+ break;
+ case 32:
+ if (firstImage->_BaseFormat == GL_RG) {
+/* Careful inspection of the tables reveals that for RG32 formats,
+ * the green channel needs to go where blue normally belongs.
+ */
+sdc[0] = c[0];
+sdc[2] = c[1];
+sdc[3] = 1;
+ } else {
+/* Copy RGBA in order. */
+for (int i = 0; i < 4; i++)
+ sdc[i] = c[i];
+ }
+ break;
+ default:
+ assert(!"Invalid number of bits per channel in integer format.");
+ break;
+ }
} else if (brw->gen == 5 || brw->gen == 6) {
struct gen5_sampler_default_color *sdc;
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
index c257cb7..10b65c2 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c
@@ -326,6 +326,9 @@ gen7_update_texture_surface(struct gl_context *ctx,
surf[3] = SET_FIELD(effective_depth - 1, BRW_SURFACE_DEPTH) |
(mt->pitch - 1);
+ if (brw->is_haswell && tObj->_IsIntegerFormat)
+ surf[3]
Mesa (10.4): mesa: fix AtomicBuffer typo in _mesa_DeleteBuffers
Module: Mesa
Branch: 10.4
Commit: 5d04b9eeedc3e22c6f6d899add0b06fc60fd6131
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d04b9eeedc3e22c6f6d899add0b06fc60fd6131
Author: Marek Olšák
Date: Tue Feb 10 01:35:23 2015 +0100
mesa: fix AtomicBuffer typo in _mesa_DeleteBuffers
Cc: 10.5 10.4 10.3
Reviewed-by: Brian Paul
(cherry picked from commit e8625a29fe0942af2876f0684b06c6ed01939227)
---
src/mesa/main/bufferobj.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index 2bae1bc..1dc7e69 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -1226,7 +1226,7 @@ _mesa_DeleteBuffers(GLsizei n, const GLuint *ids)
}
}
- if (ctx->UniformBuffer == bufObj) {
+ if (ctx->AtomicBuffer == bufObj) {
_mesa_BindBuffer( GL_ATOMIC_COUNTER_BUFFER, 0 );
}
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Mesa (10.4): radeonsi: fix instanced arrays with non-zero start instance
Module: Mesa Branch: 10.4 Commit: 51bdd19c97ea6193582af45149c449426797b01d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=51bdd19c97ea6193582af45149c449426797b01d Author: Marek Olšák Date: Sat Jan 31 19:00:44 2015 +0100 radeonsi: fix instanced arrays with non-zero start instance Fixes piglit ARB_base_instance/arb_base_instance-drawarrays. Cc: 10.3 10.4 Reviewed-by: Michel Dänzer (cherry picked from commit 50908a89188ee7f079551622cbc8a37c04e8e8ac) --- src/gallium/drivers/radeonsi/si_shader.c |6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 541e733..c15e8111 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -228,14 +228,14 @@ static LLVMValueRef get_instance_index_for_fetch( LLVMValueRef result = LLVMGetParam(radeon_bld->main_fn, si_shader_ctx->param_instance_id); - result = LLVMBuildAdd(gallivm->builder, result, LLVMGetParam( - radeon_bld->main_fn, SI_PARAM_START_INSTANCE), ""); + /* The division must be done before START_INSTANCE is added. */ if (divisor > 1) result = LLVMBuildUDiv(gallivm->builder, result, lp_build_const_int32(gallivm, divisor), ""); - return result; + return LLVMBuildAdd(gallivm->builder, result, LLVMGetParam( + radeon_bld->main_fn, SI_PARAM_START_INSTANCE), ""); } static void declare_input_vs( ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (10.4): radeonsi: fix a crash if a stencil ref state is set before a DSA state
Module: Mesa
Branch: 10.4
Commit: 67ac6a39516ad073b098855305ea5c9e9bf508e1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=67ac6a39516ad073b098855305ea5c9e9bf508e1
Author: Marek Olšák
Date: Sun Feb 15 18:12:06 2015 +0100
radeonsi: fix a crash if a stencil ref state is set before a DSA state
+ minor indentation fixes
Discovered by Axel Davy.
This can't be reproduced with any app, because all state trackers set a DSA
state first.
Cc: 10.5 10.4 10.3
Reviewed-by: Axel Davy
(cherry picked from commit 2ead74888a70481aa40b5b6ede42279e1917e66c)
---
src/gallium/drivers/radeonsi/si_state.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index edd179e..ac669fc 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -697,12 +697,16 @@ static void si_delete_rs_state(struct pipe_context *ctx,
void *state)
*/
static void si_update_dsa_stencil_ref(struct si_context *sctx)
{
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4;
struct pipe_stencil_ref *ref = &sctx->stencil_ref;
-struct si_state_dsa *dsa = sctx->queued.named.dsa;
+ struct si_state_dsa *dsa = sctx->queued.named.dsa;
-if (pm4 == NULL)
-return;
+ if (!dsa)
+ return;
+
+ pm4 = CALLOC_STRUCT(si_pm4_state);
+ if (pm4 == NULL)
+ return;
si_pm4_set_reg(pm4, R_028430_DB_STENCILREFMASK,
S_028430_STENCILTESTVAL(ref->ref_value[0]) |
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Mesa (10.4): st/mesa: treat resource-less xfb buffers as if they weren' t there
Module: Mesa
Branch: 10.4
Commit: 89289934fce2e792b792347f946496ced461f8e2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=89289934fce2e792b792347f946496ced461f8e2
Author: Ilia Mirkin
Date: Sat Feb 14 01:27:19 2015 -0500
st/mesa: treat resource-less xfb buffers as if they weren't there
If a transform feedback buffer's size is 0, st_bufferobj_data doesn't
end up creating a buffer for it. There's no point in trying to write to
such a buffer, so just pretend as if it's not really there.
This fixes arb_gpu_shader5-xfb-streams-without-invocations on nvc0.
Signed-off-by: Ilia Mirkin
Reviewed-by: Marek Olšák
Cc: "10.4 10.5"
(cherry picked from commit 80d373ed5b1d90a5e71747ee5b8951baac62f750)
---
src/mesa/state_tracker/st_cb_xformfb.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/state_tracker/st_cb_xformfb.c
b/src/mesa/state_tracker/st_cb_xformfb.c
index 8f75eda..a2bd86a 100644
--- a/src/mesa/state_tracker/st_cb_xformfb.c
+++ b/src/mesa/state_tracker/st_cb_xformfb.c
@@ -122,7 +122,7 @@ st_begin_transform_feedback(struct gl_context *ctx, GLenum
mode,
for (i = 0; i < max_num_targets; i++) {
struct st_buffer_object *bo = st_buffer_object(sobj->base.Buffers[i]);
- if (bo) {
+ if (bo && bo->buffer) {
/* Check whether we need to recreate the target. */
if (!sobj->targets[i] ||
sobj->targets[i] == sobj->draw_count ||
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Mesa (10.4): nvc0: bail out of 2d blits with non-A8_UNORM alpha formats
Module: Mesa
Branch: 10.4
Commit: dbf82d753b21ad6e8deefe745cf827e0d97bb638
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dbf82d753b21ad6e8deefe745cf827e0d97bb638
Author: Ilia Mirkin
Date: Fri Feb 13 23:21:36 2015 -0500
nvc0: bail out of 2d blits with non-A8_UNORM alpha formats
This fixes the teximage-colors uploads with GL_ALPHA format and
non-GL_UNSIGNED_BYTE type.
Signed-off-by: Ilia Mirkin
Cc: "10.4 10.5"
(cherry picked from commit 68e4f3f572b1e629f32a73ae618dc0b016f631b1)
---
src/gallium/drivers/nouveau/nvc0/nvc0_surface.c |7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
index 17fe66d..b142156 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_surface.c
@@ -1401,11 +1401,14 @@ nvc0_blit(struct pipe_context *pipe, const struct
pipe_blit_info *info)
} else
if (!nv50_2d_src_format_faithful(info->src.format)) {
if (!util_format_is_luminance(info->src.format)) {
+if (!nv50_2d_dst_format_ops_supported(info->dst.format))
+ eng3d = TRUE;
+else
if (util_format_is_intensity(info->src.format))
eng3d = info->src.format != PIPE_FORMAT_I8_UNORM;
else
-if (!nv50_2d_dst_format_ops_supported(info->dst.format))
- eng3d = TRUE;
+if (util_format_is_alpha(info->src.format))
+ eng3d = info->src.format != PIPE_FORMAT_A8_UNORM;
else
eng3d = !nv50_2d_format_supported(info->src.format);
}
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Mesa (10.4): i965: Override swizzles for integer luminance formats.
Module: Mesa
Branch: 10.4
Commit: 2ad93851ff3f3bd44867fad6e28798a367417cb1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ad93851ff3f3bd44867fad6e28798a367417cb1
Author: Kenneth Graunke
Date: Fri Feb 6 02:06:27 2015 -0800
i965: Override swizzles for integer luminance formats.
The hardware's integer luminance formats are completely unusable;
currently we fall back to RGBA. This means we need to override
the texture swizzle to obtain the XXX1 values expected for luminance
formats.
Fixes spec/EXT_texture_integer/texwrap formats bordercolor [swizzled]
on Broadwell - 100% of border color tests now pass on Broadwell.
Signed-off-by: Kenneth Graunke
Reviewed-by: Ian Romanick
Reviewed-by: Chris Forbes
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit 8cb18760cccf2c89d94c50ff14b330ec2d5c4a3c)
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c |8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index b38eba1..cb0e13d 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -199,6 +199,14 @@ brw_get_texture_swizzle(const struct gl_context *ctx,
swizzles[1] = SWIZZLE_ZERO;
swizzles[2] = SWIZZLE_ZERO;
break;
+ case GL_LUMINANCE:
+ if (t->_IsIntegerFormat) {
+ swizzles[0] = SWIZZLE_X;
+ swizzles[1] = SWIZZLE_X;
+ swizzles[2] = SWIZZLE_X;
+ swizzles[3] = SWIZZLE_ONE;
+ }
+ break;
case GL_RED:
case GL_RG:
case GL_RGB:
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Mesa (master): i965/simd8vs: Fix SIMD8 atomics (read-only)
Module: Mesa
Branch: master
Commit: 4a95be9772a255776309f23180519a4a8560f2dd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a95be9772a255776309f23180519a4a8560f2dd
Author: Jordan Justen
Date: Tue Feb 17 09:57:35 2015 -0800
i965/simd8vs: Fix SIMD8 atomics (read-only)
An update for d9cd982d556be560af3bcbcdaf62b6b93eb934a5.
A similar change was needed for CS to allow the piglit test
tests/spec/arb_compute_shader/execution/simple-barrier-atomics.shader_test
to pass.
The previous change (d9cd982d) should fix cases that write atomics,
such as atomicCounterIncrement, and this change will fix cases than
only read atomics, such as atomicCounter.
Signed-off-by: Jordan Justen
Reviewed-by: Ben Widawsky
Reviewed-by: Francisco Jerez
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index a760114..24cc118 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -3037,9 +3037,6 @@ void
fs_visitor::emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
fs_reg offset)
{
- bool uses_kill =
- (stage == MESA_SHADER_FRAGMENT) &&
- ((brw_wm_prog_data*) this->prog_data)->uses_kill;
int reg_width = dispatch_width / 8;
fs_reg *sources = ralloc_array(mem_ctx, fs_reg, 2);
@@ -3049,13 +3046,24 @@ fs_visitor::emit_untyped_surface_read(unsigned
surf_index, fs_reg dst,
emit(MOV(sources[0], fs_reg(0u)))
->force_writemask_all = true;
- if (uses_kill) {
- emit(MOV(component(sources[0], 7), brw_flag_reg(0, 1)))
- ->force_writemask_all = true;
+ if (stage == MESA_SHADER_FRAGMENT) {
+ if (((brw_wm_prog_data*)this->prog_data)->uses_kill) {
+ emit(MOV(component(sources[0], 7), brw_flag_reg(0, 1)))
+->force_writemask_all = true;
+ } else {
+ emit(MOV(component(sources[0], 7),
+ retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
+->force_writemask_all = true;
+ }
} else {
+ /* The execution mask is part of the side-band information sent together
with
+ * the message payload to the data port. It's implicitly ANDed with the
sample
+ * mask sent in the header to compute the actual set of channels that
execute
+ * the atomic operation.
+ */
+ assert(stage == MESA_SHADER_VERTEX);
emit(MOV(component(sources[0], 7),
- retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UD)))
- ->force_writemask_all = true;
+ brw_imm_ud(0xff)))->force_writemask_all = true;
}
/* Set the surface read offset. */
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Mesa (master): nir: Add a nir_shader_compiler_options struct pointed to by the shaders.
Module: Mesa
Branch: master
Commit: f90bb54734bf03be6c736812226e3f65f2e11519
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f90bb54734bf03be6c736812226e3f65f2e11519
Author: Eric Anholt
Date: Mon Feb 2 16:13:49 2015 -0800
nir: Add a nir_shader_compiler_options struct pointed to by the shaders.
This will be used to give the optimization passes a chance to customize
behavior for the particular target device.
v2: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke (v1)
---
src/glsl/nir/glsl_to_nir.cpp | 23 ++-
src/glsl/nir/nir.c |4 +++-
src/glsl/nir/nir.h | 15 +--
src/mesa/main/mtypes.h |2 ++
4 files changed, 40 insertions(+), 4 deletions(-)
diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp
index 92cfab3..bc43a75 100644
--- a/src/glsl/nir/glsl_to_nir.cpp
+++ b/src/glsl/nir/glsl_to_nir.cpp
@@ -124,11 +124,32 @@ private:
}; /* end of anonymous namespace */
+static const nir_shader_compiler_options default_options = {
+};
+
nir_shader *
glsl_to_nir(exec_list *ir, _mesa_glsl_parse_state *state,
bool native_integers)
{
- nir_shader *shader = nir_shader_create(NULL);
+ const nir_shader_compiler_options *options;
+
+ if (state) {
+ struct gl_context *ctx = state->ctx;
+ struct gl_shader_compiler_options *gl_options =
+ &ctx->Const.ShaderCompilerOptions[state->stage];
+
+ if (!gl_options->NirOptions) {
+ nir_shader_compiler_options *new_options =
+rzalloc(ctx, nir_shader_compiler_options);
+ options = gl_options->NirOptions = new_options;
+ } else {
+ options = gl_options->NirOptions;
+ }
+ } else {
+ options = &default_options;
+ }
+
+ nir_shader *shader = nir_shader_create(NULL, options);
if (state) {
shader->num_user_structures = state->num_user_structures;
diff --git a/src/glsl/nir/nir.c b/src/glsl/nir/nir.c
index b46fd30..0d8c80a 100644
--- a/src/glsl/nir/nir.c
+++ b/src/glsl/nir/nir.c
@@ -29,7 +29,7 @@
#include
nir_shader *
-nir_shader_create(void *mem_ctx)
+nir_shader_create(void *mem_ctx, const nir_shader_compiler_options *options)
{
nir_shader *shader = ralloc(mem_ctx, nir_shader);
@@ -40,6 +40,8 @@ nir_shader_create(void *mem_ctx)
shader->outputs = _mesa_hash_table_create(shader, _mesa_key_hash_string,
_mesa_key_string_equal);
+ shader->options = options;
+
shader->num_user_structures = 0;
shader->user_structures = NULL;
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index ceda977..d5253c4 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -1326,6 +1326,9 @@ typedef struct nir_function {
exec_node_data(nir_function_overload, \
exec_list_get_head(&(func)->overload_list), node)
+typedef struct nir_shader_compiler_options {
+} nir_shader_compiler_options;
+
typedef struct nir_shader {
/** hash table of name -> uniform nir_variable */
struct hash_table *uniforms;
@@ -1336,6 +1339,13 @@ typedef struct nir_shader {
/** hash table of name -> output nir_variable */
struct hash_table *outputs;
+ /** Set of driver-specific options for the shader.
+*
+* The memory for the options is expected to be kept in a single static
+* copy by the driver.
+*/
+ const struct nir_shader_compiler_options *options;
+
/** list of global variables in the shader */
struct exec_list globals;
@@ -1361,12 +1371,13 @@ typedef struct nir_shader {
unsigned num_inputs, num_uniforms, num_outputs;
} nir_shader;
-#define nir_foreach_overload(shader, overload) \
+#define nir_foreach_overload(shader, overload)\
foreach_list_typed(nir_function, func, node, &(shader)->functions) \
foreach_list_typed(nir_function_overload, overload, node, \
&(func)->overload_list)
-nir_shader *nir_shader_create(void *mem_ctx);
+nir_shader *nir_shader_create(void *mem_ctx,
+ const nir_shader_compiler_options *options);
/** creates a register, including assigning it an index and adding it to the
list */
nir_register *nir_global_reg_create(nir_shader *shader);
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 05e9575..8d2bd74 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -3034,6 +3034,8 @@ struct gl_shader_compiler_options
GLboolean OptimizeForAOS;
struct gl_sl_pragmas DefaultPragmas; /**< Default #pragma settings */
+
+ struct nir_shader_compiler_options *NirOptions;
};
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Mesa (master): nir: Add a flag for lowering ffma.
Module: Mesa
Branch: master
Commit: e5ecf8e4272522e1950d1d4318df19377bf49ae1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5ecf8e4272522e1950d1d4318df19377bf49ae1
Author: Eric Anholt
Date: Fri Jan 30 13:49:48 2015 -0800
nir: Add a flag for lowering ffma.
vc4 cse/algebraic-disabled stats:
total uniforms in shared programs: 13966 -> 13791 (-1.25%)
uniforms in affected programs: 435 -> 260 (-40.23%)
total instructions in shared programs: 44732 -> 44356 (-0.84%)
instructions in affected programs: 9599 -> 9223 (-3.92%)
v2: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke (v1)
---
src/glsl/nir/nir.h|1 +
src/glsl/nir/nir_opt_algebraic.py |3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 6448d4a..7be1abb 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -1327,6 +1327,7 @@ typedef struct nir_function {
exec_list_get_head(&(func)->overload_list), node)
typedef struct nir_shader_compiler_options {
+ bool lower_ffma;
bool lower_fpow;
bool lower_fsqrt;
/** lowers fneg and ineg to fsub and isub. */
diff --git a/src/glsl/nir/nir_opt_algebraic.py
b/src/glsl/nir/nir_opt_algebraic.py
index 8d5c03b..83a02b6 100644
--- a/src/glsl/nir/nir_opt_algebraic.py
+++ b/src/glsl/nir/nir_opt_algebraic.py
@@ -71,7 +71,8 @@ optimizations = [
(('flrp', a, b, 1.0), b),
(('flrp', a, a, b), a),
(('flrp', 0.0, a, b), ('fmul', a, b)),
- (('fadd', ('fmul', a, b), c), ('ffma', a, b, c)),
+ (('ffma', a, b, c), ('fadd', ('fmul', a, b), c), 'options->lower_ffma'),
+ (('fadd', ('fmul', a, b), c), ('ffma', a, b, c), '!options->lower_ffma'),
# Comparison simplifications
(('inot', ('flt', a, b)), ('fge', a, b)),
(('inot', ('fge', a, b)), ('flt', a, b)),
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Mesa (master): nir: Add a flag for lowering fneg/ineg.
Module: Mesa
Branch: master
Commit: 42a8ace66e539957b31ea96fe9a2aaacdb90f30e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=42a8ace66e539957b31ea96fe9a2aaacdb90f30e
Author: Eric Anholt
Date: Wed Jan 28 10:52:53 2015 -0800
nir: Add a flag for lowering fneg/ineg.
vc4 cse/algebraic-disabled stats:
total instructions in shared programs: 44911 -> 44732 (-0.40%)
instructions in affected programs: 11371 -> 11192 (-1.57%)
v2: Fix broken iabs(isub(0, a)) transformation.
v3: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke (v1)
---
src/glsl/nir/nir.h|2 ++
src/glsl/nir/nir_opt_algebraic.py | 10 ++
2 files changed, 12 insertions(+)
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 37e15ef..6448d4a 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -1329,6 +1329,8 @@ typedef struct nir_function {
typedef struct nir_shader_compiler_options {
bool lower_fpow;
bool lower_fsqrt;
+ /** lowers fneg and ineg to fsub and isub. */
+ bool lower_negate;
} nir_shader_compiler_options;
typedef struct nir_shader {
diff --git a/src/glsl/nir/nir_opt_algebraic.py
b/src/glsl/nir/nir_opt_algebraic.py
index f93757e..8d5c03b 100644
--- a/src/glsl/nir/nir_opt_algebraic.py
+++ b/src/glsl/nir/nir_opt_algebraic.py
@@ -141,6 +141,16 @@ optimizations = [
# next round of opt_algebraic, get picked up by one of the above two.
(('bcsel', '#a', b, c), ('bcsel', ('ine', 'a', 0), b, c)),
+ # Subtracts
+ (('fsub', 0.0, ('fsub', 0.0, a)), a),
+ (('isub', 0, ('isub', 0, a)), a),
+ (('fneg', a), ('fsub', 0.0, a), 'options->lower_negate'),
+ (('ineg', a), ('isub', 0, a), 'options->lower_negate'),
+ (('fadd', a, ('fsub', 0.0, b)), ('fsub', a, b)),
+ (('iadd', a, ('isub', 0, b)), ('isub', a, b)),
+ (('fabs', ('fsub', 0.0, a)), ('fabs', a)),
+ (('iabs', ('isub', 0, a)), ('iabs', a)),
+
# This one may not be exact
(('feq', ('fadd', a, b), 0.0), ('feq', a, ('fneg', b))),
]
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Mesa (master): nir: Add a flag for lowering fsat.
Module: Mesa
Branch: master
Commit: 1907a3a7ee4d756b12b6fef32a6e5ea7656436d1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1907a3a7ee4d756b12b6fef32a6e5ea7656436d1
Author: Eric Anholt
Date: Fri Jan 30 13:53:39 2015 -0800
nir: Add a flag for lowering fsat.
vc4 cse/algebraic-disabled stats:
total instructions in shared programs: 44356 -> 44354 (-0.00%)
instructions in affected programs: 55 -> 53 (-3.64%)
v2: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke (v1)
---
src/glsl/nir/nir.h|1 +
src/glsl/nir/nir_opt_algebraic.py |3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index 7be1abb..f46ec15 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -1329,6 +1329,7 @@ typedef struct nir_function {
typedef struct nir_shader_compiler_options {
bool lower_ffma;
bool lower_fpow;
+ bool lower_fsat;
bool lower_fsqrt;
/** lowers fneg and ineg to fsub and isub. */
bool lower_negate;
diff --git a/src/glsl/nir/nir_opt_algebraic.py
b/src/glsl/nir/nir_opt_algebraic.py
index 83a02b6..c7cb651 100644
--- a/src/glsl/nir/nir_opt_algebraic.py
+++ b/src/glsl/nir/nir_opt_algebraic.py
@@ -85,7 +85,8 @@ optimizations = [
(('fge', ('fneg', ('fabs', a)), 0.0), ('feq', a, 0.0)),
(('bcsel', ('flt', a, b), a, b), ('fmin', a, b)),
(('bcsel', ('flt', a, b), b, a), ('fmax', a, b)),
- (('fmin', ('fmax', a, 0.0), 1.0), ('fsat', a)),
+ (('fmin', ('fmax', a, 0.0), 1.0), ('fsat', a), '!options->lower_fsat'),
+ (('fsat', a), ('fmin', ('fmax', a, 0.0), 1.0), 'options->lower_fsat'),
# Comparison with the same args. Note that these are not done for
# the float versions because NaN always returns false on float
# inequalities.
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Mesa (master): nir: Add lowering of POW instructions if the lower flag is set.
Module: Mesa
Branch: master
Commit: ccf14bca4b892a0dffa1d8c244bfabe384d70f98
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ccf14bca4b892a0dffa1d8c244bfabe384d70f98
Author: Eric Anholt
Date: Wed Jan 28 10:32:57 2015 -0800
nir: Add lowering of POW instructions if the lower flag is set.
This could be done in a separate pass like we do in GLSL IR, but it seems
to me like having the definitions of the transformations in the two
directions next to each other makes a lot of sense.
v2: Reorder the comment about the transformation.
Reviewed-by: Kenneth Graunke
---
src/glsl/nir/nir_opt_algebraic.py |1 +
1 file changed, 1 insertion(+)
diff --git a/src/glsl/nir/nir_opt_algebraic.py
b/src/glsl/nir/nir_opt_algebraic.py
index 76917f5..b8b28f1 100644
--- a/src/glsl/nir/nir_opt_algebraic.py
+++ b/src/glsl/nir/nir_opt_algebraic.py
@@ -118,6 +118,7 @@ optimizations = [
(('fexp', ('flog', a)), a), # e^ln(a) = a
(('flog2', ('fexp2', a)), a), # lg2(2^a) = a
(('flog', ('fexp', a)), a), # ln(e^a) = a
+ (('fpow', a, b), ('fexp2', ('fmul', ('flog2', a), b)),
'options->lower_fpow'), # a^b = 2^(lg2(a)*b)
(('fexp2', ('fmul', ('flog2', a), b)), ('fpow', a, b),
'!options->lower_fpow'), # 2^(lg2(a)*b) = a^b
(('fexp', ('fmul', ('flog', a), b)), ('fpow', a, b),
'!options->lower_fpow'), # e^(ln(a)*b) = a^b
(('fpow', a, 1.0), a),
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Mesa (master): nir: Add a flag for lowering fsqrt(x) to frcp(frsqrt(x)).
Module: Mesa
Branch: master
Commit: cb95a228e81a963d77f50058c7406db0ad3bccac
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb95a228e81a963d77f50058c7406db0ad3bccac
Author: Eric Anholt
Date: Wed Jan 28 10:39:29 2015 -0800
nir: Add a flag for lowering fsqrt(x) to frcp(frsqrt(x)).
vc4 cse/algebraic-disabled stats:
total uniforms in shared programs: 13972 -> 13966 (-0.04%)
uniforms in affected programs: 408 -> 402 (-1.47%)
total instructions in shared programs: 44973 -> 44911 (-0.14%)
instructions in affected programs: 1551 -> 1489 (-4.00%)
v2: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke (v1)
---
src/glsl/nir/nir.h|1 +
src/glsl/nir/nir_opt_algebraic.py |3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index bcc51e8..37e15ef 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -1328,6 +1328,7 @@ typedef struct nir_function {
typedef struct nir_shader_compiler_options {
bool lower_fpow;
+ bool lower_fsqrt;
} nir_shader_compiler_options;
typedef struct nir_shader {
diff --git a/src/glsl/nir/nir_opt_algebraic.py
b/src/glsl/nir/nir_opt_algebraic.py
index b8b28f1..f93757e 100644
--- a/src/glsl/nir/nir_opt_algebraic.py
+++ b/src/glsl/nir/nir_opt_algebraic.py
@@ -128,7 +128,8 @@ optimizations = [
(('fdiv', 1.0, a), ('frcp', a)),
(('frcp', ('frcp', a)), a),
(('frcp', ('fsqrt', a)), ('frsq', a)),
- (('frcp', ('frsq', a)), ('fsqrt', a)),
+ (('fsqrt', a), ('frcp', ('frsq', a)), 'options->lower_fsqrt'),
+ (('frcp', ('frsq', a)), ('fsqrt', a), '!options->lower_fsqrt'),
# Boolean simplifications
(('ine', 'a@bool', 0), 'a'),
(('ieq', 'a@bool', 0), ('inot', 'a')),
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Mesa (master): nir: Conditionalize the POW reconstruction on shader compiler options.
Module: Mesa
Branch: master
Commit: 8e9dbfff17f29533ad03f3afd25ada8cb6bf1e2b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e9dbfff17f29533ad03f3afd25ada8cb6bf1e2b
Author: Eric Anholt
Date: Tue Jan 27 16:22:54 2015 -0800
nir: Conditionalize the POW reconstruction on shader compiler options.
Mesa has a shader compiler struct flagging whether GLSL IR's opt_algebraic
and other passes should try and generate certain types of opcodes or
patterns. Extend that to NIR by defining our own struct, which is
automatically generated from the Mesa struct in glsl_to_nir and provided
directly by the driver in TGSI-to-NIR.
v2: Split out the previous two prep patches.
v3: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke (v2)
---
src/glsl/nir/glsl_to_nir.cpp |3 +++
src/glsl/nir/nir.h|1 +
src/glsl/nir/nir_opt_algebraic.py |4 ++--
3 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/glsl/nir/glsl_to_nir.cpp b/src/glsl/nir/glsl_to_nir.cpp
index bc43a75..544d0d9 100644
--- a/src/glsl/nir/glsl_to_nir.cpp
+++ b/src/glsl/nir/glsl_to_nir.cpp
@@ -142,6 +142,9 @@ glsl_to_nir(exec_list *ir, _mesa_glsl_parse_state *state,
nir_shader_compiler_options *new_options =
rzalloc(ctx, nir_shader_compiler_options);
options = gl_options->NirOptions = new_options;
+
+ if (gl_options->EmitNoPow)
+new_options->lower_fpow = true;
} else {
options = gl_options->NirOptions;
}
diff --git a/src/glsl/nir/nir.h b/src/glsl/nir/nir.h
index d5253c4..bcc51e8 100644
--- a/src/glsl/nir/nir.h
+++ b/src/glsl/nir/nir.h
@@ -1327,6 +1327,7 @@ typedef struct nir_function {
exec_list_get_head(&(func)->overload_list), node)
typedef struct nir_shader_compiler_options {
+ bool lower_fpow;
} nir_shader_compiler_options;
typedef struct nir_shader {
diff --git a/src/glsl/nir/nir_opt_algebraic.py
b/src/glsl/nir/nir_opt_algebraic.py
index 83223f7..76917f5 100644
--- a/src/glsl/nir/nir_opt_algebraic.py
+++ b/src/glsl/nir/nir_opt_algebraic.py
@@ -118,8 +118,8 @@ optimizations = [
(('fexp', ('flog', a)), a), # e^ln(a) = a
(('flog2', ('fexp2', a)), a), # lg2(2^a) = a
(('flog', ('fexp', a)), a), # ln(e^a) = a
- (('fexp2', ('fmul', ('flog2', a), b)), ('fpow', a, b)), # 2^(lg2(a)*b) = a^b
- (('fexp', ('fmul', ('flog', a), b)), ('fpow', a, b)), # e^(ln(a)*b) = a^b
+ (('fexp2', ('fmul', ('flog2', a), b)), ('fpow', a, b),
'!options->lower_fpow'), # 2^(lg2(a)*b) = a^b
+ (('fexp', ('fmul', ('flog', a), b)), ('fpow', a, b),
'!options->lower_fpow'), # e^(ln(a)*b) = a^b
(('fpow', a, 1.0), a),
(('fpow', a, 2.0), ('fmul', a, a)),
(('fpow', 2.0, a), ('fexp2', a)),
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Mesa (master): nir: Add an optional expression controlling nir_algebraic xforms.
Module: Mesa
Branch: master
Commit: 955a6bb57d6ca5a679021bcfe43c7cae1863f299
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=955a6bb57d6ca5a679021bcfe43c7cae1863f299
Author: Eric Anholt
Date: Mon Feb 2 16:20:06 2015 -0800
nir: Add an optional expression controlling nir_algebraic xforms.
This will be used so that we can customize the transforms for the target
GPU, so we don't un-lower expressions that had already been lowered (or
introduce new lowering transformations that not all GPUs want)
v2: Drop the complication of having the condition->index dictionary, since
we don't actually expect there to be many different conditions (change
by Kenneth).
Reviewed-by: Kenneth Graunke
---
src/glsl/nir/nir_algebraic.py | 39 ---
1 file changed, 32 insertions(+), 7 deletions(-)
diff --git a/src/glsl/nir/nir_algebraic.py b/src/glsl/nir/nir_algebraic.py
index 4929745..afab1a0 100644
--- a/src/glsl/nir/nir_algebraic.py
+++ b/src/glsl/nir/nir_algebraic.py
@@ -147,10 +147,23 @@ class Expression(Value):
_optimization_ids = itertools.count()
+condition_list = ['true']
+
class SearchAndReplace(object):
- def __init__(self, search, replace):
+ def __init__(self, transform):
self.id = _optimization_ids.next()
+ search = transform[0]
+ replace = transform[1]
+ if len(transform) > 2:
+ self.condition = transform[2]
+ else:
+ self.condition = 'true'
+
+ if self.condition not in condition_list:
+ condition_list.append(self.condition)
+ self.condition_index = condition_list.index(self.condition)
+
varset = VarSet()
if isinstance(search, Expression):
self.search = search
@@ -171,6 +184,7 @@ _algebraic_pass_template = mako.template.Template("""
struct transform {
const nir_search_expression *search;
const nir_search_value *replace;
+ unsigned condition_offset;
};
% for (opcode, xform_list) in xform_dict.iteritems():
@@ -181,7 +195,7 @@ struct transform {
static const struct transform ${pass_name}_${opcode}_xforms[] = {
% for xform in xform_list:
- { &${xform.search.name}, ${xform.replace.c_ptr} },
+ { &${xform.search.name}, ${xform.replace.c_ptr}, ${xform.condition_index} },
% endfor
};
% endfor
@@ -189,6 +203,7 @@ static const struct transform
${pass_name}_${opcode}_xforms[] = {
struct opt_state {
void *mem_ctx;
bool progress;
+ const bool *condition_flags;
};
static bool
@@ -209,7 +224,8 @@ ${pass_name}_block(nir_block *block, void *void_state)
case nir_op_${opcode}:
for (unsigned i = 0; i < ARRAY_SIZE(${pass_name}_${opcode}_xforms);
i++) {
const struct transform *xform = &${pass_name}_${opcode}_xforms[i];
-if (nir_replace_instr(alu, xform->search, xform->replace,
+if (state->condition_flags[xform->condition_offset] &&
+nir_replace_instr(alu, xform->search, xform->replace,
state->mem_ctx)) {
state->progress = true;
break;
@@ -226,12 +242,13 @@ ${pass_name}_block(nir_block *block, void *void_state)
}
static bool
-${pass_name}_impl(nir_function_impl *impl)
+${pass_name}_impl(nir_function_impl *impl, const bool *condition_flags)
{
struct opt_state state;
state.mem_ctx = ralloc_parent(impl);
state.progress = false;
+ state.condition_flags = condition_flags;
nir_foreach_block(impl, ${pass_name}_block, &state);
@@ -242,14 +259,21 @@ ${pass_name}_impl(nir_function_impl *impl)
return state.progress;
}
+
bool
${pass_name}(nir_shader *shader)
{
bool progress = false;
+ bool condition_flags[${len(condition_list)}];
+ const nir_shader_compiler_options *options = shader->options;
+
+ % for index, condition in enumerate(condition_list):
+ condition_flags[${index}] = ${condition};
+ % endfor
nir_foreach_overload(shader, overload) {
if (overload->impl)
- progress |= ${pass_name}_impl(overload->impl);
+ progress |= ${pass_name}_impl(overload->impl, condition_flags);
}
return progress;
@@ -263,7 +287,7 @@ class AlgebraicPass(object):
for xform in transforms:
if not isinstance(xform, SearchAndReplace):
-xform = SearchAndReplace(*xform)
+xform = SearchAndReplace(xform)
if xform.search.opcode not in self.xform_dict:
self.xform_dict[xform.search.opcode] = []
@@ -272,4 +296,5 @@ class AlgebraicPass(object):
def render(self):
return _algebraic_pass_template.render(pass_name=self.pass_name,
- xform_dict=self.xform_dict)
+ xform_dict=self.xform_dict,
+ condition_list=condition_list)
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Mesa (master): nir: Recognize and reduce duplicated fsats.
Module: Mesa
Branch: master
Commit: 6eadde51bba26bc57da7b26cbb40d783259d4a5f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6eadde51bba26bc57da7b26cbb40d783259d4a5f
Author: Eric Anholt
Date: Fri Jan 30 14:10:58 2015 -0800
nir: Recognize and reduce duplicated fsats.
No effect on vc4 shader-db.
v2: Rebase to master (no TGSI->NIR present)
Reviewed-by: Kenneth Graunke (v1)
---
src/glsl/nir/nir_opt_algebraic.py |2 ++
1 file changed, 2 insertions(+)
diff --git a/src/glsl/nir/nir_opt_algebraic.py
b/src/glsl/nir/nir_opt_algebraic.py
index c7cb651..504c9f6 100644
--- a/src/glsl/nir/nir_opt_algebraic.py
+++ b/src/glsl/nir/nir_opt_algebraic.py
@@ -87,6 +87,8 @@ optimizations = [
(('bcsel', ('flt', a, b), b, a), ('fmax', a, b)),
(('fmin', ('fmax', a, 0.0), 1.0), ('fsat', a), '!options->lower_fsat'),
(('fsat', a), ('fmin', ('fmax', a, 0.0), 1.0), 'options->lower_fsat'),
+ (('fsat', ('fsat', a)), ('fsat', a)),
+ (('fmin', ('fmax', ('fmin', ('fmax', a, 0.0), 1.0), 0.0), 1.0), ('fmin',
('fmax', a, 0.0), 1.0)),
# Comparison with the same args. Note that these are not done for
# the float versions because NaN always returns false on float
# inequalities.
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Mesa (master): gallium/dri: Shut up a compiler warning.
Module: Mesa Branch: master Commit: 935ee6b652a97c1db08d999aa48eba0574e0b23e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=935ee6b652a97c1db08d999aa48eba0574e0b23e Author: Eric Anholt Date: Wed Feb 11 14:40:47 2015 -0800 gallium/dri: Shut up a compiler warning. The compiler doesn't see that buffers is set in the !image case and used in the !image case. Reviewed-by: Matt Turner --- src/gallium/state_trackers/dri/dri2.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/state_trackers/dri/dri2.c b/src/gallium/state_trackers/dri/dri2.c index aecc8eb..7d65ba3 100644 --- a/src/gallium/state_trackers/dri/dri2.c +++ b/src/gallium/state_trackers/dri/dri2.c @@ -368,7 +368,7 @@ dri2_allocate_textures(struct dri_context *ctx, /* Image specific variables */ struct __DRIimageList images; /* Dri2 specific variables */ - __DRIbuffer *buffers; + __DRIbuffer *buffers = NULL; struct winsys_handle whandle; unsigned num_buffers = statts_count; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): freedreno: add missing PIPE_CAP_RESOURCE_FROM_USER_MEMORY to switch
Module: Mesa Branch: master Commit: 069dab75765a7ea8b995eea80167ffb34cdb0034 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=069dab75765a7ea8b995eea80167ffb34cdb0034 Author: Ilia Mirkin Date: Wed Feb 18 22:36:13 2015 -0500 freedreno: add missing PIPE_CAP_RESOURCE_FROM_USER_MEMORY to switch Signed-off-by: Ilia Mirkin --- src/gallium/drivers/freedreno/freedreno_screen.c |1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index b0bdfd9..45293e4 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -233,6 +233,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_CLIP_HALFZ: case PIPE_CAP_POLYGON_OFFSET_CLAMP: case PIPE_CAP_MULTISAMPLE_Z_RESOLVE: + case PIPE_CAP_RESOURCE_FROM_USER_MEMORY: return 0; case PIPE_CAP_MAX_VIEWPORTS: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): freedreno: pass number of instances to draw
Module: Mesa Branch: master Commit: 2c6e3d822ba6f03fe208da3c6228d796895b3008 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c6e3d822ba6f03fe208da3c6228d796895b3008 Author: Ilia Mirkin Date: Wed Oct 22 00:42:04 2014 -0400 freedreno: pass number of instances to draw Signed-off-by: Ilia Mirkin --- src/gallium/drivers/freedreno/a2xx/fd2_draw.c |2 +- src/gallium/drivers/freedreno/a2xx/fd2_gmem.c |4 ++-- src/gallium/drivers/freedreno/a3xx/fd3_draw.c |4 ++-- src/gallium/drivers/freedreno/a3xx/fd3_emit.c |2 +- src/gallium/drivers/freedreno/a3xx/fd3_gmem.c | 10 +- src/gallium/drivers/freedreno/a3xx/fd3_query.c |2 +- src/gallium/drivers/freedreno/freedreno_draw.h | 10 ++ src/gallium/drivers/freedreno/freedreno_util.h |6 -- 8 files changed, 22 insertions(+), 18 deletions(-) diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_draw.c b/src/gallium/drivers/freedreno/a2xx/fd2_draw.c index 44eab7a..dfc7202 100644 --- a/src/gallium/drivers/freedreno/a2xx/fd2_draw.c +++ b/src/gallium/drivers/freedreno/a2xx/fd2_draw.c @@ -264,7 +264,7 @@ fd2_clear(struct fd_context *ctx, unsigned buffers, OUT_RING(ring, 0); /* VGT_MIN_VTX_INDX */ fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY, - DI_SRC_SEL_AUTO_INDEX, 3, INDEX_SIZE_IGN, 0, 0, NULL); + DI_SRC_SEL_AUTO_INDEX, 3, 0, INDEX_SIZE_IGN, 0, 0, NULL); OUT_PKT3(ring, CP_SET_CONSTANT, 2); OUT_RING(ring, CP_REG(REG_A2XX_A220_RB_LRZ_VSC_CONTROL)); diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c b/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c index e0aae1c..8593c4a 100644 --- a/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c +++ b/src/gallium/drivers/freedreno/a2xx/fd2_gmem.c @@ -91,7 +91,7 @@ emit_gmem2mem_surf(struct fd_context *ctx, uint32_t base, OUT_RING(ring, 0); /* VGT_MIN_VTX_INDX */ fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY, - DI_SRC_SEL_AUTO_INDEX, 3, INDEX_SIZE_IGN, 0, 0, NULL); + DI_SRC_SEL_AUTO_INDEX, 3, 0, INDEX_SIZE_IGN, 0, 0, NULL); } static void @@ -213,7 +213,7 @@ emit_mem2gmem_surf(struct fd_context *ctx, uint32_t base, OUT_RING(ring, 0); /* VGT_MIN_VTX_INDX */ fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY, - DI_SRC_SEL_AUTO_INDEX, 3, INDEX_SIZE_IGN, 0, 0, NULL); + DI_SRC_SEL_AUTO_INDEX, 3, 0, INDEX_SIZE_IGN, 0, 0, NULL); } static void diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_draw.c b/src/gallium/drivers/freedreno/a3xx/fd3_draw.c index cf704ba..179bf9c 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_draw.c +++ b/src/gallium/drivers/freedreno/a3xx/fd3_draw.c @@ -227,7 +227,7 @@ fd3_clear_binning(struct fd_context *ctx, unsigned dirty) fd_event_write(ctx, ring, PERFCOUNTER_STOP); fd_draw(ctx, ring, DI_PT_RECTLIST, IGNORE_VISIBILITY, - DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL); + DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL); } static void @@ -367,7 +367,7 @@ fd3_clear(struct fd_context *ctx, unsigned buffers, fd_event_write(ctx, ring, PERFCOUNTER_STOP); fd_draw(ctx, ring, DI_PT_RECTLIST, USE_VISIBILITY, - DI_SRC_SEL_AUTO_INDEX, 2, INDEX_SIZE_IGN, 0, 0, NULL); + DI_SRC_SEL_AUTO_INDEX, 2, 0, INDEX_SIZE_IGN, 0, 0, NULL); } void diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c index 443a59d..1c17e2d 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c +++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c @@ -781,7 +781,7 @@ fd3_emit_restore(struct fd_context *ctx) OUT_PKT3(ring, CP_DRAW_INDX, 3); OUT_RING(ring, 0x); OUT_RING(ring, DRAW(1, DI_SRC_SEL_AUTO_INDEX, - INDEX_SIZE_IGN, IGNORE_VISIBILITY)); + INDEX_SIZE_IGN, IGNORE_VISIBILITY, 0)); OUT_RING(ring, 0); /* NumIndices */ } diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c index f92cced..9b4f31c 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c +++ b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c @@ -274,7 +274,7 @@ emit_binning_workaround(struct fd_context *ctx) OUT_PKT3(ring, CP_DRAW_INDX_2, 5); OUT_RING(ring, 0x); /* viz query info. */ OUT_RING(ring, DRAW(DI_PT_RECTLIST, DI_SRC_SEL_IMMEDIATE, - INDEX_SIZE_32_BIT, IGNORE_VISIBILITY)); + INDEX_SIZE_32_BIT, IGNORE_VISIBILITY, 0)); OUT_RING(ring, 2);/* NumIndices */ OUT_RIN
Mesa (master): st/mesa: pass etc2 textures to driver if supported
Module: Mesa
Branch: master
Commit: 33edda7d975f2cbf7ba86ba0f300dcadf087fb9b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=33edda7d975f2cbf7ba86ba0f300dcadf087fb9b
Author: Ilia Mirkin
Date: Mon Feb 16 02:27:37 2015 -0500
st/mesa: pass etc2 textures to driver if supported
If the driver actually supports ETC2, don't decode it in software.
Signed-off-by: Ilia Mirkin
Reviewed-by: Marek Olšák
---
src/mesa/state_tracker/st_cb_texture.c |4 +--
src/mesa/state_tracker/st_context.c|3 +++
src/mesa/state_tracker/st_context.h|1 +
src/mesa/state_tracker/st_format.c | 43 +---
4 files changed, 40 insertions(+), 11 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_texture.c
b/src/mesa/state_tracker/st_cb_texture.c
index abc68c0..0525e87 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -211,7 +211,7 @@ st_MapTextureImage(struct gl_context *ctx,
map = st_texture_image_map(st, stImage, pipeMode, x, y, slice, w, h, 1,
&transfer);
if (map) {
- if (_mesa_is_format_etc2(texImage->TexFormat) ||
+ if ((_mesa_is_format_etc2(texImage->TexFormat) && !st->has_etc2) ||
(texImage->TexFormat == MESA_FORMAT_ETC1_RGB8 && !st->has_etc1)) {
/* ETC isn't supported by gallium and it's represented
* by uncompressed formats. Only write transfers with precompressed
@@ -254,7 +254,7 @@ st_UnmapTextureImage(struct gl_context *ctx,
struct st_context *st = st_context(ctx);
struct st_texture_image *stImage = st_texture_image(texImage);
- if (_mesa_is_format_etc2(texImage->TexFormat) ||
+ if ((_mesa_is_format_etc2(texImage->TexFormat) && !st->has_etc2) ||
(texImage->TexFormat == MESA_FORMAT_ETC1_RGB8 && !st->has_etc1)) {
/* Decompress the ETC texture to the mapped one. */
unsigned z = slice + stImage->base.Face;
diff --git a/src/mesa/state_tracker/st_context.c
b/src/mesa/state_tracker/st_context.c
index 9fd6cae..5834eba 100644
--- a/src/mesa/state_tracker/st_context.c
+++ b/src/mesa/state_tracker/st_context.c
@@ -230,6 +230,9 @@ st_create_context_priv( struct gl_context *ctx, struct
pipe_context *pipe,
st->has_etc1 = screen->is_format_supported(screen, PIPE_FORMAT_ETC1_RGB8,
PIPE_TEXTURE_2D, 0,
PIPE_BIND_SAMPLER_VIEW);
+ st->has_etc2 = screen->is_format_supported(screen, PIPE_FORMAT_ETC2_RGB8,
+ PIPE_TEXTURE_2D, 0,
+ PIPE_BIND_SAMPLER_VIEW);
st->prefer_blit_based_texture_transfer = screen->get_param(screen,
PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER);
diff --git a/src/mesa/state_tracker/st_context.h
b/src/mesa/state_tracker/st_context.h
index 20d5678..b091a88 100644
--- a/src/mesa/state_tracker/st_context.h
+++ b/src/mesa/state_tracker/st_context.h
@@ -93,6 +93,7 @@ struct st_context
boolean has_time_elapsed;
boolean has_shader_model3;
boolean has_etc1;
+ boolean has_etc2;
boolean prefer_blit_based_texture_transfer;
boolean needs_texcoord_semantic;
diff --git a/src/mesa/state_tracker/st_format.c
b/src/mesa/state_tracker/st_format.c
index 66cace1..9a91d71 100644
--- a/src/mesa/state_tracker/st_format.c
+++ b/src/mesa/state_tracker/st_format.c
@@ -443,21 +443,25 @@ st_mesa_format_to_pipe_format(struct st_context *st,
mesa_format mesaFormat)
* The destination formats mustn't be changed, because they are also
* destination formats of the unpack/decompression function. */
case MESA_FORMAT_ETC2_RGB8:
- case MESA_FORMAT_ETC2_RGBA8_EAC:
- case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1:
- return PIPE_FORMAT_R8G8B8A8_UNORM;
+ return st->has_etc2 ? PIPE_FORMAT_ETC2_RGB8 : PIPE_FORMAT_R8G8B8A8_UNORM;
case MESA_FORMAT_ETC2_SRGB8:
+ return st->has_etc2 ? PIPE_FORMAT_ETC2_SRGB8 : PIPE_FORMAT_B8G8R8A8_SRGB;
+ case MESA_FORMAT_ETC2_RGBA8_EAC:
+ return st->has_etc2 ? PIPE_FORMAT_ETC2_RGBA8 :
PIPE_FORMAT_R8G8B8A8_UNORM;
case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC:
- case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1:
- return PIPE_FORMAT_B8G8R8A8_SRGB;
+ return st->has_etc2 ? PIPE_FORMAT_ETC2_SRGBA8 :
PIPE_FORMAT_B8G8R8A8_SRGB;
case MESA_FORMAT_ETC2_R11_EAC:
- return PIPE_FORMAT_R16_UNORM;
+ return st->has_etc2 ? PIPE_FORMAT_ETC2_R11_UNORM : PIPE_FORMAT_R16_UNORM;
case MESA_FORMAT_ETC2_RG11_EAC:
- return PIPE_FORMAT_R16G16_UNORM;
+ return st->has_etc2 ? PIPE_FORMAT_ETC2_RG11_UNORM :
PIPE_FORMAT_R16G16_UNORM;
case MESA_FORMAT_ETC2_SIGNED_R11_EAC:
- return PIPE_FORMAT_R16_SNORM;
+ return st->has_etc2 ? PIPE_FORMAT_ETC2_R11_SNORM : PIPE_FORMAT_R16_SNORM;
case MESA_FORMAT_ETC2_SIGNED_RG11_EAC:
- return PIPE_FORMAT_R16G16_SNORM;
+ return st->has_etc2 ? PIPE_FORMA
Mesa (master): freedreno/a3xx: add ETC2 decoding support
Module: Mesa
Branch: master
Commit: e4ddfeea65725a6f4febe8718d7e378f50fe
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e4ddfeea65725a6f4febe8718d7e378f50fe
Author: Ilia Mirkin
Date: Mon Feb 16 02:28:50 2015 -0500
freedreno/a3xx: add ETC2 decoding support
Signed-off-by: Ilia Mirkin
---
src/gallium/drivers/freedreno/a3xx/a3xx.xml.h | 11 +++
src/gallium/drivers/freedreno/a3xx/fd3_format.c | 10 ++
2 files changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
b/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
index 0dce61c..d268f17 100644
--- a/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
+++ b/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
@@ -179,10 +179,13 @@ enum a3xx_tex_fmt {
TFMT_32_SINT = 92,
TFMT_32_32_SINT = 93,
TFMT_32_32_32_32_SINT = 95,
- TFMT_RGTC2_SNORM = 112,
- TFMT_RGTC2_UNORM = 113,
- TFMT_RGTC1_SNORM = 114,
- TFMT_RGTC1_UNORM = 115,
+ TFMT_ETC2_RG11_SNORM = 112,
+ TFMT_ETC2_RG11_UNORM = 113,
+ TFMT_ETC2_R11_SNORM = 114,
+ TFMT_ETC2_R11_UNORM = 115,
+ TFMT_ETC2_RGBA8 = 116,
+ TFMT_ETC2_RGB8A1 = 117,
+ TFMT_ETC2_RGB8 = 118,
};
enum a3xx_tex_fetchsize {
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_format.c
b/src/gallium/drivers/freedreno/a3xx/fd3_format.c
index a67d0ac..03f8d04 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_format.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_format.c
@@ -249,6 +249,16 @@ static struct fd3_format formats[PIPE_FORMAT_COUNT] = {
/* compressed */
_T(ETC1_RGB8, ETC1, NONE, WZYX),
+ _T(ETC2_RGB8, ETC2_RGB8, NONE, WZYX),
+ _T(ETC2_SRGB8, ETC2_RGB8, NONE, WZYX),
+ _T(ETC2_RGB8A1, ETC2_RGB8A1, NONE, WZYX),
+ _T(ETC2_SRGB8A1, ETC2_RGB8A1, NONE, WZYX),
+ _T(ETC2_RGBA8, ETC2_RGBA8, NONE, WZYX),
+ _T(ETC2_SRGBA8, ETC2_RGBA8, NONE, WZYX),
+ _T(ETC2_R11_UNORM, ETC2_R11_UNORM, NONE, WZYX),
+ _T(ETC2_R11_SNORM, ETC2_R11_SNORM, NONE, WZYX),
+ _T(ETC2_RG11_UNORM, ETC2_RG11_UNORM, NONE, WZYX),
+ _T(ETC2_RG11_SNORM, ETC2_RG11_SNORM, NONE, WZYX),
};
enum a3xx_vtx_fmt
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Mesa (master): gallium: add ETC2 format support
Module: Mesa
Branch: master
Commit: 0821efcb333ed2af639561f0ae77220ed4710559
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0821efcb333ed2af639561f0ae77220ed4710559
Author: Ilia Mirkin
Date: Mon Feb 16 02:25:52 2015 -0500
gallium: add ETC2 format support
No actual decoding is added, similar faking mechanism to bptc.
Signed-off-by: Ilia Mirkin
Reviewed-by: Marek Olšák
---
src/gallium/auxiliary/Makefile.sources |6 +-
src/gallium/auxiliary/util/u_format.csv| 11 ++
src/gallium/auxiliary/util/u_format_bptc.h | 109
.../util/{u_format_bptc.c => u_format_fake.c} | 13 ++-
src/gallium/auxiliary/util/u_format_fake.h | 66
src/gallium/auxiliary/util/u_format_table.py |2 +-
src/gallium/include/pipe/p_format.h| 11 ++
7 files changed, 104 insertions(+), 114 deletions(-)
diff --git a/src/gallium/auxiliary/Makefile.sources
b/src/gallium/auxiliary/Makefile.sources
index d330935..b7174d6 100644
--- a/src/gallium/auxiliary/Makefile.sources
+++ b/src/gallium/auxiliary/Makefile.sources
@@ -208,12 +208,12 @@ C_SOURCES := \
util/u_dump_state.c \
util/u_dynarray.h \
util/u_fifo.h \
- util/u_format_bptc.c \
- util/u_format_bptc.h \
util/u_format.c \
+ util/u_format.h \
util/u_format_etc.c \
util/u_format_etc.h \
- util/u_format.h \
+ util/u_format_fake.c \
+ util/u_format_fake.h \
util/u_format_latc.c \
util/u_format_latc.h \
util/u_format_other.c \
diff --git a/src/gallium/auxiliary/util/u_format.csv
b/src/gallium/auxiliary/util/u_format.csv
index a71aaf1..d3b77e6 100644
--- a/src/gallium/auxiliary/util/u_format.csv
+++ b/src/gallium/auxiliary/util/u_format.csv
@@ -186,6 +186,17 @@ PIPE_FORMAT_LATC2_SNORM , rgtc, 4, 4, x128,
, , , xxxy, rg
PIPE_FORMAT_ETC1_RGB8 , etc, 4, 4, x64, , , , xyz1,
rgb
+PIPE_FORMAT_ETC2_RGB8 , etc, 4, 4, x64, , , , xyz1,
rgb
+PIPE_FORMAT_ETC2_SRGB8, etc, 4, 4, x64, , , , xyz1,
srgb
+PIPE_FORMAT_ETC2_RGB8A1 , etc, 4, 4, x64, , , , xyzw,
rgb
+PIPE_FORMAT_ETC2_SRGB8A1 , etc, 4, 4, x64, , , , xyzw,
srgb
+PIPE_FORMAT_ETC2_RGBA8, etc, 4, 4, x128, , , , xyzw,
rgb
+PIPE_FORMAT_ETC2_SRGBA8 , etc, 4, 4, x128, , , , xyzw,
srgb
+PIPE_FORMAT_ETC2_R11_UNORM, etc, 4, 4, x64, , , , x001,
rgb
+PIPE_FORMAT_ETC2_R11_SNORM, etc, 4, 4, x64, , , , x001,
rgb
+PIPE_FORMAT_ETC2_RG11_UNORM , etc, 4, 4, x128, , , , xy01,
rgb
+PIPE_FORMAT_ETC2_RG11_SNORM , etc, 4, 4, x128, , , , xy01,
rgb
+
PIPE_FORMAT_BPTC_RGBA_UNORM , bptc, 4, 4, x128, , , , xyzw,
rgb
PIPE_FORMAT_BPTC_SRGBA, bptc, 4, 4, x128, , , , xyzw,
srgb
PIPE_FORMAT_BPTC_RGB_FLOAT, bptc, 4, 4, x128, , , , xyz1,
rgb
diff --git a/src/gallium/auxiliary/util/u_format_bptc.h
b/src/gallium/auxiliary/util/u_format_bptc.h
deleted file mode 100644
index f67d071..000
--- a/src/gallium/auxiliary/util/u_format_bptc.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/**
- *
- * Copyright 2011 Red Hat Inc.
- * All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- **/
-
-#ifndef U_FORMAT_BPTC_H_
-#define U_FORMAT_BPTC_H_
-
-void
-util_format_bptc_rgba_unorm_fetch_rgba_8unorm(uint8_t *dst, const uint8_t
*src, unsigned i, unsigned j);
-
-void
-util_format_bptc_rgba_unorm_unpack_rgba_8unorm(uint8_t *dst_row, unsigned
dst_stride, const uint8_t *src_r
Mesa (master): freedreno/a3xx: add support for vertexid and instanceid sysvals
Module: Mesa
Branch: master
Commit: f6b2e8af7425c67f8def9dfba92f6f0ad9585b40
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f6b2e8af7425c67f8def9dfba92f6f0ad9585b40
Author: Ilia Mirkin
Date: Wed Oct 1 23:13:22 2014 -0400
freedreno/a3xx: add support for vertexid and instanceid sysvals
Signed-off-by: Ilia Mirkin
---
docs/relnotes/10.6.0.html|1 +
src/gallium/drivers/freedreno/a3xx/fd3_emit.c| 46 ++---
src/gallium/drivers/freedreno/freedreno_screen.c |8 ++-
src/gallium/drivers/freedreno/ir3/ir3_compiler.c | 80 +-
src/gallium/drivers/freedreno/ir3/ir3_shader.h |1 +
5 files changed, 120 insertions(+), 16 deletions(-)
diff --git a/docs/relnotes/10.6.0.html b/docs/relnotes/10.6.0.html
index d201a65..bedbd4b 100644
--- a/docs/relnotes/10.6.0.html
+++ b/docs/relnotes/10.6.0.html
@@ -45,6 +45,7 @@ Note: some of the new features are only available with
certain drivers.
GL_AMD_pinned_memory on r600, radeonsi
+GL_ARB_draw_instanced on freedreno
GL_ARB_pipeline_statistics_query on i965, nvc0, r600, radeonsi,
softpipe
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
index 1c17e2d..ad5fcb3 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c
@@ -351,21 +351,31 @@ fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring,
struct pipe_surface *psurf
void
fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit)
{
- uint32_t i, j, last = 0;
+ int32_t i, j, last = -1;
uint32_t total_in = 0;
const struct fd_vertex_state *vtx = emit->vtx;
struct ir3_shader_variant *vp = fd3_emit_get_vp(emit);
- unsigned n = MIN2(vtx->vtx->num_elements, vp->inputs_count);
+ unsigned vertex_regid = regid(63, 0), instance_regid = regid(63, 0);
+
+ for (i = 0; i < vp->inputs_count; i++) {
+ uint8_t semantic = sem2name(vp->inputs[i].semantic);
+ if (semantic == TGSI_SEMANTIC_VERTEXID_NOBASE)
+ vertex_regid = vp->inputs[i].regid;
+ else if (semantic == TGSI_SEMANTIC_INSTANCEID)
+ instance_regid = vp->inputs[i].regid;
+ else if (i < vtx->vtx->num_elements && vp->inputs[i].compmask)
+ last = i;
+ }
/* hw doesn't like to be configured for zero vbo's, it seems: */
- if (vtx->vtx->num_elements == 0)
+ if (vtx->vtx->num_elements == 0 &&
+ vertex_regid == regid(63, 0) &&
+ instance_regid == regid(63, 0))
return;
- for (i = 0; i < n; i++)
- if (vp->inputs[i].compmask)
- last = i;
-
for (i = 0, j = 0; i <= last; i++) {
+ uint8_t semantic = sem2name(vp->inputs[i].semantic);
+ assert(semantic == 0);
if (vp->inputs[i].compmask) {
struct pipe_vertex_element *elem = &vtx->vtx->pipe[i];
const struct pipe_vertex_buffer *vb =
@@ -373,7 +383,9 @@ fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct
fd3_emit *emit)
struct fd_resource *rsc = fd_resource(vb->buffer);
enum pipe_format pfmt = elem->src_format;
enum a3xx_vtx_fmt fmt = fd3_pipe2vtx(pfmt);
- bool switchnext = (i != last);
+ bool switchnext = (i != last) ||
+ vertex_regid != regid(63, 0) ||
+ instance_regid != regid(63, 0);
bool isint = util_format_is_pure_integer(pfmt);
uint32_t fs = util_format_get_blocksize(pfmt);
@@ -409,8 +421,8 @@ fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct
fd3_emit *emit)
A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(j) |
A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(j));
OUT_RING(ring, A3XX_VFD_CONTROL_1_MAXSTORAGE(1) | // XXX
- A3XX_VFD_CONTROL_1_REGID4VTX(regid(63,0)) |
- A3XX_VFD_CONTROL_1_REGID4INST(regid(63,0)));
+ A3XX_VFD_CONTROL_1_REGID4VTX(vertex_regid) |
+ A3XX_VFD_CONTROL_1_REGID4INST(instance_regid));
}
void
@@ -580,6 +592,20 @@ fd3_emit_state(struct fd_context *ctx, struct
fd_ringbuffer *ring,
}
}
+ /* emit driver params every time */
+ if (emit->info && emit->prog == &ctx->prog) {
+ uint32_t vertex_params[4] = {
+ emit->info->indexed ? emit->info->index_bias :
emit->info->start,
+ 0,
+ 0,
+ 0
+ };
+ if (vp->constlen > vp->first_driver_param) {
+ fd3_emit_constant(ring, SB_VERT_SHADER,
vp->first_d
Mesa (master): llvmpipe, softpipe: only support ETC1, not the upcoming ETC2
Module: Mesa
Branch: master
Commit: 845b9e4294b7b89a33d77ef6713543f96eba0686
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=845b9e4294b7b89a33d77ef6713543f96eba0686
Author: Ilia Mirkin
Date: Wed Feb 18 22:23:12 2015 -0500
llvmpipe,softpipe: only support ETC1, not the upcoming ETC2
Signed-off-by: Ilia Mirkin
---
src/gallium/drivers/llvmpipe/lp_screen.c |4
src/gallium/drivers/softpipe/sp_screen.c |4
2 files changed, 8 insertions(+)
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c
b/src/gallium/drivers/llvmpipe/lp_screen.c
index 8b6e66e..3387d3a 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -453,6 +453,10 @@ llvmpipe_is_format_supported( struct pipe_screen *_screen,
return FALSE;
}
+ if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
+ format != PIPE_FORMAT_ETC1_RGB8)
+ return FALSE;
+
if (format_desc->layout == UTIL_FORMAT_LAYOUT_S3TC) {
return util_format_s3tc_enabled;
}
diff --git a/src/gallium/drivers/softpipe/sp_screen.c
b/src/gallium/drivers/softpipe/sp_screen.c
index bae1367..a269328 100644
--- a/src/gallium/drivers/softpipe/sp_screen.c
+++ b/src/gallium/drivers/softpipe/sp_screen.c
@@ -353,6 +353,10 @@ softpipe_is_format_supported( struct pipe_screen *screen,
return FALSE;
}
+ if (format_desc->layout == UTIL_FORMAT_LAYOUT_ETC &&
+ format != PIPE_FORMAT_ETC1_RGB8)
+ return FALSE;
+
/*
* All other operations (sampling, transfer, etc).
*/
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Mesa (master): freedreno/a3xx: add hardware ETC1 support
Module: Mesa
Branch: master
Commit: d622afdbc3999a4675cf0c343d5ee7863736c40a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d622afdbc3999a4675cf0c343d5ee7863736c40a
Author: Ilia Mirkin
Date: Mon Feb 16 01:33:11 2015 -0500
freedreno/a3xx: add hardware ETC1 support
Signed-off-by: Ilia Mirkin
---
src/gallium/drivers/freedreno/a3xx/a3xx.xml.h |1 +
src/gallium/drivers/freedreno/a3xx/fd3_format.c |3 +++
2 files changed, 4 insertions(+)
diff --git a/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
b/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
index 366bf2f..0dce61c 100644
--- a/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
+++ b/src/gallium/drivers/freedreno/a3xx/a3xx.xml.h
@@ -130,6 +130,7 @@ enum a3xx_tex_fmt {
TFMT_I420_Y = 24,
TFMT_I420_U = 26,
TFMT_I420_V = 27,
+ TFMT_ETC1 = 34,
TFMT_DXT1 = 36,
TFMT_DXT3 = 37,
TFMT_DXT5 = 38,
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_format.c
b/src/gallium/drivers/freedreno/a3xx/fd3_format.c
index d0ce527..a67d0ac 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_format.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_format.c
@@ -246,6 +246,9 @@ static struct fd3_format formats[PIPE_FORMAT_COUNT] = {
VT(R32G32B32A32_FLOAT, 32_32_32_32_FLOAT, R32G32B32A32_FLOAT, WZYX),
_T(R32G32B32X32_FLOAT, 32_32_32_32_FLOAT, R32G32B32A32_FLOAT, WZYX),
V_(R32G32B32A32_FIXED, 32_32_32_32_FIXED, NONE, WZYX),
+
+ /* compressed */
+ _T(ETC1_RGB8, ETC1, NONE, WZYX),
};
enum a3xx_vtx_fmt
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Mesa (master): freedreno/a3xx: add ARB_instanced_arrays support
Module: Mesa Branch: master Commit: 92fc8f04d63bae969d47d79fde2c9d48f5e90488 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=92fc8f04d63bae969d47d79fde2c9d48f5e90488 Author: Ilia Mirkin Date: Tue Dec 2 00:32:57 2014 -0500 freedreno/a3xx: add ARB_instanced_arrays support Signed-off-by: Ilia Mirkin --- docs/relnotes/10.6.0.html|1 + src/gallium/drivers/freedreno/a3xx/fd3_emit.c|3 ++- src/gallium/drivers/freedreno/freedreno_screen.c |2 +- 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/docs/relnotes/10.6.0.html b/docs/relnotes/10.6.0.html index bedbd4b..151ba17 100644 --- a/docs/relnotes/10.6.0.html +++ b/docs/relnotes/10.6.0.html @@ -46,6 +46,7 @@ Note: some of the new features are only available with certain drivers. GL_AMD_pinned_memory on r600, radeonsi GL_ARB_draw_instanced on freedreno +GL_ARB_instanced_arrays on freedreno GL_ARB_pipeline_statistics_query on i965, nvc0, r600, radeonsi, softpipe diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c index ad5fcb3..f1a17ec 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c +++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c @@ -396,7 +396,8 @@ fd3_emit_vertex_bufs(struct fd_ringbuffer *ring, struct fd3_emit *emit) A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(vb->stride) | COND(switchnext, A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT) | A3XX_VFD_FETCH_INSTR_0_INDEXCODE(j) | - A3XX_VFD_FETCH_INSTR_0_STEPRATE(1)); + COND(elem->instance_divisor, A3XX_VFD_FETCH_INSTR_0_INSTANCED) | + A3XX_VFD_FETCH_INSTR_0_STEPRATE(MAX2(1, elem->instance_divisor))); OUT_RELOC(ring, rsc->bo, vb->buffer_offset + elem->src_offset, 0, 0); OUT_PKT0(ring, REG_A3XX_VFD_DECODE_INSTR(j), 1); diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 7952c04..b0bdfd9 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -186,7 +186,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE: case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS: - case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: case PIPE_CAP_START_INSTANCE: case PIPE_CAP_COMPUTE: return 0; @@ -196,6 +195,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return is_a3xx(screen) || is_a4xx(screen); case PIPE_CAP_TGSI_INSTANCEID: + case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: return is_a3xx(screen) && glsl130; case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): 31 new commits
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=de798bb93708cebdedecefebdc96a82d9481f2aa Author: Ilia Mirkin Date: Wed Feb 18 14:53:26 2015 -0500 docs: mark ARB_gpu_shader_fp64 as done in core No driver support... yet. But core is ready. Signed-off-by: Ilia Mirkin URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e790a3c9105a54455eb634dbaffab8060805044c Author: Ilia Mirkin Date: Sun Feb 8 03:42:51 2015 -0500 glsl/tests: add DOUBLE types Signed-off-by: Ilia Mirkin Reviewed-by: Dave Airlie URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e7e7b8af6cb9055204e196db9902ec9991cd538 Author: Ilia Mirkin Date: Thu Jul 17 17:59:32 2014 -0400 glsl: add a lowering pass for frexp/ldexp with double arguments Signed-off-by: Ilia Mirkin Reviewed-by: Dave Airlie URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fffbf371242b07ff157b88792ab65d82c785de78 Author: Dave Airlie Date: Thu Aug 14 20:21:46 2014 +1000 glsl: lower double optional passes (v2) These lowering passes are optional for the backend to request, currently the TGSI softpipe backend most likely the r600g backend would want to use these passes as is. They aim to hit the gallium opcodes from the standard rounding/truncation functions. v2: also lower floor in mod_to_floor Signed-off-by: Dave Airlie Reviewed-by: Ilia Mirkin URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6354a2850d6735b857298ad206a97db0de47fd6 Author: Dave Airlie Date: Thu Aug 14 18:48:57 2014 +1000 glsl: implement double builtin functions This implements the bulk of the builtin functions for fp64 support. Signed-off-by: Dave Airlie Reviewed-by: Ilia Mirkin URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e626318e0c3ac08b8f9a6ef53325e05177b131b Author: Dave Airlie Date: Thu Aug 14 18:44:35 2014 +1000 glsl/lower_instructions: add double lowering passes This lowers double dot product and lrp to fma. Signed-off-by: Dave Airlie Reviewed-by: Ilia Mirkin URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8be5ee23de774a1101b808ff081cc3316d358933 Author: Dave Airlie Date: Thu Aug 14 18:44:50 2014 +1000 glsl: enable/disable certain lowering passes for doubles We want to restrict some lowering passes to floats only, and enable other for doubles. Signed-off-by: Dave Airlie Reviewed-by: Ilia Mirkin URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3bbaf719940447045b4f1faae77953e15908cfec Author: Tapani Pälli Date: Mon Aug 11 12:03:54 2014 +0300 glsl: validate output types for shader stages Patch fixes Piglit test: arb_gpu_shader_fp64/preprocessor/fs-output-double.frag and adds additional validation for shader outputs. Signed-off-by: Tapani Pälli Signed-off-by: Dave Airlie Reviewed-by: Ilia Mirkin URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=94f9ed701abe33b854f22577adffc4c7ad45cf18 Author: Dave Airlie Date: Thu Aug 14 18:48:09 2014 +1000 glsl: add double support to lower_mat_op_to_vec Signed-off-by: Dave Airlie Reviewed-by: Ian Romanick Reviewed-by: Ilia Mirkin URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=37730721696a0644242af1a96112381052501b18 Author: Dave Airlie Date: Thu Feb 5 12:11:58 2015 +0200 glsl: Linking support for doubles Signed-off-by: Dave Airlie Reviewed-by: Ian Romanick Reviewed-by: Ilia Mirkin URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7aa3ffe2c5411d3cb2eee9f03ad1a92cb3629527 Author: Dave Airlie Date: Thu Feb 5 12:10:26 2015 +0200 glsl: Support double loop control Signed-off-by: Dave Airlie Reviewed-by: Ilia Mirkin URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=53383476d1ba2d863ac58087fd320a45d5c7a9a5 Author: Dave Airlie Date: Thu Feb 5 12:09:04 2015 +0200 glsl: Support double inouts Signed-off-by: Dave Airlie Reviewed-by: Ilia Mirkin URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a10275f7620722f91a8c6811d2ede16f3a274b66 Author: Dave Airlie Date: Thu Feb 5 12:07:34 2015 +0200 glsl/lexer: Support double floats Signed-off-by: Dave Airlie Reviewed-by: Ian Romanick Reviewed-by: Matt Turner Reviewed-by: Ilia Mirkin URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=942574bb244a77be61896d57f79dad7f5a086db8 Author: Dave Airlie Date: Thu Feb 5 12:06:20 2015 +0200 glsl/parser: Support double floats Signed-off-by: Dave Airlie Reviewed-by: Matt Turner Reviewed-by: Ian Romanick Reviewed-by: Ilia Mirkin URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba3bab264d039926be391dcd6020dbf1c6313c41 Author: Dave Airlie Date: Thu Feb 5 12:04:58 2015 +0200 glsl/ast: Support double floats Signed-off-by:
Mesa (master): nir: Add an ALU op builder kind of like ir_builder.h
Module: Mesa
Branch: master
Commit: 2a135c470e3db165a6417ffcccab4a9f4500f526
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a135c470e3db165a6417ffcccab4a9f4500f526
Author: Eric Anholt
Date: Mon Nov 10 11:16:30 2014 -0800
nir: Add an ALU op builder kind of like ir_builder.h
v2: Rebase on the nir_opcodes.h python code generation support.
v3: Use SSA values, and set an appropriate writemask on dot products.
v4: Make the arguments be SSA references as well. This lets you stack up
expressions in the arguments of other expressions, at the cost of
having to insert a fmov/imov if you want to swizzle. Also, add
the generated file to NIR_GENERATED_FILES.
v5: Use more pythonish style for iterating the list.
v6: Infer the size of the dest from the size of the srcs, and auto-swizzle
a single small src out to the appropriate size.
v7: Add little helpers for initializing the struct, add a typedef for the
struct like other nir types have.
Reviewed-by: Kenneth Graunke (v6)
Reviewed-by: Connor Abbott (v7)
---
src/glsl/Makefile.am |5 ++
src/glsl/Makefile.sources |1 +
src/glsl/nir/.gitignore |1 +
src/glsl/nir/nir_builder.h| 130 +
src/glsl/nir/nir_builder_opcodes_h.py | 38 ++
5 files changed, 175 insertions(+)
diff --git a/src/glsl/Makefile.am b/src/glsl/Makefile.am
index 1e4d98f..5d5cacc 100644
--- a/src/glsl/Makefile.am
+++ b/src/glsl/Makefile.am
@@ -216,6 +216,7 @@ BUILT_SOURCES =
\
glsl_lexer.cpp \
glcpp/glcpp-parse.c \
glcpp/glcpp-lex.c \
+ nir/nir_builder_opcodes.h \
nir/nir_constant_expressions.c \
nir/nir_opcodes.c \
nir/nir_opcodes.h \
@@ -232,6 +233,10 @@ dist-hook:
$(RM) glcpp/tests/*.out
$(RM) glcpp/tests/subtest*/*.out
+nir/nir_builder_opcodes.h: nir/nir_opcodes.py nir/nir_builder_opcodes_h.py
+ $(MKDIR_P) nir; \
+ $(PYTHON2) $(PYTHON_FLAGS) $(srcdir)/nir/nir_builder_opcodes_h.py > $@
+
nir/nir_constant_expressions.c: nir/nir_opcodes.py
nir/nir_constant_expressions.py nir/nir_constant_expressions.h
$(MKDIR_P) nir; \
$(PYTHON2) $(PYTHON_FLAGS) $(srcdir)/nir/nir_constant_expressions.py >
$@
diff --git a/src/glsl/Makefile.sources b/src/glsl/Makefile.sources
index 7e66e91..3157d9a 100644
--- a/src/glsl/Makefile.sources
+++ b/src/glsl/Makefile.sources
@@ -11,6 +11,7 @@ LIBGLCPP_GENERATED_FILES = \
glcpp/glcpp-parse.c
NIR_GENERATED_FILES = \
+ nir/nir_builder_opcodes.h \
nir/nir_constant_expressions.c \
nir/nir_opcodes.c \
nir/nir_opcodes.h \
diff --git a/src/glsl/nir/.gitignore b/src/glsl/nir/.gitignore
index 261f64f..64828eb 100644
--- a/src/glsl/nir/.gitignore
+++ b/src/glsl/nir/.gitignore
@@ -1,3 +1,4 @@
+nir_builder_opcodes.h
nir_opt_algebraic.c
nir_opcodes.c
nir_opcodes.h
diff --git a/src/glsl/nir/nir_builder.h b/src/glsl/nir/nir_builder.h
new file mode 100644
index 000..7c4f7fd
--- /dev/null
+++ b/src/glsl/nir/nir_builder.h
@@ -0,0 +1,130 @@
+/*
+ * Copyright © 2014-2015 Broadcom
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef NIR_BUILDER_H
+#define NIR_BUILDER_H
+
+struct exec_list;
+
+typedef struct nir_builder {
+ struct exec_list *cf_node_list;
+ nir_shader *shader;
+ nir_function_impl *impl;
+} nir_builder;
+
+static inline void
+nir_builder_init(nir_builder *build, nir_function_impl *impl)
+{
+ memset(build, 0, sizeof(*build));
+ build->impl = impl;
+ build->shader = impl->overloa
Mesa (master): st/mesa: don't die for ETC2 formats when no driver support
Module: Mesa
Branch: master
Commit: 0cade4ea2b114238206055eb256d0eb000bdfac9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0cade4ea2b114238206055eb256d0eb000bdfac9
Author: Ilia Mirkin
Date: Thu Feb 19 01:38:58 2015 -0500
st/mesa: don't die for ETC2 formats when no driver support
Signed-off-by: Ilia Mirkin
---
src/mesa/state_tracker/st_format.c |3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/state_tracker/st_format.c
b/src/mesa/state_tracker/st_format.c
index 9a91d71..7868bb5 100644
--- a/src/mesa/state_tracker/st_format.c
+++ b/src/mesa/state_tracker/st_format.c
@@ -921,6 +921,9 @@ test_format_conversion(struct st_context *st)
if (i == PIPE_FORMAT_ETC1_RGB8 && !st->has_etc1)
continue;
+ if (_mesa_is_format_etc2(mf) && !st->has_etc2)
+ continue;
+
if (mf != MESA_FORMAT_NONE) {
enum pipe_format pf = st_mesa_format_to_pipe_format(st, mf);
assert(pf == i);
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Mesa (master): glsl: remove bogus 'd' constant qualifiers
Module: Mesa
Branch: master
Commit: e8e22cf65fc8b9b0c0355540985b073a03c69a51
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e8e22cf65fc8b9b0c0355540985b073a03c69a51
Author: Ilia Mirkin
Date: Thu Feb 19 01:44:44 2015 -0500
glsl: remove bogus 'd' constant qualifiers
0.0 is a double anyways. Apparently my version of gcc was happy with
0.0d as well, but this is not true of all compilers.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89218
Signed-off-by: Ilia Mirkin
---
src/glsl/lower_instructions.cpp |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/glsl/lower_instructions.cpp b/src/glsl/lower_instructions.cpp
index 8f83032..e8a69e7 100644
--- a/src/glsl/lower_instructions.cpp
+++ b/src/glsl/lower_instructions.cpp
@@ -645,7 +645,7 @@
lower_instructions_visitor::dfrexp_sig_to_arith(ir_expression *ir)
new(ir) ir_variable(bvec, "is_not_zero", ir_var_temporary);
ir_rvalue *results[4] = {NULL};
- ir_constant *dzero = new(ir) ir_constant(0.0d, vec_elem);
+ ir_constant *dzero = new(ir) ir_constant(0.0, vec_elem);
i.insert_before(is_not_zero);
i.insert_before(
assign(is_not_zero,
@@ -717,7 +717,7 @@
lower_instructions_visitor::dfrexp_exp_to_arith(ir_expression *ir)
new(ir) ir_variable(bvec, "is_not_zero", ir_var_temporary);
ir_variable *high_words =
new(ir) ir_variable(uvec, "high_words", ir_var_temporary);
- ir_constant *dzero = new(ir) ir_constant(0.0d, vec_elem);
+ ir_constant *dzero = new(ir) ir_constant(0.0, vec_elem);
ir_constant *izero = new(ir) ir_constant(0, vec_elem);
ir_rvalue *absval = abs(ir->operands[0]);
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