Mesa (master): clover: make module::symbol::name a string
Module: Mesa
Branch: master
Commit: 2d112ed96152bc62e5417472270f29966c8feece
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d112ed96152bc62e5417472270f29966c8feece
Author: EdB
Date: Fri Apr 24 12:59:56 2015 +0200
clover: make module::symbol::name a string
Acked-by: Francisco Jerez
Reviewed-by: Tom Stellard
---
src/gallium/state_trackers/clover/api/program.cpp |3 +--
src/gallium/state_trackers/clover/core/module.cpp | 21 +
src/gallium/state_trackers/clover/core/module.hpp |4 ++--
3 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/src/gallium/state_trackers/clover/api/program.cpp
b/src/gallium/state_trackers/clover/api/program.cpp
index b3be2b8..913d195 100644
--- a/src/gallium/state_trackers/clover/api/program.cpp
+++ b/src/gallium/state_trackers/clover/api/program.cpp
@@ -293,8 +293,7 @@ clGetProgramInfo(cl_program d_prog, cl_program_info param,
case CL_PROGRAM_KERNEL_NAMES:
buf.as_string() = fold([](const std::string &a, const module::symbol &s)
{
-return ((a.empty() ? "" : a + ";") +
-std::string(s.name.begin(), s.name.size()));
+return ((a.empty() ? "" : a + ";") + s.name);
}, std::string(), prog.symbols());
break;
diff --git a/src/gallium/state_trackers/clover/core/module.cpp
b/src/gallium/state_trackers/clover/core/module.cpp
index be10e35..f098b05 100644
--- a/src/gallium/state_trackers/clover/core/module.cpp
+++ b/src/gallium/state_trackers/clover/core/module.cpp
@@ -133,6 +133,27 @@ namespace {
}
};
+ /// (De)serialize a string.
+ template<>
+ struct _serializer {
+ static void
+ proc(compat::ostream &os, const std::string &s) {
+ _proc(os, s.size());
+ os.write(&s[0], s.size() * sizeof(std::string::value_type));
+ }
+
+ static void
+ proc(compat::istream &is, std::string &s) {
+ s.resize(_proc(is));
+ is.read(&s[0], s.size() * sizeof(std::string::value_type));
+ }
+
+ static void
+ proc(module::size_t &sz, const std::string &s) {
+ sz += sizeof(uint32_t) + sizeof(std::string::value_type) * s.size();
+ }
+ };
+
/// (De)serialize a module::section.
template<>
struct _serializer {
diff --git a/src/gallium/state_trackers/clover/core/module.hpp
b/src/gallium/state_trackers/clover/core/module.hpp
index ee6caf9..46112a3 100644
--- a/src/gallium/state_trackers/clover/core/module.hpp
+++ b/src/gallium/state_trackers/clover/core/module.hpp
@@ -100,12 +100,12 @@ namespace clover {
};
struct symbol {
- symbol(const compat::vector &name, resource_id section,
+ symbol(const std::string &name, resource_id section,
size_t offset, const compat::vector &args) :
name(name), section(section), offset(offset), args(args) { }
symbol() : name(), section(0), offset(0), args() { }
- compat::vector name;
+ std::string name;
resource_id section;
size_t offset;
compat::vector args;
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Mesa (master): clover: compile all sources with c++11
Module: Mesa Branch: master Commit: 3c61ff0d89da4a8cc921d131ce0c2480ddb111a0 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3c61ff0d89da4a8cc921d131ce0c2480ddb111a0 Author: EdB Date: Tue Apr 21 15:49:09 2015 +0200 clover: compile all sources with c++11 Later we can remove the compat code Reviewed-by: Francisco Jerez Reviewed-by: Tom Stellard --- src/gallium/state_trackers/clover/Makefile.am |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/state_trackers/clover/Makefile.am b/src/gallium/state_trackers/clover/Makefile.am index 62c13fa..f46d9ef 100644 --- a/src/gallium/state_trackers/clover/Makefile.am +++ b/src/gallium/state_trackers/clover/Makefile.am @@ -35,12 +35,13 @@ endif noinst_LTLIBRARIES = libclover.la libcltgsi.la libclllvm.la libcltgsi_la_CXXFLAGS = \ - -std=c++0x \ + -std=c++11 \ $(VISIBILITY_CXXFLAGS) libcltgsi_la_SOURCES = $(TGSI_SOURCES) libclllvm_la_CXXFLAGS = \ + -std=c++11 \ $(VISIBILITY_CXXFLAGS) \ $(LLVM_CXXFLAGS) \ $(DEFINES) \ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): clover: remove compat classes that match std one
Module: Mesa
Branch: master
Commit: 1b4a1d0049646e574565bab38b8ae935c1c45fae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b4a1d0049646e574565bab38b8ae935c1c45fae
Author: EdB
Date: Fri Apr 24 12:59:54 2015 +0200
clover: remove compat classes that match std one
Acked-by: Francisco Jerez
Reviewed-by: Tom Stellard
---
src/gallium/state_trackers/clover/Makefile.sources |1 -
src/gallium/state_trackers/clover/api/program.cpp |2 +-
.../state_trackers/clover/core/compiler.hpp|2 +-
src/gallium/state_trackers/clover/core/error.hpp |6 ++--
src/gallium/state_trackers/clover/util/compat.cpp | 38
src/gallium/state_trackers/clover/util/compat.hpp | 27 --
6 files changed, 6 insertions(+), 70 deletions(-)
diff --git a/src/gallium/state_trackers/clover/Makefile.sources
b/src/gallium/state_trackers/clover/Makefile.sources
index 5b3344c..03eb754 100644
--- a/src/gallium/state_trackers/clover/Makefile.sources
+++ b/src/gallium/state_trackers/clover/Makefile.sources
@@ -45,7 +45,6 @@ CPP_SOURCES := \
util/adaptor.hpp \
util/algebra.hpp \
util/algorithm.hpp \
- util/compat.cpp \
util/compat.hpp \
util/factor.hpp \
util/functional.hpp \
diff --git a/src/gallium/state_trackers/clover/api/program.cpp
b/src/gallium/state_trackers/clover/api/program.cpp
index 60184ed..c985690 100644
--- a/src/gallium/state_trackers/clover/api/program.cpp
+++ b/src/gallium/state_trackers/clover/api/program.cpp
@@ -216,7 +216,7 @@ clCompileProgram(cl_program d_prog, cl_uint num_devs,
throw error(CL_INVALID_OPERATION);
if (!any_of(key_equals(name), headers))
-headers.push_back(compat::pair(
+headers.push_back(std::pair(
name, header.source()));
},
range(header_names, num_headers),
diff --git a/src/gallium/state_trackers/clover/core/compiler.hpp
b/src/gallium/state_trackers/clover/core/compiler.hpp
index 7210d1e..bec8aac 100644
--- a/src/gallium/state_trackers/clover/core/compiler.hpp
+++ b/src/gallium/state_trackers/clover/core/compiler.hpp
@@ -29,7 +29,7 @@
#include "pipe/p_defines.h"
namespace clover {
- typedef compat::vector > header_map;
module compile_program_llvm(const compat::string &source,
diff --git a/src/gallium/state_trackers/clover/core/error.hpp
b/src/gallium/state_trackers/clover/core/error.hpp
index 7b010f1..45a38c1 100644
--- a/src/gallium/state_trackers/clover/core/error.hpp
+++ b/src/gallium/state_trackers/clover/core/error.hpp
@@ -25,6 +25,8 @@
#include "CL/cl.h"
+#include
+
#include "util/compat.hpp"
namespace clover {
@@ -50,10 +52,10 @@ namespace clover {
/// Class that represents an error that can be converted to an
/// OpenCL status code.
///
- class error : public compat::runtime_error {
+ class error : public std::runtime_error {
public:
error(cl_int code, compat::string what = "") :
- compat::runtime_error(what), code(code) {
+ std::runtime_error(what), code(code) {
}
cl_int get() const {
diff --git a/src/gallium/state_trackers/clover/util/compat.cpp
b/src/gallium/state_trackers/clover/util/compat.cpp
deleted file mode 100644
index 80d5b3e..000
--- a/src/gallium/state_trackers/clover/util/compat.cpp
+++ /dev/null
@@ -1,38 +0,0 @@
-//
-// Copyright 2013 Francisco Jerez
-//
-// Permission is hereby granted, free of charge, to any person obtaining a
-// copy of this software and associated documentation files (the "Software"),
-// to deal in the Software without restriction, including without limitation
-// the rights to use, copy, modify, merge, publish, distribute, sublicense,
-// and/or sell copies of the Software, and to permit persons to whom the
-// Software is furnished to do so, subject to the following conditions:
-//
-// The above copyright notice and this permission notice shall be included in
-// all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
-// THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
-// OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
-// ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
-// OTHER DEALINGS IN THE SOFTWARE.
-//
-
-#include "util/compat.hpp"
-
-using namespace clover::compat;
-
-exception::~exception() {
-}
-
-const char *
-exception::what() const {
- return "";
-}
-
-const char *
-runtime_error::what() const {
- return _what.c_str();
-}
diff --git a/src/gallium/state_trackers/clover/util/compat.hpp
b/src/gallium/state_trackers/clover/util/compat.hpp
index 735994f..ea7d3a0 100644
--- a/src/gallium/state_trackers/clover/util/compat.hpp
+++ b/src/gallium/sta
Mesa (master): clover: remove compat::string
Module: Mesa
Branch: master
Commit: 5ca9b23319db66d9768d46c0a7504b7bb079164a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ca9b23319db66d9768d46c0a7504b7bb079164a
Author: EdB
Date: Fri Apr 24 12:59:55 2015 +0200
clover: remove compat::string
Acked-by: Francisco Jerez
Reviewed-by: Tom Stellard
---
src/gallium/state_trackers/clover/api/program.cpp |2 +-
.../state_trackers/clover/core/compiler.hpp| 14 +--
src/gallium/state_trackers/clover/core/error.hpp |4 +-
src/gallium/state_trackers/clover/core/program.cpp |2 +-
.../state_trackers/clover/llvm/invocation.cpp | 22 ++---
.../state_trackers/clover/tgsi/compiler.cpp|7 +-
src/gallium/state_trackers/clover/util/compat.hpp | 104
7 files changed, 26 insertions(+), 129 deletions(-)
diff --git a/src/gallium/state_trackers/clover/api/program.cpp
b/src/gallium/state_trackers/clover/api/program.cpp
index c985690..b3be2b8 100644
--- a/src/gallium/state_trackers/clover/api/program.cpp
+++ b/src/gallium/state_trackers/clover/api/program.cpp
@@ -216,7 +216,7 @@ clCompileProgram(cl_program d_prog, cl_uint num_devs,
throw error(CL_INVALID_OPERATION);
if (!any_of(key_equals(name), headers))
-headers.push_back(std::pair(
+headers.push_back(std::pair(
name, header.source()));
},
range(header_names, num_headers),
diff --git a/src/gallium/state_trackers/clover/core/compiler.hpp
b/src/gallium/state_trackers/clover/core/compiler.hpp
index bec8aac..62c0f47 100644
--- a/src/gallium/state_trackers/clover/core/compiler.hpp
+++ b/src/gallium/state_trackers/clover/core/compiler.hpp
@@ -29,17 +29,17 @@
#include "pipe/p_defines.h"
namespace clover {
- typedef compat::vector > header_map;
+ typedef compat::vector > header_map;
- module compile_program_llvm(const compat::string &source,
+ module compile_program_llvm(const std::string &source,
const header_map &headers,
pipe_shader_ir ir,
- const compat::string &target,
- const compat::string &opts,
- compat::string &r_log);
+ const std::string &target,
+ const std::string &opts,
+ std::string &r_log);
- module compile_program_tgsi(const compat::string &source);
+ module compile_program_tgsi(const std::string &source);
}
#endif
diff --git a/src/gallium/state_trackers/clover/core/error.hpp
b/src/gallium/state_trackers/clover/core/error.hpp
index 45a38c1..805a0ec 100644
--- a/src/gallium/state_trackers/clover/core/error.hpp
+++ b/src/gallium/state_trackers/clover/core/error.hpp
@@ -54,7 +54,7 @@ namespace clover {
///
class error : public std::runtime_error {
public:
- error(cl_int code, compat::string what = "") :
+ error(cl_int code, std::string what = "") :
std::runtime_error(what), code(code) {
}
@@ -68,7 +68,7 @@ namespace clover {
class build_error : public error {
public:
- build_error(const compat::string &what = "") :
+ build_error(const std::string &what = "") :
error(CL_COMPILE_PROGRAM_FAILURE, what) {
}
};
diff --git a/src/gallium/state_trackers/clover/core/program.cpp
b/src/gallium/state_trackers/clover/core/program.cpp
index c07548c..50ac01b 100644
--- a/src/gallium/state_trackers/clover/core/program.cpp
+++ b/src/gallium/state_trackers/clover/core/program.cpp
@@ -52,7 +52,7 @@ program::build(const ref_vector &devs, const char
*opts,
_opts.insert({ &dev, opts });
- compat::string log;
+ std::string log;
try {
auto module = (dev.ir_format() == PIPE_SHADER_IR_TGSI ?
diff --git a/src/gallium/state_trackers/clover/llvm/invocation.cpp
b/src/gallium/state_trackers/clover/llvm/invocation.cpp
index e07d95b..2157909 100644
--- a/src/gallium/state_trackers/clover/llvm/invocation.cpp
+++ b/src/gallium/state_trackers/clover/llvm/invocation.cpp
@@ -136,7 +136,7 @@ namespace {
const std::string &name, const std::string &triple,
const std::string &processor, const std::string &opts,
clang::LangAS::Map& address_spaces, unsigned
&optimization_level,
-compat::string &r_log) {
+std::string &r_log) {
clang::CompilerInstance c;
clang::EmitLLVMOnlyAction act(&llvm_ctx);
@@ -470,7 +470,7 @@ namespace {
emit_code(LLVMTargetMachineRef tm, LLVMModuleRef mod,
LLVMCodeGenFileType file_type,
LLVMMemoryBufferRef *out_buffer,
- compat::string &r_log) {
+ std::string &r_log) {
LLVMBool err;
char *err_message = NULL;
@@ -491,7 +491,7 @@ namespace {
std::vector
compile_native(const llvm::Modul
Mesa (master): r300: do not link against libdrm_intel
Module: Mesa Branch: master Commit: b124dc2b70a1ba546d1ce46578036d263a4287fe URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b124dc2b70a1ba546d1ce46578036d263a4287fe Author: Emil Velikov Date: Wed Apr 15 14:44:02 2015 +0100 r300: do not link against libdrm_intel Accidentally added since the introduction of the file. Cc: "10.4 10.5" Signed-off-by: Emil Velikov Reviewed-by: Marek Olšák --- src/gallium/drivers/r300/Automake.inc |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/r300/Automake.inc b/src/gallium/drivers/r300/Automake.inc index 9334973..d4ddc40 100644 --- a/src/gallium/drivers/r300/Automake.inc +++ b/src/gallium/drivers/r300/Automake.inc @@ -5,7 +5,7 @@ TARGET_CPPFLAGS += -DGALLIUM_R300 TARGET_LIB_DEPS += \ $(top_builddir)/src/gallium/drivers/r300/libr300.la \ $(RADEON_LIBS) \ - $(INTEL_LIBS) + $(LIBDRM_LIBS) TARGET_RADEON_WINSYS = \ $(top_builddir)/src/gallium/winsys/radeon/drm/libradeonwinsys.la ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Don' t try to apply the opt_sampler_eot extension for vs
Module: Mesa
Branch: master
Commit: 5d4f085a43ccd1122301421f2013e42a3f0a7604
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d4f085a43ccd1122301421f2013e42a3f0a7604
Author: Neil Roberts
Date: Tue Apr 28 14:20:06 2015 +0100
i965: Don't try to apply the opt_sampler_eot extension for vs
The opt_sampler_eot optimisation of fs_visitor effectively assumes
that it is running on a fragment shader because it casts the program
key to a brw_wm_prog_key. However on Skylake fs_visitor can also be
used for vertex shaders. It looks like this usually works anyway
because the optimisation is skipped if key->nr_color_regions != 1.
However for a vertex shader the key is actually a brw_vs_prog_key so
the space for nr_color_regions is probably taken up by
key->base.program_string_id. This can end up making nr_color_regions
be 1 in which case the function will later assert when the last
instruction is not FS_OPCODE_FB_WRITE. This was making the DEQP test
suite assert. Presumably this only happens there because that compiles
a lot of shaders so it would end up with a high value for
program_string_id.
Reviewed-by: Kristian Høgsberg
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_fs.cpp |3 +++
1 file changed, 3 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 61ee056..255ddf4 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -2548,6 +2548,9 @@ fs_visitor::opt_sampler_eot()
{
brw_wm_prog_key *key = (brw_wm_prog_key*) this->key;
+ if (stage != MESA_SHADER_FRAGMENT)
+ return false;
+
if (devinfo->gen < 9 && !devinfo->is_cherryview)
return false;
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Mesa (master): clover: remove util/compat
Module: Mesa
Branch: master
Commit: d8f817ae7f4241a9ea23140805aaeb724a0ac851
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8f817ae7f4241a9ea23140805aaeb724a0ac851
Author: EdB
Date: Thu Apr 23 20:13:51 2015 +0200
clover: remove util/compat
Acked-by: Francisco Jerez
Reviewed-by: Tom Stellard
---
src/gallium/state_trackers/clover/Makefile.sources |1 -
src/gallium/state_trackers/clover/api/program.cpp | 14 +-
.../state_trackers/clover/core/compiler.hpp|4 +-
src/gallium/state_trackers/clover/core/error.hpp |2 -
src/gallium/state_trackers/clover/core/kernel.cpp |2 +-
src/gallium/state_trackers/clover/core/module.cpp | 39 +--
src/gallium/state_trackers/clover/core/module.hpp | 19 +-
src/gallium/state_trackers/clover/core/program.cpp |2 +-
src/gallium/state_trackers/clover/core/program.hpp |2 +-
.../state_trackers/clover/llvm/invocation.cpp | 20 +-
.../state_trackers/clover/tgsi/compiler.cpp|5 +-
src/gallium/state_trackers/clover/util/compat.hpp | 313
12 files changed, 56 insertions(+), 367 deletions(-)
diff --git a/src/gallium/state_trackers/clover/Makefile.sources
b/src/gallium/state_trackers/clover/Makefile.sources
index 03eb754..fa96774 100644
--- a/src/gallium/state_trackers/clover/Makefile.sources
+++ b/src/gallium/state_trackers/clover/Makefile.sources
@@ -45,7 +45,6 @@ CPP_SOURCES := \
util/adaptor.hpp \
util/algebra.hpp \
util/algorithm.hpp \
- util/compat.hpp \
util/factor.hpp \
util/functional.hpp \
util/lazy.hpp \
diff --git a/src/gallium/state_trackers/clover/api/program.cpp
b/src/gallium/state_trackers/clover/api/program.cpp
index 913d195..e9b1f38 100644
--- a/src/gallium/state_trackers/clover/api/program.cpp
+++ b/src/gallium/state_trackers/clover/api/program.cpp
@@ -23,6 +23,8 @@
#include "api/util.hpp"
#include "core/program.hpp"
+#include
+
using namespace clover;
namespace {
@@ -94,12 +96,12 @@ clCreateProgramWithBinary(cl_context d_ctx, cl_uint n,
return { CL_INVALID_VALUE, {} };
try {
-compat::istream::buffer_t bin(p, l);
-compat::istream s(bin);
+std::stringbuf bin( { (char*)p, l } );
+std::istream s(&bin);
return { CL_SUCCESS, module::deserialize(s) };
- } catch (compat::istream::error &e) {
+ } catch (std::istream::failure &e) {
return { CL_INVALID_BINARY, {} };
}
},
@@ -279,10 +281,10 @@ clGetProgramInfo(cl_program d_prog, cl_program_info param,
case CL_PROGRAM_BINARIES:
buf.as_matrix() = map([&](const device &dev) {
-compat::ostream::buffer_t bin;
-compat::ostream s(bin);
+std::stringbuf bin;
+std::ostream s(&bin);
prog.binary(dev).serialize(s);
-return bin;
+return bin.str();
},
prog.devices());
break;
diff --git a/src/gallium/state_trackers/clover/core/compiler.hpp
b/src/gallium/state_trackers/clover/core/compiler.hpp
index 62c0f47..c68aa39 100644
--- a/src/gallium/state_trackers/clover/core/compiler.hpp
+++ b/src/gallium/state_trackers/clover/core/compiler.hpp
@@ -23,14 +23,12 @@
#ifndef CLOVER_CORE_COMPILER_HPP
#define CLOVER_CORE_COMPILER_HPP
-#include "util/compat.hpp"
#include "core/error.hpp"
#include "core/module.hpp"
#include "pipe/p_defines.h"
namespace clover {
- typedef compat::vector > header_map;
+ typedef std::vector > header_map;
module compile_program_llvm(const std::string &source,
const header_map &headers,
diff --git a/src/gallium/state_trackers/clover/core/error.hpp
b/src/gallium/state_trackers/clover/core/error.hpp
index 805a0ec..eb65d62 100644
--- a/src/gallium/state_trackers/clover/core/error.hpp
+++ b/src/gallium/state_trackers/clover/core/error.hpp
@@ -27,8 +27,6 @@
#include
-#include "util/compat.hpp"
-
namespace clover {
class command_queue;
class context;
diff --git a/src/gallium/state_trackers/clover/core/kernel.cpp
b/src/gallium/state_trackers/clover/core/kernel.cpp
index 442762c..0756f06 100644
--- a/src/gallium/state_trackers/clover/core/kernel.cpp
+++ b/src/gallium/state_trackers/clover/core/kernel.cpp
@@ -192,7 +192,7 @@ kernel::exec_context::bind(intrusive_ptr _q,
if (st)
_q->pipe->delete_compute_state(_q->pipe, st);
- cs.prog = msec.data.begin();
+ cs.prog = &(msec.data[0]);
cs.req_local_mem = mem_local;
cs.req_input_mem = input.size();
st = q->pipe->create_compute_state(q->pipe, &cs);
diff --git a/src/gallium/state_trackers/clover/core/module.cpp
b/src/gallium/state_trackers/clover/core/module.cpp
index f098b05..a6c5b98 100644
--- a/src/gallium/state_trackers/clover/core/module.cpp
+++ b/src/gallium/state_trackers/clover/core/module.cpp
@@ -21,6 +21,7 @@
//
#include
+#include
#inclu
Mesa (master): winsys/radeon: move radeon_winsys.h to drivers/radeon
Module: Mesa
Branch: master
Commit: dcfbc006b6b07d41338b87c64cdc01c36608087b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dcfbc006b6b07d41338b87c64cdc01c36608087b
Author: Marek Olšák
Date: Thu Apr 16 22:50:33 2015 +0200
winsys/radeon: move radeon_winsys.h to drivers/radeon
---
src/gallium/auxiliary/target-helpers/inline_drm_helper.h |6 +++---
src/gallium/drivers/r300/r300_chipset.c |2 +-
src/gallium/drivers/r300/r300_context.h |1 -
src/gallium/drivers/r300/r300_screen.h |2 +-
src/gallium/drivers/radeon/Makefile.sources |3 ++-
src/gallium/drivers/radeon/r600_pipe_common.h|2 +-
src/gallium/drivers/radeon/radeon_uvd.c |1 -
src/gallium/drivers/radeon/radeon_uvd.h |2 +-
src/gallium/drivers/radeon/radeon_vce.c |1 -
src/gallium/drivers/radeon/radeon_vce_40_2_2.c |1 -
src/gallium/drivers/radeon/radeon_video.c|1 -
src/gallium/drivers/radeon/radeon_video.h|2 +-
.../{winsys/radeon/drm => drivers/radeon}/radeon_winsys.h|0
src/gallium/drivers/radeonsi/si_pm4.h|2 +-
src/gallium/targets/pipe-loader/pipe_r300.c |2 +-
src/gallium/targets/pipe-loader/pipe_r600.c |2 +-
src/gallium/targets/pipe-loader/pipe_radeonsi.c |2 +-
src/gallium/winsys/radeon/drm/Makefile.sources |3 +--
src/gallium/winsys/radeon/drm/radeon_drm_winsys.h|2 +-
19 files changed, 16 insertions(+), 21 deletions(-)
diff --git a/src/gallium/auxiliary/target-helpers/inline_drm_helper.h
b/src/gallium/auxiliary/target-helpers/inline_drm_helper.h
index 542ad43..d3c331d 100644
--- a/src/gallium/auxiliary/target-helpers/inline_drm_helper.h
+++ b/src/gallium/auxiliary/target-helpers/inline_drm_helper.h
@@ -28,19 +28,19 @@
#endif
#if GALLIUM_R300
-#include "radeon/drm/radeon_winsys.h"
+#include "radeon/radeon_winsys.h"
#include "radeon/drm/radeon_drm_public.h"
#include "r300/r300_public.h"
#endif
#if GALLIUM_R600
-#include "radeon/drm/radeon_winsys.h"
+#include "radeon/radeon_winsys.h"
#include "radeon/drm/radeon_drm_public.h"
#include "r600/r600_public.h"
#endif
#if GALLIUM_RADEONSI
-#include "radeon/drm/radeon_winsys.h"
+#include "radeon/radeon_winsys.h"
#include "radeon/drm/radeon_drm_public.h"
#include "radeonsi/si_public.h"
#endif
diff --git a/src/gallium/drivers/r300/r300_chipset.c
b/src/gallium/drivers/r300/r300_chipset.c
index 7a83611..c1c7ce3 100644
--- a/src/gallium/drivers/r300/r300_chipset.c
+++ b/src/gallium/drivers/r300/r300_chipset.c
@@ -22,7 +22,7 @@
* USE OR OTHER DEALINGS IN THE SOFTWARE. */
#include "r300_chipset.h"
-#include "radeon/drm/radeon_winsys.h"
+#include "radeon/radeon_winsys.h"
#include "util/u_debug.h"
#include "util/u_memory.h"
diff --git a/src/gallium/drivers/r300/r300_context.h
b/src/gallium/drivers/r300/r300_context.h
index 4d2b153..3873c9a 100644
--- a/src/gallium/drivers/r300/r300_context.h
+++ b/src/gallium/drivers/r300/r300_context.h
@@ -36,7 +36,6 @@
#include "r300_defines.h"
#include "r300_screen.h"
#include "compiler/radeon_regalloc.h"
-#include "radeon/drm/radeon_winsys.h"
struct u_upload_mgr;
struct r300_context;
diff --git a/src/gallium/drivers/r300/r300_screen.h
b/src/gallium/drivers/r300/r300_screen.h
index f0dd3c6..7bba39b 100644
--- a/src/gallium/drivers/r300/r300_screen.h
+++ b/src/gallium/drivers/r300/r300_screen.h
@@ -25,7 +25,7 @@
#define R300_SCREEN_H
#include "r300_chipset.h"
-#include "radeon/drm/radeon_winsys.h"
+#include "radeon/radeon_winsys.h"
#include "pipe/p_screen.h"
#include "util/u_slab.h"
#include "os/os_thread.h"
diff --git a/src/gallium/drivers/radeon/Makefile.sources
b/src/gallium/drivers/radeon/Makefile.sources
index 469f6d1..c655fe5 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -15,7 +15,8 @@ C_SOURCES := \
radeon_vce.c \
radeon_vce.h \
radeon_video.c \
- radeon_video.h
+ radeon_video.h \
+ radeon_winsys.h
LLVM_C_FILES := \
radeon_elf_util.c \
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index faa6e0d..f1c9503 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -34,7 +34,7 @@
#include
-#include "radeon/drm/radeon_winsys.h"
+#include "radeon/radeon_winsys.h"
#include "util/u_blitter.h"
#include "util/u_double_list.h"
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c
b/src/gallium/drivers/radeon/radeon_uvd.c
index 9668d7d..4d4b54b 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/d
Mesa (master): winsys/radeon: add a private interface for radeon_surface
Module: Mesa
Branch: master
Commit: a582b22c6382f24d921e9fe8a24917100c1396f1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a582b22c6382f24d921e9fe8a24917100c1396f1
Author: Marek Olšák
Date: Thu Apr 16 22:53:04 2015 +0200
winsys/radeon: add a private interface for radeon_surface
---
src/gallium/drivers/r600/evergreen_state.c |6 +-
src/gallium/drivers/r600/r600_uvd.c|2 +-
src/gallium/drivers/radeon/r600_pipe_common.h |2 +-
src/gallium/drivers/radeon/r600_texture.c | 12 +-
src/gallium/drivers/radeon/radeon_uvd.c|6 +-
src/gallium/drivers/radeon/radeon_uvd.h|4 +-
src/gallium/drivers/radeon/radeon_vce.c|2 +-
src/gallium/drivers/radeon/radeon_vce.h|6 +-
src/gallium/drivers/radeon/radeon_video.c |2 +-
src/gallium/drivers/radeon/radeon_video.h |2 +-
src/gallium/drivers/radeon/radeon_winsys.h | 79 -
src/gallium/drivers/radeonsi/si_state.c|4 +-
src/gallium/drivers/radeonsi/si_uvd.c |4 +-
src/gallium/winsys/radeon/drm/Makefile.sources |1 +
src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 180
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 20 +--
src/gallium/winsys/radeon/drm/radeon_drm_winsys.h |1 +
17 files changed, 286 insertions(+), 47 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 266e372..4ddbc0b 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -664,7 +664,7 @@ evergreen_create_sampler_view_custom(struct pipe_context
*ctx,
unsigned height, depth, width;
unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
enum pipe_format pipe_format = state->format;
- struct radeon_surface_level *surflevel;
+ struct radeon_surf_level *surflevel;
unsigned base_level, first_level, last_level;
uint64_t va;
@@ -918,7 +918,7 @@ static void evergreen_emit_scissor_state(struct
r600_context *rctx, struct r600_
/**
* This function intializes the CB* register values for RATs. It is meant
* to be used for 1D aligned buffers that do not have an associated
- * radeon_surface.
+ * radeon_surf.
*/
void evergreen_init_color_surface_rat(struct r600_context *rctx,
struct r600_surface *surf)
@@ -1163,7 +1163,7 @@ static void evergreen_init_depth_surface(struct
r600_context *rctx,
struct r600_screen *rscreen = rctx->screen;
struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
unsigned level = surf->base.u.tex.level;
- struct radeon_surface_level *levelinfo = &rtex->surface.level[level];
+ struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
uint64_t offset;
unsigned format, array_mode;
unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
diff --git a/src/gallium/drivers/r600/r600_uvd.c
b/src/gallium/drivers/r600/r600_uvd.c
index ee5288f..357e901 100644
--- a/src/gallium/drivers/r600/r600_uvd.c
+++ b/src/gallium/drivers/r600/r600_uvd.c
@@ -57,7 +57,7 @@ struct pipe_video_buffer *r600_video_buffer_create(struct
pipe_context *pipe,
{
struct r600_context *ctx = (struct r600_context *)pipe;
struct r600_texture *resources[VL_NUM_COMPONENTS] = {};
- struct radeon_surface* surfaces[VL_NUM_COMPONENTS] = {};
+ struct radeon_surf* surfaces[VL_NUM_COMPONENTS] = {};
struct pb_buffer **pbs[VL_NUM_COMPONENTS] = {};
const enum pipe_format *resource_formats;
struct pipe_video_buffer template;
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index f1c9503..8d885ab 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -199,7 +199,7 @@ struct r600_texture {
unsigneddirty_level_mask; /* each bit says if
that mipmap is compressed */
struct r600_texture *flushed_depth_texture;
boolean is_flushing_texture;
- struct radeon_surface surface;
+ struct radeon_surf surface;
/* Colorbuffer compression and fast clear. */
struct r600_fmask_info fmask;
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index ab8ce7b..dc510c9 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -119,7 +119,7 @@ static unsigned r600_texture_get_offset(struct r600_texture
*rtex, unsigned leve
}
static int r600_init_surface(struct r600_common_screen *rscreen,
-struct radeon_surface *surface,
+struct radeon_surf
Mesa (master): glx: Massive update of comments in struct extension_info
Module: Mesa Branch: master Commit: 2c7e289d8b1d3c63ab55b64ab3961067fd5a1985 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c7e289d8b1d3c63ab55b64ab3961067fd5a1985 Author: Ian Romanick Date: Wed Apr 15 11:34:50 2015 -0700 glx: Massive update of comments in struct extension_info In response to another patch, Emil asked for some clarification how this stuff works. Rather than just reply to the e-mail, I decided to update the exlanation in the code. Signed-off-by: Ian Romanick Cc: Emil Velikov --- src/glx/glxextensions.c | 69 --- 1 file changed, 65 insertions(+), 4 deletions(-) diff --git a/src/glx/glxextensions.c b/src/glx/glxextensions.c index a326f0d..cb8cd66 100644 --- a/src/glx/glxextensions.c +++ b/src/glx/glxextensions.c @@ -61,12 +61,73 @@ struct extension_info */ unsigned char version_major; unsigned char version_minor; + + /** +* The client (i.e., libGL) supports this extension. +* +* Except during bring up, all extensions should have this set to Y. There +* are a few cases of extensions that have partial (or speculative) +* support, but these are rare. There also shouldn't be any new ones +* added. +* +* Generally, extensions require server support and ::client_support to be +* enabled. If the display is capable of direct rendering, +* ::direct_support is also required. +* +* \sa ::client_only +*/ unsigned char client_support; + + /** +* The direct-renderer (e.g., i965_dri.so) supports this extension. +* +* For cases where all of the infrastructure to support the extension is a +* required part of the loader/driver interface, this can default to Y. +* For most cases, extended functionality, usually in the form of DRI2 +* extensions, is necessary to support the extension. The loader will set +* the flag true if all the requirements are met. +* +* If the display is capable of direct rendering, ::direct_support is +* required for the extension to be enabled. +*/ unsigned char direct_support; - unsigned char client_only;/** Is the extension client-side only? */ - unsigned char direct_only;/** Is the extension for direct - * contexts only? - */ + + /** +* The extension depends only on client support. +* +* This is for extensions like GLX_ARB_get_proc_address that are contained +* entirely in the client library. There is no dependency on the server or +* the direct-renderer. +* +* These extensions will be enabled if ::client_support is set. +* +* \note +* An extension \b cannot be both client-only and direct-only because being +* direct-only implies a dependency on the direct renderer. +* +* \sa ::client_support, ::direct_only +*/ + unsigned char client_only; + + /** +* The extension only functions with direct-rendering contexts +* +* The extension has no GLX protocol, and, therefore, no explicit +* dependency on the server. The functionality is contained entirely in +* the client library and the direct renderer. A few of the swap-related +* extensions are intended to behave this way. +* +* These extensions will be enabled if both ::client_support and +* ::direct_support are set. +* +* \note +* An extension \b cannot be both client-only and direct-only because being +* client-only implies that all functionality is outside the +* direct-renderer. +* +* \sa ::direct_support, ::client_only +*/ + unsigned char direct_only; }; /* *INDENT-OFF* */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Expose and refactor brw_update_renderbuffer_surfaces( )
Module: Mesa
Branch: master
Commit: c15e20d8f6f6d632ad55d444149c2a12d0dcc515
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c15e20d8f6f6d632ad55d444149c2a12d0dcc515
Author: Topi Pohjolainen
Date: Thu Mar 19 11:09:54 2015 +0200
i965: Expose and refactor brw_update_renderbuffer_surfaces()
Note that brw_update_renderbuffer_surfaces() already had a helper
variable which was used in parallel to direct access of the current
draw buffer of the context.
Reviewed-by: Kenneth Graunke
Reviewed-by: Matt Turner
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_state.h|5 +++
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 51 +-
2 files changed, 35 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index cfa67b6..83058b9 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -233,6 +233,11 @@ GLuint translate_tex_format(struct brw_context *brw,
int brw_get_texture_swizzle(const struct gl_context *ctx,
const struct gl_texture_object *t);
+void brw_update_renderbuffer_surfaces(struct brw_context *brw,
+ const struct gl_framebuffer *fb,
+ uint32_t render_target_start,
+ uint32_t *surf_offset);
+
/* gen7_wm_surface_state.c */
uint32_t gen7_surface_tiling_mode(uint32_t tiling);
uint32_t gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout
l);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index d451940..25fb543 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -731,40 +731,49 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
/**
* Construct SURFACE_STATE objects for renderbuffers/draw buffers.
*/
-static void
-brw_update_renderbuffer_surfaces(struct brw_context *brw)
+void
+brw_update_renderbuffer_surfaces(struct brw_context *brw,
+ const struct gl_framebuffer *fb,
+ uint32_t render_target_start,
+ uint32_t *surf_offset)
{
- struct gl_context *ctx = &brw->ctx;
- /* _NEW_BUFFERS */
- const struct gl_framebuffer *fb = ctx->DrawBuffer;
GLuint i;
- /* _NEW_BUFFERS | _NEW_COLOR */
/* Update surfaces for drawing buffers */
- if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
- for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
- const uint32_t surf_index =
-brw->wm.prog_data->binding_table.render_target_start + i;
+ if (fb->_NumColorDrawBuffers >= 1) {
+ for (i = 0; i < fb->_NumColorDrawBuffers; i++) {
+ const uint32_t surf_index = render_target_start + i;
-if (intel_renderbuffer(ctx->DrawBuffer->_ColorDrawBuffers[i])) {
-brw->wm.base.surf_offset[surf_index] =
+if (intel_renderbuffer(fb->_ColorDrawBuffers[i])) {
+surf_offset[surf_index] =
brw->vtbl.update_renderbuffer_surface(
- brw, ctx->DrawBuffer->_ColorDrawBuffers[i],
- ctx->DrawBuffer->MaxNumLayers > 0, i, surf_index);
+ brw, fb->_ColorDrawBuffers[i],
+ fb->MaxNumLayers > 0, i, surf_index);
} else {
brw->vtbl.emit_null_surface_state(
brw, fb->Width, fb->Height, fb->Visual.samples,
- &brw->wm.base.surf_offset[surf_index]);
+ &surf_offset[surf_index]);
}
}
} else {
- const uint32_t surf_index =
- brw->wm.prog_data->binding_table.render_target_start;
-
+ const uint32_t surf_index = render_target_start;
brw->vtbl.emit_null_surface_state(
brw, fb->Width, fb->Height, fb->Visual.samples,
- &brw->wm.base.surf_offset[surf_index]);
+ &surf_offset[surf_index]);
}
+}
+
+static void
+update_renderbuffer_surfaces(struct brw_context *brw)
+{
+ const struct gl_context *ctx = &brw->ctx;
+
+ /* _NEW_BUFFERS | _NEW_COLOR */
+ const struct gl_framebuffer *fb = ctx->DrawBuffer;
+ brw_update_renderbuffer_surfaces(
+ brw, fb,
+ brw->wm.prog_data->binding_table.render_target_start,
+ brw->wm.base.surf_offset);
brw->ctx.NewDriverState |= BRW_NEW_SURFACES;
}
@@ -775,7 +784,7 @@ const struct brw_tracked_state brw_renderbuffer_surfaces = {
.brw = BRW_NEW_BATCH |
BRW_NEW_FS_PROG_DATA,
},
- .emit = brw_update_renderbuffer_surfaces,
+ .emit = update_renderbuffer_surfaces,
};
const struct brw_tracked_state gen6_renderbuffer_surfaces = {
@@ -783,7 +792,7 @@ const struct brw_tracked_state gen6_renderbuffer_surfaces =
{
.mesa = _NEW_BUFFERS,
.brw = BRW_NEW_BATCH,
},
- .emit = brw_update_renderbuffer
Mesa (master): i965/ps: Use SET_FIELD() for sampler count
Module: Mesa
Branch: master
Commit: f39846fb57c2b4d29b65a40019ba55219b062117
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f39846fb57c2b4d29b65a40019ba55219b062117
Author: Topi Pohjolainen
Date: Wed Apr 29 20:35:45 2015 +0300
i965/ps: Use SET_FIELD() for sampler count
The value is actually clamped to 0-16 as sample state pointer
can be used to support more than 16 samplers.
Reviewed-by: Kenneth Graunke
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_defines.h |1 +
src/mesa/drivers/dri/i965/gen7_wm_state.c |5 +++--
src/mesa/drivers/dri/i965/gen8_ps_state.c |5 +++--
3 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index bd3218a..7d55d85 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -2259,6 +2259,7 @@ enum brw_wm_barycentric_interp_mode {
# define GEN7_PS_SPF_MODE (1 << 31)
# define GEN7_PS_VECTOR_MASK_ENABLE(1 << 30)
# define GEN7_PS_SAMPLER_COUNT_SHIFT 27
+# define GEN7_PS_SAMPLER_COUNT_MASK INTEL_MASK(29, 27)
# define GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT 18
# define GEN7_PS_FLOATING_POINT_MODE_IEEE_754 (0 << 16)
# define GEN7_PS_FLOATING_POINT_MODE_ALT (1 << 16)
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 923414e..55a1acd 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -135,8 +135,9 @@ upload_ps_state(struct brw_context *brw)
dw2 = dw4 = dw5 = ksp2 = 0;
- dw2 |=
- (ALIGN(brw->wm.base.sampler_count, 4) / 4) <<
GEN7_PS_SAMPLER_COUNT_SHIFT;
+ const unsigned sampler_count =
+ DIV_ROUND_UP(CLAMP(brw->wm.base.sampler_count, 0, 16), 4);
+ dw2 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT);
dw2 |= ((prog_data->base.binding_table.size_bytes / 4) <<
GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT);
diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c
b/src/mesa/drivers/dri/i965/gen8_ps_state.c
index 5f39e12..8481153 100644
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
@@ -133,8 +133,9 @@ upload_ps_state(struct brw_context *brw)
*/
dw3 |= GEN7_PS_VECTOR_MASK_ENABLE;
- dw3 |=
- (ALIGN(brw->wm.base.sampler_count, 4) / 4) <<
GEN7_PS_SAMPLER_COUNT_SHIFT;
+ const unsigned sampler_count =
+ DIV_ROUND_UP(CLAMP(brw->wm.base.sampler_count, 0, 16), 4);
+ dw3 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT);
/* BRW_NEW_FS_PROG_DATA */
dw3 |=
___
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Mesa (master): i965/blorp: Remove constant parameter
Module: Mesa
Branch: master
Commit: d271a13ba31168e0de75d7d4c1d4d7a2e2fb136c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d271a13ba31168e0de75d7d4c1d4d7a2e2fb136c
Author: Topi Pohjolainen
Date: Sat Mar 14 10:21:33 2015 +0200
i965/blorp: Remove constant parameter
This was still needed when we had support for blorp clears but now
this is fixed to nop.
Reviewed-by: Kenneth Graunke
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp.cpp |1 -
src/mesa/drivers/dri/i965/brw_blorp.h|8
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 11 ---
3 files changed, 20 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 131e155..b0de55d 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -162,7 +162,6 @@ brw_blorp_params::brw_blorp_params()
y1(0),
depth_format(0),
hiz_op(GEN6_HIZ_OP_NONE),
- fast_clear_op(GEN7_FAST_CLEAR_OP_NONE),
use_wm_prog(false)
{
color_write_disable[0] = false;
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index ff68000..59aecab 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -208,13 +208,6 @@ struct brw_blorp_prog_data
};
-enum gen7_fast_clear_op {
- GEN7_FAST_CLEAR_OP_NONE,
- GEN7_FAST_CLEAR_OP_FAST_CLEAR,
- GEN7_FAST_CLEAR_OP_RESOLVE,
-};
-
-
class brw_blorp_params
{
public:
@@ -232,7 +225,6 @@ public:
brw_blorp_surface_info src;
brw_blorp_surface_info dst;
enum gen6_hiz_op hiz_op;
- enum gen7_fast_clear_op fast_clear_op;
bool use_wm_prog;
brw_blorp_wm_push_constants wm_push_consts;
bool color_write_disable[4];
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index fb6a0dd..8215fe9 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -529,17 +529,6 @@ gen7_blorp_emit_ps_config(struct brw_context *brw,
dw5 |= prog_data->first_curbe_grf << GEN7_PS_DISPATCH_START_GRF_SHIFT_0;
}
- switch (params->fast_clear_op) {
- case GEN7_FAST_CLEAR_OP_FAST_CLEAR:
- dw4 |= GEN7_PS_RENDER_TARGET_FAST_CLEAR_ENABLE;
- break;
- case GEN7_FAST_CLEAR_OP_RESOLVE:
- dw4 |= GEN7_PS_RENDER_TARGET_RESOLVE_ENABLE;
- break;
- default:
- break;
- }
-
BEGIN_BATCH(8);
OUT_BATCH(_3DSTATE_PS << 16 | (8 - 2));
OUT_BATCH(params->use_wm_prog ? prog_offset : 0);
___
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Mesa (master): i965/gen7/blorp: Remove unused arguments
Module: Mesa
Branch: master
Commit: dce1972945a4568c181011880e0336a2a14909ec
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dce1972945a4568c181011880e0336a2a14909ec
Author: Topi Pohjolainen
Date: Fri Jan 30 11:30:34 2015 +0200
i965/gen7/blorp: Remove unused arguments
Reviewed-by: Kenneth Graunke
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/gen7_blorp.cpp | 75 +++---
1 file changed, 28 insertions(+), 47 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index d841346..c9e7cb7 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -48,8 +48,7 @@
* valid.
*/
static void
-gen7_blorp_emit_urb_config(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_urb_config(struct brw_context *brw)
{
unsigned urb_size = (brw->is_haswell && brw->gt == 3) ? 32 : 16;
gen7_emit_push_constant_state(brw,
@@ -73,7 +72,6 @@ gen7_blorp_emit_urb_config(struct brw_context *brw,
/* 3DSTATE_BLEND_STATE_POINTERS */
static void
gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
-const brw_blorp_params *params,
uint32_t cc_blend_state_offset)
{
BEGIN_BATCH(2);
@@ -86,7 +84,6 @@ gen7_blorp_emit_blend_state_pointer(struct brw_context *brw,
/* 3DSTATE_CC_STATE_POINTERS */
static void
gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
- const brw_blorp_params *params,
uint32_t cc_state_offset)
{
BEGIN_BATCH(2);
@@ -96,8 +93,7 @@ gen7_blorp_emit_cc_state_pointer(struct brw_context *brw,
}
static void
-gen7_blorp_emit_cc_viewport(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_cc_viewport(struct brw_context *brw)
{
struct brw_cc_viewport *ccv;
uint32_t cc_vp_offset;
@@ -121,7 +117,6 @@ gen7_blorp_emit_cc_viewport(struct brw_context *brw,
*/
static void
gen7_blorp_emit_depth_stencil_state_pointers(struct brw_context *brw,
- const brw_blorp_params *params,
uint32_t depthstencil_offset)
{
BEGIN_BATCH(2);
@@ -136,7 +131,6 @@ gen7_blorp_emit_depth_stencil_state_pointers(struct
brw_context *brw,
*/
static uint32_t
gen7_blorp_emit_surface_state(struct brw_context *brw,
- const brw_blorp_params *params,
const brw_blorp_surface_info *surface,
uint32_t read_domains, uint32_t write_domain,
bool is_render_target)
@@ -228,8 +222,7 @@ gen7_blorp_emit_surface_state(struct brw_context *brw,
* Disable vertex shader.
*/
static void
-gen7_blorp_emit_vs_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_vs_disable(struct brw_context *brw)
{
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_CONSTANT_VS << 16 | (7 - 2));
@@ -257,8 +250,7 @@ gen7_blorp_emit_vs_disable(struct brw_context *brw,
* Disable the hull shader.
*/
static void
-gen7_blorp_emit_hs_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_hs_disable(struct brw_context *brw)
{
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_CONSTANT_HS << 16 | (7 - 2));
@@ -287,8 +279,7 @@ gen7_blorp_emit_hs_disable(struct brw_context *brw,
* Disable the tesselation engine.
*/
static void
-gen7_blorp_emit_te_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_te_disable(struct brw_context *brw)
{
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_TE << 16 | (4 - 2));
@@ -304,8 +295,7 @@ gen7_blorp_emit_te_disable(struct brw_context *brw,
* Disable the domain shader.
*/
static void
-gen7_blorp_emit_ds_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_ds_disable(struct brw_context *brw)
{
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_CONSTANT_DS << 16 | (7 - 2));
@@ -332,8 +322,7 @@ gen7_blorp_emit_ds_disable(struct brw_context *brw,
* Disable the geometry shader.
*/
static void
-gen7_blorp_emit_gs_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_gs_disable(struct brw_context *brw)
{
BEGIN_BATCH(7);
OUT_BATCH(_3DSTATE_CONSTANT_GS << 16 | (7 - 2));
@@ -377,8 +366,7 @@ gen7_blorp_emit_gs_disable(struct brw_context *brw,
* Disable streamout.
*/
static void
-gen7_blorp_emit_streamout_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen7_blorp_emit_streamout_disable(struct brw_context *brw)
{
BEGIN_BATCH(3);
OUT_BATCH(_3DSTATE_STREAMOUT << 16 | (3 - 2));
@@ -544
Mesa (master): i965: Refactor sampler state setup
Module: Mesa
Branch: master
Commit: 02dbc79297203a063b91e6b5a0b81bda8aa48c19
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=02dbc79297203a063b91e6b5a0b81bda8aa48c19
Author: Topi Pohjolainen
Date: Thu Apr 2 12:45:02 2015 +0300
i965: Refactor sampler state setup
v2 (Matt): Moved * to the name.
Reviewed-by: Kenneth Graunke
Reviewed-by: Matt Turner
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_sampler_state.c | 60 -
src/mesa/drivers/dri/i965/brw_state.h |9
2 files changed, 47 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c
b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index c78e2e3..22ccbfe 100644
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -375,21 +375,16 @@ upload_default_color(struct brw_context *brw,
* Sets the sampler state for a single unit based off of the sampler key
* entry.
*/
-static void
+void
brw_update_sampler_state(struct brw_context *brw,
- int unit,
+ GLenum target, bool tex_cube_map_seamless,
+ GLfloat tex_unit_lod_bias,
+ mesa_format format, GLenum base_format,
+ bool is_integer_format,
+ const struct gl_sampler_object *sampler,
uint32_t *sampler_state,
uint32_t batch_offset_for_sampler_state)
{
- struct gl_context *ctx = &brw->ctx;
- const struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
- const struct gl_texture_object *texObj = texUnit->_Current;
- const struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
-
- /* These don't use samplers at all. */
- if (texObj->Target == GL_TEXTURE_BUFFER)
- return;
-
unsigned min_filter, mag_filter, mip_filter;
/* Select min and mip filters. */
@@ -459,12 +454,12 @@ brw_update_sampler_state(struct brw_context *brw,
unsigned wrap_t = translate_wrap_mode(brw, sampler->WrapT, either_nearest);
unsigned wrap_r = translate_wrap_mode(brw, sampler->WrapR, either_nearest);
- if (texObj->Target == GL_TEXTURE_CUBE_MAP ||
- texObj->Target == GL_TEXTURE_CUBE_MAP_ARRAY) {
+ if (target == GL_TEXTURE_CUBE_MAP ||
+ target == GL_TEXTURE_CUBE_MAP_ARRAY) {
/* Cube maps must use the same wrap mode for all three coordinate
* dimensions. Prior to Haswell, only CUBE and CLAMP are valid.
*/
- if ((ctx->Texture.CubeMapSeamless || sampler->CubeMapSeamless) &&
+ if ((tex_cube_map_seamless || sampler->CubeMapSeamless) &&
(sampler->MinFilter != GL_NEAREST ||
sampler->MagFilter != GL_NEAREST)) {
wrap_s = BRW_TEXCOORDMODE_CUBE;
@@ -475,7 +470,7 @@ brw_update_sampler_state(struct brw_context *brw,
wrap_t = BRW_TEXCOORDMODE_CLAMP;
wrap_r = BRW_TEXCOORDMODE_CLAMP;
}
- } else if (texObj->Target == GL_TEXTURE_1D) {
+ } else if (target == GL_TEXTURE_1D) {
/* There's a bug in 1D texture sampling - it actually pays
* attention to the wrap_t value, though it should not.
* Override the wrap_t value here to GL_REPEAT to keep
@@ -495,7 +490,7 @@ brw_update_sampler_state(struct brw_context *brw,
const unsigned min_lod = U_FIXED(CLAMP(sampler->MinLod, 0, 13), lod_bits);
const unsigned max_lod = U_FIXED(CLAMP(sampler->MaxLod, 0, 13), lod_bits);
const int lod_bias =
- S_FIXED(CLAMP(texUnit->LodBias + sampler->LodBias, -16, 15), lod_bits);
+ S_FIXED(CLAMP(tex_unit_lod_bias + sampler->LodBias, -16, 15), lod_bits);
const unsigned base_level = U_FIXED(0, 1);
/* Upload the border color if necessary. If not, just point it at
@@ -506,14 +501,12 @@ brw_update_sampler_state(struct brw_context *brw,
if (wrap_mode_needs_border_color(wrap_s) ||
wrap_mode_needs_border_color(wrap_t) ||
wrap_mode_needs_border_color(wrap_r)) {
- const struct gl_texture_image *first_image =
- texObj->Image[0][texObj->BaseLevel];
upload_default_color(brw, sampler,
- first_image->TexFormat, first_image->_BaseFormat,
- texObj->_IsIntegerFormat, &border_color_offset);
+ format, base_format, is_integer_format,
+ &border_color_offset);
}
- const bool non_normalized_coords = texObj->Target == GL_TEXTURE_RECTANGLE;
+ const bool non_normalized_coords = target == GL_TEXTURE_RECTANGLE;
brw_emit_sampler_state(brw,
sampler_state,
@@ -528,6 +521,29 @@ brw_update_sampler_state(struct brw_context *brw,
border_color_offset);
}
+static void
+update_sampler_state(struct brw_context *brw,
+ int unit,
+ uint32_t *sampler_state,
+ uint32_t batch_offset_for_sampler
Mesa (master): i965/gen8: Expose state base address setup
Module: Mesa
Branch: master
Commit: d7e49fba9a48b5f90c0ce8b7d0c0588545090a7f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7e49fba9a48b5f90c0ce8b7d0c0588545090a7f
Author: Topi Pohjolainen
Date: Mon Mar 2 11:29:05 2015 +0200
i965/gen8: Expose state base address setup
Reviewed-by: Kenneth Graunke
Reviewed-by: Matt Turner
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_state.h |3 +++
src/mesa/drivers/dri/i965/gen8_misc_state.c |4 ++--
2 files changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 13d541b..a2127d1 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -171,6 +171,9 @@ void brw_upload_invariant_state(struct brw_context *brw);
uint32_t
brw_depthbuffer_format(struct brw_context *brw);
+/* gen8_misc_state.c */
+void gen8_upload_state_base_address(struct brw_context *brw);
+
/***
* brw_state.c
diff --git a/src/mesa/drivers/dri/i965/gen8_misc_state.c
b/src/mesa/drivers/dri/i965/gen8_misc_state.c
index 88e425f..b20038e 100644
--- a/src/mesa/drivers/dri/i965/gen8_misc_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_misc_state.c
@@ -29,7 +29,7 @@
/**
* Define the base addresses which some state is referenced from.
*/
-static void upload_state_base_address(struct brw_context *brw)
+void gen8_upload_state_base_address(struct brw_context *brw)
{
uint32_t mocs_wb = brw->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
int pkt_len = brw->gen >= 9 ? 19 : 16;
@@ -78,5 +78,5 @@ const struct brw_tracked_state gen8_state_base_address = {
.brw = BRW_NEW_BATCH |
BRW_NEW_PROGRAM_CACHE,
},
- .emit = upload_state_base_address
+ .emit = gen8_upload_state_base_address
};
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Mesa (master): i965/blorp: Allow caller to provide sampler settings
Module: Mesa
Branch: master
Commit: 4de0bef7f438147091a7489728c4d187c6efbbc3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4de0bef7f438147091a7489728c4d187c6efbbc3
Author: Topi Pohjolainen
Date: Fri Feb 27 21:59:56 2015 +0200
i965/blorp: Allow caller to provide sampler settings
v2 (Ken): s/use_unorm_coords/non_normalized_coords/
Reviewed-by: Kenneth Graunke
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp.h|4 +++-
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 15 +--
src/mesa/drivers/dri/i965/gen7_blorp.cpp |3 ++-
3 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 59aecab..6aaae65 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -415,7 +415,9 @@ gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
uint32_t
gen6_blorp_emit_sampler_state(struct brw_context *brw,
- const brw_blorp_params *params);
+ unsigned tex_filter, unsigned max_lod,
+ bool non_normalized_coords);
+
/** \} */
#endif /* __cplusplus */
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 6c139ec..14e073b 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -455,7 +455,8 @@ gen6_blorp_emit_binding_table(struct brw_context *brw,
*/
uint32_t
gen6_blorp_emit_sampler_state(struct brw_context *brw,
- const brw_blorp_params *params)
+ unsigned tex_filter, unsigned max_lod,
+ bool non_normalized_coords)
{
uint32_t sampler_offset;
uint32_t *sampler_state = (uint32_t *)
@@ -476,8 +477,8 @@ gen6_blorp_emit_sampler_state(struct brw_context *brw,
brw_emit_sampler_state(brw,
sampler_state,
sampler_offset,
- BRW_MAPFILTER_LINEAR, /* min filter */
- BRW_MAPFILTER_LINEAR, /* mag filter */
+ tex_filter, /* min filter */
+ tex_filter, /* mag filter */
BRW_MIPFILTER_NONE,
BRW_ANISORATIO_2,
address_rounding,
@@ -485,11 +486,11 @@ gen6_blorp_emit_sampler_state(struct brw_context *brw,
BRW_TEXCOORDMODE_CLAMP,
BRW_TEXCOORDMODE_CLAMP,
0, /* min LOD */
- 0, /* max LOD */
+ max_lod,
0, /* LOD bias */
0, /* base miplevel */
0, /* shadow function */
- true, /* non-normalized coordinates */
+ non_normalized_coords,
0); /* border color offset - unused */
return sampler_offset;
@@ -1059,7 +1060,9 @@ gen6_blorp_exec(struct brw_context *brw,
gen6_blorp_emit_binding_table(brw, params,
wm_surf_offset_renderbuffer,
wm_surf_offset_texture);
- sampler_offset = gen6_blorp_emit_sampler_state(brw, params);
+ sampler_offset =
+ gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
+
gen6_blorp_emit_sampler_state_pointers(brw, params, sampler_offset);
}
gen6_blorp_emit_vs_disable(brw, params);
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 8215fe9..d841346 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -830,7 +830,8 @@ gen7_blorp_exec(struct brw_context *brw,
gen6_blorp_emit_binding_table(brw, params,
wm_surf_offset_renderbuffer,
wm_surf_offset_texture);
- sampler_offset = gen6_blorp_emit_sampler_state(brw, params);
+ sampler_offset =
+ gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
}
gen7_blorp_emit_vs_disable(brw, params);
gen7_blorp_emit_hs_disable(brw, params);
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Mesa (master): i965/blorp: Prepare for attributes other than render position
Module: Mesa
Branch: master
Commit: 7fb0db4dd18e49d3ccdb872f7ed174740301f3a2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7fb0db4dd18e49d3ccdb872f7ed174740301f3a2
Author: Topi Pohjolainen
Date: Fri Feb 27 11:45:34 2015 +0200
i965/blorp: Prepare for attributes other than render position
Note that the magic number of one in gen7 logic is replaced by
BRW_SF_URB_ENTRY_READ_OFFSET ( == 1 also) for clarity.
On gen6 the change from zero to one (BRW_SF_URB_ENTRY_READ_OFFSET)
has no effect for native blorp as blorp doesn't use any
additional attributes. In fact, regular pipeline setup always
uses BRW_SF_URB_ENTRY_READ_OFFSET even when there are no additional
attributes. Hence the change makes the two (blorp and regular)
consistent.
Reviewed-by: Kenneth Graunke
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp.cpp |5 +++--
src/mesa/drivers/dri/i965/brw_blorp.h|3 ++-
src/mesa/drivers/dri/i965/gen6_blorp.cpp |5 +++--
src/mesa/drivers/dri/i965/gen7_blorp.cpp |6 --
4 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index b0de55d..0c0cd2b 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -155,14 +155,15 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t
*tile_x,
}
-brw_blorp_params::brw_blorp_params()
+brw_blorp_params::brw_blorp_params(unsigned num_varyings)
: x0(0),
y0(0),
x1(0),
y1(0),
depth_format(0),
hiz_op(GEN6_HIZ_OP_NONE),
- use_wm_prog(false)
+ use_wm_prog(false),
+ num_varyings(num_varyings)
{
color_write_disable[0] = false;
color_write_disable[1] = false;
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index f277dee..0ba3891 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -211,7 +211,7 @@ struct brw_blorp_prog_data
class brw_blorp_params
{
public:
- brw_blorp_params();
+ explicit brw_blorp_params(unsigned num_varyings = 0);
virtual uint32_t get_wm_prog(struct brw_context *brw,
brw_blorp_prog_data **prog_data) const = 0;
@@ -228,6 +228,7 @@ public:
bool use_wm_prog;
brw_blorp_wm_push_constants wm_push_consts;
bool color_write_disable[4];
+ const unsigned num_varyings;
};
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 2fe2840..405a3e8 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -634,9 +634,10 @@ gen6_blorp_emit_sf_config(struct brw_context *brw,
{
BEGIN_BATCH(20);
OUT_BATCH(_3DSTATE_SF << 16 | (20 - 2));
- OUT_BATCH((1 - 1) << GEN6_SF_NUM_OUTPUTS_SHIFT | /* only position */
+ OUT_BATCH(params->num_varyings << GEN6_SF_NUM_OUTPUTS_SHIFT |
1 << GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT |
- 0 << GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT);
+ BRW_SF_URB_ENTRY_READ_OFFSET <<
+GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT);
OUT_BATCH(0); /* dw2 */
OUT_BATCH(params->dst.num_samples > 1 ? GEN6_SF_MSRAST_ON_PATTERN : 0);
for (int i = 0; i < 16; ++i)
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 12f515d..3065a4c 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -415,9 +415,11 @@ gen7_blorp_emit_sf_config(struct brw_context *brw,
{
BEGIN_BATCH(14);
OUT_BATCH(_3DSTATE_SBE << 16 | (14 - 2));
- OUT_BATCH((1 - 1) << GEN7_SBE_NUM_OUTPUTS_SHIFT | /* only position */
+ OUT_BATCH(GEN7_SBE_SWIZZLE_ENABLE |
+params->num_varyings << GEN7_SBE_NUM_OUTPUTS_SHIFT |
1 << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
-0 << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
+BRW_SF_URB_ENTRY_READ_OFFSET <<
+ GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT);
for (int i = 0; i < 12; ++i)
OUT_BATCH(0);
ADVANCE_BATCH();
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Mesa (master): i965: Refactor and expose brw_upload_binding_table()
Module: Mesa
Branch: master
Commit: 21071afc431bb17419c353151544518be7daf05f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=21071afc431bb17419c353151544518be7daf05f
Author: Topi Pohjolainen
Date: Thu Mar 19 10:42:49 2015 +0200
i965: Refactor and expose brw_upload_binding_table()
Read and write parts of the state stage are also split into
explicit arguments allowing future patches to use constant
program data.
v2 (Ken): s/BRW_NEW_WM_PROG_DATA/BRW_NEW_FS_PROG_DATA/
Reviewed-by: Kenneth Graunke
Reviewed-by: Matt Turner
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_binding_tables.c | 21 ++---
src/mesa/drivers/dri/i965/brw_state.h |7 +++
2 files changed, 21 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_binding_tables.c
b/src/mesa/drivers/dri/i965/brw_binding_tables.c
index 459165a..98ff0dd 100644
--- a/src/mesa/drivers/dri/i965/brw_binding_tables.c
+++ b/src/mesa/drivers/dri/i965/brw_binding_tables.c
@@ -50,15 +50,13 @@
* This copies brw_stage_state::surf_offset[] into the indirect state section
* of the batchbuffer (allocated by brw_state_batch()).
*/
-static void
+void
brw_upload_binding_table(struct brw_context *brw,
uint32_t packet_name,
GLbitfield brw_new_binding_table,
+ const struct brw_stage_prog_data *prog_data,
struct brw_stage_state *stage_state)
{
- /* BRW_NEW_*_PROG_DATA */
- struct brw_stage_prog_data *prog_data = stage_state->prog_data;
-
if (prog_data->binding_table.size_bytes == 0) {
/* There are no surfaces; skip making the binding table altogether. */
if (stage_state->bind_bo_offset == 0 && brw->gen < 9)
@@ -103,9 +101,12 @@ brw_upload_binding_table(struct brw_context *brw,
static void
brw_vs_upload_binding_table(struct brw_context *brw)
{
+ /* BRW_NEW_VS_PROG_DATA */
+ const struct brw_stage_prog_data *prog_data = brw->vs.base.prog_data;
brw_upload_binding_table(brw,
_3DSTATE_BINDING_TABLE_POINTERS_VS,
-BRW_NEW_VS_BINDING_TABLE, &brw->vs.base);
+BRW_NEW_VS_BINDING_TABLE, prog_data,
+&brw->vs.base);
}
const struct brw_tracked_state brw_vs_binding_table = {
@@ -124,9 +125,12 @@ const struct brw_tracked_state brw_vs_binding_table = {
static void
brw_upload_wm_binding_table(struct brw_context *brw)
{
+ /* BRW_NEW_FS_PROG_DATA */
+ const struct brw_stage_prog_data *prog_data = brw->wm.base.prog_data;
brw_upload_binding_table(brw,
_3DSTATE_BINDING_TABLE_POINTERS_PS,
-BRW_NEW_PS_BINDING_TABLE, &brw->wm.base);
+BRW_NEW_PS_BINDING_TABLE, prog_data,
+&brw->wm.base);
}
const struct brw_tracked_state brw_wm_binding_table = {
@@ -147,9 +151,12 @@ brw_gs_upload_binding_table(struct brw_context *brw)
if (brw->geometry_program == NULL)
return;
+ /* BRW_NEW_GS_PROG_DATA */
+ const struct brw_stage_prog_data *prog_data = brw->gs.base.prog_data;
brw_upload_binding_table(brw,
_3DSTATE_BINDING_TABLE_POINTERS_GS,
-BRW_NEW_GS_BINDING_TABLE, &brw->gs.base);
+BRW_NEW_GS_BINDING_TABLE, prog_data,
+&brw->gs.base);
}
const struct brw_tracked_state brw_gs_binding_table = {
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index 83058b9..8798369 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -159,6 +159,13 @@ brw_state_dirty(struct brw_context *brw, GLuint
mesa_flags, uint64_t brw_flags)
(brw->ctx.NewDriverState & brw_flags)) != 0;
}
+/* brw_binding_tables.c */
+void brw_upload_binding_table(struct brw_context *brw,
+ uint32_t packet_name,
+ GLbitfield brw_new_binding_table,
+ const struct brw_stage_prog_data *prog_data,
+ struct brw_stage_state *stage_state);
+
/* brw_misc_state.c */
void brw_upload_invariant_state(struct brw_context *brw);
uint32_t
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Mesa (master): i965/ps/gen7: Refactor state uploading
Module: Mesa
Branch: master
Commit: 4047420ec47488f2cdd7511cbeea95201b620480
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4047420ec47488f2cdd7511cbeea95201b620480
Author: Topi Pohjolainen
Date: Fri Feb 13 11:20:05 2015 +0200
i965/ps/gen7: Refactor state uploading
Now the uploading depends only on the input parameters instead
of consulting the current gl-state.
v2: Rebased on top of sampler count clamping
Reviewed-by: Kenneth Graunke
Reviewed-by: Matt Turner
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_state.h |9 +
src/mesa/drivers/dri/i965/gen7_wm_state.c | 56 ++---
2 files changed, 45 insertions(+), 20 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index ab067c3..f8d56b9 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -245,6 +245,15 @@ void brw_update_renderbuffer_surfaces(struct brw_context
*brw,
uint32_t render_target_start,
uint32_t *surf_offset);
+/* gen7_wm_state.c */
+void
+gen7_upload_ps_state(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_stage_state *stage_state,
+ const struct brw_wm_prog_data *prog_data,
+ bool enable_dual_src_blend, unsigned sample_mask,
+ unsigned fast_clear_op);
+
/* gen7_wm_surface_state.c */
uint32_t gen7_surface_tiling_mode(uint32_t tiling);
uint32_t gen7_surface_msaa_bits(unsigned num_samples, enum intel_msaa_layout
l);
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c
b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index 55a1acd..b918275 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -122,21 +122,23 @@ const struct brw_tracked_state gen7_wm_state = {
.emit = upload_wm_state,
};
-static void
-upload_ps_state(struct brw_context *brw)
+void
+gen7_upload_ps_state(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_stage_state *stage_state,
+ const struct brw_wm_prog_data *prog_data,
+ bool enable_dual_src_blend, unsigned sample_mask,
+ unsigned fast_clear_op)
{
struct gl_context *ctx = &brw->ctx;
uint32_t dw2, dw4, dw5, ksp0, ksp2;
const int max_threads_shift = brw->is_haswell ?
HSW_PS_MAX_THREADS_SHIFT : IVB_PS_MAX_THREADS_SHIFT;
- /* BRW_NEW_FS_PROG_DATA */
- const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
-
dw2 = dw4 = dw5 = ksp2 = 0;
const unsigned sampler_count =
- DIV_ROUND_UP(CLAMP(brw->wm.base.sampler_count, 0, 16), 4);
+ DIV_ROUND_UP(CLAMP(stage_state->sampler_count, 0, 16), 4);
dw2 |= SET_FIELD(sampler_count, GEN7_PS_SAMPLER_COUNT);
dw2 |= ((prog_data->base.binding_table.size_bytes / 4) <<
@@ -149,7 +151,7 @@ upload_ps_state(struct brw_context *brw)
* in 3DSTATE_SAMPLE_MASK; the values should match. */
/* _NEW_BUFFERS, _NEW_MULTISAMPLE */
if (brw->is_haswell)
- dw4 |= SET_FIELD(gen6_determine_sample_mask(brw), HSW_PS_SAMPLE_MASK);
+ dw4 |= SET_FIELD(sample_mask, HSW_PS_SAMPLE_MASK);
dw4 |= (brw->max_wm_threads - 1) << max_threads_shift;
@@ -182,16 +184,11 @@ upload_ps_state(struct brw_context *brw)
else
dw4 |= GEN7_PS_POSOFFSET_NONE;
- /* BRW_NEW_FS_PROG_DATA | _NEW_COLOR
-*
-* The hardware wedges if you have this bit set but don't turn on any dual
+ /* The hardware wedges if you have this bit set but don't turn on any dual
* source blend factors.
*/
- if (prog_data->dual_src_blend &&
- (ctx->Color.BlendEnabled & 1) &&
- ctx->Color.Blend[0]._UsesDualSrc) {
+ if (enable_dual_src_blend)
dw4 |= GEN7_PS_DUAL_SOURCE_BLEND_ENABLE;
- }
/* BRW_NEW_FS_PROG_DATA */
if (prog_data->num_varying_inputs != 0)
@@ -203,7 +200,7 @@ upload_ps_state(struct brw_context *brw)
* better performance than 'SIMD8 only' dispatch.
*/
int min_inv_per_frag =
- _mesa_get_min_invocations_per_fragment(ctx, brw->fragment_program,
false);
+ _mesa_get_min_invocations_per_fragment(ctx, fp, false);
assert(min_inv_per_frag >= 1);
if (prog_data->prog_offset_16 || prog_data->no_8) {
@@ -214,22 +211,22 @@ upload_ps_state(struct brw_context *brw)
GEN7_PS_DISPATCH_START_GRF_SHIFT_0);
dw5 |= (prog_data->dispatch_grf_start_reg_16 <<
GEN7_PS_DISPATCH_START_GRF_SHIFT_2);
- ksp0 = brw->wm.base.prog_offset;
- ksp2 = brw->wm.base.prog_offset + prog_data->prog_offset_16;
+ ksp0 = stage_state->prog_offset;
+ ksp2 = stage_state->prog_offset + prog_data->prog_offset_16;
} else {
dw5 |= (prog_data->dispatch_grf_start_
Mesa (master): i965/blorp: Prepare drawing rectangle for flipped coordinates
Module: Mesa Branch: master Commit: 13670e8bade296c5c5846dc08615563ad51685e4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=13670e8bade296c5c5846dc08615563ad51685e4 Author: Topi Pohjolainen Date: Sun Mar 29 21:52:02 2015 +0300 i965/blorp: Prepare drawing rectangle for flipped coordinates Reviewed-by: Kenneth Graunke Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_blorp.cpp |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index ed08898..b6a3d78 100644 --- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp +++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp @@ -950,8 +950,8 @@ gen6_blorp_emit_drawing_rectangle(struct brw_context *brw, BEGIN_BATCH(4); OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2)); OUT_BATCH(0); - OUT_BATCH(((params->x1 - 1) & 0x) | - ((params->y1 - 1) << 16)); + OUT_BATCH(((MAX2(params->x1, params->x0) - 1) & 0x) | + ((MAX2(params->y1, params->y0) - 1) << 16)); OUT_BATCH(0); ADVANCE_BATCH(); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/blorp: Remove unused arguments
Module: Mesa
Branch: master
Commit: 25ce6c6943576e22d8d00049578d0e6cc5feea07
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=25ce6c6943576e22d8d00049578d0e6cc5feea07
Author: Topi Pohjolainen
Date: Fri Jan 30 11:37:54 2015 +0200
i965/blorp: Remove unused arguments
Reviewed-by: Kenneth Graunke
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp.h|7 ++-
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 20 +++-
src/mesa/drivers/dri/i965/gen7_blorp.cpp |6 +++---
3 files changed, 12 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 6aaae65..f277dee 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -380,8 +380,7 @@ gen6_blorp_emit_blend_state(struct brw_context *brw,
const brw_blorp_params *params);
uint32_t
-gen6_blorp_emit_cc_state(struct brw_context *brw,
- const brw_blorp_params *params);
+gen6_blorp_emit_cc_state(struct brw_context *brw);
uint32_t
gen6_blorp_emit_wm_constants(struct brw_context *brw,
@@ -393,7 +392,6 @@ gen6_blorp_emit_vs_disable(struct brw_context *brw,
uint32_t
gen6_blorp_emit_binding_table(struct brw_context *brw,
- const brw_blorp_params *params,
uint32_t wm_surf_offset_renderbuffer,
uint32_t wm_surf_offset_texture);
@@ -406,8 +404,7 @@ gen6_blorp_emit_gs_disable(struct brw_context *brw,
const brw_blorp_params *params);
void
-gen6_blorp_emit_clip_disable(struct brw_context *brw,
- const brw_blorp_params *params);
+gen6_blorp_emit_clip_disable(struct brw_context *brw);
void
gen6_blorp_emit_drawing_rectangle(struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 14e073b..2fe2840 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -268,8 +268,7 @@ gen6_blorp_emit_blend_state(struct brw_context *brw,
/* CC_STATE */
uint32_t
-gen6_blorp_emit_cc_state(struct brw_context *brw,
- const brw_blorp_params *params)
+gen6_blorp_emit_cc_state(struct brw_context *brw)
{
uint32_t cc_state_offset;
@@ -431,7 +430,6 @@ gen6_blorp_emit_surface_state(struct brw_context *brw,
/* BINDING_TABLE. See brw_wm_binding_table(). */
uint32_t
gen6_blorp_emit_binding_table(struct brw_context *brw,
- const brw_blorp_params *params,
uint32_t wm_surf_offset_renderbuffer,
uint32_t wm_surf_offset_texture)
{
@@ -502,7 +500,6 @@ gen6_blorp_emit_sampler_state(struct brw_context *brw,
*/
static void
gen6_blorp_emit_sampler_state_pointers(struct brw_context *brw,
- const brw_blorp_params *params,
uint32_t sampler_offset)
{
BEGIN_BATCH(4);
@@ -602,8 +599,7 @@ gen6_blorp_emit_gs_disable(struct brw_context *brw,
* output, but does spare a few electrons.
*/
void
-gen6_blorp_emit_clip_disable(struct brw_context *brw,
- const brw_blorp_params *params)
+gen6_blorp_emit_clip_disable(struct brw_context *brw)
{
BEGIN_BATCH(4);
OUT_BATCH(_3DSTATE_CLIP << 16 | (4 - 2));
@@ -767,7 +763,6 @@ gen6_blorp_emit_constant_ps_disable(struct brw_context *brw,
*/
static void
gen6_blorp_emit_binding_table_pointers(struct brw_context *brw,
- const brw_blorp_params *params,
uint32_t wm_bind_bo_offset)
{
BEGIN_BATCH(4);
@@ -1036,7 +1031,7 @@ gen6_blorp_exec(struct brw_context *brw,
gen6_blorp_emit_urb_config(brw, params);
if (params->use_wm_prog) {
cc_blend_state_offset = gen6_blorp_emit_blend_state(brw, params);
- cc_state_offset = gen6_blorp_emit_cc_state(brw, params);
+ cc_state_offset = gen6_blorp_emit_cc_state(brw);
}
depthstencil_offset = gen6_blorp_emit_depth_stencil_state(brw, params);
gen6_blorp_emit_cc_state_pointers(brw, params, cc_blend_state_offset,
@@ -1057,17 +1052,16 @@ gen6_blorp_exec(struct brw_context *brw,
I915_GEM_DOMAIN_SAMPLER, 0);
}
wm_bind_bo_offset =
- gen6_blorp_emit_binding_table(brw, params,
+ gen6_blorp_emit_binding_table(brw,
wm_surf_offset_renderbuffer,
wm_surf_offset_texture);
sampler_offset =
gen6_blorp_emit_sampler_state(brw, BRW_MAPFILTER_LINEAR, 0, true);
-
- gen6_blorp_emit_sampler_state_pointers(brw, params, sampler_offset);
+ gen6_blorp_emit_sampler_state_pointers(brw, sampler_offse
Mesa (master): i965/blorp: Add support for layered rendering
Module: Mesa
Branch: master
Commit: dfd896699d9f640518c0fbafb0352f454d5fc466
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dfd896699d9f640518c0fbafb0352f454d5fc466
Author: Topi Pohjolainen
Date: Fri Mar 27 16:25:56 2015 +0200
i965/blorp: Add support for layered rendering
Reviewed-by: Kenneth Graunke
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp.cpp |6 --
src/mesa/drivers/dri/i965/brw_blorp.h|4 +++-
src/mesa/drivers/dri/i965/gen6_blorp.cpp |2 +-
src/mesa/drivers/dri/i965/gen7_blorp.cpp |2 +-
4 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 8f82851..b404869 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -156,7 +156,8 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t
*tile_x,
brw_blorp_params::brw_blorp_params(unsigned num_varyings,
- unsigned num_draw_buffers)
+ unsigned num_draw_buffers,
+ unsigned num_layers)
: x0(0),
y0(0),
x1(0),
@@ -165,7 +166,8 @@ brw_blorp_params::brw_blorp_params(unsigned num_varyings,
hiz_op(GEN6_HIZ_OP_NONE),
use_wm_prog(false),
num_varyings(num_varyings),
- num_draw_buffers(num_draw_buffers)
+ num_draw_buffers(num_draw_buffers),
+ num_layers(num_layers)
{
}
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index c9957a6..dd28d81 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -212,7 +212,8 @@ class brw_blorp_params
{
public:
brw_blorp_params(unsigned num_varyings = 0,
-unsigned num_draw_buffers = 1);
+unsigned num_draw_buffers = 1,
+unsigned num_layers = 1);
virtual uint32_t get_wm_prog(struct brw_context *brw,
brw_blorp_prog_data **prog_data) const = 0;
@@ -230,6 +231,7 @@ public:
brw_blorp_wm_push_constants wm_push_consts;
const unsigned num_varyings;
const unsigned num_draw_buffers;
+ const unsigned num_layers;
};
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index bfd2001..ed08898 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -992,7 +992,7 @@ gen6_blorp_emit_primitive(struct brw_context *brw,
GEN4_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL);
OUT_BATCH(3); /* vertex count per instance */
OUT_BATCH(0);
- OUT_BATCH(1); /* instance count */
+ OUT_BATCH(params->num_layers); /* instance count */
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
index 3065a4c..2bdc82b 100644
--- a/src/mesa/drivers/dri/i965/gen7_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen7_blorp.cpp
@@ -753,7 +753,7 @@ gen7_blorp_emit_primitive(struct brw_context *brw,
_3DPRIM_RECTLIST);
OUT_BATCH(3); /* vertex count per instance */
OUT_BATCH(0);
- OUT_BATCH(1); /* instance count */
+ OUT_BATCH(params->num_layers); /* instance count */
OUT_BATCH(0);
OUT_BATCH(0);
ADVANCE_BATCH();
___
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Mesa (master): i965/gen8: Use constant pointers for reading miptree details
Module: Mesa
Branch: master
Commit: d6c83c9d863f9f13e46584b93cbab6d3a3885aea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6c83c9d863f9f13e46584b93cbab6d3a3885aea
Author: Topi Pohjolainen
Date: Sun Mar 1 22:23:33 2015 +0200
i965/gen8: Use constant pointers for reading miptree details
Reviewed-by: Matt Turner
Reviewed-by: Kenneth Graunke
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/gen8_surface_state.c |4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index b8ef353..f347065 100644
--- a/src/mesa/drivers/dri/i965/gen8_surface_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_surface_state.c
@@ -70,7 +70,7 @@ surface_tiling_mode(uint32_t tiling)
}
static unsigned
-vertical_alignment(struct intel_mipmap_tree *mt)
+vertical_alignment(const struct intel_mipmap_tree *mt)
{
switch (mt->align_h) {
case 4:
@@ -85,7 +85,7 @@ vertical_alignment(struct intel_mipmap_tree *mt)
}
static unsigned
-horizontal_alignment(struct intel_mipmap_tree *mt)
+horizontal_alignment(const struct intel_mipmap_tree *mt)
{
switch (mt->align_w) {
case 4:
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Mesa (master): i965/ps/gen8: Refactor state uploading
Module: Mesa
Branch: master
Commit: fea168f49584333aeeabad2d2b0dc6aaee86f881
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fea168f49584333aeeabad2d2b0dc6aaee86f881
Author: Topi Pohjolainen
Date: Mon Mar 2 12:31:17 2015 +0200
i965/ps/gen8: Refactor state uploading
v2: Use SET_FIELD() for sampler count, and for that reason
added GEN7_PS_SAMPLER_COUNT_MASK.
Reviewed-by: Kenneth Graunke
Reviewed-by: Matt Turner
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_state.h | 12 +
src/mesa/drivers/dri/i965/gen8_ps_state.c | 72 ++---
2 files changed, 58 insertions(+), 26 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_state.h
b/src/mesa/drivers/dri/i965/brw_state.h
index f8d56b9..13d541b 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -265,6 +265,18 @@ void gen7_set_surface_mcs_info(struct brw_context *brw,
void gen7_check_surface_setup(uint32_t *surf, bool is_render_target);
void gen7_init_vtable_surface_functions(struct brw_context *brw);
+/* gen8_ps_state.c */
+void gen8_upload_ps_state(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_stage_state *stage_state,
+ const struct brw_wm_prog_data *prog_data,
+ uint32_t fast_clear_op);
+
+void gen8_upload_ps_extra(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_wm_prog_data *prog_data,
+ bool multisampled_fbo);
+
/* gen7_sol_state.c */
void gen7_upload_3dstate_so_decl_list(struct brw_context *brw,
const struct brw_vue_map *vue_map);
diff --git a/src/mesa/drivers/dri/i965/gen8_ps_state.c
b/src/mesa/drivers/dri/i965/gen8_ps_state.c
index 8481153..85ad3b6 100644
--- a/src/mesa/drivers/dri/i965/gen8_ps_state.c
+++ b/src/mesa/drivers/dri/i965/gen8_ps_state.c
@@ -27,15 +27,13 @@
#include "brw_defines.h"
#include "intel_batchbuffer.h"
-static void
-upload_ps_extra(struct brw_context *brw)
+void
+gen8_upload_ps_extra(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_wm_prog_data *prog_data,
+ bool multisampled_fbo)
{
struct gl_context *ctx = &brw->ctx;
- /* BRW_NEW_FRAGMENT_PROGRAM */
- const struct brw_fragment_program *fp =
- brw_fragment_program_const(brw->fragment_program);
- /* BRW_NEW_FS_PROG_DATA */
- const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
uint32_t dw1 = 0;
dw1 |= GEN8_PSX_PIXEL_SHADER_VALID;
@@ -47,16 +45,14 @@ upload_ps_extra(struct brw_context *brw)
if (prog_data->num_varying_inputs != 0)
dw1 |= GEN8_PSX_ATTRIBUTE_ENABLE;
- if (fp->program.Base.InputsRead & VARYING_BIT_POS)
+ if (fp->Base.InputsRead & VARYING_BIT_POS)
dw1 |= GEN8_PSX_USES_SOURCE_DEPTH | GEN8_PSX_USES_SOURCE_W;
- /* BRW_NEW_NUM_SAMPLES | _NEW_MULTISAMPLE */
- bool multisampled_fbo = brw->num_samples > 1;
if (multisampled_fbo &&
- _mesa_get_min_invocations_per_fragment(ctx, &fp->program, false) > 1)
+ _mesa_get_min_invocations_per_fragment(ctx, fp, false) > 1)
dw1 |= GEN8_PSX_SHADER_IS_PER_SAMPLE;
- if (fp->program.Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN)
+ if (fp->Base.SystemValuesRead & SYSTEM_BIT_SAMPLE_MASK_IN)
dw1 |= GEN8_PSX_SHADER_USES_INPUT_COVERAGE_MASK;
if (prog_data->uses_omask)
@@ -68,6 +64,20 @@ upload_ps_extra(struct brw_context *brw)
ADVANCE_BATCH();
}
+static void
+upload_ps_extra(struct brw_context *brw)
+{
+ /* BRW_NEW_FRAGMENT_PROGRAM */
+ const struct brw_fragment_program *fp =
+ brw_fragment_program_const(brw->fragment_program);
+ /* BRW_NEW_FS_PROG_DATA */
+ const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
+ /* BRW_NEW_NUM_SAMPLES | _NEW_MULTISAMPLE */
+ const bool multisampled_fbo = brw->num_samples > 1;
+
+ gen8_upload_ps_extra(brw, &fp->program, prog_data, multisampled_fbo);
+}
+
const struct brw_tracked_state gen8_ps_extra = {
.dirty = {
.mesa = _NEW_MULTISAMPLE,
@@ -118,15 +128,16 @@ const struct brw_tracked_state gen8_wm_state = {
.emit = upload_wm_state,
};
-static void
-upload_ps_state(struct brw_context *brw)
+void
+gen8_upload_ps_state(struct brw_context *brw,
+ const struct gl_fragment_program *fp,
+ const struct brw_stage_state *stage_state,
+ const struct brw_wm_prog_data *prog_data,
+ uint32_t fast_clear_op)
{
struct gl_context *ctx = &brw->ctx;
uint32_t dw3 = 0, dw6 = 0, dw7 = 0, ksp0, ksp2 = 0;
- /* BRW_NEW_FS_PROG_DATA */
- const struct brw_wm_prog_data *prog_data = brw->wm.prog_data;
-
/* Initialize the execution mask with VMask. Otherwise, derivatives a
Mesa (master): i965/blorp: Allow blend state to be set for multiple render targets
Module: Mesa
Branch: master
Commit: 91daf9f09bac41c84c6868a56e0d538cc59cc334
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=91daf9f09bac41c84c6868a56e0d538cc59cc334
Author: Topi Pohjolainen
Date: Thu Mar 26 16:43:31 2015 +0200
i965/blorp: Allow blend state to be set for multiple render targets
Original blorp writes only one buffer per shader invocation. Once
the launch mechanism is shared with glsl-based programs there will
be need for supporting multiple render targets.
Also drop the always constant color write disable settings.
Reviewed-by: Kenneth Graunke
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 10 --
src/mesa/drivers/dri/i965/brw_blorp.h|5 +++--
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 22 +++---
3 files changed, 18 insertions(+), 19 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 0c0cd2b..8f82851 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -155,7 +155,8 @@ brw_blorp_surface_info::compute_tile_offsets(uint32_t
*tile_x,
}
-brw_blorp_params::brw_blorp_params(unsigned num_varyings)
+brw_blorp_params::brw_blorp_params(unsigned num_varyings,
+ unsigned num_draw_buffers)
: x0(0),
y0(0),
x1(0),
@@ -163,12 +164,9 @@ brw_blorp_params::brw_blorp_params(unsigned num_varyings)
depth_format(0),
hiz_op(GEN6_HIZ_OP_NONE),
use_wm_prog(false),
- num_varyings(num_varyings)
+ num_varyings(num_varyings),
+ num_draw_buffers(num_draw_buffers)
{
- color_write_disable[0] = false;
- color_write_disable[1] = false;
- color_write_disable[2] = false;
- color_write_disable[3] = false;
}
extern "C" {
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 0ba3891..c9957a6 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -211,7 +211,8 @@ struct brw_blorp_prog_data
class brw_blorp_params
{
public:
- explicit brw_blorp_params(unsigned num_varyings = 0);
+ brw_blorp_params(unsigned num_varyings = 0,
+unsigned num_draw_buffers = 1);
virtual uint32_t get_wm_prog(struct brw_context *brw,
brw_blorp_prog_data **prog_data) const = 0;
@@ -227,8 +228,8 @@ public:
enum gen6_hiz_op hiz_op;
bool use_wm_prog;
brw_blorp_wm_push_constants wm_push_consts;
- bool color_write_disable[4];
const unsigned num_varyings;
+ const unsigned num_draw_buffers;
};
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index 405a3e8..bfd2001 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -246,21 +246,21 @@ gen6_blorp_emit_blend_state(struct brw_context *brw,
{
uint32_t cc_blend_state_offset;
+ assume(params->num_draw_buffers);
+
+ const unsigned size = params->num_draw_buffers *
+ sizeof(struct gen6_blend_state);
struct gen6_blend_state *blend = (struct gen6_blend_state *)
- brw_state_batch(brw, AUB_TRACE_BLEND_STATE,
- sizeof(struct gen6_blend_state), 64,
+ brw_state_batch(brw, AUB_TRACE_BLEND_STATE, size, 64,
&cc_blend_state_offset);
- memset(blend, 0, sizeof(*blend));
-
- blend->blend1.pre_blend_clamp_enable = 1;
- blend->blend1.post_blend_clamp_enable = 1;
- blend->blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT;
+ memset(blend, 0, size);
- blend->blend1.write_disable_r = params->color_write_disable[0];
- blend->blend1.write_disable_g = params->color_write_disable[1];
- blend->blend1.write_disable_b = params->color_write_disable[2];
- blend->blend1.write_disable_a = params->color_write_disable[3];
+ for (unsigned i = 0; i < params->num_draw_buffers; ++i) {
+ blend[i].blend1.pre_blend_clamp_enable = 1;
+ blend[i].blend1.post_blend_clamp_enable = 1;
+ blend[i].blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT;
+ }
return cc_blend_state_offset;
}
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Mesa (master): i965: Refactor rb surface setup to allow caller to store offsets
Module: Mesa
Branch: master
Commit: c8b0d890c0b7e6aa5ed326b94ac30dcb7278e7ea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c8b0d890c0b7e6aa5ed326b94ac30dcb7278e7ea
Author: Topi Pohjolainen
Date: Tue Mar 17 13:09:16 2015 +0200
i965: Refactor rb surface setup to allow caller to store offsets
Notice that in gen7_wm_surface_state.c there is also indentation
change in the surrounding code removing tabs.
v2 (Matt): Fixed whitespace: tabs -> spaces
Reviewed-by: Kenneth Graunke
Reviewed-by: Matt Turner
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_context.h |8 ++---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 38 +++--
src/mesa/drivers/dri/i965/gen6_surface_state.c| 25 +++---
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 28 +++
src/mesa/drivers/dri/i965/gen8_surface_state.c| 18 +-
5 files changed, 59 insertions(+), 58 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 8db1028..e2f26f5 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -967,10 +967,10 @@ struct brw_context
unsigned unit,
uint32_t *surf_offset,
bool for_gather);
- void (*update_renderbuffer_surface)(struct brw_context *brw,
- struct gl_renderbuffer *rb,
- bool layered,
- unsigned unit);
+ uint32_t (*update_renderbuffer_surface)(struct brw_context *brw,
+ struct gl_renderbuffer *rb,
+ bool layered, unsigned unit,
+ uint32_t surf_index);
void (*emit_texture_surface_state)(struct brw_context *brw,
struct intel_mipmap_tree *mt,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 161d140..d451940 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -626,11 +626,11 @@ brw_emit_null_surface_state(struct brw_context *brw,
* While it is only used for the front/back buffer currently, it should be
* usable for further buffers when doing ARB_draw_buffer support.
*/
-static void
+static uint32_t
brw_update_renderbuffer_surface(struct brw_context *brw,
- struct gl_renderbuffer *rb,
- bool layered,
- unsigned int unit)
+struct gl_renderbuffer *rb,
+bool layered, unsigned unit,
+uint32_t surf_index)
{
struct gl_context *ctx = &brw->ctx;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
@@ -638,11 +638,10 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
uint32_t *surf;
uint32_t tile_x, tile_y;
uint32_t format = 0;
+ uint32_t offset;
/* _NEW_BUFFERS */
mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb));
/* BRW_NEW_FS_PROG_DATA */
- uint32_t surf_index =
- brw->wm.prog_data->binding_table.render_target_start + unit;
assert(!layered);
@@ -663,8 +662,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
intel_miptree_used_for_rendering(irb->mt);
- surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32,
- &brw->wm.base.surf_offset[surf_index]);
+ surf = brw_state_batch(brw, AUB_TRACE_SURFACE_STATE, 6 * 4, 32, &offset);
format = brw->render_target_format[rb_format];
if (unlikely(!brw->format_supported_as_render_target[rb_format])) {
@@ -721,11 +719,13 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
}
drm_intel_bo_emit_reloc(brw->batch.bo,
- brw->wm.base.surf_offset[surf_index] + 4,
- mt->bo,
- surf[1] - mt->bo->offset64,
- I915_GEM_DOMAIN_RENDER,
- I915_GEM_DOMAIN_RENDER);
+ offset + 4,
+ mt->bo,
+ surf[1] - mt->bo->offset64,
+ I915_GEM_DOMAIN_RENDER,
+ I915_GEM_DOMAIN_RENDER);
+
+ return offset;
}
/**
@@ -743,13 +743,15 @@ brw_update_renderbuffer_surfaces(struct brw_context *brw)
/* Update surfaces for drawing buffers */
if (ctx->DrawBuffer->_NumColorDrawBuffers >= 1) {
for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) {
+ const uint32_t surf_index =
+brw->wm.prog_data->binding_table.render_target_start +
Mesa (master): i965: Remove dependency to tex object in default color setup
Module: Mesa
Branch: master
Commit: 47f32cb50d19145ed502e1fccd949d931c0cd392
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=47f32cb50d19145ed502e1fccd949d931c0cd392
Author: Topi Pohjolainen
Date: Sat Apr 4 20:28:45 2015 +0300
i965: Remove dependency to tex object in default color setup
Reviewed-by: Kenneth Graunke
Reviewed-by: Matt Turner
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_sampler_state.c | 22 +++---
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c
b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index c4bd949..c78e2e3 100644
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -201,16 +201,13 @@ wrap_mode_needs_border_color(unsigned wrap_mode)
static void
upload_default_color(struct brw_context *brw,
const struct gl_sampler_object *sampler,
- int unit,
+ mesa_format format, GLenum base_format,
+ bool is_integer_format,
uint32_t *sdc_offset)
{
- struct gl_context *ctx = &brw->ctx;
- struct gl_texture_unit *texUnit = &ctx->Texture.Unit[unit];
- struct gl_texture_object *texObj = texUnit->_Current;
- struct gl_texture_image *firstImage = texObj->Image[0][texObj->BaseLevel];
union gl_color_union color;
- switch (firstImage->_BaseFormat) {
+ switch (base_format) {
case GL_DEPTH_COMPONENT:
/* GL specs that border color for depth textures is taken from the
* R channel, while the hardware uses A. Spam R into all the
@@ -257,7 +254,7 @@ upload_default_color(struct brw_context *brw,
* where we've initialized the A channel to 1.0. We also have to set
* the border color alpha to 1.0 in that case.
*/
- if (firstImage->_BaseFormat == GL_RGB)
+ if (base_format == GL_RGB)
color.ui[3] = float_as_int(1.0);
if (brw->gen >= 8) {
@@ -269,7 +266,7 @@ upload_default_color(struct brw_context *brw,
uint32_t *sdc = brw_state_batch(brw, AUB_TRACE_SAMPLER_DEFAULT_COLOR,
4 * 4, 64, sdc_offset);
memcpy(sdc, color.ui, 4 * 4);
- } else if (brw->is_haswell && texObj->_IsIntegerFormat) {
+ } else if (brw->is_haswell && is_integer_format) {
/* Haswell's integer border color support is completely insane:
* SAMPLER_BORDER_COLOR_STATE is 20 DWords. The first four are
* for float colors. The next 12 DWords are MBZ and only exist to
@@ -283,7 +280,6 @@ upload_default_color(struct brw_context *brw,
memset(sdc, 0, 20 * 4);
sdc = &sdc[16];
- mesa_format format = firstImage->TexFormat;
int bits_per_channel = _mesa_get_format_bits(format, GL_RED_BITS);
/* From the Haswell PRM, "Command Reference: Structures", Page 36:
@@ -314,7 +310,7 @@ upload_default_color(struct brw_context *brw,
((uint16_t *) sdc)[5] = c[3]; /* A -> DWord 3, bits 31:16 */
break;
case 32:
- if (firstImage->_BaseFormat == GL_RG) {
+ if (base_format == GL_RG) {
/* Careful inspection of the tables reveals that for RG32 formats,
* the green channel needs to go where blue normally belongs.
*/
@@ -510,7 +506,11 @@ brw_update_sampler_state(struct brw_context *brw,
if (wrap_mode_needs_border_color(wrap_s) ||
wrap_mode_needs_border_color(wrap_t) ||
wrap_mode_needs_border_color(wrap_r)) {
- upload_default_color(brw, sampler, unit, &border_color_offset);
+ const struct gl_texture_image *first_image =
+ texObj->Image[0][texObj->BaseLevel];
+ upload_default_color(brw, sampler,
+ first_image->TexFormat, first_image->_BaseFormat,
+ texObj->_IsIntegerFormat, &border_color_offset);
}
const bool non_normalized_coords = texObj->Target == GL_TEXTURE_RECTANGLE;
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Mesa (master): i965/blorp: Refactor vertex buffer state setup
Module: Mesa
Branch: master
Commit: bfdacac86cf82a1ae8d76e3282b8842f08a21c31
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bfdacac86cf82a1ae8d76e3282b8842f08a21c31
Author: Topi Pohjolainen
Date: Fri Feb 27 11:17:05 2015 +0200
i965/blorp: Refactor vertex buffer state setup
Reviewed-by: Kenneth Graunke
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 60 +-
1 file changed, 34 insertions(+), 26 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
index e45705a..6c139ec 100644
--- a/src/mesa/drivers/dri/i965/gen6_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/gen6_blorp.cpp
@@ -93,6 +93,37 @@ gen6_blorp_emit_state_base_address(struct brw_context *brw,
ADVANCE_BATCH();
}
+static void
+gen6_blorp_emit_vertex_buffer_state(struct brw_context *brw,
+unsigned num_elems,
+unsigned vbo_size,
+uint32_t vertex_offset)
+{
+ /* 3DSTATE_VERTEX_BUFFERS */
+ const int num_buffers = 1;
+ const int batch_length = 1 + 4 * num_buffers;
+
+ uint32_t dw0 = GEN6_VB0_ACCESS_VERTEXDATA |
+ (num_elems * sizeof(float)) << BRW_VB0_PITCH_SHIFT;
+
+ if (brw->gen >= 7)
+ dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
+
+ if (brw->gen == 7)
+ dw0 |= GEN7_MOCS_L3 << 16;
+
+ BEGIN_BATCH(batch_length);
+ OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2));
+ OUT_BATCH(dw0);
+ /* start address */
+ OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
+ vertex_offset);
+ /* end address */
+ OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
+ vertex_offset + vbo_size - 1);
+ OUT_BATCH(0);
+ ADVANCE_BATCH();
+}
void
gen6_blorp_emit_vertices(struct brw_context *brw,
@@ -144,32 +175,9 @@ gen6_blorp_emit_vertices(struct brw_context *brw,
memcpy(vertex_data, vertices, GEN6_BLORP_VBO_SIZE);
}
- /* 3DSTATE_VERTEX_BUFFERS */
- {
- const int num_buffers = 1;
- const int batch_length = 1 + 4 * num_buffers;
-
- uint32_t dw0 = GEN6_VB0_ACCESS_VERTEXDATA |
- (GEN6_BLORP_NUM_VUE_ELEMS * sizeof(float)) <<
BRW_VB0_PITCH_SHIFT;
-
- if (brw->gen >= 7)
- dw0 |= GEN7_VB0_ADDRESS_MODIFYENABLE;
-
- if (brw->gen == 7)
- dw0 |= GEN7_MOCS_L3 << 16;
-
- BEGIN_BATCH(batch_length);
- OUT_BATCH((_3DSTATE_VERTEX_BUFFERS << 16) | (batch_length - 2));
- OUT_BATCH(dw0);
- /* start address */
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
- vertex_offset);
- /* end address */
- OUT_RELOC(brw->batch.bo, I915_GEM_DOMAIN_VERTEX, 0,
- vertex_offset + GEN6_BLORP_VBO_SIZE - 1);
- OUT_BATCH(0);
- ADVANCE_BATCH();
- }
+ gen6_blorp_emit_vertex_buffer_state(brw, GEN6_BLORP_NUM_VUE_ELEMS,
+ GEN6_BLORP_VBO_SIZE,
+ vertex_offset);
/* 3DSTATE_VERTEX_ELEMENTS
*
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Mesa (master): gk110/ir: fix set with a register dest to not auto-set the abs flag
Module: Mesa
Branch: master
Commit: 515ac907e68ae1485bd9c65d7351dfb3c3d1e33f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=515ac907e68ae1485bd9c65d7351dfb3c3d1e33f
Author: Ilia Mirkin
Date: Wed Apr 29 18:01:53 2015 -0400
gk110/ir: fix set with a register dest to not auto-set the abs flag
This was causing src0 to always have the absolute value flag set.
Signed-off-by: Ilia Mirkin
Cc: mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
index a73bee2..d7c6b80 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp
@@ -971,7 +971,7 @@ CodeEmitterGK110::emitSET(const CmpInstruction *i)
code[0] |= 0x1c;
} else {
switch (i->sType) {
- case TYPE_F32: op2 = 0x000; op1 = 0x820; break;
+ case TYPE_F32: op2 = 0x000; op1 = 0x800; break;
case TYPE_F64: op2 = 0x080; op1 = 0x900; break;
default:
op2 = 0x1a8;
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Mesa (master): nvc0/ir: fix predicated PFETCH emission
Module: Mesa Branch: master Commit: a9d08a250ada5fbd4e3f78f8e4119ec295d692cf URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9d08a250ada5fbd4e3f78f8e4119ec295d692cf Author: Ilia Mirkin Date: Wed Apr 29 23:05:44 2015 -0400 nvc0/ir: fix predicated PFETCH emission src1 would contain the predicate, which would get emitted as a register source by an undiscerning srcId helper. Work around this in the same way as in emitTEX. Signed-off-by: Ilia Mirkin Cc: mesa-sta...@lists.freedesktop.org --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp |4 +++- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp |4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp index d7c6b80..a6e6c1f 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp @@ -1333,8 +1333,10 @@ CodeEmitterGK110::emitPFETCH(const Instruction *i) emitPredicate(i); + const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2) + defId(i->def(0), 2); - srcId(i->src(1), 10); + srcId(i, 1, 10); } void diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp index 1a4f6e0..4ad098e 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp @@ -1495,8 +1495,10 @@ CodeEmitterNVC0::emitPFETCH(const Instruction *i) emitPredicate(i); + const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2) + defId(i->def(0), 14); - srcId(i->src(1), 20); + srcId(i, 1, 20); } void ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nv50/ir: fix asFlow() const helper for OP_JOIN
Module: Mesa
Branch: master
Commit: db269ae495425849804fb1d05cfe42b0d3d304b3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=db269ae495425849804fb1d05cfe42b0d3d304b3
Author: Ilia Mirkin
Date: Wed Apr 29 23:33:27 2015 -0400
nv50/ir: fix asFlow() const helper for OP_JOIN
Signed-off-by: Ilia Mirkin
Cc: mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h
index 255324f..e465f24 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_inlines.h
@@ -302,7 +302,7 @@ FlowInstruction *Instruction::asFlow()
const FlowInstruction *Instruction::asFlow() const
{
- if (op >= OP_BRA && op <= OP_JOINAT)
+ if (op >= OP_BRA && op <= OP_JOIN)
return static_cast(this);
return NULL;
}
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Mesa (master): nvc0/ir: fix predicated PFETCH for real
Module: Mesa Branch: master Commit: 33f0d1138d6ffa4596d3deda68fa5ba9a3d7cf86 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=33f0d1138d6ffa4596d3deda68fa5ba9a3d7cf86 Author: Ilia Mirkin Date: Thu Apr 30 02:01:22 2015 -0400 nvc0/ir: fix predicated PFETCH for real Commit a9d08a250 accidentally didn't make use of the new src1 variable. Use it. Signed-off-by: Ilia Mirkin Cc: mesa-sta...@lists.freedesktop.org --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp |2 +- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp index a6e6c1f..6bb9620 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp @@ -1336,7 +1336,7 @@ CodeEmitterGK110::emitPFETCH(const Instruction *i) const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2) defId(i->def(0), 2); - srcId(i, 1, 10); + srcId(i, src1, 10); } void diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp index 4ad098e..d9aed34 100644 --- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp +++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_nvc0.cpp @@ -1498,7 +1498,7 @@ CodeEmitterNVC0::emitPFETCH(const Instruction *i) const int src1 = (i->predSrc == 1) ? 2 : 1; // if predSrc == 1, !srcExists(2) defId(i->def(0), 14); - srcId(i, 1, 20); + srcId(i, src1, 20); } void ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
