Mesa (master): mesa: update fbo state in glTexStorage
Module: Mesa
Branch: master
Commit: 7eda897bf05dc572dbe83f3a1075b773b0c65708
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7eda897bf05dc572dbe83f3a1075b773b0c65708
Author: Tapani Pälli
Date: Thu Aug 20 10:25:59 2015 +0300
mesa: update fbo state in glTexStorage
We have to re-validate FBOs rendering to the texture like is done
with TexImage and CopyTexImage.
Signed-off-by: Tapani Pälli
Reviewed-by: Anuj Phogat
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91673
Cc: "10.6"
---
src/mesa/main/texstorage.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/src/mesa/main/texstorage.c b/src/mesa/main/texstorage.c
index db2b63d..51f49b3 100644
--- a/src/mesa/main/texstorage.c
+++ b/src/mesa/main/texstorage.c
@@ -189,6 +189,20 @@ clear_texture_fields(struct gl_context *ctx,
}
+/**
+ * Update/re-validate framebuffer object.
+ */
+static void
+update_fbo_texture(struct gl_context *ctx, struct gl_texture_object *texObj)
+{
+ const unsigned numFaces = _mesa_num_tex_faces(texObj->Target);
+ for (int level = 0; level < ARRAY_SIZE(texObj->Image[0]); level++) {
+ for (unsigned face = 0; face < numFaces; face++)
+ _mesa_update_fbo_texture(ctx, texObj, face, level);
+ }
+}
+
+
GLboolean
_mesa_is_legal_tex_storage_format(struct gl_context *ctx, GLenum
internalformat)
{
@@ -446,6 +460,7 @@ _mesa_texture_storage(struct gl_context *ctx, GLuint dims,
_mesa_set_texture_view_state(ctx, texObj, target, levels);
+ update_fbo_texture(ctx, texObj);
}
}
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Mesa (master): clover: fix llvm 3.5 build error
Module: Mesa
Branch: master
Commit: df5cdec1329507d5ac52a6d3db49c2608b9226bc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=df5cdec1329507d5ac52a6d3db49c2608b9226bc
Author: Zoltan Gilian
Date: Wed Aug 19 11:56:08 2015 +0200
clover: fix llvm 3.5 build error
There is no MDOperand in llvm 3.5.
v2: Check if kernel metadata is present to avoid crash (EdB).
v3: Second attempt to avoid crash: switch off metadata query for llvm < 3.6.
Reviewed-by: Serge Martin (EdB)
Reviewed-by: Francisco Jerez
---
.../state_trackers/clover/llvm/invocation.cpp | 33 +---
1 file changed, 21 insertions(+), 12 deletions(-)
diff --git a/src/gallium/state_trackers/clover/llvm/invocation.cpp
b/src/gallium/state_trackers/clover/llvm/invocation.cpp
index 63c3f8e..7c23a27 100644
--- a/src/gallium/state_trackers/clover/llvm/invocation.cpp
+++ b/src/gallium/state_trackers/clover/llvm/invocation.cpp
@@ -346,6 +346,15 @@ namespace {
// Kernel metadata
+ struct kernel_arg_md {
+ llvm::StringRef type_name;
+ llvm::StringRef access_qual;
+ kernel_arg_md(llvm::StringRef type_name_, llvm::StringRef access_qual_):
+ type_name(type_name_), access_qual(access_qual_) {}
+ };
+
+#if HAVE_LLVM >= 0x0306
+
const llvm::MDNode *
get_kernel_metadata(const llvm::Function *kernel_func) {
auto mod = kernel_func->getParent();
@@ -356,12 +365,8 @@ namespace {
const llvm::MDNode *kernel_node = nullptr;
for (unsigned i = 0; i < kernels_node->getNumOperands(); ++i) {
-#if HAVE_LLVM >= 0x0306
auto func = llvm::mdconst::dyn_extract(
-#else
- auto func = llvm::dyn_cast(
-#endif
-
kernels_node->getOperand(i)->getOperand(0));
+ kernels_node->getOperand(i)->getOperand(0));
if (func == kernel_func) {
kernel_node = kernels_node->getOperand(i);
break;
@@ -387,13 +392,6 @@ namespace {
return node;
}
- struct kernel_arg_md {
- llvm::StringRef type_name;
- llvm::StringRef access_qual;
- kernel_arg_md(llvm::StringRef type_name_, llvm::StringRef access_qual_):
- type_name(type_name_), access_qual(access_qual_) {}
- };
-
std::vector
get_kernel_arg_md(const llvm::Function *kernel_func) {
auto num_args = kernel_func->getArgumentList().size();
@@ -415,6 +413,17 @@ namespace {
return res;
}
+#else
+
+ std::vector
+ get_kernel_arg_md(const llvm::Function *kernel_func) {
+ return std::vector(
+kernel_func->getArgumentList().size(),
+kernel_arg_md("", ""));
+ }
+
+#endif // HAVE_LLVM >= 0x0306
+
std::vector
get_kernel_args(const llvm::Module *mod, const std::string &kernel_name,
const clang::LangAS::Map &address_spaces) {
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Mesa (master): i965: allow image_size on float images
Module: Mesa Branch: master Commit: f142e64b2938ab3ebc42fd40436a1de74e3ed2e2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f142e64b2938ab3ebc42fd40436a1de74e3ed2e2 Author: Martin Peres Date: Fri Aug 21 16:25:14 2015 +0300 i965: allow image_size on float images This got missed because the piglit test only tested int images to avoid a combinatiorial explosion of format, targets, stages and sizes which takes more than 5 minutes to test on nvidia's driver. This patch also drops the IMAGE_FUNCTION_AVAIL_ATOMIC which is not applicable to the image_size codepath but was not hurting in any way. Signed-off-by: Martin Peres Reviewed-by: Francisco Jerez --- src/glsl/builtin_functions.cpp |3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/glsl/builtin_functions.cpp b/src/glsl/builtin_functions.cpp index 57bed86..1bc3de4 100644 --- a/src/glsl/builtin_functions.cpp +++ b/src/glsl/builtin_functions.cpp @@ -2739,7 +2739,8 @@ builtin_builder::add_image_functions(bool glsl) add_image_function(glsl ? "imageSize" : "__intrinsic_image_size", "__intrinsic_image_size", - &builtin_builder::_image_size_prototype, 1, atom_flags); + &builtin_builder::_image_size_prototype, 1, + flags | IMAGE_FUNCTION_SUPPORTS_FLOAT_DATA_TYPE); } ir_variable * ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): st/mesa: pass through 4th opcode argument in bitmap/ pixel visitors
Module: Mesa
Branch: master
Commit: 3525aa1dc9c27fb2394a37788a29c272b3a81d1b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3525aa1dc9c27fb2394a37788a29c272b3a81d1b
Author: Ilia Mirkin
Date: Thu Aug 20 20:06:50 2015 -0400
st/mesa: pass through 4th opcode argument in bitmap/pixel visitors
Signed-off-by: Ilia Mirkin
Cc: "10.6"
Reviewed-by: Marek Olšák
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index f641567..cba9881 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -4402,12 +4402,12 @@ get_pixel_transfer_visitor(struct st_fragment_program
*fp,
* new visitor. */
foreach_in_list(glsl_to_tgsi_instruction, inst, &original->instructions) {
glsl_to_tgsi_instruction *newinst;
- st_src_reg src_regs[3];
+ st_src_reg src_regs[4];
if (inst->dst[0].file == PROGRAM_OUTPUT)
prog->OutputsWritten |= BITFIELD64_BIT(inst->dst[0].index);
- for (int i = 0; i < 3; i++) {
+ for (int i = 0; i < 4; i++) {
src_regs[i] = inst->src[i];
if (src_regs[i].file == PROGRAM_INPUT &&
src_regs[i].index == VARYING_SLOT_COL0) {
@@ -4418,7 +4418,7 @@ get_pixel_transfer_visitor(struct st_fragment_program *fp,
prog->InputsRead |= BITFIELD64_BIT(src_regs[i].index);
}
- newinst = v->emit_asm(NULL, inst->op, inst->dst[0], src_regs[0],
src_regs[1], src_regs[2]);
+ newinst = v->emit_asm(NULL, inst->op, inst->dst[0], src_regs[0],
src_regs[1], src_regs[2], src_regs[3]);
newinst->tex_target = inst->tex_target;
newinst->sampler_array_size = inst->sampler_array_size;
}
@@ -4487,18 +4487,18 @@ get_bitmap_visitor(struct st_fragment_program *fp,
* new visitor. */
foreach_in_list(glsl_to_tgsi_instruction, inst, &original->instructions) {
glsl_to_tgsi_instruction *newinst;
- st_src_reg src_regs[3];
+ st_src_reg src_regs[4];
if (inst->dst[0].file == PROGRAM_OUTPUT)
prog->OutputsWritten |= BITFIELD64_BIT(inst->dst[0].index);
- for (int i = 0; i < 3; i++) {
+ for (int i = 0; i < 4; i++) {
src_regs[i] = inst->src[i];
if (src_regs[i].file == PROGRAM_INPUT)
prog->InputsRead |= BITFIELD64_BIT(src_regs[i].index);
}
- newinst = v->emit_asm(NULL, inst->op, inst->dst[0], src_regs[0],
src_regs[1], src_regs[2]);
+ newinst = v->emit_asm(NULL, inst->op, inst->dst[0], src_regs[0],
src_regs[1], src_regs[2], src_regs[3]);
newinst->tex_target = inst->tex_target;
newinst->sampler_array_size = inst->sampler_array_size;
}
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Mesa (master): st/mesa: fix assignments with 4-operand arguments (i.e. BFI )
Module: Mesa
Branch: master
Commit: 681efdf7a18b73ce06989cb2d3299e3feabdb5f5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=681efdf7a18b73ce06989cb2d3299e3feabdb5f5
Author: Ilia Mirkin
Date: Thu Aug 20 19:59:04 2015 -0400
st/mesa: fix assignments with 4-operand arguments (i.e. BFI)
Signed-off-by: Ilia Mirkin
Cc: "10.6"
Reviewed-by: Marek Olšák
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 6f00727..f641567 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -2816,7 +2816,7 @@ glsl_to_tgsi_visitor::visit(ir_assignment *ir)
*/
glsl_to_tgsi_instruction *inst, *new_inst;
inst = (glsl_to_tgsi_instruction *)this->instructions.get_tail();
- new_inst = emit_asm(ir, inst->op, l, inst->src[0], inst->src[1],
inst->src[2]);
+ new_inst = emit_asm(ir, inst->op, l, inst->src[0], inst->src[1],
inst->src[2], inst->src[3]);
new_inst->saturate = inst->saturate;
inst->dead_mask = inst->dst[0].writemask;
} else {
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Mesa (master): relnote updates
Module: Mesa Branch: master Commit: 1fcc423064b3d31677657d59a803aaa99f1edb9e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1fcc423064b3d31677657d59a803aaa99f1edb9e Author: Rob Clark Date: Mon Aug 10 17:27:19 2015 -0400 relnote updates Signed-off-by: Rob Clark --- docs/relnotes/11.0.0.html |7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/docs/relnotes/11.0.0.html b/docs/relnotes/11.0.0.html index 7e4b09d..125d21b 100644 --- a/docs/relnotes/11.0.0.html +++ b/docs/relnotes/11.0.0.html @@ -46,9 +46,12 @@ Note: some of the new features are only available with certain drivers. New hardware support for AMD GCN 1.2 GPUs: Tonga, Iceland, Carrizo, Fiji OpenGL 4.1 on radeonsi, nvc0 +OpenGL ES 3.1 on freedreno (a3xx, a4xx) GL_AMD_vertex_shader_viewport_index on radeonsi GL_ARB_conditional_render_inverted on r600, radeonsi +GL_ARB_depth_buffer_float on a4xx GL_ARB_derivative_control on radeonsi +GL_ARB_draw_buffers, GL_ARB_draw_buffers_blend on a4xx GL_ARB_fragment_layer_viewport on radeonsi GL_ARB_framebuffer_no_attachments on i965 GL_ARB_get_texture_sub_image for all drivers @@ -60,10 +63,11 @@ Note: some of the new features are only available with certain drivers. GL_ARB_shader_stencil_export on llvmpipe GL_ARB_shader_subroutine on core profile all drivers GL_ARB_tessellation_shader on nvc0, radeonsi +GL_ARB_transform_feedback2, GL_ARB_transform_feedback_instanced, GL_EXT_transform_feedback on a3xx, a4xx GL_ARB_vertex_attrib_64bit on llvmpipe, radeonsi GL_ARB_viewport_array on radeonsi GL_EXT_depth_bounds_test on radeonsi, nv30, nv50, nvc0 -GL_EXT_texture_compression_s3tc on freedreno +GL_EXT_texture_compression_s3tc on freedreno (a3xx) GL_NV_read_depth (GLES) on all drivers GL_NV_read_depth_stencil (GLES) on all drivers GL_NV_read_stencil (GLES) on all drivers @@ -71,6 +75,7 @@ Note: some of the new features are only available with certain drivers. GL_OES_texture_half_float on all r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe GL_OES_texture_float_linear on all r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe GL_OES_texture_half_float_linear on all r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe +GL_EXT_draw_buffers2 on a4xx GLX_ARB_create_context_robustness on r600, radeonsi EGL_EXT_create_context_robustness on r600, radeonsi EGL_KHR_gl_colorspace on r600, radeonsi, nv50, nvc0 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): relnote updates
Module: Mesa Branch: master Commit: 3b4d03d44044f683d9b194c069cd3c1e6acb105f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b4d03d44044f683d9b194c069cd3c1e6acb105f Author: Rob Clark Date: Mon Aug 10 17:27:19 2015 -0400 relnote updates Signed-off-by: Rob Clark --- docs/relnotes/11.0.0.html |7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/docs/relnotes/11.0.0.html b/docs/relnotes/11.0.0.html index 7e4b09d..537b883 100644 --- a/docs/relnotes/11.0.0.html +++ b/docs/relnotes/11.0.0.html @@ -46,9 +46,12 @@ Note: some of the new features are only available with certain drivers. New hardware support for AMD GCN 1.2 GPUs: Tonga, Iceland, Carrizo, Fiji OpenGL 4.1 on radeonsi, nvc0 +OpenGL ES 3.0 on freedreno (a3xx, a4xx) GL_AMD_vertex_shader_viewport_index on radeonsi GL_ARB_conditional_render_inverted on r600, radeonsi +GL_ARB_depth_buffer_float on a4xx GL_ARB_derivative_control on radeonsi +GL_ARB_draw_buffers, GL_ARB_draw_buffers_blend on a4xx GL_ARB_fragment_layer_viewport on radeonsi GL_ARB_framebuffer_no_attachments on i965 GL_ARB_get_texture_sub_image for all drivers @@ -60,10 +63,11 @@ Note: some of the new features are only available with certain drivers. GL_ARB_shader_stencil_export on llvmpipe GL_ARB_shader_subroutine on core profile all drivers GL_ARB_tessellation_shader on nvc0, radeonsi +GL_ARB_transform_feedback2, GL_ARB_transform_feedback_instanced, GL_EXT_transform_feedback on a3xx, a4xx GL_ARB_vertex_attrib_64bit on llvmpipe, radeonsi GL_ARB_viewport_array on radeonsi GL_EXT_depth_bounds_test on radeonsi, nv30, nv50, nvc0 -GL_EXT_texture_compression_s3tc on freedreno +GL_EXT_texture_compression_s3tc on freedreno (a3xx) GL_NV_read_depth (GLES) on all drivers GL_NV_read_depth_stencil (GLES) on all drivers GL_NV_read_stencil (GLES) on all drivers @@ -71,6 +75,7 @@ Note: some of the new features are only available with certain drivers. GL_OES_texture_half_float on all r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe GL_OES_texture_float_linear on all r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe GL_OES_texture_half_float_linear on all r300, r600, radeonsi, nv30, nv50, nvc0, softpipe, llvmpipe +GL_EXT_draw_buffers2 on a4xx GLX_ARB_create_context_robustness on r600, radeonsi EGL_EXT_create_context_robustness on r600, radeonsi EGL_KHR_gl_colorspace on r600, radeonsi, nv50, nvc0 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl: fix error message when validating tcs output decls
Module: Mesa Branch: master Commit: 365d631eb220e7d546a726d6f38f76e2e3746d65 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=365d631eb220e7d546a726d6f38f76e2e3746d65 Author: Ilia Mirkin Date: Fri Aug 21 15:08:15 2015 -0400 glsl: fix error message when validating tcs output decls Signed-off-by: Ilia Mirkin Reviewed-by: Marek Olšák --- src/glsl/ast_to_hir.cpp |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp index c7ce409..517841c 100644 --- a/src/glsl/ast_to_hir.cpp +++ b/src/glsl/ast_to_hir.cpp @@ -3317,7 +3317,7 @@ handle_tess_ctrl_shader_output_decl(struct _mesa_glsl_parse_state *state, validate_layout_qualifier_vertex_count(state, loc, var, num_vertices, &state->tcs_output_size, - "geometry shader input"); + "tessellation control shader output"); } /** ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): 72 new commits
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=20746c2e7d8d065445bbb30f0d1383c30459a784 Author: Krzysztof Sobiecki Date: Thu Aug 20 23:19:30 2015 +0200 st/nine: Always use user constant buffers We had several reports of users hitting bugs with the other path to upload constants, and switching to the user constant buffer path solves the bugs. User constant buffers are expected to be slower for Nvidia cards, so ideally this patch should be reverted when the path is fixed. Reviewed-by: Axel Davy Signed-off-by: Krzysztof Sobiecki URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f57e9c77e388e1c5373265f4bc15434e63477757 Author: Axel Davy Date: Sun Aug 16 13:11:50 2015 +0200 st/nine: Silent warning in nine_ff release build was complaining Signed-off-by: Axel Davy URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3cc205bbeb19d417b17be0f6200cb5cda9adca8a Author: Axel Davy Date: Sun Aug 16 13:11:27 2015 +0200 st/nine: Silent warning in sm1_declusage_to_tgsi release build was complaining Signed-off-by: Axel Davy URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d48cab9fa6b75db054e3a53819b465611923e9bc Author: Axel Davy Date: Sun Aug 16 12:58:41 2015 +0200 st/nine: Silent warning in NineCubeTexture9_ctor The compiler was complaining the value may be uninitialised when it is used (which is wrong). Initialize to NULL to silent the warning. URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f02d5e814904d7a5c041d6869751731712e8195 Author: Axel Davy Date: Sun Aug 16 12:57:40 2015 +0200 st/nine: Silent warning in update_vertex_buffer There was an unused variable URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=719f124620d3c9b4d6ce14db3dbfc7af05626e5b Author: Axel Davy Date: Sun Aug 9 19:06:01 2015 +0200 st/nine: Catch setting the same shader This is quite rare that an app does set again the same shaders, but it isn't an expensive check either. Signed-off-by: Axel Davy URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=eba3c390a3c6221781ca4d9c344c6f448e177b6c Author: Axel Davy Date: Sun Aug 9 19:02:02 2015 +0200 st/nine: Avoid Constant upload when there is no change It is very common for d3d9 apps to set again the constants they need before every draw call, even if nothing changed. Since we are mostly gpu bound, it is better to check for change, and upload constants again (and thus use gpu bandwith) only if the constants changed. Signed-off-by: Axel Davy URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a747094ed0ab32541936dd18931f382901affe6 Author: Axel Davy Date: Sat Jul 25 17:54:26 2015 +0200 st/nine: Fix the number of texture stages The number of texture stages is 8. 'tex_stage' array was too big, and thus the checks with 'Elements(state->ff.tex_stage)' were passing, causing some invalid API calls to pass, and crash because of out of bounds write since bumpmap_vars was just the correct size. Signed-off-by: Axel Davy URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f15ff98e2c53f6ce62443b24e3a9cf79c60ddff7 Author: Axel Davy Date: Thu May 14 19:24:57 2015 +0200 st/nine: Use CSO cache for sampler views The CSO cache unbinds views that are not needed anymore, which we don't do. It checks for change before committing the views. Signed-off-by: Axel Davy URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=98f786b270b3e55a1e8a7bdc8182e436702748a2 Author: Axel Davy Date: Thu May 14 19:10:41 2015 +0200 st/nine: Calculate dummy sampler state only once Signed-off-by: Axel Davy URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5effeb8eaf16e39a2f561b4b277f3810a69fc88 Author: Axel Davy Date: Thu May 14 15:42:50 2015 +0200 st/nine: Better check shader constant limits Signed-off-by: Axel Davy URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bae2c7c15444b02a4820e3182c345545bd348561 Author: Axel Davy Date: Thu Aug 13 19:24:02 2015 +0200 st/nine: Remove NINED3DRS_ZBIASSCALE It wasn't giving the expected result. This fixes some object being transparents in games like FEAR. Signed-off-by: Axel Davy URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6379a28aa75a38676120891b355c434bec4125e1 Author: Axel Davy Date: Sun May 17 00:22:33 2015 +0200 st/nine: Implement special DOTPRODUCT3 behaviour Taken from wine tests Signed-off-by: Axel Davy URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=791b794a849f4576e59bda29680bdd49ed0429a9 Author: Axel Davy Date: Sat May 16 12:14:54 2015 +0200 st/nine: Implement ff vertex data passthrough Fixes Wine tests Signed-off-by: Axel Davy URL
Mesa (master): vc4: Use the SSA defs list for figuring out eligible MOVs for copy prop.
Module: Mesa
Branch: master
Commit: 2002438c91981b22991ae70fefc5d492dda72835
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2002438c91981b22991ae70fefc5d492dda72835
Author: Eric Anholt
Date: Fri Aug 21 09:22:32 2015 -0700
vc4: Use the SSA defs list for figuring out eligible MOVs for copy prop.
I thought I'd converted this over previously. It was copy propagating
MOVs badly with the new destination packing flags.
---
src/gallium/drivers/vc4/vc4_opt_copy_propagation.c | 22 +---
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/vc4/vc4_opt_copy_propagation.c
b/src/gallium/drivers/vc4/vc4_opt_copy_propagation.c
index a755de9..fd2539a 100644
--- a/src/gallium/drivers/vc4/vc4_opt_copy_propagation.c
+++ b/src/gallium/drivers/vc4/vc4_opt_copy_propagation.c
@@ -39,21 +39,27 @@ qir_opt_copy_propagation(struct vc4_compile *c)
{
bool progress = false;
bool debug = false;
-struct qreg *movs = calloc(c->num_temps, sizeof(struct qreg));
list_for_each_entry(struct qinst, inst, &c->instructions, link) {
for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
int index = inst->src[i].index;
if (inst->src[i].file == QFILE_TEMP &&
-(movs[index].file == QFILE_TEMP ||
- movs[index].file == QFILE_UNIF)) {
+c->defs[index] &&
+c->defs[index]->op == QOP_MOV &&
+(c->defs[index]->src[0].file == QFILE_TEMP ||
+ c->defs[index]->src[0].file == QFILE_UNIF)) {
+/* If it has a pack, it shouldn't be an SSA
+ * def.
+ */
+assert(!c->defs[index]->dst.pack);
+
if (debug) {
fprintf(stderr, "Copy propagate: ");
qir_dump_inst(c, inst);
fprintf(stderr, "\n");
}
-inst->src[i] = movs[index];
+inst->src[i] = c->defs[index]->src[0];
if (debug) {
fprintf(stderr, "to: ");
@@ -64,14 +70,6 @@ qir_opt_copy_propagation(struct vc4_compile *c)
progress = true;
}
}
-
-if (inst->op == QOP_MOV &&
-inst->dst.file == QFILE_TEMP &&
-inst->src[0].file != QFILE_VPM) {
-movs[inst->dst.index] = inst->src[0];
-}
}
-
-free(movs);
return progress;
}
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Mesa (master): vc4: Reuse QPU dumping for packing bits in QIR.
Module: Mesa
Branch: master
Commit: 7e0b868cf31003ada12063398fb91485ed8043dd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e0b868cf31003ada12063398fb91485ed8043dd
Author: Eric Anholt
Date: Fri Aug 21 00:04:36 2015 -0700
vc4: Reuse QPU dumping for packing bits in QIR.
---
src/gallium/drivers/vc4/vc4_qir.c| 25 +
src/gallium/drivers/vc4/vc4_qpu.h|7 +++
src/gallium/drivers/vc4/vc4_qpu_disasm.c | 16 ++--
3 files changed, 26 insertions(+), 22 deletions(-)
diff --git a/src/gallium/drivers/vc4/vc4_qir.c
b/src/gallium/drivers/vc4/vc4_qir.c
index 4e0dc38..e5efb7cb 100644
--- a/src/gallium/drivers/vc4/vc4_qir.c
+++ b/src/gallium/drivers/vc4/vc4_qir.c
@@ -287,26 +287,11 @@ qir_dump_inst(struct vc4_compile *c, struct qinst *inst)
qir_print_reg(c, inst->dst, true);
if (inst->dst.pack) {
-if (qir_is_mul(inst)) {
-switch (inst->dst.pack) {
-case QPU_PACK_MUL_:
-fprintf(stderr, ".");
-break;
-case QPU_PACK_MUL_8A:
-fprintf(stderr, ".8a");
-break;
-case QPU_PACK_MUL_8B:
-fprintf(stderr, ".8b");
-break;
-case QPU_PACK_MUL_8C:
-fprintf(stderr, ".8c");
-break;
-case QPU_PACK_MUL_8D:
-fprintf(stderr, ".8d");
-break;
-}
-} else {
-unreachable("packs only set up for MULs so far.\n");
+if (inst->dst.pack) {
+if (qir_is_mul(inst))
+vc4_qpu_disasm_pack_mul(stderr,
inst->dst.pack);
+else
+vc4_qpu_disasm_pack_a(stderr, inst->dst.pack);
}
}
for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
diff --git a/src/gallium/drivers/vc4/vc4_qpu.h
b/src/gallium/drivers/vc4/vc4_qpu.h
index fbb90ba..0719d28 100644
--- a/src/gallium/drivers/vc4/vc4_qpu.h
+++ b/src/gallium/drivers/vc4/vc4_qpu.h
@@ -24,6 +24,7 @@
#ifndef VC4_QPU_H
#define VC4_QPU_H
+#include
#include
#include "util/u_math.h"
@@ -206,6 +207,12 @@ void
vc4_qpu_disasm(const uint64_t *instructions, int num_instructions);
void
+vc4_qpu_disasm_pack_mul(FILE *out, uint32_t pack);
+
+void
+vc4_qpu_disasm_pack_a(FILE *out, uint32_t pack);
+
+void
vc4_qpu_validate(uint64_t *insts, uint32_t num_inst);
#endif /* VC4_QPU_H */
diff --git a/src/gallium/drivers/vc4/vc4_qpu_disasm.c
b/src/gallium/drivers/vc4/vc4_qpu_disasm.c
index 00aeb30..0879787 100644
--- a/src/gallium/drivers/vc4/vc4_qpu_disasm.c
+++ b/src/gallium/drivers/vc4/vc4_qpu_disasm.c
@@ -245,6 +245,18 @@ get_special_write_desc(int reg, bool is_a)
return special_write[reg];
}
+void
+vc4_qpu_disasm_pack_mul(FILE *out, uint32_t pack)
+{
+fprintf(out, ".%s", DESC(qpu_pack_mul, pack));
+}
+
+void
+vc4_qpu_disasm_pack_a(FILE *out, uint32_t pack)
+{
+fprintf(out, "%s", DESC(qpu_pack_a, pack));
+}
+
static void
print_alu_dst(uint64_t inst, bool is_mul)
{
@@ -263,9 +275,9 @@ print_alu_dst(uint64_t inst, bool is_mul)
fprintf(stderr, "%s%d?", file, waddr);
if (is_mul && (inst & QPU_PM)) {
-fprintf(stderr, ".%s", DESC(qpu_pack_mul, pack));
+vc4_qpu_disasm_pack_mul(stderr, pack);
} else if (is_a && !(inst & QPU_PM)) {
-fprintf(stderr, "%s", DESC(qpu_pack_a, pack));
+vc4_qpu_disasm_pack_a(stderr, pack);
}
}
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Mesa (master): vc4: Make _dest variants of qir ALU helpers to provide an explicit dest.
Module: Mesa
Branch: master
Commit: 4ae137534a8718db4611782dbfec773504b6e3be
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4ae137534a8718db4611782dbfec773504b6e3be
Author: Eric Anholt
Date: Tue Aug 18 20:26:05 2015 -0700
vc4: Make _dest variants of qir ALU helpers to provide an explicit dest.
---
src/gallium/drivers/vc4/vc4_qir.c |2 +-
src/gallium/drivers/vc4/vc4_qir.h | 22 +++---
2 files changed, 20 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/vc4/vc4_qir.c
b/src/gallium/drivers/vc4/vc4_qir.c
index 92669a8..4e0dc38 100644
--- a/src/gallium/drivers/vc4/vc4_qir.c
+++ b/src/gallium/drivers/vc4/vc4_qir.c
@@ -384,7 +384,7 @@ qir_emit(struct vc4_compile *c, struct qinst *inst)
if (inst->dst.file == QFILE_TEMP)
c->defs[inst->dst.index] = inst;
-list_addtail(&inst->link, &c->instructions);
+qir_emit_nodef(c, inst);
}
bool
diff --git a/src/gallium/drivers/vc4/vc4_qir.h
b/src/gallium/drivers/vc4/vc4_qir.h
index 65d493d..cbeff43 100644
--- a/src/gallium/drivers/vc4/vc4_qir.h
+++ b/src/gallium/drivers/vc4/vc4_qir.h
@@ -446,7 +446,13 @@ struct qreg qir_uniform(struct vc4_compile *c,
enum quniform_contents contents,
uint32_t data);
void qir_reorder_uniforms(struct vc4_compile *c);
+
void qir_emit(struct vc4_compile *c, struct qinst *inst);
+static inline void qir_emit_nodef(struct vc4_compile *c, struct qinst *inst)
+{
+list_addtail(&inst->link, &c->instructions);
+}
+
struct qreg qir_get_temp(struct vc4_compile *c);
int qir_get_op_nsrc(enum qop qop);
bool qir_reg_equals(struct qreg a, struct qreg b);
@@ -512,6 +518,12 @@ qir_##name(struct vc4_compile *c, struct qreg a)
\
struct qreg t = qir_get_temp(c); \
qir_emit(c, qir_inst(QOP_##name, t, a, c->undef)); \
return t;\
+}\
+static inline void \
+qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
+ struct qreg a) \
+{\
+qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, c->undef)); \
}
#define QIR_ALU2(name) \
@@ -521,6 +533,12 @@ qir_##name(struct vc4_compile *c, struct qreg a, struct
qreg b) \
struct qreg t = qir_get_temp(c); \
qir_emit(c, qir_inst(QOP_##name, t, a, b)); \
return t;\
+}\
+static inline void \
+qir_##name##_dest(struct vc4_compile *c, struct qreg dest, \
+ struct qreg a, struct qreg b) \
+{\
+qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, b)); \
}
#define QIR_NODST_1(name) \
@@ -541,9 +559,7 @@ qir_##name(struct vc4_compile *c, struct qreg a, struct
qreg b) \
static inline struct qreg\
qir_##name(struct vc4_compile *c, struct qreg dest, struct qreg a) \
{\
-qir_emit(c, qir_inst(QOP_##name, dest, a, c->undef));\
-if (dest.file == QFILE_TEMP) \
-c->defs[dest.index] = NULL; \
+qir_emit_nodef(c, qir_inst(QOP_##name, dest, a, c->undef)); \
return dest; \
}
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Mesa (master): vc4: Fold the 16-bit integer pack into the instructions generating it.
Module: Mesa
Branch: master
Commit: 89b1b33f44bc6ce71109ac8668529c30b6d6d910
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=89b1b33f44bc6ce71109ac8668529c30b6d6d910
Author: Eric Anholt
Date: Fri Aug 21 00:08:13 2015 -0700
vc4: Fold the 16-bit integer pack into the instructions generating it.
total instructions in shared programs: 97580 -> 96798 (-0.80%)
instructions in affected programs: 52826 -> 52044 (-1.48%)
---
src/gallium/drivers/vc4/vc4_program.c | 19 ++-
src/gallium/drivers/vc4/vc4_qir.c |2 --
src/gallium/drivers/vc4/vc4_qir.h |4
src/gallium/drivers/vc4/vc4_qpu_emit.c | 14 +-
src/gallium/drivers/vc4/vc4_register_allocate.c | 13 +++--
5 files changed, 22 insertions(+), 30 deletions(-)
diff --git a/src/gallium/drivers/vc4/vc4_program.c
b/src/gallium/drivers/vc4/vc4_program.c
index 6bf4c9e..e002983 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -1186,22 +1186,23 @@ emit_frag_end(struct vc4_compile *c)
static void
emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
{
-struct qreg xyi[2];
+struct qreg packed = qir_get_temp(c);
for (int i = 0; i < 2; i++) {
struct qreg scale =
qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
-xyi[i] = qir_FTOI(c, qir_FMUL(c,
- qir_FMUL(c,
-
c->outputs[c->output_position_index + i],
- scale),
- rcp_w));
+struct qreg packed_chan = packed;
+packed_chan.pack = QPU_PACK_A_16A + i;
+
+qir_FTOI_dest(c, packed_chan,
+ qir_FMUL(c,
+ qir_FMUL(c,
+
c->outputs[c->output_position_index + i],
+scale),
+ rcp_w));
}
-struct qreg packed = qir_get_temp(c);
-qir_PACK_16A_I(c, packed, xyi[0]);
-qir_PACK_16B_I(c, packed, xyi[1]);
qir_VPM_WRITE(c, packed);
}
diff --git a/src/gallium/drivers/vc4/vc4_qir.c
b/src/gallium/drivers/vc4/vc4_qir.c
index e5efb7cb..9d93071 100644
--- a/src/gallium/drivers/vc4/vc4_qir.c
+++ b/src/gallium/drivers/vc4/vc4_qir.c
@@ -76,8 +76,6 @@ static const struct qir_op_info qir_op_info[] = {
[QOP_PACK_8B_F] = { "pack_8b_f", 1, 1 },
[QOP_PACK_8C_F] = { "pack_8c_f", 1, 1 },
[QOP_PACK_8D_F] = { "pack_8d_f", 1, 1 },
-[QOP_PACK_16A_I] = { "pack_16a_i", 1, 1 },
-[QOP_PACK_16B_I] = { "pack_16b_i", 1, 1 },
[QOP_TLB_DISCARD_SETUP] = { "discard", 0, 1, true },
[QOP_TLB_STENCIL_SETUP] = { "tlb_stencil_setup", 0, 1, true },
[QOP_TLB_Z_WRITE] = { "tlb_z", 0, 1, true },
diff --git a/src/gallium/drivers/vc4/vc4_qir.h
b/src/gallium/drivers/vc4/vc4_qir.h
index cbeff43..a2b21fa 100644
--- a/src/gallium/drivers/vc4/vc4_qir.h
+++ b/src/gallium/drivers/vc4/vc4_qir.h
@@ -110,8 +110,6 @@ enum qop {
QOP_PACK_8B_F,
QOP_PACK_8C_F,
QOP_PACK_8D_F,
-QOP_PACK_16A_I,
-QOP_PACK_16B_I,
QOP_TLB_DISCARD_SETUP,
QOP_TLB_STENCIL_SETUP,
QOP_TLB_Z_WRITE,
@@ -604,8 +602,6 @@ QIR_PACK(PACK_8A_F)
QIR_PACK(PACK_8B_F)
QIR_PACK(PACK_8C_F)
QIR_PACK(PACK_8D_F)
-QIR_PACK(PACK_16A_I)
-QIR_PACK(PACK_16B_I)
QIR_ALU1(VARY_ADD_C)
QIR_NODST_2(TEX_S)
QIR_NODST_2(TEX_T)
diff --git a/src/gallium/drivers/vc4/vc4_qpu_emit.c
b/src/gallium/drivers/vc4/vc4_qpu_emit.c
index bf614a2..adf3a8b 100644
--- a/src/gallium/drivers/vc4/vc4_qpu_emit.c
+++ b/src/gallium/drivers/vc4/vc4_qpu_emit.c
@@ -402,15 +402,6 @@ vc4_generate_code(struct vc4_context *vc4, struct
vc4_compile *c)
queue(c, qpu_a_FADD(dst, src[0], qpu_r5()));
break;
-case QOP_PACK_16A_I:
-case QOP_PACK_16B_I:
-queue(c,
- qpu_a_MOV(dst, src[0]) |
- QPU_SET_FIELD(qinst->op == QOP_PACK_16A_I ?
-QPU_PACK_A_16A : QPU_PACK_A_16B,
-QPU_PACK));
-break;
-
case QOP_TEX_S:
case QOP_TEX_T:
case QOP_TEX_R:
@@ -516,6 +507,11 @@ vc4_generate_code(struct vc4_context *vc4, struct
vc4_compile *c)
queue(c, qpu_a_alu2(translate[qinst->op].op,
dst,
src[0], src[1]));
+if (qinst->dst.pack)
Mesa (master): vc4: Actually allow math results to allocate into r4.
Module: Mesa
Branch: master
Commit: eb2776504ae32feaf41a5bad9f09f154045e96a3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb2776504ae32feaf41a5bad9f09f154045e96a3
Author: Eric Anholt
Date: Fri Aug 21 10:57:24 2015 -0700
vc4: Actually allow math results to allocate into r4.
I switched us to tracking whether the results *could* go to r4, but then
didn't make a separate register class for the class bits that included r4.
Switch the "any" class to actually be "any", and name the "any but r4"
class more appropriately.
total instructions in shared programs: 96798 -> 94680 (-2.19%)
instructions in affected programs: 62736 -> 60618 (-3.38%)
---
src/gallium/drivers/vc4/vc4_context.h |1 +
src/gallium/drivers/vc4/vc4_register_allocate.c |7 ++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/vc4/vc4_context.h
b/src/gallium/drivers/vc4/vc4_context.h
index 654c46f..3a63af8 100644
--- a/src/gallium/drivers/vc4/vc4_context.h
+++ b/src/gallium/drivers/vc4/vc4_context.h
@@ -270,6 +270,7 @@ struct vc4_context {
struct ra_regs *regs;
unsigned int reg_class_any;
+unsigned int reg_class_a_or_b_or_acc;
unsigned int reg_class_r4_or_a;
unsigned int reg_class_a;
diff --git a/src/gallium/drivers/vc4/vc4_register_allocate.c
b/src/gallium/drivers/vc4/vc4_register_allocate.c
index 2ea8850..3ced50f 100644
--- a/src/gallium/drivers/vc4/vc4_register_allocate.c
+++ b/src/gallium/drivers/vc4/vc4_register_allocate.c
@@ -116,6 +116,7 @@ vc4_alloc_reg_set(struct vc4_context *vc4)
vc4->regs = ra_alloc_reg_set(vc4, ARRAY_SIZE(vc4_regs), true);
vc4->reg_class_any = ra_alloc_reg_class(vc4->regs);
+vc4->reg_class_a_or_b_or_acc = ra_alloc_reg_class(vc4->regs);
vc4->reg_class_r4_or_a = ra_alloc_reg_class(vc4->regs);
vc4->reg_class_a = ra_alloc_reg_class(vc4->regs);
for (uint32_t i = 0; i < ARRAY_SIZE(vc4_regs); i++) {
@@ -130,10 +131,12 @@ vc4_alloc_reg_set(struct vc4_context *vc4)
*/
if (vc4_regs[i].mux == QPU_MUX_R4) {
ra_class_add_reg(vc4->regs, vc4->reg_class_r4_or_a, i);
+ra_class_add_reg(vc4->regs, vc4->reg_class_any, i);
continue;
}
ra_class_add_reg(vc4->regs, vc4->reg_class_any, i);
+ra_class_add_reg(vc4->regs, vc4->reg_class_a_or_b_or_acc, i);
}
for (uint32_t i = AB_INDEX; i < AB_INDEX + 64; i += 2) {
@@ -304,9 +307,11 @@ vc4_register_allocate(struct vc4_context *vc4, struct
vc4_compile *c)
switch (class_bits[i]) {
case CLASS_BIT_A | CLASS_BIT_B_OR_ACC | CLASS_BIT_R4:
-case CLASS_BIT_A | CLASS_BIT_B_OR_ACC:
ra_set_node_class(g, node, vc4->reg_class_any);
break;
+case CLASS_BIT_A | CLASS_BIT_B_OR_ACC:
+ra_set_node_class(g, node,
vc4->reg_class_a_or_b_or_acc);
+break;
case CLASS_BIT_A | CLASS_BIT_R4:
ra_set_node_class(g, node, vc4->reg_class_r4_or_a);
break;
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