Mesa (master): winsys/amdgpu: Process RADEON_FLAG_* independently from RADEON_DOMAIN_*

2016-01-28 Thread Michel Dänzer 
Module: Mesa
Branch: master
Commit: 30fcf241e13f82b3b9e3099632358b34cd35bff2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=30fcf241e13f82b3b9e3099632358b34cd35bff2

Author: Michel Dänzer 
Date:   Tue Jan 26 16:38:55 2016 +0900

winsys/amdgpu: Process RADEON_FLAG_* independently from RADEON_DOMAIN_*

In particular, AMDGPU_GEM_CREATE_CPU_GTT_USWC can affect even BOs created
in VRAM if they get evicted to GTT. In general there's no need to
restrict any of the flags to any particular domains.

Reviewed-by: Edward O'Callaghan 
Reviewed-by: Christian König 
Reviewed-by: Marek Olšák 
Reviewed-by: Alex Deucher 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 19 +--
 1 file changed, 9 insertions(+), 10 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 1e997d9..59a801b 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -288,18 +288,17 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct 
amdgpu_winsys *ws,
request.alloc_size = size;
request.phys_alignment = alignment;
 
-   if (initial_domain & RADEON_DOMAIN_VRAM) {
+   if (initial_domain & RADEON_DOMAIN_VRAM)
   request.preferred_heap |= AMDGPU_GEM_DOMAIN_VRAM;
-  if (flags & RADEON_FLAG_CPU_ACCESS)
- request.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
-  if (flags & RADEON_FLAG_NO_CPU_ACCESS)
- request.flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
-   }
-   if (initial_domain & RADEON_DOMAIN_GTT) {
+   if (initial_domain & RADEON_DOMAIN_GTT)
   request.preferred_heap |= AMDGPU_GEM_DOMAIN_GTT;
-  if (flags & RADEON_FLAG_GTT_WC)
- request.flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
-   }
+
+   if (flags & RADEON_FLAG_CPU_ACCESS)
+  request.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+   if (flags & RADEON_FLAG_NO_CPU_ACCESS)
+  request.flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
+   if (flags & RADEON_FLAG_GTT_WC)
+  request.flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 
r = amdgpu_bo_alloc(ws->dev, &request, &buf_handle);
if (r) {

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Mesa (master): winsys/amdgpu: Handle RADEON_FLAG_NO_CPU_ACCESS

2016-01-28 Thread Michel Dänzer 
Module: Mesa
Branch: master
Commit: 62f837e2ea7b854215efb2e110b176dad61c2af0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=62f837e2ea7b854215efb2e110b176dad61c2af0

Author: Michel Dänzer 
Date:   Tue Jan 26 16:15:59 2016 +0900

winsys/amdgpu: Handle RADEON_FLAG_NO_CPU_ACCESS

Failing to do this was resulting in the kernel driver unnecessarily
leaving open the possibility of CPU access to tiled BOs.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93862

(This change shouldn't be backported to stable branches, because
released versions of xf86-video-amdgpu unnecessarily try to map the
front buffer)

Reviewed-by: Edward O'Callaghan 
Reviewed-by: Christian König 
Reviewed-by: Marek Olšák 
Reviewed-by: Alex Deucher 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 30a1aa8..1e997d9 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -292,6 +292,8 @@ static struct amdgpu_winsys_bo *amdgpu_create_bo(struct 
amdgpu_winsys *ws,
   request.preferred_heap |= AMDGPU_GEM_DOMAIN_VRAM;
   if (flags & RADEON_FLAG_CPU_ACCESS)
  request.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+  if (flags & RADEON_FLAG_NO_CPU_ACCESS)
+ request.flags |= AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
}
if (initial_domain & RADEON_DOMAIN_GTT) {
   request.preferred_heap |= AMDGPU_GEM_DOMAIN_GTT;

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Mesa (master): nv50/ir: optimize mad/fma with third argument 0 to mul

2016-01-28 Thread Ilia Mirkin 
Module: Mesa
Branch: master
Commit: 29d09f8747abea35f4deadced0196725d4ab89cf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=29d09f8747abea35f4deadced0196725d4ab89cf

Author: Karol Herbst 
Date:   Wed Jan 27 18:25:08 2016 +0100

nv50/ir: optimize mad/fma with third argument 0 to mul

Very modest effect, but it's clearly the right thing to do.

total instructions in shared programs : 6131491 -> 6131398 (-0.00%)
total gprs used in shared programs: 910157 -> 910131 (-0.00%)
total local used in shared programs   : 15328 -> 15328 (0.00%)

localgpr   inst  bytes
helped   0  55  85  85
  hurt   0  26  20  20

Signed-off-by: Karol Herbst 
Reviewed-by: Ilia Mirkin 

---

 .../drivers/nouveau/codegen/nv50_ir_peephole.cpp| 21 +
 1 file changed, 21 insertions(+)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index bda9c7d..eb790d0 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -336,6 +336,7 @@ private:
void expr(Instruction *, ImmediateValue&, ImmediateValue&);
void expr(Instruction *, ImmediateValue&, ImmediateValue&, ImmediateValue&);
void opnd(Instruction *, ImmediateValue&, int s);
+   void opnd3(Instruction *, ImmediateValue&);
 
void unary(Instruction *, const ImmediateValue&);
 
@@ -388,6 +389,8 @@ ConstantFolding::visit(BasicBlock *bb)
   else
   if (i->srcExists(1) && i->src(1).getImmediate(src1))
  opnd(i, src1, 1);
+  if (i->srcExists(2) && i->src(2).getImmediate(src2))
+ opnd3(i, src2);
}
return true;
 }
@@ -873,6 +876,24 @@ ConstantFolding::tryCollapseChainedMULs(Instruction *mul2,
 }
 
 void
+ConstantFolding::opnd3(Instruction *i, ImmediateValue &imm2)
+{
+   switch (i->op) {
+   case OP_MAD:
+   case OP_FMA:
+  if (imm2.isInteger(0)) {
+ i->op = OP_MUL;
+ i->setSrc(2, NULL);
+ foldCount++;
+ return;
+  }
+  break;
+   default:
+  return;
+   }
+}
+
+void
 ConstantFolding::opnd(Instruction *i, ImmediateValue &imm0, int s)
 {
const int t = !s;

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Mesa (master): nv50/ir: optimize shl(shr(a, c), c) to and(a, ~((1 << c) - 1))

2016-01-28 Thread Ilia Mirkin 
Module: Mesa
Branch: master
Commit: 978ae28ca279354852a586b202e705db3d596041
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=978ae28ca279354852a586b202e705db3d596041

Author: Karol Herbst 
Date:   Wed Jan 27 18:25:05 2016 +0100

nv50/ir: optimize shl(shr(a, c), c) to and(a, ~((1 << c) - 1))

Following shader-db results on GK110:

total instructions in shared programs : 6141510 -> 6131491 (-0.16%)
total gprs used in shared programs: 910187 -> 910157 (-0.00%)
total local used in shared programs   : 15328 -> 15328 (0.00%)

localgpr   inst  bytes
helped   0  18 821 821
  hurt   0   0   0   0

Signed-off-by: Karol Herbst 
Reviewed-by: Ilia Mirkin 

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 8 
 1 file changed, 8 insertions(+)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index 95e9fdf..b2c9fdf 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -1202,6 +1202,14 @@ ConstantFolding::opnd(Instruction *i, ImmediateValue 
&imm0, int s)
 i->setSrc(1, bld.loadImm(NULL, imm0.reg.data.u32 + 
imm1.reg.data.u32));
  }
  break;
+  case OP_SHR:
+ if (si->src(1).getImmediate(imm1) && imm0.reg.data.u32 == 
imm1.reg.data.u32) {
+bld.setPosition(i, false);
+i->op = OP_AND;
+i->setSrc(0, si->getSrc(0));
+i->setSrc(1, bld.loadImm(NULL, ~((1 << imm0.reg.data.u32) - 1)));
+ }
+ break;
   case OP_MUL:
  int muls;
  if (isFloatType(si->dType))

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Mesa (master): nv50/ir: run DCE backwards

2016-01-28 Thread Ilia Mirkin 
Module: Mesa
Branch: master
Commit: 3aa681449ed030ba8b9c56f0a6f2b08bd1fb15a6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3aa681449ed030ba8b9c56f0a6f2b08bd1fb15a6

Author: Karol Herbst 
Date:   Wed Jan 27 18:25:07 2016 +0100

nv50/ir: run DCE backwards

Reduces calls up to 50%

Signed-off-by: Karol Herbst 
Reviewed-by: Ilia Mirkin 

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
index b2c9fdf..bda9c7d 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_peephole.cpp
@@ -3187,10 +3187,10 @@ DeadCodeElim::buryAll(Program *prog)
 bool
 DeadCodeElim::visit(BasicBlock *bb)
 {
-   Instruction *next;
+   Instruction *prev;
 
-   for (Instruction *i = bb->getFirst(); i; i = next) {
-  next = i->next;
+   for (Instruction *i = bb->getExit(); i; i = prev) {
+  prev = i->prev;
   if (i->isDead()) {
  ++deadCount;
  delete_Instruction(prog, i);

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Mesa (master): glsl: disallow implicit conversions in ESSL shaders

2016-01-28 Thread Ilia Mirkin 
Module: Mesa
Branch: master
Commit: 089f60543930fcdab3848d59e6182abcaaeb1b86
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=089f60543930fcdab3848d59e6182abcaaeb1b86

Author: Ilia Mirkin 
Date:   Wed Jan 27 13:52:41 2016 -0500

glsl: disallow implicit conversions in ESSL shaders

Signed-off-by: Ilia Mirkin 
Reviewed-by: Timothy Arceri 
Reviewed-by: Kenneth Graunke 

---

 src/compiler/glsl/ast_to_hir.cpp | 4 
 src/compiler/glsl_types.cpp  | 7 +++
 2 files changed, 11 insertions(+)

diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index dfd3196..3fca18a 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -291,6 +291,10 @@ apply_implicit_conversion(const glsl_type *to, ir_rvalue * 
&from,
if (!state->is_version(120, 0))
   return false;
 
+   /* ESSL does not allow implicit conversions */
+   if (state->es_shader)
+  return false;
+
/* From page 27 (page 33 of the PDF) of the GLSL 1.50 spec:
 *
 *"There are no implicit array or structure conversions. For
diff --git a/src/compiler/glsl_types.cpp b/src/compiler/glsl_types.cpp
index 17ebf07..ef6c3c6 100644
--- a/src/compiler/glsl_types.cpp
+++ b/src/compiler/glsl_types.cpp
@@ -1139,6 +1139,13 @@ glsl_type::can_implicitly_convert_to(const glsl_type 
*desired,
if (this == desired)
   return true;
 
+   /* ESSL does not allow implicit conversions. If there is no state, we're
+* doing intra-stage function linking where these checks have already been
+* done.
+*/
+   if (state && state->es_shader)
+  return false;
+
/* There is no conversion among matrix types. */
if (this->matrix_columns > 1 || desired->matrix_columns > 1)
   return false;

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Mesa (master): radeonsi: Add option for SI scheduler

2016-01-28 Thread Axel Davy 
Module: Mesa
Branch: master
Commit: dda7a849868d5a4be6cec9d28c86a52aba62b32b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dda7a849868d5a4be6cec9d28c86a52aba62b32b

Author: Axel Davy 
Date:   Fri Jan 15 10:47:42 2016 +0100

radeonsi: Add option for SI scheduler

Add a debug option to select the LLVM SI Machine Scheduler.
R600_DEBUG=sisched

Signed-off-by: Axel Davy 
Reviewed-by: Edward O'Callaghan 
Reviewed-by: Nicolai Hähnle 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeon/r600_pipe_common.c | 1 +
 src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
 src/gallium/drivers/radeonsi/si_pipe.c| 6 +-
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 34fe57b..c827dbd 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -409,6 +409,7 @@ static const struct debug_named_value 
common_debug_options[] = {
{ "nodcc", DBG_NO_DCC, "Disable DCC." },
{ "nodccclear", DBG_NO_DCC_CLEAR, "Disable DCC fast clear." },
{ "norbplus", DBG_NO_RB_PLUS, "Disable RB+ on Stoney." },
+   { "sisched", DBG_SI_SCHED, "Enable LLVM SI Machine Instruction 
Scheduler." },
 
DEBUG_NAMED_VALUE_END /* must be last */
 };
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index a8928f2..88e9cbc 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -87,6 +87,7 @@
 #define DBG_NO_DCC (1llu << 43)
 #define DBG_NO_DCC_CLEAR   (1llu << 44)
 #define DBG_NO_RB_PLUS (1llu << 45)
+#define DBG_SI_SCHED   (1llu << 46)
 
 #define R600_MAP_BUFFER_ALIGNMENT 64
 
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 0c1ae90..f483f92 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -215,7 +215,11 @@ static struct pipe_context *si_create_context(struct 
pipe_screen *screen,
r600_target = radeon_llvm_get_r600_target(triple);
sctx->tm = LLVMCreateTargetMachine(r600_target, triple,
   
r600_get_llvm_processor_name(sscreen->b.family),
-  "+DumpCode,+vgpr-spilling",
+#if HAVE_LLVM >= 0x0308
+  sscreen->b.debug_flags & 
DBG_SI_SCHED ?
+   
"+DumpCode,+vgpr-spilling,+si-scheduler" :
+#endif
+   "+DumpCode,+vgpr-spilling",
   LLVMCodeGenLevelDefault,
   LLVMRelocDefault,
   LLVMCodeModelDefault);

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Demos (master): wgl: Minor cleanups to wglfont.

2016-01-28 Thread Jose Fonseca 
Module: Demos
Branch: master
Commit: fca1062e8bdeaff6bedcd43fba718a0f78aa3c77
URL:
http://cgit.freedesktop.org/mesa/demos/commit/?id=fca1062e8bdeaff6bedcd43fba718a0f78aa3c77

Author: Jose Fonseca 
Date:   Thu Jan 28 14:21:08 2016 +

wgl: Minor cleanups to wglfont.

Ensure things get destroyed, and use the full 256 range.

Trivial.

---

 src/wgl/wglfont.c | 15 +--
 1 file changed, 13 insertions(+), 2 deletions(-)

diff --git a/src/wgl/wglfont.c b/src/wgl/wglfont.c
index 2e448ec..d61195f 100644
--- a/src/wgl/wglfont.c
+++ b/src/wgl/wglfont.c
@@ -68,7 +68,7 @@ main(int argc, char *argv[])
pfd.dwFlags = PFD_DOUBLEBUFFER | PFD_DRAW_TO_WINDOW | PFD_SUPPORT_OPENGL;
pfd.iPixelType = PFD_TYPE_RGBA;
pfd.cColorBits = 24;
-   pfd.cDepthBits = 24;
+   pfd.cDepthBits = 0;
pfd.iLayerType = PFD_MAIN_PLANE;
 
iPixelFormat = ChoosePixelFormat(hdc, &pfd);
@@ -87,9 +87,12 @@ main(int argc, char *argv[])
 
wglMakeCurrent(hdc, hglrc);
 
+   glClearColor(0.0, 0.0, 0.0, 1.0);
+   glClear(GL_COLOR_BUFFER_BIT);
+
SelectObject(hdc, GetStockObject(SYSTEM_FONT));
 
-   wglUseFontBitmaps(hdc, 0, 255, 1000);
+   wglUseFontBitmaps(hdc, 0, 256, 1000);
 
glListBase(1000);
 
@@ -99,5 +102,13 @@ main(int argc, char *argv[])
 
Sleep(1000);
 
+   wglMakeCurrent(NULL, NULL);
+
+   wglDeleteContext(hglrc);
+
+   ReleaseDC(hwnd, hdc);
+
+   DestroyWindow(hwnd);
+
return 0;
 }

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Mesa (master): glsl: double-precision values don't support interpolation

2016-01-28 Thread Samuel Iglesias Gonsálvez 
Module: Mesa
Branch: master
Commit: f9c43dd22f92cd631f7feffb362a4cd3dad06c87
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9c43dd22f92cd631f7feffb362a4cd3dad06c87

Author: Samuel Iglesias Gonsálvez 
Date:   Tue Jan 26 12:47:26 2016 +0100

glsl: double-precision values don't support interpolation

ARB_gpu_shader_fp64 spec says:

  "This extension does not support interpolation of double-precision
  values; doubles used as fragment shader inputs must be qualified as
  "flat"."

Fixes the regressions added by commit 781d278:

arb_gpu_shader_fp64-double-gettransformfeedbackvarying
arb_gpu_shader_fp64-tf-interleaved
arb_gpu_shader_fp64-tf-interleaved-aligned
arb_gpu_shader_fp64-tf-separate

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93878
Signed-off-by: Samuel Iglesias Gonsálvez 
Reviewed-by: Timothy Arceri 
Reviewed-by: Tapani Pälli 

---

 src/compiler/glsl/link_varyings.cpp | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/compiler/glsl/link_varyings.cpp 
b/src/compiler/glsl/link_varyings.cpp
index 264b69c..a4c730f 100644
--- a/src/compiler/glsl/link_varyings.cpp
+++ b/src/compiler/glsl/link_varyings.cpp
@@ -967,11 +967,16 @@ varying_matches::record(ir_variable *producer_var, 
ir_variable *consumer_var)
   return;
}
 
-   if ((consumer_var == NULL && producer_var->type->contains_integer()) ||
+   bool needs_flat_qualifier = consumer_var == NULL &&
+  (producer_var->type->contains_integer() ||
+   producer_var->type->contains_double());
+
+   if (needs_flat_qualifier ||
(consumer_stage != -1 && consumer_stage != MESA_SHADER_FRAGMENT)) {
   /* Since this varying is not being consumed by the fragment shader, its
* interpolation type varying cannot possibly affect rendering.
-   * Also, this variable is non-flat and is (or contains) an integer.
+   * Also, this variable is non-flat and is (or contains) an integer
+   * or a double.
* If the consumer stage is unknown, don't modify the interpolation
* type as it could affect rendering later with separate shaders.
*

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