Mesa (master): isl: Replace bash generator with python generator
Module: Mesa Branch: master Commit: 5a87bc718197deab7577a028c64a7f591bbfaec4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a87bc718197deab7577a028c64a7f591bbfaec4 Author: Dylan Baker Date: Mon Jun 13 11:19:18 2016 -0700 isl: Replace bash generator with python generator This replaces the current bash generator with a python based generator using mako. It's quite fast and works with both python 2.7 and python 3.5, and should work with 3.3+ and maybe even 3.2. It produces an almost identical file except for a minor layout changes, and the addition of a "generated file, do not edit" warning. Cc: "12.0" Signed-off-by: Dylan Baker Reviewed-by: Jason Ekstrand Reviewed-by: Emil Velikov --- src/intel/isl/Android.mk | 6 +- src/intel/isl/Makefile.am| 12 +- src/intel/isl/gen_format_layout.py | 207 +++ src/intel/isl/isl_format_layout_gen.bash | 129 --- 4 files changed, 217 insertions(+), 137 deletions(-) diff --git a/src/intel/isl/Android.mk b/src/intel/isl/Android.mk index 3134981..ff0c8c9 100644 --- a/src/intel/isl/Android.mk +++ b/src/intel/isl/Android.mk @@ -139,14 +139,14 @@ LOCAL_GENERATED_SOURCES += $(addprefix $(intermediates)/, $(ISL_GENERATED_FILES) define bash-gen @mkdir -p $(dir $@) @echo "Gen Bash: $(PRIVATE_MODULE) <= $(notdir $(@))" - $(hide) $(PRIVATE_SCRIPT) < $(PRIVATE_CSV) > $@ + $(hide) $(PRIVATE_SCRIPT) --csv $(PRIVATE_CSV) --out $@ endef isl_format_layout_deps := \ - $(LOCAL_PATH)/isl_format_layout_gen.bash \ + $(LOCAL_PATH)/gen_format_layout.py \ $(LOCAL_PATH)/isl_format_layout.csv -$(intermediates)/isl_format_layout.c: PRIVATE_SCRIPT := bash -c $(LOCAL_PATH)/isl_format_layout_gen.bash +$(intermediates)/isl_format_layout.c: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/gen_format_layout.py $(intermediates)/isl_format_layout.c: PRIVATE_CSV := $(LOCAL_PATH)/isl_format_layout.csv $(intermediates)/isl_format_layout.c: $(isl_format_layout_deps) $(call bash-gen) diff --git a/src/intel/isl/Makefile.am b/src/intel/isl/Makefile.am index 74f863a..1fd6683 100644 --- a/src/intel/isl/Makefile.am +++ b/src/intel/isl/Makefile.am @@ -1,4 +1,4 @@ -# Copyright 2015 Intel Corporation +# Copyright 2015-2016 Intel Corporation # # Permission is hereby granted, free of charge, to any person obtaining a # copy of this software and associated documentation files (the "Software"), @@ -66,10 +66,12 @@ libisl_gen9_la_CFLAGS = $(libisl_la_CFLAGS) -DGEN_VERSIONx10=90 BUILT_SOURCES = $(ISL_GENERATED_FILES) -isl_format_layout.c: isl_format_layout_gen.bash \ +PYTHON_GEN = $(AM_V_GEN)$(PYTHON2) $(PYTHON_FLAGS) + +isl_format_layout.c: gen_format_layout.py \ isl_format_layout.csv - $(AM_V_GEN)$(srcdir)/isl_format_layout_gen.bash \ - <$(srcdir)/isl_format_layout.csv >$@ + $(PYTHON_GEN) $(srcdir)/gen_format_layout.py \ + --csv $(srcdir)/isl_format_layout.csv --out $@ # # Tests @@ -87,6 +89,6 @@ tests_isl_surf_get_image_offset_test_LDADD = \ # EXTRA_DIST = \ - isl_format_layout_gen.bash \ + gen_format_layout.py \ isl_format_layout.csv \ README diff --git a/src/intel/isl/gen_format_layout.py b/src/intel/isl/gen_format_layout.py new file mode 100644 index 000..d7f3900 --- /dev/null +++ b/src/intel/isl/gen_format_layout.py @@ -0,0 +1,207 @@ +# encoding=utf-8 +# Copyright © 2016 Intel Corporation + +# Permission is hereby granted, free of charge, to any person obtaining a copy +# of this software and associated documentation files (the "Software"), to deal +# in the Software without restriction, including without limitation the rights +# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +# copies of the Software, and to permit persons to whom the Software is +# furnished to do so, subject to the following conditions: + +# The above copyright notice and this permission notice shall be included in +# all copies or substantial portions of the Software. + +# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +# SOFTWARE. + +"""Generates isl_format_layout.c.""" + +from __future__ import absolute_import, division, print_function +import argparse +import csv +import re +import textwrap + +from mako import template + +# Load the template, ensure that __future__.division is imp
Mesa (master): mesa: Make use of u_bit_scan{,64}.
Module: Mesa
Branch: master
Commit: ed2dae86aef759a6858f56d77eba77895bec5020
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed2dae86aef759a6858f56d77eba77895bec5020
Author: Mathias Fröhlich
Date: Thu Jun 9 06:35:34 2016 +0200
mesa: Make use of u_bit_scan{,64}.
Reviewed-by: Brian Paul
Tested-by: Brian Paul
Signed-off-by: Mathias Fröhlich
---
src/mesa/main/arrayobj.c | 6 +++---
src/mesa/main/buffers.c | 4 ++--
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/mesa/main/arrayobj.c b/src/mesa/main/arrayobj.c
index 897dac6..9c3451e 100644
--- a/src/mesa/main/arrayobj.c
+++ b/src/mesa/main/arrayobj.c
@@ -52,6 +52,7 @@
#include "mtypes.h"
#include "varray.h"
#include "main/dispatch.h"
+#include "util/bitscan.h"
/**
@@ -342,13 +343,12 @@ _mesa_update_vao_client_arrays(struct gl_context *ctx,
GLbitfield64 arrays = vao->NewArrays;
while (arrays) {
+ const int attrib = u_bit_scan64(&arrays);
+
struct gl_client_array *client_array;
struct gl_vertex_attrib_array *attrib_array;
struct gl_vertex_buffer_binding *buffer_binding;
- GLint attrib = ffsll(arrays) - 1;
- arrays ^= BITFIELD64_BIT(attrib);
-
attrib_array = &vao->VertexAttrib[attrib];
buffer_binding = &vao->VertexBinding[attrib_array->VertexBinding];
client_array = &vao->_VertexAttrib[attrib];
diff --git a/src/mesa/main/buffers.c b/src/mesa/main/buffers.c
index a28c583..e8aedde 100644
--- a/src/mesa/main/buffers.c
+++ b/src/mesa/main/buffers.c
@@ -36,6 +36,7 @@
#include "enums.h"
#include "fbobject.h"
#include "mtypes.h"
+#include "util/bitscan.h"
#define BAD_MASK ~0u
@@ -595,13 +596,12 @@ _mesa_drawbuffers(struct gl_context *ctx, struct
gl_framebuffer *fb,
if (n > 0 && _mesa_bitcount(destMask[0]) > 1) {
GLuint count = 0, destMask0 = destMask[0];
while (destMask0) {
- GLint bufIndex = ffs(destMask0) - 1;
+ const int bufIndex = u_bit_scan(&destMask0);
if (fb->_ColorDrawBufferIndexes[count] != bufIndex) {
updated_drawbuffers(ctx, fb);
fb->_ColorDrawBufferIndexes[count] = bufIndex;
}
count++;
- destMask0 &= ~(1 << bufIndex);
}
fb->ColorDrawBuffer[0] = buffers[0];
fb->_NumColorDrawBuffers = count;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa/gallium: Move u_bit_scan{, 64} from gallium to util.
Module: Mesa
Branch: master
Commit: c3b66566760dd44eaeed9e4df13687dc3ee69bd9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c3b66566760dd44eaeed9e4df13687dc3ee69bd9
Author: Mathias Fröhlich
Date: Thu Jun 9 06:35:34 2016 +0200
mesa/gallium: Move u_bit_scan{,64} from gallium to util.
The functions are also useful for mesa.
Introduce src/util/bitscan.{h,c}. Move ffs function
implementations from src/mesa/main/imports.{h,c}.
Move bit scan related functions from
src/gallium/auxiliary/util/u_math.h. Merge platform
handling with what is available from within mesa.
v2: Try to fix MSVC compile.
Reviewed-by: Brian Paul
Tested-by: Brian Paul
Signed-off-by: Mathias Fröhlich
---
src/gallium/auxiliary/util/u_math.h | 149 +--
src/mesa/main/imports.c | 58 --
src/mesa/main/imports.h | 17 +---
src/util/Makefile.sources | 2 +
src/util/bitscan.c | 80 +++
src/util/bitscan.h | 153
6 files changed, 237 insertions(+), 222 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_math.h
b/src/gallium/auxiliary/util/u_math.h
index ecb1d63..c94967e 100644
--- a/src/gallium/auxiliary/util/u_math.h
+++ b/src/gallium/auxiliary/util/u_math.h
@@ -46,14 +46,7 @@
#include
#include
-#ifdef PIPE_OS_UNIX
-#include /* for ffs */
-#endif
-
-#if defined(_MSC_VER)
-#include
-#endif
-
+#include "util/bitscan.h"
#ifdef __cplusplus
extern "C" {
@@ -354,80 +347,6 @@ util_half_inf_sign(int16_t x)
/**
- * Find first bit set in word. Least significant bit is 1.
- * Return 0 if no bits set.
- */
-#ifndef FFS_DEFINED
-#define FFS_DEFINED 1
-
-#if defined(_MSC_VER) && (_M_IX86 || _M_AMD64 || _M_IA64)
-static inline
-unsigned long ffs( unsigned long u )
-{
- unsigned long i;
- if (_BitScanForward(&i, u))
- return i + 1;
- else
- return 0;
-}
-#elif defined(PIPE_CC_MSVC) && defined(PIPE_ARCH_X86)
-static inline
-unsigned ffs( unsigned u )
-{
- unsigned i;
-
- if (u == 0) {
- return 0;
- }
-
- __asm bsf eax, [u]
- __asm inc eax
- __asm mov [i], eax
-
- return i;
-}
-#elif defined(__MINGW32__) || defined(PIPE_OS_ANDROID) || \
-defined(HAVE___BUILTIN_FFS)
-#define ffs __builtin_ffs
-#endif
-
-#ifdef HAVE___BUILTIN_FFSLL
-#define ffsll __builtin_ffsll
-#else
-static inline int
-ffsll(long long int val)
-{
- int bit;
-
- bit = ffs((unsigned) (val & 0x));
- if (bit != 0)
- return bit;
-
- bit = ffs((unsigned) (val >> 32));
- if (bit != 0)
- return 32 + bit;
-
- return 0;
-}
-#endif
-
-#endif /* FFS_DEFINED */
-
-/**
- * Find first bit set in long long. Least significant bit is 1.
- * Return 0 if no bits set.
- */
-#ifndef FFSLL_DEFINED
-#define FFSLL_DEFINED 1
-
-#if defined(__MINGW32__) || defined(PIPE_OS_ANDROID) || \
-defined(HAVE___BUILTIN_FFSLL)
-#define ffsll __builtin_ffsll
-#endif
-
-#endif /* FFSLL_DEFINED */
-
-/**
* Find last bit set in a word. The least significant bit is 1.
* Return 0 if no bits are set.
*/
@@ -479,72 +398,6 @@ util_last_bit_signed(int i)
return util_last_bit(~(unsigned)i);
}
-/* Destructively loop over all of the bits in a mask as in:
- *
- * while (mymask) {
- * int i = u_bit_scan(&mymask);
- * ... process element i
- * }
- *
- */
-static inline int
-u_bit_scan(unsigned *mask)
-{
- int i = ffs(*mask) - 1;
- *mask &= ~(1u << i);
- return i;
-}
-
-#ifndef _MSC_VER
-static inline int
-u_bit_scan64(uint64_t *mask)
-{
- int i = ffsll(*mask) - 1;
- *mask &= ~(1llu << i);
- return i;
-}
-#endif
-
-/* For looping over a bitmask when you want to loop over consecutive bits
- * manually, for example:
- *
- * while (mask) {
- *int start, count, i;
- *
- *u_bit_scan_consecutive_range(&mask, &start, &count);
- *
- *for (i = 0; i < count; i++)
- * ... process element (start+i)
- * }
- */
-static inline void
-u_bit_scan_consecutive_range(unsigned *mask, int *start, int *count)
-{
- if (*mask == 0x) {
- *start = 0;
- *count = 32;
- *mask = 0;
- return;
- }
- *start = ffs(*mask) - 1;
- *count = ffs(~(*mask >> *start)) - 1;
- *mask &= ~(((1u << *count) - 1) << *start);
-}
-
-static inline void
-u_bit_scan_consecutive_range64(uint64_t *mask, int *start, int *count)
-{
- if (*mask == ~0llu) {
- *start = 0;
- *count = 64;
- *mask = 0;
- return;
- }
- *start = ffsll(*mask) - 1;
- *count = ffsll(~(*mask >> *start)) - 1;
- *mask &= ~(((1llu << *count) - 1) << *start);
-}
-
/* Returns a bitfield in which the first count bits starting at start are
* set.
*/
diff --git a/src/mesa/main/imports.c b/src/mesa/main/imports.c
index fe54109..808b8f6 100644
--- a/src/mesa/main/imports.c
+++ b/src/mesa/main/imports.c
@@ -219,64 +219,6 @@ _mesa_align_realloc(void *oldBuffer, size_t oldSize,
size_t newSize,
/*@{*/
-#ifndef HAVE___BUILTIN_FFS
-/**
- * Find
Mesa (master): clover: Include generated sources in AM_CPPFLAGS
Module: Mesa Branch: master Commit: fafe026dbe0680c971bf3ba2452954eea84287f2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fafe026dbe0680c971bf3ba2452954eea84287f2 Author: Aaron Watry Date: Mon Jun 13 21:46:33 2016 -0500 clover: Include generated sources in AM_CPPFLAGS git_sha1.c is generated in $(top_builddir)/src. Fixes out-of-tree builds since 4825264f75c83576. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96516 Signed-off-by: Aaron Watry Reviewed-and-Tested-by: Michel Dänzer --- src/gallium/state_trackers/clover/Makefile.am | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/state_trackers/clover/Makefile.am b/src/gallium/state_trackers/clover/Makefile.am index 4c9d7d9..d0b1914 100644 --- a/src/gallium/state_trackers/clover/Makefile.am +++ b/src/gallium/state_trackers/clover/Makefile.am @@ -7,6 +7,7 @@ AM_CPPFLAGS = \ -I$(top_srcdir)/src/gallium/drivers \ -I$(top_srcdir)/src/gallium/auxiliary \ -I$(top_srcdir)/src/gallium/winsys \ + -I$(top_builddir)/src \ -I$(srcdir) if HAVE_CLOVER_ICD ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nv50/ir: make Graph destructor virtual
Module: Mesa
Branch: master
Commit: 0140938b26c9585fb432a4391ddef2f82b91a57d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0140938b26c9585fb432a4391ddef2f82b91a57d
Author: Stephan Bergmann
Date: Thu Jun 9 17:13:20 2016 +0200
nv50/ir: make Graph destructor virtual
Avoid ASan new-delete-type-mismatch when Function::domTree is created as
DominatorTree in Function::convertToSSA but destroyed only as base
Graph in ~Function.
Reviewed-by: Ilia Mirkin
---
src/gallium/drivers/nouveau/codegen/nv50_ir_graph.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_graph.h
b/src/gallium/drivers/nouveau/codegen/nv50_ir_graph.h
index b0981ff..115f20e 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_graph.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_graph.h
@@ -147,7 +147,7 @@ public:
public:
Graph();
- ~Graph(); // does *not* free the nodes (make it an option ?)
+ virtual ~Graph(); // does *not* free the nodes (make it an option ?)
inline Node *getRoot() const { return root; }
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/compiler: Bring back the INTEL_PRECISE_TRIG environment variable
Module: Mesa
Branch: master
Commit: be32a2132785fbc119f17e62070e007ee7d17af7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=be32a2132785fbc119f17e62070e007ee7d17af7
Author: Jason Ekstrand
Date: Sat Jun 11 13:17:27 2016 -0700
i965/compiler: Bring back the INTEL_PRECISE_TRIG environment variable
This was removed in d9546b0c5d and replced with the precise_trig driconf
option. However, we still need precise trig in the Vulkan driver so this
commit brings back the environment variable and compiler->precise_trig is
effectively the logical OR of the two.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96484
Reviewed-by: Kenneth Graunke
Cc: "12.0"
---
src/mesa/drivers/dri/i965/brw_compiler.c | 2 ++
src/mesa/drivers/dri/i965/brw_context.c | 4 ++--
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.c
b/src/mesa/drivers/dri/i965/brw_compiler.c
index 9eda3fc..a4855a0 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.c
+++ b/src/mesa/drivers/dri/i965/brw_compiler.c
@@ -103,6 +103,8 @@ brw_compiler_create(void *mem_ctx, const struct
brw_device_info *devinfo)
brw_fs_alloc_reg_sets(compiler);
brw_vec4_alloc_reg_set(compiler);
+ compiler->precise_trig = env_var_as_boolean("INTEL_PRECISE_TRIG", false);
+
compiler->scalar_stage[MESA_SHADER_VERTEX] =
devinfo->gen >= 8 && !(INTEL_DEBUG & DEBUG_VEC4VS);
compiler->scalar_stage[MESA_SHADER_TESS_CTRL] =
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index a5c6581..dabe6c6 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -803,8 +803,8 @@ brw_process_driconf_options(struct brw_context *brw)
brw->precompile = driQueryOptionb(&brw->optionCache, "shader_precompile");
- brw->intelScreen->compiler->precise_trig =
- driQueryOptionb(&brw->optionCache, "precise_trig");
+ if (driQueryOptionb(&brw->optionCache, "precise_trig"))
+ brw->intelScreen->compiler->precise_trig = true;
ctx->Const.ForceGLSLExtensionsWarn =
driQueryOptionb(options, "force_glsl_extensions_warn");
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Defeat the register stride checker in URB reads.
Module: Mesa
Branch: master
Commit: ed3ba651f6faa4ea94dde16fa880781090785477
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed3ba651f6faa4ea94dde16fa880781090785477
Author: Kenneth Graunke
Date: Wed Jun 8 16:24:50 2016 -0700
i965: Defeat the register stride checker in URB reads.
Pulling DF inputs from the URB generates messages like:
send(8) g23<1>DFg1<8,8,1>UD
urb 3 SIMD8 read mlen 1 rlen 2 { align1 1Q };
which makes the simulator angry:
"For 64-bit Align1 operation or multiplication of dwords in CHV,
source horizontal stride must be aligned to qword."
This seems to be documented in the Cherryview PRM, Volume 7, Page 823:
"When source or destination datatype is 64b or operation is integer
DWord multiply, regioning in Align1 must follow these rules:
1. Source and Destination horizontal stride must be aligned to the
same qword."
Setting the source horizontal stride to QWord is insane, as it's the
message header containing 8 URB handles in a single 32-bit DWord.
Instead, we should whack the destination type to UD, D, or F so that
the register stride checker doesn't notice. The destination type of
send messages is basically irrelevant anyway.
Cc: "12.0"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95462
Signed-off-by: Kenneth Graunke
Reviewed-by: Jordan Justen
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 93a9519..8faa856 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -440,7 +440,7 @@ fs_generator::generate_urb_read(fs_inst *inst,
assert(header.type == BRW_REGISTER_TYPE_UD);
brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
- brw_set_dest(p, send, dst);
+ brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UD));
brw_set_src0(p, send, header);
brw_set_src1(p, send, brw_imm_ud(0u));
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Fix issues with number of VS URB entries on Cherryview/Broxton.
Module: Mesa Branch: master Commit: 9f37df06dafbf54cec6749543cac1baa77d0b5e2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f37df06dafbf54cec6749543cac1baa77d0b5e2 Author: Kenneth Graunke Date: Wed Jun 8 15:55:18 2016 -0700 i965: Fix issues with number of VS URB entries on Cherryview/Broxton. Cherryview/Broxton annoyingly have a minimum number of VS URB entries of 34, which is not a multiple of 8. When the VS size is less than 9, the number of VS entries has to be a multiple of 8. Notably, BLORP programmed the minimum number of VS URB entries (34), with a size of 1 (less than 9), which is invalid. It seemed like this could be a problem in the regular URB code as well, so I went ahead and updated that to be safe. Cc: "12.0" Signed-off-by: Kenneth Graunke Reviewed-by: Jordan Justen --- src/mesa/drivers/dri/i965/gen7_blorp.c | 5 +++-- src/mesa/drivers/dri/i965/gen7_urb.c | 2 ++ 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.c b/src/mesa/drivers/dri/i965/gen7_blorp.c index 270fe57..235f0b5 100644 --- a/src/mesa/drivers/dri/i965/gen7_blorp.c +++ b/src/mesa/drivers/dri/i965/gen7_blorp.c @@ -67,8 +67,9 @@ gen7_blorp_emit_urb_config(struct brw_context *brw) push_constant_bytes / chunk_size_bytes; const unsigned vs_size = 1; const unsigned vs_start = push_constant_chunks; + const unsigned min_vs_entries = ALIGN(brw->urb.min_vs_entries, 8); const unsigned vs_chunks = - DIV_ROUND_UP(brw->urb.min_vs_entries * vs_size * 64, chunk_size_bytes); + DIV_ROUND_UP(min_vs_entries * vs_size * 64, chunk_size_bytes); if (gen7_blorp_skip_urb_config(brw)) return; @@ -83,7 +84,7 @@ gen7_blorp_emit_urb_config(struct brw_context *brw) urb_size / 2 /* fs_size */); gen7_emit_urb_state(brw, - brw->urb.min_vs_entries /* num_vs_entries */, + min_vs_entries /* num_vs_entries */, vs_size, vs_start, 0 /* num_hs_entries */, diff --git a/src/mesa/drivers/dri/i965/gen7_urb.c b/src/mesa/drivers/dri/i965/gen7_urb.c index a412a42..387ed2e 100644 --- a/src/mesa/drivers/dri/i965/gen7_urb.c +++ b/src/mesa/drivers/dri/i965/gen7_urb.c @@ -234,6 +234,8 @@ gen7_upload_urb(struct brw_context *brw) */ unsigned vs_min_entries = tess_present && brw->gen == 8 ? 192 : brw->urb.min_vs_entries; + /* Min VS Entries isn't a multiple of 8 on Cherryview/Broxton; round up */ + vs_min_entries = ALIGN(vs_min_entries, vs_granularity); unsigned vs_chunks = DIV_ROUND_UP(vs_min_entries * vs_entry_size_bytes, chunk_size_bytes); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Defeat the register stride checker in pull uniform messages.
Module: Mesa Branch: master Commit: a0ed8503b753574b14df3dc280fd917ae7c207f8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0ed8503b753574b14df3dc280fd917ae7c207f8 Author: Samuel Iglesias Gonsálvez Date: Thu Jun 9 13:03:59 2016 +0200 i965: Defeat the register stride checker in pull uniform messages. Pulling DF uniforms from pull constant buffer generates messages like: send(4) g12<1>DFg12<0,1,0>F sampler ld SIMD4x2 Surface = 1 Sampler = 0 mlen 1 rlen 1 which produces GPU hangs in Cherryview/Braswell: "For 64-bit Align1 operation or multiplication of dwords in CHV, source horizontal stride must be aligned to qword." This seems to be documented in the Cherryview PRM, Volume 7, Page 843: "When source or destination datatype is 64b or operation is integer DWord multiply, regioning in Align1 must follow these rules: 1. Source and Destination horizontal stride must be aligned to the same qword." We should set the destination type to UD, D, or F so that the register stride checker doesn't notice. The destination type of send messages is basically irrelevant anyway. Cc: "12.0" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=95462 Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Kenneth Graunke Reviewed-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 8faa856..d25d26a 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -1177,7 +1177,7 @@ fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst, brw_inst_set_exec_size(devinfo, send, BRW_EXECUTE_4); brw_pop_insn_state(p); - brw_set_dest(p, send, dst); + brw_set_dest(p, send, retype(dst, BRW_REGISTER_TYPE_UD)); brw_set_src0(p, send, src); brw_set_sampler_message(p, send, surf_index, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl: make sure UBO arrays are sized in ES
Module: Mesa
Branch: master
Commit: b010fa85675b98962426fe8961466fbae2d25499
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b010fa85675b98962426fe8961466fbae2d25499
Author: Timothy Arceri
Date: Tue Jun 14 10:13:41 2016 +1000
glsl: make sure UBO arrays are sized in ES
This check was removed in 5b2675093e86 add it back in.
Reviewed-by: Dave Airlie
Cc: "12.0"
https://bugs.freedesktop.org/show_bug.cgi?id=96349
---
src/compiler/glsl/ast_to_hir.cpp | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index 1c751f6..ea32924 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -7613,6 +7613,20 @@ ast_interface_block::hir(exec_list *instructions,
if (is_unsized_array_last_element(var)) {
var->data.from_ssbo_unsized_array = true;
}
+} else {
+ /* From GLSL ES 3.10 spec, section 4.1.9 "Arrays":
+*
+* "If an array is declared as the last member of a shader
storage
+* block and the size is not specified at compile-time, it is
+* sized at run-time. In all other cases, arrays are sized only
+* at compile-time."
+*/
+ if (state->es_shader) {
+ _mesa_glsl_error(&loc, state, "unsized array `%s' "
+ "definition: only last member of a shader "
+ "storage block can be defined as unsized "
+ "array", fields[i].name);
+ }
}
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Fix scratch overallocation if the original slot size was already a power of two.
Module: Mesa
Branch: master
Commit: 013ae4a70aeb40dc74e53943824bff33dda109e1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=013ae4a70aeb40dc74e53943824bff33dda109e1
Author: Francisco Jerez
Date: Wed Jun 8 17:53:24 2016 -0700
i965: Fix scratch overallocation if the original slot size was already a power
of two.
The bitwise arithmetic trick used in brw_get_scratch_size() to clamp
the scratch allocation to 1KB has the unintended side effect that it
will cause us to allocate 2x the required amount of scratch space if
the original per-thread scratch size happened to be already a power of
two. Instead use the obvious MAX2 idiom to clamp the scratch
allocation to the expected range.
Cc:
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 4b22201..daa9ed2 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1477,7 +1477,7 @@ void brwInitFragProgFuncs( struct dd_function_table
*functions );
static inline int
brw_get_scratch_size(int size)
{
- return util_next_power_of_two(size | 1023);
+ return MAX2(1024, util_next_power_of_two(size));
}
void brw_get_scratch_bo(struct brw_context *brw,
drm_intel_bo **scratch_bo, int size);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): clover: Update OpenCL version string to match OpenGL
Module: Mesa
Branch: master
Commit: 4825264f75c83576f251290547f121f066b46a70
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4825264f75c83576f251290547f121f066b46a70
Author: Vedran Miletić
Date: Mon Jun 6 12:43:33 2016 +0200
clover: Update OpenCL version string to match OpenGL
Change MESA into Mesa in CL_PLATFORM_VERSION and CL_DEVICE_VERSION. For
both, always append git version suffix from git_sha1.h.
v5: move semicolon to same line as MESA_GIT_SHA1.
v4: drop #ifdef guards.
v3: add missing include.
v2: change CL_DEVICE_VERSION as well.
Cc:
Reviewed-by: Francisco Jerez
---
src/gallium/state_trackers/clover/api/device.cpp | 4 +++-
src/gallium/state_trackers/clover/api/platform.cpp | 4 +++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/gallium/state_trackers/clover/api/device.cpp
b/src/gallium/state_trackers/clover/api/device.cpp
index bc93f91..ed323e0 100644
--- a/src/gallium/state_trackers/clover/api/device.cpp
+++ b/src/gallium/state_trackers/clover/api/device.cpp
@@ -23,6 +23,7 @@
#include "api/util.hpp"
#include "core/platform.hpp"
#include "core/device.hpp"
+#include "git_sha1.h"
using namespace clover;
@@ -300,7 +301,8 @@ clGetDeviceInfo(cl_device_id d_dev, cl_device_info param,
break;
case CL_DEVICE_VERSION:
- buf.as_string() = "OpenCL 1.1 MESA " PACKAGE_VERSION;
+ buf.as_string() = "OpenCL 1.1 Mesa " PACKAGE_VERSION
+" (" MESA_GIT_SHA1 ")";
break;
case CL_DEVICE_EXTENSIONS:
diff --git a/src/gallium/state_trackers/clover/api/platform.cpp
b/src/gallium/state_trackers/clover/api/platform.cpp
index cf71593..cdb8a99 100644
--- a/src/gallium/state_trackers/clover/api/platform.cpp
+++ b/src/gallium/state_trackers/clover/api/platform.cpp
@@ -22,6 +22,7 @@
#include "api/util.hpp"
#include "core/platform.hpp"
+#include "git_sha1.h"
using namespace clover;
@@ -57,7 +58,8 @@ clover::GetPlatformInfo(cl_platform_id d_platform,
cl_platform_info param,
break;
case CL_PLATFORM_VERSION:
- buf.as_string() = "OpenCL 1.1 MESA " PACKAGE_VERSION;
+ buf.as_string() = "OpenCL 1.1 Mesa " PACKAGE_VERSION
+" (" MESA_GIT_SHA1 ")";
break;
case CL_PLATFORM_NAME:
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Keep track of the per-thread scratch allocation in brw_stage_state.
Module: Mesa
Branch: master
Commit: d960284e447df9b1563deef0ce950617decfba63
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d960284e447df9b1563deef0ce950617decfba63
Author: Francisco Jerez
Date: Mon Jun 13 14:56:22 2016 -0700
i965: Keep track of the per-thread scratch allocation in brw_stage_state.
This will be used to find out what per-thread slot size a previously
allocated scratch BO was used with in order to fix a hardware race
condition without introducing additional stalls or memory allocations.
Instead of calling brw_get_scratch_bo() manually from the various
codegen functions, call a new helper function that keeps track of the
per-thread scratch size and conditionally allocates a larger scratch
BO.
v2: Handle BO allocation manually instead of relying on
brw_get_scratch_bo (Ken).
Cc:
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_context.h | 10 +++
src/mesa/drivers/dri/i965/brw_cs.c | 48 -
src/mesa/drivers/dri/i965/brw_gs.c | 8 +++---
src/mesa/drivers/dri/i965/brw_program.c | 22 +++
src/mesa/drivers/dri/i965/brw_tcs.c | 8 +++---
src/mesa/drivers/dri/i965/brw_tes.c | 8 +++---
src/mesa/drivers/dri/i965/brw_vs.c | 8 +++---
src/mesa/drivers/dri/i965/brw_wm.c | 7 +++--
8 files changed, 70 insertions(+), 49 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index daa9ed2..9618b4a 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -677,6 +677,12 @@ struct brw_stage_state
*/
drm_intel_bo *scratch_bo;
+ /**
+* Scratch slot size allocated for each thread in the buffer object given
+* by \c scratch_bo.
+*/
+ uint32_t per_thread_scratch;
+
/** Offset in the program cache to the program */
uint32_t prog_offset;
@@ -1481,6 +1487,10 @@ brw_get_scratch_size(int size)
}
void brw_get_scratch_bo(struct brw_context *brw,
drm_intel_bo **scratch_bo, int size);
+void brw_alloc_stage_scratch(struct brw_context *brw,
+ struct brw_stage_state *stage_state,
+ unsigned per_thread_size,
+ unsigned thread_count);
void brw_init_shader_time(struct brw_context *brw);
int brw_get_shader_time_index(struct brw_context *brw,
struct gl_shader_program *shader_prog,
diff --git a/src/mesa/drivers/dri/i965/brw_cs.c
b/src/mesa/drivers/dri/i965/brw_cs.c
index 22856b6..45128bc 100644
--- a/src/mesa/drivers/dri/i965/brw_cs.c
+++ b/src/mesa/drivers/dri/i965/brw_cs.c
@@ -148,31 +148,29 @@ brw_codegen_cs_prog(struct brw_context *brw,
}
}
- if (prog_data.base.total_scratch) {
- const unsigned subslices = MAX2(brw->intelScreen->subslice_total, 1);
-
- /* WaCSScratchSize:hsw
- *
- * Haswell's scratch space address calculation appears to be sparse
- * rather than tightly packed. The Thread ID has bits indicating
- * which subslice, EU within a subslice, and thread within an EU
- * it is. There's a maximum of two slices and two subslices, so these
- * can be stored with a single bit. Even though there are only 10 EUs
- * per subslice, this is stored in 4 bits, so there's an effective
- * maximum value of 16 EUs. Similarly, although there are only 7
- * threads per EU, this is stored in a 3 bit number, giving an effective
- * maximum value of 8 threads per EU.
- *
- * This means that we need to use 16 * 8 instead of 10 * 7 for the
- * number of threads per subslice.
- */
- const unsigned scratch_ids_per_subslice =
- brw->is_haswell ? 16 * 8 : brw->max_cs_threads;
-
- brw_get_scratch_bo(brw, &brw->cs.base.scratch_bo,
- prog_data.base.total_scratch *
- scratch_ids_per_subslice * subslices);
- }
+ const unsigned subslices = MAX2(brw->intelScreen->subslice_total, 1);
+
+ /* WaCSScratchSize:hsw
+*
+* Haswell's scratch space address calculation appears to be sparse
+* rather than tightly packed. The Thread ID has bits indicating
+* which subslice, EU within a subslice, and thread within an EU
+* it is. There's a maximum of two slices and two subslices, so these
+* can be stored with a single bit. Even though there are only 10 EUs
+* per subslice, this is stored in 4 bits, so there's an effective
+* maximum value of 16 EUs. Similarly, although there are only 7
+* threads per EU, this is stored in a 3 bit number, giving an effective
+* maximum value of 8 threads per EU.
+*
+* This means that we need to use 16 * 8 instead of 10 * 7 for the
+* number of threads per subslice.
+*/
+ const unsigned scratch_ids_per_subslice =
+ brw->is_haswell ? 16 * 8 : brw->max_cs_threads;
+
+ brw_alloc_stage_scratch
Mesa (master): i965/fs: Fix regs_written for SIMD-lowered instructions some more.
Module: Mesa Branch: master Commit: bd9f9726519fad94e88b9266b0c255aa00251f4d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd9f9726519fad94e88b9266b0c255aa00251f4d Author: Francisco Jerez Date: Fri Jun 10 17:55:39 2016 -0700 i965/fs: Fix regs_written for SIMD-lowered instructions some more. ISTR having suggested this during review of the recent FP64 changes to the SIMD lowering pass, but it doesn't look like it was taken into account in the end. Using the fs_reg::component_size helper instead of this open-coded variant makes sure that the stride is taken into account correctly. Fixes at least the following piglit tests with spilling forced on (since otherwise regs_written would be calculated incorrectly and the spilling code would be rather confused about how much data needs to be spilled): spec.arb_gpu_shader_fp64.shader_storage.layout-std140-fp64-shader spec.arb_gpu_shader_fp64.shader_storage.layout-std140-fp64-mixed-shader Cc: Reviewed-by: Jordan Justen --- src/mesa/drivers/dri/i965/brw_fs.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 104c20b..0347b0a 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -5261,9 +5261,9 @@ fs_visitor::lower_simd_width() split_inst.src[j] = emit_unzip(lbld, block, inst, j); split_inst.dst = emit_zip(lbld, block, inst); -split_inst.regs_written = - DIV_ROUND_UP(type_sz(inst->dst.type) * dst_size * lower_width, -REG_SIZE); +split_inst.regs_written = DIV_ROUND_UP( + split_inst.dst.component_size(lower_width) * dst_size, + REG_SIZE); lbld.emit(split_inst); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Fix cross-primitive scratch corruption when changing the per-thread allocation.
Module: Mesa
Branch: master
Commit: a84b5d43e2e54dbebe3600111f4f35c29411f831
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a84b5d43e2e54dbebe3600111f4f35c29411f831
Author: Francisco Jerez
Date: Fri Jun 10 16:41:59 2016 -0700
i965: Fix cross-primitive scratch corruption when changing the per-thread
allocation.
I haven't found any mention of this in the hardware docs, but
experimentally what seems to be going on is that when the per-thread
scratch slot size is changed between two pipelined draw calls, shader
invocations using the old and new scratch size setting may end up
being executed in parallel, causing their scratch offset calculations
to be based in a different partitioning of the scratch space, which
can cause their thread-local scratch space to overlap leading to
cross-thread scratch corruption.
I've been experimenting with alternative workarounds, like emitting a
PIPE_CONTROL with DC flush and CS stall between draw (or dispatch
compute) calls using different per-thread scratch allocation settings,
or avoiding reuse of the scratch BO if the per-thread scratch
allocation doesn't exactly match the original. Both seem to be as
effective as this workaround, but they have potential performance
implications, while this should be basically for free.
Fixes over 40 failures in our CI system with spilling forced on
(including CTS, dEQP and Piglit failures) on a number of different
platforms from Gen4 to Gen9. The 'glsl-max-varyings' piglit test
seems to be able to reproduce this bug consistently in the vertex
shader on at least Gen4, Gen8 and Gen9 with spilling forced on.
Cc:
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_context.h | 13 +
src/mesa/drivers/dri/i965/brw_vs_state.c | 2 +-
src/mesa/drivers/dri/i965/brw_wm_state.c | 2 +-
src/mesa/drivers/dri/i965/gen6_gs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen6_vs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen6_wm_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_cs_state.c | 6 +++---
src/mesa/drivers/dri/i965/gen7_ds_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_gs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_hs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_vs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen7_wm_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_ds_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_gs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_hs_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_ps_state.c | 2 +-
src/mesa/drivers/dri/i965/gen8_vs_state.c | 2 +-
17 files changed, 31 insertions(+), 18 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 9618b4a..6e84506 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -674,6 +674,19 @@ struct brw_stage_state
/**
* Optional scratch buffer used to store spilled register values and
* variably-indexed GRF arrays.
+*
+* The contents of this buffer are short-lived so the same memory can be
+* re-used at will for multiple shader programs (executed by the same fixed
+* function). However reusing a scratch BO for which shader invocations
+* are still in flight with a per-thread scratch slot size other than the
+* original can cause threads with different scratch slot size and FFTID
+* (which may be executed in parallel depending on the shader stage and
+* hardware generation) to map to an overlapping region of the scratch
+* space, which can potentially lead to mutual scratch space corruption.
+* For that reason if you borrow this scratch buffer you should only be
+* using the slot size given by the \c per_thread_scratch member below,
+* unless you're taking additional measures to synchronize thread execution
+* across slot size changes.
*/
drm_intel_bo *scratch_bo;
diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c
b/src/mesa/drivers/dri/i965/brw_vs_state.c
index c728f09..331949a 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
@@ -83,7 +83,7 @@ brw_upload_vs_unit(struct brw_context *brw)
vs->thread2.scratch_space_base_pointer =
stage_state->scratch_bo->offset64 >> 10; /* reloc */
vs->thread2.per_thread_scratch_space =
-ffs(brw->vs.prog_data->base.base.total_scratch) - 11;
+ffs(stage_state->per_thread_scratch) - 11;
} else {
vs->thread2.scratch_space_base_pointer = 0;
vs->thread2.per_thread_scratch_space = 0;
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c
b/src/mesa/drivers/dri/i965/brw_wm_state.c
index bf1bdc9..dda4f23 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -133,7 +133,7 @@ brw_upload_wm_unit(struct brw_context *brw)
wm->thread2.scratch_space_base_pointer =
brw->wm.base.scratch_bo->offset64 >> 10; /* reloc */
wm->thread2.per_thread_
Mesa (master): mesa: Make TexSubImage check negative dimensions sooner.
Module: Mesa
Branch: master
Commit: 2df8f4a2534e1e2258a719e7c5cbf342621fdf1f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2df8f4a2534e1e2258a719e7c5cbf342621fdf1f
Author: Kenneth Graunke
Date: Thu Apr 14 02:19:59 2016 -0700
mesa: Make TexSubImage check negative dimensions sooner.
Two dEQP tests expect INVALID_VALUE errors for negative width/height
parameters, but get INVALID_OPERATION because they haven't actually
created a destination image. This is arguably not a bug in Mesa, as
there's no specified ordering of error conditions.
However, it's also really easy to make the tests pass, and there's
no real harm in doing these checks earlier.
Fixes:
dEQP-GLES3.functional.negative_api.texture.texsubimage3d_neg_width_height
dEQP-GLES31.functional.debug.negative_coverage.get_error.texture.texsubimage3d_neg_width_height
v2: Drop redundant check (caught by Anuj Phogat).
Signed-off-by: Kenneth Graunke
Reviewed-by: Anuj Phogat
---
src/mesa/main/teximage.c | 62 +---
1 file changed, 43 insertions(+), 19 deletions(-)
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 58b7f27..26a6c21 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -1102,6 +1102,32 @@ _mesa_legal_texture_dimensions(struct gl_context *ctx,
GLenum target,
}
}
+static bool
+error_check_subtexture_negative_dimensions(struct gl_context *ctx,
+ GLuint dims,
+ GLsizei subWidth,
+ GLsizei subHeight,
+ GLsizei subDepth,
+ const char *func)
+{
+ /* Check size */
+ if (subWidth < 0) {
+ _mesa_error(ctx, GL_INVALID_VALUE, "%s(width=%d)", func, subWidth);
+ return true;
+ }
+
+ if (dims > 1 && subHeight < 0) {
+ _mesa_error(ctx, GL_INVALID_VALUE, "%s(height=%d)", func, subHeight);
+ return true;
+ }
+
+ if (dims > 2 && subDepth < 0) {
+ _mesa_error(ctx, GL_INVALID_VALUE, "%s(depth=%d)", func, subDepth);
+ return true;
+ }
+
+ return false;
+}
/**
* Do error checking of xoffset, yoffset, zoffset, width, height and depth
@@ -1119,25 +1145,6 @@ error_check_subtexture_dimensions(struct gl_context
*ctx, GLuint dims,
const GLenum target = destImage->TexObject->Target;
GLuint bw, bh, bd;
- /* Check size */
- if (subWidth < 0) {
- _mesa_error(ctx, GL_INVALID_VALUE,
- "%s(width=%d)", func, subWidth);
- return GL_TRUE;
- }
-
- if (dims > 1 && subHeight < 0) {
- _mesa_error(ctx, GL_INVALID_VALUE,
- "%s(height=%d)", func, subHeight);
- return GL_TRUE;
- }
-
- if (dims > 2 && subDepth < 0) {
- _mesa_error(ctx, GL_INVALID_VALUE,
- "%s(depth=%d)", func, subDepth);
- return GL_TRUE;
- }
-
/* check xoffset and width */
if (xoffset < - (GLint) destImage->Border) {
_mesa_error(ctx, GL_INVALID_VALUE, "%s(xoffset)", func);
@@ -2104,6 +2111,12 @@ texsubimage_error_check(struct gl_context *ctx, GLuint
dimensions,
return GL_TRUE;
}
+ if (error_check_subtexture_negative_dimensions(ctx, dimensions,
+ width, height, depth,
+ callerName)) {
+ return GL_TRUE;
+ }
+
texImage = _mesa_select_tex_image(texObj, target, level);
if (!texImage) {
/* non-existant texture level */
@@ -2497,6 +2510,11 @@ copytexsubimage_error_check(struct gl_context *ctx,
GLuint dimensions,
return GL_TRUE;
}
+ if (error_check_subtexture_negative_dimensions(ctx, dimensions,
+ width, height, 1, caller)) {
+ return GL_TRUE;
+ }
+
if (error_check_subtexture_dimensions(ctx, dimensions, texImage,
xoffset, yoffset, zoffset,
width, height, 1, caller)) {
@@ -4387,6 +4405,12 @@ compressed_subtexture_error_check(struct gl_context
*ctx, GLint dims,
return GL_TRUE;
}
+ if (error_check_subtexture_negative_dimensions(ctx, dims,
+ width, height, depth,
+ callerName)) {
+ return GL_TRUE;
+ }
+
if (error_check_subtexture_dimensions(ctx, dims,
texImage, xoffset, yoffset, zoffset,
width, height, depth,
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): util: update some assertions in util_resource_copy_region()
Module: Mesa Branch: master Commit: cf9bb9acac0fd3b5926da8102bda33171a906a6b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cf9bb9acac0fd3b5926da8102bda33171a906a6b Author: Brian Paul Date: Mon Jun 13 09:54:12 2016 -0600 util: update some assertions in util_resource_copy_region() To cope with copies of compressed images which are not multiples of the block size. Suggested by Jose. Reviewed-by: Jose Fonseca Reviewed-by: Roland Scheidegger --- src/gallium/auxiliary/util/u_surface.c | 12 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/gallium/auxiliary/util/u_surface.c b/src/gallium/auxiliary/util/u_surface.c index e48e47c..b9d2da0 100644 --- a/src/gallium/auxiliary/util/u_surface.c +++ b/src/gallium/auxiliary/util/u_surface.c @@ -332,12 +332,16 @@ util_resource_copy_region(struct pipe_context *pipe, /* check that region boxes are block aligned */ assert(src_box.x % src_bw == 0); assert(src_box.y % src_bh == 0); - assert(src_box.width % src_bw == 0 || src_box.width < src_bw); - assert(src_box.height % src_bh == 0 || src_box.height < src_bh); + assert(src_box.width % src_bw == 0 || + src_box.x + src_box.width == minify(src->width0, src_level, src_bw)); + assert(src_box.height % src_bh == 0 || + src_box.y + src_box.height == minify(src->height0, src_level, src_bh)); assert(dst_box.x % dst_bw == 0); assert(dst_box.y % dst_bh == 0); - assert(dst_box.width % dst_bw == 0 || dst_box.width < dst_bw); - assert(dst_box.height % dst_bh == 0 || dst_box.height < src_bh); + assert(dst_box.width % dst_bw == 0 || + dst_box.x + dst_box.width == minify(dst->width0, dst_level, dst_bw)); + assert(dst_box.height % dst_bh == 0 || + dst_box.y + dst_box.height == minify(dst->height0, dst_level, dst_bh)); /* check that region boxes are not out of bounds */ assert(src_box.x + src_box.width <= ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Don't leak scratch BOs for TCS/TES.
Module: Mesa Branch: master Commit: 667e5cec760d1908af73a40de28c53848b5b70a0 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=667e5cec760d1908af73a40de28c53848b5b70a0 Author: Kenneth Graunke Date: Sun Jun 12 15:44:55 2016 -0700 i965: Don't leak scratch BOs for TCS/TES. These need to be freed too. Cc: "12.0" Signed-off-by: Kenneth Graunke --- src/mesa/drivers/dri/i965/brw_context.c | 4 1 file changed, 4 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 7bbc128..a5c6581 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -1100,6 +1100,10 @@ intelDestroyContext(__DRIcontext * driContextPriv) drm_intel_bo_unreference(brw->curbe.curbe_bo); if (brw->vs.base.scratch_bo) drm_intel_bo_unreference(brw->vs.base.scratch_bo); + if (brw->tcs.base.scratch_bo) + drm_intel_bo_unreference(brw->tcs.base.scratch_bo); + if (brw->tes.base.scratch_bo) + drm_intel_bo_unreference(brw->tes.base.scratch_bo); if (brw->gs.base.scratch_bo) drm_intel_bo_unreference(brw->gs.base.scratch_bo); if (brw->wm.base.scratch_bo) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Fix encode_slm_size() to take a generation, not a device info.
Module: Mesa
Branch: master
Commit: 5a0d294d38505ae61293ae1a9184e1b3228ef2af
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5a0d294d38505ae61293ae1a9184e1b3228ef2af
Author: Kenneth Graunke
Date: Mon Jun 13 12:18:23 2016 -0700
i965: Fix encode_slm_size() to take a generation, not a device info.
In the Vulkan driver, we have the generation number (a compile time
constant) but not necessarily the brw_device_info struct. I meant
to rework the function to take a generation number instead of a
brw_device_info pointer to accomodate this. But I forgot, and left
it taking a brw_device_info pointer, while making Vulkan pass the
generation number (8, 9, ...) directly. This led to crashes.
Brown paper bag fix for commit 87d062a94080373995170f51063a9649.
Cc: "12.0"
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96504
Signed-off-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_compiler.h | 4 ++--
src/mesa/drivers/dri/i965/gen7_cs_state.c | 3 ++-
2 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_compiler.h
b/src/mesa/drivers/dri/i965/brw_compiler.h
index c944eff..10e9f47 100644
--- a/src/mesa/drivers/dri/i965/brw_compiler.h
+++ b/src/mesa/drivers/dri/i965/brw_compiler.h
@@ -833,7 +833,7 @@ brw_compile_cs(const struct brw_compiler *compiler, void
*log_data,
char **error_str);
static inline uint32_t
-encode_slm_size(const struct brw_device_info *devinfo, uint32_t bytes)
+encode_slm_size(unsigned gen, uint32_t bytes)
{
uint32_t slm_size = 0;
@@ -852,7 +852,7 @@ encode_slm_size(const struct brw_device_info *devinfo,
uint32_t bytes)
/* Shared Local Memory Size is specified as powers of two. */
slm_size = util_next_power_of_two(bytes);
- if (devinfo->gen >= 9) {
+ if (gen >= 9) {
/* Use a minimum of 1kB; turn an exponent of 10 (1024 kB) into 1. */
slm_size = ffs(MAX2(slm_size, 1024)) - 10;
} else {
diff --git a/src/mesa/drivers/dri/i965/gen7_cs_state.c
b/src/mesa/drivers/dri/i965/gen7_cs_state.c
index ba558a6..ff308e6 100644
--- a/src/mesa/drivers/dri/i965/gen7_cs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_cs_state.c
@@ -164,7 +164,8 @@ brw_upload_cs_state(struct brw_context *brw)
SET_FIELD(cs_prog_data->threads, MEDIA_GPGPU_THREAD_COUNT);
assert(cs_prog_data->threads <= brw->max_cs_threads);
- const uint32_t slm_size = encode_slm_size(devinfo, prog_data->total_shared);
+ const uint32_t slm_size =
+ encode_slm_size(devinfo->gen, prog_data->total_shared);
desc[dw++] =
SET_FIELD(cs_prog_data->uses_barrier, MEDIA_BARRIER_ENABLE) |
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv/pipeline: Don't dereference NULL dynamic state pointers
Module: Mesa
Branch: master
Commit: a4a59172482d50318a5ae7f99021bcf0125e0f53
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4a59172482d50318a5ae7f99021bcf0125e0f53
Author: Nanley Chery
Date: Thu Jun 9 14:48:00 2016 -0700
anv/pipeline: Don't dereference NULL dynamic state pointers
Add guards to prevent dereferencing NULL dynamic pipeline state. Asserts
of pCreateInfo members are moved to the earliest points at which they
should not be NULL.
This fixes a segfault seen in the McNopper demo, VKTS_Example09.
v3 (Jason Ekstrand):
- Fix disabled rasterization check
- Revert opaque detection of color attachment usage
Signed-off-by: Nanley Chery
Reviewed-by: Jason Ekstrand
Cc: "12.0"
---
src/intel/vulkan/anv_pipeline.c | 70 -
1 file changed, 48 insertions(+), 22 deletions(-)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index ae03787..60b7c6b 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -979,18 +979,27 @@ copy_non_dynamic_state(struct anv_pipeline *pipeline,
struct anv_dynamic_state *dynamic = &pipeline->dynamic_state;
- dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
- if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
- typed_memcpy(dynamic->viewport.viewports,
- pCreateInfo->pViewportState->pViewports,
- pCreateInfo->pViewportState->viewportCount);
- }
+ /* Section 9.2 of the Vulkan 1.0.15 spec says:
+*
+*pViewportState is [...] NULL if the pipeline
+*has rasterization disabled.
+*/
+ if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
+ assert(pCreateInfo->pViewportState);
+
+ dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
+ if (states & (1 << VK_DYNAMIC_STATE_VIEWPORT)) {
+ typed_memcpy(dynamic->viewport.viewports,
+ pCreateInfo->pViewportState->pViewports,
+ pCreateInfo->pViewportState->viewportCount);
+ }
- dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
- if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
- typed_memcpy(dynamic->scissor.scissors,
- pCreateInfo->pViewportState->pScissors,
- pCreateInfo->pViewportState->scissorCount);
+ dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
+ if (states & (1 << VK_DYNAMIC_STATE_SCISSOR)) {
+ typed_memcpy(dynamic->scissor.scissors,
+ pCreateInfo->pViewportState->pScissors,
+ pCreateInfo->pViewportState->scissorCount);
+ }
}
if (states & (1 << VK_DYNAMIC_STATE_LINE_WIDTH)) {
@@ -1008,10 +1017,27 @@ copy_non_dynamic_state(struct anv_pipeline *pipeline,
pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
}
- if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS)) {
+ /* Section 9.2 of the Vulkan 1.0.15 spec says:
+*
+*pColorBlendState is [...] NULL if the pipeline has rasterization
+*disabled or if the subpass of the render pass the pipeline is
+*created against does not use any color attachments.
+*/
+ bool uses_color_att = false;
+ for (unsigned i = 0; i < subpass->color_count; ++i) {
+ if (subpass->color_attachments[i] != VK_ATTACHMENT_UNUSED) {
+ uses_color_att = true;
+ break;
+ }
+ }
+
+ if (uses_color_att &&
+ !pCreateInfo->pRasterizationState->rasterizerDiscardEnable) {
assert(pCreateInfo->pColorBlendState);
- typed_memcpy(dynamic->blend_constants,
- pCreateInfo->pColorBlendState->blendConstants, 4);
+
+ if (states & (1 << VK_DYNAMIC_STATE_BLEND_CONSTANTS))
+ typed_memcpy(dynamic->blend_constants,
+ pCreateInfo->pColorBlendState->blendConstants, 4);
}
/* If there is no depthstencil attachment, then don't read
@@ -1020,14 +1046,17 @@ copy_non_dynamic_state(struct anv_pipeline *pipeline,
* no need to override the depthstencil defaults in
* anv_pipeline::dynamic_state when there is no depthstencil attachment.
*
-* From the Vulkan spec (20 Oct 2015, git-aa308cb):
+* Section 9.2 of the Vulkan 1.0.15 spec says:
*
-*pDepthStencilState [...] may only be NULL if renderPass and subpass
-*specify a subpass that has no depth/stencil attachment.
+*pDepthStencilState is [...] NULL if the pipeline has rasterization
+*disabled or if the subpass of the render pass the pipeline is created
+*against does not use a depth/stencil attachment.
*/
- if (subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
+ if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
+ subpass->depth_stencil_attachment != VK_ATTACHMENT_UNUSED) {
+ assert(pCreateInfo->pDepthStencilState);
+
if (states & (1 << VK_DYNAMIC_STATE_DE
Mesa (master): anv: Document and rename anv_pipeline_init_dynamic_state()
Module: Mesa
Branch: master
Commit: a0d84a9ef9df69606a928cf7dca8f2b80dea1c36
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0d84a9ef9df69606a928cf7dca8f2b80dea1c36
Author: Nanley Chery
Date: Thu Jun 9 12:12:29 2016 -0700
anv: Document and rename anv_pipeline_init_dynamic_state()
To reduce confusion, clarify that the state being copied is not dynamic.
This agrees with the Vulkan spec's usage of the term. Various sections
specify that the various pipeline state which have VkDynamicState enums
(e.g. viewport, scissor, etc.) may or may not be dynamic.
Signed-off-by: Nanley Chery
Reviewed-by: Jason Ekstrand
Cc: "12.0"
---
src/intel/vulkan/anv_pipeline.c | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index 959fbbd..ae03787 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -947,9 +947,22 @@ anv_compute_urb_partition(struct anv_pipeline *pipeline)
pipeline->urb.entries[MESA_SHADER_TESS_EVAL] = 0;
}
+/**
+ * Copy pipeline state not marked as dynamic.
+ * Dynamic state is pipeline state which hasn't been provided at pipeline
+ * creation time, but is dynamically provided afterwards using various
+ * vkCmdSet* functions.
+ *
+ * The set of state considered "non_dynamic" is determined by the pieces of
+ * state that have their corresponding VkDynamicState enums omitted from
+ * VkPipelineDynamicStateCreateInfo::pDynamicStates.
+ *
+ * @param[out] pipelineDestination non_dynamic state.
+ * @param[in] pCreateInfo Source of non_dynamic state to be copied.
+ */
static void
-anv_pipeline_init_dynamic_state(struct anv_pipeline *pipeline,
-const VkGraphicsPipelineCreateInfo
*pCreateInfo)
+copy_non_dynamic_state(struct anv_pipeline *pipeline,
+ const VkGraphicsPipelineCreateInfo *pCreateInfo)
{
anv_cmd_dirty_mask_t states = ANV_CMD_DIRTY_DYNAMIC_ALL;
ANV_FROM_HANDLE(anv_render_pass, pass, pCreateInfo->renderPass);
@@ -1122,7 +1135,7 @@ anv_pipeline_init(struct anv_pipeline *pipeline,
pipeline->batch.end = pipeline->batch.start + sizeof(pipeline->batch_data);
pipeline->batch.relocs = &pipeline->batch_relocs;
- anv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
+ copy_non_dynamic_state(pipeline, pCreateInfo);
pipeline->use_repclear = extra && extra->use_repclear;
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nvc0/ir: clamp the UBO index for compute on Kepler
Module: Mesa
Branch: master
Commit: 7f257abc1bdd153b3981efffc3f201e1ea5fe843
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f257abc1bdd153b3981efffc3f201e1ea5fe843
Author: Samuel Pitoiset
Date: Mon Jun 13 17:13:28 2016 +0200
nvc0/ir: clamp the UBO index for compute on Kepler
We already check that the address is not "too far", but we should also
clamp the UBO index in order to avoid looking at the wrong place in the
driver cb. This is a pretty rare situation though.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Ilia Mirkin
Cc: "12.0"
---
src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index cb82216..71013eb 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -2183,7 +2183,15 @@ NVC0LoweringPass::handleLDST(Instruction *i)
int8_t fileIndex = i->getSrc(0)->reg.fileIndex - 1;
Value *ind = i->getIndirect(0, 1);
- // TODO: clamp the offset to the maximum number of const buf.
+ if (ind) {
+// Clamp the UBO index when an indirect access is used to avoid
+// loading information from the wrong place in the driver cb.
+ind = bld.mkOp2v(OP_MIN, TYPE_U32, ind,
+ bld.mkOp2v(OP_ADD, TYPE_U32, bld.getSSA(),
+ind, bld.loadImm(NULL, fileIndex)),
+ bld.loadImm(NULL, 12));
+ }
+
if (i->src(0).isIndirect(1)) {
Value *offset = bld.loadImm(NULL, i->getSrc(0)->reg.data.offset +
typeSizeof(i->sType));
Value *ptr = loadUboInfo64(ind, fileIndex * 16);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: enable scratch coalescing
Module: Mesa
Branch: master
Commit: 6e1b12c7881fe663cb500cb2f7374f4862bae179
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e1b12c7881fe663cb500cb2f7374f4862bae179
Author: Marek Olšák
Date: Wed Jun 8 13:21:25 2016 +0200
radeonsi: enable scratch coalescing
This makes one particular compute shader 8x faster.
Latest LLVM git is required.
Reviewed-by: Nicolai Hähnle
---
src/gallium/drivers/radeonsi/si_shader.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 754b4af..f2bd337 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -5903,8 +5903,16 @@ void si_shader_apply_scratch_relocs(struct si_context
*sctx,
unsigned i;
uint32_t scratch_rsrc_dword0 = scratch_va;
uint32_t scratch_rsrc_dword1 =
- S_008F04_BASE_ADDRESS_HI(scratch_va >> 32)
- | S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
+ S_008F04_BASE_ADDRESS_HI(scratch_va >> 32);
+
+ /* Enable scratch coalescing if LLVM sets ELEMENT_SIZE & INDEX_STRIDE
+* correctly.
+*/
+ if (HAVE_LLVM >= 0x0309)
+ scratch_rsrc_dword1 |= S_008F04_SWIZZLE_ENABLE(1);
+ else
+ scratch_rsrc_dword1 |=
+ S_008F04_STRIDE(config->scratch_bytes_per_wave / 64);
for (i = 0 ; i < shader->binary.reloc_count; i++) {
const struct radeon_shader_reloc *reloc =
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): 22 new commits
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c0f841e5de27d01312f8857641668ca439b1ab1 Author: Jimmy Berry Date: Thu Apr 21 15:05:41 2016 +0200 st/va: hardlink driver instances to gallium_drv_video.so Removes the need to set LIBVA_DRIVER_NAME=gallium for supported targets and is consistent with vdpau and general gallium drivers. Note: some versions of libva can detect the gallium name and use the backend. Although that behaviour seems inconsistent since it only works for some platforms/backends. Cc: "12.0" Reviewed-by: Emil Velikov URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1fb4179f927442354f93dfc8494f0236e50af838 Author: Jan Vesely Date: Thu Jun 9 23:01:46 2016 -0400 vl: Fix trivial sign compare warnings v2: add whitepace fixes Signed-off-by: Jan Vesely Acked-by: Jose Fonseca [Emil Velikov: squash a few more whitespace issues] Reviewed-by: Emil Velikov URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=112e988329b6af817b4892b530f703e7997b1d7d Author: Rob Herring Date: Tue Jun 7 18:27:34 2016 -0500 Android: move libdrm settings to top-level Android.common.mk Fix warnings like these due to HAVE_LIBDRM being inconsistently defined: external/libdrm/include/drm/drm.h:839:30: warning: redefinition of typedef 'drm_clip_rect_t' is a C11 feature [-Wtypedef-redefinition] typedef struct drm_clip_rect drm_clip_rect_t; HAVE_LIBDRM needs to be set project wide to fix this. This change also harmlessly links libdrm with everything, but simplifies the makefiles a bit. Signed-off-by: Rob Herring Acked-by: Emil Velikov URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=54e550ab8ad7ca5ebd24edbbb3f96e5412209ba9 Author: Rob Herring Date: Tue Jun 7 18:27:33 2016 -0500 Android: disable some noisy warnings Turn off warnings for -Wpointer-arith, -Wno-missing-field-initializers, -Wno-initializer-overrides, and -Wno-mismatched-tags. These are all deemed pointless, on purpose or no plans to fix. Signed-off-by: Rob Herring Acked-by: Emil Velikov URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=db8790c0dadffb6c88a0939bd34eca2b8e75d2e0 Author: Emil Velikov Date: Tue Jun 7 17:33:48 2016 +0100 st/mesa: inline _mesa_create_context() into its only caller Inline the function into it's only caller. This way it's more obvious how the classic and gallium drivers (st/mesa) use _mesa_initialize_context. Signed-off-by: Emil Velikov Reviewed-by: Ian Romanick URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4fa8bf819fd7189ab1d41e82b79dc007f7a7300 Author: Emil Velikov Date: Tue Jun 7 17:33:47 2016 +0100 st/mesa: remove unneeded break from st_api_create_context() We have return on the previous line, thus the break will never be reached. Signed-off-by: Emil Velikov Reviewed-by: Ian Romanick URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6406bc15926b1a2f6ad62dc4a3770b0d4f484e7d Author: Emil Velikov Date: Tue Jun 7 17:33:46 2016 +0100 st/mesa: use c99 initializer for st_gl_api Signed-off-by: Emil Velikov Acked-by: Ian Romanick URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=15bc7856bf1b328cc403f464ace979b3a0afa892 Author: Emil Velikov Date: Tue Jun 7 17:33:45 2016 +0100 gallium: remove st_api::get_proc_address hook It has been unused for a long time, plus makes the gallium dri modules require an extra glapi symbol relative to their classic counterparts. Signed-off-by: Emil Velikov URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=23a7fca6aa07df1e074f7cf866dc9d2045fe0417 Author: Emil Velikov Date: Mon Jun 13 14:27:54 2016 +0100 mesa: remove _mesa_init_get_hash() The actual code of the function print_table_stats() is guarded by a ifdef GET_DEBUG, which was not been defined in years. The last fix in 2013 (7db6b5aa91a) indicates that it's rarely used/tested. Since the issue has gone unnoticed for a whole year (broken with 2ad4a475474). Let's remove it for now. We can always revive it at a later stage. Signed-off-by: Emil Velikov Reviewed-by: Ian Romanick URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b81685eb32d7fd51f12cfdbac8b5f6046c416304 Author: Emil Velikov Date: Tue Jun 7 17:33:41 2016 +0100 mesa: kill off _mesa_do_init_remap_table() ... and inline its contents in _mesa_init_remap_table(). Signed-off-by: Emil Velikov Reviewed-by: Ian Romanick URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bfbf286f7d607f1add1cedd2e2717e249fb45d0f Author: Emil Velikov Date: Tue Jun 7 17:33:40 2016 +0100 mesa: use native types when possible All of the functions and related data is internal, so there's no point if using the
Mesa (master): gallivm: Fix trivial sign warnings
Module: Mesa
Branch: master
Commit: ace70aedcf8b29380a17f68a994b18f60976bca6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ace70aedcf8b29380a17f68a994b18f60976bca6
Author: Jan Vesely
Date: Thu Jun 2 20:03:14 2016 -0400
gallivm: Fix trivial sign warnings
v2: include whitespace fixes
Signed-off-by: Jan Vesely
Reviewed-by: Jose Fonseca
---
src/gallium/auxiliary/gallivm/lp_bld_conv.c | 4 ++--
src/gallium/auxiliary/gallivm/lp_bld_logic.c| 10 ++
src/gallium/auxiliary/gallivm/lp_bld_pack.c | 2 +-
src/gallium/auxiliary/gallivm/lp_bld_printf.c | 7 +++
src/gallium/auxiliary/gallivm/lp_bld_swizzle.c | 2 +-
src/gallium/auxiliary/gallivm/lp_bld_tgsi.c | 6 +++---
src/gallium/auxiliary/gallivm/lp_bld_tgsi.h | 2 +-
src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c | 10 +-
8 files changed, 22 insertions(+), 21 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_conv.c
b/src/gallium/auxiliary/gallivm/lp_bld_conv.c
index 7cf0dee..69d24a5 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_conv.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_conv.c
@@ -311,7 +311,7 @@ lp_build_clamped_float_to_unsigned_norm(struct
gallivm_state *gallivm,
* important, we also get exact results for 0.0 and 1.0.
*/
- unsigned n = MIN2(src_type.width - 1, dst_width);
+ unsigned n = MIN2(src_type.width - 1u, dst_width);
double scale = (double)(1ULL << n);
unsigned lshift = dst_width - n;
@@ -445,7 +445,7 @@ int lp_build_conv_auto(struct gallivm_state *gallivm,
unsigned num_srcs,
LLVMValueRef *dst)
{
- int i;
+ unsigned i;
int num_dsts = num_srcs;
if (src_type.floating == dst_type->floating &&
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_logic.c
b/src/gallium/auxiliary/gallivm/lp_bld_logic.c
index a26cc48..14bf236 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_logic.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_logic.c
@@ -88,8 +88,6 @@ lp_build_compare_ext(struct gallivm_state *gallivm,
LLVMValueRef cond;
LLVMValueRef res;
- assert(func >= PIPE_FUNC_NEVER);
- assert(func <= PIPE_FUNC_ALWAYS);
assert(lp_check_value(type, a));
assert(lp_check_value(type, b));
@@ -98,6 +96,9 @@ lp_build_compare_ext(struct gallivm_state *gallivm,
if(func == PIPE_FUNC_ALWAYS)
return ones;
+ assert(func > PIPE_FUNC_NEVER);
+ assert(func < PIPE_FUNC_ALWAYS);
+
if(type.floating) {
LLVMRealPredicate op;
switch(func) {
@@ -176,8 +177,6 @@ lp_build_compare(struct gallivm_state *gallivm,
LLVMValueRef zeros = LLVMConstNull(int_vec_type);
LLVMValueRef ones = LLVMConstAllOnes(int_vec_type);
- assert(func >= PIPE_FUNC_NEVER);
- assert(func <= PIPE_FUNC_ALWAYS);
assert(lp_check_value(type, a));
assert(lp_check_value(type, b));
@@ -186,6 +185,9 @@ lp_build_compare(struct gallivm_state *gallivm,
if(func == PIPE_FUNC_ALWAYS)
return ones;
+ assert(func > PIPE_FUNC_NEVER);
+ assert(func < PIPE_FUNC_ALWAYS);
+
#if defined(PIPE_ARCH_X86) || defined(PIPE_ARCH_X86_64)
/*
* There are no unsigned integer comparison instructions in SSE.
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_pack.c
b/src/gallium/auxiliary/gallivm/lp_bld_pack.c
index 35b4c58..b0e76e6 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_pack.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_pack.c
@@ -236,7 +236,7 @@ lp_build_concat_n(struct gallivm_state *gallivm,
unsigned num_dsts)
{
int size = num_srcs / num_dsts;
- int i;
+ unsigned i;
assert(num_srcs >= num_dsts);
assert((num_srcs % size) == 0);
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_printf.c
b/src/gallium/auxiliary/gallivm/lp_bld_printf.c
index 14131b3..575ebdf 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_printf.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_printf.c
@@ -155,10 +155,10 @@ lp_build_print_value(struct gallivm_state *gallivm,
}
-static int
+static unsigned
lp_get_printf_arg_count(const char *fmt)
{
- int count =0;
+ unsigned count = 0;
const char *p = fmt;
int c;
@@ -195,8 +195,7 @@ lp_build_printf(struct gallivm_state *gallivm,
{
LLVMValueRef params[50];
va_list arglist;
- int argcount;
- int i;
+ unsigned argcount, i;
argcount = lp_get_printf_arg_count(fmt);
assert(ARRAY_SIZE(params) >= argcount + 1);
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_swizzle.c
b/src/gallium/auxiliary/gallivm/lp_bld_swizzle.c
index 92f387d..5a97c48 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_swizzle.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_swizzle.c
@@ -467,7 +467,7 @@ lp_build_swizzle_aos(struct lp_build_context *bld,
LLVMValueRef res;
struct lp_type type4;
unsigned cond = 0;
- unsigned chan;
+ int chan;
int shift;
/*
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
b/src/gallium/auxiliary/gallivm/
Mesa (master): st/va: use proper temp pipe_video_buffer template
Module: Mesa
Branch: master
Commit: a04804746f6d05cda125a0778160d62c73a2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a04804746f6d05cda125a0778160d62c73a2
Author: Julien Isorce
Date: Thu Jun 2 15:03:34 2016 +0100
st/va: use proper temp pipe_video_buffer template
Instead of changing the format on the existing template
which makes error handling not nice and confuses coverity.
CoverityID: 1337953
Signed-off-by: Julien Isorce
Reviewed-by: Christian König
---
src/gallium/state_trackers/va/image.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/gallium/state_trackers/va/image.c
b/src/gallium/state_trackers/va/image.c
index 92d014c..1b956e3 100644
--- a/src/gallium/state_trackers/va/image.c
+++ b/src/gallium/state_trackers/va/image.c
@@ -473,19 +473,19 @@ vlVaPutImage(VADriverContextP ctx, VASurfaceID surface,
VAImageID image,
if (format != surf->buffer->buffer_format) {
struct pipe_video_buffer *tmp_buf;
- enum pipe_format old_surf_format = surf->templat.buffer_format;
+ struct pipe_video_buffer templat = surf->templat;
- surf->templat.buffer_format = format;
- tmp_buf = drv->pipe->create_video_buffer(drv->pipe, &surf->templat);
+ templat.buffer_format = format;
+ tmp_buf = drv->pipe->create_video_buffer(drv->pipe, &templat);
if (!tmp_buf) {
- surf->templat.buffer_format = old_surf_format;
pipe_mutex_unlock(drv->mutex);
return VA_STATUS_ERROR_ALLOCATION_FAILED;
}
surf->buffer->destroy(surf->buffer);
surf->buffer = tmp_buf;
+ surf->templat.buffer_format = format;
}
views = surf->buffer->get_sampler_view_planes(surf->buffer);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): st/va: it is valid to release the VABuffer of an exported resource
Module: Mesa
Branch: master
Commit: 6c43e0016e344de3d7e82b098992cdfecbff2ab2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6c43e0016e344de3d7e82b098992cdfecbff2ab2
Author: Julien Isorce
Date: Thu Jun 2 15:03:01 2016 +0100
st/va: it is valid to release the VABuffer of an exported resource
pipe_resource_reference(&res, NULL) will decrement reference counting,
i.e. p_atomic_dec(res->count). But the va surface still has the initial
reference since it has created the resource. So calling vaDestroyImage
on a derived image calls VaDestroyBuffer but the decrementation won't
reach 0. It is just wrong for vlVaDestroyBuffer to rely on the
export_refcount flag. Finally the vaapi intel driver has the same logic.
Signed-off-by: Julien Isorce
Reviewed-by: Christian König
---
src/gallium/state_trackers/va/buffer.c | 8 +---
1 file changed, 1 insertion(+), 7 deletions(-)
diff --git a/src/gallium/state_trackers/va/buffer.c
b/src/gallium/state_trackers/va/buffer.c
index 2fd8661..7d3167b 100644
--- a/src/gallium/state_trackers/va/buffer.c
+++ b/src/gallium/state_trackers/va/buffer.c
@@ -192,14 +192,8 @@ vlVaDestroyBuffer(VADriverContextP ctx, VABufferID buf_id)
return VA_STATUS_ERROR_INVALID_BUFFER;
}
- if (buf->derived_surface.resource) {
- if (buf->export_refcount > 0) {
- pipe_mutex_unlock(drv->mutex);
- return VA_STATUS_ERROR_INVALID_BUFFER;
- }
-
+ if (buf->derived_surface.resource)
pipe_resource_reference(&buf->derived_surface.resource, NULL);
- }
FREE(buf->data);
FREE(buf);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
