Mesa (master): nv50/ir: add missing string for SV_WORK_DIM

2016-07-14 Thread Samuel Pitoiset 
Module: Mesa
Branch: master
Commit: ea6b236ab1a53cc0a616088aec4a0ec4d804f77d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea6b236ab1a53cc0a616088aec4a0ec4d804f77d

Author: Samuel Pitoiset 
Date:   Tue Jul 12 14:17:44 2016 +0200

nv50/ir: add missing string for SV_WORK_DIM

Fixes: 2aa1197 ("nouveau: Add support for SV_WORK_DIM")
Signed-off-by: Samuel Pitoiset 
Reviewed-by: Ilia Mirkin 
Reviewed-by: Hans de Goede 

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
index 6469f71..ae0dd78 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_print.cpp
@@ -312,6 +312,7 @@ static const char *SemanticStr[SV_LAST + 1] =
"BASEVERTEX",
"BASEINSTANCE",
"DRAWID",
+   "WORK_DIM",
"?",
"(INVALID)"
 };

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Mesa (master): Revert "radeon/llvm: Use alloca instructions for larger arrays"

2016-07-14 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: f84e9d749fbb6da73a60fb70e6725db773c9b8f8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f84e9d749fbb6da73a60fb70e6725db773c9b8f8

Author: Marek Olšák 
Date:   Thu Jul 14 22:07:46 2016 +0200

Revert "radeon/llvm: Use alloca instructions for larger arrays"

This reverts commit 513fccdfb68e6a71180e21827f071617c93fd09b.

Bioshock Infinite hangs with that.

---

 src/gallium/drivers/radeon/radeon_llvm.h   |   7 +-
 .../drivers/radeon/radeon_setup_tgsi_llvm.c| 167 +++--
 2 files changed, 25 insertions(+), 149 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_llvm.h 
b/src/gallium/drivers/radeon/radeon_llvm.h
index 13f3336..d456a92 100644
--- a/src/gallium/drivers/radeon/radeon_llvm.h
+++ b/src/gallium/drivers/radeon/radeon_llvm.h
@@ -50,11 +50,6 @@ struct radeon_llvm_loop {
LLVMBasicBlockRef endloop_block;
 };
 
-struct radeon_llvm_array {
-   struct tgsi_declaration_range range;
-   LLVMValueRef alloca;
-};
-
 struct radeon_llvm_context {
struct lp_build_tgsi_soa_context soa;
 
@@ -101,7 +96,7 @@ struct radeon_llvm_context {
unsigned loop_depth;
unsigned loop_depth_max;
 
-   struct radeon_llvm_array *arrays;
+   struct tgsi_declaration_range *arrays;
 
LLVMValueRef main_fn;
LLVMTypeRef return_type;
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c 
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index d382496..ed8fd30 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -112,25 +112,11 @@ static LLVMValueRef emit_swizzle(struct 
lp_build_tgsi_context *bld_base,
 
 static struct tgsi_declaration_range
 get_array_range(struct lp_build_tgsi_context *bld_base,
-   unsigned File, unsigned reg_index,
-   const struct tgsi_ind_register *reg)
+   unsigned File, const struct tgsi_ind_register *reg)
 {
struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base);
 
-   if (!reg) {
-   unsigned i;
-   unsigned num_arrays = 
bld_base->info->array_max[TGSI_FILE_TEMPORARY];
-   for (i = 0; i < num_arrays; i++) {
-   const struct tgsi_declaration_range *range =
-   >arrays[i].range;
-
-   if (reg_index >= range->First && reg_index <= 
range->Last) {
-   return ctx->arrays[i].range;
-   }
-   }
-   }
-
-   if (File != TGSI_FILE_TEMPORARY || !reg || reg->ArrayID == 0 ||
+   if (File != TGSI_FILE_TEMPORARY || reg->ArrayID == 0 ||
reg->ArrayID > bld_base->info->array_max[TGSI_FILE_TEMPORARY]) {
struct tgsi_declaration_range range;
range.First = 0;
@@ -138,30 +124,7 @@ get_array_range(struct lp_build_tgsi_context *bld_base,
return range;
}
 
-   return ctx->arrays[reg->ArrayID - 1].range;
-}
-
-static LLVMValueRef get_alloca_for_array(struct lp_build_tgsi_context 
*bld_base,
-unsigned file,
-unsigned index)
-{
-   unsigned i;
-   unsigned num_arrays;
-   struct radeon_llvm_context *ctx = radeon_llvm_context(bld_base);
-
-   if (file != TGSI_FILE_TEMPORARY)
-   return NULL;
-
-   num_arrays = bld_base->info->array_max[TGSI_FILE_TEMPORARY];
-   for (i = 0; i < num_arrays; i++) {
-   const struct tgsi_declaration_range *range =
-   >arrays[i].range;
-
-   if (index >= range->First && index <= range->Last) {
-   return ctx->arrays[i].alloca;
-   }
-   }
-   return NULL;
+   return ctx->arrays[reg->ArrayID - 1];
 }
 
 static LLVMValueRef
@@ -171,9 +134,6 @@ emit_array_index(struct lp_build_tgsi_soa_context *bld,
 {
struct gallivm_state *gallivm = bld->bld_base.base.gallivm;
 
-   if (!reg) {
-   return lp_build_const_int32(gallivm, offset);
-   }
LLVMValueRef addr = LLVMBuildLoad(gallivm->builder, 
bld->addr[reg->Index][reg->Swizzle], "");
return LLVMBuildAdd(gallivm->builder, addr, 
lp_build_const_int32(gallivm, offset), "");
 }
@@ -221,7 +181,7 @@ emit_array_fetch(struct lp_build_tgsi_context *bld_base,
tmp_reg.Register.Index = i + range.First;
LLVMValueRef temp = radeon_llvm_emit_fetch(bld_base, _reg, 
type, swizzle);
result = LLVMBuildInsertElement(builder, result, temp,
-   lp_build_const_int32(gallivm, i), "array_vector");
+   lp_build_const_int32(gallivm, i), "");
}
return result;
 }
@@ -235,35 +195,13 @@ load_value_from_array(struct lp_build_tgsi_context 
*bld_base,

Mesa (master): r600,compute: Reserve vtx 3 for kernel arguments

2016-07-14 Thread Jan Vesely 
Module: Mesa
Branch: master
Commit: 489bb5473b96a22ae445107297b66bc38b4701f7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=489bb5473b96a22ae445107297b66bc38b4701f7

Author: Jan Vesely 
Date:   Sat Jun 25 22:06:09 2016 -0400

r600,compute: Reserve vtx 3 for kernel arguments

Using vtx 0 does not work for dynamic offsets.

v2: add explanatory comment

Signed-off-by: Jan Vesely 
Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/r600/evergreen_compute.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/r600/evergreen_compute.c 
b/src/gallium/drivers/r600/evergreen_compute.c
index 6dd6e74..b711786 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -369,7 +369,11 @@ static void evergreen_compute_upload_input(struct 
pipe_context *ctx,
 
ctx->transfer_unmap(ctx, transfer);
 
-   /* ID=0 is reserved for the parameters */
+   /* ID=0 and ID=3 are reserved for the parameters.
+* LLVM will preferably use ID=0, but it does not work for dynamic
+* indices. */
+   evergreen_cs_set_vertex_buffer(rctx, 3, 0,
+   (struct pipe_resource*)shader->kernel_param);
evergreen_cs_set_constant_buffer(rctx, 0, 0, input_size,
(struct pipe_resource*)shader->kernel_param);
 }
@@ -615,9 +619,9 @@ static void evergreen_set_compute_resources(struct 
pipe_context *ctx,
start, count);
 
for (unsigned i = 0; i < count; i++) {
-   /* The First three vertex buffers are reserved for parameters 
and
+   /* The First four vertex buffers are reserved for parameters and
 * global buffers. */
-   unsigned vtx_id = 3 + i;
+   unsigned vtx_id = 4 + i;
if (resources[i]) {
struct r600_resource_global *buffer =
(struct r600_resource_global*)

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Mesa (master): gallium/radeon: add a return value to cs_flush

2016-07-14 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: a7d84f7731b2095ed5dc4f741213fef60a55dcd3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7d84f7731b2095ed5dc4f741213fef60a55dcd3

Author: Marek Olšák 
Date:   Wed Jul 13 15:16:20 2016 +0200

gallium/radeon: add a return value to cs_flush

Required by our UVD code.

Reviewed-by: Christian König 

---

 src/gallium/drivers/radeon/radeon_winsys.h| 8 +---
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 7 ---
 src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 7 ---
 3 files changed, 13 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index 090cafc..a9c9b9e 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -733,10 +733,12 @@ struct radeon_winsys {
  * \param flags,  RADEON_FLUSH_ASYNC or 0.
  * \param fence   Pointer to a fence. If non-NULL, a fence is inserted
  *after the CS and is returned through this parameter.
+ * \return Negative POSIX error code or 0 for success.
+ * Asynchronous submissions never return an error.
  */
-void (*cs_flush)(struct radeon_winsys_cs *cs,
- unsigned flags,
- struct pipe_fence_handle **fence);
+int (*cs_flush)(struct radeon_winsys_cs *cs,
+unsigned flags,
+struct pipe_fence_handle **fence);
 
 /**
  * Return true if a buffer is referenced by a command stream.
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 1302f29..1094c3f 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -968,9 +968,9 @@ void amdgpu_cs_sync_flush(struct radeon_winsys_cs *rcs)
 
 DEBUG_GET_ONCE_BOOL_OPTION(noop, "RADEON_NOOP", false)
 
-static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
-unsigned flags,
-struct pipe_fence_handle **fence)
+static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
+   unsigned flags,
+   struct pipe_fence_handle **fence)
 {
struct amdgpu_cs *cs = amdgpu_cs(rcs);
struct amdgpu_winsys *ws = cs->ctx->ws;
@@ -1069,6 +1069,7 @@ static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
   amdgpu_get_new_ib(>base, cs, IB_CONST_PREAMBLE);
 
ws->num_cs_flushes++;
+   return 0;
 }
 
 static void amdgpu_cs_destroy(struct radeon_winsys_cs *rcs)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index ed34a2c..767c263 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -471,9 +471,9 @@ void radeon_drm_cs_sync_flush(struct radeon_winsys_cs *rcs)
 
 DEBUG_GET_ONCE_BOOL_OPTION(noop, "RADEON_NOOP", false)
 
-static void radeon_drm_cs_flush(struct radeon_winsys_cs *rcs,
-unsigned flags,
-struct pipe_fence_handle **fence)
+static int radeon_drm_cs_flush(struct radeon_winsys_cs *rcs,
+   unsigned flags,
+   struct pipe_fence_handle **fence)
 {
 struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
 struct radeon_cs_context *tmp;
@@ -602,6 +602,7 @@ static void radeon_drm_cs_flush(struct radeon_winsys_cs 
*rcs,
 cs->base.current.cdw = 0;
 
 cs->ws->num_cs_flushes++;
+return 0;
 }
 
 static void radeon_drm_cs_destroy(struct radeon_winsys_cs *rcs)

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Mesa (master): winsys/amdgpu: return an error on IB submission failures

2016-07-14 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: 85388652f9406c07803f8ef327af11c6028b52d6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=85388652f9406c07803f8ef327af11c6028b52d6

Author: Marek Olšák 
Date:   Wed Jul 13 18:31:16 2016 +0200

winsys/amdgpu: return an error on IB submission failures

Reviewed-by: Christian König 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 7 ++-
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 3 +++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 1094c3f..1a094fd 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -900,6 +900,7 @@ void amdgpu_cs_submit_ib(void *job, int thread_index)
   if (!handles) {
  pipe_mutex_unlock(ws->global_bo_list_lock);
  amdgpu_cs_context_cleanup(cs);
+ cs->error_code = -ENOMEM;
  return;
   }
 
@@ -923,10 +924,12 @@ void amdgpu_cs_submit_ib(void *job, int thread_index)
   fprintf(stderr, "amdgpu: buffer list creation failed (%d)\n", r);
   cs->request.resources = NULL;
   amdgpu_fence_signalled(cs->fence);
+  cs->error_code = r;
   goto cleanup;
}
 
r = amdgpu_cs_submit(acs->ctx->ctx, 0, >request, 1);
+   cs->error_code = r;
if (r) {
   if (r == -ENOMEM)
  fprintf(stderr, "amdgpu: Not enough memory for command 
submission.\n");
@@ -974,6 +977,7 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
 {
struct amdgpu_cs *cs = amdgpu_cs(rcs);
struct amdgpu_winsys *ws = cs->ctx->ws;
+   int error_code = 0;
 
rcs->current.max_dw += amdgpu_cs_epilog_dws(cs->ring_type);
 
@@ -1057,6 +1061,7 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
 amdgpu_cs_submit_ib);
   } else {
  amdgpu_cs_submit_ib(cs, 0);
+ error_code = cs->cst->error_code;
   }
} else {
   amdgpu_cs_context_cleanup(cs->csc);
@@ -1069,7 +1074,7 @@ static int amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
   amdgpu_get_new_ib(>base, cs, IB_CONST_PREAMBLE);
 
ws->num_cs_flushes++;
-   return 0;
+   return error_code;
 }
 
 static void amdgpu_cs_destroy(struct radeon_winsys_cs *rcs)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
index f56b5a5..e80b333 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
@@ -88,6 +88,9 @@ struct amdgpu_cs_context {
unsignedmax_dependencies;
 
struct pipe_fence_handle*fence;
+
+   /* the error returned from cs_flush for non-async submissions */
+   int error_code;
 };
 
 struct amdgpu_cs {

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Mesa (master): radeon/uvd: fail to create a decoder if RUVD_MSG_CREATE submission fails

2016-07-14 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: 33eddde4a7823e3f0276cda160bbd8c0b07a4769
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=33eddde4a7823e3f0276cda160bbd8c0b07a4769

Author: Marek Olšák 
Date:   Wed Jul 13 18:51:36 2016 +0200

radeon/uvd: fail to create a decoder if RUVD_MSG_CREATE submission fails

This is the bare minimum for reporting the error to the user.

Reviewed-by: Christian König 

---

 src/gallium/drivers/radeon/radeon_uvd.c | 15 +--
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_uvd.c 
b/src/gallium/drivers/radeon/radeon_uvd.c
index c693b79..10bed7c 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -92,9 +92,9 @@ struct ruvd_decoder {
 };
 
 /* flush IB to the hardware */
-static void flush(struct ruvd_decoder *dec)
+static int flush(struct ruvd_decoder *dec, unsigned flags)
 {
-   dec->ws->cs_flush(dec->cs, RADEON_FLUSH_ASYNC, NULL);
+   return dec->ws->cs_flush(dec->cs, flags, NULL);
 }
 
 /* add a new set register command to the IB */
@@ -927,7 +927,7 @@ static void ruvd_destroy(struct pipe_video_codec *decoder)
dec->msg->stream_handle = dec->stream_handle;
send_msg_buf(dec);
 
-   flush(dec);
+   flush(dec, 0);
 
dec->ws->cs_destroy(dec->cs);
 
@@ -1137,7 +1137,7 @@ static void ruvd_end_frame(struct pipe_video_codec 
*decoder,
 FB_BUFFER_OFFSET + dec->fb_size, RADEON_USAGE_READ, 
RADEON_DOMAIN_GTT);
set_reg(dec, RUVD_ENGINE_CNTL, 1);
 
-   flush(dec);
+   flush(dec, RADEON_FLUSH_ASYNC);
next_buffer(dec);
 }
 
@@ -1162,7 +1162,7 @@ struct pipe_video_codec *ruvd_create_decoder(struct 
pipe_context *context,
unsigned bs_buf_size;
struct radeon_info info;
struct ruvd_decoder *dec;
-   int i;
+   int r, i;
 
ws->query_info(ws, );
 
@@ -1268,7 +1268,10 @@ struct pipe_video_codec *ruvd_create_decoder(struct 
pipe_context *context,
dec->msg->body.create.height_in_samples = dec->base.height;
dec->msg->body.create.dpb_size = dpb_size;
send_msg_buf(dec);
-   flush(dec);
+   r = flush(dec, 0);
+   if (r)
+   goto error;
+
next_buffer(dec);
 
return >base;

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Mesa (master): glsl/types: Use _mesa_hash_data for hashing function types

2016-07-14 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: b919100d6101c0bd7e15a187968af9a36b49e6de
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b919100d6101c0bd7e15a187968af9a36b49e6de

Author: Jason Ekstrand 
Date:   Wed Jul 13 14:26:50 2016 -0700

glsl/types: Use _mesa_hash_data for hashing function types

This is way better than the stupid string approach especially since you
could overflow the string.  Again, I thought I had something better at one
point but it obviously got lost.

Signed-off-by: Jason Ekstrand 
Reviewed-by: Iago Toral Quiroga 
Cc: "12.0" 

---

 src/compiler/glsl_types.cpp | 16 ++--
 1 file changed, 2 insertions(+), 14 deletions(-)

diff --git a/src/compiler/glsl_types.cpp b/src/compiler/glsl_types.cpp
index fa27135..e9b58dd 100644
--- a/src/compiler/glsl_types.cpp
+++ b/src/compiler/glsl_types.cpp
@@ -1097,20 +1097,8 @@ static uint32_t
 function_key_hash(const void *a)
 {
const glsl_type *const key = (glsl_type *) a;
-   char hash_key[128];
-   unsigned size = 0;
-
-   size = snprintf(hash_key, sizeof(hash_key), "%08x", key->length);
-
-   for (unsigned i = 0; i < key->length; i++) {
-  if (size >= sizeof(hash_key))
-break;
-
-  size += snprintf(& hash_key[size], sizeof(hash_key) - size,
-  "%p", (void *) key->fields.structure[i].type);
-   }
-
-   return _mesa_hash_string(hash_key);
+   return _mesa_hash_data(key->fields.parameters,
+  (key->length + 1) * sizeof(*key->fields.parameters));
 }
 
 const glsl_type *

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Mesa (master): glsl/types: Fix function type comparison function

2016-07-14 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: 11ac1c4dbbc9fc41d163fa4d9a76bb73c3907871
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=11ac1c4dbbc9fc41d163fa4d9a76bb73c3907871

Author: Jason Ekstrand 
Date:   Wed Jul 13 14:25:11 2016 -0700

glsl/types: Fix function type comparison function

It was returning true if the function types have different lengths rather
than false.  This was new with the SPIR-V to NIR pass and I thought I'd
fixed it a while ago but it may have gotten lost in rebasing somewhere.

Signed-off-by: Jason Ekstrand 
Reviewed-by: Iago Toral Quiroga 
Cc: "12.0" 

---

 src/compiler/glsl_types.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/glsl_types.cpp b/src/compiler/glsl_types.cpp
index 066a74e..fa27135 100644
--- a/src/compiler/glsl_types.cpp
+++ b/src/compiler/glsl_types.cpp
@@ -1086,7 +1086,7 @@ function_key_compare(const void *a, const void *b)
const glsl_type *const key2 = (glsl_type *) b;
 
if (key1->length != key2->length)
-  return 1;
+  return false;
 
return memcmp(key1->fields.parameters, key2->fields.parameters,
  (key1->length + 1) * sizeof(*key1->fields.parameters)) == 0;

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Mesa (master): freedreno/a4xx: Fix sign compare warnings

2016-07-14 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: 3db7f3458ffbec51329d66f3bed8a3d8eaf35a3d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3db7f3458ffbec51329d66f3bed8a3d8eaf35a3d

Author: franci...@gmail.com 
Date:   Thu Jun 30 19:16:08 2016 +0200

freedreno/a4xx: Fix sign compare warnings

Signed-off-by: Rob Clark 

---

 src/gallium/drivers/freedreno/a4xx/fd4_screen.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a4xx/fd4_screen.c 
b/src/gallium/drivers/freedreno/a4xx/fd4_screen.c
index c193f36..57fecf1 100644
--- a/src/gallium/drivers/freedreno/a4xx/fd4_screen.c
+++ b/src/gallium/drivers/freedreno/a4xx/fd4_screen.c
@@ -52,14 +52,14 @@ fd4_screen_is_format_supported(struct pipe_screen *pscreen,
}
 
if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
-   (fd4_pipe2vtx(format) != ~0)) {
+   (fd4_pipe2vtx(format) != ~0u)) {
retval |= PIPE_BIND_VERTEX_BUFFER;
}
 
if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
(target == PIPE_BUFFER ||
 util_format_get_blocksize(format) != 12) &&
-   (fd4_pipe2tex(format) != ~0)) {
+   (fd4_pipe2tex(format) != ~0u)) {
retval |= PIPE_BIND_SAMPLER_VIEW;
}
 
@@ -67,8 +67,8 @@ fd4_screen_is_format_supported(struct pipe_screen *pscreen,
PIPE_BIND_DISPLAY_TARGET |
PIPE_BIND_SCANOUT |
PIPE_BIND_SHARED)) &&
-   (fd4_pipe2color(format) != ~0) &&
-   (fd4_pipe2tex(format) != ~0)) {
+   (fd4_pipe2color(format) != ~0u) &&
+   (fd4_pipe2tex(format) != ~0u)) {
retval |= usage & (PIPE_BIND_RENDER_TARGET |
PIPE_BIND_DISPLAY_TARGET |
PIPE_BIND_SCANOUT |
@@ -76,13 +76,13 @@ fd4_screen_is_format_supported(struct pipe_screen *pscreen,
}
 
if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
-   (fd4_pipe2depth(format) != ~0) &&
-   (fd4_pipe2tex(format) != ~0)) {
+   (fd4_pipe2depth(format) != ~0u) &&
+   (fd4_pipe2tex(format) != ~0u)) {
retval |= PIPE_BIND_DEPTH_STENCIL;
}
 
if ((usage & PIPE_BIND_INDEX_BUFFER) &&
-   (fd_pipe2index(format) != ~0)) {
+   (fd_pipe2index(format) != ~0u)) {
retval |= PIPE_BIND_INDEX_BUFFER;
}
 

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Mesa (master): freedreno/a3xx: Fix sign compare warnings

2016-07-14 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: 948822018fa36ef286197e8223a721f16a7146ff
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=948822018fa36ef286197e8223a721f16a7146ff

Author: franci...@gmail.com 
Date:   Thu Jun 30 19:16:07 2016 +0200

freedreno/a3xx: Fix sign compare warnings

Signed-off-by: Rob Clark 

---

 src/gallium/drivers/freedreno/a3xx/fd3_screen.c | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_screen.c 
b/src/gallium/drivers/freedreno/a3xx/fd3_screen.c
index 4aea2fe..013b0ca 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_screen.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_screen.c
@@ -52,12 +52,12 @@ fd3_screen_is_format_supported(struct pipe_screen *pscreen,
}
 
if ((usage & PIPE_BIND_VERTEX_BUFFER) &&
-   (fd3_pipe2vtx(format) != ~0)) {
+   (fd3_pipe2vtx(format) != ~0u)) {
retval |= PIPE_BIND_VERTEX_BUFFER;
}
 
if ((usage & PIPE_BIND_SAMPLER_VIEW) &&
-   (fd3_pipe2tex(format) != ~0)) {
+   (fd3_pipe2tex(format) != ~0u)) {
retval |= PIPE_BIND_SAMPLER_VIEW;
}
 
@@ -66,8 +66,8 @@ fd3_screen_is_format_supported(struct pipe_screen *pscreen,
PIPE_BIND_SCANOUT |
PIPE_BIND_SHARED |
PIPE_BIND_BLENDABLE)) &&
-   (fd3_pipe2color(format) != ~0) &&
-   (fd3_pipe2tex(format) != ~0)) {
+   (fd3_pipe2color(format) != ~0u) &&
+   (fd3_pipe2tex(format) != ~0u)) {
retval |= usage & (PIPE_BIND_RENDER_TARGET |
PIPE_BIND_DISPLAY_TARGET |
PIPE_BIND_SCANOUT |
@@ -77,13 +77,13 @@ fd3_screen_is_format_supported(struct pipe_screen *pscreen,
}
 
if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
-   (fd_pipe2depth(format) != ~0) &&
-   (fd3_pipe2tex(format) != ~0)) {
+   (fd_pipe2depth(format) != ~0u) &&
+   (fd3_pipe2tex(format) != ~0u)) {
retval |= PIPE_BIND_DEPTH_STENCIL;
}
 
if ((usage & PIPE_BIND_INDEX_BUFFER) &&
-   (fd_pipe2index(format) != ~0)) {
+   (fd_pipe2index(format) != ~0u)) {
retval |= PIPE_BIND_INDEX_BUFFER;
}
 

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Mesa (master): freedreno/a2xx: Fix sign compare warnings

2016-07-14 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: cf2f34535625d597cc90d04d7fa7237f61f6a634
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cf2f34535625d597cc90d04d7fa7237f61f6a634

Author: franci...@gmail.com 
Date:   Thu Jun 30 19:16:06 2016 +0200

freedreno/a2xx: Fix sign compare warnings

Signed-off-by: Rob Clark 

---

 src/gallium/drivers/freedreno/a2xx/fd2_screen.c | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/freedreno/a2xx/fd2_screen.c 
b/src/gallium/drivers/freedreno/a2xx/fd2_screen.c
index c2baa6f..fe4849b 100644
--- a/src/gallium/drivers/freedreno/a2xx/fd2_screen.c
+++ b/src/gallium/drivers/freedreno/a2xx/fd2_screen.c
@@ -61,7 +61,7 @@ fd2_screen_is_format_supported(struct pipe_screen *pscreen,
 
if ((usage & (PIPE_BIND_SAMPLER_VIEW |
PIPE_BIND_VERTEX_BUFFER)) &&
-   (fd2_pipe2surface(format) != ~0)) {
+   (fd2_pipe2surface(format) != ~0u)) {
retval |= usage & (PIPE_BIND_SAMPLER_VIEW |
PIPE_BIND_VERTEX_BUFFER);
}
@@ -70,7 +70,7 @@ fd2_screen_is_format_supported(struct pipe_screen *pscreen,
PIPE_BIND_DISPLAY_TARGET |
PIPE_BIND_SCANOUT |
PIPE_BIND_SHARED)) &&
-   (fd2_pipe2color(format) != ~0)) {
+   (fd2_pipe2color(format) != ~0u)) {
retval |= usage & (PIPE_BIND_RENDER_TARGET |
PIPE_BIND_DISPLAY_TARGET |
PIPE_BIND_SCANOUT |
@@ -78,12 +78,12 @@ fd2_screen_is_format_supported(struct pipe_screen *pscreen,
}
 
if ((usage & PIPE_BIND_DEPTH_STENCIL) &&
-   (fd_pipe2depth(format) != ~0)) {
+   (fd_pipe2depth(format) != ~0u)) {
retval |= PIPE_BIND_DEPTH_STENCIL;
}
 
if ((usage & PIPE_BIND_INDEX_BUFFER) &&
-   (fd_pipe2index(format) != ~0)) {
+   (fd_pipe2index(format) != ~0u)) {
retval |= PIPE_BIND_INDEX_BUFFER;
}
 

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Mesa (master): radeon/vce: handle newly added parameters

2016-07-14 Thread Christian König 
Module: Mesa
Branch: master
Commit: 23c5e8bc58cd5955151e30aa95e138031d1dad4f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=23c5e8bc58cd5955151e30aa95e138031d1dad4f

Author: Boyuan Zhang 
Date:   Wed Jul 13 18:51:14 2016 -0400

radeon/vce: handle newly added parameters

Replace the previous hardcoded value with newly defined parameters

Signed-off-by: Boyuan Zhang 
Reviewed-by: Christian König 

---

 src/gallium/drivers/radeon/radeon_vce_52.c | 33 ++
 1 file changed, 20 insertions(+), 13 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_vce_52.c 
b/src/gallium/drivers/radeon/radeon_vce_52.c
index 869b29b..136f080 100644
--- a/src/gallium/drivers/radeon/radeon_vce_52.c
+++ b/src/gallium/drivers/radeon/radeon_vce_52.c
@@ -48,13 +48,14 @@ static void get_rate_control_param(struct rvce_encoder 
*enc, struct pipe_h264_en
enc->enc_pic.rc.quant_i_frames = pic->quant_i_frames;
enc->enc_pic.rc.quant_p_frames = pic->quant_p_frames;
enc->enc_pic.rc.quant_b_frames = pic->quant_b_frames;
+   enc->enc_pic.rc.gop_size = pic->gop_size;
enc->enc_pic.rc.frame_rate_num = pic->rate_ctrl.frame_rate_num;
enc->enc_pic.rc.frame_rate_den = pic->rate_ctrl.frame_rate_den;
enc->enc_pic.rc.max_qp = 51;
enc->enc_pic.rc.vbv_buffer_size = pic->rate_ctrl.vbv_buffer_size;
-   enc->enc_pic.rc.vbv_buf_lv = 0;
-   enc->enc_pic.rc.fill_data_enable = 0;
-   enc->enc_pic.rc.enforce_hrd = 0;
+   enc->enc_pic.rc.vbv_buf_lv = pic->rate_ctrl.vbv_buf_lv;
+   enc->enc_pic.rc.fill_data_enable = pic->rate_ctrl.fill_data_enable;
+   enc->enc_pic.rc.enforce_hrd = pic->rate_ctrl.enforce_hrd;
enc->enc_pic.rc.target_bits_picture = 
pic->rate_ctrl.target_bits_picture;
enc->enc_pic.rc.peak_bits_picture_integer = 
pic->rate_ctrl.peak_bits_picture_integer;
enc->enc_pic.rc.peak_bits_picture_fraction = 
pic->rate_ctrl.peak_bits_picture_fraction;
@@ -62,13 +63,13 @@ static void get_rate_control_param(struct rvce_encoder 
*enc, struct pipe_h264_en
 
 static void get_motion_estimation_param(struct rvce_encoder *enc, struct 
pipe_h264_enc_picture_desc *pic)
 {
-   enc->enc_pic.me.motion_est_quarter_pixel = 0x;
-   enc->enc_pic.me.enc_disable_sub_mode = 0x00fe;
-   enc->enc_pic.me.lsmvert = 0x;
-   enc->enc_pic.me.enc_en_ime_overw_dis_subm = 0x;
-   enc->enc_pic.me.enc_ime_overw_dis_subm_no = 0x;
-   enc->enc_pic.me.enc_ime2_search_range_x = 0x0001;
-   enc->enc_pic.me.enc_ime2_search_range_y = 0x0001;
+   enc->enc_pic.me.motion_est_quarter_pixel = 
pic->motion_est.motion_est_quarter_pixel;
+   enc->enc_pic.me.enc_disable_sub_mode = 
pic->motion_est.enc_disable_sub_mode;
+   enc->enc_pic.me.lsmvert = pic->motion_est.lsmvert;
+   enc->enc_pic.me.enc_en_ime_overw_dis_subm = 
pic->motion_est.enc_en_ime_overw_dis_subm;
+   enc->enc_pic.me.enc_ime_overw_dis_subm_no = 
pic->motion_est.enc_ime_overw_dis_subm_no;
+   enc->enc_pic.me.enc_ime2_search_range_x = 
pic->motion_est.enc_ime2_search_range_x;
+   enc->enc_pic.me.enc_ime2_search_range_y = 
pic->motion_est.enc_ime2_search_range_y;
enc->enc_pic.me.enc_ime_decimation_search = 0x0001;
enc->enc_pic.me.motion_est_half_pixel = 0x0001;
enc->enc_pic.me.enc_search_range_x = 0x0010;
@@ -90,8 +91,8 @@ static void get_pic_control_param(struct rvce_encoder *enc, 
struct pipe_h264_enc
enc->enc_pic.pc.enc_max_num_ref_frames = enc->base.max_references + 1;
enc->enc_pic.pc.enc_num_default_active_ref_l0 = 0x0001;
enc->enc_pic.pc.enc_num_default_active_ref_l1 = 0x0001;
-   enc->enc_pic.pc.enc_cabac_enable = 0x;
-   enc->enc_pic.pc.enc_constraint_set_flags = 0x0040;
+   enc->enc_pic.pc.enc_cabac_enable = pic->pic_ctrl.enc_cabac_enable;
+   enc->enc_pic.pc.enc_constraint_set_flags = 
pic->pic_ctrl.enc_constraint_set_flags;
enc->enc_pic.pc.enc_num_default_active_ref_l0 = 0x0001;
enc->enc_pic.pc.enc_num_default_active_ref_l1 = 0x0001;
 }
@@ -113,7 +114,7 @@ static void get_config_ext_param(struct rvce_encoder *enc)
 
 static void get_vui_param(struct rvce_encoder *enc, struct 
pipe_h264_enc_picture_desc *pic)
 {
-   enc->enc_pic.enable_vui = (pic->rate_ctrl.frame_rate_num != 0);
+   enc->enc_pic.enable_vui = pic->enable_vui;
enc->enc_pic.vui.video_format = 0x0005;
enc->enc_pic.vui.color_prim = 0x0002;
enc->enc_pic.vui.transfer_char = 0x0002;
@@ -149,10 +150,16 @@ void radeon_vce_52_get_param(struct rvce_encoder *enc, 
struct pipe_h264_enc_pict
 
enc->enc_pic.picture_type = pic->picture_type;
enc->enc_pic.frame_num = pic->frame_num;
+   enc->enc_pic.frame_num_cnt = pic->frame_num_cnt;
+   enc->enc_pic.p_remain = pic->p_remain;
+

Mesa (master): vl: add parameters for VAAPI encode

2016-07-14 Thread Christian König 
Module: Mesa
Branch: master
Commit: b86bf4b568634b4bf11c645c60025840a0dcab5c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b86bf4b568634b4bf11c645c60025840a0dcab5c

Author: Boyuan Zhang 
Date:   Wed Jul 13 18:51:11 2016 -0400

vl: add parameters for VAAPI encode

Allow to specify more parameters in the encoding interface
which previously just hardcoded in the encoder

Signed-off-by: Boyuan Zhang 
Reviewed-by: Christian König 

---

 src/gallium/include/pipe/p_video_state.h | 33 
 1 file changed, 33 insertions(+)

diff --git a/src/gallium/include/pipe/p_video_state.h 
b/src/gallium/include/pipe/p_video_state.h
index d353be6..754d013 100644
--- a/src/gallium/include/pipe/p_video_state.h
+++ b/src/gallium/include/pipe/p_video_state.h
@@ -352,9 +352,29 @@ struct pipe_h264_enc_rate_control
unsigned frame_rate_num;
unsigned frame_rate_den;
unsigned vbv_buffer_size;
+   unsigned vbv_buf_lv;
unsigned target_bits_picture;
unsigned peak_bits_picture_integer;
unsigned peak_bits_picture_fraction;
+   unsigned fill_data_enable;
+   unsigned enforce_hrd;
+};
+
+struct pipe_h264_enc_motion_estimation
+{
+   unsigned motion_est_quarter_pixel;
+   unsigned enc_disable_sub_mode;
+   unsigned lsmvert;
+   unsigned enc_en_ime_overw_dis_subm;
+   unsigned enc_ime_overw_dis_subm_no;
+   unsigned enc_ime2_search_range_x;
+   unsigned enc_ime2_search_range_y;
+};
+
+struct pipe_h264_enc_pic_control
+{
+   unsigned enc_cabac_enable;
+   unsigned enc_constraint_set_flags;
 };
 
 struct pipe_h264_enc_picture_desc
@@ -363,17 +383,30 @@ struct pipe_h264_enc_picture_desc
 
struct pipe_h264_enc_rate_control rate_ctrl;
 
+   struct pipe_h264_enc_motion_estimation motion_est;
+   struct pipe_h264_enc_pic_control pic_ctrl;
+
unsigned quant_i_frames;
unsigned quant_p_frames;
unsigned quant_b_frames;
 
enum pipe_h264_enc_picture_type picture_type;
unsigned frame_num;
+   unsigned frame_num_cnt;
+   unsigned p_remain;
+   unsigned i_remain;
+   unsigned idr_pic_id;
+   unsigned gop_cnt;
unsigned pic_order_cnt;
unsigned ref_idx_l0;
unsigned ref_idx_l1;
+   unsigned gop_size;
+   unsigned ref_pic_mode;
 
bool not_referenced;
+   bool is_idr;
+   bool enable_vui;
+   unsigned int frame_idx[32];
 };
 
 struct pipe_h265_sps

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Mesa (master): st/omx: assign previous values to new structure

2016-07-14 Thread Christian König 
Module: Mesa
Branch: master
Commit: 5490068fb146dc2d391cf7f7c4eb875ac6973e88
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5490068fb146dc2d391cf7f7c4eb875ac6973e88

Author: Boyuan Zhang 
Date:   Wed Jul 13 18:51:13 2016 -0400

st/omx: assign previous values to new structure

Assign previously hardcoded values for OMX to newly defined
structure. As a result, OMX behaviour will not change at all.

Signed-off-by: Boyuan Zhang 
Reviewed-by: Christian König 

---

 src/gallium/state_trackers/omx/vid_enc.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/src/gallium/state_trackers/omx/vid_enc.c 
b/src/gallium/state_trackers/omx/vid_enc.c
index d70439a..bbc7941 100644
--- a/src/gallium/state_trackers/omx/vid_enc.c
+++ b/src/gallium/state_trackers/omx/vid_enc.c
@@ -1006,6 +1006,14 @@ static void enc_ScaleInput(omx_base_PortType *port, 
struct pipe_video_buffer **v
priv->current_scale_buffer %= OMX_VID_ENC_NUM_SCALING_BUFFERS;
 }
 
+static void enc_GetPictureParamPreset(struct pipe_h264_enc_picture_desc 
*picture)
+{
+   picture->motion_est.enc_disable_sub_mode = 0x00fe;
+   picture->motion_est.enc_ime2_search_range_x = 0x0001;
+   picture->motion_est.enc_ime2_search_range_y = 0x0001;
+   picture->pic_ctrl.enc_constraint_set_flags = 0x0040;
+}
+
 static void enc_ControlPicture(omx_base_PortType *port, struct 
pipe_h264_enc_picture_desc *picture)
 {
OMX_COMPONENTTYPE* comp = port->standCompContainer;
@@ -1064,6 +1072,8 @@ static void enc_ControlPicture(omx_base_PortType *port, 
struct pipe_h264_enc_pic
picture->frame_num = priv->frame_num;
picture->ref_idx_l0 = priv->ref_idx_l0;
picture->ref_idx_l1 = priv->ref_idx_l1;
+   picture->enable_vui = (picture->rate_ctrl.frame_rate_num != 0);
+   enc_GetPictureParamPreset(picture);
 }
 
 static void enc_HandleTask(omx_base_PortType *port, struct encode_task *task,

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Mesa (master): st/mesa: fix reference counting bug in st_vdpau

2016-07-14 Thread Christian König 
Module: Mesa
Branch: master
Commit: 9ce52baf7f479d506bcea17a371dcf2fad92f139
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ce52baf7f479d506bcea17a371dcf2fad92f139

Author: Christian König 
Date:   Wed Jul 13 14:54:31 2016 +0200

st/mesa: fix reference counting bug in st_vdpau

Otherwise we leak the resources created for the DMA-buf descriptors.

Signed-off-by: Christian König 
Cc: 12.0 
Tested-and-Reviewed by: Leo Liu 
Ack-by: Tom St Denis 

---

 src/mesa/state_tracker/st_vdpau.c | 10 --
 1 file changed, 8 insertions(+), 2 deletions(-)

diff --git a/src/mesa/state_tracker/st_vdpau.c 
b/src/mesa/state_tracker/st_vdpau.c
index dffa52f..4f599dd 100644
--- a/src/mesa/state_tracker/st_vdpau.c
+++ b/src/mesa/state_tracker/st_vdpau.c
@@ -65,6 +65,7 @@ st_vdpau_video_surface_gallium(struct gl_context *ctx, const 
void *vdpSurface,
 
struct pipe_video_buffer *buffer;
struct pipe_sampler_view **samplers;
+   struct pipe_resource *res = NULL;
 
getProcAddr = (void *)ctx->vdpGetProcAddress;
if (getProcAddr(device, VDP_FUNC_ID_VIDEO_SURFACE_GALLIUM, (void**)))
@@ -82,7 +83,8 @@ st_vdpau_video_surface_gallium(struct gl_context *ctx, const 
void *vdpSurface,
if (!sv)
   return NULL;
 
-   return sv->texture;
+   pipe_resource_reference(, sv->texture);
+   return res;
 }
 
 static struct pipe_resource *
@@ -90,13 +92,15 @@ st_vdpau_output_surface_gallium(struct gl_context *ctx, 
const void *vdpSurface)
 {
int (*getProcAddr)(uint32_t device, uint32_t id, void **ptr);
uint32_t device = (uintptr_t)ctx->vdpDevice;
+   struct pipe_resource *res = NULL;
VdpOutputSurfaceGallium *f;
 
getProcAddr = (void *)ctx->vdpGetProcAddress;
if (getProcAddr(device, VDP_FUNC_ID_OUTPUT_SURFACE_GALLIUM, (void**)))
   return NULL;
 
-   return f((uintptr_t)vdpSurface);
+   pipe_resource_reference(, f((uintptr_t)vdpSurface));
+   return res;
 }
 
 static struct pipe_resource *
@@ -208,6 +212,7 @@ st_vdpau_map_surface(struct gl_context *ctx, GLenum target, 
GLenum access,
/* do we have different screen objects ? */
if (res->screen != st->pipe->screen) {
   _mesa_error(ctx, GL_INVALID_OPERATION, "VDPAUMapSurfacesNV");
+  pipe_resource_reference(, NULL);
   return;
}
 
@@ -241,6 +246,7 @@ st_vdpau_map_surface(struct gl_context *ctx, GLenum target, 
GLenum access,
stObj->surface_format = res->format;
 
_mesa_dirty_texobj(ctx, texObj);
+   pipe_resource_reference(, NULL);
 }
 
 static void

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Mesa (master): vc4: Add support for scheduling of branch instructions.

2016-07-14 Thread Eric Anholt 
Module: Mesa
Branch: master
Commit: 44df061aaad96fc5db630ae69fb2fe2a03bb5659
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=44df061aaad96fc5db630ae69fb2fe2a03bb5659

Author: Eric Anholt 
Date:   Wed Apr 27 12:14:07 2016 -0700

vc4: Add support for scheduling of branch instructions.

For now we don't fill the delay slots, and instead just drop in NOPs.

---

 src/gallium/drivers/vc4/vc4_qir.h  |  11 +++
 src/gallium/drivers/vc4/vc4_qpu_schedule.c | 120 +
 2 files changed, 114 insertions(+), 17 deletions(-)

diff --git a/src/gallium/drivers/vc4/vc4_qir.h 
b/src/gallium/drivers/vc4/vc4_qir.h
index fabdf10..e7ddfaa 100644
--- a/src/gallium/drivers/vc4/vc4_qir.h
+++ b/src/gallium/drivers/vc4/vc4_qir.h
@@ -362,6 +362,17 @@ struct qblock {
 
 int index;
 
+/* Instruction IPs for the first and last instruction of the block.
+ * Set by vc4_qpu_schedule.c.
+ */
+uint32_t start_qpu_ip;
+uint32_t end_qpu_ip;
+
+/* Instruction IP for the branch instruction of the block.  Set by
+ * vc4_qpu_schedule.c.
+ */
+uint32_t branch_qpu_ip;
+
 /** @{ used by vc4_qir_live_variables.c */
 BITSET_WORD *def;
 BITSET_WORD *use;
diff --git a/src/gallium/drivers/vc4/vc4_qpu_schedule.c 
b/src/gallium/drivers/vc4/vc4_qpu_schedule.c
index fad10e5..a55b035 100644
--- a/src/gallium/drivers/vc4/vc4_qpu_schedule.c
+++ b/src/gallium/drivers/vc4/vc4_qpu_schedule.c
@@ -354,7 +354,8 @@ calculate_deps(struct schedule_state *state, struct 
schedule_node *n)
 
 if (sig != QPU_SIG_LOAD_IMM) {
 process_raddr_deps(state, n, raddr_a, true);
-if (sig != QPU_SIG_SMALL_IMM)
+if (sig != QPU_SIG_SMALL_IMM &&
+sig != QPU_SIG_BRANCH)
 process_raddr_deps(state, n, raddr_b, false);
 }
 
@@ -392,20 +393,23 @@ calculate_deps(struct schedule_state *state, struct 
schedule_node *n)
 add_read_dep(state, state->last_tlb, n);
 break;
 
+case QPU_SIG_BRANCH:
+add_read_dep(state, state->last_sf, n);
+break;
+
 case QPU_SIG_PROG_END:
 case QPU_SIG_WAIT_FOR_SCOREBOARD:
 case QPU_SIG_SCOREBOARD_UNLOCK:
 case QPU_SIG_COVERAGE_LOAD:
 case QPU_SIG_COLOR_LOAD_END:
 case QPU_SIG_ALPHA_MASK_LOAD:
-case QPU_SIG_BRANCH:
 fprintf(stderr, "Unhandled signal bits %d\n", sig);
 abort();
 }
 
 process_cond_deps(state, n, QPU_GET_FIELD(inst, QPU_COND_ADD));
 process_cond_deps(state, n, QPU_GET_FIELD(inst, QPU_COND_MUL));
-if (inst & QPU_SF)
+if ((inst & QPU_SF) && sig != QPU_SIG_BRANCH)
 add_write_dep(state, >last_sf, n);
 }
 
@@ -525,6 +529,16 @@ choose_instruction_to_schedule(struct choose_scoreboard 
*scoreboard,
 list_for_each_entry(struct schedule_node, n, schedule_list, link) {
 uint64_t inst = n->inst->inst;
 
+/* Don't choose the branch instruction until it's the last one
+ * left.  XXX: We could potentially choose it before it's the
+ * last one, if the remaining instructions fit in the delay
+ * slots.
+ */
+if (QPU_GET_FIELD(inst, QPU_SIG) == QPU_SIG_BRANCH &&
+!list_is_singular(schedule_list)) {
+continue;
+}
+
 /* "An instruction must not read from a location in physical
  *  regfile A or B that was written to by the previous
  *  instruction."
@@ -722,19 +736,16 @@ mark_instruction_scheduled(struct list_head 
*schedule_list,
 }
 
 static uint32_t
-schedule_instructions(struct vc4_compile *c, struct list_head *schedule_list,
+schedule_instructions(struct vc4_compile *c,
+  struct choose_scoreboard *scoreboard,
+  struct qblock *block,
+  struct list_head *schedule_list,
   enum quniform_contents *orig_uniform_contents,
   uint32_t *orig_uniform_data,
   uint32_t *next_uniform)
 {
-struct choose_scoreboard scoreboard;
 uint32_t time = 0;
 
-memset(, 0, sizeof(scoreboard));
-scoreboard.last_waddr_a = ~0;
-scoreboard.last_waddr_b = ~0;
-scoreboard.last_sfu_write_tick = -10;
-
 if (debug) {
 fprintf(stderr, "initial deps:\n");
 dump_state(schedule_list);
@@ -749,7 +760,7 @@ schedule_instructions(struct vc4_compile *c, struct 
list_head *schedule_list,
 
 while (!list_empty(schedule_list)) {
 struct schedule_node *chosen =
-choose_instruction_to_schedule(,
+choose_instruction_to_schedule(scoreboard,

Mesa (master): vc4: Convert vc4_opt_dead_code to work in the presence of control flow.

2016-07-14 Thread Eric Anholt 
Module: Mesa
Branch: master
Commit: ee69cfd11d34e6570c579c42f9cd8b5c8ea36bcf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee69cfd11d34e6570c579c42f9cd8b5c8ea36bcf

Author: Eric Anholt 
Date:   Fri Jul  8 16:23:38 2016 -0700

vc4: Convert vc4_opt_dead_code to work in the presence of control flow.

With control flow, we can't be sure that we'll see the uses of a variable
before its def as we walk backwards.  Given that NIR is eliminating our
long chains of dead code, a simple solution for now seems fine.

This slightly changes the order of some optimizations, and so an opt_vpm
happens before opt_dce, causing 3 dead MOVs to be turned into dead FMAXes
in Minecraft:

instructions in affected programs: 52 -> 54 (3.85%)

---

 src/gallium/drivers/vc4/vc4_opt_dead_code.c | 47 ++---
 1 file changed, 29 insertions(+), 18 deletions(-)

diff --git a/src/gallium/drivers/vc4/vc4_opt_dead_code.c 
b/src/gallium/drivers/vc4/vc4_opt_dead_code.c
index 26fa3ed..f516d38 100644
--- a/src/gallium/drivers/vc4/vc4_opt_dead_code.c
+++ b/src/gallium/drivers/vc4/vc4_opt_dead_code.c
@@ -24,11 +24,15 @@
 /**
  * @file vc4_opt_dead_code.c
  *
- * This is a simmple dead code eliminator for QIR with no control flow.
+ * This is a simple dead code eliminator for SSA values in QIR.
  *
- * It walks from the bottom of the instruction list, removing instructions
- * with a destination that is never used, and marking the sources of non-dead
- * instructions as used.
+ * It walks all the instructions finding what temps are used, then walks again
+ * to remove instructions writing unused temps.
+ *
+ * This is an inefficient implementation if you have long chains of
+ * instructions where the entire chain is dead, but we expect those to have
+ * been eliminated at the NIR level, and here we're just cleaning up small
+ * problems produced by NIR->QIR.
  */
 
 #include "vc4_qir.h"
@@ -83,15 +87,27 @@ qir_opt_dead_code(struct vc4_compile *c)
 bool progress = false;
 bool *used = calloc(c->num_temps, sizeof(bool));
 
-list_for_each_entry_safe_rev(struct qinst, inst,
- >cur_block->instructions,
- link) {
-if ((inst->dst.file == QFILE_NULL ||
- (inst->dst.file == QFILE_TEMP &&
-  !used[inst->dst.index])) &&
-!inst->sf &&
-!qir_has_side_effects(c, inst) &&
-!has_nonremovable_reads(c, inst)) {
+qir_for_each_inst_inorder(inst, c) {
+for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
+if (inst->src[i].file == QFILE_TEMP)
+used[inst->src[i].index] = true;
+}
+}
+
+qir_for_each_block(block, c) {
+qir_for_each_inst_safe(inst, block) {
+if (inst->dst.file != QFILE_NULL &&
+!(inst->dst.file == QFILE_TEMP &&
+  !used[inst->dst.index])) {
+continue;
+}
+
+if (inst->sf ||
+qir_has_side_effects(c, inst) ||
+has_nonremovable_reads(c, inst)) {
+continue;
+}
+
 for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
 if (inst->src[i].file != QFILE_VPM)
 continue;
@@ -108,11 +124,6 @@ qir_opt_dead_code(struct vc4_compile *c)
 progress = true;
 continue;
 }
-
-for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
-if (inst->src[i].file == QFILE_TEMP)
-used[inst->src[i].index] = true;
-}
 }
 
 free(used);

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Mesa (master): vc4: Emit resets of the uniform stream at the starts of blocks.

2016-07-14 Thread Eric Anholt 
Module: Mesa
Branch: master
Commit: 9194473dd260fe72042807a97be0072c6f0537da
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9194473dd260fe72042807a97be0072c6f0537da

Author: Eric Anholt 
Date:   Thu May  5 18:11:04 2016 -0700

vc4: Emit resets of the uniform stream at the starts of blocks.

If a block might be entered from multiple locations, then the uniform
stream will (probably) be at different points, and we need to make sure
that it's pointing where we expect it to be.  The kernel also enforces
that any block reading a uniform resets uniforms, to prevent reading
outside of the uniform stream by using looping.

---

 src/gallium/drivers/vc4/Makefile.sources   |   1 +
 src/gallium/drivers/vc4/vc4_program.c  |   1 +
 src/gallium/drivers/vc4/vc4_qir.c  |   1 +
 src/gallium/drivers/vc4/vc4_qir.h  |  12 +++
 .../vc4/vc4_qir_emit_uniform_stream_resets.c   | 101 +
 src/gallium/drivers/vc4/vc4_qir_schedule.c |  16 
 src/gallium/drivers/vc4/vc4_qpu_emit.c |   8 ++
 src/gallium/drivers/vc4/vc4_qpu_schedule.c |  21 +
 src/gallium/drivers/vc4/vc4_uniforms.c |   6 ++
 9 files changed, 167 insertions(+)

diff --git a/src/gallium/drivers/vc4/Makefile.sources 
b/src/gallium/drivers/vc4/Makefile.sources
index 76e46f5..76e52ce 100644
--- a/src/gallium/drivers/vc4/Makefile.sources
+++ b/src/gallium/drivers/vc4/Makefile.sources
@@ -31,6 +31,7 @@ C_SOURCES := \
vc4_opt_vpm.c \
vc4_program.c \
vc4_qir.c \
+   vc4_qir_emit_uniform_stream_resets.c \
vc4_qir_live_variables.c \
vc4_qir_lower_uniforms.c \
vc4_qir_schedule.c \
diff --git a/src/gallium/drivers/vc4/vc4_program.c 
b/src/gallium/drivers/vc4/vc4_program.c
index 465e052..521f971 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -2114,6 +2114,7 @@ vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
 qir_lower_uniforms(c);
 
 qir_schedule_instructions(c);
+qir_emit_uniform_stream_resets(c);
 
 if (vc4_debug & VC4_DEBUG_QIR) {
 fprintf(stderr, "%s prog %d/%d QIR:\n",
diff --git a/src/gallium/drivers/vc4/vc4_qir.c 
b/src/gallium/drivers/vc4/vc4_qir.c
index e1d663d..9ff1561 100644
--- a/src/gallium/drivers/vc4/vc4_qir.c
+++ b/src/gallium/drivers/vc4/vc4_qir.c
@@ -85,6 +85,7 @@ static const struct qir_op_info qir_op_info[] = {
 [QOP_LOAD_IMM] = { "load_imm", 0, 1 },
 
 [QOP_BRANCH] = { "branch", 0, 0, true },
+[QOP_UNIFORMS_RESET] = { "uniforms_reset", 0, 2, true },
 };
 
 static const char *
diff --git a/src/gallium/drivers/vc4/vc4_qir.h 
b/src/gallium/drivers/vc4/vc4_qir.h
index e7ddfaa..88eda22 100644
--- a/src/gallium/drivers/vc4/vc4_qir.h
+++ b/src/gallium/drivers/vc4/vc4_qir.h
@@ -162,6 +162,12 @@ enum qop {
  * that block->successor[1] may be unset if the condition is ALWAYS.
  */
 QOP_BRANCH,
+
+/* Emits an ADD from src[0] to src[1], where src[0] must be a
+ * QOP_LOAD_IMM result and src[1] is a QUNIFORM_UNIFORMS_ADDRESS,
+ * required by the kernel as part of its branch validation.
+ */
+QOP_UNIFORMS_RESET,
 };
 
 struct queued_qpu_inst {
@@ -260,6 +266,11 @@ enum quniform_contents {
 
 QUNIFORM_ALPHA_REF,
 QUNIFORM_SAMPLE_MASK,
+
+/* Placeholder uniform that will be updated by the kernel when used by
+ * an instruction writing to QPU_W_UNIFORMS_ADDRESS.
+ */
+QUNIFORM_UNIFORMS_ADDRESS,
 };
 
 struct vc4_varying_slot {
@@ -521,6 +532,7 @@ struct qreg qir_uniform(struct vc4_compile *c,
 uint32_t data);
 void qir_schedule_instructions(struct vc4_compile *c);
 void qir_reorder_uniforms(struct vc4_compile *c);
+void qir_emit_uniform_stream_resets(struct vc4_compile *c);
 
 struct qreg qir_emit_def(struct vc4_compile *c, struct qinst *inst);
 struct qinst *qir_emit_nondef(struct vc4_compile *c, struct qinst *inst);
diff --git a/src/gallium/drivers/vc4/vc4_qir_emit_uniform_stream_resets.c 
b/src/gallium/drivers/vc4/vc4_qir_emit_uniform_stream_resets.c
new file mode 100644
index 000..3fd6358
--- /dev/null
+++ b/src/gallium/drivers/vc4/vc4_qir_emit_uniform_stream_resets.c
@@ -0,0 +1,101 @@
+/*
+ * Copyright © 2014 Broadcom
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or

Mesa (master): vc4: Disable vc4_opt_vpm in the presence of control flow.

2016-07-14 Thread Eric Anholt 
Module: Mesa
Branch: master
Commit: 37ecc616628d3d5fb75e53135f2f31b11e0cce74
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=37ecc616628d3d5fb75e53135f2f31b11e0cce74

Author: Eric Anholt 
Date:   Fri Jul  8 17:06:18 2016 -0700

vc4: Disable vc4_opt_vpm in the presence of control flow.

It's a really valuable pass currently, but it will be a mess to rewrite
for control flow.  For now, just disable it if we have multiple blocks
present.

---

 src/gallium/drivers/vc4/vc4_opt_vpm.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/gallium/drivers/vc4/vc4_opt_vpm.c 
b/src/gallium/drivers/vc4/vc4_opt_vpm.c
index e2249bd..34ea336 100644
--- a/src/gallium/drivers/vc4/vc4_opt_vpm.c
+++ b/src/gallium/drivers/vc4/vc4_opt_vpm.c
@@ -38,6 +38,11 @@ qir_opt_vpm(struct vc4_compile *c)
 if (c->stage == QSTAGE_FRAG)
 return false;
 
+/* For now, only do this pass when we don't have control flow. */
+struct qblock *block = qir_entry_block(c);
+if (block != qir_exit_block(c))
+return false;
+
 bool progress = false;
 struct qinst *vpm_writes[64] = { 0 };
 uint32_t use_count[c->num_temps];

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Mesa (master): vc4: Update copy propagation for control flow.

2016-07-14 Thread Eric Anholt 
Module: Mesa
Branch: master
Commit: 4e797bd98f3aaea8d295c661f7501053156d211a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e797bd98f3aaea8d295c661f7501053156d211a

Author: Eric Anholt 
Date:   Wed Jul 13 13:37:56 2016 -0700

vc4: Update copy propagation for control flow.

Previously, we could assume that a MOV from a temp was always an available
copy, because all temps were SSA in NIR, and their non-SSA state in QIR
was just due to the fact that they were from a bcsel or pack_unorm_4x8, so
we could use the current value of the temp after that series of QIR
instructions to define it.

However, this is no longer the case with control flow.  Instead, we track
a new array of MOVs defined within the block that haven't had their source
or dest killed yet, and use that primarily.  We fall back to looking
through the QIR defs array to handle across-block MOVs, but now require
that copies from the SSA defs have an SSA src as well.

---

 src/gallium/drivers/vc4/vc4_opt_copy_propagation.c | 199 ++---
 1 file changed, 137 insertions(+), 62 deletions(-)

diff --git a/src/gallium/drivers/vc4/vc4_opt_copy_propagation.c 
b/src/gallium/drivers/vc4/vc4_opt_copy_propagation.c
index a180f04..f8f1365 100644
--- a/src/gallium/drivers/vc4/vc4_opt_copy_propagation.c
+++ b/src/gallium/drivers/vc4/vc4_opt_copy_propagation.c
@@ -34,85 +34,160 @@
 
 #include "vc4_qir.h"
 
-bool
-qir_opt_copy_propagation(struct vc4_compile *c)
+static bool
+is_copy_mov(struct qinst *inst)
+{
+if (!inst)
+return false;
+
+if (inst->op != QOP_MOV &&
+inst->op != QOP_FMOV &&
+inst->op != QOP_MMOV) {
+return false;
+}
+
+if (inst->dst.file != QFILE_TEMP)
+return false;
+
+if (inst->src[0].file != QFILE_TEMP &&
+inst->src[0].file != QFILE_UNIF) {
+return false;
+}
+
+if (inst->dst.pack || inst->cond != QPU_COND_ALWAYS)
+return false;
+
+return true;
+
+}
+
+static bool
+try_copy_prop(struct vc4_compile *c, struct qinst *inst, struct qinst **movs)
 {
-bool progress = false;
 bool debug = false;
+bool progress = false;
+
+   for (int i = 0; i < qir_get_op_nsrc(inst->op); i++) {
+if (inst->src[i].file != QFILE_TEMP)
+continue;
 
-qir_for_each_inst_inorder(inst, c) {
-int nsrc = qir_get_op_nsrc(inst->op);
-for (int i = 0; i < nsrc; i++) {
-if (inst->src[i].file != QFILE_TEMP)
+/* We have two ways of finding MOVs we can copy propagate
+ * from.  One is if it's an SSA def: then we can reuse it from
+ * any block in the program, as long as its source is also an
+ * SSA def.  Alternatively, if it's in the "movs" array
+ * tracked within the block, then we know the sources for it
+ * haven't been changed since we saw the instruction within
+ * our block.
+ */
+struct qinst *mov = movs[inst->src[i].index];
+if (!mov) {
+if (!is_copy_mov(c->defs[inst->src[i].index]))
 continue;
+mov = c->defs[inst->src[i].index];
 
-struct qinst *mov = c->defs[inst->src[i].index];
-if (!mov ||
-(mov->op != QOP_MOV &&
- mov->op != QOP_FMOV &&
- mov->op != QOP_MMOV)) {
+if (mov->src[0].file == QFILE_TEMP &&
+!c->defs[mov->src[0].index])
 continue;
-}
+}
 
-if (mov->src[0].file != QFILE_TEMP &&
-mov->src[0].file != QFILE_UNIF) {
+uint8_t unpack;
+if (mov->src[0].pack) {
+/* Make sure that the meaning of the unpack
+ * would be the same between the two
+ * instructions.
+ */
+if (qir_is_float_input(inst) !=
+qir_is_float_input(mov)) {
 continue;
 }
 
-if (mov->dst.pack)
+/* There's only one unpack field, so make sure
+ * this instruction doesn't already use it.
+ */
+bool already_has_unpack = false;
+for (int j = 0; j < qir_get_op_nsrc(inst->op); j++) {
+if (inst->src[j].pack)
+already_has_unpack = true;
+}
+

Mesa (master): vc4: Move the QPU instructions to schedule into each block.

2016-07-14 Thread Eric Anholt 
Module: Mesa
Branch: master
Commit: a59da513d3229c883809ac2088c9612abcec1470
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a59da513d3229c883809ac2088c9612abcec1470

Author: Eric Anholt 
Date:   Tue Mar 15 17:53:36 2016 -0700

vc4: Move the QPU instructions to schedule into each block.

We'll want to schedule them individually, to handle delay slots.

---

 src/gallium/drivers/vc4/vc4_qir.c  |   1 +
 src/gallium/drivers/vc4/vc4_qir.h  |   2 +
 src/gallium/drivers/vc4/vc4_qpu_emit.c | 205 +++--
 src/gallium/drivers/vc4/vc4_qpu_schedule.c | 113 +---
 4 files changed, 180 insertions(+), 141 deletions(-)

diff --git a/src/gallium/drivers/vc4/vc4_qir.c 
b/src/gallium/drivers/vc4/vc4_qir.c
index 982e829..e1d663d 100644
--- a/src/gallium/drivers/vc4/vc4_qir.c
+++ b/src/gallium/drivers/vc4/vc4_qir.c
@@ -536,6 +536,7 @@ qir_new_block(struct vc4_compile *c)
 struct qblock *block = rzalloc(c, struct qblock);
 
 list_inithead(>instructions);
+list_inithead(>qpu_inst_list);
 
 block->predecessors = _mesa_set_create(block,
_mesa_hash_pointer,
diff --git a/src/gallium/drivers/vc4/vc4_qir.h 
b/src/gallium/drivers/vc4/vc4_qir.h
index fe85b76..fabdf10 100644
--- a/src/gallium/drivers/vc4/vc4_qir.h
+++ b/src/gallium/drivers/vc4/vc4_qir.h
@@ -355,6 +355,7 @@ struct qblock {
 struct list_head link;
 
 struct list_head instructions;
+struct list_head qpu_inst_list;
 
 struct set *predecessors;
 struct qblock *successors[2];
@@ -467,6 +468,7 @@ struct vc4_compile {
 struct qblock *loop_break_block;
 
 struct list_head qpu_inst_list;
+
 uint64_t *qpu_insts;
 uint32_t qpu_inst_count;
 uint32_t qpu_inst_size;
diff --git a/src/gallium/drivers/vc4/vc4_qpu_emit.c 
b/src/gallium/drivers/vc4/vc4_qpu_emit.c
index 2257dcc..9001643 100644
--- a/src/gallium/drivers/vc4/vc4_qpu_emit.c
+++ b/src/gallium/drivers/vc4/vc4_qpu_emit.c
@@ -44,31 +44,31 @@ vc4_dump_program(struct vc4_compile *c)
 }
 
 static void
-queue(struct vc4_compile *c, uint64_t inst)
+queue(struct qblock *block, uint64_t inst)
 {
-struct queued_qpu_inst *q = rzalloc(c, struct queued_qpu_inst);
+struct queued_qpu_inst *q = rzalloc(block, struct queued_qpu_inst);
 q->inst = inst;
-list_addtail(>link, >qpu_inst_list);
+list_addtail(>link, >qpu_inst_list);
 }
 
 static uint64_t *
-last_inst(struct vc4_compile *c)
+last_inst(struct qblock *block)
 {
 struct queued_qpu_inst *q =
-(struct queued_qpu_inst *)c->qpu_inst_list.prev;
+(struct queued_qpu_inst *)block->qpu_inst_list.prev;
 return >inst;
 }
 
 static void
-set_last_cond_add(struct vc4_compile *c, uint32_t cond)
+set_last_cond_add(struct qblock *block, uint32_t cond)
 {
-*last_inst(c) = qpu_set_cond_add(*last_inst(c), cond);
+*last_inst(block) = qpu_set_cond_add(*last_inst(block), cond);
 }
 
 static void
-set_last_cond_mul(struct vc4_compile *c, uint32_t cond)
+set_last_cond_mul(struct qblock *block, uint32_t cond)
 {
-*last_inst(c) = qpu_set_cond_mul(*last_inst(c), cond);
+*last_inst(block) = qpu_set_cond_mul(*last_inst(block), cond);
 }
 
 /**
@@ -106,7 +106,7 @@ swap_file(struct qpu_reg *src)
  * instruction, instead.  We reserve ra31/rb31 for this purpose.
  */
 static void
-fixup_raddr_conflict(struct vc4_compile *c,
+fixup_raddr_conflict(struct qblock *block,
  struct qpu_reg dst,
  struct qpu_reg *src0, struct qpu_reg *src1,
  struct qinst *inst, uint64_t *unpack)
@@ -129,39 +129,39 @@ fixup_raddr_conflict(struct vc4_compile *c,
  * in case of unpacks.
  */
 if (qir_is_float_input(inst))
-queue(c, qpu_a_FMAX(qpu_rb(31), *src0, *src0));
+queue(block, qpu_a_FMAX(qpu_rb(31), *src0, *src0));
 else
-queue(c, qpu_a_MOV(qpu_rb(31), *src0));
+queue(block, qpu_a_MOV(qpu_rb(31), *src0));
 
 /* If we had an unpack on this A-file source, we need to put
  * it into this MOV, not into the later move from regfile B.
  */
 if (inst->src[0].pack) {
-*last_inst(c) |= *unpack;
+*last_inst(block) |= *unpack;
 *unpack = 0;
 }
 *src0 = qpu_rb(31);
 } else {
-queue(c, qpu_a_MOV(qpu_ra(31), *src0));
+queue(block, qpu_a_MOV(qpu_ra(31), *src0));
 *src0 = qpu_ra(31);
 }
 }
 
 static void
-set_last_dst_pack(struct vc4_compile *c, struct qinst *inst)
+set_last_dst_pack(struct qblock *block, struct qinst *inst)
 {
-bool had_pm =

Mesa (master): i965/eu: set DF imm value to the source of DIM

2016-07-14 Thread Samuel Iglesias Gonsálvez 
Module: Mesa
Branch: master
Commit: 0534863c477240e47f1d85616b59c31fad453ea2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0534863c477240e47f1d85616b59c31fad453ea2

Author: Samuel Iglesias Gonsálvez 
Date:   Thu Jul  7 13:55:32 2016 +0200

i965/eu: set DF imm value to the source of DIM

According to HSW's PRM, vol02b, the DIM instruction has the following
restriction:

"Restriction : src0 must be immediate. src0 must specify the :f (F, Float)
type encoding but is an immediate 64-bit DF (Double Float) value. dst
must have type DF."

This commit allows to upload the immediate 64-bit DF value to the source
of a DIM instruction even when it is of float type encoding.

Signed-off-by: Samuel Iglesias Gonsálvez 
Reviewed-by: Matt Turner 

---

 src/mesa/drivers/dri/i965/brw_eu_emit.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index f2f55410..fc187d1 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -350,7 +350,8 @@ brw_set_src0(struct brw_codegen *p, brw_inst *inst, struct 
brw_reg reg)
brw_inst_set_src0_address_mode(devinfo, inst, reg.address_mode);
 
if (reg.file == BRW_IMMEDIATE_VALUE) {
-  if (reg.type == BRW_REGISTER_TYPE_DF)
+  if (reg.type == BRW_REGISTER_TYPE_DF ||
+  brw_inst_opcode(devinfo, inst) == BRW_OPCODE_DIM)
  brw_inst_set_imm_df(devinfo, inst, reg.df);
   else
  brw_inst_set_imm_ud(devinfo, inst, reg.ud);

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Mesa (master): i965/fs: emit DIM instruction to load 64-bit immediates in HSW

2016-07-14 Thread Samuel Iglesias Gonsálvez 
Module: Mesa
Branch: master
Commit: 94135e8736f2741684e978afac9d34c368f7bcb1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=94135e8736f2741684e978afac9d34c368f7bcb1

Author: Samuel Iglesias Gonsálvez 
Date:   Thu Jul  7 09:19:43 2016 +0200

i965/fs: emit DIM instruction to load 64-bit immediates in HSW

v2 (Matt):
- Use brw_imm_df() as source argument of DIM instruction.

Signed-off-by: Samuel Iglesias Gonsálvez 
Reviewed-by: Matt Turner 

---

 src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index a65c273..129984a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -4558,6 +4558,16 @@ setup_imm_df(const fs_builder , double v)
if (devinfo->gen >= 8)
   return brw_imm_df(v);
 
+   /* gen7.5 does not support DF immediates straighforward but the DIM
+* instruction allows to set the 64-bit immediate value.
+*/
+   if (devinfo->is_haswell) {
+  const fs_builder ubld = bld.exec_all();
+  fs_reg dst = ubld.vgrf(BRW_REGISTER_TYPE_DF, 1);
+  ubld.DIM(dst, brw_imm_df(v));
+  return component(dst, 0);
+   }
+
/* gen7 does not support DF immediates, so we generate a 64-bit constant by
 * writing the low 32-bit of the constant to suboffset 0 of a VGRF and
 * the high 32-bit to suboffset 4 and then applying a stride of 0.

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Mesa (master): i965: enable the emission of the DIM instruction

2016-07-14 Thread Samuel Iglesias Gonsálvez 
Module: Mesa
Branch: master
Commit: 6e28976d35cf0a15c62bed1fd2ceeb734a3fc81e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e28976d35cf0a15c62bed1fd2ceeb734a3fc81e

Author: Samuel Iglesias Gonsálvez 
Date:   Thu Jul  7 08:38:22 2016 +0200

i965: enable the emission of the DIM instruction

v2 (Matt):
- Take a DF source argument for the DIM instruction emission
in the visitors.
- Indentation.

Signed-off-by: Samuel Iglesias Gonsálvez 
Reviewed-by: Matt Turner 

---

 src/mesa/drivers/dri/i965/brw_defines.h  | 2 +-
 src/mesa/drivers/dri/i965/brw_eu.c   | 2 +-
 src/mesa/drivers/dri/i965/brw_eu.h   | 1 +
 src/mesa/drivers/dri/i965/brw_eu_emit.c  | 1 +
 src/mesa/drivers/dri/i965/brw_fs_builder.h   | 1 +
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp   | 7 +++
 src/mesa/drivers/dri/i965/brw_vec4.h | 2 ++
 src/mesa/drivers/dri/i965/brw_vec4_builder.h | 1 +
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 7 +++
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp   | 1 +
 10 files changed, 23 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index d2cd53a..740d03d 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -857,7 +857,7 @@ enum opcode {
BRW_OPCODE_XOR =7,
BRW_OPCODE_SHR =8,
BRW_OPCODE_SHL =9,
-   // BRW_OPCODE_DIM = 10,  /**< Gen7.5 only */ /* Reused */
+   BRW_OPCODE_DIM =10,  /**< Gen7.5 only */ /* Reused */
// BRW_OPCODE_SMOV =10,  /**< Gen8+   */ /* Reused */
/* Reserved - 11 */
BRW_OPCODE_ASR =12,
diff --git a/src/mesa/drivers/dri/i965/brw_eu.c 
b/src/mesa/drivers/dri/i965/brw_eu.c
index cc252de..3a309dc 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -421,7 +421,7 @@ enum gen {
 #define GEN_LE(gen) (GEN_LT(gen) | (gen))
 
 static const struct opcode_desc opcode_10_descs[] = {
-   { .name = "dim",   .nsrc = 0, .ndst = 0, .gens = GEN75 },
+   { .name = "dim",   .nsrc = 1, .ndst = 1, .gens = GEN75 },
{ .name = "smov",  .nsrc = 0, .ndst = 0, .gens = GEN_GE(GEN8) },
 };
 
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h 
b/src/mesa/drivers/dri/i965/brw_eu.h
index b057f17..09f51db 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -157,6 +157,7 @@ ALU2(OR)
 ALU2(XOR)
 ALU2(SHR)
 ALU2(SHL)
+ALU1(DIM)
 ALU2(ASR)
 ALU1(F32TO16)
 ALU1(F16TO32)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 2a8e661..f2f55410 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -1064,6 +1064,7 @@ ALU2(OR)
 ALU2(XOR)
 ALU2(SHR)
 ALU2(SHL)
+ALU1(DIM)
 ALU2(ASR)
 ALU1(FRC)
 ALU1(RNDD)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_builder.h 
b/src/mesa/drivers/dri/i965/brw_fs_builder.h
index f22903e..8e43484 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_builder.h
+++ b/src/mesa/drivers/dri/i965/brw_fs_builder.h
@@ -460,6 +460,7 @@ namespace brw {
   ALU1(CBIT)
   ALU2(CMPN)
   ALU3(CSEL)
+  ALU1(DIM)
   ALU2(DP2)
   ALU2(DP3)
   ALU2(DP4)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index ce1ec0a..1e9c7da 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -2082,6 +2082,13 @@ fs_generator::generate_code(const cfg_t *cfg, int 
dispatch_width)
 generate_barrier(inst, src[0]);
 break;
 
+  case BRW_OPCODE_DIM:
+ assert(devinfo->is_haswell);
+ assert(src[0].type == BRW_REGISTER_TYPE_DF);
+ assert(dst.type == BRW_REGISTER_TYPE_DF);
+ brw_DIM(p, dst, retype(src[0], BRW_REGISTER_TYPE_F));
+ break;
+
   default:
  unreachable("Unsupported opcode");
 
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 76dea04..3043147 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -213,6 +213,8 @@ public:
EMIT3(MAD)
EMIT2(ADDC)
EMIT2(SUBB)
+   EMIT1(DIM)
+
 #undef EMIT1
 #undef EMIT2
 #undef EMIT3
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_builder.h 
b/src/mesa/drivers/dri/i965/brw_vec4_builder.h
index 3a8617e..d25a87a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_builder.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4_builder.h
@@ -373,6 +373,7 @@ namespace brw {
   ALU1(CBIT)
   ALU2(CMPN)
   ALU3(CSEL)
+  ALU1(DIM)
   ALU2(DP2)
   ALU2(DP3)
   ALU2(DP4)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index bb0254e..3878c4a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++