Mesa (master): nvc0: add support for BGRA8 images

2016-07-18 Thread Ilia Mirkin 
Module: Mesa
Branch: master
Commit: 8e7893eb53213254997a1a3beb0575be11821f83
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e7893eb53213254997a1a3beb0575be11821f83

Author: Ilia Mirkin 
Date:   Sat Jul 16 15:07:21 2016 -0400

nvc0: add support for BGRA8 images

This is useful for pbo downloads, which are now accelerated with images.
BGRA8 is a moderately common format to do that in.

Signed-off-by: Ilia Mirkin 
Reviewed-by: Samuel Pitoiset 

---

 src/gallium/drivers/nouveau/codegen/nv50_ir.cpp   | 2 ++
 src/gallium/drivers/nouveau/codegen/nv50_ir.h | 3 +++
 src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 2 ++
 src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 4 
 src/gallium/drivers/nouveau/nv50/g80_defs.xml.h   | 1 +
 src/gallium/drivers/nouveau/nv50/nv50_formats.c   | 3 ++-
 src/gallium/drivers/nouveau/nvc0/nvc0_tex.c   | 2 ++
 7 files changed, 16 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
index 2caebe8..179ad0b 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.cpp
@@ -1012,6 +1012,8 @@ const struct TexInstruction::ImgFormatDesc 
TexInstruction::formatTable[] =
{ "RG8_SNORM",2, {  8,  8,  0,  0 }, SNORM },
{ "R16_SNORM",1, { 16,  0,  0,  0 }, SNORM },
{ "R8_SNORM", 1, {  8,  0,  0,  0 }, SNORM },
+
+   { "BGRA8",4, {  8,  8,  8,  8 }, UNORM, true },
 };
 
 void
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir.h 
b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
index 41804b6..6d2ee8b 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir.h
@@ -412,6 +412,8 @@ enum ImgFormat
FMT_R16_SNORM,
FMT_R8_SNORM,
 
+   FMT_BGRA8,
+
IMG_FORMAT_COUNT,
 };
 
@@ -967,6 +969,7 @@ public:
   uint8_t components;
   uint8_t bits[4];
   ImgType type;
+  bool bgra;
};
 
static const struct ImgFormatDesc formatTable[IMG_FORMAT_COUNT];
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 61eb7f5..7dff08a 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -508,6 +508,8 @@ static nv50_ir::ImgFormat translateImgFormat(uint format)
FMT_CASE(R8G8_SNORM, RG8_SNORM);
FMT_CASE(R16_SNORM, R16_SNORM);
FMT_CASE(R8_SNORM, R8_SNORM);
+
+   FMT_CASE(B8G8R8A8_UNORM, BGRA8);
}
 
assert(!"Unexpected format");
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
index 18955eb..92bc0bb 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp
@@ -1940,6 +1940,10 @@ NVC0LoweringPass::convertSurfaceFormat(TexInstruction 
*su)
  bld.mkCvt(OP_CVT, TYPE_F32, typedDst[i], TYPE_F16, typedDst[i]);
   }
}
+
+   if (format->bgra) {
+  std::swap(typedDst[0], typedDst[2]);
+   }
 }
 
 void
diff --git a/src/gallium/drivers/nouveau/nv50/g80_defs.xml.h 
b/src/gallium/drivers/nouveau/nv50/g80_defs.xml.h
index 5d40624..49bf860 100644
--- a/src/gallium/drivers/nouveau/nv50/g80_defs.xml.h
+++ b/src/gallium/drivers/nouveau/nv50/g80_defs.xml.h
@@ -177,6 +177,7 @@ WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 
SOFTWARE.
 #define GK104_IMAGE_FORMAT_RG32_FLOAT  0x000d
 #define GK104_IMAGE_FORMAT_RG32_SINT   0x000e
 #define GK104_IMAGE_FORMAT_RG32_UINT   0x000f
+#define GK104_IMAGE_FORMAT_BGRA8_UNORM 0x0011
 #define GK104_IMAGE_FORMAT_RGB10_A2_UNORM  0x0013
 #define GK104_IMAGE_FORMAT_RGB10_A2_UINT   0x0015
 #define GK104_IMAGE_FORMAT_RGBA8_UNORM 0x0018
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_formats.c 
b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
index 34d32d1..07c4419 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_formats.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
@@ -50,6 +50,7 @@
 #define U_IB  PIPE_BIND_BLENDABLE | U_IR
 #define U_TD  PIPE_BIND_SCANOUT | PIPE_BIND_DISPLAY_TARGET | U_TB
 #define U_TZ  PIPE_BIND_DEPTH_STENCIL | U_T
+#define U_ID  U_TD | U_I
 #if NOUVEAU_DRIVER == 0xc0
 # define U_TC  U_TB
 # define U_IC  U_IB
@@ -122,7 +123,7 @@ const struct nvc0_format 
nvc0_format_table[PIPE_FORMAT_COUNT] =
 const struct nv50_format nv50_format_table[PIPE_FORMAT_COUNT] =
 #endif
 {
-   C4(A, B8G8R8A8_UNORM, BGRA8_UNORM, B, G, R, A, UNORM, A8B8G8R8, TD),
+   C4(A, B8G8R8A8_UNORM, BGRA8_UNORM, B, G,

Mesa (master): nv50, nvc0: srgb rendering is only available for rgba/bgra

2016-07-18 Thread Ilia Mirkin 
Module: Mesa
Branch: master
Commit: ed9dd3bcd9990b321f523823287643cbf893949f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed9dd3bcd9990b321f523823287643cbf893949f

Author: Ilia Mirkin 
Date:   Sun Jul 17 17:14:24 2016 -0400

nv50,nvc0: srgb rendering is only available for rgba/bgra

Mark both L8_SRGB and L8A8_SRGB as non-renderable (the latter already
didn't have the bind flags). This makes the state tracker pick a
different format when rendering is required, or mark the fb as
incomplete. This fixes:

  bin/getteximage-formats init-by-clear-and-render -auto -fbo
  bin/getteximage-formats init-by-rendering -auto -fbo

which previously ran into srgb-encoding differences.

Signed-off-by: Ilia Mirkin 
Reviewed-by: Samuel Pitoiset 
Cc: mesa-sta...@lists.freedesktop.org

---

 src/gallium/drivers/nouveau/nv50/nv50_formats.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_formats.c 
b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
index 07c4419..a95641f 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_formats.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_formats.c
@@ -162,7 +162,7 @@ const struct nv50_format 
nv50_format_table[PIPE_FORMAT_COUNT] =
F3(A, R11G11B10_FLOAT, R11G11B10_FLOAT, R, G, B, xx, FLOAT, BF10GF11RF11, 
IB),
 
F3(A, L8_UNORM, R8_UNORM, R, R, R, xx, UNORM, R8, TB),
-   F3(A, L8_SRGB, R8_UNORM, R, R, R, xx, UNORM, R8, TB),
+   F3(A, L8_SRGB, NONE, R, R, R, xx, UNORM, R8, T),
F3(A, L8_SNORM, R8_SNORM, R, R, R, xx, SNORM, R8, TC),
I3(A, L8_SINT, R8_SINT, R, R, R, xx, SINT, R8, TR),
I3(A, L8_UINT, R8_UINT, R, R, R, xx, UINT, R8, TR),
@@ -204,7 +204,7 @@ const struct nv50_format 
nv50_format_table[PIPE_FORMAT_COUNT] =
C4(A, L4A4_UNORM, NONE, R, R, R, G, UNORM, G4R4, T),
C4(A, L8A8_UNORM, RG8_UNORM, R, R, R, G, UNORM, G8R8, T),
C4(A, L8A8_SNORM, RG8_SNORM, R, R, R, G, SNORM, G8R8, T),
-   C4(A, L8A8_SRGB, RG8_UNORM, R, R, R, G, UNORM, G8R8, T),
+   C4(A, L8A8_SRGB, NONE, R, R, R, G, UNORM, G8R8, T),
C4(A, L8A8_SINT, RG8_SINT, R, R, R, G, SINT, G8R8, T),
C4(A, L8A8_UINT, RG8_UINT, R, R, R, G, UINT, G8R8, T),
C4(A, L16A16_UNORM, RG16_UNORM, R, R, R, G, UNORM, R16_G16, T),

___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit

Mesa (master): i965: Skip update_texture_surface when the plane doesn' t exist

2016-07-18 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: 905d7dc4d164b7ccc287b390a5b2492da3e0fd8b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=905d7dc4d164b7ccc287b390a5b2492da3e0fd8b

Author: Jason Ekstrand 
Date:   Mon Jul 18 09:13:01 2016 -0700

i965: Skip update_texture_surface when the plane doesn't exist

Thanks to rebase fail, recent surface state changes (commits 7e951cd56,
8521ce1a7, and 69c0dc5c53) effectively reverted 727a9b24933 and 367cf3a2e3e
which was unintentional.  This should bring it back.

Signed-off-by: Jason Ekstrand 
Reviewed-by: Jordan Justen 

---

 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 18 ++
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index c1a7579..d896789 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -385,6 +385,13 @@ brw_update_texture_surface(struct gl_context *ctx,
} else {
   struct intel_texture_object *intel_obj = intel_texture_object(obj);
   struct intel_mipmap_tree *mt = intel_obj->mt;
+
+  if (plane > 0) {
+ if (mt->plane[plane - 1] == NULL)
+return;
+ mt = mt->plane[plane - 1];
+  }
+
   struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
   /* If this is a view with restricted NumLayers, then our effective depth
* is not just the miptree depth.
@@ -406,8 +413,9 @@ brw_update_texture_surface(struct gl_context *ctx,
   const unsigned swizzle = (unlikely(alpha_depth) ? SWIZZLE_XYZW :
 brw_get_texture_swizzle(>ctx, obj));
 
-  unsigned format = translate_tex_format(
- brw, intel_obj->_Format, sampler->sRGBDecode);
+  mesa_format mesa_fmt = plane == 0 ? intel_obj->_Format : mt->format;
+  unsigned format = translate_tex_format(brw, mesa_fmt,
+ sampler->sRGBDecode);
 
   /* Implement gen6 and gen7 gather work-around */
   bool need_green_to_blue = false;
@@ -449,12 +457,6 @@ brw_update_texture_surface(struct gl_context *ctx,
  assert(brw->gen >= 8);
  mt = mt->stencil_mt;
  format = BRW_SURFACEFORMAT_R8_UINT;
-  } else if (obj->Target == GL_TEXTURE_EXTERNAL_OES) {
- if (plane > 0)
-mt = mt->plane[plane - 1];
- if (mt == NULL)
-return;
- format = translate_tex_format(brw, mt->format, sampler->sRGBDecode);
   }
 
   const int surf_index = surf_offset - >wm.base.surf_offset[0];

___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit

Mesa (master): glsl: use linked shaders rather than compiled shaders

2016-07-18 Thread Timothy Arceri 
Module: Mesa
Branch: master
Commit: cd5cbf0f6b69557ef0c6123c11f9732d43490f4f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd5cbf0f6b69557ef0c6123c11f9732d43490f4f

Author: Timothy Arceri 
Date:   Mon Jul 11 12:11:42 2016 +1000

glsl: use linked shaders rather than compiled shaders

At this point there is no reason not to be using the linked shaders,
using the linked shaders should be faster and will make things simpler
for upcoming shader cache work.

The previous variable name suggests the linked shaders were intended
to be used here anyway.

Reviewed-by: Iago Toral Quiroga 

---

 src/compiler/glsl/linker.cpp | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index d963f54..6d45a02 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -4112,12 +4112,12 @@ calculate_array_size_and_stride(struct 
gl_shader_program *shProg,
   }
}
 
-   for (unsigned i = 0; i < shProg->NumShaders; i++) {
-  if (shProg->Shaders[i] == NULL)
+   for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
+  const gl_linked_shader *sh = shProg->_LinkedShaders[i];
+  if (sh == NULL)
  continue;
 
-  const gl_shader *stage = shProg->Shaders[i];
-  foreach_in_list(ir_instruction, node, stage->ir) {
+  foreach_in_list(ir_instruction, node, sh->ir) {
  ir_variable *var = node->as_variable();
  if (!var || !var->get_interface_type() ||
  var->data.mode != ir_var_shader_storage)

___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit

Mesa (master): The extension is already exposed, this simply marks it as done.

2016-07-18 Thread Roland Scheidegger 
Module: Mesa
Branch: master
Commit: 198074a41c20300373ec4f906a34da89cad63fbf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=198074a41c20300373ec4f906a34da89cad63fbf

Author: Lars Hamre 
Date:   Tue Jul 19 01:20:27 2016 +0200

The extension is already exposed, this simply marks it as done.

Signed-off-by: Lars Hamre 
Reviewed-by: Roland Scheidegger 

---

 docs/GL3.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index ce34869..1335397 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -171,7 +171,7 @@ GL 4.3, GLSL 4.30 -- all DONE: nvc0, radeonsi
   GL_ARB_copy_image DONE (i965, nv50, 
r600, softpipe, llvmpipe)
   GL_KHR_debug  DONE (all drivers)
   GL_ARB_explicit_uniform_location  DONE (all drivers that 
support GLSL)
-  GL_ARB_fragment_layer_viewportDONE (i965, nv50, 
r600, llvmpipe)
+  GL_ARB_fragment_layer_viewportDONE (i965, nv50, 
r600, llvmpipe, softpipe)
   GL_ARB_framebuffer_no_attachments DONE (i965, r600, 
softpipe)
   GL_ARB_internalformat_query2  DONE (all drivers)
   GL_ARB_invalidate_subdata DONE (all drivers)

___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit

Mesa (master): docs: Fix typo in extension name

2016-07-18 Thread Anuj Phogat 
Module: Mesa
Branch: master
Commit: 22935a304076bfc5c2f7a4e348c24707f2c866e1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=22935a304076bfc5c2f7a4e348c24707f2c866e1

Author: Anuj Phogat 
Date:   Mon Jul 18 15:53:24 2016 -0700

docs: Fix typo in extension name

Signed-off-by: Anuj Phogat 

---

 docs/relnotes/12.1.0.html | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/relnotes/12.1.0.html b/docs/relnotes/12.1.0.html
index 50d93c2..e7c3a52 100644
--- a/docs/relnotes/12.1.0.html
+++ b/docs/relnotes/12.1.0.html
@@ -47,7 +47,7 @@ Note: some of the new features are only available with 
certain drivers.
 GL_ARB_shader_group_vote on nvc0
 GL_ARB_ES3_1_compatibility on i965
 GL_EXT_window_rectangles on nv50, nvc0
-KHR_texture_compression_astc_sliced_3d on i965
+GL_KHR_texture_compression_astc_sliced_3d on i965
 
 
 Bug fixes

___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit

Mesa (master): Revert "docs: Mark KHR_texture_compression_astc_sliced_3d done on i965"

2016-07-18 Thread Anuj Phogat 
Module: Mesa
Branch: master
Commit: c7b787ef90c4740f0a36f218c31f9d0364236cd9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c7b787ef90c4740f0a36f218c31f9d0364236cd9

Author: Anuj Phogat 
Date:   Mon Jul 18 15:17:53 2016 -0700

Revert "docs: Mark KHR_texture_compression_astc_sliced_3d done on i965"

This reverts commit 82f8c239506ef126dcad266156f8945c62dc6bc9.

KHR_texture_compression_astc_sliced_3d is not a requirement for
GLES 3.2.

Reported-by: Ilia Mirkin \
Signed-off-by: Anuj Phogat 

---

 docs/GL3.txt | 1 -
 1 file changed, 1 deletion(-)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index 883604a..ce34869 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -255,7 +255,6 @@ GLES3.2, GLSL ES 3.2
   GL_KHR_debug  DONE (all drivers)
   GL_KHR_robustness DONE (i965)
   GL_KHR_texture_compression_astc_ldr   DONE (i965/gen9+)
-  GL_KHR_texture_compression_astc_sliced_3d DONE (i965/gen9+)
   GL_OES_copy_image DONE (i965)
   GL_OES_draw_buffers_indexed   DONE (all drivers that 
support GL_ARB_draw_buffers_blend)
   GL_OES_draw_elements_base_vertex  DONE (all drivers)

___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit

Mesa (master): docs: Add support for GL_KHR_texture_compression_astc_sliced_3d

2016-07-18 Thread Anuj Phogat 
Module: Mesa
Branch: master
Commit: 7832e188795557348b6198fcb7ecca1966679527
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7832e188795557348b6198fcb7ecca1966679527

Author: Anuj Phogat 
Date:   Mon Jul 18 15:42:18 2016 -0700

docs: Add support for GL_KHR_texture_compression_astc_sliced_3d

Signed-off-by: Anuj Phogat 
Reported-by: Ilia Mirkin 

---

 docs/relnotes/12.1.0.html | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/relnotes/12.1.0.html b/docs/relnotes/12.1.0.html
index 096f551..50d93c2 100644
--- a/docs/relnotes/12.1.0.html
+++ b/docs/relnotes/12.1.0.html
@@ -47,6 +47,7 @@ Note: some of the new features are only available with 
certain drivers.
 GL_ARB_shader_group_vote on nvc0
 GL_ARB_ES3_1_compatibility on i965
 GL_EXT_window_rectangles on nv50, nvc0
+KHR_texture_compression_astc_sliced_3d on i965
 
 
 Bug fixes

___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit

Mesa (master): i965/gen9: Enable KHR_texture_compression_astc_sliced_3d

2016-07-18 Thread Anuj Phogat 
Module: Mesa
Branch: master
Commit: ac0eb36d8e82abc5590773d045c6b63d9be6949a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac0eb36d8e82abc5590773d045c6b63d9be6949a

Author: Anuj Phogat 
Date:   Thu Jul  7 17:04:17 2016 -0700

i965/gen9: Enable KHR_texture_compression_astc_sliced_3d

Signed-off-by: Anuj Phogat 
Reviewed-by: Nanley Chery 

---

 src/mesa/drivers/dri/i965/intel_extensions.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 27dfb0c..c557137 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -391,6 +391,7 @@ intelInitExtensions(struct gl_context *ctx)
 
if (brw->gen >= 9) {
   ctx->Extensions.KHR_texture_compression_astc_ldr = true;
+  ctx->Extensions.KHR_texture_compression_astc_sliced_3d = true;
   ctx->Extensions.ARB_shader_stencil_export = true;
}
 

___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit

Mesa (master): docs: Mark KHR_texture_compression_astc_sliced_3d done on i965

2016-07-18 Thread Anuj Phogat 
Module: Mesa
Branch: master
Commit: 82f8c239506ef126dcad266156f8945c62dc6bc9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=82f8c239506ef126dcad266156f8945c62dc6bc9

Author: Anuj Phogat 
Date:   Thu Jul  7 17:05:02 2016 -0700

docs: Mark KHR_texture_compression_astc_sliced_3d done on i965

Signed-off-by: Anuj Phogat 
Reviewed-by: Nanley Chery 

---

 docs/GL3.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index ce34869..883604a 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -255,6 +255,7 @@ GLES3.2, GLSL ES 3.2
   GL_KHR_debug  DONE (all drivers)
   GL_KHR_robustness DONE (i965)
   GL_KHR_texture_compression_astc_ldr   DONE (i965/gen9+)
+  GL_KHR_texture_compression_astc_sliced_3d DONE (i965/gen9+)
   GL_OES_copy_image DONE (i965)
   GL_OES_draw_buffers_indexed   DONE (all drivers that 
support GL_ARB_draw_buffers_blend)
   GL_OES_draw_elements_base_vertex  DONE (all drivers)

___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit

Mesa (master): mesa: Add the infrastructure for KHR_texture_compression_astc_sliced_3d

2016-07-18 Thread Anuj Phogat 
Module: Mesa
Branch: master
Commit: 15dea5ca82f45f9b1113e69fe2048b6f05ed426b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=15dea5ca82f45f9b1113e69fe2048b6f05ed426b

Author: Anuj Phogat 
Date:   Thu Jul  7 17:03:19 2016 -0700

mesa: Add the infrastructure for KHR_texture_compression_astc_sliced_3d

V2: Drop the changes to gl.xml.

Signed-off-by: Anuj Phogat 
Reviewed-by: Nanley Chery 

---

 src/mesa/main/extensions_table.h | 1 +
 src/mesa/main/mtypes.h   | 1 +
 src/mesa/main/teximage.c | 7 ---
 3 files changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index ad3bffc..6c47b3b 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -285,6 +285,7 @@ EXT(KHR_robust_buffer_access_behavior   , 
ARB_robust_buffer_access_behavior
 EXT(KHR_robustness  , KHR_robustness   
  , GLL, GLC,  x , ES2, 2012)
 EXT(KHR_texture_compression_astc_hdr, KHR_texture_compression_astc_hdr 
  , GLL, GLC,  x , ES2, 2012)
 EXT(KHR_texture_compression_astc_ldr, KHR_texture_compression_astc_ldr 
  , GLL, GLC,  x , ES2, 2012)
+EXT(KHR_texture_compression_astc_sliced_3d  , 
KHR_texture_compression_astc_sliced_3d , GLL, GLC,  x , ES2, 2015)
 
 EXT(MESA_pack_invert, MESA_pack_invert 
  , GLL, GLC,  x ,  x , 2002)
 EXT(MESA_texture_signed_rgba, EXT_texture_snorm
  , GLL, GLC,  x ,  x , 2009)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 3dae168..ecc5b49 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -3946,6 +3946,7 @@ struct gl_extensions
GLboolean KHR_robustness;
GLboolean KHR_texture_compression_astc_hdr;
GLboolean KHR_texture_compression_astc_ldr;
+   GLboolean KHR_texture_compression_astc_sliced_3d;
GLboolean MESA_pack_invert;
GLboolean MESA_ycbcr_texture;
GLboolean NV_conditional_render;
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index d74a45f..8869b3d 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -1447,11 +1447,12 @@ _mesa_target_can_be_compressed(const struct gl_context 
*ctx, GLenum target,
  break;
   case MESA_FORMAT_LAYOUT_ASTC:
  target_can_be_compresed =
- ctx->Extensions.KHR_texture_compression_astc_hdr;
+ctx->Extensions.KHR_texture_compression_astc_hdr ||
+ctx->Extensions.KHR_texture_compression_astc_sliced_3d;
 
  /* Throw an INVALID_OPERATION error if the target is TEXTURE_3D and
-  * and the hdr extension is not supported.
-  * See comment in switch case GL_TEXTURE_CUBE_MAP_ARRAY for more info.
+  * neither of the above extensions are supported. See comment in
+  * switch case GL_TEXTURE_CUBE_MAP_ARRAY for more info.
   */
  if (!target_can_be_compresed)
 return write_error(error, GL_INVALID_OPERATION);

___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit

Mesa (master): radeon/uvd: add session context buffer for polaris 10/11 v2

2016-07-18 Thread Christian König 
Module: Mesa
Branch: master
Commit: 3e1ad846f9c2f3516861d03ba99c4cb22f5f1b6e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e1ad846f9c2f3516861d03ba99c4cb22f5f1b6e

Author: Christian König 
Date:   Thu Jul  7 14:28:06 2016 +0200

radeon/uvd: add session context buffer for polaris 10/11 v2

This way we have unlimited UVD sessions.

v2: only enable it when kernel supports it as well.

Signed-off-by: Christian König 
Reviewed-by: Leo Liu 

---

 src/gallium/drivers/radeon/radeon_uvd.c | 20 
 src/gallium/drivers/radeon/radeon_uvd.h |  1 +
 2 files changed, 21 insertions(+)

diff --git a/src/gallium/drivers/radeon/radeon_uvd.c 
b/src/gallium/drivers/radeon/radeon_uvd.c
index 10bed7c..d5d654a 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -59,6 +59,7 @@
 #define FB_BUFFER_SIZE 2048
 #define FB_BUFFER_SIZE_TONGA (2048 * 64)
 #define IT_SCALING_TABLE_SIZE 992
+#define UVD_SESSION_CONTEXT_SIZE (128 * 1024)
 
 /* UVD decoder representation */
 struct ruvd_decoder {
@@ -89,6 +90,7 @@ struct ruvd_decoder {
struct rvid_buffer  dpb;
booluse_legacy;
struct rvid_buffer  ctx;
+   struct rvid_buffer  sessionctx;
 };
 
 /* flush IB to the hardware */
@@ -170,6 +172,12 @@ static void send_msg_buf(struct ruvd_decoder *dec)
dec->fb = NULL;
dec->it = NULL;
 
+
+   if (dec->sessionctx.res)
+   send_cmd(dec, RUVD_CMD_SESSION_CONTEXT_BUFFER,
+dec->sessionctx.res->buf, 0, RADEON_USAGE_READWRITE,
+RADEON_DOMAIN_VRAM);
+
/* and send it to the hardware */
send_cmd(dec, RUVD_CMD_MSG_BUFFER, buf->res->buf, 0,
 RADEON_USAGE_READ, RADEON_DOMAIN_GTT);
@@ -938,6 +946,7 @@ static void ruvd_destroy(struct pipe_video_codec *decoder)
 
rvid_destroy_buffer(>dpb);
rvid_destroy_buffer(>ctx);
+   rvid_destroy_buffer(>sessionctx);
 
FREE(dec);
 }
@@ -1259,6 +1268,16 @@ struct pipe_video_codec *ruvd_create_decoder(struct 
pipe_context *context,
rvid_clear_buffer(context, >ctx);
}
 
+   if (info.family >= CHIP_POLARIS10 && info.drm_minor >= 3) {
+   if (!rvid_create_buffer(dec->screen, >sessionctx,
+   UVD_SESSION_CONTEXT_SIZE,
+   PIPE_USAGE_DEFAULT)) {
+   RVID_ERR("Can't allocated session ctx.\n");
+   goto error;
+   }
+   rvid_clear_buffer(context, >sessionctx);
+   }
+
map_msg_fb_it_buf(dec);
dec->msg->size = sizeof(*dec->msg);
dec->msg->msg_type = RUVD_MSG_CREATE;
@@ -1286,6 +1305,7 @@ error:
 
rvid_destroy_buffer(>dpb);
rvid_destroy_buffer(>ctx);
+   rvid_destroy_buffer(>sessionctx);
 
FREE(dec);
 
diff --git a/src/gallium/drivers/radeon/radeon_uvd.h 
b/src/gallium/drivers/radeon/radeon_uvd.h
index bb1782a..e3f8504 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.h
+++ b/src/gallium/drivers/radeon/radeon_uvd.h
@@ -61,6 +61,7 @@
 #define RUVD_CMD_DPB_BUFFER0x0001
 #define RUVD_CMD_DECODING_TARGET_BUFFER0x0002
 #define RUVD_CMD_FEEDBACK_BUFFER   0x0003
+#define RUVD_CMD_SESSION_CONTEXT_BUFFER0x0005
 #define RUVD_CMD_BITSTREAM_BUFFER  0x0100
 #define RUVD_CMD_ITSCALING_TABLE_BUFFER0x0204
 #define RUVD_CMD_CONTEXT_BUFFER0x0206

___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit

Mesa (master): vl/dri3: fix a memory leak from front buffer

2016-07-18 Thread Leo Liu 
Module: Mesa
Branch: master
Commit: 134d6e4e4f980d738361bfcae1daedb8cc58b5df
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=134d6e4e4f980d738361bfcae1daedb8cc58b5df

Author: Leo Liu 
Date:   Thu Jul 14 09:19:59 2016 -0400

vl/dri3: fix a memory leak from front buffer

Inspired by fix for mem leak of vdpau interop, resource_from_handle
set texture reference count, that need to be decreased and released,
recall there is a similar case for DRI3, that is with VA-API glx
extension, there is temporary TFP(texture from pixmap), we target it
through dma-buf. leak happens when without count down the reference.

Checked and found with mpv vo=opengl case, there only one static TFP,
the leak happens once, but for totem player using gstreamer VA-API glx,
the dynamic TFP for each frame, so leak quite a bit.

This fixes mem leak for mpv and totem.

Signed-off-by: Leo Liu 
Cc: "12.0" 

---

 src/gallium/auxiliary/vl/vl_winsys_dri3.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/auxiliary/vl/vl_winsys_dri3.c 
b/src/gallium/auxiliary/vl/vl_winsys_dri3.c
index f7f572e..493e645 100644
--- a/src/gallium/auxiliary/vl/vl_winsys_dri3.c
+++ b/src/gallium/auxiliary/vl/vl_winsys_dri3.c
@@ -89,6 +89,7 @@ dri3_free_front_buffer(struct vl_dri3_screen *scrn,
 {
xcb_sync_destroy_fence(scrn->conn, buffer->sync_fence);
xshmfence_unmap_shm(buffer->shm_fence);
+   pipe_resource_reference(>texture, NULL);
FREE(buffer);
 }
 

___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit

Mesa (master): i965/tcs/scalar: only update imm_offset for second message in 64bit input loads

2016-07-18 Thread Iago Toral Quiroga 
Module: Mesa
Branch: master
Commit: 1737e75bfb85eb22a30e4f1c69a825b3abd946f6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1737e75bfb85eb22a30e4f1c69a825b3abd946f6

Author: Iago Toral Quiroga 
Date:   Fri Jul 15 10:48:03 2016 +0200

i965/tcs/scalar: only update imm_offset for second message in 64bit input loads

Our indirect URB read messages take both a direct and an indirect offset
so when we emit the second message for a 64-bit input load we can just
always incremement the immediate offset, even for the indirect case.

Reviewed-by: Timothy Arceri 

---

 src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 8 +---
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index 5442b73..f3c8430 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -2509,13 +2509,7 @@ fs_visitor::nir_emit_tcs_intrinsic(const fs_builder ,
   */
  if (num_iterations > 1) {
 num_components = instr->num_components - 2;
-if (indirect_offset.file == BAD_FILE) {
-   imm_offset++;
-} else {
-   fs_reg new_indirect = bld.vgrf(BRW_REGISTER_TYPE_UD, 1);
-   bld.ADD(new_indirect, indirect_offset, brw_imm_ud(1u));
-   indirect_offset = new_indirect;
-}
+imm_offset++;
  }
   }
   break;

___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit

Mesa (master): i965/tes/scalar: fix 64-bit indirect input loads

2016-07-18 Thread Iago Toral Quiroga 
Module: Mesa
Branch: master
Commit: 0f2516d88f6607b2816445c2dc18607cdaf1beff
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0f2516d88f6607b2816445c2dc18607cdaf1beff

Author: Iago Toral Quiroga 
Date:   Fri Jul 15 10:55:05 2016 +0200

i965/tes/scalar: fix 64-bit indirect input loads

We totally ignored this before because there were no piglit tests for
indirect loads in tessellation stages with doubles.

Reviewed-by: Timothy Arceri 

---

 src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 86 
 1 file changed, 64 insertions(+), 22 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
index f3c8430..6265dc6 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_nir.cpp
@@ -2928,31 +2928,73 @@ fs_visitor::nir_emit_tes_intrinsic(const fs_builder 
,
  }
   } else {
  /* Indirect indexing - use per-slot offsets as well. */
- const fs_reg srcs[] = {
-retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD),
-indirect_offset
- };
- fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, 2);
- bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
 
- if (first_component != 0) {
-unsigned read_components =
-instr->num_components + first_component;
-fs_reg tmp = bld.vgrf(dest.type, read_components);
-inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, tmp,
-payload);
-inst->regs_written = read_components;
-for (unsigned i = 0; i < instr->num_components; i++) {
-   bld.MOV(offset(dest, bld, i),
-   offset(tmp, bld, i + first_component));
+ /* We can only read two double components with each URB read, so
+  * we send two read messages in that case, each one loading up to
+  * two double components.
+  */
+ unsigned num_iterations = 1;
+ unsigned num_components = instr->num_components;
+ fs_reg orig_dest = dest;
+ if (type_sz(dest.type) == 8) {
+if (instr->num_components > 2) {
+   num_iterations = 2;
+   num_components = 2;
+}
+fs_reg tmp = fs_reg(VGRF, alloc.allocate(4), dest.type);
+dest = tmp;
+ }
+
+ for (unsigned iter = 0; iter < num_iterations; iter++) {
+const fs_reg srcs[] = {
+   retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UD),
+   indirect_offset
+};
+fs_reg payload = bld.vgrf(BRW_REGISTER_TYPE_UD, 2);
+bld.LOAD_PAYLOAD(payload, srcs, ARRAY_SIZE(srcs), 0);
+
+if (first_component != 0) {
+   unsigned read_components =
+   num_components + first_component;
+   fs_reg tmp = bld.vgrf(dest.type, read_components);
+   inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, tmp,
+   payload);
+   for (unsigned i = 0; i < num_components; i++) {
+  bld.MOV(offset(dest, bld, i),
+  offset(tmp, bld, i + first_component));
+   }
+} else {
+   inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dest,
+   payload);
+}
+inst->mlen = 2;
+inst->offset = imm_offset;
+inst->regs_written =
+   ((num_components + first_component) * type_sz(dest.type) / 4);
+
+/* If we are reading 64-bit data using 32-bit read messages we need
+ * build proper 64-bit data elements by shuffling the low and high
+ * 32-bit components around like we do for other things like UBOs
+ * or SSBOs.
+ */
+if (type_sz(dest.type) == 8) {
+   shuffle_32bit_load_result_to_64bit_data(
+  bld, dest, retype(dest, BRW_REGISTER_TYPE_F), 
num_components);
+
+   for (unsigned c = 0; c < num_components; c++) {
+  bld.MOV(offset(orig_dest, bld, iter * 2 + c),
+  offset(dest, bld, c));
+   }
+}
+
+/* If we are loading double data and we need a second read message
+ * adjust the offset
+ */
+if (num_iterations > 1) {
+   num_components = instr->num_components - 2;
+   imm_offset++;
 }
- } else {
-inst = bld.emit(SHADER_OPCODE_URB_READ_SIMD8_PER_SLOT, dest,
-payload);
-inst->regs_written = instr->num_components;
  }
- inst->mlen = 2;
- inst->offset = imm_offset;
   }
   break;
}

___
mesa-commit mailing list