Mesa (master): 24 new commits

[Jason Ekstrand]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1e49be71360a5a6124b5e7911b98d1887911e41
Author: Jason Ekstrand 
Date:   Thu Sep 8 21:34:16 2016 -0700

i965: Use blorp_copy for all copy_image operations on gen6+

Signed-off-by: Jason Ekstrand 
Reviewed-by: Chad Versace 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=540395bf9bba2a255809328d019b58a318e19c83
Author: Jason Ekstrand 
Date:   Thu Sep 8 21:27:01 2016 -0700

i965/blorp: Add a copy_miptrees helper

Signed-off-by: Jason Ekstrand 
Reviewed-by: Chad Versace 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d038adca0eae173be0d2082f9b6d7e6d7c8aadf1
Author: Jason Ekstrand 
Date:   Thu Sep 8 22:18:47 2016 -0700

intel/isl: Add support for RGB formats in X and Y-tiled memory

Normally, using a non-linear tiling format helps improve cache locality by
ensuring that neighboring pixels are usually close-by in memory.  For RGB
formats, this still sort-of holds, but it can also lead to rather terrible
memory access patterns where a single RGB pixel value crosses a tile
boundary and gets split into two pieces in different 4K pages.  It also
makes for some rather awkward calculations because your tile size is no
longer an even multiple of surface element size.  For these reasons, we
chose to simply never create tiled RGB images in the Vulkan driver.

The GL driver, however, is not so kind so we need to support it somehow.  I
briefly toyed with a couple of different schemes but this is the best one I
could come up with.  The fundamental problem is that a tile no longer
contains an integer number of surface elements.  I briefly considered a
couple other options but found them wanting:

 1) Using floats for the logical tile size.  This leads to potential
rounding error problems.

 2) When presented with a RGB format, just make the tile 3-times as wide.
This isn't so nice because now our tiles are no longer power-of-two
size.  Also, it can force the row_pitch to be larger than needed which,
while not strictly a problem for ISL, causes incompatibility problems
with the way the GL driver chooses surface pitches.

The chosen method requires that you pay attention and not just assume that
your tile_info is in the units you think it is.  However, it's nice because
it provides a nice "these are the units" declaration in isl_tile_info
itself.  Previously, the tile_info wasn't usable as a stand-alone structure
because you had to also know the format.  It also forces figuring out how
to deal with inconsistencies between tiling and format back to the caller
which is good because the two different consumers of isl_tile_info really
want to deal with it differently:  Computation of the surface size wants
the fewest number of horizontal tiles possible while get_intratile_offset
is far more concerned with things aligning nicely.

Signed-off-by: Jason Ekstrand 
Acked-by: Chad Versace 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=883086500b130e4667108a52bca9f37defcd7564
Author: Jason Ekstrand 
Date:   Fri Sep 9 08:57:14 2016 -0700

intel/isl: Allow valign2 for texture-only Y-tiled surfaces on gen7

The restriction that Y-tiled surfaces must have valign == 4 only aplies to
render targets but we were applying it universally.  This causes problems
if ISL_FORMAT_R32G32B32_FLOAT is used because it requires valign == 2; this
should be okay because you can't render to that format.

Signed-off-by: Jason Ekstrand 
Reviewed-by: Chad Versace 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=54db5afd2c8bd3a32658b3fef698c6896f6a297b
Author: Jason Ekstrand 
Date:   Sat Sep 3 11:40:09 2016 -0700

intel/blorp: Work in terms of logical array layers

When Ivy Bridge introduced array multisampling, someone made the decision
to do lots of stuff throughout the driver in terms of physical array layers
rather than logical array layers.  In ISL, we use logical array layers most
of the time and it really makes no sense to use physical array layers in
the blorp API.  Every time someone passes physical array layers into blorp
for an array multisampled surface, they're always divisible by the number
of samples and we divide right away.

Eventually, I'd like to rework most of the GL driver internals to use
logical array layers but that's going to be a big project and will probably
happen as part of the ISL conversion.  For now, we'll do the 

Mesa (master): docs: Add OES_tessellation_shader to the release notes.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 376d1dc2f1f5a36fe20ede5defe394b87b385731
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=376d1dc2f1f5a36fe20ede5defe394b87b385731

Author: Kenneth Graunke 
Date:   Mon Sep 12 17:24:35 2016 -0700

docs: Add OES_tessellation_shader to the release notes.

---

 docs/relnotes/12.1.0.html | 1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/relnotes/12.1.0.html b/docs/relnotes/12.1.0.html
index 3368ebc..f68b513 100644
--- a/docs/relnotes/12.1.0.html
+++ b/docs/relnotes/12.1.0.html
@@ -61,6 +61,7 @@ Note: some of the new features are only available with 
certain drivers.
 GL_OES_geometry_shader on i965/gen8+, nvc0, radeonsi
 GL_OES_primitive_bounding_box on i965/gen7+, nvc0, radeonsi
 GL_OES_texture_cube_map_array on i965/gen8+, nvc0, radeonsi
+GL_OES_tessellation_shader on i965/gen7+, nvc0, radeonsi
 
 
 Bug fixes

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Mesa (master): docs: Mark OES_tessellation_shader as done.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 049cee2c164dda219d2c4803dcb5c64fb5ad2b4c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=049cee2c164dda219d2c4803dcb5c64fb5ad2b4c

Author: Kenneth Graunke 
Date:   Mon Sep 12 17:23:10 2016 -0700

docs: Mark OES_tessellation_shader as done.

---

 docs/features.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/features.txt b/docs/features.txt
index 690c160..4cc06637 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -268,7 +268,7 @@ GLES3.2, GLSL ES 3.2:
   GL_OES_shader_image_atomicDONE (all drivers that 
support GL_ARB_shader_image_load_store)
   GL_OES_shader_io_blocks   DONE (i965/gen8+, 
nvc0, radeonsi)
   GL_OES_shader_multisample_interpolation   DONE (i965, nvc0, 
r600, radeonsi)
-  GL_OES_tessellation_shaderstarted (Ken)
+  GL_OES_tessellation_shaderDONE (all drivers that 
support GL_ARB_tessellation_shader)
   GL_OES_texture_border_clamp   DONE (all drivers)
   GL_OES_texture_buffer DONE (i965, nvc0, 
radeonsi)
   GL_OES_texture_cube_map_array DONE (i965/gen8+, 
nvc0, radeonsi)

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Mesa (master): st/mesa: fix is_scissor_enabled when X/Y are negative

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: 742832434abc8caff2425fcc174966b2834ac552
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=742832434abc8caff2425fcc174966b2834ac552

Author: Ilia Mirkin 
Date:   Sun Sep 11 13:37:30 2016 -0400

st/mesa: fix is_scissor_enabled when X/Y are negative

Similar to commit 49c24d8a24 ("i965: fix noop_scissor range issue on
width/height") - take the X/Y into account to determine whether the
scissor covers the whole area or not.

Fixes the recently-added gl-1.0-scissor-depth-clear-negative-xy piglit
test.

Signed-off-by: Ilia Mirkin 
Reviewed-by: Michel Dänzer 
Reviewed-by: Marek Olšák 
Cc: 

---

 src/mesa/state_tracker/st_cb_clear.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/mesa/state_tracker/st_cb_clear.c 
b/src/mesa/state_tracker/st_cb_clear.c
index e70cba6..813ba9b 100644
--- a/src/mesa/state_tracker/st_cb_clear.c
+++ b/src/mesa/state_tracker/st_cb_clear.c
@@ -313,11 +313,13 @@ clear_with_quad(struct gl_context *ctx, unsigned 
clear_buffers)
 static inline GLboolean
 is_scissor_enabled(struct gl_context *ctx, struct gl_renderbuffer *rb)
 {
+   const struct gl_scissor_rect *scissor = >Scissor.ScissorArray[0];
+
return (ctx->Scissor.EnableFlags & 1) &&
-  (ctx->Scissor.ScissorArray[0].X > 0 ||
-   ctx->Scissor.ScissorArray[0].Y > 0 ||
-   (unsigned) ctx->Scissor.ScissorArray[0].Width < rb->Width ||
-   (unsigned) ctx->Scissor.ScissorArray[0].Height < rb->Height);
+  (scissor->X > 0 ||
+   scissor->Y > 0 ||
+   scissor->X + scissor->Width < rb->Width ||
+   scissor->Y + scissor->Height < rb->Height);
 }
 
 /**

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Mesa (master): android: add support for libmesa_amdgpu_addrlib

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 6b9d7e69ee7fd1162f7ac231a337630d859c493b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b9d7e69ee7fd1162f7ac231a337630d859c493b

Author: Mauro Rossi 
Date:   Tue Sep 13 01:15:16 2016 +0200

android: add support for libmesa_amdgpu_addrlib

Android porting of the following commits:

f1f1ba3 "radeonsi: move sid.h/r600d_common.h to a common place."
69fca64 "amd/addrlib: move addrlib from amdgpu winsys to common code"

This patch fixes android building errors

Reviewed-by: Dave Airlie 

---

 Android.mk   |  1 +
 src/amd/Android.addrlib.mk   | 44 
 src/amd/Android.mk   | 28 
 src/gallium/drivers/r600/Android.mk  |  2 ++
 src/gallium/drivers/radeonsi/Android.mk  |  4 ++-
 src/gallium/targets/dri/Android.mk   |  2 +-
 src/gallium/winsys/amdgpu/drm/Android.mk |  9 ---
 7 files changed, 84 insertions(+), 6 deletions(-)

diff --git a/Android.mk b/Android.mk
index dfc45c4..fb29105 100644
--- a/Android.mk
+++ b/Android.mk
@@ -95,6 +95,7 @@ SUBDIRS := \
src/mesa \
src/util \
src/egl \
+   src/amd \
src/intel \
src/mesa/drivers/dri
 
diff --git a/src/amd/Android.addrlib.mk b/src/amd/Android.addrlib.mk
new file mode 100644
index 000..d296ce0
--- /dev/null
+++ b/src/amd/Android.addrlib.mk
@@ -0,0 +1,44 @@
+# Copyright © 2016 Red Hat.
+# Copyright © 2016 Mauro Rossi 
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice (including the next
+# paragraph) shall be included in all copies or substantial portions of the
+# Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+# IN THE SOFTWARE.
+
+# ---
+# Build libmesa_amdgpu_addrlib
+# ---
+
+include $(CLEAR_VARS)
+
+LOCAL_MODULE := libmesa_amdgpu_addrlib
+
+LOCAL_SRC_FILES := $(ADDRLIB_FILES)
+
+LOCAL_CFLAGS := -DBRAHMA_BUILD=1
+
+LOCAL_C_INCLUDES := \
+   $(MESA_TOP)/src \
+   $(MESA_TOP)/src/amd/common \
+   $(MESA_TOP)/src/amd/addrlib \
+   $(MESA_TOP)/src/amd/addrlib/core \
+   $(MESA_TOP)/src/amd/addrlib/inc/chip/r800 \
+   $(MESA_TOP)/src/amd/addrlib/r800/chip
+
+include $(MESA_COMMON_MK)
+include $(BUILD_STATIC_LIBRARY)
diff --git a/src/amd/Android.mk b/src/amd/Android.mk
new file mode 100644
index 000..7b745fe
--- /dev/null
+++ b/src/amd/Android.mk
@@ -0,0 +1,28 @@
+# Copyright © 2016 Red Hat.
+# Copyright © 2016 Mauro Rossi 
+#
+# Permission is hereby granted, free of charge, to any person obtaining a
+# copy of this software and associated documentation files (the "Software"),
+# to deal in the Software without restriction, including without limitation
+# the rights to use, copy, modify, merge, publish, distribute, sublicense,
+# and/or sell copies of the Software, and to permit persons to whom the
+# Software is furnished to do so, subject to the following conditions:
+#
+# The above copyright notice and this permission notice (including the next
+# paragraph) shall be included in all copies or substantial portions of the
+# Software.
+#
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+# IN THE SOFTWARE.
+
+LOCAL_PATH := $(call my-dir)
+
+# Import variables
+include $(LOCAL_PATH)/Makefile.sources
+
+include $(LOCAL_PATH)/Android.addrlib.mk
diff --git a/src/gallium/drivers/r600/Android.mk 
b/src/gallium/drivers/r600/Android.mk
index 6476091..eac3116 100644
--- a/src/gallium/drivers/r600/Android.mk
+++ b/src/gallium/drivers/r600/Android.mk
@@ -30,6 +30,8 @@ include $(CLEAR_VARS)
 
 

Mesa (master): u_endian: add android to glibc clause

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 0fe9152868fd7429aca63c58a0930542b8a95219
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0fe9152868fd7429aca63c58a0930542b8a95219

Author: Dave Airlie 
Date:   Mon Sep 12 11:21:29 2016 +1000

u_endian: add android to glibc clause

Tested-by: Mauro Rossi 

---

 src/util/u_endian.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/util/u_endian.h b/src/util/u_endian.h
index aae3e5a..b9d563d 100644
--- a/src/util/u_endian.h
+++ b/src/util/u_endian.h
@@ -27,7 +27,7 @@
 #ifndef U_ENDIAN_H
 #define U_ENDIAN_H
 
-#ifdef __GLIBC__
+#if defined(__GLIBC__) || defined(ANDROID)
 #include 
 
 #if __BYTE_ORDER == __LITTLE_ENDIAN

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Mesa (master): intel/blorp: Handle the 512 layers restriction on Sandy Bridge

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 2519237c2495adb9564062eed6b9cd225b886dc0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2519237c2495adb9564062eed6b9cd225b886dc0

Author: Jason Ekstrand 
Date:   Mon Sep 12 11:46:22 2016 -0700

intel/blorp: Handle the 512 layers restriction on Sandy Bridge

Signed-off-by: Jason Ekstrand 
Reviewed-by: Kenneth Graunke 

---

 src/intel/blorp/blorp.c   |  6 ++
 src/intel/blorp/blorp_clear.c | 17 +
 2 files changed, 19 insertions(+), 4 deletions(-)

diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c
index 17c1ff4..8dfebbc 100644
--- a/src/intel/blorp/blorp.c
+++ b/src/intel/blorp/blorp.c
@@ -139,6 +139,12 @@ brw_blorp_surface_info_init(struct blorp_context *blorp,
   info->view.array_len -= info->view.base_array_layer;
   info->z_offset = 0;
}
+
+   /* Sandy Bridge has a limit of a maximum of 512 layers for layered
+* rendering.
+*/
+   if (is_render_target && blorp->isl_dev->info->gen == 6)
+  info->view.array_len = MIN2(info->view.array_len, 512);
 }
 
 
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index cba4823..2213ada 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -246,7 +246,6 @@ blorp_clear(struct blorp_batch *batch,
 {
struct blorp_params params;
blorp_params_init();
-   params.num_layers = num_layers;
 
params.x0 = x0;
params.y0 = y0;
@@ -278,10 +277,20 @@ blorp_clear(struct blorp_batch *batch,
blorp_params_get_clear_kernel(batch->blorp, ,
  use_simd16_replicated_data);
 
-   brw_blorp_surface_info_init(batch->blorp, , surf, level,
-   start_layer, format, true);
+   while (num_layers > 0) {
+  brw_blorp_surface_info_init(batch->blorp, , surf, level,
+  start_layer, format, true);
 
-   batch->blorp->exec(batch, );
+  /* We may be restricted on the number of layers we can bind at any one
+   * time.  In particular, Sandy Bridge has a maximum number of layers of
+   * 512 but a maximum 3D texture size is much larger.
+   */
+  params.num_layers = MIN2(params.dst.view.array_len, num_layers);
+  batch->blorp->exec(batch, );
+
+  start_layer += params.num_layers;
+  num_layers -= params.num_layers;
+   }
 }
 
 void

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Mesa (master): intel/isl: Treat 3-D textures as 2-D arrays for rendering

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 48f195d7c6483ed00a6d02526c6f35bb527fcaba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=48f195d7c6483ed00a6d02526c6f35bb527fcaba

Author: Jason Ekstrand 
Date:   Mon Sep 12 08:13:43 2016 -0700

intel/isl: Treat 3-D textures as 2-D arrays for rendering

In particular, this means that isl_view::base_array_layer and
isl_view::array_len get applied to 3-D textures but only when rendering.
We were already applying isl_view::base_array_layer for rendering into 3-D
textures so this isn't a huge deviation.

Signed-off-by: Jason Ekstrand 
Reviewed-by: Kenneth Graunke 

---

 src/intel/isl/isl.h   |  6 ++
 src/intel/isl/isl_surface_state.c | 11 +++
 2 files changed, 13 insertions(+), 4 deletions(-)

diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index bb20d17..e01624b 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -879,6 +879,12 @@ struct isl_view {
 *
 * For cube maps, both base_array_layer and array_len should be
 * specified in terms of 2-D layers and must be a multiple of 6.
+*
+* 3-D textures are effectively treated as 2-D arrays when used as a
+* storage image or render target.  If `usage` contains
+* ISL_SURF_USAGE_RENDER_TARGET_BIT or ISL_SURF_USAGE_STORAGE_BIT then
+* base_array_layer and array_len are applied.  If the surface is only used
+* for texturing, they are ignored.
 */
uint32_t base_array_layer;
uint32_t array_len;
diff --git a/src/intel/isl/isl_surface_state.c 
b/src/intel/isl/isl_surface_state.c
index 979e140..5c5386e 100644
--- a/src/intel/isl/isl_surface_state.c
+++ b/src/intel/isl/isl_surface_state.c
@@ -288,8 +288,6 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, 
void *state,
  s.RenderTargetViewExtent = s.Depth;
   break;
case SURFTYPE_3D:
-  s.MinimumArrayElement = info->view->base_array_layer;
-
   /* From the Broadwell PRM >> RENDER_SURFACE_STATE::Depth:
*
*If the volume texture is MIP-mapped, this field specifies the
@@ -309,11 +307,16 @@ isl_genX(surf_fill_state_s)(const struct isl_device *dev, 
void *state,
* textures with more levels than we can render to.  In order to prevent
* assert-failures in the packing function below, we only set the field
* when it's actually going to be used by the hardware.
+   *
+   * Similaraly, the MinimumArrayElement field is ignored by all hardware
+   * prior to Sky Lake when texturing and we want it set to 0 anyway.
+   * Since it's already initialized to 0, we can just leave it alone for
+   * texture surfaces.
*/
   if (info->view->usage & (ISL_SURF_USAGE_RENDER_TARGET_BIT |
ISL_SURF_USAGE_STORAGE_BIT)) {
- s.RenderTargetViewExtent = 
isl_minify(info->surf->logical_level0_px.depth,
-   info->view->base_level) - 1;
+ s.MinimumArrayElement = info->view->base_array_layer;
+ s.RenderTargetViewExtent = info->view->array_len - 1;
   }
   break;
default:

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Mesa (master): Revert "i965: Drop the maximum 3D texture size to 512 on Sandy Bridge"

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: 24be6306609179efddfb7e5cc6ec5d6a335c9b88
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=24be6306609179efddfb7e5cc6ec5d6a335c9b88

Author: Jason Ekstrand 
Date:   Mon Sep 12 08:18:53 2016 -0700

Revert "i965: Drop the maximum 3D texture size to 512 on Sandy Bridge"

This reverts commit 6ba88bce64b343761aabe3a6c7ee285c6020a959.  The commit
was erroneous because GL has a separate limit, GL_MAX_FRAMEBUFFER_LAYERS
which guards the number of layers you are allowed to render into.

The GL 4.5 spec says:

   "The framebuffer attachment point attachment is said to be framebuffer
   attachment complete if [...] all of the following conditions are true:

  [...]

  If image is a three-dimensional, one- or two-dimensional array, or
  cube map array texture and the attachment is layered, the depth or
  layer count of the texture is less than or equal to the value of the
  implementation-dependent limit MAX_FRAMEBUFFER_LAYERS."

and goes on to say that "framebuffer complete" requires all attachments to
be "framebuffer attachment complete".

On Sandy Bridge, we set GL_MAX_FRAMEBUFFER_LAYERS to 512 so creating a 3D
texture bigger than 512 is fine; you just can't render into all of the
slices at once.

Fixes ES3-CTS.gtf.GL3Tests.npot_textures.npot_tex_image on Sandy Bridge

Signed-off-by: Jason Ekstrand 
Reviewed-by: Kenneth Graunke 
Reviewed-by: Chad Versace 

---

 src/mesa/drivers/dri/i965/brw_context.c | 11 +--
 1 file changed, 1 insertion(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index c28401a..3af4555 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -524,16 +524,7 @@ brw_initialize_context_constants(struct brw_context *brw)
ctx->Const.MaxImageUnits = MAX_IMAGE_UNITS;
ctx->Const.MaxRenderbufferSize = 8192;
ctx->Const.MaxTextureLevels = MIN2(14 /* 8192 */, MAX_TEXTURE_LEVELS);
-
-   /* On Sandy Bridge and prior, the "Render Target View Extent" field of
-* RENDER_SURFACE_STATE is only 9 bits so the largest 3-D texture we can do
-* a layered render into has a depth of 512.  On Iron Lake and earlier, we
-* don't support layered rendering and we use manual offsetting to render
-* into the different layers so this doesn't matter.  On Sandy Bridge,
-* however, we do support layered rendering so this is a problem.
-*/
-   ctx->Const.Max3DTextureLevels = brw->gen == 6 ? 10 /* 512 */ : 12; /* 2048 
*/
-
+   ctx->Const.Max3DTextureLevels = 12; /* 2048 */
ctx->Const.MaxCubeTextureLevels = 14; /* 8192 */
ctx->Const.MaxArrayTextureLayers = brw->gen >= 7 ? 2048 : 512;
ctx->Const.MaxTextureMbytes = 1536;

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Mesa (master): aubinator: Simplify gen_disasm_create()'s devinfo handling

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 63fe9ab8943741cc21d8ba54566ddc49275a6b58
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=63fe9ab8943741cc21d8ba54566ddc49275a6b58

Author: Sirisha Gandikota 
Date:   Thu Sep  8 16:15:19 2016 -0700

aubinator: Simplify gen_disasm_create()'s devinfo handling

Copy the whole devinfo structure instead of just few fields (Ken)

Earlier, copied only couple of fields which added more code. So,
simplify code by copying the whole structure.

Signed-off-by: Sirisha Gandikota 
Reviewed-by: Kenneth Graunke 

---

 src/intel/tools/disasm.c | 8 +---
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/src/intel/tools/disasm.c b/src/intel/tools/disasm.c
index ddbfa9f..7e5a7cb 100644
--- a/src/intel/tools/disasm.c
+++ b/src/intel/tools/disasm.c
@@ -89,18 +89,12 @@ struct gen_disasm *
 gen_disasm_create(int pciid)
 {
struct gen_disasm *gd;
-   const struct gen_device_info *dev_info = NULL;
 
gd = malloc(sizeof *gd);
if (gd == NULL)
   return NULL;
 
-   dev_info = gen_get_device_info(pciid);
-
-   gd->devinfo.gen = dev_info->gen;
-   gd->devinfo.is_cherryview = dev_info->is_cherryview;
-   gd->devinfo.is_g4x = dev_info->is_g4x;
-
+   gd->devinfo = *gen_get_device_info(pciid);
brw_init_compaction_tables(>devinfo);
 
return gd;

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Mesa (master): aubinator: Fix compiler warning

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: d2869c95fbee8213a3d90b42f60414da546c4962
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2869c95fbee8213a3d90b42f60414da546c4962

Author: Sirisha Gandikota 
Date:   Thu Sep  8 16:15:18 2016 -0700

aubinator: Fix compiler warning

Add 'const' qualifier to gen_field_iterator::p pointer (Ken)

Signed-off-by: Sirisha Gandikota 
Reviewed-by: Kenneth Graunke 

---

 src/intel/tools/decoder.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/tools/decoder.h b/src/intel/tools/decoder.h
index b46e451..4ab0765 100644
--- a/src/intel/tools/decoder.h
+++ b/src/intel/tools/decoder.h
@@ -47,7 +47,7 @@ struct gen_field_iterator {
struct gen_group *group;
const char *name;
char value[128];
-   uint32_t *p;
+   const uint32_t *p;
int i;
 };
 

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Mesa (master): st/va: also honors interlaced preference when providing a video format

[Julien Isorce]

Module: Mesa
Branch: master
Commit: bf901a2f8c8954e55a3eebc6cd1b725f18802012
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf901a2f8c8954e55a3eebc6cd1b725f18802012

Author: Julien Isorce 
Date:   Sat Sep  3 09:10:21 2016 +0100

st/va: also honors interlaced preference when providing a video format

This fixes a crash when using the prefered video format with vaapisink
on Nvidia hardwares.
Also caught by the following assert:
  nouveau_vp3_video.c:91: Assertion `templat->interlaced' failed.

TEST= gst-launch-1.0 videotestsrc ! video/x-raw, format=NV12 ! vaapisink

Cc: 
Signed-off-by: Julien Isorce 
Tested-by: Víctor Manuel Jáquez Leal 
Tested-by: Boyuan Zhang 
Reviewed-by: Christian König 

---

 src/gallium/state_trackers/va/surface.c | 36 +
 1 file changed, 19 insertions(+), 17 deletions(-)

diff --git a/src/gallium/state_trackers/va/surface.c 
b/src/gallium/state_trackers/va/surface.c
index 3ee1cdd..00df69d 100644
--- a/src/gallium/state_trackers/va/surface.c
+++ b/src/gallium/state_trackers/va/surface.c
@@ -632,24 +632,26 @@ vlVaCreateSurfaces2(VADriverContextP ctx, unsigned int 
format,
 
memset(, 0, sizeof(templat));
 
+   templat.buffer_format = pscreen->get_video_param(
+  pscreen,
+  PIPE_VIDEO_PROFILE_UNKNOWN,
+  PIPE_VIDEO_ENTRYPOINT_BITSTREAM,
+  PIPE_VIDEO_CAP_PREFERED_FORMAT
+   );
+   templat.interlaced = pscreen->get_video_param(
+  pscreen,
+  PIPE_VIDEO_PROFILE_UNKNOWN,
+  PIPE_VIDEO_ENTRYPOINT_BITSTREAM,
+  PIPE_VIDEO_CAP_PREFERS_INTERLACED
+   );
+
if (expected_fourcc) {
-  templat.buffer_format = VaFourccToPipeFormat(expected_fourcc);
-  templat.interlaced = 0;
-   } else {
-  templat.buffer_format = pscreen->get_video_param
-(
-   pscreen,
-   PIPE_VIDEO_PROFILE_UNKNOWN,
-   PIPE_VIDEO_ENTRYPOINT_BITSTREAM,
-   PIPE_VIDEO_CAP_PREFERED_FORMAT
-   );
-  templat.interlaced = pscreen->get_video_param
-(
-   pscreen,
-   PIPE_VIDEO_PROFILE_UNKNOWN,
-   PIPE_VIDEO_ENTRYPOINT_BITSTREAM,
-   PIPE_VIDEO_CAP_PREFERS_INTERLACED
-   );
+  enum pipe_format expected_format = VaFourccToPipeFormat(expected_fourcc);
+
+  if (expected_format != templat.buffer_format || memory_attibute)
+templat.interlaced = 0;
+
+  templat.buffer_format = expected_format;
}
 
templat.chroma_format = ChromaToPipe(format);

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Mesa (master): tgsi: document semantics for compute shaders

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: 3f3640c86cd850d7d85fe83f102634af92aa894e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f3640c86cd850d7d85fe83f102634af92aa894e

Author: Samuel Pitoiset 
Date:   Sat Sep 10 17:10:46 2016 +0200

tgsi: document semantics for compute shaders

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Nicolai Hähnle 

---

 src/gallium/docs/source/tgsi.rst | 28 
 1 file changed, 28 insertions(+)

diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst
index c6e5ceb..881aef6 100644
--- a/src/gallium/docs/source/tgsi.rst
+++ b/src/gallium/docs/source/tgsi.rst
@@ -3054,6 +3054,34 @@ parameter to the clEnqueueNDRangeKernel call with which 
the shader
 was started.
 
 
+TGSI_SEMANTIC_GRID_SIZE
+"""
+
+For compute shaders, this semantic indicates the maximum (x, y, z) dimensions
+of a grid of thread blocks.
+
+
+TGSI_SEMANTIC_BLOCK_ID
+""
+
+For compute shaders, this semantic indicates the (x, y, z) coordinates of the
+current block inside of the grid.
+
+
+TGSI_SEMANTIC_BLOCK_SIZE
+
+
+For compute shaders, this semantic indicates the maximum (x, y, z) dimensions
+of a block in threads.
+
+
+TGSI_SEMANTIC_THREAD_ID
+"""
+
+For compute shaders, this semantic indicates the (x, y, z) coordinates of the
+current thread inside of the block.
+
+
 Declaration Interpolate
 ^^^
 

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Mesa (master): mesa: Enable OES/ EXT_tessellation_shader for ES 3.1 + ARB_tess drivers.

[Kenneth Graunke]

Module: Mesa
Branch: master
Commit: 54138af1cd40898eea17b824432faee60e743794
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=54138af1cd40898eea17b824432faee60e743794

Author: Kenneth Graunke 
Date:   Fri Jul  8 11:48:15 2016 -0700

mesa: Enable OES/EXT_tessellation_shader for ES 3.1 + ARB_tess drivers.

Drivers which support ARB_tessellation_shader and ES 3.1 now will
expose OES_tessellation_shader and EXT_tessellation_shader as well.

Signed-off-by: Kenneth Graunke 
Reviewed-by: Ian Romanick 
Acked-by: Ilia Mirkin 

---

 src/mesa/main/extensions_table.h | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/mesa/main/extensions_table.h b/src/mesa/main/extensions_table.h
index 75cdcb8..edfc458 100644
--- a/src/mesa/main/extensions_table.h
+++ b/src/mesa/main/extensions_table.h
@@ -238,8 +238,8 @@ EXT(EXT_shadow_funcs, ARB_shadow
 EXT(EXT_stencil_two_side, EXT_stencil_two_side 
  , GLL,  x ,  x ,  x , 2001)
 EXT(EXT_stencil_wrap, dummy_true   
  , GLL,  x ,  x ,  x , 2002)
 EXT(EXT_subtexture  , dummy_true   
  , GLL,  x ,  x ,  x , 1995)
-EXT(EXT_tessellation_point_size , dummy_false  
  ,  x ,  x ,  x ,  31, 2013)
-EXT(EXT_tessellation_shader , dummy_false  
  ,  x ,  x ,  x ,  31, 2013)
+EXT(EXT_tessellation_point_size , ARB_tessellation_shader  
  ,  x ,  x ,  x ,  31, 2013)
+EXT(EXT_tessellation_shader , ARB_tessellation_shader  
  ,  x ,  x ,  x ,  31, 2013)
 EXT(EXT_texture , dummy_true   
  , GLL,  x ,  x ,  x , 1996)
 EXT(EXT_texture3D   , dummy_true   
  , GLL,  x ,  x ,  x , 1996)
 EXT(EXT_texture_array   , EXT_texture_array
  , GLL, GLC,  x ,  x , 2006)
@@ -369,8 +369,8 @@ EXT(OES_stencil4, dummy_false
 EXT(OES_stencil8, dummy_true   
  ,  x ,  x , ES1, ES2, 2005)
 EXT(OES_stencil_wrap, dummy_true   
  ,  x ,  x , ES1,  x , 2002)
 EXT(OES_surfaceless_context , dummy_true   
  ,  x ,  x , ES1, ES2, 2012)
-EXT(OES_tessellation_point_size , dummy_false  
  ,  x ,  x ,  x ,  31, 2014)
-EXT(OES_tessellation_shader , dummy_false  
  ,  x ,  x ,  x ,  31, 2014)
+EXT(OES_tessellation_point_size , ARB_tessellation_shader  
  ,  x ,  x ,  x ,  31, 2014)
+EXT(OES_tessellation_shader , ARB_tessellation_shader  
  ,  x ,  x ,  x ,  31, 2014)
 EXT(OES_texture_3D  , dummy_true   
  ,  x ,  x ,  x , ES2, 2005)
 EXT(OES_texture_border_clamp, ARB_texture_border_clamp 
  ,  x ,  x ,  x , ES2, 2014)
 EXT(OES_texture_buffer  , OES_texture_buffer   
  ,  x ,  x ,  x ,  31, 2014)

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Mesa (master): radeonsi: don' t preload constants at the beginning of shaders

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 546bc07349d0e53b71766780cf726fe21f7d6983
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=546bc07349d0e53b71766780cf726fe21f7d6983

Author: Marek Olšák 
Date:   Sat Sep 10 00:29:31 2016 +0200

radeonsi: don't preload constants at the beginning of shaders

LLVM can CSE the loads, thus we can always re-load constants before each
use. The decrease in SGPR spilling is huge.

The best improvements are the dumbest ones.

26011 shaders in 14651 tests
Totals:
SGPRS: 1453346 -> 1251920 (-13.86 %)
VGPRS: 742576 -> 728421 (-1.91 %)
Spilled SGPRs: 52298 -> 16644 (-68.17 %)
Spilled VGPRs: 397 -> 369 (-7.05 %)
Scratch VGPRs: 1372 -> 1344 (-2.04 %) dwords per thread
Code Size: 36136488 -> 36001064 (-0.37 %) bytes
LDS: 767 -> 767 (0.00 %) blocks
Max Waves: 219315 -> 21 (1.33 %)

Reviewed-by: Bas Nieuwenhuizen 
Reviewed-by: Edward O'Callaghan 
Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_shader.c | 31 +++
 1 file changed, 11 insertions(+), 20 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 0b7de18..6801722 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -107,7 +107,6 @@ struct si_shader_context
 
LLVMValueRef const_buffers[SI_NUM_CONST_BUFFERS];
LLVMValueRef lds;
-   LLVMValueRef *constants[SI_NUM_CONST_BUFFERS];
LLVMValueRef shader_buffers[SI_NUM_SHADER_BUFFERS];
LLVMValueRef sampler_views[SI_NUM_SAMPLERS];
LLVMValueRef sampler_states[SI_NUM_SAMPLERS];
@@ -1881,12 +1880,19 @@ static LLVMValueRef fetch_constant(
idx = reg->Register.Index * 4 + swizzle;
 
if (!reg->Register.Indirect && !reg->Dimension.Indirect) {
+   LLVMValueRef c0, c1;
+
+   c0 = buffer_load_const(ctx, ctx->const_buffers[buf],
+  LLVMConstInt(ctx->i32, idx * 4, 0));
+
if (!tgsi_type_is_64bit(type))
-   return bitcast(bld_base, type, 
ctx->constants[buf][idx]);
+   return bitcast(bld_base, type, c0);
else {
+   c1 = buffer_load_const(ctx, ctx->const_buffers[buf],
+  LLVMConstInt(ctx->i32,
+   (idx + 1) * 4, 0));
return radeon_llvm_emit_fetch_64bit(bld_base, type,
-   
ctx->constants[buf][idx],
-   
ctx->constants[buf][idx + 1]);
+   c0, c1);
}
}
 
@@ -5796,25 +5802,12 @@ static void preload_constants(struct si_shader_context 
*ctx)
LLVMValueRef ptr = LLVMGetParam(ctx->radeon_bld.main_fn, 
SI_PARAM_CONST_BUFFERS);
 
for (buf = 0; buf < SI_NUM_CONST_BUFFERS; buf++) {
-   unsigned i, num_const = info->const_file_max[buf] + 1;
-
-   if (num_const == 0)
+   if (info->const_file_max[buf] == -1)
continue;
 
-   /* Allocate space for the constant values */
-   ctx->constants[buf] = CALLOC(num_const * 4, 
sizeof(LLVMValueRef));
-
/* Load the resource descriptor */
ctx->const_buffers[buf] =
build_indexed_load_const(ctx, ptr, 
lp_build_const_int32(gallivm, buf));
-
-   /* Load the constants, we rely on the code sinking to do the 
rest */
-   for (i = 0; i < num_const * 4; ++i) {
-   ctx->constants[buf][i] =
-   buffer_load_const(ctx,
-   ctx->const_buffers[buf],
-   lp_build_const_int32(gallivm, i * 4));
-   }
}
 }
 
@@ -6905,8 +6898,6 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
}
 
 out:
-   for (int i = 0; i < SI_NUM_CONST_BUFFERS; i++)
-   FREE(ctx.constants[i]);
return r;
 }
 

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Mesa (master): intel/blorp: Add a TODO file

[Jason Ekstrand]

Module: Mesa
Branch: master
Commit: e2fb0441150e81f7ba30db1c8e8583858c3d8d5e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2fb0441150e81f7ba30db1c8e8583858c3d8d5e

Author: Jason Ekstrand 
Date:   Mon Sep 12 10:13:52 2016 -0700

intel/blorp: Add a TODO file

This provides a nice little place to share notes on what still needs to be
done and/or would be nice to have in BLORP.

Signed-off-by: Jason Ekstrand 

---

 src/intel/blorp/TODO | 16 
 1 file changed, 16 insertions(+)

diff --git a/src/intel/blorp/TODO b/src/intel/blorp/TODO
new file mode 100644
index 000..e3ac6e9
--- /dev/null
+++ b/src/intel/blorp/TODO
@@ -0,0 +1,16 @@
+Intel BLORP ToDo
+
+
+Missing features:
+
+ - Splitting larger-than-max blits (Jordan)
+ - Bit-for-bit copies (Jason)
+ - Depth and Stencil clears
+ - Gen4-5 support
+
+Performance:
+
+ - Layered Clears (Topi)
+ - Layered Blits
+ - Avoid re-emitting state for repeated blorp calls
+ - Avoid re-emitting push constant setup

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Mesa (master): i965: check for GL_TEXTURE_EXTERNAL_OES at miptree_create_for_teximage

[Alejandro Pinheiro]

Module: Mesa
Branch: master
Commit: 6165603209f08cd95dc687363034f54978fe2c77
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6165603209f08cd95dc687363034f54978fe2c77

Author: Alejandro Piñeiro 
Date:   Sun Sep 11 00:07:30 2016 +0200

i965: check for GL_TEXTURE_EXTERNAL_OES at miptree_create_for_teximage

Forgotten on commit "i965: Fix calculation of the image height at start level".

Thanks to Ilia Mirkin for point it.

Fixes the following regressions on Haswell and Broadwell:
ES2-CTS.gtf.GL2ExtensionTests.egl_image_external.TestSimpleUnassociated (crash 
back to pass)
ES2-CTS.gtf.GL2ExtensionTests.egl_image_external.TestSimple (crash back to fail)
ES2-CTS.gtf.GL2ExtensionTests.egl_image_external.TestVertexShader (crash back 
to fail)

https://bugs.freedesktop.org/show_bug.cgi?id=97761

Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/intel_tex_image.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c 
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index 6142a5f..f204db3 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -50,6 +50,7 @@ intel_miptree_create_for_teximage(struct brw_context *brw,
case GL_TEXTURE_2D_MULTISAMPLE:
case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
case GL_TEXTURE_RECTANGLE:
+   case GL_TEXTURE_EXTERNAL_OES:
   assert(intelImage->base.Base.Level == 0);
   break;
case GL_TEXTURE_3D:

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Mesa (master): gbm: fix potential NULL deref of mapImage/unmapImage.

[Emil Velikov]

Module: Mesa
Branch: master
Commit: 9a1eb5423722955bee5c5b5f48fb058f0884fab0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a1eb5423722955bee5c5b5f48fb058f0884fab0

Author: Chuanbo Weng 
Date:   Tue Sep  6 17:28:43 2016 +0800

gbm: fix potential NULL deref of mapImage/unmapImage.

The mapImage/unmapImage functions of DRIimage extension can be NULL,
so we should add additional check for them.

Cc: 
Signed-off-by: Chuanbo Weng 
Reviewed-by: Emil Velikov 

---

 src/gbm/backends/dri/gbm_dri.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/gbm/backends/dri/gbm_dri.c b/src/gbm/backends/dri/gbm_dri.c
index c1f9d62..0ab67da 100644
--- a/src/gbm/backends/dri/gbm_dri.c
+++ b/src/gbm/backends/dri/gbm_dri.c
@@ -949,7 +949,7 @@ gbm_dri_bo_map(struct gbm_bo *_bo,
   return *map_data;
}
 
-   if (!dri->image || dri->image->base.version < 12) {
+   if (!dri->image || dri->image->base.version < 12 || !dri->image->mapImage) {
   errno = ENOSYS;
   return NULL;
}
@@ -980,7 +980,8 @@ gbm_dri_bo_unmap(struct gbm_bo *_bo, void *map_data)
   return;
}
 
-   if (!dri->context || !dri->image || dri->image->base.version < 12)
+   if (!dri->context || !dri->image ||
+   dri->image->base.version < 12 || !dri->image->unmapImage)
   return;
 
dri->image->unmapImage(dri->context, bo->image, map_data);

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Mesa (master): Remove GL_GLEXT_PROTOTYPES guards from non-ext headers.

[Emil Velikov]

Module: Mesa
Branch: master
Commit: 63faf7de619be093c883318e90b5e317b9cb0eb1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=63faf7de619be093c883318e90b5e317b9cb0eb1

Author: Emil Velikov 
Date:   Mon Sep 12 13:26:40 2016 +0100

Remove GL_GLEXT_PROTOTYPES guards from non-ext headers.

A earlier sync with the Khronos headers added _extension_ prototype
guards to all the GLES2/3/31/32 core entry points. Effectively breaking
all the applications that aim to be portable and do not set the define.

The issue has been reported to Khronos (internal bugzilla #14206) and is
being worked on. Until updated/fixed headers are released locally fix
the issue.

The following report is when building weston.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97773

Cc: Armin Krezović 
Cc: Emmanuel Gil Peyrot 
Cc: Pekka Paalanen 
Fixes: 6a5504de2fb ("Update Khronos-supplied headers to r33100")
Cc: Dave Airlie 
Signed-off-by: Emil Velikov 
Reviewed-by: Daniel Stone 
Reviewed-by: Ilia Mirkin 

---

 include/GLES2/gl2.h  | 2 --
 include/GLES3/gl3.h  | 4 
 include/GLES3/gl31.h | 6 --
 include/GLES3/gl32.h | 8 
 4 files changed, 20 deletions(-)

diff --git a/include/GLES2/gl2.h b/include/GLES2/gl2.h
index 27ecbd8..57e1b50 100644
--- a/include/GLES2/gl2.h
+++ b/include/GLES2/gl2.h
@@ -520,7 +520,6 @@ typedef void (GL_APIENTRYP PFNGLVERTEXATTRIB4FPROC) (GLuint 
index, GLfloat x, GL
 typedef void (GL_APIENTRYP PFNGLVERTEXATTRIB4FVPROC) (GLuint index, const 
GLfloat *v);
 typedef void (GL_APIENTRYP PFNGLVERTEXATTRIBPOINTERPROC) (GLuint index, GLint 
size, GLenum type, GLboolean normalized, GLsizei stride, const void *pointer);
 typedef void (GL_APIENTRYP PFNGLVIEWPORTPROC) (GLint x, GLint y, GLsizei 
width, GLsizei height);
-#ifdef GL_GLEXT_PROTOTYPES
 GL_APICALL void GL_APIENTRY glActiveTexture (GLenum texture);
 GL_APICALL void GL_APIENTRY glAttachShader (GLuint program, GLuint shader);
 GL_APICALL void GL_APIENTRY glBindAttribLocation (GLuint program, GLuint 
index, const GLchar *name);
@@ -663,7 +662,6 @@ GL_APICALL void GL_APIENTRY glVertexAttrib4f (GLuint index, 
GLfloat x, GLfloat y
 GL_APICALL void GL_APIENTRY glVertexAttrib4fv (GLuint index, const GLfloat *v);
 GL_APICALL void GL_APIENTRY glVertexAttribPointer (GLuint index, GLint size, 
GLenum type, GLboolean normalized, GLsizei stride, const void *pointer);
 GL_APICALL void GL_APIENTRY glViewport (GLint x, GLint y, GLsizei width, 
GLsizei height);
-#endif
 #endif /* GL_ES_VERSION_2_0 */
 
 #ifdef __cplusplus
diff --git a/include/GLES3/gl3.h b/include/GLES3/gl3.h
index 963d85e..d8153c0 100644
--- a/include/GLES3/gl3.h
+++ b/include/GLES3/gl3.h
@@ -520,7 +520,6 @@ typedef void (GL_APIENTRYP PFNGLVERTEXATTRIB4FPROC) (GLuint 
index, GLfloat x, GL
 typedef void (GL_APIENTRYP PFNGLVERTEXATTRIB4FVPROC) (GLuint index, const 
GLfloat *v);
 typedef void (GL_APIENTRYP PFNGLVERTEXATTRIBPOINTERPROC) (GLuint index, GLint 
size, GLenum type, GLboolean normalized, GLsizei stride, const void *pointer);
 typedef void (GL_APIENTRYP PFNGLVIEWPORTPROC) (GLint x, GLint y, GLsizei 
width, GLsizei height);
-#ifdef GL_GLEXT_PROTOTYPES
 GL_APICALL void GL_APIENTRY glActiveTexture (GLenum texture);
 GL_APICALL void GL_APIENTRY glAttachShader (GLuint program, GLuint shader);
 GL_APICALL void GL_APIENTRY glBindAttribLocation (GLuint program, GLuint 
index, const GLchar *name);
@@ -663,7 +662,6 @@ GL_APICALL void GL_APIENTRY glVertexAttrib4f (GLuint index, 
GLfloat x, GLfloat y
 GL_APICALL void GL_APIENTRY glVertexAttrib4fv (GLuint index, const GLfloat *v);
 GL_APICALL void GL_APIENTRY glVertexAttribPointer (GLuint index, GLint size, 
GLenum type, GLboolean normalized, GLsizei stride, const void *pointer);
 GL_APICALL void GL_APIENTRY glViewport (GLint x, GLint y, GLsizei width, 
GLsizei height);
-#endif
 #endif /* GL_ES_VERSION_2_0 */
 
 #ifndef GL_ES_VERSION_3_0
@@ -1094,7 +1092,6 @@ typedef void (GL_APIENTRYP 
PFNGLINVALIDATESUBFRAMEBUFFERPROC) (GLenum target, GL
 typedef void (GL_APIENTRYP PFNGLTEXSTORAGE2DPROC) (GLenum target, GLsizei 
levels, GLenum internalformat, GLsizei width, GLsizei height);
 typedef void (GL_APIENTRYP PFNGLTEXSTORAGE3DPROC) (GLenum target, GLsizei 
levels, GLenum internalformat, GLsizei width, GLsizei height, GLsizei depth);
 typedef void (GL_APIENTRYP PFNGLGETINTERNALFORMATIVPROC) (GLenum target, 
GLenum internalformat, GLenum pname, GLsizei bufSize, GLint *params);
-#ifdef GL_GLEXT_PROTOTYPES
 GL_APICALL void GL_APIENTRY glReadBuffer (GLenum src);
 GL_APICALL void GL_APIENTRY glDrawRangeElements (GLenum mode, GLuint start, 
GLuint end, GLsizei count, GLenum type, const void *indices);
 GL_APICALL void GL_APIENTRY glTexImage3D (GLenum target, GLint level, GLint 
internalformat, GLsizei width, GLsizei height, GLsizei depth, GLint border, 
GLenum 

Mesa (master): aubinator: rework print_help()

[Emil Velikov]

Module: Mesa
Branch: master
Commit: ceaa2e1738f9d0ee1280899af6dfee64f72c405a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ceaa2e1738f9d0ee1280899af6dfee64f72c405a

Author: Emil Velikov 
Date:   Mon Sep 12 12:34:10 2016 +0100

aubinator: rework print_help()

Rather than using platform specific methods to retrieve the program
name pass it explicitly. The function is called directly from main().

Similarly - basename comes in two versions POSIX (can modify string,
always pass a copy) and GNU (never modifies the string).

Just printout the complete program name, esp. since the program is not
meant to be installed. Thus using $basename is unlikely to work, not to
mention it is misleading.

Reported-by: Timothy Arceri 
Signed-off-by: Emil Velikov 
Reviewed-by: Jonathan Gray 

---

 src/intel/tools/aubinator.c | 17 +
 1 file changed, 5 insertions(+), 12 deletions(-)

diff --git a/src/intel/tools/aubinator.c b/src/intel/tools/aubinator.c
index fe1f369..9d29b68 100644
--- a/src/intel/tools/aubinator.c
+++ b/src/intel/tools/aubinator.c
@@ -30,7 +30,6 @@
 #include 
 #include 
 #include 
-#include 
 #include 
 #include 
 #include 
@@ -1012,14 +1011,8 @@ setup_pager(void)
 }
 
 static void
-print_help(FILE *file)
+print_help(const char *progname, FILE *file)
 {
-   const char *progname;
-#if defined(__GLIBC__) || defined(__CYGWIN__)
-   progname = program_invocation_short_name;
-#else
-   progname = getprogname();
-#endif
fprintf(file,
"Usage: %s [OPTION]... FILE\n"
"Decode aub file contents.\n\n"
@@ -1031,7 +1024,7 @@ print_help(FILE *file)
"if omitted), 'always', or 'never'\n"
"  --no-pager  don't launch pager\n"
"  --no-offsetsdon't print instruction offsets\n",
-   basename(progname));
+   progname);
 }
 
 static bool
@@ -1062,7 +1055,7 @@ int main(int argc, char *argv[])
char gen_file[256], gen_val[24];
 
if (argc == 1) {
-  print_help(stderr);
+  print_help(argv[0], stderr);
   exit(EXIT_FAILURE);
}
 
@@ -1094,7 +1087,7 @@ int main(int argc, char *argv[])
 exit(EXIT_FAILURE);
  }
   } else if (strcmp(argv[i], "--help") == 0) {
- print_help(stdout);
+ print_help(argv[0], stdout);
  exit(EXIT_SUCCESS);
   } else {
  if (argv[i][0] == '-') {
@@ -1174,7 +1167,7 @@ int main(int argc, char *argv[])
disasm = gen_disasm_create(pci_id);
 
if (argv[i] == NULL) {
-   print_help(stderr);
+   print_help(argv[0], stderr);
exit(EXIT_FAILURE);
} else {
file = aub_file_open(argv[i]);

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Mesa (master): egl: Rename MESA_configless_context bit to KHR_no_config_context

[Adam Jackson]

Module: Mesa
Branch: master
Commit: d9f5b1915b397d4baaf4c9c23a93fda49f3db4ca
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d9f5b1915b397d4baaf4c9c23a93fda49f3db4ca

Author: Adam Jackson 
Date:   Fri Sep  9 12:25:34 2016 -0400

egl: Rename MESA_configless_context bit to KHR_no_config_context

Keep the old name in the extension string, but refer to the KHR
extension internally.

Reviewed-by: Kristian Høgsberg 
Reviewed-by: Eric Anholt 
Signed-off-by: Adam Jackson 

---

 src/egl/drivers/dri2/egl_dri2.c | 2 +-
 src/egl/main/eglapi.c   | 6 --
 src/egl/main/eglcontext.c   | 4 ++--
 src/egl/main/egldisplay.h   | 2 +-
 4 files changed, 8 insertions(+), 6 deletions(-)

diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index 859612f..bbc457c 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -603,8 +603,8 @@ dri2_setup_screen(_EGLDisplay *disp)
   disp->ClientAPIs |= EGL_OPENGL_ES3_BIT_KHR;
 
assert(dri2_dpy->image_driver || dri2_dpy->dri2 || dri2_dpy->swrast);
+   disp->Extensions.KHR_no_config_context = EGL_TRUE;
disp->Extensions.KHR_surfaceless_context = EGL_TRUE;
-   disp->Extensions.MESA_configless_context = EGL_TRUE;
 
if (dri2_renderer_query_integer(dri2_dpy,
__DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB))
diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index df2dcd6..ba8305e 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -406,11 +406,13 @@ _eglCreateExtensionsString(_EGLDisplay *dpy)
   _eglAppendExtension(, "EGL_KHR_image");
_EGL_CHECK_EXTENSION(KHR_image_base);
_EGL_CHECK_EXTENSION(KHR_image_pixmap);
+   _EGL_CHECK_EXTENSION(KHR_no_config_context);
_EGL_CHECK_EXTENSION(KHR_reusable_sync);
_EGL_CHECK_EXTENSION(KHR_surfaceless_context);
_EGL_CHECK_EXTENSION(KHR_wait_sync);
 
-   _EGL_CHECK_EXTENSION(MESA_configless_context);
+   if (dpy->Extensions.KHR_no_config_context)
+  _eglAppendExtension(, "EGL_MESA_configless_context");
_EGL_CHECK_EXTENSION(MESA_drm_image);
_EGL_CHECK_EXTENSION(MESA_image_dma_buf_export);
 
@@ -627,7 +629,7 @@ eglCreateContext(EGLDisplay dpy, EGLConfig config, 
EGLContext share_list,
 
_EGL_CHECK_DISPLAY(disp, EGL_NO_CONTEXT, drv);
 
-   if (!config && !disp->Extensions.MESA_configless_context)
+   if (!config && !disp->Extensions.KHR_no_config_context)
   RETURN_EGL_ERROR(disp, EGL_BAD_CONFIG, EGL_NO_CONTEXT);
 
if (!share && share_list != EGL_NO_CONTEXT)
diff --git a/src/egl/main/eglcontext.c b/src/egl/main/eglcontext.c
index 7eac79a..60625f6 100644
--- a/src/egl/main/eglcontext.c
+++ b/src/egl/main/eglcontext.c
@@ -642,9 +642,9 @@ _eglCheckMakeCurrent(_EGLContext *ctx, _EGLSurface *draw, 
_EGLSurface *read)
   (read && read->Config != ctx->Config))
  return _eglError(EGL_BAD_MATCH, "eglMakeCurrent");
} else {
-  /* Otherwise we must be using the EGL_MESA_configless_context
+  /* Otherwise we must be using the EGL_KHR_no_config_context
* extension */
-  assert(dpy->Extensions.MESA_configless_context);
+  assert(dpy->Extensions.KHR_no_config_context);
 
   /* The extension doesn't permit binding draw and read buffers with
* differing contexts */
diff --git a/src/egl/main/egldisplay.h b/src/egl/main/egldisplay.h
index 6bfc858..6f3340e 100644
--- a/src/egl/main/egldisplay.h
+++ b/src/egl/main/egldisplay.h
@@ -112,11 +112,11 @@ struct _egl_extensions
EGLBoolean KHR_gl_texture_cubemap_image;
EGLBoolean KHR_image_base;
EGLBoolean KHR_image_pixmap;
+   EGLBoolean KHR_no_config_context;
EGLBoolean KHR_reusable_sync;
EGLBoolean KHR_surfaceless_context;
EGLBoolean KHR_wait_sync;
 
-   EGLBoolean MESA_configless_context;
EGLBoolean MESA_drm_image;
EGLBoolean MESA_image_dma_buf_export;
 

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Mesa (master): egl: QueryContext on a configless context returns zero

[Adam Jackson]

Module: Mesa
Branch: master
Commit: cc45a5c30872e2070aae6a79dbe0e2bcf7404917
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc45a5c30872e2070aae6a79dbe0e2bcf7404917

Author: Adam Jackson 
Date:   Fri Sep  9 12:25:33 2016 -0400

egl: QueryContext on a configless context returns zero

MESA_configless_context does not specify the interaction with
QueryContext at all, and the code to generate an error in this case
predates the Mesa extension. Since EGL_NO_CONFIG_{KHR,MESA} are
numerically identical there's no way to distinguish which one the
application asked for, so use the KHR behaviour.

Reviewed-by: Kristian Høgsberg 
Reviewed-by: Eric Anholt 
Signed-off-by: Adam Jackson 

---

 src/egl/main/eglcontext.c | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/egl/main/eglcontext.c b/src/egl/main/eglcontext.c
index 58740c3..7eac79a 100644
--- a/src/egl/main/eglcontext.c
+++ b/src/egl/main/eglcontext.c
@@ -538,9 +538,14 @@ _eglQueryContext(_EGLDriver *drv, _EGLDisplay *dpy, 
_EGLContext *c,
 
switch (attribute) {
case EGL_CONFIG_ID:
-  if (!c->Config)
- return _eglError(EGL_BAD_ATTRIBUTE, "eglQueryContext");
-  *value = c->Config->ConfigID;
+  /*
+   * From EGL_KHR_no_config_context:
+   *
+   *"Querying EGL_CONFIG_ID returns the ID of the EGLConfig with
+   * respect to which the context was created, or zero if created
+   * without respect to an EGLConfig."
+   */
+  *value = c->Config ? c->Config->ConfigID : 0;
   break;
case EGL_CONTEXT_CLIENT_VERSION:
   *value = c->ClientMajorVersion;

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Mesa (master): docs: Note MESA_configless_context as superseded

[Adam Jackson]

Module: Mesa
Branch: master
Commit: 0cb1428fbbbcbd17c975b6505cab6f685c0129aa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0cb1428fbbbcbd17c975b6505cab6f685c0129aa

Author: Adam Jackson 
Date:   Fri Sep  9 12:25:35 2016 -0400

docs: Note MESA_configless_context as superseded

Reviewed-by: Kristian Høgsberg 
Reviewed-by: Eric Anholt 
Signed-off-by: Adam Jackson 

---

 docs/specs/MESA_configless_context.spec | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/docs/specs/MESA_configless_context.spec 
b/docs/specs/MESA_configless_context.spec
index f2fafb3..d7ba62d 100644
--- a/docs/specs/MESA_configless_context.spec
+++ b/docs/specs/MESA_configless_context.spec
@@ -12,11 +12,12 @@ Contact
 
 Status
 
-Proposal
+Superseded by the functionally identical EGL_KHR_no_config_context
+extension.
 
 Version
 
-Version 1, February 28, 2014
+Version 2, September 9, 2016
 
 Number
 
@@ -121,5 +122,8 @@ Issues
 
 Revision History
 
+Version 2, September 9, 2016
+Defer to EGL_KHR_no_config_context (Adam Jackson)
+
 Version 1, February 28, 2014
 Initial draft (Neil Roberts)

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Mesa (master): st/va: enable vbr rate control for vaapi encode

[Leo Liu]

Module: Mesa
Branch: master
Commit: e5009b7c2638e1fe10443ae2efafaa3a4e7f19c7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5009b7c2638e1fe10443ae2efafaa3a4e7f19c7

Author: Boyuan Zhang 
Date:   Tue Sep  6 16:39:45 2016 -0400

st/va: enable vbr rate control for vaapi encode

This patch enables variable bit-rate for vaapi encoding. According to va.h,
target bit-rate equals to maximum bit-rate multiplies by target_percentage.

Signed-off-by: Boyuan Zhang 
Reviewed-by: Christian König 

---

 src/gallium/state_trackers/va/config.c  | 2 +-
 src/gallium/state_trackers/va/picture.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/state_trackers/va/config.c 
b/src/gallium/state_trackers/va/config.c
index 84bf913..4052316 100644
--- a/src/gallium/state_trackers/va/config.c
+++ b/src/gallium/state_trackers/va/config.c
@@ -120,7 +120,7 @@ vlVaGetConfigAttributes(VADriverContextP ctx, VAProfile 
profile, VAEntrypoint en
  value = VA_RT_FORMAT_YUV420;
  break;
   case VAConfigAttribRateControl:
- value = VA_RC_CQP | VA_RC_CBR;
+ value = VA_RC_CQP | VA_RC_CBR | VA_RC_VBR;
  break;
   default:
  value = VA_ATTRIB_NOT_SUPPORTED;
diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index a283e83..7f3d96d 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -322,7 +322,7 @@ handleVAEncMiscParameterTypeRateControl(vlVaContext 
*context, VAEncMiscParameter
PIPE_H264_ENC_RATE_CONTROL_METHOD_CONSTANT)
   context->desc.h264enc.rate_ctrl.target_bitrate = rc->bits_per_second;
else
-  context->desc.h264enc.rate_ctrl.target_bitrate = rc->bits_per_second * 
rc->target_percentage;
+  context->desc.h264enc.rate_ctrl.target_bitrate = rc->bits_per_second * 
rc->target_percentage / 100;
context->desc.h264enc.rate_ctrl.peak_bitrate = rc->bits_per_second;
if (context->desc.h264enc.rate_ctrl.target_bitrate < 200)
   context->desc.h264enc.rate_ctrl.vbv_buffer_size = 
MIN2((context->desc.h264enc.rate_ctrl.target_bitrate * 2.75), 200);

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Mesa (master): vl/rbsp: match initial escaped bits with valid in the buffer

[Leo Liu]

Module: Mesa
Branch: master
Commit: 6a7f79af9b1ac4380e46c1bc438a7a491d1d99da
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a7f79af9b1ac4380e46c1bc438a7a491d1d99da

Author: Leo Liu 
Date:   Tue Sep  6 13:14:48 2016 -0400

vl/rbsp: match initial escaped bits with valid in the buffer

Otherwise the check for the three byte will not make sense.

Signed-off-by: Leo Liu 

---

 src/gallium/auxiliary/vl/vl_rbsp.h | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/vl/vl_rbsp.h 
b/src/gallium/auxiliary/vl/vl_rbsp.h
index 160b2f8..4d90c2d 100644
--- a/src/gallium/auxiliary/vl/vl_rbsp.h
+++ b/src/gallium/auxiliary/vl/vl_rbsp.h
@@ -56,8 +56,6 @@ static inline void vl_rbsp_init(struct vl_rbsp *rbsp, struct 
vl_vlc *nal, unsign
/* copy the position */
rbsp->nal = *nal;
 
-   rbsp->escaped = 16;
-
/* search for the end of the NAL unit */
while (vl_vlc_search_byte(nal, num_bits, 0x00)) {
   if (vl_vlc_peekbits(nal, 24) == 0x01 ||
@@ -76,6 +74,10 @@ static inline void vl_rbsp_init(struct vl_rbsp *rbsp, struct 
vl_vlc *nal, unsign
  i += 8;
   }
}
+
+   valid = vl_vlc_valid_bits(>nal);
+
+   rbsp->escaped = (valid >= 16) ? 16 : ((valid >= 8) ? 8 : 0);
 }
 
 /**

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Mesa (master): egl: fix gcc warning braces around scalar initializer

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 2da15a3b89aa6ab6f1a7f78f57e3ef91b2ddda50
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2da15a3b89aa6ab6f1a7f78f57e3ef91b2ddda50

Author: Timothy Arceri 
Date:   Mon Sep 12 09:24:00 2016 +1000

egl: fix gcc warning braces around scalar initializer

Reviewed-by: Alejandro Piñeiro 

---

 src/egl/main/eglcurrent.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/egl/main/eglcurrent.c b/src/egl/main/eglcurrent.c
index 345f4cc..2a225bc 100644
--- a/src/egl/main/eglcurrent.c
+++ b/src/egl/main/eglcurrent.c
@@ -38,7 +38,7 @@
 
 /* This should be kept in sync with _eglInitThreadInfo() */
 #define _EGL_THREAD_INFO_INITIALIZER \
-   { EGL_SUCCESS, { NULL }, 0 }
+   { EGL_SUCCESS, NULL, 0 }
 
 /* a fallback thread info to guarantee that every thread always has one */
 static _EGLThreadInfo dummy_thread = _EGL_THREAD_INFO_INITIALIZER;

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Mesa (master): winsys/amdgpu: add do_winsys_deinit function

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 480ac143df281fef762e30f92bccc3b89674fef8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=480ac143df281fef762e30f92bccc3b89674fef8

Author: Nicolai Hähnle 
Date:   Tue Sep  6 15:12:18 2016 +0200

winsys/amdgpu: add do_winsys_deinit function

The idea is to have matching init/deinit functions so that deinit can be
re-used for cleanup in the error path of amdgpu_winsys_create.

Reviewed-by: Marek Olšák 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 9 +++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index 521a78a..3961ee3 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -368,6 +368,12 @@ fail:
return false;
 }
 
+static void do_winsys_deinit(struct amdgpu_winsys *ws)
+{
+   AddrDestroy(ws->addrlib);
+   amdgpu_device_deinitialize(ws->dev);
+}
+
 static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
 {
struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
@@ -378,8 +384,7 @@ static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
pipe_mutex_destroy(ws->bo_fence_lock);
pb_cache_deinit(>bo_cache);
pipe_mutex_destroy(ws->global_bo_list_lock);
-   AddrDestroy(ws->addrlib);
-   amdgpu_device_deinitialize(ws->dev);
+   do_winsys_deinit(ws);
FREE(rws);
 }
 

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Mesa (master): gallium/radeon: page alignment for buffers is unnecessary

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: a6c38d47d422f66e4ba17f15144f68c574080b17
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a6c38d47d422f66e4ba17f15144f68c574080b17

Author: Nicolai Hähnle 
Date:   Fri Sep  9 12:59:10 2016 +0200

gallium/radeon: page alignment for buffers is unnecessary

In some places (e.g. shader program pointers) we require 256 bytes alignment.

Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeon/r600_pipe_common.c | 5 +
 1 file changed, 1 insertion(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 6d7cc1b..f0fdc9b 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -1081,11 +1081,8 @@ static void r600_query_memory_info(struct pipe_screen 
*screen,
 struct pipe_resource *r600_resource_create_common(struct pipe_screen *screen,
  const struct pipe_resource 
*templ)
 {
-   struct r600_common_screen *rscreen = (struct r600_common_screen*)screen;
-
if (templ->target == PIPE_BUFFER) {
-   return r600_buffer_create(screen, templ,
- rscreen->info.gart_page_size);
+   return r600_buffer_create(screen, templ, 256);
} else {
return r600_texture_create(screen, templ);
}

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Mesa (master): winsys/amdgpu: clean up error paths in amdgpu_winsys_create

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 9fb8d354cafd080e1616f5bd5e2f50b43c0d820f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9fb8d354cafd080e1616f5bd5e2f50b43c0d820f

Author: Nicolai Hähnle 
Date:   Tue Sep  6 15:10:06 2016 +0200

winsys/amdgpu: clean up error paths in amdgpu_winsys_create

No need to call pb_cache_deinit, because the cache hasn't been initialized
at that point.

Reviewed-by: Marek Olšák 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 12 +---
 1 file changed, 5 insertions(+), 7 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index 33aa492..521a78a 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -527,17 +527,15 @@ amdgpu_winsys_create(int fd, radeon_screen_create_t 
screen_create)
 
/* Create a new winsys. */
ws = CALLOC_STRUCT(amdgpu_winsys);
-   if (!ws) {
-  pipe_mutex_unlock(dev_tab_mutex);
-  return NULL;
-   }
+   if (!ws)
+  goto fail;
 
ws->dev = dev;
ws->info.drm_major = drm_major;
ws->info.drm_minor = drm_minor;
 
if (!do_winsys_init(ws, fd))
-  goto fail;
+  goto fail_alloc;
 
/* Create managers. */
pb_cache_init(>bo_cache, 50, ws->check_vm ? 1.0f : 2.0f, 0,
@@ -587,9 +585,9 @@ amdgpu_winsys_create(int fd, radeon_screen_create_t 
screen_create)
 
return >base;
 
+fail_alloc:
+   FREE(ws);
 fail:
pipe_mutex_unlock(dev_tab_mutex);
-   pb_cache_deinit(>bo_cache);
-   FREE(ws);
return NULL;
 }

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Mesa (master): winsys/amdgpu: extract adding a new buffer list entry into its own function

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: cc53dfda9f8b6731419c743d30bc470d36dea218
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc53dfda9f8b6731419c743d30bc470d36dea218

Author: Nicolai Hähnle 
Date:   Wed Sep  7 12:39:30 2016 +0200

winsys/amdgpu: extract adding a new buffer list entry into its own function

While at it, try to be a little more robust in the face of memory allocation
failure.

Reviewed-by: Marek Olšák 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 113 ++
 1 file changed, 70 insertions(+), 43 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 16dd45a..a5b350a 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -291,63 +291,90 @@ int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs, 
struct amdgpu_winsys_bo *
return -1;
 }
 
-static unsigned amdgpu_add_buffer(struct amdgpu_cs *acs,
- struct amdgpu_winsys_bo *bo,
- enum radeon_bo_usage usage,
- enum radeon_bo_domain domains,
- unsigned priority,
- enum radeon_bo_domain *added_domains)
+static int
+amdgpu_lookup_or_add_buffer(struct amdgpu_cs_context *cs, struct 
amdgpu_winsys_bo *bo)
 {
-   struct amdgpu_cs_context *cs = acs->csc;
struct amdgpu_cs_buffer *buffer;
-   unsigned hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1);
-   int i = -1;
+   unsigned hash;
+   int idx = amdgpu_lookup_buffer(cs, bo);
 
-   assert(priority < 64);
-   *added_domains = 0;
-
-   i = amdgpu_lookup_buffer(cs, bo);
-
-   if (i >= 0) {
-  buffer = >buffers[i];
-  buffer->priority_usage |= 1llu << priority;
-  buffer->usage |= usage;
-  *added_domains = domains & ~buffer->domains;
-  buffer->domains |= domains;
-  cs->flags[i] = MAX2(cs->flags[i], priority / 4);
-  return i;
-   }
+   if (idx >= 0)
+  return idx;
 
/* New buffer, check if the backing array is large enough. */
if (cs->num_buffers >= cs->max_num_buffers) {
-  uint32_t size;
-  cs->max_num_buffers += 10;
+  unsigned new_max =
+ MAX2(cs->max_num_buffers + 16, (unsigned)(cs->max_num_buffers * 1.3));
+  struct amdgpu_cs_buffer *new_buffers;
+  amdgpu_bo_handle *new_handles;
+  uint8_t *new_flags;
+
+  new_buffers = MALLOC(new_max * sizeof(*new_buffers));
+  new_handles = MALLOC(new_max * sizeof(*new_handles));
+  new_flags = MALLOC(new_max * sizeof(*new_flags));
+
+  if (!new_buffers || !new_handles || !new_flags) {
+ fprintf(stderr, "amdgpu_lookup_or_add_buffer: allocation failed\n");
+ FREE(new_buffers);
+ FREE(new_handles);
+ FREE(new_flags);
+ return -1;
+  }
 
-  size = cs->max_num_buffers * sizeof(struct amdgpu_cs_buffer);
-  cs->buffers = realloc(cs->buffers, size);
+  memcpy(new_buffers, cs->buffers, cs->num_buffers * sizeof(*new_buffers));
+  memcpy(new_handles, cs->handles, cs->num_buffers * sizeof(*new_handles));
+  memcpy(new_flags, cs->flags, cs->num_buffers * sizeof(*new_flags));
 
-  size = cs->max_num_buffers * sizeof(amdgpu_bo_handle);
-  cs->handles = realloc(cs->handles, size);
+  FREE(cs->buffers);
+  FREE(cs->handles);
+  FREE(cs->flags);
 
-  cs->flags = realloc(cs->flags, cs->max_num_buffers);
+  cs->max_num_buffers = new_max;
+  cs->buffers = new_buffers;
+  cs->handles = new_handles;
+  cs->flags = new_flags;
}
 
-   /* Initialize the new buffer. */
-   cs->buffers[cs->num_buffers].bo = NULL;
-   amdgpu_winsys_bo_reference(>buffers[cs->num_buffers].bo, bo);
-   cs->handles[cs->num_buffers] = bo->bo;
-   cs->flags[cs->num_buffers] = priority / 4;
+   idx = cs->num_buffers;
+   buffer = >buffers[idx];
+   memset(buffer, 0, sizeof(*buffer));
+   amdgpu_winsys_bo_reference(>bo, bo);
+   cs->handles[idx] = bo->bo;
+   cs->flags[idx] = 0;
p_atomic_inc(>num_cs_references);
-   buffer = >buffers[cs->num_buffers];
-   buffer->bo = bo;
-   buffer->priority_usage = 1llu << priority;
-   buffer->usage = usage;
-   buffer->domains = domains;
+   cs->num_buffers++;
 
-   cs->buffer_indices_hashlist[hash] = cs->num_buffers;
+   hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1);
+   cs->buffer_indices_hashlist[hash] = idx;
+
+   return idx;
+}
+
+static unsigned amdgpu_add_buffer(struct amdgpu_cs *acs,
+ struct amdgpu_winsys_bo *bo,
+ enum radeon_bo_usage usage,
+ enum radeon_bo_domain domains,
+ unsigned priority,
+ enum radeon_bo_domain *added_domains)
+{
+   struct amdgpu_cs_context *cs = acs->csc;
+   struct amdgpu_cs_buffer 

Mesa (master): gallium/radeon/winsyses: remove #includes of pb_bufmgr.h

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 339867c0774952e1174b8e3509383942e6e86b7f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=339867c0774952e1174b8e3509383942e6e86b7f

Author: Nicolai Hähnle 
Date:   Tue Sep  6 14:50:52 2016 +0200

gallium/radeon/winsyses: remove #includes of pb_bufmgr.h

Reviewed-by: Marek Olšák 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_bo.h | 1 -
 src/gallium/winsys/radeon/drm/radeon_drm_bo.h | 1 -
 src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 1 -
 3 files changed, 3 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
index e2ee049..70d9854 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
@@ -34,7 +34,6 @@
 #define AMDGPU_BO_H
 
 #include "amdgpu_winsys.h"
-#include "pipebuffer/pb_bufmgr.h"
 
 struct amdgpu_winsys_bo {
struct pb_buffer base;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.h 
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.h
index f7f4ce3..a9f31c0 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.h
@@ -33,7 +33,6 @@
 #define RADEON_DRM_BO_H
 
 #include "radeon_drm_winsys.h"
-#include "pipebuffer/pb_bufmgr.h"
 #include "os/os_thread.h"
 
 struct radeon_bo {
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index d73b7f4..aa4bf5f 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -35,7 +35,6 @@
 #include "radeon_drm_cs.h"
 #include "radeon_drm_public.h"
 
-#include "pipebuffer/pb_bufmgr.h"
 #include "util/u_memory.h"
 #include "util/u_hash_table.h"
 

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Mesa (master): winsys/amdgpu: remove amdgpu_cs_lookup_buffer

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 17fff0c2dece289214499a5621ca29ca08e639f0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=17fff0c2dece289214499a5621ca29ca08e639f0

Author: Nicolai Hähnle 
Date:   Thu Sep  8 09:31:53 2016 +0200

winsys/amdgpu: remove amdgpu_cs_lookup_buffer

The radeonsi driver doesn't and shouldn't care about the buffer index.
Only the virtual addresses matter.

Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeon/radeon_winsys.h | 3 +++
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c  | 9 -
 2 files changed, 3 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_winsys.h 
b/src/gallium/drivers/radeon/radeon_winsys.h
index 9693032..91f6e89 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -603,6 +603,9 @@ struct radeon_winsys {
 /**
  * Return the index of an already-added buffer.
  *
+ * Not supported on amdgpu. Drivers with GPUVM should not care about
+ * buffer indices.
+ *
  * \param csCommand stream
  * \param buf   Buffer
  * \return  The buffer index, or -1 if the buffer has not been 
added.
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 0783370..e2f2974 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -697,14 +697,6 @@ amdgpu_cs_add_const_preamble_ib(struct radeon_winsys_cs 
*rcs)
return >const_preamble_ib.base;
 }
 
-static int amdgpu_cs_lookup_buffer(struct radeon_winsys_cs *rcs,
-   struct pb_buffer *buf)
-{
-   struct amdgpu_cs *cs = amdgpu_cs(rcs);
-
-   return amdgpu_lookup_buffer(cs->csc, (struct amdgpu_winsys_bo*)buf);
-}
-
 static bool amdgpu_cs_validate(struct radeon_winsys_cs *rcs)
 {
return true;
@@ -1116,7 +1108,6 @@ void amdgpu_cs_init_functions(struct amdgpu_winsys *ws)
ws->base.cs_add_const_preamble_ib = amdgpu_cs_add_const_preamble_ib;
ws->base.cs_destroy = amdgpu_cs_destroy;
ws->base.cs_add_buffer = amdgpu_cs_add_buffer;
-   ws->base.cs_lookup_buffer = amdgpu_cs_lookup_buffer;
ws->base.cs_validate = amdgpu_cs_validate;
ws->base.cs_check_space = amdgpu_cs_check_space;
ws->base.cs_get_buffer_list = amdgpu_cs_get_buffer_list;

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Mesa (master): winsys/amdgpu: use only one fence per BO

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 11cbf4d7aea861e37067407ba7a660ea566c1593
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=11cbf4d7aea861e37067407ba7a660ea566c1593

Author: Nicolai Hähnle 
Date:   Wed Sep  7 10:50:14 2016 +0200

winsys/amdgpu: use only one fence per BO

The fence that is added to the BO during flush is guaranteed to be
signaled after all the fences that were in the fences array of the BO
before the flush, because those fences are added as dependencies for the
submission (and all this happens atomically under the bo_fence_lock).

Therefore, keeping only the last fence around is sufficient.

Reviewed-by: Marek Olšák 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 54 +++--
 src/gallium/winsys/amdgpu/drm/amdgpu_bo.h |  4 +-
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 66 +++
 3 files changed, 56 insertions(+), 68 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 32df0be..a6d4aa4 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -44,7 +44,6 @@ static bool amdgpu_bo_wait(struct pb_buffer *_buf, uint64_t 
timeout,
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
struct amdgpu_winsys *ws = bo->ws;
int64_t abs_timeout;
-   int i;
 
if (timeout == 0) {
   if (p_atomic_read(>num_active_ioctls))
@@ -75,49 +74,42 @@ static bool amdgpu_bo_wait(struct pb_buffer *_buf, uint64_t 
timeout,
 
if (timeout == 0) {
   pipe_mutex_lock(ws->bo_fence_lock);
-  for (i = 0; i < RING_LAST; i++)
- if (bo->fence[i]) {
-if (amdgpu_fence_wait(bo->fence[i], 0, false)) {
-   /* Release the idle fence to avoid checking it again later. */
-   amdgpu_fence_reference(>fence[i], NULL);
-} else {
-   pipe_mutex_unlock(ws->bo_fence_lock);
-   return false;
-}
+  if (bo->fence) {
+ if (amdgpu_fence_wait(bo->fence, 0, false)) {
+/* Release the idle fence to avoid checking it again later. */
+amdgpu_fence_reference(>fence, NULL);
+ } else {
+pipe_mutex_unlock(ws->bo_fence_lock);
+return false;
  }
+  }
   pipe_mutex_unlock(ws->bo_fence_lock);
   return true;
 
} else {
-  struct pipe_fence_handle *fence[RING_LAST] = {};
-  bool fence_idle[RING_LAST] = {};
+  struct pipe_fence_handle *fence = NULL;
+  bool fence_idle = false;
   bool buffer_idle = true;
 
-  /* Take references to all fences, so that we can wait for them
+  /* Take a reference to the fences, so that we can wait for it
* without the lock. */
   pipe_mutex_lock(ws->bo_fence_lock);
-  for (i = 0; i < RING_LAST; i++)
- amdgpu_fence_reference([i], bo->fence[i]);
+  amdgpu_fence_reference(, bo->fence);
   pipe_mutex_unlock(ws->bo_fence_lock);
 
-  /* Now wait for the fences. */
-  for (i = 0; i < RING_LAST; i++) {
- if (fence[i]) {
-if (amdgpu_fence_wait(fence[i], abs_timeout, true))
-   fence_idle[i] = true;
-else
-   buffer_idle = false;
- }
+  /* Now wait for the fence. */
+  if (fence) {
+ if (amdgpu_fence_wait(fence, abs_timeout, true))
+fence_idle = true;
+ else
+buffer_idle = false;
   }
 
   /* Release idle fences to avoid checking them again later. */
   pipe_mutex_lock(ws->bo_fence_lock);
-  for (i = 0; i < RING_LAST; i++) {
- if (fence[i] == bo->fence[i] && fence_idle[i])
-amdgpu_fence_reference(>fence[i], NULL);
-
- amdgpu_fence_reference([i], NULL);
-  }
+  if (fence == bo->fence && fence_idle)
+ amdgpu_fence_reference(>fence, NULL);
+  amdgpu_fence_reference(, NULL);
   pipe_mutex_unlock(ws->bo_fence_lock);
 
   return buffer_idle;
@@ -133,7 +125,6 @@ static enum radeon_bo_domain amdgpu_bo_get_initial_domain(
 void amdgpu_bo_destroy(struct pb_buffer *_buf)
 {
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
-   int i;
 
pipe_mutex_lock(bo->ws->global_bo_list_lock);
LIST_DEL(>global_list_item);
@@ -144,8 +135,7 @@ void amdgpu_bo_destroy(struct pb_buffer *_buf)
amdgpu_va_range_free(bo->va_handle);
amdgpu_bo_free(bo->bo);
 
-   for (i = 0; i < RING_LAST; i++)
-  amdgpu_fence_reference(>fence[i], NULL);
+   amdgpu_fence_reference(>fence, NULL);
 
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
   bo->ws->allocated_vram -= align64(bo->base.size, 
bo->ws->info.gart_page_size);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h 
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
index 70d9854..07403dd 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
@@ -62,8 +62,8 @@ struct 

Mesa (master): winsys/amdgpu: remove initial buffer list allocation

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 3cdeb2a177decd309810d52eb4ad6cd22a5c0e59
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3cdeb2a177decd309810d52eb4ad6cd22a5c0e59

Author: Nicolai Hähnle 
Date:   Wed Sep  7 12:42:15 2016 +0200

winsys/amdgpu: remove initial buffer list allocation

It's really not necessary.

Reviewed-by: Marek Olšák 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 20 
 1 file changed, 20 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index a5b350a..b572ad7 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -575,26 +575,6 @@ static bool amdgpu_init_cs_context(struct 
amdgpu_cs_context *cs,
   break;
}
 
-   cs->max_num_buffers = 512;
-   cs->buffers = (struct amdgpu_cs_buffer*)
-  CALLOC(1, cs->max_num_buffers * sizeof(struct 
amdgpu_cs_buffer));
-   if (!cs->buffers) {
-  return false;
-   }
-
-   cs->handles = CALLOC(1, cs->max_num_buffers * sizeof(amdgpu_bo_handle));
-   if (!cs->handles) {
-  FREE(cs->buffers);
-  return false;
-   }
-
-   cs->flags = CALLOC(1, cs->max_num_buffers);
-   if (!cs->flags) {
-  FREE(cs->handles);
-  FREE(cs->buffers);
-  return false;
-   }
-
for (i = 0; i < ARRAY_SIZE(cs->buffer_indices_hashlist); i++) {
   cs->buffer_indices_hashlist[i] = -1;
}

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Mesa (master): winsys/radeon: rename nrelocs, crelocs to max_relocs, num_relocs

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: b8703e363c7f949c7257c4ab1ab12c4663702dad
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b8703e363c7f949c7257c4ab1ab12c4663702dad

Author: Nicolai Hähnle 
Date:   Fri Sep  9 18:53:22 2016 +0200

winsys/radeon: rename nrelocs, crelocs to max_relocs, num_relocs

Reviewed-by: Marek Olšák 

---

 src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 48 +--
 src/gallium/winsys/radeon/drm/radeon_drm_cs.h |  6 ++--
 2 files changed, 27 insertions(+), 27 deletions(-)

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index 4f2501e..c4933f0 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -125,13 +125,13 @@ static void radeon_cs_context_cleanup(struct 
radeon_cs_context *csc)
 {
 unsigned i;
 
-for (i = 0; i < csc->crelocs; i++) {
+for (i = 0; i < csc->num_relocs; i++) {
 p_atomic_dec(>relocs_bo[i].bo->num_cs_references);
 radeon_bo_reference(>relocs_bo[i].bo, NULL);
 }
 
-csc->crelocs = 0;
-csc->validated_crelocs = 0;
+csc->num_relocs = 0;
+csc->num_validated_relocs = 0;
 csc->chunks[0].length_dw = 0;
 csc->chunks[1].length_dw = 0;
 
@@ -212,7 +212,7 @@ int radeon_lookup_buffer(struct radeon_cs_context *csc, 
struct radeon_bo *bo)
 return i;
 
 /* Hash collision, look for the BO in the list of relocs linearly. */
-for (i = csc->crelocs - 1; i >= 0; i--) {
+for (i = csc->num_relocs - 1; i >= 0; i--) {
 if (csc->relocs_bo[i].bo == bo) {
 /* Put this reloc in the hash list.
  * This will prevent additional hash collisions if there are
@@ -270,36 +270,36 @@ static unsigned radeon_add_buffer(struct radeon_drm_cs 
*cs,
 }
 
 /* New relocation, check if the backing array is large enough. */
-if (csc->crelocs >= csc->nrelocs) {
+if (csc->num_relocs >= csc->max_relocs) {
 uint32_t size;
-csc->nrelocs = MAX2(csc->nrelocs + 16, (unsigned)(csc->nrelocs * 1.3));
+csc->max_relocs = MAX2(csc->max_relocs + 16, 
(unsigned)(csc->max_relocs * 1.3));
 
-size = csc->nrelocs * sizeof(csc->relocs_bo[0]);
+size = csc->max_relocs * sizeof(csc->relocs_bo[0]);
 csc->relocs_bo = realloc(csc->relocs_bo, size);
 
-size = csc->nrelocs * sizeof(struct drm_radeon_cs_reloc);
+size = csc->max_relocs * sizeof(struct drm_radeon_cs_reloc);
 csc->relocs = realloc(csc->relocs, size);
 
 csc->chunks[1].chunk_data = (uint64_t)(uintptr_t)csc->relocs;
 }
 
 /* Initialize the new relocation. */
-csc->relocs_bo[csc->crelocs].bo = NULL;
-csc->relocs_bo[csc->crelocs].priority_usage = 1llu << priority;
-radeon_bo_reference(>relocs_bo[csc->crelocs].bo, bo);
+csc->relocs_bo[csc->num_relocs].bo = NULL;
+csc->relocs_bo[csc->num_relocs].priority_usage = 1llu << priority;
+radeon_bo_reference(>relocs_bo[csc->num_relocs].bo, bo);
 p_atomic_inc(>num_cs_references);
-reloc = >relocs[csc->crelocs];
+reloc = >relocs[csc->num_relocs];
 reloc->handle = bo->handle;
 reloc->read_domains = rd;
 reloc->write_domain = wd;
 reloc->flags = priority / 4;
 
-csc->reloc_indices_hashlist[hash] = csc->crelocs;
+csc->reloc_indices_hashlist[hash] = csc->num_relocs;
 
 csc->chunks[1].length_dw += RELOC_DWORDS;
 
 *added_domains = rd | wd;
-return csc->crelocs++;
+return csc->num_relocs++;
 }
 
 static unsigned radeon_drm_cs_add_buffer(struct radeon_winsys_cs *rcs,
@@ -338,21 +338,21 @@ static bool radeon_drm_cs_validate(struct 
radeon_winsys_cs *rcs)
 cs->base.used_vram < cs->ws->info.vram_size * 0.8;
 
 if (status) {
-cs->csc->validated_crelocs = cs->csc->crelocs;
+cs->csc->num_validated_relocs = cs->csc->num_relocs;
 } else {
 /* Remove lately-added buffers. The validation failed with them
  * and the CS is about to be flushed because of that. Keep only
  * the already-validated buffers. */
 unsigned i;
 
-for (i = cs->csc->validated_crelocs; i < cs->csc->crelocs; i++) {
+for (i = cs->csc->num_validated_relocs; i < cs->csc->num_relocs; i++) {
 p_atomic_dec(>csc->relocs_bo[i].bo->num_cs_references);
 radeon_bo_reference(>csc->relocs_bo[i].bo, NULL);
 }
-cs->csc->crelocs = cs->csc->validated_crelocs;
+cs->csc->num_relocs = cs->csc->num_validated_relocs;
 
 /* Flush if there are any relocs. Clean up otherwise. */
-if (cs->csc->crelocs) {
+if (cs->csc->num_relocs) {
 cs->flush_cs(cs->flush_data, RADEON_FLUSH_ASYNC, NULL);
 } else {
 radeon_cs_context_cleanup(cs->csc);
@@ -381,13 +381,13 @@ static unsigned radeon_drm_cs_get_buffer_list(struct 
radeon_winsys_cs *rcs,
 int i;
 
 if (list) {
-   

Mesa (master): winsys/amdgpu: remove unused field domains from amdgpu_cs_buffer

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 12657a7abf68ae9480140f39d2b614668f2551be
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=12657a7abf68ae9480140f39d2b614668f2551be

Author: Nicolai Hähnle 
Date:   Wed Sep  7 18:07:22 2016 +0200

winsys/amdgpu: remove unused field domains from amdgpu_cs_buffer

Reviewed-by: Marek Olšák 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 53 ++-
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.h |  1 -
 2 files changed, 17 insertions(+), 37 deletions(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index b572ad7..0783370 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -292,8 +292,9 @@ int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs, 
struct amdgpu_winsys_bo *
 }
 
 static int
-amdgpu_lookup_or_add_buffer(struct amdgpu_cs_context *cs, struct 
amdgpu_winsys_bo *bo)
+amdgpu_lookup_or_add_buffer(struct amdgpu_cs *acs, struct amdgpu_winsys_bo *bo)
 {
+   struct amdgpu_cs_context *cs = acs->csc;
struct amdgpu_cs_buffer *buffer;
unsigned hash;
int idx = amdgpu_lookup_buffer(cs, bo);
@@ -347,34 +348,12 @@ amdgpu_lookup_or_add_buffer(struct amdgpu_cs_context *cs, 
struct amdgpu_winsys_b
hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1);
cs->buffer_indices_hashlist[hash] = idx;
 
-   return idx;
-}
-
-static unsigned amdgpu_add_buffer(struct amdgpu_cs *acs,
- struct amdgpu_winsys_bo *bo,
- enum radeon_bo_usage usage,
- enum radeon_bo_domain domains,
- unsigned priority,
- enum radeon_bo_domain *added_domains)
-{
-   struct amdgpu_cs_context *cs = acs->csc;
-   struct amdgpu_cs_buffer *buffer;
-   int i = amdgpu_lookup_or_add_buffer(cs, bo);
-
-   assert(priority < 64);
-
-   if (i < 0) {
-  *added_domains = 0;
-  return ~0;
-   }
+   if (bo->initial_domain & RADEON_DOMAIN_VRAM)
+  acs->main.base.used_vram += bo->base.size;
+   else if (bo->initial_domain & RADEON_DOMAIN_GTT)
+  acs->main.base.used_gart += bo->base.size;
 
-   buffer = >buffers[i];
-   buffer->priority_usage |= 1llu << priority;
-   buffer->usage |= usage;
-   *added_domains = domains & ~buffer->domains;
-   buffer->domains |= domains;
-   cs->flags[i] = MAX2(cs->flags[i], priority / 4);
-   return i;
+   return idx;
 }
 
 static unsigned amdgpu_cs_add_buffer(struct radeon_winsys_cs *rcs,
@@ -386,17 +365,19 @@ static unsigned amdgpu_cs_add_buffer(struct 
radeon_winsys_cs *rcs,
/* Don't use the "domains" parameter. Amdgpu doesn't support changing
 * the buffer placement during command submission.
 */
-   struct amdgpu_cs *cs = amdgpu_cs(rcs);
+   struct amdgpu_cs *acs = amdgpu_cs(rcs);
+   struct amdgpu_cs_context *cs = acs->csc;
struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
-   enum radeon_bo_domain added_domains;
-   unsigned index = amdgpu_add_buffer(cs, bo, usage, bo->initial_domain,
- priority, _domains);
+   struct amdgpu_cs_buffer *buffer;
+   int index = amdgpu_lookup_or_add_buffer(acs, bo);
 
-   if (added_domains & RADEON_DOMAIN_VRAM)
-  cs->main.base.used_vram += bo->base.size;
-   else if (added_domains & RADEON_DOMAIN_GTT)
-  cs->main.base.used_gart += bo->base.size;
+   if (index < 0)
+  return 0;
 
+   buffer = >buffers[index];
+   buffer->priority_usage |= 1llu << priority;
+   buffer->usage |= usage;
+   cs->flags[index] = MAX2(cs->flags[index], priority / 4);
return index;
 }
 
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
index 7455061..51753db 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
@@ -47,7 +47,6 @@ struct amdgpu_cs_buffer {
struct amdgpu_winsys_bo *bo;
uint64_t priority_usage;
enum radeon_bo_usage usage;
-   enum radeon_bo_domain domains;
 };
 
 enum ib_type {

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Mesa (master): winsys/radeon: remove unused radeon_cs_context:: priority_usage

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: f47da2e34fd2480a15b50df2ac43487c7505674b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f47da2e34fd2480a15b50df2ac43487c7505674b

Author: Nicolai Hähnle 
Date:   Fri Sep  9 15:34:08 2016 +0200

winsys/radeon: remove unused radeon_cs_context::priority_usage

Reviewed-by: Marek Olšák 

---

 src/gallium/winsys/radeon/drm/radeon_drm_cs.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h 
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
index 76004c5..208452d 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
@@ -49,7 +49,6 @@ struct radeon_cs_context {
 unsignedvalidated_crelocs;
 struct radeon_bo_item   *relocs_bo;
 struct drm_radeon_cs_reloc  *relocs;
-uint64_t*priority_usage;
 
 int reloc_indices_hashlist[4096];
 };

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Mesa (master): winsys/radeon: don't pre-allocate the relocations array

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: d66bbfbeded04cb728a2d8e4356c8e2b5e67ace1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d66bbfbeded04cb728a2d8e4356c8e2b5e67ace1

Author: Nicolai Hähnle 
Date:   Fri Sep  9 18:50:34 2016 +0200

winsys/radeon: don't pre-allocate the relocations array

It's really not necessary. Switch to an exponential resizing strategy.

Reviewed-by: Marek Olšák 

---

 src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 15 +--
 1 file changed, 1 insertion(+), 14 deletions(-)

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index 9de00c2..4f2501e 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -98,19 +98,6 @@ static bool radeon_init_cs_context(struct radeon_cs_context 
*csc,
 int i;
 
 csc->fd = ws->fd;
-csc->nrelocs = 512;
-csc->relocs_bo = (struct radeon_bo_item*)
- CALLOC(1, csc->nrelocs * sizeof(csc->relocs_bo[0]));
-if (!csc->relocs_bo) {
-return false;
-}
-
-csc->relocs = (struct drm_radeon_cs_reloc*)
-  CALLOC(1, csc->nrelocs * sizeof(struct drm_radeon_cs_reloc));
-if (!csc->relocs) {
-FREE(csc->relocs_bo);
-return false;
-}
 
 csc->chunks[0].chunk_id = RADEON_CHUNK_ID_IB;
 csc->chunks[0].length_dw = 0;
@@ -285,7 +272,7 @@ static unsigned radeon_add_buffer(struct radeon_drm_cs *cs,
 /* New relocation, check if the backing array is large enough. */
 if (csc->crelocs >= csc->nrelocs) {
 uint32_t size;
-csc->nrelocs += 10;
+csc->nrelocs = MAX2(csc->nrelocs + 16, (unsigned)(csc->nrelocs * 1.3));
 
 size = csc->nrelocs * sizeof(csc->relocs_bo[0]);
 csc->relocs_bo = realloc(csc->relocs_bo, size);

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Mesa (master): i965/rbc: Clarify rational given for shader image resolves

[Topi Pohjolainen]

Module: Mesa
Branch: master
Commit: e54b70b3d4e88c71b47a9123d496dd05e0e056cd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e54b70b3d4e88c71b47a9123d496dd05e0e056cd

Author: Topi Pohjolainen 
Date:   Thu Sep  8 08:22:38 2016 +0300

i965/rbc: Clarify rational given for shader image resolves

Original commit added documentation explaining lossless compression
case:

commit 56f29911ec9da25c78fbd3d4945d499e65ca4b5a
Author: Topi Pohjolainen 
Date:   Tue Feb 2 10:00:41 2016 +0200

i965: Add a flag telling color resolve pass to ignore CCS_E

It, however, easily gives the impression that the sole purpose
of the intel_miptree_resolve_color() is to address lossless
compression. Original intention is to document the lack of
INTEL_MIPTREE_IGNORE_CCS_E flag given for the resolve call.

This patch fixes this along with a typo found spotted further
down.

Signed-off-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_context.c | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 0e36d47..c28401a 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -283,8 +283,9 @@ intel_update_state(struct gl_context * ctx, GLuint 
new_state)
/* Access to images is implemented using indirect messages
 * against data port. Normal render target write understands
 * lossless compression but unfortunately the typed/untyped
-* read/write interface doesn't. Therefore the compressed
-* surfaces need to be resolved prior to accessing them.
+* read/write interface doesn't. Therefore even lossless
+* compressed surfaces need to be resolved prior to accessing
+* them. Hence skip setting INTEL_MIPTREE_IGNORE_CCS_E.
 */
intel_miptree_resolve_color(brw, tex_obj->mt, 0);
 
@@ -300,7 +301,7 @@ intel_update_state(struct gl_context * ctx, GLuint 
new_state)
   }
}
 
-   /* Resolve color buffers for non-coherent framebufer fetch. */
+   /* Resolve color buffers for non-coherent framebuffer fetch. */
if (!ctx->Extensions.MESA_shader_framebuffer_fetch &&
ctx->FragmentProgram._Current &&
ctx->FragmentProgram._Current->Base.OutputsRead) {

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Mesa (master): i965/rbc: Consult rb settings for texture surface setup

[Topi Pohjolainen]

Module: Mesa
Branch: master
Commit: 1b6fcc08df677725cf5ee4e913ebfbd2bff27e22
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b6fcc08df677725cf5ee4e913ebfbd2bff27e22

Author: Topi Pohjolainen 
Date:   Wed Aug 31 10:08:17 2016 +0300

i965/rbc: Consult rb settings for texture surface setup

Once mcs buffer gets allocated without delay for lossless
compression (same as we do for msaa), one gets regression in:

GL45-CTS.texture_barrier_ARB.same-texel-rw

Setting the auxiliary surface for both sampling engine and data
port seems to fix this. I haven't found any hardware documentation
backing this though.

v2 (Jason): Prepare also for the case where surface is sampled with
non-compressible format forcing also rendering without
compression.
v3: Split asserts and decision making.
v4: Detailed comment provided by Jason explaining the need for using
auxiliary buffer for texturing when the same surface is also
used as render target.
Added check for existence of renderbuffer before considering if
underlying miptree matches.

Signed-off-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 67 +---
 1 file changed, 60 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 62a4eb8..f12df8f 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -140,9 +140,7 @@ brw_emit_surface_state(struct brw_context *brw,
struct isl_surf *aux_surf = NULL, aux_surf_s;
uint64_t aux_offset = 0;
enum isl_aux_usage aux_usage = ISL_AUX_USAGE_NONE;
-   if (mt->mcs_mt &&
-   ((view.usage & ISL_SURF_USAGE_RENDER_TARGET_BIT) ||
-mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_RESOLVED)) {
+   if (mt->mcs_mt && !(flags & INTEL_AUX_BUFFER_DISABLED)) {
   intel_miptree_get_aux_isl_surf(brw, mt, _surf_s, _usage);
   aux_surf = _surf_s;
   assert(mt->mcs_mt->offset == 0);
@@ -425,6 +423,58 @@ swizzle_to_scs(GLenum swizzle, bool need_green_to_blue)
return (need_green_to_blue && scs == HSW_SCS_GREEN) ? HSW_SCS_BLUE : scs;
 }
 
+static unsigned
+brw_find_matching_rb(const struct gl_framebuffer *fb,
+ const struct intel_mipmap_tree *mt)
+{
+   for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
+  const struct intel_renderbuffer *irb =
+ intel_renderbuffer(fb->_ColorDrawBuffers[i]);
+
+  if (irb && irb->mt == mt)
+ return i;
+   }
+
+   return fb->_NumColorDrawBuffers;
+}
+
+static bool
+brw_disable_aux_surface(const struct brw_context *brw,
+const struct intel_mipmap_tree *mt)
+{
+   /* Nothing to disable. */
+   if (!mt->mcs_mt)
+  return false;
+
+   /* There are special cases only for lossless compression. */
+   if (!intel_miptree_is_lossless_compressed(brw, mt))
+  return mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED;
+
+   const struct gl_framebuffer *fb = brw->ctx.DrawBuffer;
+   const unsigned rb_index = brw_find_matching_rb(fb, mt);
+
+   /* If we are drawing into this with compression enabled, then we must also
+* enable compression when texturing from it regardless of
+* fast_clear_state.  If we don't then, after the first draw call with
+* this setup, there will be data in the CCS which won't get picked up by
+* subsequent texturing operations as required by ARB_texture_barrier.
+* Since we don't want to re-emit the binding table or do a resolve
+* operation every draw call, the easiest thing to do is just enable
+* compression on the texturing side.  This is completely safe to do
+* since, if compressed texturing weren't allowed, we would have disabled
+* compression of render targets in whatever_that_function_is_called().
+*/
+   if (rb_index < fb->_NumColorDrawBuffers) {
+  if (brw->draw_aux_buffer_disabled[rb_index]) {
+ assert(mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED);
+  }
+
+  return brw->draw_aux_buffer_disabled[rb_index];
+   }
+
+   return mt->fast_clear_state == INTEL_FAST_CLEAR_STATE_RESOLVED;
+}
+
 void
 brw_update_texture_surface(struct gl_context *ctx,
unsigned unit,
@@ -542,7 +592,8 @@ brw_update_texture_surface(struct gl_context *ctx,
   obj->Target == GL_TEXTURE_CUBE_MAP_ARRAY)
  view.usage |= ISL_SURF_USAGE_CUBE_BIT;
 
-  const int flags = 0;
+  const int flags =
+ brw_disable_aux_surface(brw, mt) ? INTEL_AUX_BUFFER_DISABLED : 0;
   brw_emit_surface_state(brw, mt, flags, mt->target, view,
  surface_state_infos[brw->gen].tex_mocs,
  surf_offset, surf_index,
@@ -1113,7 +1164,8 @@ update_renderbuffer_read_surfaces(struct brw_context *brw)
  

Mesa (master): i965/blorp: Sanity check all layers before actual clear

[Topi Pohjolainen]

Module: Mesa
Branch: master
Commit: b712aa2614447985cacabdd375ab99ff18bd1e71
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b712aa2614447985cacabdd375ab99ff18bd1e71

Author: Topi Pohjolainen 
Date:   Mon Aug 29 10:16:40 2016 +0300

i965/blorp: Sanity check all layers before actual clear

Signed-off-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_blorp.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index dc2be1e..703e547 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -720,7 +720,6 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
   }
}
 
-   intel_miptree_check_level_layer(irb->mt, irb->mt_level, layer);
intel_miptree_used_for_rendering(irb->mt);
 
/* We can't setup the blorp_surf until we've allocated the MCS above */
@@ -790,12 +789,16 @@ brw_blorp_clear_color(struct brw_context *brw, struct 
gl_framebuffer *fb,
   if (rb == NULL)
  continue;
 
+  const unsigned num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
+  for (unsigned layer = 0; layer < num_layers; layer++) {
+ intel_miptree_check_level_layer(irb->mt, irb->mt_level, layer);
+  }
+
   if (fb->MaxNumLayers > 0) {
  unsigned layer_multiplier =
 (irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
  irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) ?
 irb->mt->num_samples : 1;
- unsigned num_layers = irb->layer_count;
  for (unsigned layer = 0; layer < num_layers; layer++) {
 if (!do_single_blorp_clear(
 brw, fb, rb, buf, partial_clear, encode_srgb,

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Mesa (master): i965/blorp: Instruct vertex fetcher to provide prim instance id

[Topi Pohjolainen]

Module: Mesa
Branch: master
Commit: e597821ef2292fff42488d44917f3480cceb56ad
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e597821ef2292fff42488d44917f3480cceb56ad

Author: Topi Pohjolainen 
Date:   Fri Aug 26 17:37:44 2016 +0300

i965/blorp: Instruct vertex fetcher to provide prim instance id

This will indicate target layer (Render Target Array Index) needed
for layered clears.

v2: Use 3DSTATE_VF_SGVS for gen8+

Signed-off-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/intel/blorp/blorp_genX_exec.h | 26 ++
 1 file changed, 22 insertions(+), 4 deletions(-)

diff --git a/src/intel/blorp/blorp_genX_exec.h 
b/src/intel/blorp/blorp_genX_exec.h
index d049eb0..65a981d 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -293,8 +293,10 @@ blorp_emit_vertex_elements(struct blorp_batch *batch,
 * the URB. This is controlled by the 3DSTATE_VERTEX_BUFFERS and
 * 3DSTATE_VERTEX_ELEMENTS packets below. The VUE contents are as follows:
 *   dw0: Reserved, MBZ.
-*   dw1: Render Target Array Index. The HiZ op does not use indexed
-*vertices, so set the dword to 0.
+*   dw1: Render Target Array Index. Below vertex fetcher gets programmed
+*to assign this with primitive instance identifier which will be
+*used for layered clears. All other renders have only one instance
+*and therefore the value will be effectively zero.
 *   dw2: Viewport Index. The HiZ op disables viewport mapping and
 *scissoring, so set the dword to 0.
 *   dw3: Point Width: The HiZ op does not emit the POINTLIST primitive,
@@ -313,7 +315,7 @@ blorp_emit_vertex_elements(struct blorp_batch *batch,
 * "Vertex URB Entry (VUE) Formats".
 *
 * Only vertex position X and Y are going to be variable, Z is fixed to
-* zero and W to one. Header words dw0-3 are all zero. There is no need to
+* zero and W to one. Header words dw0,2,3 are zero. There is no need to
 * include the fixed values in the vertex buffer. Vertex fetcher can be
 * instructed to fill vertex elements with constant values of one and zero
 * instead of reading them from the buffer.
@@ -327,7 +329,16 @@ blorp_emit_vertex_elements(struct blorp_batch *batch,
ve[0].SourceElementFormat = ISL_FORMAT_R32G32B32A32_FLOAT;
ve[0].SourceElementOffset = 0;
ve[0].Component0Control = VFCOMP_STORE_0;
+
+   /* From Gen8 onwards hardware is no more instructed to overwrite components
+* using an element specifier. Instead one has separate 3DSTATE_VF_SGVS
+* (System Generated Value Setup) state packet for it.
+*/
+#if GEN_GEN >= 8
ve[0].Component1Control = VFCOMP_STORE_0;
+#else
+   ve[0].Component1Control = VFCOMP_STORE_IID;
+#endif
ve[0].Component2Control = VFCOMP_STORE_0;
ve[0].Component3Control = VFCOMP_STORE_0;
 
@@ -361,7 +372,14 @@ blorp_emit_vertex_elements(struct blorp_batch *batch,
}
 
 #if GEN_GEN >= 8
-   blorp_emit(batch, GENX(3DSTATE_VF_SGVS), sgvs);
+   /* Overwrite Render Target Array Index (2nd dword) in the VUE header with
+* primitive instance identifier. This is used for layered clears.
+*/
+   blorp_emit(batch, GENX(3DSTATE_VF_SGVS), sgvs) {
+  sgvs.InstanceIDEnable = true;
+  sgvs.InstanceIDComponentNumber = COMP_1;
+  sgvs.InstanceIDElementOffset = 0;
+   }
 
for (unsigned i = 0; i < num_elements; i++) {
   blorp_emit(batch, GENX(3DSTATE_VF_INSTANCING), vf) {

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Mesa (master): i965: Replace boolean rb surface state setup argument with flags

[Topi Pohjolainen]

Module: Mesa
Branch: master
Commit: 1f51217d99e7eb70a62b2611cd1b70f9b5a40fcf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f51217d99e7eb70a62b2611cd1b70f9b5a40fcf

Author: Topi Pohjolainen 
Date:   Mon Sep  5 15:14:11 2016 +0300

i965: Replace boolean rb surface state setup argument with flags

And add plumbing to provide it all the way to surface state emitter.
This is not used yet but will be in subsequent patches to carry
additional constraints.

v2 (Jason): Use uint32_t instead of int as the type

Signed-off-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_context.h  |  2 +-
 src/mesa/drivers/dri/i965/brw_state.h|  2 +-
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 28 +++-
 3 files changed, 20 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index e7c90b7..7780ce5 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -747,7 +747,7 @@ struct brw_context
{
   uint32_t (*update_renderbuffer_surface)(struct brw_context *brw,
   struct gl_renderbuffer *rb,
-  bool layered, unsigned unit,
+  uint32_t flags, unsigned unit,
   uint32_t surf_index);
   void (*emit_null_surface_state)(struct brw_context *brw,
   unsigned width,
diff --git a/src/mesa/drivers/dri/i965/brw_state.h 
b/src/mesa/drivers/dri/i965/brw_state.h
index bfcdf29..b42b9af 100644
--- a/src/mesa/drivers/dri/i965/brw_state.h
+++ b/src/mesa/drivers/dri/i965/brw_state.h
@@ -288,7 +288,7 @@ void brw_update_texture_surface(struct gl_context *ctx,
 
 uint32_t brw_update_renderbuffer_surface(struct brw_context *brw,
  struct gl_renderbuffer *rb,
- bool layered, unsigned unit,
+ uint32_t flags, unsigned unit,
  uint32_t surf_index);
 
 void brw_update_renderbuffer_surfaces(struct brw_context *brw,
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index c347b5d..0683b76 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -54,6 +54,10 @@
 #include "brw_defines.h"
 #include "brw_wm.h"
 
+enum {
+   INTEL_RENDERBUFFER_LAYERED = 1 << 0,
+};
+
 struct surface_state_info {
unsigned num_dwords;
unsigned ss_align; /* Required alignment of RENDER_SURFACE_STATE in bytes */
@@ -74,7 +78,7 @@ static const struct surface_state_info surface_state_infos[] 
= {
 
 static void
 brw_emit_surface_state(struct brw_context *brw,
-   struct intel_mipmap_tree *mt,
+   struct intel_mipmap_tree *mt, uint32_t flags,
GLenum target, struct isl_view view,
uint32_t mocs, uint32_t *surf_offset, int surf_index,
unsigned read_domains, unsigned write_domains)
@@ -183,7 +187,7 @@ brw_emit_surface_state(struct brw_context *brw,
 uint32_t
 brw_update_renderbuffer_surface(struct brw_context *brw,
 struct gl_renderbuffer *rb,
-bool layered, unsigned unit /* unused */,
+uint32_t flags, unsigned unit /* unused */,
 uint32_t surf_index)
 {
struct gl_context *ctx = >ctx;
@@ -220,7 +224,7 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
};
 
uint32_t offset;
-   brw_emit_surface_state(brw, mt, mt->target, view,
+   brw_emit_surface_state(brw, mt, flags, mt->target, view,
   surface_state_infos[brw->gen].rb_mocs,
   , surf_index,
   I915_GEM_DOMAIN_RENDER,
@@ -533,7 +537,8 @@ brw_update_texture_surface(struct gl_context *ctx,
   obj->Target == GL_TEXTURE_CUBE_MAP_ARRAY)
  view.usage |= ISL_SURF_USAGE_CUBE_BIT;
 
-  brw_emit_surface_state(brw, mt, mt->target, view,
+  const int flags = 0;
+  brw_emit_surface_state(brw, mt, flags, mt->target, view,
  surface_state_infos[brw->gen].tex_mocs,
  surf_offset, surf_index,
  I915_GEM_DOMAIN_SAMPLER, 0);
@@ -865,7 +870,7 @@ brw_emit_null_surface_state(struct brw_context *brw,
 static uint32_t
 gen4_update_renderbuffer_surface(struct brw_context *brw,
  struct gl_renderbuffer *rb,
- bool layered, unsigned unit,
+ 

Mesa (master): i965/blorp: Use hw generetad primitive copies for layered clears

[Topi Pohjolainen]

Module: Mesa
Branch: master
Commit: 1df4b666ed72b07b295b1117aec9938127160261
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1df4b666ed72b07b295b1117aec9938127160261

Author: Topi Pohjolainen 
Date:   Mon Aug 29 08:57:31 2016 +0300

i965/blorp: Use hw generetad primitive copies for layered clears

Signed-off-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_blorp.c | 36 ---
 1 file changed, 12 insertions(+), 24 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 703e547..712a228 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -653,7 +653,7 @@ set_write_disables(const struct intel_renderbuffer *irb,
 static bool
 do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb,
   struct gl_renderbuffer *rb, unsigned buf,
-  bool partial_clear, bool encode_srgb, unsigned layer)
+  bool partial_clear, bool encode_srgb)
 {
struct gl_context *ctx = >ctx;
struct intel_renderbuffer *irb = intel_renderbuffer(rb);
@@ -727,16 +727,17 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
struct blorp_surf surf;
unsigned level = irb->mt_level;
blorp_surf_for_miptree(brw, , irb->mt, true, , isl_tmp);
+   const unsigned num_layers = fb->MaxNumLayers ? irb->layer_count : 1;
 
if (can_fast_clear) {
-  DBG("%s (fast) to mt %p level %d layer %d\n", __FUNCTION__,
-  irb->mt, irb->mt_level, irb->mt_layer);
+  DBG("%s (fast) to mt %p level %d layers %d+%d\n", __FUNCTION__,
+  irb->mt, irb->mt_level, irb->mt_layer, num_layers);
 
   struct blorp_batch batch;
   blorp_batch_init(>blorp, , brw);
   blorp_fast_clear(, ,
(enum isl_format)brw->render_target_format[format],
-   level, layer, 1, x0, y0, x1, y1);
+   level, irb->mt_layer, num_layers, x0, y0, x1, y1);
   blorp_batch_finish();
 
   /* Now that the fast clear has occurred, put the buffer in
@@ -745,15 +746,16 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
*/
   irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_CLEAR;
} else {
-  DBG("%s (slow) to mt %p level %d layer %d\n", __FUNCTION__,
-  irb->mt, irb->mt_level, irb->mt_layer);
+  DBG("%s (slow) to mt %p level %d layer %d+%d\n", __FUNCTION__,
+  irb->mt, irb->mt_level, irb->mt_layer, num_layers);
 
   union isl_color_value clear_color;
   memcpy(clear_color.f32, ctx->Color.ClearColor.f, sizeof(float) * 4);
 
   struct blorp_batch batch;
   blorp_batch_init(>blorp, , brw);
-  blorp_clear(, , level, layer, 1, x0, y0, x1, y1,
+  blorp_clear(, , level, irb->mt_layer, num_layers,
+  x0, y0, x1, y1,
   (enum isl_format)brw->render_target_format[format],
   clear_color, color_write_disable);
   blorp_batch_finish();
@@ -794,23 +796,9 @@ brw_blorp_clear_color(struct brw_context *brw, struct 
gl_framebuffer *fb,
  intel_miptree_check_level_layer(irb->mt, irb->mt_level, layer);
   }
 
-  if (fb->MaxNumLayers > 0) {
- unsigned layer_multiplier =
-(irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_UMS ||
- irb->mt->msaa_layout == INTEL_MSAA_LAYOUT_CMS) ?
-irb->mt->num_samples : 1;
- for (unsigned layer = 0; layer < num_layers; layer++) {
-if (!do_single_blorp_clear(
-brw, fb, rb, buf, partial_clear, encode_srgb,
-irb->mt_layer + layer * layer_multiplier)) {
-   return false;
-}
- }
-  } else {
- unsigned layer = irb->mt_layer;
- if (!do_single_blorp_clear(brw, fb, rb, buf, partial_clear,
-encode_srgb, layer))
-return false;
+  if (!do_single_blorp_clear(brw, fb, rb, buf, partial_clear,
+ encode_srgb)) {
+ return false;
   }
 
   irb->need_downsample = true;

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Mesa (master): i965/rbc: Allow integer formats as advertised in isl_format.c

[Topi Pohjolainen]

Module: Mesa
Branch: master
Commit: 1634a4963c64d84da89ce47ba01828a7fc22d22a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1634a4963c64d84da89ce47ba01828a7fc22d22a

Author: Topi Pohjolainen 
Date:   Thu Aug 25 17:46:09 2016 +0300

i965/rbc: Allow integer formats as advertised in isl_format.c

Blorp consults brw_is_color_fast_clear_compatible() to see if any
restrictions apply for fast clear in addition to the capablities
advertised in isl_format.c::format_info[]. On Gen8+ integer formats
are backlisted for plain old fast clear but there is no reason why
lossless compression shouldn't be supported. In fact, lossless
compression of integer formats is already supported for normal
render paths.

This patch prepares for dropping the delayed allocating of the mcs
buffer for lossless compression. Until now the skip of fast clear
also prevented the mcs being allocated and hence the lossless
compression being effectively turned off for integer formats.
Once the mcs buffer is allocated beforehand, the assertion addressed
here would start triggering.

v2: Drop the assert instead of relaxing it (Jason)
Fix typo while at it.

Signed-off-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_blorp.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index c902f2e..b0fbb64 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -759,10 +759,9 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
 
   if (intel_miptree_is_lossless_compressed(brw, irb->mt)) {
  /* Compressed buffers can be cleared also using normal rep-clear. In
-  * such case they bahave such as if they were drawn using normal 3D
+  * such case they behave such as if they were drawn using normal 3D
   * render pipeline, and we simply mark the mcs as dirty.
   */
- assert(partial_clear);
  irb->mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_UNRESOLVED;
   }
}

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Mesa (master): intel/blorp: Allow multiple layers

[Topi Pohjolainen]

Module: Mesa
Branch: master
Commit: 514afdce95e1c75a754412203425a8ac1282cd2d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=514afdce95e1c75a754412203425a8ac1282cd2d

Author: Topi Pohjolainen 
Date:   Fri Aug 26 18:37:09 2016 +0300

intel/blorp: Allow multiple layers

Signed-off-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/intel/blorp/blorp.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c
index 4dbba01..17c1ff4 100644
--- a/src/intel/blorp/blorp.c
+++ b/src/intel/blorp/blorp.c
@@ -119,6 +119,9 @@ brw_blorp_surface_info_init(struct blorp_context *blorp,
   },
};
 
+   info->view.array_len = MAX2(info->surf.logical_level0_px.depth,
+   info->surf.logical_level0_px.array_len);
+
if (!is_render_target &&
(info->surf.dim == ISL_SURF_DIM_3D ||
 info->surf.msaa_layout == ISL_MSAA_LAYOUT_ARRAY)) {
@@ -128,12 +131,12 @@ brw_blorp_surface_info_init(struct blorp_context *blorp,
* guaranteed that we won't be doing any funny surface hacks.
*/
   info->view.base_array_layer = 0;
-  info->view.array_len = MAX2(info->surf.logical_level0_px.depth,
-  info->surf.logical_level0_px.array_len);
   info->z_offset = layer / layer_multiplier;
} else {
   info->view.base_array_layer = layer / layer_multiplier;
-  info->view.array_len = 1;
+
+  assert(info->view.array_len >= info->view.base_array_layer);
+  info->view.array_len -= info->view.base_array_layer;
   info->z_offset = 0;
}
 }

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Mesa (master): isl/gen8+: Allow 1D and 3D auxiliary surfaces

[Topi Pohjolainen]

Module: Mesa
Branch: master
Commit: 024a39511f95a156b7d6524fc0770d95fbbcd1d0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=024a39511f95a156b7d6524fc0770d95fbbcd1d0

Author: Topi Pohjolainen 
Date:   Wed Aug 31 11:16:12 2016 +0300

isl/gen8+: Allow 1D and 3D auxiliary surfaces

Otherwise once mcs buffer gets allocated without delay for lossless
compression (same as we do for msaa), assert starts to fire in
piglit case: tex3d. The test uses depth of one which is in fact
supported even now.

v2 (Jason): Allow also 1D case as there is nothing in the specs
constraining it either.

Signed-off-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/intel/isl/isl.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c
index c7639d0..3dfdf20 100644
--- a/src/intel/isl/isl.c
+++ b/src/intel/isl/isl.c
@@ -1329,7 +1329,8 @@ isl_surf_get_ccs_surf(const struct isl_device *dev,
assert(surf->samples == 1 && surf->msaa_layout == ISL_MSAA_LAYOUT_NONE);
assert(ISL_DEV_GEN(dev) >= 7);
 
-   assert(surf->dim == ISL_SURF_DIM_2D);
+   assert(ISL_DEV_GEN(dev) >= 8 || surf->dim == ISL_SURF_DIM_2D);
+
assert(surf->logical_level0_px.depth == 1);
 
/* TODO: More conditions where it can fail. */

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Mesa (master): i965: Add sanity check for non-compressible texture views

[Topi Pohjolainen]

Module: Mesa
Branch: master
Commit: 6939532593efb5f6dc0ddb79081989f31d0a6851
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6939532593efb5f6dc0ddb79081989f31d0a6851

Author: Topi Pohjolainen 
Date:   Wed Sep  7 09:38:11 2016 +0300

i965: Add sanity check for non-compressible texture views

v2: Fix missing inline declaration

Signed-off-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 34 
 1 file changed, 34 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index f12df8f..89d76c1 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -438,6 +438,38 @@ brw_find_matching_rb(const struct gl_framebuffer *fb,
return fb->_NumColorDrawBuffers;
 }
 
+static inline bool
+brw_texture_view_sane(const struct brw_context *brw,
+  const struct intel_mipmap_tree *mt, unsigned format)
+{
+   /* There are special cases only for lossless compression. */
+   if (!intel_miptree_is_lossless_compressed(brw, mt))
+  return true;
+
+   if (isl_format_supports_lossless_compression(brw->intelScreen->devinfo,
+format))
+  return true;
+
+   /* Logic elsewhere needs to take care to resolve the color buffer prior
+* to sampling it as non-compressed.
+*/
+   if (mt->fast_clear_state != INTEL_FAST_CLEAR_STATE_RESOLVED)
+  return false;
+
+   const struct gl_framebuffer *fb = brw->ctx.DrawBuffer;
+   const unsigned rb_index = brw_find_matching_rb(fb, mt);
+
+   if (rb_index == fb->_NumColorDrawBuffers)
+  return true;
+
+   /* Underlying surface is compressed but it is sampled using a format that
+* the sampling engine doesn't support as compressed. Compression must be
+* disabled for both sampling engine and data port in case the same surface
+* is used also as render target.
+*/
+   return brw->draw_aux_buffer_disabled[rb_index];
+}
+
 static bool
 brw_disable_aux_surface(const struct brw_context *brw,
 const struct intel_mipmap_tree *mt)
@@ -592,6 +624,8 @@ brw_update_texture_surface(struct gl_context *ctx,
   obj->Target == GL_TEXTURE_CUBE_MAP_ARRAY)
  view.usage |= ISL_SURF_USAGE_CUBE_BIT;
 
+  assert(brw_texture_view_sane(brw, mt, format));
+
   const int flags =
  brw_disable_aux_surface(brw, mt) ? INTEL_AUX_BUFFER_DISABLED : 0;
   brw_emit_surface_state(brw, mt, flags, mt->target, view,

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Mesa (master): i965: Track non-compressible sampling of renderbuffers

[Topi Pohjolainen]

Module: Mesa
Branch: master
Commit: 22d9a4824baf0bf89bb8e39025ad01fecb213888
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=22d9a4824baf0bf89bb8e39025ad01fecb213888

Author: Topi Pohjolainen 
Date:   Sun Sep  4 11:02:39 2016 +0300

i965: Track non-compressible sampling of renderbuffers

v3:
   - Actually set the flags when needed instead of falsely
 overwriting them (Jason).
   - Use more generic name for flag (dropped RENDERBUFFER)
   - Consult also shader images
v4:
   - Consult only lossless compressd shader images

v5:
   - Check the existence of renderbuffer before considering
 if it matches the given miptree

Signed-off-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_context.c  | 32 
 src/mesa/drivers/dri/i965/brw_context.h  | 10 
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 +++--
 3 files changed, 52 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index b880b4f..0e36d47 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -168,6 +168,24 @@ intel_update_framebuffer(struct gl_context *ctx,
  fb->DefaultGeometry.NumSamples);
 }
 
+static bool
+intel_disable_rb_aux_buffer(struct brw_context *brw, const drm_intel_bo *bo)
+{
+   const struct gl_framebuffer *fb = brw->ctx.DrawBuffer;
+   bool found = false;
+
+   for (unsigned i = 0; i < fb->_NumColorDrawBuffers; i++) {
+  const struct intel_renderbuffer *irb =
+ intel_renderbuffer(fb->_ColorDrawBuffers[i]);
+
+  if (irb && irb->mt->bo == bo) {
+ found = brw->draw_aux_buffer_disabled[i] = true;
+  }
+   }
+
+   return found;
+}
+
 /* On Gen9 color buffers may be compressed by the hardware (lossless
  * compression). There are, however, format restrictions and care needs to be
  * taken that the sampler engine is capable for re-interpreting a buffer with
@@ -197,6 +215,10 @@ intel_texture_view_requires_resolve(struct brw_context 
*brw,
   _mesa_get_format_name(intel_tex->_Format),
   _mesa_get_format_name(intel_tex->mt->format));
 
+   if (intel_disable_rb_aux_buffer(brw, intel_tex->mt->bo))
+  perf_debug("Sampling renderbuffer with non-compressible format - "
+ "turning off compression");
+
return true;
 }
 
@@ -220,6 +242,9 @@ intel_update_state(struct gl_context * ctx, GLuint 
new_state)
if (depth_irb)
   intel_renderbuffer_resolve_hiz(brw, depth_irb);
 
+   memset(brw->draw_aux_buffer_disabled, 0,
+  sizeof(brw->draw_aux_buffer_disabled));
+
/* Resolve depth buffer and render cache of each enabled texture. */
int maxEnabledUnit = ctx->Texture._MaxEnabledTexImageUnit;
for (int i = 0; i <= maxEnabledUnit; i++) {
@@ -262,6 +287,13 @@ intel_update_state(struct gl_context * ctx, GLuint 
new_state)
 * surfaces need to be resolved prior to accessing them.
 */
intel_miptree_resolve_color(brw, tex_obj->mt, 0);
+
+   if (intel_miptree_is_lossless_compressed(brw, tex_obj->mt) &&
+   intel_disable_rb_aux_buffer(brw, tex_obj->mt->bo)) {
+  perf_debug("Using renderbuffer as shader image - turning "
+ "off lossless compression");
+   }
+
brw_render_cache_set_check_flush(brw, tex_obj->mt->bo);
 }
  }
diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 7780ce5..2c55b5e 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1333,6 +1333,16 @@ struct brw_context
 
struct brw_fast_clear_state *fast_clear_state;
 
+   /* Array of flags telling if auxiliary buffer is disabled for corresponding
+* renderbuffer. If draw_aux_buffer_disabled[i] is set then use of
+* auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is
+* disabled.
+* This is needed in case the same underlying buffer is also configured
+* to be sampled but with a format that the sampling engine can't treat
+* compressed or fast cleared.
+*/
+   bool draw_aux_buffer_disabled[MAX_DRAW_BUFFERS];
+
__DRIcontext *driContext;
struct intel_screen *intelScreen;
 };
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 0683b76..62a4eb8 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -56,6 +56,7 @@
 
 enum {
INTEL_RENDERBUFFER_LAYERED = 1 << 0,
+   INTEL_AUX_BUFFER_DISABLED = 1 << 1,
 };
 
 struct surface_state_info {
@@ -194,6 +195,10 @@ brw_update_renderbuffer_surface(struct brw_context *brw,
struct 

Mesa (master): i965/rbc: Allocate mcs directly

[Topi Pohjolainen]

Module: Mesa
Branch: master
Commit: 39712b2a14745861d06ab608ba9a56f1c006addc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=39712b2a14745861d06ab608ba9a56f1c006addc

Author: Topi Pohjolainen 
Date:   Fri Aug 26 09:26:15 2016 +0300

i965/rbc: Allocate mcs directly

such as we do for compressed msaa. In case of non-compressed simgle
sampled buffers the allocation of mcs is deferred until there is
actually a clear operation that needs the mcs.
In case of render buffer compression the mcs buffer always needed
and there is no real reason to defer the allocation. By doing it
directly allows to drop quite a bit unnecessary complexity.

Patch leaves brw_predraw_set_aux_buffers() a no-op. Subsequent
patches will re-use it and it seemed cleaner to leave it instead
of removing and re-introducing.

Signed-off-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_blorp.c | 10 ++--
 src/mesa/drivers/dri/i965/brw_draw.c  |  4 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 68 +++
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  7 +--
 4 files changed, 26 insertions(+), 63 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index b0fbb64..fdaf429 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -287,8 +287,6 @@ brw_blorp_blit_miptrees(struct brw_context *brw,
intel_miptree_slice_resolve_depth(brw, src_mt, src_level, src_layer);
intel_miptree_slice_resolve_depth(brw, dst_mt, dst_level, dst_layer);
 
-   intel_miptree_prepare_mcs(brw, dst_mt);
-
DBG("%s from %dx %s mt %p %d %d (%f,%f) (%f,%f)"
"to %dx %s mt %p %d %d (%f,%f) (%f,%f) (flip %d,%d)\n",
__func__,
@@ -689,6 +687,9 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
!brw_is_color_fast_clear_compatible(brw, irb->mt, 
>Color.ClearColor))
   can_fast_clear = false;
 
+   const bool is_lossless_compressed = intel_miptree_is_lossless_compressed(
+  brw, irb->mt);
+
if (can_fast_clear) {
   /* Record the clear color in the miptree so that it will be
* programmed in SURFACE_STATE by later rendering and resolve
@@ -708,7 +709,8 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
* it now.
*/
   if (!irb->mt->mcs_mt) {
- if (!intel_miptree_alloc_non_msrt_mcs(brw, irb->mt)) {
+ assert(!is_lossless_compressed);
+ if (!intel_miptree_alloc_non_msrt_mcs(brw, irb->mt, false)) {
 /* MCS allocation failed--probably this will only happen in
  * out-of-memory conditions.  But in any case, try to recover
  * by falling back to a non-blorp clear technique.
@@ -757,7 +759,7 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
   clear_color, color_write_disable);
   blorp_batch_finish();
 
-  if (intel_miptree_is_lossless_compressed(brw, irb->mt)) {
+  if (is_lossless_compressed) {
  /* Compressed buffers can be cleared also using normal rep-clear. In
   * such case they behave such as if they were drawn using normal 3D
   * render pipeline, and we simply mark the mcs as dirty.
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 9b1e18c..cab67c9 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -409,8 +409,8 @@ brw_predraw_set_aux_buffers(struct brw_context *brw)
   struct intel_renderbuffer *irb =
  intel_renderbuffer(fb->_ColorDrawBuffers[i]);
 
-  if (irb) {
- intel_miptree_prepare_mcs(brw, irb->mt);
+  if (!irb) {
+ continue;
   }
}
 }
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 7b97183..427657c 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -789,6 +789,20 @@ intel_miptree_create(struct brw_context *brw,
intel_miptree_supports_non_msrt_fast_clear(brw, mt)) {
   mt->fast_clear_state = INTEL_FAST_CLEAR_STATE_RESOLVED;
   assert(brw->gen < 8 || mt->halign == 16 || num_samples <= 1);
+
+  /* On Gen9+ clients are not currently capable of consuming compressed
+   * single-sampled buffers. Disabling compression allows us to skip
+   * resolves.
+   */
+  const bool lossless_compression_disabled = INTEL_DEBUG & DEBUG_NO_RBC;
+  const bool is_lossless_compressed =
+ unlikely(!lossless_compression_disabled) &&
+ brw->gen >= 9 && !mt->is_scanout &&
+ intel_miptree_supports_lossless_compressed(brw, mt);
+
+  if (is_lossless_compressed) {
+ intel_miptree_alloc_non_msrt_mcs(brw, mt, 

Mesa (master): intel/blorp: Add plumbing for setting color clear layer count

[Topi Pohjolainen]

Module: Mesa
Branch: master
Commit: a1c7de09dc2b00cc990903ebee52228315e5d4e5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1c7de09dc2b00cc990903ebee52228315e5d4e5

Author: Topi Pohjolainen 
Date:   Fri Aug 26 18:44:18 2016 +0300

intel/blorp: Add plumbing for setting color clear layer count

Signed-off-by: Topi Pohjolainen 
Reviewed-by: Jason Ekstrand 

---

 src/intel/blorp/blorp.h   |  6 +++---
 src/intel/blorp/blorp_clear.c | 16 +---
 src/mesa/drivers/dri/i965/brw_blorp.c |  6 +++---
 3 files changed, 15 insertions(+), 13 deletions(-)

diff --git a/src/intel/blorp/blorp.h b/src/intel/blorp/blorp.h
index 12f1833..238e7c7 100644
--- a/src/intel/blorp/blorp.h
+++ b/src/intel/blorp/blorp.h
@@ -110,14 +110,14 @@ blorp_blit(struct blorp_batch *batch,
 
 void
 blorp_fast_clear(struct blorp_batch *batch,
- const struct blorp_surf *surf,
- uint32_t level, uint32_t layer, enum isl_format format,
+ const struct blorp_surf *surf, enum isl_format format,
+ uint32_t level, uint32_t start_layer, uint32_t num_layers,
  uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1);
 
 void
 blorp_clear(struct blorp_batch *batch,
 const struct blorp_surf *surf,
-uint32_t level, uint32_t layer,
+uint32_t level, uint32_t start_layer, uint32_t num_layers,
 uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1,
 enum isl_format format, union isl_color_value clear_color,
 bool color_write_disable[4]);
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index 831c8ed..cba4823 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -208,12 +208,13 @@ get_fast_clear_rect(const struct isl_device *dev,
 
 void
 blorp_fast_clear(struct blorp_batch *batch,
- const struct blorp_surf *surf,
- uint32_t level, uint32_t layer, enum isl_format format,
+ const struct blorp_surf *surf, enum isl_format format,
+ uint32_t level, uint32_t start_layer, uint32_t num_layers,
  uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1)
 {
struct blorp_params params;
blorp_params_init();
+   params.num_layers = num_layers;
 
params.x0 = x0;
params.y0 = y0;
@@ -228,8 +229,8 @@ blorp_fast_clear(struct blorp_batch *batch,
 
blorp_params_get_clear_kernel(batch->blorp, , true);
 
-   brw_blorp_surface_info_init(batch->blorp, , surf, level, layer,
-   format, true);
+   brw_blorp_surface_info_init(batch->blorp, , surf, level,
+   start_layer, format, true);
 
batch->blorp->exec(batch, );
 }
@@ -238,13 +239,14 @@ blorp_fast_clear(struct blorp_batch *batch,
 void
 blorp_clear(struct blorp_batch *batch,
 const struct blorp_surf *surf,
-uint32_t level, uint32_t layer,
+uint32_t level, uint32_t start_layer, uint32_t num_layers,
 uint32_t x0, uint32_t y0, uint32_t x1, uint32_t y1,
 enum isl_format format, union isl_color_value clear_color,
 bool color_write_disable[4])
 {
struct blorp_params params;
blorp_params_init();
+   params.num_layers = num_layers;
 
params.x0 = x0;
params.y0 = y0;
@@ -276,8 +278,8 @@ blorp_clear(struct blorp_batch *batch,
blorp_params_get_clear_kernel(batch->blorp, ,
  use_simd16_replicated_data);
 
-   brw_blorp_surface_info_init(batch->blorp, , surf, level, layer,
-   format, true);
+   brw_blorp_surface_info_init(batch->blorp, , surf, level,
+   start_layer, format, true);
 
batch->blorp->exec(batch, );
 }
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index fdaf429..dc2be1e 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -735,9 +735,9 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
 
   struct blorp_batch batch;
   blorp_batch_init(>blorp, , brw);
-  blorp_fast_clear(, , level, layer,
+  blorp_fast_clear(, ,
(enum isl_format)brw->render_target_format[format],
-   x0, y0, x1, y1);
+   level, layer, 1, x0, y0, x1, y1);
   blorp_batch_finish();
 
   /* Now that the fast clear has occurred, put the buffer in
@@ -754,7 +754,7 @@ do_single_blorp_clear(struct brw_context *brw, struct 
gl_framebuffer *fb,
 
   struct blorp_batch batch;
   blorp_batch_init(>blorp, , brw);
-  blorp_clear(, , level, layer, x0, y0, x1, y1,
+  blorp_clear(, , level, layer, 1, x0, y0, x1, y1,
   (enum isl_format)brw->render_target_format[format],
   clear_color,