Mesa (master): gallium/radeon: Initialize pipe_resource::next to NULL
Module: Mesa
Branch: master
Commit: 8d8c440ebf1a41dd235a67f3f1538cf47adec013
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d8c440ebf1a41dd235a67f3f1538cf47adec013
Author: Michel Dänzer
Date: Tue Sep 27 18:17:12 2016 +0900
gallium/radeon: Initialize pipe_resource::next to NULL
Fixes lots of piglit tests crashing due to using uninitialized memory.
Fixes: ecd6fce2611e ("mesa/st: support lowering multi-planar YUV")
Reviewed-by: Nicolai Hähnle
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeon/r600_buffer_common.c | 1 +
src/gallium/drivers/radeon/r600_texture.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c
b/src/gallium/drivers/radeon/r600_buffer_common.c
index 2e8b6f4..cbbcc29 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -511,6 +511,7 @@ r600_alloc_buffer_struct(struct pipe_screen *screen,
rbuffer = MALLOC_STRUCT(r600_resource);
rbuffer->b.b = *templ;
+ rbuffer->b.b.next = NULL;
pipe_reference_init(&rbuffer->b.b.reference, 1);
rbuffer->b.b.screen = screen;
rbuffer->b.vtbl = &r600_buffer_vtbl;
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index b2ed93c..6ad5f85 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1040,6 +1040,7 @@ r600_texture_create_object(struct pipe_screen *screen,
resource = &rtex->resource;
resource->b.b = *base;
+ resource->b.b.next = NULL;
resource->b.vtbl = &r600_texture_vtbl;
pipe_reference_init(&resource->b.b.reference, 1);
resource->b.b.screen = screen;
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Mesa (master): glsl: don' t crash when dumping shaders if some come from cache
Module: Mesa
Branch: master
Commit: 3eb0baeecfed7a2de2b323e1b5d90e2b14dfc803
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3eb0baeecfed7a2de2b323e1b5d90e2b14dfc803
Author: Timothy Arceri
Date: Sun Mar 27 16:25:12 2016 +1100
glsl: don't crash when dumping shaders if some come from cache
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_link.cpp | 14 ++
src/mesa/main/shaderapi.c | 9 +++--
2 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp
b/src/mesa/drivers/dri/i965/brw_link.cpp
index e528411..02151d6 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -183,10 +183,16 @@ process_glsl_ir(struct brw_context *brw,
if (ctx->_Shader->Flags & GLSL_DUMP) {
fprintf(stderr, "\n");
- fprintf(stderr, "GLSL IR for linked %s program %d:\n",
- _mesa_shader_stage_to_string(shader->Stage),
- shader_prog->Name);
- _mesa_print_ir(stderr, shader->ir, NULL);
+ if (shader->ir) {
+ fprintf(stderr, "GLSL IR for linked %s program %d:\n",
+ _mesa_shader_stage_to_string(shader->Stage),
+ shader_prog->Name);
+ _mesa_print_ir(stderr, shader->ir, NULL);
+ } else {
+ fprintf(stderr, "No GLSL IR for linked %s program %d (shader may be "
+ "from cache)\n", _mesa_shader_stage_to_string(shader->Stage),
+ shader_prog->Name);
+ }
fprintf(stderr, "\n");
}
}
diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index 4ebc39f..1af1c3f 100644
--- a/src/mesa/main/shaderapi.c
+++ b/src/mesa/main/shaderapi.c
@@ -1039,8 +1039,13 @@ _mesa_compile_shader(struct gl_context *ctx, struct
gl_shader *sh)
if (ctx->_Shader->Flags & GLSL_DUMP) {
if (sh->CompileStatus) {
-_mesa_log("GLSL IR for shader %d:\n", sh->Name);
-_mesa_print_ir(_mesa_get_log_file(), sh->ir, NULL);
+if (sh->ir) {
+ _mesa_log("GLSL IR for shader %d:\n", sh->Name);
+ _mesa_print_ir(_mesa_get_log_file(), sh->ir, NULL);
+} else {
+ _mesa_log("No GLSL IR for shader %d (shader may be from "
+ "cache)\n", sh->Name);
+}
_mesa_log("\n\n");
} else {
_mesa_log("GLSL shader %d failed to compile.\n", sh->Name);
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Mesa (master): glsl: Add initial functions to implement an on-disk cache
Module: Mesa Branch: master Commit: 87ab26b2ab35a29d446ae66f1795d40c184c0739 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=87ab26b2ab35a29d446ae66f1795d40c184c0739 Author: Timothy Arceri Date: Wed Sep 28 08:55:02 2016 +1000 glsl: Add initial functions to implement an on-disk cache This code provides for an on-disk cache of objects. Objects are stored and retrieved via names that are arbitrary 20-byte sequences, (intended to be SHA-1 hashes of something identifying for the content). The directory used for the cache can be specified by means of environment variables in the following priority order: $MESA_GLSL_CACHE_DIR $XDG_CACHE_HOME/mesa /.cache/mesa By default the cache will be limited to a maximum size of 1GB. The environment variable: $MESA_GLSL_CACHE_MAX_SIZE can be set (at the time of GL context creation) to choose some other size. This variable is a number that can optionally be followed by 'K', 'M', or 'G' to select a size in kilobytes, megabytes, or gigabytes. By default, an unadorned value will be interpreted as gigabytes. The cache will be entirely disabled at runtime if the variable MESA_GLSL_CACHE_DISABLE is set at the time of GL context creation. Many thanks to Kristian Høgsberg for the initial implementation of code that led to this patch. In particular, the idea of using an mmapped file, (indexed by a portion of the SHA-1), for the efficent implementation of cache_has_key was entirely his idea. Kristian also provided some very helpful advice in discussions regarding various race conditions to be avoided in this code. Signed-off-by: Timothy Arceri Reviewed-by: Eric Anholt --- configure.ac | 3 + src/compiler/Makefile.glsl.am| 10 + src/compiler/Makefile.sources| 4 + src/compiler/glsl/cache.c| 710 +++ src/compiler/glsl/cache.h| 172 + src/compiler/glsl/tests/.gitignore | 1 + src/compiler/glsl/tests/cache_test.c | 416 7 files changed, 1316 insertions(+) diff --git a/configure.ac b/configure.ac index b9e6000..c702b53 100644 --- a/configure.ac +++ b/configure.ac @@ -1305,6 +1305,9 @@ if test "x$with_sha1" = "x"; then fi fi AM_CONDITIONAL([ENABLE_SHADER_CACHE], [test x$enable_shader_cache = xyes]) +if test "x$enable_shader_cache" = "xyes"; then + AC_DEFINE([ENABLE_SHADER_CACHE], [1], [Enable shader cache]) +fi case "$host_os" in linux*) diff --git a/src/compiler/Makefile.glsl.am b/src/compiler/Makefile.glsl.am index b8225cb..80dfb73 100644 --- a/src/compiler/Makefile.glsl.am +++ b/src/compiler/Makefile.glsl.am @@ -33,6 +33,7 @@ EXTRA_DIST += glsl/tests glsl/glcpp/tests glsl/README \ TESTS += glsl/glcpp/tests/glcpp-test \ glsl/glcpp/tests/glcpp-test-cr-lf \ glsl/tests/blob-test\ + glsl/tests/cache-test \ glsl/tests/general-ir-test \ glsl/tests/optimization-test\ glsl/tests/sampler-types-test \ @@ -47,6 +48,7 @@ check_PROGRAMS += \ glsl/glcpp/glcpp\ glsl/glsl_test \ glsl/tests/blob-test\ + glsl/tests/cache-test \ glsl/tests/general-ir-test \ glsl/tests/sampler-types-test \ glsl/tests/uniform-initializer-test @@ -58,6 +60,11 @@ glsl_tests_blob_test_SOURCES = \ glsl_tests_blob_test_LDADD = \ glsl/libglsl.la +glsl_tests_cache_test_SOURCES =\ + glsl/tests/cache_test.c +glsl_tests_cache_test_LDADD = \ + glsl/libglsl.la + glsl_tests_general_ir_test_SOURCES = \ glsl/tests/builtin_variable_test.cpp\ glsl/tests/invalidate_locations_test.cpp\ @@ -120,6 +127,9 @@ glsl_libglsl_la_SOURCES = \ $(LIBGLSL_GENERATED_FILES) \ $(LIBGLSL_FILES) +if ENABLE_SHADER_CACHE +glsl_libglsl_la_SOURCES += $(LIBGLSL_SHADER_CACHE_FILES) +endif glsl_libstandalone_la_SOURCES = \ $(GLSL_COMPILER_CXX_FILES) diff --git a/src/compiler/Makefile.sources b/src/compiler/Makefile.sources index f5b4f9c..712b33a 100644 --- a/src/compiler/Makefile.sources +++ b/src/compiler/Makefile.sources @@ -136,6 +136,10 @@ LIBGLSL_FILES = \ glsl/s_expression.cpp \ glsl/s_expression.h +LIBGLSL_SHADER_CACHE_FILES = \ + glsl/cache.c \ + glsl/cache.h + # glsl_compiler GLSL_COMPILER_CXX_FILES = \ diff --git a/src/compiler/glsl/cache.c b/src/compiler/glsl/cache.c new file mode 100644 index 000..64a34f0 --- /dev/null +++
Mesa (master): .gitignore: Ignore src/compiler/spirv2nir
Module: Mesa Branch: master Commit: 44bcf1ffcced04fd7f2b537a922ffa85dd1418e2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=44bcf1ffcced04fd7f2b537a922ffa85dd1418e2 Author: Chad Versace Date: Tue Sep 27 13:22:44 2016 -0700 .gitignore: Ignore src/compiler/spirv2nir --- src/compiler/.gitignore | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/.gitignore b/src/compiler/.gitignore index c0e6299..5d30b4e 100644 --- a/src/compiler/.gitignore +++ b/src/compiler/.gitignore @@ -1,4 +1,5 @@ glsl_compiler +spirv2nir subtest-cr subtest-cr-lf subtest-lf ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl/standalone: Enable GLSL 4.00 through 4.50
Module: Mesa Branch: master Commit: 5f7f7d582b1d6d3696506250743fd3f6be3277b8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f7f7d582b1d6d3696506250743fd3f6be3277b8 Author: Ian Romanick Date: Thu Sep 15 11:16:02 2016 -0700 glsl/standalone: Enable GLSL 4.00 through 4.50 Signed-off-by: Ian Romanick Reviewed-by: Kenneth Graunke --- src/compiler/glsl/standalone.cpp | 12 1 file changed, 12 insertions(+) diff --git a/src/compiler/glsl/standalone.cpp b/src/compiler/glsl/standalone.cpp index a7e6254..6b1c2ce 100644 --- a/src/compiler/glsl/standalone.cpp +++ b/src/compiler/glsl/standalone.cpp @@ -153,6 +153,12 @@ initialize_context(struct gl_context *ctx, gl_api api) break; case 150: case 330: + case 400: + case 410: + case 420: + case 430: + case 440: + case 450: ctx->Const.MaxClipPlanes = 8; ctx->Const.MaxDrawBuffers = 8; ctx->Const.MinProgramTexelOffset = -8; @@ -324,6 +330,12 @@ standalone_compile_shader(const struct standalone_options *_options, case 140: case 150: case 330: + case 400: + case 410: + case 420: + case 430: + case 440: + case 450: glsl_es = false; break; default: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl: Fix cut-and-paste bug in hierarchical visitor ir_expression::accept
Module: Mesa Branch: master Commit: ea6ed2379d43330152273caa87f93ea7a77ec9f7 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea6ed2379d43330152273caa87f93ea7a77ec9f7 Author: Ian Romanick Date: Thu Sep 15 11:11:12 2016 -0700 glsl: Fix cut-and-paste bug in hierarchical visitor ir_expression::accept At this point in the code, s must be visit_continue. If the child returned visit_stop, visit_stop is the only correct thing to return. Found by inspection. Signed-off-by: Ian Romanick Cc: mesa-sta...@lists.freedesktop.org Reviewed-by: Kenneth Graunke --- src/compiler/glsl/ir_hv_accept.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/glsl/ir_hv_accept.cpp b/src/compiler/glsl/ir_hv_accept.cpp index 213992a..5cc6a34 100644 --- a/src/compiler/glsl/ir_hv_accept.cpp +++ b/src/compiler/glsl/ir_hv_accept.cpp @@ -147,7 +147,7 @@ ir_expression::accept(ir_hierarchical_visitor *v) goto done; case visit_stop: -return s; +return visit_stop; } } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl/standalone: Use API_OPENGL_CORE if the GLSL version is >= 1.40
Module: Mesa
Branch: master
Commit: 798d1b8816fed0a88674c6d89d56e478519a5a55
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=798d1b8816fed0a88674c6d89d56e478519a5a55
Author: Ian Romanick
Date: Wed Sep 14 13:51:19 2016 -0700
glsl/standalone: Use API_OPENGL_CORE if the GLSL version is >= 1.40
Otherwise extensions to 1.40 that are only for core profile won't work.
Signed-off-by: Ian Romanick
Reviewed-by: Kenneth Graunke
---
src/compiler/glsl/standalone.cpp | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/compiler/glsl/standalone.cpp b/src/compiler/glsl/standalone.cpp
index d6e6829..a7e6254 100644
--- a/src/compiler/glsl/standalone.cpp
+++ b/src/compiler/glsl/standalone.cpp
@@ -331,7 +331,11 @@ standalone_compile_shader(const struct standalone_options
*_options,
return NULL;
}
- initialize_context(ctx, (glsl_es) ? API_OPENGLES2 : API_OPENGL_COMPAT);
+ if (glsl_es) {
+ initialize_context(ctx, API_OPENGLES2);
+ } else {
+ initialize_context(ctx, options->glsl_version > 130 ? API_OPENGL_CORE :
API_OPENGL_COMPAT);
+ }
struct gl_shader_program *whole_program;
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Mesa (master): glsl: Update function parameter documentation for do_common_optimization
Module: Mesa Branch: master Commit: afd99734db400ad5c0357735f239d45436809b7e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=afd99734db400ad5c0357735f239d45436809b7e Author: Ian Romanick Date: Wed Sep 14 15:14:22 2016 -0700 glsl: Update function parameter documentation for do_common_optimization max_unroll_iterations was moved into options a long, long time ago. Signed-off-by: Ian Romanick Reviewed-by: Kenneth Graunke --- src/compiler/glsl/glsl_parser_extras.cpp | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/src/compiler/glsl/glsl_parser_extras.cpp b/src/compiler/glsl/glsl_parser_extras.cpp index b108afd..5f3474e 100644 --- a/src/compiler/glsl/glsl_parser_extras.cpp +++ b/src/compiler/glsl/glsl_parser_extras.cpp @@ -2012,10 +2012,11 @@ _mesa_glsl_compile_shader(struct gl_context *ctx, struct gl_shader *shader, *of unused uniforms from being removed. *The setting of this flag only matters if *\c linked is \c true. - * \param max_unroll_iterations Maximum number of loop iterations to be - *unrolled. Setting to 0 disables loop - *unrolling. * \param options The driver's preferred shader options. + * \param native_integers Selects optimizations that depend on the + *implementations supporting integers + *natively (as opposed to supporting + *integers in floating point registers). */ bool do_common_optimization(exec_list *ir, bool linked, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl: Add bit_xor builder
Module: Mesa
Branch: master
Commit: 7f64041cee3101c673be6d7bffbb03dab69ccca4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f64041cee3101c673be6d7bffbb03dab69ccca4
Author: Ian Romanick
Date: Tue Sep 6 23:17:51 2016 -0700
glsl: Add bit_xor builder
Signed-off-by: Ian Romanick
Reviewed-by: Kenneth Graunke
---
src/compiler/glsl/ir_builder.cpp | 6 ++
src/compiler/glsl/ir_builder.h | 1 +
2 files changed, 7 insertions(+)
diff --git a/src/compiler/glsl/ir_builder.cpp b/src/compiler/glsl/ir_builder.cpp
index d68647f..f430100 100644
--- a/src/compiler/glsl/ir_builder.cpp
+++ b/src/compiler/glsl/ir_builder.cpp
@@ -417,6 +417,12 @@ bit_or(operand a, operand b)
}
ir_expression*
+bit_xor(operand a, operand b)
+{
+ return expr(ir_binop_bit_xor, a, b);
+}
+
+ir_expression*
lshift(operand a, operand b)
{
return expr(ir_binop_lshift, a, b);
diff --git a/src/compiler/glsl/ir_builder.h b/src/compiler/glsl/ir_builder.h
index b483ebf..231fbfc 100644
--- a/src/compiler/glsl/ir_builder.h
+++ b/src/compiler/glsl/ir_builder.h
@@ -168,6 +168,7 @@ ir_expression *logic_or(operand a, operand b);
ir_expression *bit_not(operand a);
ir_expression *bit_or(operand a, operand b);
ir_expression *bit_and(operand a, operand b);
+ir_expression *bit_xor(operand a, operand b);
ir_expression *lshift(operand a, operand b);
ir_expression *rshift(operand a, operand b);
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Mesa (master): swr: replace gallium->swr format enum conversion
Module: Mesa
Branch: master
Commit: 50842e8a9313400a0d31f5fca2e346b95d12b262
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=50842e8a9313400a0d31f5fca2e346b95d12b262
Author: Tim Rowley
Date: Tue Sep 20 11:15:55 2016 -0500
swr: replace gallium->swr format enum conversion
Replace old string comparison with a mapping table.
Reviewed-by: Bruce Cherniak
---
src/gallium/drivers/swr/swr_screen.cpp | 344 -
1 file changed, 293 insertions(+), 51 deletions(-)
diff --git a/src/gallium/drivers/swr/swr_screen.cpp
b/src/gallium/drivers/swr/swr_screen.cpp
index 2ffb3a7..90fc77e 100644
--- a/src/gallium/drivers/swr/swr_screen.cpp
+++ b/src/gallium/drivers/swr/swr_screen.cpp
@@ -45,6 +45,7 @@ extern "C" {
#include "jit_api.h"
#include
+#include
/* MSVC case instensitive compare */
#if defined(PIPE_CC_MSVC)
@@ -415,60 +416,301 @@ swr_get_paramf(struct pipe_screen *screen, enum
pipe_capf param)
SWR_FORMAT
mesa_to_swr_format(enum pipe_format format)
{
- const struct util_format_description *format_desc =
- util_format_description(format);
- if (!format_desc)
- return (SWR_FORMAT)-1;
-
- // more robust check would be comparing all attributes of the formats
- // luckily format names are mostly standardized
- for (int i = 0; i < NUM_SWR_FORMATS; i++) {
- const SWR_FORMAT_INFO &swr_desc = GetFormatInfo((SWR_FORMAT)i);
-
- if (!strcasecmp(format_desc->short_name, swr_desc.name))
- return (SWR_FORMAT)i;
+ static const std::map mesa2swr = {
+ {PIPE_FORMAT_NONE, (SWR_FORMAT)-1},
+ {PIPE_FORMAT_B8G8R8A8_UNORM, B8G8R8A8_UNORM},
+ {PIPE_FORMAT_B8G8R8X8_UNORM, B8G8R8X8_UNORM},
+ {PIPE_FORMAT_A8R8G8B8_UNORM, (SWR_FORMAT)-1},
+ {PIPE_FORMAT_X8R8G8B8_UNORM, (SWR_FORMAT)-1},
+ {PIPE_FORMAT_B5G5R5A1_UNORM, B5G5R5A1_UNORM},
+ {PIPE_FORMAT_B4G4R4A4_UNORM, B4G4R4A4_UNORM},
+ {PIPE_FORMAT_B5G6R5_UNORM, B5G6R5_UNORM},
+ {PIPE_FORMAT_R10G10B10A2_UNORM, R10G10B10A2_UNORM},
+ {PIPE_FORMAT_L8_UNORM, L8_UNORM},
+ {PIPE_FORMAT_A8_UNORM, A8_UNORM},
+ {PIPE_FORMAT_I8_UNORM, I8_UNORM},
+ {PIPE_FORMAT_L8A8_UNORM, L8A8_UNORM},
+ {PIPE_FORMAT_L16_UNORM, L16_UNORM},
+ {PIPE_FORMAT_UYVY, YCRCB_SWAPUVY},
+ {PIPE_FORMAT_YUYV, (SWR_FORMAT)-1},
+ {PIPE_FORMAT_Z16_UNORM, R16_UNORM}, // z
+ {PIPE_FORMAT_Z32_UNORM, (SWR_FORMAT)-1},
+ {PIPE_FORMAT_Z32_FLOAT, R32_FLOAT}, // z
+ {PIPE_FORMAT_Z24_UNORM_S8_UINT, R24_UNORM_X8_TYPELESS}, // z
+ {PIPE_FORMAT_S8_UINT_Z24_UNORM, (SWR_FORMAT)-1},
+ {PIPE_FORMAT_Z24X8_UNORM,R24_UNORM_X8_TYPELESS}, // z
+ {PIPE_FORMAT_X8Z24_UNORM,(SWR_FORMAT)-1},
+ {PIPE_FORMAT_S8_UINT,(SWR_FORMAT)-1},
+ {PIPE_FORMAT_R64_FLOAT, (SWR_FORMAT)-1},
+ {PIPE_FORMAT_R64G64_FLOAT, (SWR_FORMAT)-1},
+ {PIPE_FORMAT_R64G64B64_FLOAT,(SWR_FORMAT)-1},
+ {PIPE_FORMAT_R64G64B64A64_FLOAT, (SWR_FORMAT)-1},
+ {PIPE_FORMAT_R32_FLOAT, R32_FLOAT},
+ {PIPE_FORMAT_R32G32_FLOAT, R32G32_FLOAT},
+ {PIPE_FORMAT_R32G32B32_FLOAT,R32G32B32_FLOAT},
+ {PIPE_FORMAT_R32G32B32A32_FLOAT, R32G32B32A32_FLOAT},
+ {PIPE_FORMAT_R32_UNORM, (SWR_FORMAT)-1},
+ {PIPE_FORMAT_R32G32_UNORM, (SWR_FORMAT)-1},
+ {PIPE_FORMAT_R32G32B32_UNORM,(SWR_FORMAT)-1},
+ {PIPE_FORMAT_R32G32B32A32_UNORM, (SWR_FORMAT)-1},
+ {PIPE_FORMAT_R32_USCALED,R32_USCALED},
+ {PIPE_FORMAT_R32G32_USCALED, R32G32_USCALED},
+ {PIPE_FORMAT_R32G32B32_USCALED, R32G32B32_USCALED},
+ {PIPE_FORMAT_R32G32B32A32_USCALED, R32G32B32A32_USCALED},
+ {PIPE_FORMAT_R32_SNORM, (SWR_FORMAT)-1},
+ {PIPE_FORMAT_R32G32_SNORM, (SWR_FORMAT)-1},
+ {PIPE_FORMAT_R32G32B32_SNORM,(SWR_FORMAT)-1},
+ {PIPE_FORMAT_R32G32B32A32_SNORM, (SWR_FORMAT)-1},
+ {PIPE_FORMAT_R32_SSCALED,R32_SSCALED},
+ {PIPE_FORMAT_R32G32_SSCALED, R32G32_SSCALED},
+ {PIPE_FORMAT_R32G32B32_SSCALED, R32G32B32_SSCALED},
+ {PIPE_FORMAT_R32G32B32A32_SSCALED, R32G32B32A32_SSCALED},
+ {PIPE_FORMAT_R16_UNORM, R16_UNORM},
+ {PIPE_FORMAT_R16G16_UNORM, R16G16_UNORM},
+ {PIPE_FORMAT_R16G16B16_UNORM,R16G16B16_UNORM},
+ {PIPE_FORMAT_R16G16B16A16_UNORM, R16G16B16A16_UNORM},
+ {PIPE_FORMAT_R16_USCALED,R16_USCALED},
+ {PIPE_FORMAT_R16G16_USCALED, R16G16_USCALED},
+ {PIPE_FORMAT_R16G16B16_USCALED, R16G16B16_USCALED},
+ {PIPE_FORMAT_R16G16B16A16_USCALED, R16G16B16A16_USCALED},
+ {PIPE_FORMAT_R16_S
Mesa (master): configure.ac: add llvm inteljitevents component if enabled
Module: Mesa
Branch: master
Commit: bacdd9ef4c00d49cda4f704eadbbd871bb467735
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bacdd9ef4c00d49cda4f704eadbbd871bb467735
Author: Tim Rowley
Date: Thu Jul 21 18:34:37 2016 -0500
configure.ac: add llvm inteljitevents component if enabled
Needed to successfully link llvmpipe or swr when using shared llvm libs
built with inteljitevents enabled.
v2: Make adding inteljitevents component global rather than just
llvmpipe/swr, since libgallium will have a symbol dependency.
Cc:
Reviewed-by: Emil Velikov
---
configure.ac | 4
1 file changed, 4 insertions(+)
diff --git a/configure.ac b/configure.ac
index 0604ad9..b9e6000 100644
--- a/configure.ac
+++ b/configure.ac
@@ -2196,6 +2196,10 @@ if test "x$enable_gallium_llvm" = xyes; then
LLVM_COMPONENTS="engine bitwriter mcjit mcdisassembler"
+if $LLVM_CONFIG --components | grep -q inteljitevents ; then
+LLVM_COMPONENTS="${LLVM_COMPONENTS} inteljitevents"
+fi
+
if test "x$enable_opencl" = xyes; then
llvm_check_version_for "3" "6" "0" "opencl"
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Mesa (master): winsys/amdgpu: do not synchronize unsynchronized buffers
Module: Mesa
Branch: master
Commit: 5af9eef719cda5e45b69a0cd1fde135df5dd3fbc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5af9eef719cda5e45b69a0cd1fde135df5dd3fbc
Author: Nicolai Hähnle
Date: Wed Sep 7 11:01:17 2016 +0200
winsys/amdgpu: do not synchronize unsynchronized buffers
When a buffer is added to a CS without the SYNCHRONIZED usage flag, we now
no longer add a dependency on the buffer's fence(s).
However, we still need to add a fence to the buffer during flush, so that
cache reclaim works correctly (and in the hypothetical case that the buffer
is later added to a CS _with_ the SYNCHRONIZED flag).
It is now possible that the submissions refererring to a buffer are no longer
linearly ordered, and so we may have to keep multiple fences around. We keep
the fences in a FIFO. It should usually stay quite short (# of contexts * 2,
for gfx + dma rings).
While we're at it, extract amdgpu_add_fence_dependency for a single buffer,
which will make adding the distinction between real buffer and slab cases
easier.
Reviewed-by: Marek Olšák
---
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 73 ++-
src/gallium/winsys/amdgpu/drm/amdgpu_bo.h | 6 ++-
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 84 ---
3 files changed, 118 insertions(+), 45 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 0dbd0fb..37a7ba1 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -73,43 +73,58 @@ static bool amdgpu_bo_wait(struct pb_buffer *_buf, uint64_t
timeout,
}
if (timeout == 0) {
+ unsigned idle_fences;
+ bool buffer_idle;
+
pipe_mutex_lock(ws->bo_fence_lock);
- if (bo->fence) {
- if (amdgpu_fence_wait(bo->fence, 0, false)) {
-/* Release the idle fence to avoid checking it again later. */
-amdgpu_fence_reference(&bo->fence, NULL);
- } else {
-pipe_mutex_unlock(ws->bo_fence_lock);
-return false;
- }
+
+ for (idle_fences = 0; idle_fences < bo->num_fences; ++idle_fences) {
+ if (!amdgpu_fence_wait(bo->fences[idle_fences], 0, false))
+break;
}
+
+ /* Release the idle fences to avoid checking them again later. */
+ for (unsigned i = 0; i < idle_fences; ++i)
+ amdgpu_fence_reference(&bo->fences[i], NULL);
+
+ memmove(&bo->fences[0], &bo->fences[idle_fences],
+ (bo->num_fences - idle_fences) * sizeof(*bo->fences));
+ bo->num_fences -= idle_fences;
+
+ buffer_idle = !bo->num_fences;
pipe_mutex_unlock(ws->bo_fence_lock);
- return true;
+ return buffer_idle;
} else {
- struct pipe_fence_handle *fence = NULL;
- bool fence_idle = false;
bool buffer_idle = true;
- /* Take a reference to the fences, so that we can wait for it
- * without the lock. */
pipe_mutex_lock(ws->bo_fence_lock);
- amdgpu_fence_reference(&fence, bo->fence);
- pipe_mutex_unlock(ws->bo_fence_lock);
+ while (bo->num_fences && buffer_idle) {
+ struct pipe_fence_handle *fence = NULL;
+ bool fence_idle = false;
- /* Now wait for the fence. */
- if (fence) {
+ amdgpu_fence_reference(&fence, bo->fences[0]);
+
+ /* Wait for the fence. */
+ pipe_mutex_unlock(ws->bo_fence_lock);
if (amdgpu_fence_wait(fence, abs_timeout, true))
fence_idle = true;
else
buffer_idle = false;
- }
+ pipe_mutex_lock(ws->bo_fence_lock);
+
+ /* Release an idle fence to avoid checking it again later, keeping in
+ * mind that the fence array may have been modified by other threads.
+ */
+ if (fence_idle && bo->num_fences && bo->fences[0] == fence) {
+amdgpu_fence_reference(&bo->fences[0], NULL);
+memmove(&bo->fences[0], &bo->fences[1],
+(bo->num_fences - 1) * sizeof(*bo->fences));
+bo->num_fences--;
+ }
- /* Release idle fences to avoid checking them again later. */
- pipe_mutex_lock(ws->bo_fence_lock);
- if (fence == bo->fence && fence_idle)
- amdgpu_fence_reference(&bo->fence, NULL);
- amdgpu_fence_reference(&fence, NULL);
+ amdgpu_fence_reference(&fence, NULL);
+ }
pipe_mutex_unlock(ws->bo_fence_lock);
return buffer_idle;
@@ -122,6 +137,16 @@ static enum radeon_bo_domain amdgpu_bo_get_initial_domain(
return ((struct amdgpu_winsys_bo*)buf)->initial_domain;
}
+static void amdgpu_bo_remove_fences(struct amdgpu_winsys_bo *bo)
+{
+ for (unsigned i = 0; i < bo->num_fences; ++i)
+ amdgpu_fence_reference(&bo->fences[i], NULL);
+
+ FREE(bo->fences);
+ bo->num_fences = 0;
+ bo->max_fences = 0;
+}
+
void amdgpu_bo_destroy(struct pb_buffer *_buf)
{
struct amdgpu_winsys_bo *bo = amdgp
Mesa (master): winsys/radeon: add fine-grained fences for slab buffers
Module: Mesa
Branch: master
Commit: a1e391e39df2b1d8169e773a30153167ab8e13e8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1e391e39df2b1d8169e773a30153167ab8e13e8
Author: Nicolai Hähnle
Date: Mon Sep 12 11:46:12 2016 +0200
winsys/radeon: add fine-grained fences for slab buffers
Note the logic for adding fences is somewhat different than for amdgpu,
because radeon has no scheduler and we therefore have no guarantee about
the order in which submissions from multiple threads are processed.
(Ironically, this is only an issue when "multi-threaded submission" is
disabled, because "multi-threaded submission" actually means that all
submissions happen from a single thread that happens to be separate from
the application's threads. If we only supported "multi-threaded
submission", the fence handling could be simplified by adding the fences
in that thread where everything is serialized.)
Reviewed-by: Marek Olšák
---
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 55 ++-
src/gallium/winsys/radeon/drm/radeon_drm_bo.h | 4 ++
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 86 ---
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 2 +
src/gallium/winsys/radeon/drm/radeon_drm_winsys.h | 1 +
5 files changed, 137 insertions(+), 11 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 3f58b00..f9cf2e0 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -53,7 +53,7 @@ struct radeon_bo_va_hole {
uint64_t size;
};
-static bool radeon_bo_is_busy(struct radeon_bo *bo)
+static bool radeon_real_bo_is_busy(struct radeon_bo *bo)
{
struct drm_radeon_gem_busy args = {0};
@@ -62,7 +62,31 @@ static bool radeon_bo_is_busy(struct radeon_bo *bo)
&args, sizeof(args)) != 0;
}
-static void radeon_bo_wait_idle(struct radeon_bo *bo)
+static bool radeon_bo_is_busy(struct radeon_bo *bo)
+{
+unsigned num_idle;
+bool busy = false;
+
+if (bo->handle)
+return radeon_real_bo_is_busy(bo);
+
+pipe_mutex_lock(bo->rws->bo_fence_lock);
+for (num_idle = 0; num_idle < bo->u.slab.num_fences; ++num_idle) {
+if (radeon_real_bo_is_busy(bo->u.slab.fences[num_idle])) {
+busy = true;
+break;
+}
+radeon_bo_reference(&bo->u.slab.fences[num_idle], NULL);
+}
+memmove(&bo->u.slab.fences[0], &bo->u.slab.fences[num_idle],
+(bo->u.slab.num_fences - num_idle) * sizeof(bo->u.slab.fences[0]));
+bo->u.slab.num_fences -= num_idle;
+pipe_mutex_unlock(bo->rws->bo_fence_lock);
+
+return busy;
+}
+
+static void radeon_real_bo_wait_idle(struct radeon_bo *bo)
{
struct drm_radeon_gem_wait_idle args = {0};
@@ -71,6 +95,33 @@ static void radeon_bo_wait_idle(struct radeon_bo *bo)
&args, sizeof(args)) == -EBUSY);
}
+static void radeon_bo_wait_idle(struct radeon_bo *bo)
+{
+if (bo->handle) {
+radeon_real_bo_wait_idle(bo);
+} else {
+pipe_mutex_lock(bo->rws->bo_fence_lock);
+while (bo->u.slab.num_fences) {
+struct radeon_bo *fence = NULL;
+radeon_bo_reference(&fence, bo->u.slab.fences[0]);
+pipe_mutex_unlock(bo->rws->bo_fence_lock);
+
+/* Wait without holding the fence lock. */
+radeon_real_bo_wait_idle(fence);
+
+pipe_mutex_lock(bo->rws->bo_fence_lock);
+if (bo->u.slab.num_fences && fence == bo->u.slab.fences[0]) {
+radeon_bo_reference(&bo->u.slab.fences[0], NULL);
+memmove(&bo->u.slab.fences[0], &bo->u.slab.fences[1],
+(bo->u.slab.num_fences - 1) *
sizeof(bo->u.slab.fences[0]));
+bo->u.slab.num_fences--;
+}
+radeon_bo_reference(&fence, NULL);
+}
+pipe_mutex_unlock(bo->rws->bo_fence_lock);
+}
+}
+
static bool radeon_bo_wait(struct pb_buffer *_buf, uint64_t timeout,
enum radeon_bo_usage usage)
{
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.h
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.h
index 8e35a38..8f767fd 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.h
@@ -50,6 +50,10 @@ struct radeon_bo {
struct {
struct pb_slab_entry entry;
struct radeon_bo *real;
+
+unsigned num_fences;
+unsigned max_fences;
+struct radeon_bo **fences;
} slab;
} u;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index 9fbd378..79c09e2 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -471,6 +471,8 @@ void radeon_drm_cs_emit_ioctl_oneshot(void *job, int
thread_inde
Mesa (master): winsys/radeon: separate adding a buffer from updating its reloc data
Module: Mesa
Branch: master
Commit: cbb9c2f170e364054c644e013277ff95a6ad2f0a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cbb9c2f170e364054c644e013277ff95a6ad2f0a
Author: Nicolai Hähnle
Date: Fri Sep 9 18:30:40 2016 +0200
winsys/radeon: separate adding a buffer from updating its reloc data
Reviewed-by: Marek Olšák
---
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 52 +--
1 file changed, 17 insertions(+), 35 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index a3b03be..20f90cf 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -189,19 +189,6 @@ radeon_drm_cs_create(struct radeon_winsys_ctx *ctx,
return &cs->base;
}
-static inline void update_reloc(struct drm_radeon_cs_reloc *reloc,
-enum radeon_bo_domain rd,
-enum radeon_bo_domain wd,
-unsigned priority,
-enum radeon_bo_domain *added_domains)
-{
-*added_domains = (rd | wd) & ~(reloc->read_domains | reloc->write_domain);
-
-reloc->read_domains |= rd;
-reloc->write_domain |= wd;
-reloc->flags = MAX2(reloc->flags, priority);
-}
-
int radeon_lookup_buffer(struct radeon_cs_context *csc, struct radeon_bo *bo)
{
unsigned hash = bo->handle & (ARRAY_SIZE(csc->reloc_indices_hashlist)-1);
@@ -230,30 +217,17 @@ int radeon_lookup_buffer(struct radeon_cs_context *csc,
struct radeon_bo *bo)
return -1;
}
-static unsigned radeon_add_buffer(struct radeon_drm_cs *cs,
- struct radeon_bo *bo,
- enum radeon_bo_usage usage,
- enum radeon_bo_domain domains,
- unsigned priority,
- enum radeon_bo_domain *added_domains)
+static unsigned radeon_lookup_or_add_buffer(struct radeon_drm_cs *cs,
+struct radeon_bo *bo)
{
struct radeon_cs_context *csc = cs->csc;
struct drm_radeon_cs_reloc *reloc;
unsigned hash = bo->handle & (ARRAY_SIZE(csc->reloc_indices_hashlist)-1);
-enum radeon_bo_domain rd = usage & RADEON_USAGE_READ ? domains : 0;
-enum radeon_bo_domain wd = usage & RADEON_USAGE_WRITE ? domains : 0;
int i = -1;
-assert(priority < 64);
-*added_domains = 0;
-
i = radeon_lookup_buffer(csc, bo);
if (i >= 0) {
-reloc = &csc->relocs[i];
-update_reloc(reloc, rd, wd, priority / 4, added_domains);
-csc->relocs_bo[i].priority_usage |= 1llu << priority;
-
/* For async DMA, every add_buffer call must add a buffer to the list
* no matter how many duplicates there are. This is due to the fact
* the DMA CS checker doesn't use NOP packets for offset patching,
@@ -285,20 +259,19 @@ static unsigned radeon_add_buffer(struct radeon_drm_cs
*cs,
/* Initialize the new relocation. */
csc->relocs_bo[csc->num_relocs].bo = NULL;
-csc->relocs_bo[csc->num_relocs].priority_usage = 1llu << priority;
+csc->relocs_bo[csc->num_relocs].priority_usage = 0;
radeon_bo_reference(&csc->relocs_bo[csc->num_relocs].bo, bo);
p_atomic_inc(&bo->num_cs_references);
reloc = &csc->relocs[csc->num_relocs];
reloc->handle = bo->handle;
-reloc->read_domains = rd;
-reloc->write_domain = wd;
-reloc->flags = priority / 4;
+reloc->read_domains = 0;
+reloc->write_domain = 0;
+reloc->flags = 0;
csc->reloc_indices_hashlist[hash] = csc->num_relocs;
csc->chunks[1].length_dw += RELOC_DWORDS;
-*added_domains = rd | wd;
return csc->num_relocs++;
}
@@ -311,8 +284,17 @@ static unsigned radeon_drm_cs_add_buffer(struct
radeon_winsys_cs *rcs,
struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
struct radeon_bo *bo = (struct radeon_bo*)buf;
enum radeon_bo_domain added_domains;
-unsigned index = radeon_add_buffer(cs, bo, usage, domains, priority,
- &added_domains);
+enum radeon_bo_domain rd = usage & RADEON_USAGE_READ ? domains : 0;
+enum radeon_bo_domain wd = usage & RADEON_USAGE_WRITE ? domains : 0;
+struct drm_radeon_cs_reloc *reloc;
+unsigned index = radeon_lookup_or_add_buffer(cs, bo);
+
+reloc = &cs->csc->relocs[index];
+added_domains = (rd | wd) & ~(reloc->read_domains | reloc->write_domain);
+reloc->read_domains |= rd;
+reloc->write_domain |= wd;
+reloc->flags = MAX2(reloc->flags, priority);
+cs->csc->relocs_bo[index].priority_usage |= 1llu << priority;
if (added_domains & RADEON_DOMAIN_VRAM)
cs->base.used_vram += bo->base.size;
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Mesa (master): gallium/pipebuffer: add pb_slab utility
Module: Mesa
Branch: master
Commit: 84f156c0cbf0deb0f51163dc3fd6b09a62270c50
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=84f156c0cbf0deb0f51163dc3fd6b09a62270c50
Author: Nicolai Hähnle
Date: Tue Sep 6 14:43:00 2016 +0200
gallium/pipebuffer: add pb_slab utility
This is a simple framework for slab allocation from buffers that fits into
the buffer management scheme of the radeon and amdgpu winsyses where bufmgrs
aren't used.
The utility knows about different sized allocations and explicitly manages
reclaim of allocations that have pending fences. It manages all the free lists
but does not actually touch buffer objects directly, relying on callbacks for
that.
Reviewed-by: Marek Olšák
---
src/gallium/auxiliary/Makefile.sources | 2 +
src/gallium/auxiliary/pipebuffer/pb_slab.c | 252 +
src/gallium/auxiliary/pipebuffer/pb_slab.h | 155 ++
3 files changed, 409 insertions(+)
diff --git a/src/gallium/auxiliary/Makefile.sources
b/src/gallium/auxiliary/Makefile.sources
index f8954c9..ed9eaa8 100644
--- a/src/gallium/auxiliary/Makefile.sources
+++ b/src/gallium/auxiliary/Makefile.sources
@@ -95,6 +95,8 @@ C_SOURCES := \
pipebuffer/pb_bufmgr_slab.c \
pipebuffer/pb_cache.c \
pipebuffer/pb_cache.h \
+ pipebuffer/pb_slab.c \
+ pipebuffer/pb_slab.h \
pipebuffer/pb_validate.c \
pipebuffer/pb_validate.h \
postprocess/filters.h \
diff --git a/src/gallium/auxiliary/pipebuffer/pb_slab.c
b/src/gallium/auxiliary/pipebuffer/pb_slab.c
new file mode 100644
index 000..79529df
--- /dev/null
+++ b/src/gallium/auxiliary/pipebuffer/pb_slab.c
@@ -0,0 +1,252 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
+ * AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#include "pb_slab.h"
+
+#include "util/u_math.h"
+#include "util/u_memory.h"
+
+/* All slab allocations from the same heap and with the same size belong
+ * to the same group.
+ */
+struct pb_slab_group
+{
+ /* Slabs with allocation candidates. Typically, slabs in this list should
+* have some free entries.
+*
+* However, when the head becomes full we purposefully keep it around
+* until the next allocation attempt, at which time we try a reclaim.
+* The intention is to keep serving allocations from the same slab as long
+* as possible for better locality.
+*
+* Due to a race in new slab allocation, additional slabs in this list
+* can be fully allocated as well.
+*/
+ struct list_head slabs;
+};
+
+
+static void
+pb_slab_reclaim(struct pb_slabs *slabs, struct pb_slab_entry *entry)
+{
+ struct pb_slab *slab = entry->slab;
+
+ LIST_DEL(&entry->head); /* remove from reclaim list */
+ LIST_ADD(&entry->head, &slab->free);
+ slab->num_free++;
+
+ /* Add slab to the group's list if it isn't already linked. */
+ if (!slab->head.next) {
+ struct pb_slab_group *group = &slabs->groups[entry->group_index];
+ LIST_ADDTAIL(&slab->head, &group->slabs);
+ }
+
+ if (slab->num_free >= slab->num_entries) {
+ LIST_DEL(&slab->head);
+ slabs->slab_free(slabs->priv, slab);
+ }
+}
+
+static void
+pb_slabs_reclaim_locked(struct pb_slabs *slabs)
+{
+ while (!LIST_IS_EMPTY(&slabs->reclaim)) {
+ struct pb_slab_entry *entry =
+ LIST_ENTRY(struct pb_slab_entry, slabs->reclaim.next, head);
+
+ if (!slabs->can_reclaim(slabs->priv, entry))
+ break;
+
+ pb_slab_reclaim(slabs, entry);
+ }
+}
+
+/* Allocate a slab entry of the given size from the given heap.
+ *
+ * This will try to re-use entries that have previously been freed. However,
+ * if no entries are free (or all free entries are still "in flight" as
+ * determined by the can_reclaim fallback function), a new slab will be
+ * requested via the slab_alloc callback.
+ *
+ * Note tha
Mesa (master): gallium/radeon/winsyses: reduce the number of pb_cache buckets
Module: Mesa Branch: master Commit: 4421c0fb0dc7a51c3d639c452ad8a5d55a99cec1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4421c0fb0dc7a51c3d639c452ad8a5d55a99cec1 Author: Nicolai Hähnle Date: Mon Sep 12 16:27:41 2016 +0200 gallium/radeon/winsyses: reduce the number of pb_cache buckets Small buffers are now handled via the slabs code, so separate buckets in pb_cache have become redundant. Reviewed-by: Marek Olšák --- src/gallium/auxiliary/pipebuffer/pb_cache.h | 2 +- src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 6 ++ src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 6 ++ 3 files changed, 5 insertions(+), 9 deletions(-) diff --git a/src/gallium/auxiliary/pipebuffer/pb_cache.h b/src/gallium/auxiliary/pipebuffer/pb_cache.h index aa83cc8..7000fcd 100644 --- a/src/gallium/auxiliary/pipebuffer/pb_cache.h +++ b/src/gallium/auxiliary/pipebuffer/pb_cache.h @@ -50,7 +50,7 @@ struct pb_cache /* The cache is divided into buckets for minimizing cache misses. * The driver controls which buffer goes into which bucket. */ - struct list_head buckets[8]; + struct list_head buckets[4]; pipe_mutex mutex; uint64_t cache_size; diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c index c13dc2b..e8d2c00 100644 --- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c +++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c @@ -741,12 +741,10 @@ no_slab: /* Determine the pb_cache bucket for minimizing pb_cache misses. */ pb_cache_bucket = 0; - if (size <= 4096) /* small buffers */ - pb_cache_bucket += 1; if (domain & RADEON_DOMAIN_VRAM) /* VRAM or VRAM+GTT */ - pb_cache_bucket += 2; + pb_cache_bucket += 1; if (flags == RADEON_FLAG_GTT_WC) /* WC */ - pb_cache_bucket += 4; + pb_cache_bucket += 2; assert(pb_cache_bucket < ARRAY_SIZE(ws->bo_cache.buckets)); /* Get a buffer from the cache. */ diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c index 3af01f8..5818006 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c @@ -1014,12 +1014,10 @@ no_slab: /* Determine the pb_cache bucket for minimizing pb_cache misses. */ pb_cache_bucket = 0; -if (size <= 4096) /* small buffers */ - pb_cache_bucket += 1; if (domain & RADEON_DOMAIN_VRAM) /* VRAM or VRAM+GTT */ - pb_cache_bucket += 2; + pb_cache_bucket += 1; if (flags == RADEON_FLAG_GTT_WC) /* WC */ - pb_cache_bucket += 4; + pb_cache_bucket += 2; assert(pb_cache_bucket < ARRAY_SIZE(ws->bo_cache.buckets)); bo = radeon_bo(pb_cache_reclaim_buffer(&ws->bo_cache, size, alignment, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): winsys/amdgpu: enable buffer allocation from slabs
Module: Mesa
Branch: master
Commit: ffa1c669ddb48c25bab3457b8b2bfcd255acc674
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ffa1c669ddb48c25bab3457b8b2bfcd255acc674
Author: Nicolai Hähnle
Date: Wed Sep 7 10:50:59 2016 +0200
winsys/amdgpu: enable buffer allocation from slabs
Reviewed-by: Marek Olšák
---
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 165 ++
src/gallium/winsys/amdgpu/drm/amdgpu_bo.h | 18 +++
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 13 ++
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h | 5 +
4 files changed, 201 insertions(+)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index c367929..c13dc2b 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -38,6 +38,13 @@
#include
#include
+static struct pb_buffer *
+amdgpu_bo_create(struct radeon_winsys *rws,
+ uint64_t size,
+ unsigned alignment,
+ enum radeon_bo_domain domain,
+ enum radeon_bo_flag flags);
+
static bool amdgpu_bo_wait(struct pb_buffer *_buf, uint64_t timeout,
enum radeon_bo_usage usage)
{
@@ -443,6 +450,116 @@ bool amdgpu_bo_can_reclaim(struct pb_buffer *_buf)
return amdgpu_bo_wait(_buf, 0, RADEON_USAGE_READWRITE);
}
+bool amdgpu_bo_can_reclaim_slab(void *priv, struct pb_slab_entry *entry)
+{
+ struct amdgpu_winsys_bo *bo = NULL; /* fix container_of */
+ bo = container_of(entry, bo, u.slab.entry);
+
+ return amdgpu_bo_can_reclaim(&bo->base);
+}
+
+static void amdgpu_bo_slab_destroy(struct pb_buffer *_buf)
+{
+ struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
+
+ assert(!bo->bo);
+
+ pb_slab_free(&bo->ws->bo_slabs, &bo->u.slab.entry);
+}
+
+static const struct pb_vtbl amdgpu_winsys_bo_slab_vtbl = {
+ amdgpu_bo_slab_destroy
+ /* other functions are never called */
+};
+
+struct pb_slab *amdgpu_bo_slab_alloc(void *priv, unsigned heap,
+ unsigned entry_size,
+ unsigned group_index)
+{
+ struct amdgpu_winsys *ws = priv;
+ struct amdgpu_slab *slab = CALLOC_STRUCT(amdgpu_slab);
+ enum radeon_bo_domain domains;
+ enum radeon_bo_flag flags = 0;
+ uint32_t base_id;
+
+ if (!slab)
+ return NULL;
+
+ if (heap & 1)
+ flags |= RADEON_FLAG_GTT_WC;
+ if (heap & 2)
+ flags |= RADEON_FLAG_CPU_ACCESS;
+
+ switch (heap >> 2) {
+ case 0:
+ domains = RADEON_DOMAIN_VRAM;
+ break;
+ default:
+ case 1:
+ domains = RADEON_DOMAIN_VRAM_GTT;
+ break;
+ case 2:
+ domains = RADEON_DOMAIN_GTT;
+ break;
+ }
+
+ slab->buffer = amdgpu_winsys_bo(amdgpu_bo_create(&ws->base,
+64 * 1024, 64 * 1024,
+domains, flags));
+ if (!slab->buffer)
+ goto fail;
+
+ assert(slab->buffer->bo);
+
+ slab->base.num_entries = slab->buffer->base.size / entry_size;
+ slab->base.num_free = slab->base.num_entries;
+ slab->entries = CALLOC(slab->base.num_entries, sizeof(*slab->entries));
+ if (!slab->entries)
+ goto fail_buffer;
+
+ LIST_INITHEAD(&slab->base.free);
+
+ base_id = __sync_fetch_and_add(&ws->next_bo_unique_id,
slab->base.num_entries);
+
+ for (unsigned i = 0; i < slab->base.num_entries; ++i) {
+ struct amdgpu_winsys_bo *bo = &slab->entries[i];
+
+ bo->base.alignment = entry_size;
+ bo->base.usage = slab->buffer->base.usage;
+ bo->base.size = entry_size;
+ bo->base.vtbl = &amdgpu_winsys_bo_slab_vtbl;
+ bo->ws = ws;
+ bo->va = slab->buffer->va + i * entry_size;
+ bo->initial_domain = domains;
+ bo->unique_id = base_id + i;
+ bo->u.slab.entry.slab = &slab->base;
+ bo->u.slab.entry.group_index = group_index;
+ bo->u.slab.real = slab->buffer;
+
+ LIST_ADDTAIL(&bo->u.slab.entry.head, &slab->base.free);
+ }
+
+ return &slab->base;
+
+fail_buffer:
+ amdgpu_winsys_bo_reference(&slab->buffer, NULL);
+fail:
+ FREE(slab);
+ return NULL;
+}
+
+void amdgpu_bo_slab_free(void *priv, struct pb_slab *pslab)
+{
+ struct amdgpu_slab *slab = amdgpu_slab(pslab);
+
+ for (unsigned i = 0; i < slab->base.num_entries; ++i)
+ amdgpu_bo_remove_fences(&slab->entries[i]);
+
+ FREE(slab->entries);
+ amdgpu_winsys_bo_reference(&slab->buffer, NULL);
+ FREE(slab);
+}
+
static unsigned eg_tile_split(unsigned tile_split)
{
switch (tile_split) {
@@ -555,6 +672,53 @@ amdgpu_bo_create(struct radeon_winsys *rws,
struct amdgpu_winsys_bo *bo;
unsigned usage = 0, pb_cache_bucket;
+ /* Sub-allocate small buffers from slabs. */
+ if (!(flags & RADEON_FLAG_HANDLE) &&
+ size <= (1 << AMDGPU_SLAB_MAX_SIZE_LOG2) &&
+ alignment <= MAX2(1 << AMDGPU_SLAB_MIN_SIZE_LOG2,
util_next_power_of_two(size))) {
+ struct pb_slab_entry *entry;
+
Mesa (master): winsys/amdgpu: add slab entry structures to amdgpu_winsys_bo
Module: Mesa
Branch: master
Commit: a987e4377a0a11cf05ffe57c7f8596b82409a5d9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a987e4377a0a11cf05ffe57c7f8596b82409a5d9
Author: Nicolai Hähnle
Date: Wed Sep 7 10:37:42 2016 +0200
winsys/amdgpu: add slab entry structures to amdgpu_winsys_bo
Already adjust amdgpu_bo_map/unmap accordingly.
Reviewed-by: Marek Olšák
---
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 83 ---
src/gallium/winsys/amdgpu/drm/amdgpu_bo.h | 25 +++---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 2 +-
3 files changed, 74 insertions(+), 36 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 37a7ba1..c367929 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -151,13 +151,15 @@ void amdgpu_bo_destroy(struct pb_buffer *_buf)
{
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
+ assert(bo->bo && "must not be called for slab entries");
+
pipe_mutex_lock(bo->ws->global_bo_list_lock);
- LIST_DEL(&bo->global_list_item);
+ LIST_DEL(&bo->u.real.global_list_item);
bo->ws->num_buffers--;
pipe_mutex_unlock(bo->ws->global_bo_list_lock);
amdgpu_bo_va_op(bo->bo, 0, bo->base.size, bo->va, 0, AMDGPU_VA_OP_UNMAP);
- amdgpu_va_range_free(bo->va_handle);
+ amdgpu_va_range_free(bo->u.real.va_handle);
amdgpu_bo_free(bo->bo);
amdgpu_bo_remove_fences(bo);
@@ -167,7 +169,7 @@ void amdgpu_bo_destroy(struct pb_buffer *_buf)
else if (bo->initial_domain & RADEON_DOMAIN_GTT)
bo->ws->allocated_gtt -= align64(bo->base.size,
bo->ws->info.gart_page_size);
- if (bo->map_count >= 1) {
+ if (bo->u.real.map_count >= 1) {
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
bo->ws->mapped_vram -= bo->base.size;
else if (bo->initial_domain & RADEON_DOMAIN_GTT)
@@ -181,8 +183,10 @@ static void amdgpu_bo_destroy_or_cache(struct pb_buffer
*_buf)
{
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
- if (bo->use_reusable_pool)
- pb_cache_add_buffer(&bo->cache_entry);
+ assert(bo->bo); /* slab buffers have a separate vtbl */
+
+ if (bo->u.real.use_reusable_pool)
+ pb_cache_add_buffer(&bo->u.real.cache_entry);
else
amdgpu_bo_destroy(_buf);
}
@@ -192,9 +196,11 @@ static void *amdgpu_bo_map(struct pb_buffer *buf,
enum pipe_transfer_usage usage)
{
struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
+ struct amdgpu_winsys_bo *real;
struct amdgpu_cs *cs = (struct amdgpu_cs*)rcs;
int r;
void *cpu = NULL;
+ uint64_t offset = 0;
/* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
if (!(usage & PIPE_TRANSFER_UNSYNCHRONIZED)) {
@@ -272,41 +278,51 @@ static void *amdgpu_bo_map(struct pb_buffer *buf,
/* If the buffer is created from user memory, return the user pointer. */
if (bo->user_ptr)
- return bo->user_ptr;
+ return bo->user_ptr;
+
+ if (bo->bo) {
+ real = bo;
+ } else {
+ real = bo->u.slab.real;
+ offset = bo->va - real->va;
+ }
- r = amdgpu_bo_cpu_map(bo->bo, &cpu);
+ r = amdgpu_bo_cpu_map(real->bo, &cpu);
if (r) {
/* Clear the cache and try again. */
- pb_cache_release_all_buffers(&bo->ws->bo_cache);
- r = amdgpu_bo_cpu_map(bo->bo, &cpu);
+ pb_cache_release_all_buffers(&real->ws->bo_cache);
+ r = amdgpu_bo_cpu_map(real->bo, &cpu);
if (r)
return NULL;
}
- if (p_atomic_inc_return(&bo->map_count) == 1) {
- if (bo->initial_domain & RADEON_DOMAIN_VRAM)
- bo->ws->mapped_vram += bo->base.size;
- else if (bo->initial_domain & RADEON_DOMAIN_GTT)
- bo->ws->mapped_gtt += bo->base.size;
+ if (p_atomic_inc_return(&real->u.real.map_count) == 1) {
+ if (real->initial_domain & RADEON_DOMAIN_VRAM)
+ real->ws->mapped_vram += real->base.size;
+ else if (real->initial_domain & RADEON_DOMAIN_GTT)
+ real->ws->mapped_gtt += real->base.size;
}
- return cpu;
+ return (uint8_t*)cpu + offset;
}
static void amdgpu_bo_unmap(struct pb_buffer *buf)
{
struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
+ struct amdgpu_winsys_bo *real;
if (bo->user_ptr)
return;
- if (p_atomic_dec_zero(&bo->map_count)) {
- if (bo->initial_domain & RADEON_DOMAIN_VRAM)
- bo->ws->mapped_vram -= bo->base.size;
- else if (bo->initial_domain & RADEON_DOMAIN_GTT)
- bo->ws->mapped_gtt -= bo->base.size;
+ real = bo->bo ? bo : bo->u.slab.real;
+
+ if (p_atomic_dec_zero(&real->u.real.map_count)) {
+ if (real->initial_domain & RADEON_DOMAIN_VRAM)
+ real->ws->mapped_vram -= real->base.size;
+ else if (real->initial_domain & RADEON_DOMAIN_GTT)
+ real->ws->mapped_gtt -= real->base.size;
}
- amdgpu_bo_cpu_unmap(bo->bo);
+ amdgpu_bo_cpu_unmap(real->bo);
}
sta
Mesa (master): winsys/radeon: add slab buffer list
Module: Mesa
Branch: master
Commit: 0edebde9a48ab609c636050208505885da363593
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0edebde9a48ab609c636050208505885da363593
Author: Nicolai Hähnle
Date: Mon Sep 12 10:52:35 2016 +0200
winsys/radeon: add slab buffer list
Introducing radeon_bo::hash will reduce collisions between "real" buffers
and buffers from slabs.
Reviewed-by: Marek Olšák
---
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 3 +
src/gallium/winsys/radeon/drm/radeon_drm_bo.h | 1 +
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 98 ---
src/gallium/winsys/radeon/drm/radeon_drm_cs.h | 16 +++-
src/gallium/winsys/radeon/drm/radeon_drm_winsys.h | 1 +
5 files changed, 107 insertions(+), 12 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 147a877..3f58b00 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -587,6 +587,7 @@ static struct radeon_bo *radeon_create_bo(struct
radeon_drm_winsys *rws,
bo->handle = args.handle;
bo->va = 0;
bo->initial_domain = initial_domains;
+bo->hash = __sync_fetch_and_add(&rws->next_bo_hash, 1);
pipe_mutex_init(bo->u.real.map_mutex);
pb_cache_init_entry(&rws->bo_cache, &bo->u.real.cache_entry, &bo->base,
pb_cache_bucket);
@@ -864,6 +865,7 @@ static struct pb_buffer *radeon_winsys_bo_from_ptr(struct
radeon_winsys *rws,
bo->user_ptr = pointer;
bo->va = 0;
bo->initial_domain = RADEON_DOMAIN_GTT;
+bo->hash = __sync_fetch_and_add(&ws->next_bo_hash, 1);
pipe_mutex_init(bo->u.real.map_mutex);
util_hash_table_set(ws->bo_handles, (void*)(uintptr_t)bo->handle, bo);
@@ -997,6 +999,7 @@ static struct pb_buffer
*radeon_winsys_bo_from_handle(struct radeon_winsys *rws,
bo->base.vtbl = &radeon_bo_vtbl;
bo->rws = ws;
bo->va = 0;
+bo->hash = __sync_fetch_and_add(&ws->next_bo_hash, 1);
pipe_mutex_init(bo->u.real.map_mutex);
if (bo->flink_name)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.h
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.h
index b9a4a05..8e35a38 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.h
@@ -59,6 +59,7 @@ struct radeon_bo {
uint32_t handle; /* 0 for slab entries */
uint32_t flink_name;
uint64_t va;
+uint32_t hash;
enum radeon_bo_domain initial_domain;
/* how many command streams is this bo referenced in? */
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index 20f90cf..9fbd378 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -129,9 +129,14 @@ static void radeon_cs_context_cleanup(struct
radeon_cs_context *csc)
p_atomic_dec(&csc->relocs_bo[i].bo->num_cs_references);
radeon_bo_reference(&csc->relocs_bo[i].bo, NULL);
}
+for (i = 0; i < csc->num_slab_buffers; ++i) {
+p_atomic_dec(&csc->slab_buffers[i].bo->num_cs_references);
+radeon_bo_reference(&csc->slab_buffers[i].bo, NULL);
+}
csc->num_relocs = 0;
csc->num_validated_relocs = 0;
+csc->num_slab_buffers = 0;
csc->chunks[0].length_dw = 0;
csc->chunks[1].length_dw = 0;
@@ -143,6 +148,7 @@ static void radeon_cs_context_cleanup(struct
radeon_cs_context *csc)
static void radeon_destroy_cs_context(struct radeon_cs_context *csc)
{
radeon_cs_context_cleanup(csc);
+FREE(csc->slab_buffers);
FREE(csc->relocs_bo);
FREE(csc->relocs);
}
@@ -191,16 +197,26 @@ radeon_drm_cs_create(struct radeon_winsys_ctx *ctx,
int radeon_lookup_buffer(struct radeon_cs_context *csc, struct radeon_bo *bo)
{
-unsigned hash = bo->handle & (ARRAY_SIZE(csc->reloc_indices_hashlist)-1);
+unsigned hash = bo->hash & (ARRAY_SIZE(csc->reloc_indices_hashlist)-1);
+struct radeon_bo_item *buffers;
+unsigned num_buffers;
int i = csc->reloc_indices_hashlist[hash];
+if (bo->handle) {
+buffers = csc->relocs_bo;
+num_buffers = csc->num_relocs;
+} else {
+buffers = csc->slab_buffers;
+num_buffers = csc->num_slab_buffers;
+}
+
/* not found or found */
-if (i == -1 || csc->relocs_bo[i].bo == bo)
+if (i == -1 || (i < num_buffers && buffers[i].bo == bo))
return i;
/* Hash collision, look for the BO in the list of relocs linearly. */
-for (i = csc->num_relocs - 1; i >= 0; i--) {
-if (csc->relocs_bo[i].bo == bo) {
+for (i = num_buffers - 1; i >= 0; i--) {
+if (buffers[i].bo == bo) {
/* Put this reloc in the hash list.
* This will prevent additional hash collisions if there are
* several consecutive lookup_buffer calls for the same buffer.
@@ -217,12 +233,12 @@ int radeon_lookup_buffe
Mesa (master): winsys/radeon: enable buffer allocation from slabs
Module: Mesa
Branch: master
Commit: fb827c055cb1bdd2b18d0687c06c56b537d805f3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb827c055cb1bdd2b18d0687c06c56b537d805f3
Author: Nicolai Hähnle
Date: Mon Sep 12 12:19:47 2016 +0200
winsys/radeon: enable buffer allocation from slabs
Only enable for chips with GPUVM, because older driver paths do not take the
required offset into account.
Reviewed-by: Marek Olšák
---
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 170 ++
src/gallium/winsys/radeon/drm/radeon_drm_bo.h | 12 ++
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 24 ++-
src/gallium/winsys/radeon/drm/radeon_drm_winsys.h | 5 +
4 files changed, 209 insertions(+), 2 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index f9cf2e0..3af01f8 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -42,6 +42,13 @@
#include
#include
+static struct pb_buffer *
+radeon_winsys_bo_create(struct radeon_winsys *rws,
+uint64_t size,
+unsigned alignment,
+enum radeon_bo_domain domain,
+enum radeon_bo_flag flags);
+
static inline struct radeon_bo *radeon_bo(struct pb_buffer *bo)
{
return (struct radeon_bo *)bo;
@@ -700,6 +707,120 @@ bool radeon_bo_can_reclaim(struct pb_buffer *_buf)
return radeon_bo_wait(_buf, 0, RADEON_USAGE_READWRITE);
}
+bool radeon_bo_can_reclaim_slab(void *priv, struct pb_slab_entry *entry)
+{
+struct radeon_bo *bo = NULL; /* fix container_of */
+bo = container_of(entry, bo, u.slab.entry);
+
+return radeon_bo_can_reclaim(&bo->base);
+}
+
+static void radeon_bo_slab_destroy(struct pb_buffer *_buf)
+{
+struct radeon_bo *bo = radeon_bo(_buf);
+
+assert(!bo->handle);
+
+pb_slab_free(&bo->rws->bo_slabs, &bo->u.slab.entry);
+}
+
+static const struct pb_vtbl radeon_winsys_bo_slab_vtbl = {
+radeon_bo_slab_destroy
+/* other functions are never called */
+};
+
+struct pb_slab *radeon_bo_slab_alloc(void *priv, unsigned heap,
+ unsigned entry_size,
+ unsigned group_index)
+{
+struct radeon_drm_winsys *ws = priv;
+struct radeon_slab *slab = CALLOC_STRUCT(radeon_slab);
+enum radeon_bo_domain domains;
+enum radeon_bo_flag flags = 0;
+unsigned base_hash;
+
+if (!slab)
+return NULL;
+
+if (heap & 1)
+flags |= RADEON_FLAG_GTT_WC;
+if (heap & 2)
+flags |= RADEON_FLAG_CPU_ACCESS;
+
+switch (heap >> 2) {
+case 0:
+domains = RADEON_DOMAIN_VRAM;
+break;
+default:
+case 1:
+domains = RADEON_DOMAIN_VRAM_GTT;
+break;
+case 2:
+domains = RADEON_DOMAIN_GTT;
+break;
+}
+
+slab->buffer = radeon_bo(radeon_winsys_bo_create(&ws->base,
+ 64 * 1024, 64 * 1024,
+ domains, flags));
+if (!slab->buffer)
+goto fail;
+
+assert(slab->buffer->handle);
+
+slab->base.num_entries = slab->buffer->base.size / entry_size;
+slab->base.num_free = slab->base.num_entries;
+slab->entries = CALLOC(slab->base.num_entries, sizeof(*slab->entries));
+if (!slab->entries)
+goto fail_buffer;
+
+LIST_INITHEAD(&slab->base.free);
+
+base_hash = __sync_fetch_and_add(&ws->next_bo_hash,
slab->base.num_entries);
+
+for (unsigned i = 0; i < slab->base.num_entries; ++i) {
+struct radeon_bo *bo = &slab->entries[i];
+
+bo->base.alignment = entry_size;
+bo->base.usage = slab->buffer->base.usage;
+bo->base.size = entry_size;
+bo->base.vtbl = &radeon_winsys_bo_slab_vtbl;
+bo->rws = ws;
+bo->va = slab->buffer->va + i * entry_size;
+bo->initial_domain = domains;
+bo->hash = base_hash + i;
+bo->u.slab.entry.slab = &slab->base;
+bo->u.slab.entry.group_index = group_index;
+bo->u.slab.real = slab->buffer;
+
+LIST_ADDTAIL(&bo->u.slab.entry.head, &slab->base.free);
+}
+
+return &slab->base;
+
+fail_buffer:
+radeon_bo_reference(&slab->buffer, NULL);
+fail:
+FREE(slab);
+return NULL;
+}
+
+void radeon_bo_slab_free(void *priv, struct pb_slab *pslab)
+{
+struct radeon_slab *slab = (struct radeon_slab *)pslab;
+
+for (unsigned i = 0; i < slab->base.num_entries; ++i) {
+struct radeon_bo *bo = &slab->entries[i];
+for (unsigned j = 0; j < bo->u.slab.num_fences; ++j)
+radeon_bo_reference(&bo->u.slab.fences[j], NULL);
+FREE(bo->u.slab.fences);
+}
+
+FREE(slab->entries);
+radeon_bo_reference(&slab->buffer, NULL);
+FREE(slab);
+}
+
static unsigned eg_tile_split(unsigned tile_split)
{
switch (tile_split) {
@@ -823,6 +944,54
Mesa (master): gallium/u_math: add util_logbase2_ceil
Module: Mesa
Branch: master
Commit: b3ebc229dcd5d1cc882443f9b851890b00cd9dbc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3ebc229dcd5d1cc882443f9b851890b00cd9dbc
Author: Nicolai Hähnle
Date: Tue Sep 6 14:41:51 2016 +0200
gallium/u_math: add util_logbase2_ceil
For finding the exponent of the next power of two.
Reviewed-by: Marek Olšák
---
src/gallium/auxiliary/util/u_math.h | 12
1 file changed, 12 insertions(+)
diff --git a/src/gallium/auxiliary/util/u_math.h
b/src/gallium/auxiliary/util/u_math.h
index a923271..2ab5f03 100644
--- a/src/gallium/auxiliary/util/u_math.h
+++ b/src/gallium/auxiliary/util/u_math.h
@@ -429,6 +429,18 @@ util_logbase2(unsigned n)
#endif
}
+/**
+ * Returns the ceiling of log n base 2, and 0 when n == 0. Equivalently,
+ * returns the smallest x such that n <= 2**x.
+ */
+static inline unsigned
+util_logbase2_ceil(unsigned n)
+{
+ if (n <= 1)
+ return 0;
+
+ return 1 + util_logbase2(n - 1);
+}
/**
* Returns the smallest power of two >= x
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): winsys/radeon: add slab entry structures to radeon_bo
Module: Mesa
Branch: master
Commit: a9e8672585afd4d0332d6b22b391f920c35a9979
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9e8672585afd4d0332d6b22b391f920c35a9979
Author: Nicolai Hähnle
Date: Fri Sep 9 15:21:03 2016 +0200
winsys/radeon: add slab entry structures to radeon_bo
Already adjust the map/unmap logic accordingly.
Reviewed-by: Marek Olšák
---
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 94 ++-
src/gallium/winsys/radeon/drm/radeon_drm_bo.h | 23 +--
2 files changed, 78 insertions(+), 39 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index db92035..147a877 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -269,6 +269,8 @@ void radeon_bo_destroy(struct pb_buffer *_buf)
struct radeon_drm_winsys *rws = bo->rws;
struct drm_gem_close args;
+assert(bo->handle && "must not be called for slab entries");
+
memset(&args, 0, sizeof(args));
pipe_mutex_lock(rws->bo_handles_mutex);
@@ -279,8 +281,8 @@ void radeon_bo_destroy(struct pb_buffer *_buf)
}
pipe_mutex_unlock(rws->bo_handles_mutex);
-if (bo->ptr)
-os_munmap(bo->ptr, bo->base.size);
+if (bo->u.real.ptr)
+os_munmap(bo->u.real.ptr, bo->base.size);
if (rws->info.has_virtual_memory) {
if (rws->va_unmap_working) {
@@ -310,14 +312,14 @@ void radeon_bo_destroy(struct pb_buffer *_buf)
args.handle = bo->handle;
drmIoctl(rws->fd, DRM_IOCTL_GEM_CLOSE, &args);
-pipe_mutex_destroy(bo->map_mutex);
+pipe_mutex_destroy(bo->u.real.map_mutex);
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
rws->allocated_vram -= align(bo->base.size, rws->info.gart_page_size);
else if (bo->initial_domain & RADEON_DOMAIN_GTT)
rws->allocated_gtt -= align(bo->base.size, rws->info.gart_page_size);
-if (bo->map_count >= 1) {
+if (bo->u.real.map_count >= 1) {
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
bo->rws->mapped_vram -= bo->base.size;
else
@@ -331,8 +333,10 @@ static void radeon_bo_destroy_or_cache(struct pb_buffer
*_buf)
{
struct radeon_bo *bo = radeon_bo(_buf);
- if (bo->use_reusable_pool)
- pb_cache_add_buffer(&bo->cache_entry);
+assert(bo->handle && "must not be called for slab entries");
+
+ if (bo->u.real.use_reusable_pool)
+ pb_cache_add_buffer(&bo->u.real.cache_entry);
else
radeon_bo_destroy(_buf);
}
@@ -341,18 +345,26 @@ void *radeon_bo_do_map(struct radeon_bo *bo)
{
struct drm_radeon_gem_mmap args = {0};
void *ptr;
+unsigned offset;
/* If the buffer is created from user memory, return the user pointer. */
if (bo->user_ptr)
return bo->user_ptr;
+if (bo->handle) {
+offset = 0;
+} else {
+offset = bo->va - bo->u.slab.real->va;
+bo = bo->u.slab.real;
+}
+
/* Map the buffer. */
-pipe_mutex_lock(bo->map_mutex);
+pipe_mutex_lock(bo->u.real.map_mutex);
/* Return the pointer if it's already mapped. */
-if (bo->ptr) {
-bo->map_count++;
-pipe_mutex_unlock(bo->map_mutex);
-return bo->ptr;
+if (bo->u.real.ptr) {
+bo->u.real.map_count++;
+pipe_mutex_unlock(bo->u.real.map_mutex);
+return (uint8_t*)bo->u.real.ptr + offset;
}
args.handle = bo->handle;
args.offset = 0;
@@ -361,7 +373,7 @@ void *radeon_bo_do_map(struct radeon_bo *bo)
DRM_RADEON_GEM_MMAP,
&args,
sizeof(args))) {
-pipe_mutex_unlock(bo->map_mutex);
+pipe_mutex_unlock(bo->u.real.map_mutex);
fprintf(stderr, "radeon: gem_mmap failed: %p 0x%08X\n",
bo, bo->handle);
return NULL;
@@ -376,21 +388,21 @@ void *radeon_bo_do_map(struct radeon_bo *bo)
ptr = os_mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED,
bo->rws->fd, args.addr_ptr);
if (ptr == MAP_FAILED) {
-pipe_mutex_unlock(bo->map_mutex);
+pipe_mutex_unlock(bo->u.real.map_mutex);
fprintf(stderr, "radeon: mmap failed, errno: %i\n", errno);
return NULL;
}
}
-bo->ptr = ptr;
-bo->map_count = 1;
+bo->u.real.ptr = ptr;
+bo->u.real.map_count = 1;
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
bo->rws->mapped_vram += bo->base.size;
else
bo->rws->mapped_gtt += bo->base.size;
-pipe_mutex_unlock(bo->map_mutex);
-return bo->ptr;
+pipe_mutex_unlock(bo->u.real.map_mutex);
+return (uint8_t*)bo->u.real.ptr + offset;
}
static void *radeon_bo_map(struct pb_buffer *buf,
@@ -478,27 +490,30 @@ static void radeon_bo_unmap(struct pb_buffer *_buf)
if (bo->user_ptr)
return;
-pipe_mutex_lock(bo->map_mutex);
-if (!bo->ptr) {
-
Mesa (master): gallium/radeon: add RADEON_USAGE_SYNCHRONIZED
Module: Mesa
Branch: master
Commit: e703f71ebdf91938c83f47c898f1da058ce0ac32
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e703f71ebdf91938c83f47c898f1da058ce0ac32
Author: Nicolai Hähnle
Date: Wed Sep 7 10:57:56 2016 +0200
gallium/radeon: add RADEON_USAGE_SYNCHRONIZED
This is really the behavior we want most of the time, but having a
SYNCHRONIZED flag instead of an UNSYNCHRONIZED one has the advantage that
OR'ing different flags together always results in stronger guarantees.
The parent BOs of sub-allocated buffers will be added unsynchronized.
Reviewed-by: Marek Olšák
---
src/gallium/drivers/r300/r300_emit.c | 19 +++
src/gallium/drivers/radeon/r600_cs.h | 6 --
src/gallium/drivers/radeon/radeon_uvd.c| 3 ++-
src/gallium/drivers/radeon/radeon_vce.c| 3 ++-
src/gallium/drivers/radeon/radeon_winsys.h | 7 ++-
5 files changed, 25 insertions(+), 13 deletions(-)
diff --git a/src/gallium/drivers/r300/r300_emit.c
b/src/gallium/drivers/r300/r300_emit.c
index 95971de..671aa62 100644
--- a/src/gallium/drivers/r300/r300_emit.c
+++ b/src/gallium/drivers/r300/r300_emit.c
@@ -1321,7 +1321,7 @@ validate:
tex = r300_resource(fb->cbufs[i]->texture);
assert(tex && tex->buf && "cbuf is marked, but NULL!");
r300->rws->cs_add_buffer(r300->cs, tex->buf,
-RADEON_USAGE_READWRITE,
+RADEON_USAGE_READWRITE |
RADEON_USAGE_SYNCHRONIZED,
r300_surface(fb->cbufs[i])->domain,
tex->b.b.nr_samples > 1 ?
RADEON_PRIO_COLOR_BUFFER_MSAA :
@@ -1332,7 +1332,7 @@ validate:
tex = r300_resource(fb->zsbuf->texture);
assert(tex && tex->buf && "zsbuf is marked, but NULL!");
r300->rws->cs_add_buffer(r300->cs, tex->buf,
-RADEON_USAGE_READWRITE,
+RADEON_USAGE_READWRITE |
RADEON_USAGE_SYNCHRONIZED,
r300_surface(fb->zsbuf)->domain,
tex->b.b.nr_samples > 1 ?
RADEON_PRIO_DEPTH_BUFFER_MSAA :
@@ -1343,7 +1343,7 @@ validate:
if (r300->aa_state.dirty) {
if (aa->dest) {
r300->rws->cs_add_buffer(r300->cs, aa->dest->buf,
-RADEON_USAGE_WRITE,
+RADEON_USAGE_WRITE |
RADEON_USAGE_SYNCHRONIZED,
aa->dest->domain,
RADEON_PRIO_COLOR_BUFFER);
}
@@ -1356,19 +1356,22 @@ validate:
}
tex = r300_resource(texstate->sampler_views[i]->base.texture);
-r300->rws->cs_add_buffer(r300->cs, tex->buf, RADEON_USAGE_READ,
+r300->rws->cs_add_buffer(r300->cs, tex->buf,
+ RADEON_USAGE_READ |
RADEON_USAGE_SYNCHRONIZED,
tex->domain, RADEON_PRIO_SAMPLER_TEXTURE);
}
}
/* ...occlusion query buffer... */
if (r300->query_current)
r300->rws->cs_add_buffer(r300->cs, r300->query_current->buf,
-RADEON_USAGE_WRITE, RADEON_DOMAIN_GTT,
+ RADEON_USAGE_WRITE |
RADEON_USAGE_SYNCHRONIZED,
+ RADEON_DOMAIN_GTT,
RADEON_PRIO_QUERY);
/* ...vertex buffer for SWTCL path... */
if (r300->vbo)
r300->rws->cs_add_buffer(r300->cs, r300->vbo,
-RADEON_USAGE_READ, RADEON_DOMAIN_GTT,
+ RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED,
+ RADEON_DOMAIN_GTT,
RADEON_PRIO_VERTEX_BUFFER);
/* ...vertex buffers for HWTCL path... */
if (do_validate_vertex_buffers && r300->vertex_arrays_dirty) {
@@ -1383,7 +1386,7 @@ validate:
continue;
r300->rws->cs_add_buffer(r300->cs, r300_resource(buf)->buf,
-RADEON_USAGE_READ,
+RADEON_USAGE_READ |
RADEON_USAGE_SYNCHRONIZED,
r300_resource(buf)->domain,
RADEON_PRIO_SAMPLER_BUFFER);
}
@@ -1391,7 +1394,7 @@ validate:
/* ...and index buffer for HWTCL path. */
if (index_buffer)
r300->rws->cs_add_buffer(r300->cs, r300_resource(index_buffer)->buf,
-RADEON_USAGE_READ,
+RADEON_USAGE_READ | RADEON_USAGE_SYNCHRONIZED,
r300_resource(index_buffer)->domain,
RADEON_PRIO_INDEX_BUFFER);
diff --git a/src/gallium/drivers/radeon/r600_cs.h
b/src/gallium/drivers/
Mesa (master): winsys/amdgpu: add fence and buffer list logic for slab allocated buffers
Module: Mesa
Branch: master
Commit: a3832590c60e3016a94bbba79072b2913585a672
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a3832590c60e3016a94bbba79072b2913585a672
Author: Nicolai Hähnle
Date: Thu Sep 8 10:05:55 2016 +0200
winsys/amdgpu: add fence and buffer list logic for slab allocated buffers
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeon/radeon_winsys.h | 3 +
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 168 ++---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 26 +++--
3 files changed, 152 insertions(+), 45 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index cce7928..55f0395 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -641,6 +641,9 @@ struct radeon_winsys {
/**
* Return the buffer list.
*
+ * This is the buffer list as passed to the kernel, i.e. it only contains
+ * the parent buffers of sub-allocated buffers.
+ *
* \param csCommand stream
* \param list Returned buffer list. Set to NULL to query the count only.
* \return The buffer count.
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 6fc47aa..c0e810c 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -267,14 +267,24 @@ int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs,
struct amdgpu_winsys_bo *
{
unsigned hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1);
int i = cs->buffer_indices_hashlist[hash];
+ struct amdgpu_cs_buffer *buffers;
+ int num_buffers;
+
+ if (bo->bo) {
+ buffers = cs->real_buffers;
+ num_buffers = cs->num_real_buffers;
+ } else {
+ buffers = cs->slab_buffers;
+ num_buffers = cs->num_slab_buffers;
+ }
/* not found or found */
- if (i == -1 || cs->buffers[i].bo == bo)
+ if (i < 0 || (i < num_buffers && buffers[i].bo == bo))
return i;
/* Hash collision, look for the BO in the list of buffers linearly. */
- for (i = cs->num_buffers - 1; i >= 0; i--) {
- if (cs->buffers[i].bo == bo) {
+ for (i = num_buffers - 1; i >= 0; i--) {
+ if (buffers[i].bo == bo) {
/* Put this buffer in the hash list.
* This will prevent additional hash collisions if there are
* several consecutive lookup_buffer calls for the same buffer.
@@ -292,7 +302,7 @@ int amdgpu_lookup_buffer(struct amdgpu_cs_context *cs,
struct amdgpu_winsys_bo *
}
static int
-amdgpu_lookup_or_add_buffer(struct amdgpu_cs *acs, struct amdgpu_winsys_bo *bo)
+amdgpu_lookup_or_add_real_buffer(struct amdgpu_cs *acs, struct
amdgpu_winsys_bo *bo)
{
struct amdgpu_cs_context *cs = acs->csc;
struct amdgpu_cs_buffer *buffer;
@@ -303,9 +313,9 @@ amdgpu_lookup_or_add_buffer(struct amdgpu_cs *acs, struct
amdgpu_winsys_bo *bo)
return idx;
/* New buffer, check if the backing array is large enough. */
- if (cs->num_buffers >= cs->max_num_buffers) {
+ if (cs->num_real_buffers >= cs->max_real_buffers) {
unsigned new_max =
- MAX2(cs->max_num_buffers + 16, (unsigned)(cs->max_num_buffers * 1.3));
+ MAX2(cs->max_real_buffers + 16, (unsigned)(cs->max_real_buffers *
1.3));
struct amdgpu_cs_buffer *new_buffers;
amdgpu_bo_handle *new_handles;
uint8_t *new_flags;
@@ -322,28 +332,29 @@ amdgpu_lookup_or_add_buffer(struct amdgpu_cs *acs, struct
amdgpu_winsys_bo *bo)
return -1;
}
- memcpy(new_buffers, cs->buffers, cs->num_buffers * sizeof(*new_buffers));
- memcpy(new_handles, cs->handles, cs->num_buffers * sizeof(*new_handles));
- memcpy(new_flags, cs->flags, cs->num_buffers * sizeof(*new_flags));
+ memcpy(new_buffers, cs->real_buffers, cs->num_real_buffers *
sizeof(*new_buffers));
+ memcpy(new_handles, cs->handles, cs->num_real_buffers *
sizeof(*new_handles));
+ memcpy(new_flags, cs->flags, cs->num_real_buffers * sizeof(*new_flags));
- FREE(cs->buffers);
+ FREE(cs->real_buffers);
FREE(cs->handles);
FREE(cs->flags);
- cs->max_num_buffers = new_max;
- cs->buffers = new_buffers;
+ cs->max_real_buffers = new_max;
+ cs->real_buffers = new_buffers;
cs->handles = new_handles;
cs->flags = new_flags;
}
- idx = cs->num_buffers;
- buffer = &cs->buffers[idx];
+ idx = cs->num_real_buffers;
+ buffer = &cs->real_buffers[idx];
+
memset(buffer, 0, sizeof(*buffer));
amdgpu_winsys_bo_reference(&buffer->bo, bo);
cs->handles[idx] = bo->bo;
cs->flags[idx] = 0;
p_atomic_inc(&bo->num_cs_references);
- cs->num_buffers++;
+ cs->num_real_buffers++;
hash = bo->unique_id & (ARRAY_SIZE(cs->buffer_indices_hashlist)-1);
cs->buffer_indices_hashlist[hash] = idx;
@@ -356,6 +367,55 @@ amdgpu_lookup_or_add_buffer(struct amdgpu_cs *acs, st
Mesa (master): gallium/radeon: add RADEON_FLAG_HANDLE
Module: Mesa
Branch: master
Commit: 6d89a4067627fdf568c6c4e3d9a201fd45d5352b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6d89a4067627fdf568c6c4e3d9a201fd45d5352b
Author: Nicolai Hähnle
Date: Fri Sep 9 11:49:18 2016 +0200
gallium/radeon: add RADEON_FLAG_HANDLE
When passed to winsys->buffer_create, this flag will indicate that we require
a buffer that maps 1:1 with a kernel buffer handle.
This is currently set for all textures, since textures can potentially be
exported to other processes. This is not a huge loss, since the main purpose
of this patch series is to deal with applications that allocate many small
buffers.
A hypothetical application with tons of tiny textures might still benefit
from not setting this flag, but that's not a use case I'm worried about
just now.
Reviewed-by: Marek Olšák
---
src/gallium/drivers/r300/r300_texture.c | 2 +-
src/gallium/drivers/radeon/r600_texture.c | 2 ++
src/gallium/drivers/radeon/radeon_winsys.h| 1 +
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 3 +++
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 3 +++
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 2 +-
6 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r300/r300_texture.c
b/src/gallium/drivers/r300/r300_texture.c
index 5f459e4..fbac07a 100644
--- a/src/gallium/drivers/r300/r300_texture.c
+++ b/src/gallium/drivers/r300/r300_texture.c
@@ -1114,7 +1114,7 @@ r300_texture_create_object(struct r300_screen *rscreen,
/* Create the backing buffer if needed. */
if (!tex->buf) {
tex->buf = rws->buffer_create(rws, tex->tex.size_in_bytes, 2048,
- tex->domain, 0);
+ tex->domain, RADEON_FLAG_HANDLE);
if (!tex->buf) {
goto fail;
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index b02b2dc..b2ed93c 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1117,6 +1117,8 @@ r600_texture_create_object(struct pipe_screen *screen,
r600_init_resource_fields(rscreen, resource, rtex->size,
rtex->surface.bo_alignment);
+ resource->flags |= RADEON_FLAG_HANDLE;
+
if (!r600_alloc_resource(rscreen, resource)) {
FREE(rtex);
return NULL;
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index 809a203..cce7928 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -52,6 +52,7 @@ enum radeon_bo_flag { /* bitfield */
RADEON_FLAG_GTT_WC =(1 << 0),
RADEON_FLAG_CPU_ACCESS =(1 << 1),
RADEON_FLAG_NO_CPU_ACCESS = (1 << 2),
+RADEON_FLAG_HANDLE =(1 << 3), /* the buffer most not be
suballocated */
};
enum radeon_bo_usage { /* bitfield */
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 5b099b0..0dbd0fb 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -508,6 +508,9 @@ amdgpu_bo_create(struct radeon_winsys *rws,
struct amdgpu_winsys_bo *bo;
unsigned usage = 0, pb_cache_bucket;
+ /* This flag is irrelevant for the cache. */
+ flags &= ~RADEON_FLAG_HANDLE;
+
/* Align size to page size. This is the minimum alignment for normal
* BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
* like constant/uniform buffers, can benefit from better and more reuse.
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 5db2061..db92035 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -750,6 +750,9 @@ radeon_winsys_bo_create(struct radeon_winsys *rws,
if (size > UINT_MAX)
return NULL;
+/* This flag is irrelevant for the cache. */
+flags &= ~RADEON_FLAG_HANDLE;
+
/* Align size to page size. This is the minimum alignment for normal
* BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
* like constant/uniform buffers, can benefit from better and more reuse.
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index c4933f0..a3b03be 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -620,7 +620,7 @@ radeon_cs_create_fence(struct radeon_winsys_cs *rcs)
/* Create a fence, which is a dummy BO. */
fence = cs->ws->base.buffer_create(&cs->ws->base, 1, 1,
- RADEON_DOMAIN_GTT, 0);
+ RADEON_DOMAIN_GTT, RADEON_FLAG_HANDLE);
/* Add the fence as a dummy relocation. *
Mesa (master): st/dri: check pipe_screen->resource_get_handle() return value
Module: Mesa Branch: master Commit: aa560e8e6328acd5b8feec1fea54dec06ae21368 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=aa560e8e6328acd5b8feec1fea54dec06ae21368 Author: Nicholas Bishop Date: Thu Sep 22 16:04:13 2016 +0100 st/dri: check pipe_screen->resource_get_handle() return value Change dri2_query_image to check the return value of resource_get_handle and return GL_FALSE if an error occurs. For reference this is an example callstack that should propagate the error back to the user: i915_drm_buffer_get_handle i915_texture_get_handle u_resource_get_handle_vtbl dri2_query_image gbm_dri_bo_get_fd gbm_bo_get_fd Cc: mesa-sta...@lists.freedesktop.org Signed-off-by: Nicholas Bishop Reviewed-by: Eric Engestrom (v1) [Emil Velikov: Split from larger patch, polish coding style, cc stable] Signed-off-by: Emil Velikov --- src/gallium/state_trackers/dri/dri2.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/gallium/state_trackers/dri/dri2.c b/src/gallium/state_trackers/dri/dri2.c index a22e7ee..64d9c3e 100644 --- a/src/gallium/state_trackers/dri/dri2.c +++ b/src/gallium/state_trackers/dri/dri2.c @@ -1055,8 +1055,10 @@ dri2_query_image(__DRIimage *image, int attrib, int *value) return GL_TRUE; case __DRI_IMAGE_ATTRIB_FD: whandle.type= DRM_API_HANDLE_TYPE_FD; - image->texture->screen->resource_get_handle(image->texture->screen, - NULL, image->texture, &whandle, usage); + if (!image->texture->screen->resource_get_handle(image->texture->screen, +NULL, image->texture, &whandle, usage)) + return GL_FALSE; + *value = whandle.handle; return GL_TRUE; case __DRI_IMAGE_ATTRIB_FORMAT: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i915g: add dma-buf support to i915_drm_buffer_get_handle
Module: Mesa
Branch: master
Commit: c060f291c26ac22721a515c78c7a4779f389ff7e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c060f291c26ac22721a515c78c7a4779f389ff7e
Author: Nicholas Bishop
Date: Thu Sep 8 15:55:03 2016 -0400
i915g: add dma-buf support to i915_drm_buffer_get_handle
The implementation of i915_drm_buffer_get_handle now handles
DRM_API_HANDLE_TYPE_FD in the same way that intel_winsys_import_handle
does, by calling drm_intel_bo_gem_create_from_prime.
Tested by successfully running Chrome's ozone_demo [1] with the
ozone-gbm backend on an Intel Pineview M machine. Without this change
it fails while trying to create a DMA-BUF.
[1]
https://chromium.googlesource.com/chromium/src.git/+/master/ui/ozone/demo/ozone_demo.cc
Signed-off-by: Nicholas Bishop
[Emil Velikov: Fix coding style]
Signed-off-by: Emil Velikov
---
src/gallium/winsys/i915/drm/i915_drm_buffer.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/gallium/winsys/i915/drm/i915_drm_buffer.c
b/src/gallium/winsys/i915/drm/i915_drm_buffer.c
index ba454ec..890f7dc 100644
--- a/src/gallium/winsys/i915/drm/i915_drm_buffer.c
+++ b/src/gallium/winsys/i915/drm/i915_drm_buffer.c
@@ -153,6 +153,12 @@ i915_drm_buffer_get_handle(struct i915_winsys *iws,
whandle->handle = buf->flink;
} else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
whandle->handle = buf->bo->handle;
+ } else if (whandle->type == DRM_API_HANDLE_TYPE_FD) {
+ int fd;
+
+ if (drm_intel_bo_gem_export_to_prime(buf->bo, &fd))
+ return FALSE;
+ whandle->handle = fd;
} else {
assert(!"unknown usage");
return FALSE;
___
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Mesa (master): gbm: return appropriate error when queryImage() fails
Module: Mesa Branch: master Commit: 2d05ba2ca0af336ceae3167432d7df9df3366b74 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d05ba2ca0af336ceae3167432d7df9df3366b74 Author: Nicholas Bishop Date: Thu Sep 8 15:55:02 2016 -0400 gbm: return appropriate error when queryImage() fails Change gbm_dri_bo_get_fd to check the return value of queryImage and return -1 (an invalid file descriptor) if an error occurs. Update the comment for gbm_bo_get_fd to return -1, since (apart from the above) we've already return -1 on error. Cc: mesa-sta...@lists.freedesktop.org Signed-off-by: Nicholas Bishop Reviewed-by: Eric Engestrom (v1) [Emil Velikov: Split from larger patch, polish coding style, cc stable] Signed-off-by: Emil Velikov --- src/gbm/backends/dri/gbm_dri.c | 3 ++- src/gbm/main/gbm.c | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/src/gbm/backends/dri/gbm_dri.c b/src/gbm/backends/dri/gbm_dri.c index 0ab67da..f863616 100644 --- a/src/gbm/backends/dri/gbm_dri.c +++ b/src/gbm/backends/dri/gbm_dri.c @@ -591,7 +591,8 @@ gbm_dri_bo_get_fd(struct gbm_bo *_bo) if (bo->image == NULL) return -1; - dri->image->queryImage(bo->image, __DRI_IMAGE_ATTRIB_FD, &fd); + if (!dri->image->queryImage(bo->image, __DRI_IMAGE_ATTRIB_FD, &fd)) + return -1; return fd; } diff --git a/src/gbm/main/gbm.c b/src/gbm/main/gbm.c index 5a8e8b7..b9fb70d 100644 --- a/src/gbm/main/gbm.c +++ b/src/gbm/main/gbm.c @@ -204,7 +204,8 @@ gbm_bo_get_handle(struct gbm_bo *bo) * descriptor. * \param bo The buffer object - * \return Returns a file descriptor referring to the underlying buffer + * \return Returns a file descriptor referring to the underlying buffer or -1 + * if an error occurs. */ GBM_EXPORT int gbm_bo_get_fd(struct gbm_bo *bo) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): st/va: Fix vaSyncSurface with no outstanding operation
Module: Mesa
Branch: master
Commit: a543f231d712dbdfd309ff589766179c5cb32b20
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a543f231d712dbdfd309ff589766179c5cb32b20
Author: Mark Thompson
Date: Mon Sep 26 23:22:31 2016 +0100
st/va: Fix vaSyncSurface with no outstanding operation
Fixes crash if the application doesn't do what the state tracker expects.
Reviewed-by: Christian König
---
src/gallium/state_trackers/va/surface.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/gallium/state_trackers/va/surface.c
b/src/gallium/state_trackers/va/surface.c
index 115db43..173e7d9 100644
--- a/src/gallium/state_trackers/va/surface.c
+++ b/src/gallium/state_trackers/va/surface.c
@@ -111,6 +111,12 @@ vlVaSyncSurface(VADriverContextP ctx, VASurfaceID
render_target)
return VA_STATUS_ERROR_INVALID_SURFACE;
}
+ if (!surf->feedback) {
+ // No outstanding operation: nothing to do.
+ pipe_mutex_unlock(drv->mutex);
+ return VA_STATUS_SUCCESS;
+ }
+
context = handle_table_get(drv->htab, surf->ctx);
if (!context) {
pipe_mutex_unlock(drv->mutex);
@@ -126,6 +132,7 @@ vlVaSyncSurface(VADriverContextP ctx, VASurfaceID
render_target)
if (frame_diff < 2)
context->decoder->flush(context->decoder);
context->decoder->get_feedback(context->decoder, surf->feedback,
&(surf->coded_buf->coded_size));
+ surf->feedback = NULL;
}
pipe_mutex_unlock(drv->mutex);
return VA_STATUS_SUCCESS;
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Mesa (master): st/va Avoid VBR bitrate calculation overflow v2
Module: Mesa Branch: master Commit: a5993022275c20061ac025d9adc26c5f9d02afee URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5993022275c20061ac025d9adc26c5f9d02afee Author: Andy Furniss Date: Mon Sep 26 10:44:35 2016 +0100 st/va Avoid VBR bitrate calculation overflow v2 VBR bitrate calc needs 64 bits at high rates. v2: use float. Signed-off-by: Andy Furniss Reviewed-by: Christian König Cc: mesa-sta...@lists.freedesktop.org --- src/gallium/state_trackers/va/picture.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/state_trackers/va/picture.c b/src/gallium/state_trackers/va/picture.c index 7f3d96d..399667f 100644 --- a/src/gallium/state_trackers/va/picture.c +++ b/src/gallium/state_trackers/va/picture.c @@ -322,7 +322,7 @@ handleVAEncMiscParameterTypeRateControl(vlVaContext *context, VAEncMiscParameter PIPE_H264_ENC_RATE_CONTROL_METHOD_CONSTANT) context->desc.h264enc.rate_ctrl.target_bitrate = rc->bits_per_second; else - context->desc.h264enc.rate_ctrl.target_bitrate = rc->bits_per_second * rc->target_percentage / 100; + context->desc.h264enc.rate_ctrl.target_bitrate = rc->bits_per_second * (rc->target_percentage / 100.0); context->desc.h264enc.rate_ctrl.peak_bitrate = rc->bits_per_second; if (context->desc.h264enc.rate_ctrl.target_bitrate < 200) context->desc.h264enc.rate_ctrl.vbv_buffer_size = MIN2((context->desc.h264enc.rate_ctrl.target_bitrate * 2.75), 200); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl: remove remaining tabs in glsl_parser_extras.h
Module: Mesa
Branch: master
Commit: df920367bf85d3a326da5928a73f35844a4a8c72
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=df920367bf85d3a326da5928a73f35844a4a8c72
Author: Timothy Arceri
Date: Tue Sep 27 12:00:51 2016 +1000
glsl: remove remaining tabs in glsl_parser_extras.h
Reviewed-by: Eric Engestrom
---
src/compiler/glsl/glsl_parser_extras.h | 60 +-
1 file changed, 30 insertions(+), 30 deletions(-)
diff --git a/src/compiler/glsl/glsl_parser_extras.h
b/src/compiler/glsl/glsl_parser_extras.h
index f4050e3..b9c9a1a 100644
--- a/src/compiler/glsl/glsl_parser_extras.h
+++ b/src/compiler/glsl/glsl_parser_extras.h
@@ -69,12 +69,12 @@ typedef struct YYLTYPE {
# define YYLTYPE_IS_TRIVIAL 1
extern void _mesa_glsl_error(YYLTYPE *locp, _mesa_glsl_parse_state *state,
-const char *fmt, ...);
+ const char *fmt, ...);
struct _mesa_glsl_parse_state {
_mesa_glsl_parse_state(struct gl_context *_ctx, gl_shader_stage stage,
- void *mem_ctx);
+ void *mem_ctx);
DECLARE_RALLOC_CXX_OPERATORS(_mesa_glsl_parse_state);
@@ -816,23 +816,23 @@ struct _mesa_glsl_parse_state {
unsigned clip_dist_size, cull_dist_size;
};
-# define YYLLOC_DEFAULT(Current, Rhs, N) \
-do { \
- if (N) \
- { \
- (Current).first_line = YYRHSLOC(Rhs, 1).first_line;\
- (Current).first_column = YYRHSLOC(Rhs, 1).first_column; \
- (Current).last_line= YYRHSLOC(Rhs, N).last_line; \
- (Current).last_column = YYRHSLOC(Rhs, N).last_column; \
- } \
- else\
- { \
- (Current).first_line = (Current).last_line = \
-YYRHSLOC(Rhs, 0).last_line;\
- (Current).first_column = (Current).last_column = \
-YYRHSLOC(Rhs, 0).last_column; \
- } \
- (Current).source = 0; \
+# define YYLLOC_DEFAULT(Current, Rhs, N)\
+do {\
+ if (N) \
+ {\
+ (Current).first_line = YYRHSLOC(Rhs, 1).first_line; \
+ (Current).first_column = YYRHSLOC(Rhs, 1).first_column; \
+ (Current).last_line= YYRHSLOC(Rhs, N).last_line; \
+ (Current).last_column = YYRHSLOC(Rhs, N).last_column;\
+ }\
+ else \
+ {\
+ (Current).first_line = (Current).last_line =\
+ YYRHSLOC(Rhs, 0).last_line;\
+ (Current).first_column = (Current).last_column = \
+ YYRHSLOC(Rhs, 0).last_column; \
+ }\
+ (Current).source = 0;\
} while (0)
/**
@@ -841,11 +841,11 @@ do {
\
* \sa _mesa_glsl_error
*/
extern void _mesa_glsl_warning(const YYLTYPE *locp,
- _mesa_glsl_parse_state *state,
- const char *fmt, ...);
+ _mesa_glsl_parse_state *state,
+ const char *fmt, ...);
extern void _mesa_glsl_lexer_ctor(struct _mesa_glsl_parse_state *state,
- const char *string);
+ const char *string);
extern void _mesa_glsl_lexer_dtor(struct _mesa_glsl_parse_state *state);
@@ -863,9 +863,9 @@ extern int _mesa_glsl_parse(struct _mesa_glsl_parse_state
*);
* \c false is returned.
*/
extern bool _mesa_glsl_process_extension(const char *name, YYLTYPE *name_locp,
-const char *behavior,
-YYLTYPE *behavior_locp,
-_mesa_glsl_parse_state *state);
+ const char *behavior,
+ YYLTYPE *behavior_locp,
+ _mesa_glsl_parse_state *state);
#endif /* __cplusplus */
@@ -880,11 +880,11 @@ extern "C" {
struct glcpp_parser;
typedef void (*glcpp_extension_iterator)(
-
