Mesa (master): mesa: Add linear ETC2/ EAC to the compressed format list with ES3 compat.

2016-11-04 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: 0c17b0b6f089e325de6a3f871c8d799326be4202
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c17b0b6f089e325de6a3f871c8d799326be4202

Author: Kenneth Graunke 
Date:   Thu Nov  3 01:58:03 2016 -0700

mesa: Add linear ETC2/EAC to the compressed format list with ES3 compat.

GL_ARB_ES3_compatibility brings ETC2/EAC formats to desktop GL.

The meaning of the GL compressed format list is pretty vague - it's
supposed to return formats for "general-purpose usage".  (GL 4.2
deprecates the list because of this.)  Basically everyone interprets
this as "linear RGB/RGBA".

ETC2/EAC meets that criteria, so while we shouldn't be required to add
it to the list, there's also little harm in doing so, at least on
platforms with native support.  I doubt anyone is using this list for
much anyway, so even on platforms without native support, it's probably
not a big deal.

Makes the following GL45-CTS.gtf43 tests pass:

* GL3Tests.eac_compression_r11.gl_compressed_r11_eac
* GL3Tests.eac_compression_rg11.gl_compressed_rg11_eac
* GL3Tests.eac_compression_signed_r11.gl_compressed_signed_r11_eac
* GL3Tests.eac_compression_signed_rg11.gl_compressed_signed_rg11_eac
* GL3Tests.etc2_compression_rgb8.gl_compressed_rgb8_etc2
* GL3Tests.etc2_compression_rgb8_pt_alpha1.gl_compressed_rgb8_pt_alpha1_etc2
* GL3Tests.etc2_compression_rgba8.gl_compressed_rgba8_etc2

Signed-off-by: Kenneth Graunke 
Reviewed-by: Eduardo Lima Mitev 

---

 src/mesa/main/texcompress.c | 18 --
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index 9567c5d..15970a7 100644
--- a/src/mesa/main/texcompress.c
+++ b/src/mesa/main/texcompress.c
@@ -358,21 +358,27 @@ _mesa_get_compressed_formats(struct gl_context *ctx, 
GLint *formats)
   }
}
 
-   if (_mesa_is_gles3(ctx)) {
+   if (_mesa_is_gles3(ctx) || ctx->Extensions.ARB_ES3_compatibility) {
   if (formats) {
  formats[n++] = GL_COMPRESSED_RGB8_ETC2;
- formats[n++] = GL_COMPRESSED_SRGB8_ETC2;
  formats[n++] = GL_COMPRESSED_RGBA8_ETC2_EAC;
- formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ETC2_EAC;
  formats[n++] = GL_COMPRESSED_R11_EAC;
  formats[n++] = GL_COMPRESSED_RG11_EAC;
  formats[n++] = GL_COMPRESSED_SIGNED_R11_EAC;
  formats[n++] = GL_COMPRESSED_SIGNED_RG11_EAC;
  formats[n++] = GL_COMPRESSED_RGB8_PUNCHTHROUGH_ALPHA1_ETC2;
- formats[n++] = GL_COMPRESSED_SRGB8_PUNCHTHROUGH_ALPHA1_ETC2;
+  } else {
+ n += 7;
   }
-  else {
- n += 10;
+   }
+
+   if (_mesa_is_gles3(ctx)) {
+  if (formats) {
+ formats[n++] = GL_COMPRESSED_SRGB8_ETC2;
+ formats[n++] = GL_COMPRESSED_SRGB8_ALPHA8_ETC2_EAC;
+ formats[n++] = GL_COMPRESSED_SRGB8_PUNCHTHROUGH_ALPHA1_ETC2;
+  } else {
+ n += 3;
   }
}
 

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Mesa (master): vc4: Use Newton-Raphson on the 1/ W write to fix glmark2 terrain.

2016-11-04 Thread Eric Anholt 
Module: Mesa
Branch: master
Commit: 283d4d18e598793bbff7d9ba5a601bced9b36542
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=283d4d18e598793bbff7d9ba5a601bced9b36542

Author: Eric Anholt 
Date:   Fri Nov  4 13:41:20 2016 -0700

vc4: Use Newton-Raphson on the 1/W write to fix glmark2 terrain.

The 1/W was apparently not accurate enough, and we were getting sparklies
in the distance.  The closed driver also did a N-R step here.

Cc: 

---

 src/gallium/drivers/vc4/vc4_program.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/vc4/vc4_program.c 
b/src/gallium/drivers/vc4/vc4_program.c
index f4be5f4..33cd135 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -1421,7 +1421,7 @@ emit_vert_end(struct vc4_compile *c,
   struct vc4_varying_slot *fs_inputs,
   uint32_t num_fs_inputs)
 {
-struct qreg rcp_w = qir_RCP(c, c->outputs[c->output_position_index + 
3]);
+struct qreg rcp_w = ntq_rcp(c, c->outputs[c->output_position_index + 
3]);
 
 emit_stub_vpm_read(c);
 

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Mesa (master): vc4: Make sure that vertex shader texture2D() calls use LOD 0.

2016-11-04 Thread Eric Anholt 
Module: Mesa
Branch: master
Commit: 70fc3a941abc876f8679a32bc9aa83ff3ca2a129
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=70fc3a941abc876f8679a32bc9aa83ff3ca2a129

Author: Eric Anholt 
Date:   Fri Nov  4 12:04:15 2016 -0700

vc4: Make sure that vertex shader texture2D() calls use LOD 0.

I noticed this while trying to debug glmark2 terrain (which does vertex
shader texturing, but no mipmaps on its textures sampled from the VS).

---

 src/gallium/drivers/vc4/vc4_program.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/src/gallium/drivers/vc4/vc4_program.c 
b/src/gallium/drivers/vc4/vc4_program.c
index 809c96d..f4be5f4 100644
--- a/src/gallium/drivers/vc4/vc4_program.c
+++ b/src/gallium/drivers/vc4/vc4_program.c
@@ -417,6 +417,16 @@ ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
 }
 }
 
+if (c->stage != QSTAGE_FRAG && !is_txl) {
+/* From the GLSL 1.20 spec:
+ *
+ * "If it is mip-mapped and running on the vertex shader,
+ *  then the base texture is used."
+ */
+is_txl = true;
+lod = qir_uniform_ui(c, 0);
+}
+
 if (c->key->tex[unit].force_first_level) {
 lod = qir_uniform(c, QUNIFORM_TEXTURE_FIRST_LEVEL, unit);
 is_txl = true;

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Mesa (master): radeonsi: fix vertex fetches for 2_10_10_10 formats

2016-11-04 Thread Nicolai Hähnle 
Module: Mesa
Branch: master
Commit: 2c875158e2763d57e5dae8892af96a894bdb7dc9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c875158e2763d57e5dae8892af96a894bdb7dc9

Author: Nicolai Hähnle 
Date:   Wed Nov  2 19:07:40 2016 +0100

radeonsi: fix vertex fetches for 2_10_10_10 formats

The hardware always treats the alpha channel as unsigned, so add a shader
workaround. This is rare enough that we'll just build a monolithic vertex
shader.

The SINT case cannot actually happen in OpenGL, but I've included it for
completeness since it's just a mix of the other cases.

Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_shader.c| 54 ++---
 src/gallium/drivers/radeonsi/si_shader.h| 11 +
 src/gallium/drivers/radeonsi/si_state.c | 14 +++
 src/gallium/drivers/radeonsi/si_state.h |  1 +
 src/gallium/drivers/radeonsi/si_state_shaders.c |  4 ++
 5 files changed, 78 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 28a8b1f..b170eb9 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -369,17 +369,16 @@ static LLVMValueRef get_instance_index_for_fetch(
 }
 
 static void declare_input_vs(
-   struct si_shader_context *radeon_bld,
+   struct si_shader_context *ctx,
unsigned input_index,
const struct tgsi_full_declaration *decl,
LLVMValueRef out[4])
 {
-   struct lp_build_context *base = _bld->soa.bld_base.base;
+   struct lp_build_context *base = >soa.bld_base.base;
struct gallivm_state *gallivm = base->gallivm;
-   struct si_shader_context *ctx =
-   si_shader_context(_bld->soa.bld_base);
 
unsigned chan;
+   unsigned fix_fetch;
 
LLVMValueRef t_list_ptr;
LLVMValueRef t_offset;
@@ -399,7 +398,7 @@ static void declare_input_vs(
/* Build the attribute offset */
attribute_offset = lp_build_const_int32(gallivm, 0);
 
-   buffer_index = LLVMGetParam(radeon_bld->main_fn,
+   buffer_index = LLVMGetParam(ctx->main_fn,
ctx->param_vertex_index0 +
input_index);
 
@@ -416,6 +415,45 @@ static void declare_input_vs(
out[chan] = LLVMBuildExtractElement(gallivm->builder,
input, llvm_chan, "");
}
+
+   fix_fetch = (ctx->shader->key.vs.fix_fetch >> (2 * input_index)) & 3;
+   if (fix_fetch) {
+   /* The hardware returns an unsigned value; convert it to a
+* signed one.
+*/
+   LLVMValueRef tmp = out[3];
+   LLVMValueRef c30 = LLVMConstInt(ctx->i32, 30, 0);
+
+   /* First, recover the sign-extended signed integer value. */
+   if (fix_fetch == SI_FIX_FETCH_A2_SSCALED)
+   tmp = LLVMBuildFPToUI(gallivm->builder, tmp, ctx->i32, 
"");
+   else
+   tmp = LLVMBuildBitCast(gallivm->builder, tmp, ctx->i32, 
"");
+
+   /* For the integer-like cases, do a natural sign extension.
+*
+* For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
+* and happen to contain 0, 1, 2, 3 as the two LSBs of the
+* exponent.
+*/
+   tmp = LLVMBuildShl(gallivm->builder, tmp,
+  fix_fetch == SI_FIX_FETCH_A2_SNORM ?
+  LLVMConstInt(ctx->i32, 7, 0) : c30, "");
+   tmp = LLVMBuildAShr(gallivm->builder, tmp, c30, "");
+
+   /* Convert back to the right type. */
+   if (fix_fetch == SI_FIX_FETCH_A2_SNORM) {
+   LLVMValueRef clamp;
+   LLVMValueRef neg_one = LLVMConstReal(ctx->f32, -1.0);
+   tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, 
"");
+   clamp = LLVMBuildFCmp(gallivm->builder, LLVMRealULT, 
tmp, neg_one, "");
+   tmp = LLVMBuildSelect(gallivm->builder, clamp, neg_one, 
tmp, "");
+   } else if (fix_fetch == SI_FIX_FETCH_A2_SSCALED) {
+   tmp = LLVMBuildSIToFP(gallivm->builder, tmp, ctx->f32, 
"");
+   }
+
+   out[3] = tmp;
+   }
 }
 
 static LLVMValueRef get_primitive_id(struct lp_build_tgsi_context *bld_base,
@@ -8102,11 +8140,15 @@ int si_shader_create(struct si_screen *sscreen, 
LLVMTargetMachineRef tm,
 
/* LS, ES, VS are compiled on demand if the main part hasn't been
 * compiled for that stage.
+*
+* Vertex shaders are compiled on demand when a vertex fetch
+* workaround must be applied.
 */
if (!mainp ||
(sel->type == PIPE_SHADER_VERTEX &&

Mesa (master): st/mesa: fix the layer of VDPAU surface samplers

2016-11-04 Thread Nicolai Hähnle 
Module: Mesa
Branch: master
Commit: 322483f71b068b3bbf69e5434e888f3fd3f4589e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=322483f71b068b3bbf69e5434e888f3fd3f4589e

Author: Nicolai Hähnle 
Date:   Thu Nov  3 21:49:40 2016 +0100

st/mesa: fix the layer of VDPAU surface samplers

A (latent) bug in VDPAU interop was exposed by commit
e5cc84dd43be066c1dd418e32f5ad258e31a150a.

Before that commit, the st_vdpau code created samplers with
first_layer == last_layer == 1 that the general texture handling code
would immediately delete and re-create, because the layer does not match
the information in the GL texture object.

This was correct behavior at least in the DMABUF case, because the imported
resource is supposed to have the correct offset already applied.  In the
non-DMABUF case, this was just plain wrong but apparently nobody noticed.

After that commit, the state tracker assumes that an existing sampler is
correct at all times.  Existing samplers are supposed to be deleted when
they may become invalid, and they will be created on-demand.  This meant
that the sampler with first_layer == last_layer == 1 stuck around, leading
to rendering artefacts (on radeonsi), command stream failures (on r600), and
assertions (in debug builds everywhere).

This patch fixes the problem by simply not creating a sampler at all in
st_vdpau_map_surface.  We rely on the generic texture code to do the right
thing, adding the layer_override to make the non-DMABUF case work.

v2: add the layer_override

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98512
Cc: 13.0 
Cc: Christian König 
Cc: Ilia Mirkin 
Reviewed-by: Marek Olšák  (v1)
Reviewed-by: Christian König 

---

 src/mesa/state_tracker/st_sampler_view.c | 15 +++
 src/mesa/state_tracker/st_texture.h  |  9 +
 src/mesa/state_tracker/st_vdpau.c| 20 +++-
 3 files changed, 27 insertions(+), 17 deletions(-)

diff --git a/src/mesa/state_tracker/st_sampler_view.c 
b/src/mesa/state_tracker/st_sampler_view.c
index 9fe0bfe..2b2fa8b 100644
--- a/src/mesa/state_tracker/st_sampler_view.c
+++ b/src/mesa/state_tracker/st_sampler_view.c
@@ -430,8 +430,12 @@ st_create_texture_sampler_view_from_stobj(struct 
st_context *st,
   templ.u.tex.first_level = stObj->base.MinLevel + stObj->base.BaseLevel;
   templ.u.tex.last_level = last_level(stObj);
   assert(templ.u.tex.first_level <= templ.u.tex.last_level);
-  templ.u.tex.first_layer = stObj->base.MinLayer;
-  templ.u.tex.last_layer = last_layer(stObj);
+  if (stObj->layer_override) {
+ templ.u.tex.first_layer = templ.u.tex.last_layer = 
stObj->layer_override;
+  } else {
+ templ.u.tex.first_layer = stObj->base.MinLayer;
+ templ.u.tex.last_layer = last_layer(stObj);
+  }
   assert(templ.u.tex.first_layer <= templ.u.tex.last_layer);
   templ.target = gl_target_to_pipe(stObj->base.Target);
}
@@ -478,8 +482,11 @@ st_get_texture_sampler_view_from_stobj(struct st_context 
*st,
  assert(stObj->base.MinLevel + stObj->base.BaseLevel ==
 view->u.tex.first_level);
  assert(last_level(stObj) == view->u.tex.last_level);
- assert(stObj->base.MinLayer == view->u.tex.first_layer);
- assert(last_layer(stObj) == view->u.tex.last_layer);
+ assert(stObj->layer_override || stObj->base.MinLayer == 
view->u.tex.first_layer);
+ assert(stObj->layer_override || last_layer(stObj) == 
view->u.tex.last_layer);
+ assert(!stObj->layer_override ||
+(stObj->layer_override == view->u.tex.first_layer &&
+ stObj->layer_override == view->u.tex.last_layer));
   }
}
else {
diff --git a/src/mesa/state_tracker/st_texture.h 
b/src/mesa/state_tracker/st_texture.h
index 730843a..0ce7989 100644
--- a/src/mesa/state_tracker/st_texture.h
+++ b/src/mesa/state_tracker/st_texture.h
@@ -108,6 +108,15 @@ struct st_texture_object
 */
enum pipe_format surface_format;
 
+   /* When non-zero, samplers should use this layer instead of the one
+* specified by the GL state.
+*
+* This is used for VDPAU interop, where imported pipe_resources may be
+* array textures (containing layers with different fields) even though the
+* GL state describes one non-array texture per field.
+*/
+   uint layer_override;
+
/** The glsl version of the shader seen during the previous validation */
unsigned prev_glsl_version;
/** The value of the sampler's sRGBDecode state at the previous validation 
*/
diff --git a/src/mesa/state_tracker/st_vdpau.c 
b/src/mesa/state_tracker/st_vdpau.c
index 7912057..0273815 100644
--- a/src/mesa/state_tracker/st_vdpau.c
+++ b/src/mesa/state_tracker/st_vdpau.c
@@ -189,8 +189,8 @@ st_vdpau_map_surface(struct gl_context *ctx, GLenum target, 
GLenum

Mesa (master): Revert "st/vdpau: use linear layout for output surfaces"

2016-11-04 Thread Emil Velikov 
Module: Mesa
Branch: master
Commit: d0d5f7600c2e8ab8d0c153787185f7a534753edd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d0d5f7600c2e8ab8d0c153787185f7a534753edd

Author: Dave Airlie 
Date:   Thu Sep 15 13:58:33 2016 +1000

Revert "st/vdpau: use linear layout for output surfaces"

This reverts commit d180de35320eafa3df3d76f0e82b332656530126.

This is a radeon specific hack that causes problems on nouveau
when combined with the SHARED flag later. If radeonsi needs a fix
for this, please fix it in the driver.

[chk]
Using linear surfaces for this makes sense because tilling isn't
beneficial and the surfaces can potentially be shared with other GPUs
using the VDPAU OpenGL interop.

[airlied]
I think we need a flag that isn't SHARED/LINEAR that is more
SHARED_OTHER_GPU.

[mareko]
Does radeonsi need PIPE_BIND_VIDEO_DECODE_OUTPUT that it would translate
into linear ?

[mareko]
My only concern is decoding performance. If the decoder works in 64x1
blocks, tiling will hurt. That's the theory. I don't know how the
decoder works.

Cc: 12.0 13.0 
Acked-by: Christian König 
Signed-off-by: Dave Airlie 
Tested-by: Ilia Mirkin 
Tested-by: Nayan Deshmukh  (I+A)

---

 src/gallium/state_trackers/vdpau/output.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/state_trackers/vdpau/output.c 
b/src/gallium/state_trackers/vdpau/output.c
index f4d62a3..8c29a3f 100644
--- a/src/gallium/state_trackers/vdpau/output.c
+++ b/src/gallium/state_trackers/vdpau/output.c
@@ -82,7 +82,7 @@ vlVdpOutputSurfaceCreate(VdpDevice device,
res_tmpl.depth0 = 1;
res_tmpl.array_size = 1;
res_tmpl.bind = PIPE_BIND_SAMPLER_VIEW | PIPE_BIND_RENDER_TARGET |
-   PIPE_BIND_LINEAR | PIPE_BIND_SHARED;
+   PIPE_BIND_SHARED;
res_tmpl.usage = PIPE_USAGE_DEFAULT;
 
pipe_mutex_lock(dev->mutex);

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Mesa (master): egl: make interop ABI visible again

2016-11-04 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: ee39d4456e7551b257343551d59e7c6a3388fdc0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee39d4456e7551b257343551d59e7c6a3388fdc0

Author: Marek Olšák 
Date:   Wed Nov  2 18:59:22 2016 +0100

egl: make interop ABI visible again

This was broken when the GLAPI use was removed from mesa_glinterop.h.

Cc: 12.0 13.0 
Acked-by: Alex Deucher 
Reviewed-by: Nicolai Hähnle 
Reviewed-by: Emil Velikov 

---

 src/egl/main/eglapi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index 04cac03..53340bf 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -2391,7 +2391,7 @@ _eglLockDisplayInterop(EGLDisplay dpy, EGLContext context,
return MESA_GLINTEROP_SUCCESS;
 }
 
-int
+PUBLIC int
 MesaGLInteropEGLQueryDeviceInfo(EGLDisplay dpy, EGLContext context,
 struct mesa_glinterop_device_info *out)
 {
@@ -2413,7 +2413,7 @@ MesaGLInteropEGLQueryDeviceInfo(EGLDisplay dpy, 
EGLContext context,
return ret;
 }
 
-int
+PUBLIC int
 MesaGLInteropEGLExportObject(EGLDisplay dpy, EGLContext context,
  struct mesa_glinterop_export_in *in,
  struct mesa_glinterop_export_out *out)

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Mesa (master): radeonsi: fix an assertion failure in si_decompress_sampler_color_textures

2016-11-04 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: 00baaa4752ab7e721218a2840cf0952d8c7c6eca
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=00baaa4752ab7e721218a2840cf0952d8c7c6eca

Author: Marek Olšák 
Date:   Thu Nov  3 19:16:51 2016 +0100

radeonsi: fix an assertion failure in si_decompress_sampler_color_textures

This fixes a crash in Deus Ex: Mankind Divided. Release builds were
unaffected, so it's not too serious.

Cc: 11.2 12.0 13.0 
Reviewed-by: Bas Nieuwenhuizen 
Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_blit.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index e086ed8..075d76a 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -486,7 +486,9 @@ si_decompress_sampler_color_textures(struct si_context 
*sctx,
assert(view);
 
tex = (struct r600_texture *)view->texture;
-   assert(tex->cmask.size || tex->fmask.size || tex->dcc_offset);
+   /* CMASK or DCC can be discarded and we can still end up here. 
*/
+   if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
+   continue;
 
si_blit_decompress_color(>b.b, tex,
 view->u.tex.first_level, 
view->u.tex.last_level,

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Mesa (master): egl: use util/macros.h

2016-11-04 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: bf51b45313c7cc5ca792401f0cc29574aa9122cf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf51b45313c7cc5ca792401f0cc29574aa9122cf

Author: Marek Olšák 
Date:   Wed Nov  2 18:56:39 2016 +0100

egl: use util/macros.h

I need the definition of PUBLIC.

Cc: 12.0 13.0 
Acked-by: Alex Deucher 
Reviewed-by: Nicolai Hähnle 
Reviewed-by: Emil Velikov 

---

 src/egl/drivers/dri2/egl_dri2.h | 2 --
 src/egl/main/egldefines.h   | 5 ++---
 2 files changed, 2 insertions(+), 5 deletions(-)

diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h
index 85d4b85..0020a5b 100644
--- a/src/egl/drivers/dri2/egl_dri2.h
+++ b/src/egl/drivers/dri2/egl_dri2.h
@@ -80,8 +80,6 @@
 #include "eglimage.h"
 #include "eglsync.h"
 
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-
 struct wl_buffer;
 
 struct dri2_egl_driver
diff --git a/src/egl/main/egldefines.h b/src/egl/main/egldefines.h
index 13a7563..d0502f3 100644
--- a/src/egl/main/egldefines.h
+++ b/src/egl/main/egldefines.h
@@ -34,6 +34,8 @@
 #ifndef EGLDEFINES_INCLUDED
 #define EGLDEFINES_INCLUDED
 
+#include "util/macros.h"
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -48,9 +50,6 @@ extern "C" {
 
 #define _EGL_VENDOR_STRING "Mesa Project"
 
-#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-#define MIN2(A, B)  (((A) < (B)) ? (A) : (B))
-
 #ifdef __cplusplus
 }
 #endif

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Mesa (master): glx: make interop ABI visible again

2016-11-04 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: 64c2593a5c33a98d880d141793360b44d07d1366
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=64c2593a5c33a98d880d141793360b44d07d1366

Author: Marek Olšák 
Date:   Wed Nov  2 18:59:22 2016 +0100

glx: make interop ABI visible again

This was broken when the GLAPI use was removed from mesa_glinterop.h.

Cc: 12.0 13.0 
Acked-by: Alex Deucher 
Reviewed-by: Nicolai Hähnle 
Reviewed-by: Emil Velikov 

---

 src/glx/glxcmds.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/glx/glxcmds.c b/src/glx/glxcmds.c
index 6abe0b9..8980de3 100644
--- a/src/glx/glxcmds.c
+++ b/src/glx/glxcmds.c
@@ -2713,7 +2713,7 @@ __glXGetUST(int64_t * ust)
 
 #if defined(GLX_DIRECT_RENDERING) && !defined(GLX_USE_APPLEGL)
 
-int
+PUBLIC int
 MesaGLInteropGLXQueryDeviceInfo(Display *dpy, GLXContext context,
 struct mesa_glinterop_device_info *out)
 {
@@ -2737,7 +2737,7 @@ MesaGLInteropGLXQueryDeviceInfo(Display *dpy, GLXContext 
context,
return ret;
 }
 
-int
+PUBLIC int
 MesaGLInteropGLXExportObject(Display *dpy, GLXContext context,
  struct mesa_glinterop_export_in *in,
  struct mesa_glinterop_export_out *out)

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Mesa (master): st/glsl_to_tgsi: fix dvec[34] loads from SSBO

2016-11-04 Thread Nicolai Hähnle 
Module: Mesa
Branch: master
Commit: e4b378800eff13752dcfe1f5c6b640444208d543
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e4b378800eff13752dcfe1f5c6b640444208d543

Author: Nicolai Hähnle 
Date:   Thu Nov  3 11:00:36 2016 +0100

st/glsl_to_tgsi: fix dvec[34] loads from SSBO

When splitting up loads, we have to add 16 bytes to the offset for
the high components, just like already happens for stores.

Fixes arb_gpu_shader_fp64@shader_storage@layout-std140-fp64-shader.

Cc: 13.0 
Reviewed-by: Marek Olšák 

---

 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 5b53c40..882e959 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -774,9 +774,9 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned 
op,
 
  int i = u_bit_scan();
 
- /* before emitting the instruction, see if we have to adjust store
+ /* before emitting the instruction, see if we have to adjust load / 
store
   * address */
- if (i > 1 && inst->op == TGSI_OPCODE_STORE &&
+ if (i > 1 && (inst->op == TGSI_OPCODE_LOAD || inst->op == 
TGSI_OPCODE_STORE) &&
  addr.file == PROGRAM_UNDEFINED) {
 /* We have to advance the buffer address by 16 */
 addr = get_temp(glsl_type::uint_type);
@@ -784,7 +784,6 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned 
op,
  inst->src[0], st_src_reg_for_int(16));
  }
 
-
  /* first time use previous instruction */
  if (dinst == NULL) {
 dinst = inst;
@@ -804,11 +803,10 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, 
unsigned op,
dinst->dst[j].writemask = (i & 1) ? WRITEMASK_ZW : WRITEMASK_XY;
dinst->dst[j].index = initial_dst_idx[j];
if (i > 1) {
-  if (dinst->op == TGSI_OPCODE_STORE) {
+  if (dinst->op == TGSI_OPCODE_LOAD || dinst->op == 
TGSI_OPCODE_STORE)
  dinst->src[0] = addr;
-  } else {
+  if (dinst->op != TGSI_OPCODE_STORE)
  dinst->dst[j].index++;
-  }
}
 } else {
/* if we aren't writing to a double, just get the bit of the 
initial writemask

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Mesa (master): radeonsi: enable GLSL 4.50

2016-11-04 Thread Nicolai Hähnle 
Module: Mesa
Branch: master
Commit: 84a74be9e4ce5149c7952f16a9e94e2094f4b353
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=84a74be9e4ce5149c7952f16a9e94e2094f4b353

Author: Nicolai Hähnle 
Date:   Fri Oct  7 18:21:51 2016 +0200

radeonsi: enable GLSL 4.50

Reviewed-by: Edward O'Callaghan 
Reviewed-by: Dave Airlie 

---

 src/gallium/drivers/radeonsi/si_pipe.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index bc633bb..273633c 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -438,7 +438,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum 
pipe_cap param)
 
case PIPE_CAP_GLSL_FEATURE_LEVEL:
if (si_have_tgsi_compute(sscreen))
-   return 430;
+   return 450;
return HAVE_LLVM >= 0x0309 ? 420 :
   HAVE_LLVM >= 0x0307 ? 410 : 330;
 

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Mesa (master): glsl/cache: correct asprintf error handling

2016-11-04 Thread Nicolai Hähnle 
Module: Mesa
Branch: master
Commit: aef7eb4cacbb241dc895f3e08dba4c91052a98a8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aef7eb4cacbb241dc895f3e08dba4c91052a98a8

Author: Nicolai Hähnle 
Date:   Thu Nov  3 10:23:17 2016 +0100

glsl/cache: correct asprintf error handling

From the manpage of asprintf:

   "If memory allocation wasn't possible, or some other error occurs,
these functions will return -1, and the contents of strp are
undefined."

Reviewed-by: Iago Toral Quiroga 
Reviewed-by: Edward O'Callaghan 

---

 src/compiler/glsl/cache.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/compiler/glsl/cache.c b/src/compiler/glsl/cache.c
index 64a34f0..e74c27d 100644
--- a/src/compiler/glsl/cache.c
+++ b/src/compiler/glsl/cache.c
@@ -416,7 +416,8 @@ choose_random_file_matching(const char *dir_path,
   return NULL;
}
 
-   asprintf(, "%s/%s", dir_path, entry->d_name);
+   if (asprintf(, "%s/%s", dir_path, entry->d_name) < 0)
+  filename = NULL;
 
closedir(dir);
 
@@ -497,8 +498,7 @@ evict_random_item(struct program_cache *cache)
a = rand() % 16;
b = rand() % 16;
 
-   asprintf (_path, "%s/%c%c", cache->path, hex[a], hex[b]);
-   if (dir_path == NULL)
+   if (asprintf(_path, "%s/%c%c", cache->path, hex[a], hex[b]) < 0)
   return;
 
size = unlink_random_file_from_directory(dir_path);

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Mesa (master): gallium/radeon: Use flags parameter in radeon_winsys_surface_init

2016-11-04 Thread Michel Dänzer 
Module: Mesa
Branch: master
Commit: 356458363d1ee590fe05afb37ca502c2dd733666
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=356458363d1ee590fe05afb37ca502c2dd733666

Author: Michel Dänzer 
Date:   Wed Nov  2 19:48:35 2016 +0900

gallium/radeon: Use flags parameter in radeon_winsys_surface_init

Fixes valgrind warnings about surf_ws->flags being uninitialized while
starting X.

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index 7b85973..6836a1b 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -228,7 +228,7 @@ static int radeon_winsys_surface_init(struct radeon_winsys 
*rws,
 
 surf_winsys_to_drm(_drm, tex, flags, bpe, mode, surf_ws);
 
-if (!(surf_ws->flags & RADEON_SURF_IMPORTED)) {
+if (!(flags & RADEON_SURF_IMPORTED)) {
r = radeon_surface_best(ws->surf_man, _drm);
if (r)
   return r;

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Mesa (master): gallium/radeon: Only loop up to last_level for drm<-> winsys conversion

2016-11-04 Thread Michel Dänzer 
Module: Mesa
Branch: master
Commit: 38fb9aa1aa8a25443196a6fdbe21d538ba91a347
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=38fb9aa1aa8a25443196a6fdbe21d538ba91a347

Author: Michel Dänzer 
Date:   Wed Nov  2 18:43:37 2016 +0900

gallium/radeon: Only loop up to last_level for drm<->winsys conversion

Fixes spurious assertion failure in surf_level_drm_to_winsys when
starting X, due to processing a miplevel which was never initialized.

Fixes: e9c76eeeaa67 ("gallium/radeon: remove radeon_surf_level::pitch_bytes")
Reviewed-by: Nicolai Hähnle 
Reviewed-by: Marek Olšák 

---

 src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index c6fa475..e3eea59 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -157,7 +157,7 @@ static void surf_winsys_to_drm(struct radeon_surface 
*surf_drm,
 surf_drm->tile_split = surf_ws->tile_split;
 surf_drm->stencil_tile_split = surf_ws->stencil_tile_split;
 
-for (i = 0; i < RADEON_SURF_MAX_LEVELS; i++) {
+for (i = 0; i <= surf_drm->last_level; i++) {
 surf_level_winsys_to_drm(_drm->level[i], _ws->level[i], bpe);
 surf_level_winsys_to_drm(_drm->stencil_level[i],
  _ws->stencil_level[i], bpe);
@@ -192,7 +192,7 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
 
 surf_ws->macro_tile_index = cik_get_macro_tile_index(surf_ws);
 
-for (i = 0; i < RADEON_SURF_MAX_LEVELS; i++) {
+for (i = 0; i <= surf_drm->last_level; i++) {
 surf_level_drm_to_winsys(_ws->level[i], _drm->level[i],
  surf_drm->bpe * surf_drm->nsamples);
 surf_level_drm_to_winsys(_ws->stencil_level[i],

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Mesa (master): gallium/radeon: Only convert stencil info if RADEON_SURF_SBUFFER is set

2016-11-04 Thread Michel Dänzer 
Module: Mesa
Branch: master
Commit: 6f844a30c1616eac4955134ff130aad699a8079c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f844a30c1616eac4955134ff130aad699a8079c

Author: Michel Dänzer 
Date:   Wed Nov  2 19:09:06 2016 +0900

gallium/radeon: Only convert stencil info if RADEON_SURF_SBUFFER is set

Fixes valgrind warnings about using uninitialized memory when starting X.

Reviewed-by: Nicolai Hähnle 
Reviewed-by: Marek Olšák 

---

 src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 31 +++---
 1 file changed, 21 insertions(+), 10 deletions(-)

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index e3eea59..7b85973 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -155,15 +155,20 @@ static void surf_winsys_to_drm(struct radeon_surface 
*surf_drm,
 surf_drm->bankh = surf_ws->bankh;
 surf_drm->mtilea = surf_ws->mtilea;
 surf_drm->tile_split = surf_ws->tile_split;
-surf_drm->stencil_tile_split = surf_ws->stencil_tile_split;
 
 for (i = 0; i <= surf_drm->last_level; i++) {
 surf_level_winsys_to_drm(_drm->level[i], _ws->level[i], bpe);
-surf_level_winsys_to_drm(_drm->stencil_level[i],
- _ws->stencil_level[i], bpe);
-
 surf_drm->tiling_index[i] = surf_ws->tiling_index[i];
-surf_drm->stencil_tiling_index[i] = surf_ws->stencil_tiling_index[i];
+}
+
+if (flags & RADEON_SURF_SBUFFER) {
+surf_drm->stencil_tile_split = surf_ws->stencil_tile_split;
+
+for (i = 0; i <= surf_drm->last_level; i++) {
+surf_level_winsys_to_drm(_drm->stencil_level[i],
+ _ws->stencil_level[i], bpe);
+surf_drm->stencil_tiling_index[i] = 
surf_ws->stencil_tiling_index[i];
+}
 }
 }
 
@@ -188,18 +193,24 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys 
*ws,
 surf_ws->bankh = surf_drm->bankh;
 surf_ws->mtilea = surf_drm->mtilea;
 surf_ws->tile_split = surf_drm->tile_split;
-surf_ws->stencil_tile_split = surf_drm->stencil_tile_split;
 
 surf_ws->macro_tile_index = cik_get_macro_tile_index(surf_ws);
 
 for (i = 0; i <= surf_drm->last_level; i++) {
 surf_level_drm_to_winsys(_ws->level[i], _drm->level[i],
  surf_drm->bpe * surf_drm->nsamples);
-surf_level_drm_to_winsys(_ws->stencil_level[i],
- _drm->stencil_level[i], 
surf_drm->nsamples);
-
 surf_ws->tiling_index[i] = surf_drm->tiling_index[i];
-surf_ws->stencil_tiling_index[i] = surf_drm->stencil_tiling_index[i];
+}
+
+if (surf_ws->flags & RADEON_SURF_SBUFFER) {
+surf_ws->stencil_tile_split = surf_drm->stencil_tile_split;
+
+for (i = 0; i <= surf_drm->last_level; i++) {
+surf_level_drm_to_winsys(_ws->stencil_level[i],
+ _drm->stencil_level[i],
+ surf_drm->nsamples);
+surf_ws->stencil_tiling_index[i] = 
surf_drm->stencil_tiling_index[i];
+}
 }
 
 set_micro_tile_mode(surf_ws, >info);

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Mesa (master): gallium/radeon: Multiply bpe by nsamples in surf_winsys_to_drm

2016-11-04 Thread Michel Dänzer 
Module: Mesa
Branch: master
Commit: 8ce7ef75f5d164bfe9eae23749e83b6a88e2b270
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ce7ef75f5d164bfe9eae23749e83b6a88e2b270

Author: Michel Dänzer 
Date:   Wed Nov  2 18:54:44 2016 +0900

gallium/radeon: Multiply bpe by nsamples in surf_winsys_to_drm

For symmetry with surf_drm_to_winsys.

Reviewed-by: Nicolai Hähnle 
Reviewed-by: Marek Olšák 

---

 src/gallium/winsys/radeon/drm/radeon_drm_surface.c | 7 +--
 1 file changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c 
b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
index 6836a1b..8324d28 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_surface.c
@@ -157,7 +157,9 @@ static void surf_winsys_to_drm(struct radeon_surface 
*surf_drm,
 surf_drm->tile_split = surf_ws->tile_split;
 
 for (i = 0; i <= surf_drm->last_level; i++) {
-surf_level_winsys_to_drm(_drm->level[i], _ws->level[i], bpe);
+surf_level_winsys_to_drm(_drm->level[i], _ws->level[i],
+ bpe * surf_drm->nsamples);
+
 surf_drm->tiling_index[i] = surf_ws->tiling_index[i];
 }
 
@@ -166,7 +168,8 @@ static void surf_winsys_to_drm(struct radeon_surface 
*surf_drm,
 
 for (i = 0; i <= surf_drm->last_level; i++) {
 surf_level_winsys_to_drm(_drm->stencil_level[i],
- _ws->stencil_level[i], bpe);
+ _ws->stencil_level[i],
+ surf_drm->nsamples);
 surf_drm->stencil_tiling_index[i] = 
surf_ws->stencil_tiling_index[i];
 }
 }

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Mesa (master): anv: use limits.h instead of deprecated/obsolete values.h

2016-11-04 Thread Tapani Pälli 
Module: Mesa
Branch: master
Commit: 1e3f7bfc9ae4c35f75e6843dda451fde7c107e5c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e3f7bfc9ae4c35f75e6843dda451fde7c107e5c

Author: Tapani Pälli 
Date:   Thu Nov  3 13:44:47 2016 +0200

anv: use limits.h instead of deprecated/obsolete values.h

Mesa uses limits.h elsewhere, and this makes is possible to
compile anv_allocator.c on Android.

Signed-off-by: Tapani Pälli 
Reviewed-by: Samuel Iglesias Gonsálvez 

---

 src/intel/vulkan/anv_allocator.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
index 36cabd7..2249fa6 100644
--- a/src/intel/vulkan/anv_allocator.c
+++ b/src/intel/vulkan/anv_allocator.c
@@ -24,7 +24,7 @@
 #include 
 #include 
 #include 
-#include 
+#include 
 #include 
 #include 
 #include 

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