date:20161226

Mesa (master): egl/dri2: implement query surface hook

2016-12-26 Thread Tapani Pälli

Module: Mesa
Branch: master
Commit: 4d6d4f939e0af4252e0b6ba3fcb2c9f4101e9e39
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4d6d4f939e0af4252e0b6ba3fcb2c9f4101e9e39

Author: Tapani Pälli 
Date:   Wed Dec 21 10:21:34 2016 +0200

egl/dri2: implement query surface hook

This makes better guarantee that the values we return are
in sync what the underlying drawable currently has.

Together with dEQP change in bug #98327 this fixes following test:

   dEQP-EGL.functional.resize.surface_size.grow

v2: avoid unnecessary x11 roundtrips (Chad Versace)

Signed-off-by: Tapani Pälli 
Tested-by: Mark Janes 
Reviewed-by: Chad Versace 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98327

---

 src/egl/drivers/dri2/platform_x11.c | 36 
 1 file changed, 36 insertions(+)

diff --git a/src/egl/drivers/dri2/platform_x11.c 
b/src/egl/drivers/dri2/platform_x11.c
index db7d3b9..9a93b19 100644
--- a/src/egl/drivers/dri2/platform_x11.c
+++ b/src/egl/drivers/dri2/platform_x11.c
@@ -395,6 +395,40 @@ dri2_x11_destroy_surface(_EGLDriver *drv, _EGLDisplay 
*disp, _EGLSurface *surf)
 }
 
 /**
+ * Function utilizes swrastGetDrawableInfo to get surface
+ * geometry from x server and calls default query surface
+ * implementation that returns the updated values.
+ *
+ * In case of errors we still return values that we currently
+ * have.
+ */
+static EGLBoolean
+dri2_query_surface(_EGLDriver *drv, _EGLDisplay *dpy,
+   _EGLSurface *surf, EGLint attribute,
+   EGLint *value)
+{
+   struct dri2_egl_display *dri2_dpy = dri2_egl_display(dpy);
+   struct dri2_egl_surface *dri2_surf = dri2_egl_surface(surf);
+   int x, y, w = -1, h = -1;
+
+   __DRIdrawable *drawable = dri2_dpy->vtbl->get_dri_drawable(surf);
+
+   switch (attribute) {
+   case EGL_WIDTH:
+   case EGL_HEIGHT:
+  swrastGetDrawableInfo(drawable, , , , , dri2_surf);
+  if (w != -1 && h != -1) {
+ surf->Width = w;
+ surf->Height = h;
+  }
+  break;
+   default:
+  break;
+   }
+   return _eglQuerySurface(drv, dpy, surf, attribute, value);
+}
+
+/**
  * Process list of buffer received from the server
  *
  * Processes the list of buffers received in a reply from the server to either
@@ -1113,6 +1147,7 @@ static struct dri2_egl_display_vtbl 
dri2_x11_swrast_display_vtbl = {
.post_sub_buffer = dri2_fallback_post_sub_buffer,
.copy_buffers = dri2_x11_copy_buffers,
.query_buffer_age = dri2_fallback_query_buffer_age,
+   .query_surface = dri2_query_surface,
.create_wayland_buffer_from_image = 
dri2_fallback_create_wayland_buffer_from_image,
.get_sync_values = dri2_fallback_get_sync_values,
.get_dri_drawable = dri2_surface_get_dri_drawable,
@@ -1132,6 +1167,7 @@ static struct dri2_egl_display_vtbl dri2_x11_display_vtbl 
= {
.post_sub_buffer = dri2_x11_post_sub_buffer,
.copy_buffers = dri2_x11_copy_buffers,
.query_buffer_age = dri2_fallback_query_buffer_age,
+   .query_surface = dri2_query_surface,
.create_wayland_buffer_from_image = 
dri2_fallback_create_wayland_buffer_from_image,
.get_sync_values = dri2_x11_get_sync_values,
.get_dri_drawable = dri2_surface_get_dri_drawable,

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Mesa (master): radv: Also skip DCC clear flushes for compute.

2016-12-26 Thread Dave Airlie

Module: Mesa
Branch: master
Commit: 059af2515ad778f569e999547cb44a195f66c198
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=059af2515ad778f569e999547cb44a195f66c198

Author: Bas Nieuwenhuizen 
Date:   Tue Dec 27 00:57:36 2016 +0100

radv: Also skip DCC clear flushes for compute.

(airlied: fixes DOOM hang with compute queue enabled)
Reviewed-by: Dave Airlie 
Signed-off-by: Bas Nieuwenhuizen 

---

 src/amd/vulkan/radv_cmd_buffer.c | 14 +-
 src/amd/vulkan/radv_image.c  |  6 +++---
 src/amd/vulkan/radv_meta_clear.c |  2 +-
 src/amd/vulkan/radv_private.h|  6 +++---
 4 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index d29432b..fdb35a0 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2398,8 +2398,8 @@ static void radv_handle_cmask_image_transition(struct 
radv_cmd_buffer *cmd_buffe
radv_initialise_cmask(cmd_buffer, image, 0xu);
else
radv_initialise_cmask(cmd_buffer, image, 0xu);
-   } else if (radv_layout_has_cmask(image, src_layout, src_queue_mask) &&
-  !radv_layout_has_cmask(image, dst_layout, dst_queue_mask)) {
+   } else if (radv_layout_can_fast_clear(image, src_layout, 
src_queue_mask) &&
+  !radv_layout_can_fast_clear(image, dst_layout, 
dst_queue_mask)) {
radv_fast_clear_flush_image_inplace(cmd_buffer, image);
}
 }
@@ -2425,13 +2425,15 @@ static void radv_handle_dcc_image_transition(struct 
radv_cmd_buffer *cmd_buffer,
 struct radv_image *image,
 VkImageLayout src_layout,
 VkImageLayout dst_layout,
+unsigned src_queue_mask,
+unsigned dst_queue_mask,
 VkImageSubresourceRange range,
 VkImageAspectFlags pending_clears)
 {
if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
radv_initialize_dcc(cmd_buffer, image, 0x20202020u);
-   } else if(src_layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL &&
- dst_layout != VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL) {
+   } else if (radv_layout_can_fast_clear(image, src_layout, 
src_queue_mask) &&
+  !radv_layout_can_fast_clear(image, dst_layout, 
dst_queue_mask)) {
radv_fast_clear_flush_image_inplace(cmd_buffer, image);
}
 }
@@ -2477,7 +2479,9 @@ static void radv_handle_image_transition(struct 
radv_cmd_buffer *cmd_buffer,
 
if (image->surface.dcc_size)
radv_handle_dcc_image_transition(cmd_buffer, image, src_layout,
-dst_layout, range, 
pending_clears);
+dst_layout, src_queue_mask,
+dst_queue_mask, range,
+pending_clears);
 }
 
 void radv_CmdPipelineBarrier(
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 6e03f49..8af064b 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -893,9 +893,9 @@ bool radv_layout_can_expclear(const struct radv_image 
*image,
layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL);
 }
 
-bool radv_layout_has_cmask(const struct radv_image *image,
-  VkImageLayout layout,
-  unsigned queue_mask)
+bool radv_layout_can_fast_clear(const struct radv_image *image,
+   VkImageLayout layout,
+   unsigned queue_mask)
 {
return (layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL ||
layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL) &&
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index b7263dd..cb2aa1a 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -805,7 +805,7 @@ emit_fast_color_clear(struct radv_cmd_buffer *cmd_buffer,
if (!cmd_buffer->device->allow_fast_clears)
return false;
 
-   if (!radv_layout_has_cmask(iview->image, image_layout, 
radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index)))
+   if (!radv_layout_can_fast_clear(iview->image, image_layout, 
radv_image_queue_family_mask(iview->image, cmd_buffer->queue_family_index)))
goto fail;
if (vk_format_get_blocksizebits(iview->image->vk_format) > 64)
goto fail;
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index e15556e..f76d38d 100644
---

Mesa (master): radv: add some asserts for operations on general queue

2016-12-26 Thread Dave Airlie

Module: Mesa
Branch: master
Commit: d8423772cad8245c21d1a63ed4fabb8d9e20b4fa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8423772cad8245c21d1a63ed4fabb8d9e20b4fa

Author: Dave Airlie 
Date:   Tue Dec 27 03:26:11 2016 +

radv: add some asserts for operations on general queue

These might be useful in the future, or not.

Signed-off-by: Dave Airlie 

---

 src/amd/vulkan/radv_meta_decompress.c | 2 ++
 src/amd/vulkan/radv_meta_fast_clear.c | 1 +
 2 files changed, 3 insertions(+)

diff --git a/src/amd/vulkan/radv_meta_decompress.c 
b/src/amd/vulkan/radv_meta_decompress.c
index 47ef64d..4907475 100644
--- a/src/amd/vulkan/radv_meta_decompress.c
+++ b/src/amd/vulkan/radv_meta_decompress.c
@@ -450,6 +450,7 @@ void radv_decompress_depth_image_inplace(struct 
radv_cmd_buffer *cmd_buffer,
 struct radv_image *image,
 VkImageSubresourceRange 
*subresourceRange)
 {
+   assert(cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL);
radv_process_depth_image_inplace(cmd_buffer, image, subresourceRange,
 
cmd_buffer->device->meta_state.depth_decomp.decompress_pipeline);
 }
@@ -458,6 +459,7 @@ void radv_resummarize_depth_image_inplace(struct 
radv_cmd_buffer *cmd_buffer,
 struct radv_image *image,
 VkImageSubresourceRange 
*subresourceRange)
 {
+   assert(cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL);
radv_process_depth_image_inplace(cmd_buffer, image, subresourceRange,
 
cmd_buffer->device->meta_state.depth_decomp.resummarize_pipeline);
 }
diff --git a/src/amd/vulkan/radv_meta_fast_clear.c 
b/src/amd/vulkan/radv_meta_fast_clear.c
index f79c634..950b438 100644
--- a/src/amd/vulkan/radv_meta_fast_clear.c
+++ b/src/amd/vulkan/radv_meta_fast_clear.c
@@ -419,6 +419,7 @@ radv_fast_clear_flush_image_inplace(struct radv_cmd_buffer 
*cmd_buffer,
VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
 
+   assert(cmd_buffer->queue_family_index == RADV_QUEUE_GENERAL);
radv_meta_save_pass(_pass_state, cmd_buffer);
radv_meta_save_graphics_reset_vport_scissor(_state, cmd_buffer);
 

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Mesa (master): radv: handle queue present directly to winsys

2016-12-26 Thread Dave Airlie

Module: Mesa
Branch: master
Commit: 3fd306b4232656914267bca824b7dde4be0e2ffb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3fd306b4232656914267bca824b7dde4be0e2ffb

Author: Dave Airlie 
Date:   Fri Dec 23 06:24:21 2016 +

radv: handle queue present directly to winsys

Don't call the QueueSubmit interface, just call direct to the
winsys, so we can pass the wait semaphores.

Noticed while debugging doom, doesn't fix anything.

Reviewed-by: Bas Nieuwenhuizen 
Signed-off-by: Dave Airlie 

---

 src/amd/vulkan/radv_wsi.c | 10 +-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_wsi.c b/src/amd/vulkan/radv_wsi.c
index 1f1ab1c..2eb8e45 100644
--- a/src/amd/vulkan/radv_wsi.c
+++ b/src/amd/vulkan/radv_wsi.c
@@ -362,7 +362,15 @@ VkResult radv_QueuePresentKHR(
 1, >fences[0]);
}
 
-   radv_QueueSubmit(_queue, 0, NULL, swapchain->fences[0]);
+   RADV_FROM_HANDLE(radv_fence, fence, swapchain->fences[0]);
+   struct radeon_winsys_fence *base_fence = fence->fence;
+   struct radeon_winsys_ctx *ctx = queue->device->hw_ctx;
+   queue->device->ws->cs_submit(ctx, queue->queue_idx,
+
>device->empty_cs[queue->queue_family_index],
+1,
+(struct radeon_winsys_sem 
**)pPresentInfo->pWaitSemaphores,
+pPresentInfo->waitSemaphoreCount, 
NULL, 0, false, base_fence);
+   fence->submitted = true;
 
result = swapchain->queue_present(swapchain,
  
pPresentInfo->pImageIndices[i]);

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Mesa (master): intel/blorp_blit: Fix max blit size for gen6

2016-12-26 Thread Jordan Justen

Module: Mesa
Branch: master
Commit: 097c9dc2d4abc57bac5195fa0bed327828a4a895
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=097c9dc2d4abc57bac5195fa0bed327828a4a895

Author: Jordan Justen 
Date:   Fri Dec 23 18:41:15 2016 -0800

intel/blorp_blit: Fix max blit size for gen6

Fixes 
ES3-CTS.gtf.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_stencil_blit

Signed-off-by: Jordan Justen 
Reviewed-by: Lionel Landwerlin 
Reviewed-by: Kenneth Graunke 

---

 src/intel/blorp/blorp_blit.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 8abe3a8..1cbd940 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -1522,10 +1522,11 @@ static unsigned
 get_max_surface_size(const struct gen_device_info *devinfo,
  const struct blorp_params *params)
 {
+   const unsigned max = devinfo->gen >= 7 ? 16384 : 8192;
if (split_blorp_blit_debug && can_shrink_surfaces(params))
-  return 16384 >> 4; /* A smaller restriction when debug is enabled */
+  return max >> 4; /* A smaller restriction when debug is enabled */
else
-  return 16384;
+  return max;
 }
 
 struct blt_axis {

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Mesa (master): egl/dri2: implement query surface hook

Mesa (master): radv: Also skip DCC clear flushes for compute.

Mesa (master): radv: add some asserts for operations on general queue

Mesa (master): radv: handle queue present directly to winsys

Mesa (master): intel/blorp_blit: Fix max blit size for gen6

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