Mesa (master): glsl: fix tes linking regression

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: f3f9207786c2862b9b3fed1b4348ecb6a85cf02e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f3f9207786c2862b9b3fed1b4348ecb6a85cf02e

Author: Timothy Arceri 
Date:   Mon Jan 23 18:06:37 2017 +1100

glsl: fix tes linking regression

Fixes regression caused by cbeba6bd48da2c. I accidentally pushed the
wrong version of the patch.

---

 src/compiler/glsl/linker.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index 77eb78a..dafa39d 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -1804,13 +1804,13 @@ link_tes_in_layout_qualifiers(struct gl_shader_program 
*prog,
if (gl_prog->info.tess.spacing == TESS_SPACING_UNSPECIFIED)
   gl_prog->info.tess.spacing = TESS_SPACING_EQUAL;
 
-   if (vertex_order == 0)
+   if (vertex_order == 0 || vertex_order == GL_CCW)
   gl_prog->info.tess.ccw = true;
else
   gl_prog->info.tess.ccw = false;
 
 
-   if (point_mode == -1)
+   if (point_mode == -1 || point_mode == GL_FALSE)
   gl_prog->info.tess.point_mode = false;
else
   gl_prog->info.tess.point_mode = true;

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Mesa (master): glsl: split DIV_TO_MUL_RCP into single- and double-precision flags

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: b71c415c3d288da4b5f533ece42f50f4f20a8c33
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b71c415c3d288da4b5f533ece42f50f4f20a8c33

Author: Nicolai Hähnle 
Date:   Mon Jan 16 16:39:06 2017 +0100

glsl: split DIV_TO_MUL_RCP into single- and double-precision flags

Reviewed-by: Marek Olšák 
Reviewed-by: Iago Toral Quiroga 
Tested-by: Glenn Kennard 
Tested-by: James Harvey 
Cc: 17.0 

---

 src/compiler/glsl/ir_optimization.h  |  4 +++-
 src/compiler/glsl/lower_instructions.cpp | 19 +++
 2 files changed, 14 insertions(+), 9 deletions(-)

diff --git a/src/compiler/glsl/ir_optimization.h 
b/src/compiler/glsl/ir_optimization.h
index d46b957..67a7514 100644
--- a/src/compiler/glsl/ir_optimization.h
+++ b/src/compiler/glsl/ir_optimization.h
@@ -30,7 +30,7 @@
 
 /* Operations for lower_instructions() */
 #define SUB_TO_ADD_NEG 0x01
-#define DIV_TO_MUL_RCP 0x02
+#define FDIV_TO_MUL_RCP0x02
 #define EXP_TO_EXP20x04
 #define POW_TO_EXP20x08
 #define LOG_TO_LOG20x10
@@ -49,6 +49,8 @@
 #define FIND_LSB_TO_FLOAT_CAST0x2
 #define FIND_MSB_TO_FLOAT_CAST0x4
 #define IMUL_HIGH_TO_MUL  0x8
+#define DDIV_TO_MUL_RCP   0x10
+#define DIV_TO_MUL_RCP(FDIV_TO_MUL_RCP | DDIV_TO_MUL_RCP)
 
 /* Opertaions for lower_64bit_integer_instructions() */
 #define MUL64 (1U << 0)
diff --git a/src/compiler/glsl/lower_instructions.cpp 
b/src/compiler/glsl/lower_instructions.cpp
index 9fc83d1..729cb13 100644
--- a/src/compiler/glsl/lower_instructions.cpp
+++ b/src/compiler/glsl/lower_instructions.cpp
@@ -54,8 +54,8 @@
  * want to recognize add(op0, neg(op1)) or the other way around to
  * produce a subtract anyway.
  *
- * DIV_TO_MUL_RCP and INT_DIV_TO_MUL_RCP:
- * --
+ * FDIV_TO_MUL_RCP, DDIV_TO_MUL_RCP, and INT_DIV_TO_MUL_RCP:
+ * -
  * Breaks an ir_binop_div expression down to op0 * (rcp(op1)).
  *
  * Many GPUs don't have a divide instruction (945 and 965 included),
@@ -63,9 +63,11 @@
  * reciprocal.  By breaking the operation down, constant reciprocals
  * can get constant folded.
  *
- * DIV_TO_MUL_RCP only lowers floating point division; INT_DIV_TO_MUL_RCP
- * handles the integer case, converting to and from floating point so that
- * RCP is possible.
+ * FDIV_TO_MUL_RCP only lowers single-precision floating point division;
+ * DDIV_TO_MUL_RCP only lowers double-precision floating point division.
+ * DIV_TO_MUL_RCP is a convenience macro that sets both flags.
+ * INT_DIV_TO_MUL_RCP handles the integer case, converting to and from floating
+ * point so that RCP is possible.
  *
  * EXP_TO_EXP2 and LOG_TO_LOG2:
  * 
@@ -326,7 +328,8 @@ lower_instructions_visitor::mod_to_floor(ir_expression *ir)
/* Don't generate new IR that would need to be lowered in an additional
 * pass.
 */
-   if (lowering(DIV_TO_MUL_RCP) && (ir->type->is_float() || 
ir->type->is_double()))
+   if ((lowering(FDIV_TO_MUL_RCP) && ir->type->is_float()) ||
+   (lowering(DDIV_TO_MUL_RCP) && ir->type->is_double()))
   div_to_mul_rcp(div_expr);
 
ir_expression *const floor_expr =
@@ -1599,8 +1602,8 @@ lower_instructions_visitor::visit_leave(ir_expression *ir)
case ir_binop_div:
   if (ir->operands[1]->type->is_integer() && lowering(INT_DIV_TO_MUL_RCP))
 int_div_to_mul_rcp(ir);
-  else if ((ir->operands[1]->type->is_float() ||
-ir->operands[1]->type->is_double()) && 
lowering(DIV_TO_MUL_RCP))
+  else if ((ir->operands[1]->type->is_float() && 
lowering(FDIV_TO_MUL_RCP)) ||
+   (ir->operands[1]->type->is_double() && 
lowering(DDIV_TO_MUL_RCP)))
 div_to_mul_rcp(ir);
   break;
 

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Mesa (master): r600: factor out cayman_emit_unary_double_raw

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 488560cfe6ee2206f7a7f894694ebc43b419be61
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=488560cfe6ee2206f7a7f894694ebc43b419be61

Author: Nicolai Hähnle 
Date:   Thu Jan 19 14:44:24 2017 +0100

r600: factor out cayman_emit_unary_double_raw

We will use it for DDIV.

Tested-by: Glenn Kennard 
Tested-by: James Harvey 
Cc: 17.0 

---

 src/gallium/drivers/r600/r600_shader.c | 62 +++---
 1 file changed, 42 insertions(+), 20 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 7d1452a..5c4bc91 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -4185,42 +4185,64 @@ static int egcm_double_to_int(struct r600_shader_ctx 
*ctx)
return 0;
 }
 
-static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
+static int cayman_emit_unary_double_raw(struct r600_bytecode *bc,
+   unsigned op,
+   int dst_reg,
+   struct r600_shader_src *src,
+   bool abs)
 {
-   struct tgsi_full_instruction *inst = 
&ctx->parse.FullToken.FullInstruction;
-   int i, r;
struct r600_bytecode_alu alu;
-   int last_slot = 3;
-   int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
-   int t1 = ctx->temp_reg;
+   const int last_slot = 3;
+   int r;
 
/* these have to write the result to X/Y by the looks of it */
-   for (i = 0 ; i < last_slot; i++) {
+   for (int i = 0 ; i < last_slot; i++) {
memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-   alu.op = ctx->inst_info->op;
-
-   /* should only be one src regs */
-   assert (inst->Instruction.NumSrcRegs == 1);
+   alu.op = op;
 
-   r600_bytecode_src(&alu.src[0], &ctx->src[0], 1);
-   r600_bytecode_src(&alu.src[1], &ctx->src[0], 0);
+   r600_bytecode_src(&alu.src[0], src, 1);
+   r600_bytecode_src(&alu.src[1], src, 0);
 
-   /* RSQ should take the absolute value of src */
-   if (ctx->parse.FullToken.FullInstruction.Instruction.Opcode == 
TGSI_OPCODE_DRSQ ||
-   ctx->parse.FullToken.FullInstruction.Instruction.Opcode == 
TGSI_OPCODE_DSQRT) {
+   if (abs)
r600_bytecode_src_set_abs(&alu.src[1]);
-   }
-   alu.dst.sel = t1;
+
+   alu.dst.sel = dst_reg;
alu.dst.chan = i;
alu.dst.write = (i == 0 || i == 1);
 
-   if (ctx->bc->chip_class != CAYMAN || i == last_slot - 1)
+   if (bc->chip_class != CAYMAN || i == last_slot - 1)
alu.last = 1;
-   r = r600_bytecode_add_alu(ctx->bc, &alu);
+   r = r600_bytecode_add_alu(bc, &alu);
if (r)
return r;
}
 
+   return 0;
+}
+
+static int cayman_emit_double_instr(struct r600_shader_ctx *ctx)
+{
+   struct tgsi_full_instruction *inst = 
&ctx->parse.FullToken.FullInstruction;
+   int i, r;
+   struct r600_bytecode_alu alu;
+   int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
+   int t1 = ctx->temp_reg;
+
+   /* should only be one src regs */
+   assert(inst->Instruction.NumSrcRegs == 1);
+
+   /* only support one double at a time */
+   assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
+  inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
+
+   r = cayman_emit_unary_double_raw(
+   ctx->bc, ctx->inst_info->op, t1,
+   &ctx->src[0],
+   ctx->parse.FullToken.FullInstruction.Instruction.Opcode == 
TGSI_OPCODE_DRSQ ||
+   ctx->parse.FullToken.FullInstruction.Instruction.Opcode == 
TGSI_OPCODE_DSQRT);
+   if (r)
+   return r;
+
for (i = 0 ; i <= lasti; i++) {
if (!(inst->Dst[0].Register.WriteMask & (1 << i)))
continue;

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Mesa (master): st/glsl_to_tgsi: use DDIV instead of DRCP + DMUL

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: cfabbbcfd778cc404813c9f05a9ef79efe531980
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cfabbbcfd778cc404813c9f05a9ef79efe531980

Author: Nicolai Hähnle 
Date:   Mon Jan 16 16:43:54 2017 +0100

st/glsl_to_tgsi: use DDIV instead of DRCP + DMUL

Fixes GL45-CTS.gpu_shader_fp64.built_in_functions.

v2: use DDIV unconditionally (Roland)

Reviewed-by: Roland Scheidegger  (v1)
Reviewed-by: Marek Olšák  (v1)
Tested-by: Glenn Kennard 
Tested-by: James Harvey 
Cc: 17.0 

---

 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 9 +++--
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 46952dc..37bd09f 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -955,7 +955,7 @@ glsl_to_tgsi_visitor::get_opcode(unsigned op,
   case3fid(MUL, UMUL, DMUL);
   case3fid(MAD, UMAD, DMAD);
   case3fid(FMA, UMAD, DFMA);
-  case3(DIV, IDIV, UDIV);
+  case4d(DIV, IDIV, UDIV, DDIV);
   case4d(MAX, IMAX, UMAX, DMAX);
   case4d(MIN, IMIN, UMIN, DMIN);
   case2iu(MOD, UMOD);
@@ -1710,10 +1710,7 @@ glsl_to_tgsi_visitor::visit_expression(ir_expression* 
ir, st_src_reg *op)
   emit_asm(ir, TGSI_OPCODE_MUL, result_dst, op[0], op[1]);
   break;
case ir_binop_div:
-  if (result_dst.type == GLSL_TYPE_FLOAT || result_dst.type == 
GLSL_TYPE_DOUBLE)
- assert(!"not reached: should be handled by ir_div_to_mul_rcp");
-  else
- emit_asm(ir, TGSI_OPCODE_DIV, result_dst, op[0], op[1]);
+  emit_asm(ir, TGSI_OPCODE_DIV, result_dst, op[0], op[1]);
   break;
case ir_binop_mod:
   if (result_dst.type == GLSL_TYPE_FLOAT)
@@ -6918,7 +6915,7 @@ st_link_shader(struct gl_context *ctx, struct 
gl_shader_program *prog)
 
   lower_instructions(ir,
  MOD_TO_FLOOR |
- DIV_TO_MUL_RCP |
+ FDIV_TO_MUL_RCP |
  EXP_TO_EXP2 |
  LOG_TO_LOG2 |
  LDEXP_TO_ARITH |

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Mesa (master): r600: implement DDIV

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: e4f8f9a638c1ffb9b76840b088290f11f0f91813
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e4f8f9a638c1ffb9b76840b088290f11f0f91813

Author: Nicolai Hähnle 
Date:   Thu Jan 19 14:44:57 2017 +0100

r600: implement DDIV

Tested-by: Glenn Kennard 
Tested-by: James Harvey 
Cc: 17.0 

---

 src/gallium/drivers/r600/r600_shader.c | 59 ++
 1 file changed, 59 insertions(+)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 5c4bc91..eaabb04 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -4391,6 +4391,63 @@ static int cayman_mul_double_instr(struct 
r600_shader_ctx *ctx)
 }
 
 /*
+ * Emit RECIP_64 + MUL_64 to implement division.
+ */
+static int cayman_ddiv_instr(struct r600_shader_ctx *ctx)
+{
+   struct tgsi_full_instruction *inst = 
&ctx->parse.FullToken.FullInstruction;
+   int r;
+   struct r600_bytecode_alu alu;
+   int t1 = ctx->temp_reg;
+   int k;
+
+   /* Only support one double at a time. This is the same constraint as
+* in DMUL lowering. */
+   assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
+  inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
+
+   k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
+
+   r = cayman_emit_unary_double_raw(ctx->bc, ALU_OP2_RECIP_64, t1, 
&ctx->src[1], false);
+   if (r)
+   return r;
+
+   for (int i = 0; i < 4; i++) {
+   memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+   alu.op = ALU_OP2_MUL_64;
+
+   r600_bytecode_src(&alu.src[0], &ctx->src[0], k * 2 + ((i == 3) 
? 0 : 1));
+
+   alu.src[1].sel = t1;
+   alu.src[1].chan = (i == 3) ? 0 : 1;
+
+   alu.dst.sel = t1;
+   alu.dst.chan = i;
+   alu.dst.write = 1;
+   if (i == 3)
+   alu.last = 1;
+   r = r600_bytecode_add_alu(ctx->bc, &alu);
+   if (r)
+   return r;
+   }
+
+   for (int i = 0; i < 2; i++) {
+   memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+   alu.op = ALU_OP1_MOV;
+   alu.src[0].sel = t1;
+   alu.src[0].chan = i;
+   tgsi_dst(ctx, &inst->Dst[0], k * 2 + i, &alu.dst);
+   alu.dst.write = 1;
+   if (i == 1)
+   alu.last = 1;
+   r = r600_bytecode_add_alu(ctx->bc, &alu);
+   if (r)
+   return r;
+   }
+   return 0;
+}
+
+/*
  * r600 - trunc to -PI..PI range
  * r700 - normalize by dividing by 2PI
  * see fdo bug 27901
@@ -9400,6 +9457,7 @@ static const struct r600_shader_tgsi_instruction 
eg_shader_tgsi_instruction[] =
[TGSI_OPCODE_DNEG]  = { ALU_OP2_ADD_64, tgsi_dneg},
[TGSI_OPCODE_DADD]  = { ALU_OP2_ADD_64, tgsi_op2_64},
[TGSI_OPCODE_DMUL]  = { ALU_OP2_MUL_64, cayman_mul_double_instr},
+   [TGSI_OPCODE_DDIV]  = { 0, cayman_ddiv_instr },
[TGSI_OPCODE_DMAX]  = { ALU_OP2_MAX_64, tgsi_op2_64},
[TGSI_OPCODE_DMIN]  = { ALU_OP2_MIN_64, tgsi_op2_64},
[TGSI_OPCODE_DSLT]  = { ALU_OP2_SETGT_64, 
tgsi_op2_64_single_dest_s},
@@ -9622,6 +9680,7 @@ static const struct r600_shader_tgsi_instruction 
cm_shader_tgsi_instruction[] =
[TGSI_OPCODE_DNEG]  = { ALU_OP2_ADD_64, tgsi_dneg},
[TGSI_OPCODE_DADD]  = { ALU_OP2_ADD_64, tgsi_op2_64},
[TGSI_OPCODE_DMUL]  = { ALU_OP2_MUL_64, cayman_mul_double_instr},
+   [TGSI_OPCODE_DDIV]  = { 0, cayman_ddiv_instr },
[TGSI_OPCODE_DMAX]  = { ALU_OP2_MAX_64, tgsi_op2_64},
[TGSI_OPCODE_DMIN]  = { ALU_OP2_MIN_64, tgsi_op2_64},
[TGSI_OPCODE_DSLT]  = { ALU_OP2_SETGT_64, 
tgsi_op2_64_single_dest_s},

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Mesa (master): r600: double multiply can handle only one multiply at a time

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 76b02d2fe1df5351f67f53d07b37952043f0a84c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=76b02d2fe1df5351f67f53d07b37952043f0a84c

Author: Nicolai Hähnle 
Date:   Thu Jan 19 14:38:54 2017 +0100

r600: double multiply can handle only one multiply at a time

It seems clear that trying to multiply two pairs of doubles would result
in the temporary register getting overwritten by the second pair. So
make the code more explicit.

Tested-by: Glenn Kennard 
Tested-by: James Harvey 
Cc: 17.0 

---

 src/gallium/drivers/r600/r600_shader.c | 36 ++
 1 file changed, 19 insertions(+), 17 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index ebe2744..7d1452a 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -4326,25 +4326,27 @@ static int cayman_mul_double_instr(struct 
r600_shader_ctx *ctx)
int lasti = tgsi_last_instruction(inst->Dst[0].Register.WriteMask);
int t1 = ctx->temp_reg;
 
-   for (k = 0; k < 2; k++) {
-   if (!(inst->Dst[0].Register.WriteMask & (0x3 << (k * 2
-   continue;
+   /* t1 would get overwritten below if we actually tried to
+* multiply two pairs of doubles at a time. */
+   assert(inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ||
+  inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_ZW);
 
-   for (i = 0; i < 4; i++) {
-   memset(&alu, 0, sizeof(struct r600_bytecode_alu));
-   alu.op = ctx->inst_info->op;
-   for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
-   r600_bytecode_src(&alu.src[j], &ctx->src[j], k 
* 2 + ((i == 3) ? 0 : 1));
-   }
-   alu.dst.sel = t1;
-   alu.dst.chan = i;
-   alu.dst.write = 1;
-   if (i == 3)
-   alu.last = 1;
-   r = r600_bytecode_add_alu(ctx->bc, &alu);
-   if (r)
-   return r;
+   k = inst->Dst[0].Register.WriteMask == TGSI_WRITEMASK_XY ? 0 : 1;
+
+   for (i = 0; i < 4; i++) {
+   memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+   alu.op = ctx->inst_info->op;
+   for (j = 0; j < inst->Instruction.NumSrcRegs; j++) {
+   r600_bytecode_src(&alu.src[j], &ctx->src[j], k * 2 + 
((i == 3) ? 0 : 1));
}
+   alu.dst.sel = t1;
+   alu.dst.chan = i;
+   alu.dst.write = 1;
+   if (i == 3)
+   alu.last = 1;
+   r = r600_bytecode_add_alu(ctx->bc, &alu);
+   if (r)
+   return r;
}
 
for (i = 0; i <= lasti; i++) {

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Mesa (master): drirc: remove spurious tabs

[Nicolai Hähnle]

Module: Mesa
Branch: master
Commit: 50141e131a7fa1d33f8b6d16db4e128711b1fdf0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=50141e131a7fa1d33f8b6d16db4e128711b1fdf0

Author: Eric Engestrom 
Date:   Thu Jan  5 21:06:35 2017 +

drirc: remove spurious tabs

Signed-off-by: Eric Engestrom 
Reviewed-by: Edward O'Callaghan 
Reviewed-by: Nicolai Hähnle 

---

 src/mesa/drivers/dri/common/drirc | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/common/drirc 
b/src/mesa/drivers/dri/common/drirc
index 798283f..20fd812 100644
--- a/src/mesa/drivers/dri/common/drirc
+++ b/src/mesa/drivers/dri/common/drirc
@@ -28,46 +28,46 @@ TODO: document the other workarounds.
 
 
 
-   
+
 
 
 
 
-   
+
 
 
 
 
 
-   
+
 
 
 
 
 
-   
+
 
 
 
 
 
-   
+
 
 
 
 
 
-   
+
 
 
 
 
-   
+
 
 
 
 
-   
+
 
 
 

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Mesa (master): st/va: make sure that we call begin_frame() only once v2

[Christian König]

Module: Mesa
Branch: master
Commit: 1338d912f52b69f76ef75d1ad313893db77d4da8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1338d912f52b69f76ef75d1ad313893db77d4da8

Author: Christian König 
Date:   Thu Jan 19 13:44:34 2017 +0100

st/va: make sure that we call begin_frame() only once v2

This fixes "st/va: delay calling begin_frame until we have all parameters".

v2: call begin frame after decoder (re)creation as well.

Signed-off-by: Christian König 
Reviewed-by: Nayan Deshmukh 
Tested-by: Andy Furniss 

---

 src/gallium/state_trackers/va/picture.c| 11 ---
 src/gallium/state_trackers/va/va_private.h |  1 +
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index dc7121c..82584ea 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -81,7 +81,7 @@ vlVaBeginPicture(VADriverContextP ctx, VAContextID 
context_id, VASurfaceID rende
}
 
if (context->decoder->entrypoint != PIPE_VIDEO_ENTRYPOINT_ENCODE)
-  context->decoder->begin_frame(context->decoder, context->target, 
&context->desc.base);
+  context->needs_begin_frame = true;
 
return VA_STATUS_SUCCESS;
 }
@@ -178,6 +178,8 @@ handlePictureParameterBuffer(vlVaDriver *drv, vlVaContext 
*context, vlVaBuffer *
 
   if (!context->decoder)
  return VA_STATUS_ERROR_ALLOCATION_FAILED;
+
+  context->needs_begin_frame = true;
}
 
return vaStatus;
@@ -308,8 +310,11 @@ handleVASliceDataBufferType(vlVaContext *context, 
vlVaBuffer *buf)
sizes[num_buffers] = buf->size;
++num_buffers;
 
-   context->decoder->begin_frame(context->decoder, context->target,
-  &context->desc.base);
+   if (context->needs_begin_frame) {
+  context->decoder->begin_frame(context->decoder, context->target,
+ &context->desc.base);
+  context->needs_begin_frame = false;
+   }
context->decoder->decode_bitstream(context->decoder, context->target, 
&context->desc.base,
   num_buffers, (const void * const*)buffers, sizes);
 }
diff --git a/src/gallium/state_trackers/va/va_private.h 
b/src/gallium/state_trackers/va/va_private.h
index 8faec10..0877236 100644
--- a/src/gallium/state_trackers/va/va_private.h
+++ b/src/gallium/state_trackers/va/va_private.h
@@ -261,6 +261,7 @@ typedef struct {
int target_id;
bool first_single_submitted;
int gop_coeff;
+   bool needs_begin_frame;
 } vlVaContext;
 
 typedef struct {

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Mesa (master): dri: allow 16bit R/GR images to be exported via drm buffers

[Ben Widawsky]

Module: Mesa
Branch: master
Commit: 09b140abb532dede5de6b03b1cc3c03852c1c9e9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=09b140abb532dede5de6b03b1cc3c03852c1c9e9

Author: Rainer Hochecker 
Date:   Thu Jan  5 16:58:56 2017 +0100

dri: allow 16bit R/GR images to be exported via drm buffers

This allows eglCreateImageKHR to access P010 surfaces created by vaapi

Signed-off-by: Rainer Hochecker 
Acked-by: Ben Widawky 

---

 include/GL/internal/dri_interface.h  |  4 
 src/egl/drivers/dri2/egl_dri2.c  | 10 ++
 src/mesa/drivers/dri/common/dri_util.c   |  4 
 src/mesa/drivers/dri/i965/intel_screen.c |  6 ++
 4 files changed, 24 insertions(+)

diff --git a/include/GL/internal/dri_interface.h 
b/include/GL/internal/dri_interface.h
index 8922356..598d111 100644
--- a/include/GL/internal/dri_interface.h
+++ b/include/GL/internal/dri_interface.h
@@ -1164,6 +1164,8 @@ struct __DRIdri2ExtensionRec {
 #define __DRI_IMAGE_FORMAT_ARGB2101010  0x100a
 #define __DRI_IMAGE_FORMAT_SARGB8   0x100b
 #define __DRI_IMAGE_FORMAT_ARGB1555 0x100c
+#define __DRI_IMAGE_FORMAT_R16  0x100d
+#define __DRI_IMAGE_FORMAT_GR1616   0x100e
 
 #define __DRI_IMAGE_USE_SHARE  0x0001
 #define __DRI_IMAGE_USE_SCANOUT0x0002
@@ -1192,6 +1194,8 @@ struct __DRIdri2ExtensionRec {
 #define __DRI_IMAGE_FOURCC_R8  0x20203852
 #define __DRI_IMAGE_FOURCC_GR880x38385247
 #define __DRI_IMAGE_FOURCC_ARGB15550x35315241
+#define __DRI_IMAGE_FOURCC_R16 0x20363152
+#define __DRI_IMAGE_FOURCC_GR1616  0x32335247
 #define __DRI_IMAGE_FOURCC_RGB565  0x36314752
 #define __DRI_IMAGE_FOURCC_ARGB0x34325241
 #define __DRI_IMAGE_FOURCC_XRGB0x34325258
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index 63e29fc..94b7c20 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -75,6 +75,14 @@
 #define DRM_FORMAT_GR88  fourcc_code('G', 'R', '8', '8') /* [15:0] G:R 
8:8 little endian */
 #endif
 
+#ifndef DRM_FORMAT_R16
+#define DRM_FORMAT_R16   fourcc_code('R', '1', '6', ' ') /* [15:0] R 
16 little endian */
+#endif
+
+#ifndef DRM_FORMAT_GR1616
+#define DRM_FORMAT_GR1616fourcc_code('G', 'R', '3', '2') /* [31:0] R:G 
16:16 little endian */
+#endif
+
 const __DRIuseInvalidateExtension use_invalidate = {
.base = { __DRI_USE_INVALIDATE, 1 }
 };
@@ -1957,6 +1965,8 @@ dri2_check_dma_buf_format(const _EGLImageAttribs *attrs)
case DRM_FORMAT_R8:
case DRM_FORMAT_RG88:
case DRM_FORMAT_GR88:
+   case DRM_FORMAT_R16:
+   case DRM_FORMAT_GR1616:
case DRM_FORMAT_RGB332:
case DRM_FORMAT_BGR233:
case DRM_FORMAT_XRGB:
diff --git a/src/mesa/drivers/dri/common/dri_util.c 
b/src/mesa/drivers/dri/common/dri_util.c
index 209a42a..f92eee9 100644
--- a/src/mesa/drivers/dri/common/dri_util.c
+++ b/src/mesa/drivers/dri/common/dri_util.c
@@ -881,8 +881,12 @@ driImageFormatToGLFormat(uint32_t image_format)
   return MESA_FORMAT_R8G8B8X8_UNORM;
case __DRI_IMAGE_FORMAT_R8:
   return MESA_FORMAT_R_UNORM8;
+   case __DRI_IMAGE_FORMAT_R16:
+  return MESA_FORMAT_R_UNORM16;
case __DRI_IMAGE_FORMAT_GR88:
   return MESA_FORMAT_R8G8_UNORM;
+   case __DRI_IMAGE_FORMAT_GR1616:
+  return MESA_FORMAT_R16G16_UNORM;
case __DRI_IMAGE_FORMAT_SARGB8:
   return MESA_FORMAT_B8G8R8A8_SRGB;
case __DRI_IMAGE_FORMAT_NONE:
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 6ae211d..5f8 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -239,9 +239,15 @@ static struct intel_image_format intel_image_formats[] = {
{ __DRI_IMAGE_FOURCC_R8, __DRI_IMAGE_COMPONENTS_R, 1,
  { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, } },
 
+   { __DRI_IMAGE_FOURCC_R16, __DRI_IMAGE_COMPONENTS_R, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 1 }, } },
+
{ __DRI_IMAGE_FOURCC_GR88, __DRI_IMAGE_COMPONENTS_RG, 1,
  { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR88, 2 }, } },
 
+   { __DRI_IMAGE_FOURCC_GR1616, __DRI_IMAGE_COMPONENTS_RG, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_GR1616, 2 }, } },
+
{ __DRI_IMAGE_FOURCC_YUV410, __DRI_IMAGE_COMPONENTS_Y_U_V, 3,
  { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 },
{ 1, 2, 2, __DRI_IMAGE_FORMAT_R8, 1 },

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Mesa (master): i965: Use UNUSED to silence unused variable (used in assert ).

[Matt Turner]

Module: Mesa
Branch: master
Commit: d349449a16825abc8336495afabadb2540b5a688
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d349449a16825abc8336495afabadb2540b5a688

Author: Matt Turner 
Date:   Mon Jan 23 10:50:20 2017 -0800

i965: Use UNUSED to silence unused variable (used in assert).

---

 src/mesa/drivers/dri/i965/brw_eu_emit.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index de6a1d9..257757f 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -286,7 +286,7 @@ validate_reg(const struct gen_device_info *devinfo,
* destination horiz stride has to be a word.
*/
   if (reg.type == BRW_REGISTER_TYPE_V) {
- unsigned elem_size = brw_element_size(devinfo, inst, dst);
+ unsigned UNUSED elem_size = brw_element_size(devinfo, inst, dst);
  assert(hstride_for_reg[brw_inst_dst_hstride(devinfo, inst)] *
 elem_size == 2);
   }

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Mesa (master): swr: Align query results allocation

[Tim Rowley]

Module: Mesa
Branch: master
Commit: 00847e4f14dd237dfcdb2c3d15be1325a08ccf5a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=00847e4f14dd237dfcdb2c3d15be1325a08ccf5a

Author: George Kyriazis 
Date:   Wed Jan 18 17:09:08 2017 -0600

swr: Align query results allocation

Some query results struct contents are declared as cache line aligned.
Use aligned malloc, and align the whole struct, to be safe.

Fixes crash when compiling with clang.

CC: 

Reviewed-by: Bruce Cherniak 

---

 src/gallium/drivers/swr/swr_query.cpp | 7 ---
 src/gallium/drivers/swr/swr_query.h   | 2 +-
 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/swr/swr_query.cpp 
b/src/gallium/drivers/swr/swr_query.cpp
index 6eb0781..e097790 100644
--- a/src/gallium/drivers/swr/swr_query.cpp
+++ b/src/gallium/drivers/swr/swr_query.cpp
@@ -29,7 +29,7 @@
 #include "swr_query.h"
 #include "swr_screen.h"
 #include "swr_state.h"
-
+#include "common/os.h"
 
 static struct swr_query *
 swr_query(struct pipe_query *p)
@@ -45,7 +45,8 @@ swr_create_query(struct pipe_context *pipe, unsigned type, 
unsigned index)
assert(type < PIPE_QUERY_TYPES);
assert(index < MAX_SO_STREAMS);
 
-   pq = CALLOC_STRUCT(swr_query);
+   pq = (struct swr_query *) AlignedMalloc(sizeof(struct swr_query), 64);
+   memset(pq, 0, sizeof(*pq));
 
if (pq) {
   pq->type = type;
@@ -67,7 +68,7 @@ swr_destroy_query(struct pipe_context *pipe, struct 
pipe_query *q)
   swr_fence_reference(pipe->screen, &pq->fence, NULL);
}
 
-   FREE(pq);
+   AlignedFree(pq);
 }
 
 
diff --git a/src/gallium/drivers/swr/swr_query.h 
b/src/gallium/drivers/swr/swr_query.h
index c5160ce..1c736e4 100644
--- a/src/gallium/drivers/swr/swr_query.h
+++ b/src/gallium/drivers/swr/swr_query.h
@@ -34,7 +34,7 @@ struct swr_query_result {
uint64_t timestamp_end;
 };
 
-struct swr_query {
+OSALIGNLINE(struct) swr_query {
unsigned type; /* PIPE_QUERY_* */
unsigned index;
 

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Mesa (master): swr: Prune empty nodes in CalculateProcessorTopology.

[Tim Rowley]

Module: Mesa
Branch: master
Commit: b829206b0739925501bcc68233437d6d03b79795
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b829206b0739925501bcc68233437d6d03b79795

Author: Bruce Cherniak 
Date:   Thu Jan 19 15:44:52 2017 -0600

swr: Prune empty nodes in CalculateProcessorTopology.

CalculateProcessorTopology tries to figure out system topology by
parsing /proc/cpuinfo to determine the number of threads, cores, and
NUMA nodes.  There are some architectures where the "physical id" begins
with 1 rather than 0, which was creating and empty "0" node and causing a
crash in CreateThreadPool.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97102
Reviewed-By: George Kyriazis 
CC: 

---

 src/gallium/drivers/swr/rasterizer/core/threads.cpp | 9 +
 1 file changed, 9 insertions(+)

diff --git a/src/gallium/drivers/swr/rasterizer/core/threads.cpp 
b/src/gallium/drivers/swr/rasterizer/core/threads.cpp
index ee12612..f1c3030 100644
--- a/src/gallium/drivers/swr/rasterizer/core/threads.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/threads.cpp
@@ -217,6 +217,15 @@ void CalculateProcessorTopology(CPUNumaNodes& out_nodes, 
uint32_t& out_numThread
 out_numThreadsPerProcGroup++;
 }
 
+/* Prune empty numa nodes */
+for (auto it = out_nodes.begin(); it != out_nodes.end(); ) {
+   if ((*it).cores.size() == 0)
+  it = out_nodes.erase(it);
+   else
+  ++it;
+}
+
+/* Prune empty core nodes */
 for (uint32_t node = 0; node < out_nodes.size(); node++) {
 auto& numaNode = out_nodes[node];
 auto it = numaNode.cores.begin();

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Mesa (master): gallium/radeon: add HUD queries for monitoring some hw blocks

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: aa2ace8e4975419e723f78d624087637c57ef2fa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aa2ace8e4975419e723f78d624087637c57ef2fa

Author: Samuel Pitoiset 
Date:   Fri Jan 20 19:21:12 2017 +0100

gallium/radeon: add HUD queries for monitoring some hw blocks

It's also possible to monitor them via performance counters but
the hardware can only use two counters simultaneously. It seems
easier to re-use the existing code which reads from MMIO instead
of writing a multi-pass approach.

v2: - add new lines after ':'

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeon/r600_gpu_load.c| 48 +++
 src/gallium/drivers/radeon/r600_pipe_common.h | 12 +++
 src/gallium/drivers/radeon/r600_query.c   | 39 +-
 src/gallium/drivers/radeon/r600_query.h   | 12 +++
 4 files changed, 110 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/r600_gpu_load.c 
b/src/gallium/drivers/radeon/r600_gpu_load.c
index 62f5d03..775ac7a 100644
--- a/src/gallium/drivers/radeon/r600_gpu_load.c
+++ b/src/gallium/drivers/radeon/r600_gpu_load.c
@@ -43,7 +43,19 @@
 #define SAMPLES_PER_SEC 1
 
 #define GRBM_STATUS0x8010
+#define TA_BUSY(x) (((x) >> 14) & 0x1)
+#define GDS_BUSY(x)(((x) >> 15) & 0x1)
+#define VGT_BUSY(x)(((x) >> 17) & 0x1)
+#define IA_BUSY(x) (((x) >> 19) & 0x1)
+#define SX_BUSY(x) (((x) >> 20) & 0x1)
+#define WD_BUSY(x) (((x) >> 21) & 0x1)
 #define SPI_BUSY(x)(((x) >> 22) & 0x1)
+#define BCI_BUSY(x)(((x) >> 23) & 0x1)
+#define SC_BUSY(x) (((x) >> 24) & 0x1)
+#define PA_BUSY(x) (((x) >> 25) & 0x1)
+#define DB_BUSY(x) (((x) >> 26) & 0x1)
+#define CP_BUSY(x) (((x) >> 29) & 0x1)
+#define CB_BUSY(x) (((x) >> 30) & 0x1)
 #define GUI_ACTIVE(x)  (((x) >> 31) & 0x1)
 
 #define UPDATE_COUNTER(field, mask)\
@@ -59,7 +71,19 @@ static void r600_update_grbm_counters(struct 
r600_common_screen *rscreen,
 
rscreen->ws->read_registers(rscreen->ws, GRBM_STATUS, 1, &value);
 
+   UPDATE_COUNTER(ta, TA_BUSY);
+   UPDATE_COUNTER(gds, GDS_BUSY);
+   UPDATE_COUNTER(vgt, VGT_BUSY);
+   UPDATE_COUNTER(ia, IA_BUSY);
+   UPDATE_COUNTER(sx, SX_BUSY);
+   UPDATE_COUNTER(wd, WD_BUSY);
UPDATE_COUNTER(spi, SPI_BUSY);
+   UPDATE_COUNTER(bci, BCI_BUSY);
+   UPDATE_COUNTER(sc, SC_BUSY);
+   UPDATE_COUNTER(pa, PA_BUSY);
+   UPDATE_COUNTER(db, DB_BUSY);
+   UPDATE_COUNTER(cp, CP_BUSY);
+   UPDATE_COUNTER(cb, CB_BUSY);
UPDATE_COUNTER(gui, GUI_ACTIVE);
 }
 
@@ -158,6 +182,30 @@ static unsigned busy_index_from_type(struct 
r600_common_screen *rscreen,
return BUSY_INDEX(rscreen, gui);
case R600_QUERY_GPU_SHADERS_BUSY:
return BUSY_INDEX(rscreen, spi);
+   case R600_QUERY_GPU_TA_BUSY:
+   return BUSY_INDEX(rscreen, ta);
+   case R600_QUERY_GPU_GDS_BUSY:
+   return BUSY_INDEX(rscreen, gds);
+   case R600_QUERY_GPU_VGT_BUSY:
+   return BUSY_INDEX(rscreen, vgt);
+   case R600_QUERY_GPU_IA_BUSY:
+   return BUSY_INDEX(rscreen, ia);
+   case R600_QUERY_GPU_SX_BUSY:
+   return BUSY_INDEX(rscreen, sx);
+   case R600_QUERY_GPU_WD_BUSY:
+   return BUSY_INDEX(rscreen, wd);
+   case R600_QUERY_GPU_BCI_BUSY:
+   return BUSY_INDEX(rscreen, bci);
+   case R600_QUERY_GPU_SC_BUSY:
+   return BUSY_INDEX(rscreen, sc);
+   case R600_QUERY_GPU_PA_BUSY:
+   return BUSY_INDEX(rscreen, pa);
+   case R600_QUERY_GPU_DB_BUSY:
+   return BUSY_INDEX(rscreen, db);
+   case R600_QUERY_GPU_CP_BUSY:
+   return BUSY_INDEX(rscreen, cp);
+   case R600_QUERY_GPU_CB_BUSY:
+   return BUSY_INDEX(rscreen, cb);
default:
unreachable("query type does not correspond to grbm id");
}
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index e340e6f..afb1385 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -361,6 +361,18 @@ union r600_grbm_counters {
struct {
struct r600_grbm_counter spi;
struct r600_grbm_counter gui;
+   struct r600_grbm_counter ta;
+   struct r600_grbm_counter gds;
+   struct r600_grbm_counter vgt;
+   struct r600_grbm_counter ia;
+   struct r600_grbm_counter sx;
+   struct r600_grbm_counter wd;
+   struct r600_grbm_counter bci;
+   struct r600_grbm_counter sc;
+   struct r600_grbm_counter pa;
+   struct r600_grbm_counter db;
+ 

Mesa (master): gallium/radeon: refactor the GRBM counters path

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: a704f1924765fb1cac61cdb9d6e84ad2cb5c7f9c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a704f1924765fb1cac61cdb9d6e84ad2cb5c7f9c

Author: Samuel Pitoiset 
Date:   Fri Jan 20 18:15:50 2017 +0100

gallium/radeon: refactor the GRBM counters path

This will allow to expose more queries in order to know which
blocks are busy/idle.

v2: - add new lines after ':'

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeon/r600_gpu_load.c| 58 +++
 src/gallium/drivers/radeon/r600_pipe_common.h | 18 +
 src/gallium/drivers/radeon/r600_query.c   | 14 +++
 3 files changed, 47 insertions(+), 43 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_gpu_load.c 
b/src/gallium/drivers/radeon/r600_gpu_load.c
index e3488b3..62f5d03 100644
--- a/src/gallium/drivers/radeon/r600_gpu_load.c
+++ b/src/gallium/drivers/radeon/r600_gpu_load.c
@@ -35,6 +35,7 @@
  */
 
 #include "r600_pipe_common.h"
+#include "r600_query.h"
 #include "os/os_time.h"
 
 /* For good accuracy at 1000 fps or lower. This will be inaccurate for higher
@@ -45,6 +46,12 @@
 #define SPI_BUSY(x)(((x) >> 22) & 0x1)
 #define GUI_ACTIVE(x)  (((x) >> 31) & 0x1)
 
+#define UPDATE_COUNTER(field, mask)\
+   if (mask(value))\
+   p_atomic_inc(&counters->named.field.busy);  \
+   else\
+   p_atomic_inc(&counters->named.field.idle);
+
 static void r600_update_grbm_counters(struct r600_common_screen *rscreen,
  union r600_grbm_counters *counters)
 {
@@ -52,15 +59,8 @@ static void r600_update_grbm_counters(struct 
r600_common_screen *rscreen,
 
rscreen->ws->read_registers(rscreen->ws, GRBM_STATUS, 1, &value);
 
-   if (SPI_BUSY(value))
-   p_atomic_inc(&counters->named.spi_busy);
-   else
-   p_atomic_inc(&counters->named.spi_idle);
-
-   if (GUI_ACTIVE(value))
-   p_atomic_inc(&counters->named.gui_busy);
-   else
-   p_atomic_inc(&counters->named.gui_idle);
+   UPDATE_COUNTER(spi, SPI_BUSY);
+   UPDATE_COUNTER(gui, GUI_ACTIVE);
 }
 
 static PIPE_THREAD_ROUTINE(r600_gpu_load_thread, param)
@@ -104,8 +104,8 @@ void r600_gpu_load_kill_thread(struct r600_common_screen 
*rscreen)
rscreen->gpu_load_thread = 0;
 }
 
-static uint64_t r600_read_counter(struct r600_common_screen *rscreen,
- unsigned busy_index)
+static uint64_t r600_read_grbm_counter(struct r600_common_screen *rscreen,
+  unsigned busy_index)
 {
/* Start the thread if needed. */
if (!rscreen->gpu_load_thread) {
@@ -123,10 +123,10 @@ static uint64_t r600_read_counter(struct 
r600_common_screen *rscreen,
return busy | ((uint64_t)idle << 32);
 }
 
-static unsigned r600_end_counter(struct r600_common_screen *rscreen,
-uint64_t begin, unsigned busy_index)
+static unsigned r600_end_grbm_counter(struct r600_common_screen *rscreen,
+ uint64_t begin, unsigned busy_index)
 {
-   uint64_t end = r600_read_counter(rscreen, busy_index);
+   uint64_t end = r600_read_grbm_counter(rscreen, busy_index);
unsigned busy = (end & 0x) - (begin & 0x);
unsigned idle = (end >> 32) - (begin >> 32);
 
@@ -147,25 +147,31 @@ static unsigned r600_end_counter(struct 
r600_common_screen *rscreen,
}
 }
 
-#define BUSY_INDEX(rscreen, field) (&rscreen->grbm_counters.named.field##_busy 
- \
+#define BUSY_INDEX(rscreen, field) (&rscreen->grbm_counters.named.field.busy - 
\
rscreen->grbm_counters.array)
 
-uint64_t r600_begin_counter_spi(struct r600_common_screen *rscreen)
-{
-   return r600_read_counter(rscreen, BUSY_INDEX(rscreen, spi));
-}
-
-unsigned r600_end_counter_spi(struct r600_common_screen *rscreen, uint64_t 
begin)
+static unsigned busy_index_from_type(struct r600_common_screen *rscreen,
+unsigned type)
 {
-   return r600_end_counter(rscreen, begin, BUSY_INDEX(rscreen, spi));
+   switch (type) {
+   case R600_QUERY_GPU_LOAD:
+   return BUSY_INDEX(rscreen, gui);
+   case R600_QUERY_GPU_SHADERS_BUSY:
+   return BUSY_INDEX(rscreen, spi);
+   default:
+   unreachable("query type does not correspond to grbm id");
+   }
 }
 
-uint64_t r600_begin_counter_gui(struct r600_common_screen *rscreen)
+uint64_t r600_begin_counter(struct r600_common_screen *rscreen, unsigned type)
 {
-   return r600_read_counter(rscreen, BUSY_INDEX(rscreen, gui));
+   unsigned busy_index = busy_index_from_type(rscreen, type);
+   return r600_read_grbm_counter(rscreen, busy_index);
 }
 
-unsigned r600_end_co

Mesa (master): radv: don' t resubmit the same cs over and over while tracing

[Bas Nieuwenhuizen]

Module: Mesa
Branch: master
Commit: f65b3641c3233f1697b96ea8126b578dae6de4f1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f65b3641c3233f1697b96ea8126b578dae6de4f1

Author: Grazvydas Ignotas 
Date:   Mon Jan 23 23:16:42 2017 +0200

radv: don't resubmit the same cs over and over while tracing

Fixes: 97dfff54 ("radv: Dump command buffer on hang.")
Signed-off-by: Grazvydas Ignotas 
Reviewed-by: Bas Nieuwenhuizen 
CC: 

---

 src/amd/vulkan/radv_device.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 9371536..4aa6af2 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -989,8 +989,7 @@ VkResult radv_QueueSubmit(
if (queue->device->trace_bo)
*queue->device->trace_id_ptr = 0;
 
-   ret = queue->device->ws->cs_submit(ctx, 
queue->queue_idx, cs_array,
-   
pSubmits[i].commandBufferCount,
+   ret = queue->device->ws->cs_submit(ctx, 
queue->queue_idx, cs_array + j, advance,
(struct 
radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
b ? 
pSubmits[i].waitSemaphoreCount : 0,
(struct 
radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,

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Mesa (master): vulkan: import latest registry for 1.0.39 extensions.

[Dave Airlie]

Module: Mesa
Branch: master
Commit: dcfcb3047c96e7ab0bc6dbb133fa69e9225c1400
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dcfcb3047c96e7ab0bc6dbb133fa69e9225c1400

Author: Dave Airlie 
Date:   Tue Jan 24 08:05:39 2017 +1000

vulkan: import latest registry for 1.0.39 extensions.

Acked-by: Jason Ekstrand 
Signed-off-by: Dave Airlie 

---

 src/vulkan/registry/vk.xml | 450 -
 1 file changed, 408 insertions(+), 42 deletions(-)

Diff:   
http://cgit.freedesktop.org/mesa/mesa/diff/?id=dcfcb3047c96e7ab0bc6dbb133fa69e9225c1400
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Mesa (master): vulkan: bump vulkan.h to 1.0.39 version

[Dave Airlie]

Module: Mesa
Branch: master
Commit: e38bee34bf047a683ceea54e44e5d596af86160d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e38bee34bf047a683ceea54e44e5d596af86160d

Author: Dave Airlie 
Date:   Tue Jan 24 07:55:51 2017 +1000

vulkan: bump vulkan.h to 1.0.39 version

This introduces a bunch of new extension defines.

Acked-by: Jason Ekstrand 
Signed-off-by: Dave Airlie 

---

 include/vulkan/vulkan.h | 367 +++-
 1 file changed, 365 insertions(+), 2 deletions(-)

diff --git a/include/vulkan/vulkan.h b/include/vulkan/vulkan.h
index f24a0a2..81dedf7 100644
--- a/include/vulkan/vulkan.h
+++ b/include/vulkan/vulkan.h
@@ -6,7 +6,7 @@ extern "C" {
 #endif
 
 /*
-** Copyright (c) 2015-2016 The Khronos Group Inc.
+** Copyright (c) 2015-2017 The Khronos Group Inc.
 **
 ** Licensed under the Apache License, Version 2.0 (the "License");
 ** you may not use this file except in compliance with the License.
@@ -43,7 +43,7 @@ extern "C" {
 #define VK_VERSION_MINOR(version) (((uint32_t)(version) >> 12) & 0x3ff)
 #define VK_VERSION_PATCH(version) ((uint32_t)(version) & 0xfff)
 // Version of this file
-#define VK_HEADER_VERSION 38
+#define VK_HEADER_VERSION 39
 
 
 #define VK_NULL_HANDLE 0
@@ -145,6 +145,7 @@ typedef enum VkResult {
 VK_ERROR_INCOMPATIBLE_DISPLAY_KHR = -103001,
 VK_ERROR_VALIDATION_FAILED_EXT = -111001,
 VK_ERROR_INVALID_SHADER_NV = -112000,
+VK_ERROR_OUT_OF_POOL_MEMORY_KHR = -169000,
 VK_RESULT_BEGIN_RANGE = VK_ERROR_FRAGMENTED_POOL,
 VK_RESULT_END_RANGE = VK_INCOMPLETE,
 VK_RESULT_RANGE_SIZE = (VK_INCOMPLETE - VK_ERROR_FRAGMENTED_POOL + 1),
@@ -225,13 +226,28 @@ typedef enum VkStructureType {
 VK_STRUCTURE_TYPE_IMPORT_MEMORY_WIN32_HANDLE_INFO_NV = 157000,
 VK_STRUCTURE_TYPE_EXPORT_MEMORY_WIN32_HANDLE_INFO_NV = 157001,
 VK_STRUCTURE_TYPE_WIN32_KEYED_MUTEX_ACQUIRE_RELEASE_INFO_NV = 158000,
+VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2_KHR = 159000,
+VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROPERTIES_2_KHR = 159001,
+VK_STRUCTURE_TYPE_FORMAT_PROPERTIES_2_KHR = 159002,
+VK_STRUCTURE_TYPE_IMAGE_FORMAT_PROPERTIES_2_KHR = 159003,
+VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_FORMAT_INFO_2_KHR = 159004,
+VK_STRUCTURE_TYPE_QUEUE_FAMILY_PROPERTIES_2_KHR = 159005,
+VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PROPERTIES_2_KHR = 159006,
+VK_STRUCTURE_TYPE_SPARSE_IMAGE_FORMAT_PROPERTIES_2_KHR = 159007,
+VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SPARSE_IMAGE_FORMAT_INFO_2_KHR = 
159008,
 VK_STRUCTURE_TYPE_VALIDATION_FLAGS_EXT = 161000,
+VK_STRUCTURE_TYPE_VI_SURFACE_CREATE_INFO_NN = 162000,
 VK_STRUCTURE_TYPE_OBJECT_TABLE_CREATE_INFO_NVX = 186000,
 VK_STRUCTURE_TYPE_INDIRECT_COMMANDS_LAYOUT_CREATE_INFO_NVX = 186001,
 VK_STRUCTURE_TYPE_CMD_PROCESS_COMMANDS_INFO_NVX = 186002,
 VK_STRUCTURE_TYPE_CMD_RESERVE_SPACE_FOR_COMMANDS_INFO_NVX = 186003,
 VK_STRUCTURE_TYPE_DEVICE_GENERATED_COMMANDS_LIMITS_NVX = 186004,
 VK_STRUCTURE_TYPE_DEVICE_GENERATED_COMMANDS_FEATURES_NVX = 186005,
+VK_STRUCTURE_TYPE_SURFACE_CAPABILITIES2_EXT = 19,
+VK_STRUCTURE_TYPE_DISPLAY_POWER_INFO_EXT = 191000,
+VK_STRUCTURE_TYPE_DEVICE_EVENT_INFO_EXT = 191001,
+VK_STRUCTURE_TYPE_DISPLAY_EVENT_INFO_EXT = 191002,
+VK_STRUCTURE_TYPE_SWAPCHAIN_COUNTER_CREATE_INFO_EXT = 191003,
 VK_STRUCTURE_TYPE_BEGIN_RANGE = VK_STRUCTURE_TYPE_APPLICATION_INFO,
 VK_STRUCTURE_TYPE_END_RANGE = VK_STRUCTURE_TYPE_LOADER_DEVICE_CREATE_INFO,
 VK_STRUCTURE_TYPE_RANGE_SIZE = 
(VK_STRUCTURE_TYPE_LOADER_DEVICE_CREATE_INFO - 
VK_STRUCTURE_TYPE_APPLICATION_INFO + 1),
@@ -840,6 +856,8 @@ typedef enum VkFormatFeatureFlagBits {
 VK_FORMAT_FEATURE_BLIT_DST_BIT = 0x0800,
 VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_LINEAR_BIT = 0x1000,
 VK_FORMAT_FEATURE_SAMPLED_IMAGE_FILTER_CUBIC_BIT_IMG = 0x2000,
+VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR = 0x4000,
+VK_FORMAT_FEATURE_TRANSFER_DST_BIT_KHR = 0x8000,
 VK_FORMAT_FEATURE_FLAG_BITS_MAX_ENUM = 0x7FFF
 } VkFormatFeatureFlagBits;
 typedef VkFlags VkFormatFeatureFlags;
@@ -863,6 +881,7 @@ typedef enum VkImageCreateFlagBits {
 VK_IMAGE_CREATE_SPARSE_ALIASED_BIT = 0x0004,
 VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT = 0x0008,
 VK_IMAGE_CREATE_CUBE_COMPATIBLE_BIT = 0x0010,
+VK_IMAGE_CREATE_2D_ARRAY_COMPATIBLE_BIT_KHR = 0x0020,
 VK_IMAGE_CREATE_FLAG_BITS_MAX_ENUM = 0x7FFF
 } VkImageCreateFlagBits;
 typedef VkFlags VkImageCreateFlags;
@@ -3206,6 +3225,18 @@ VK_DEFINE_NON_DISPATCHABLE_HANDLE(VkSurfaceKHR)
 
 typedef enum VkColorSpaceKHR {
 VK_COLOR_SPACE_SRGB_NONLINEAR_KHR = 0,
+VK_COLOR_SPACE_DISPLAY_P3_LINEAR_EXT = 1000104001,
+VK_COLOR_SPACE_DISPLAY_P3_NONLINEAR_EXT = 1000104002,
+VK_COLOR_SPACE_SCRGB_LINEAR_EXT = 1000104003,
+VK_COLOR_SPACE_SCRGB_NONLINEAR_EXT = 1000104004,
+   

Mesa (master): winsys/amdgpu: drop all IBs if at least one was rejected within the context

[Marek Olšák]

Module: Mesa
Branch: master
Commit: e248390e93d025472d55b89252216895bc895a74
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e248390e93d025472d55b89252216895bc895a74

Author: Marek Olšák 
Date:   Thu Jan 19 20:44:49 2017 +0100

winsys/amdgpu: drop all IBs if at least one was rejected within the context

The corruption is inevitable and hangs are possible too.

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index d63ff36..0bc4ce9 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -1039,11 +1039,17 @@ void amdgpu_cs_submit_ib(void *job, int thread_index)
   goto cleanup;
}
 
-   r = amdgpu_cs_submit(acs->ctx->ctx, 0, &cs->request, 1);
+   if (acs->ctx->num_rejected_cs)
+  r = -ECANCELED;
+   else
+  r = amdgpu_cs_submit(acs->ctx->ctx, 0, &cs->request, 1);
+
cs->error_code = r;
if (r) {
   if (r == -ENOMEM)
  fprintf(stderr, "amdgpu: Not enough memory for command 
submission.\n");
+  else if (r == -ECANCELED)
+ fprintf(stderr, "amdgpu: The CS has been cancelled because the 
context is lost.\n");
   else
  fprintf(stderr, "amdgpu: The CS has been rejected, "
  "see dmesg for more information (%i).\n", r);

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Mesa (master): winsys/amdgpu: report a rejected IB as a lost context

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 18408008609df9007dc40512f00c5700167c5887
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=18408008609df9007dc40512f00c5700167c5887

Author: Marek Olšák 
Date:   Thu Jan 19 20:32:28 2017 +0100

winsys/amdgpu: report a rejected IB as a lost context

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 11 +++
 src/gallium/winsys/amdgpu/drm/amdgpu_cs.h |  2 ++
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h |  1 +
 3 files changed, 14 insertions(+)

diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 87246f7..d63ff36 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -178,6 +178,7 @@ static struct radeon_winsys_ctx *amdgpu_ctx_create(struct 
radeon_winsys *ws)
 
ctx->ws = amdgpu_winsys(ws);
ctx->refcount = 1;
+   ctx->initial_num_total_rejected_cs = ctx->ws->num_total_rejected_cs;
 
r = amdgpu_cs_ctx_create(ctx->ws->dev, &ctx->ctx);
if (r) {
@@ -227,6 +228,13 @@ amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx 
*rwctx)
uint32_t result, hangs;
int r;
 
+   /* Return a failure due to a rejected command submission. */
+   if (ctx->ws->num_total_rejected_cs > ctx->initial_num_total_rejected_cs) {
+  return ctx->num_rejected_cs ? PIPE_GUILTY_CONTEXT_RESET :
+PIPE_INNOCENT_CONTEXT_RESET;
+   }
+
+   /* Return a failure due to a GPU hang. */
r = amdgpu_cs_query_reset_state(ctx->ctx, &result, &hangs);
if (r) {
   fprintf(stderr, "amdgpu: amdgpu_cs_query_reset_state failed. (%i)\n", r);
@@ -1041,6 +1049,9 @@ void amdgpu_cs_submit_ib(void *job, int thread_index)
  "see dmesg for more information (%i).\n", r);
 
   amdgpu_fence_signalled(cs->fence);
+
+  acs->ctx->num_rejected_cs++;
+  ws->num_total_rejected_cs++;
} else {
   /* Success. */
   uint64_t *user_fence = NULL;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h 
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
index 5f181a5..90b9e83 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.h
@@ -41,6 +41,8 @@ struct amdgpu_ctx {
amdgpu_bo_handle user_fence_bo;
uint64_t *user_fence_cpu_address_base;
int refcount;
+   unsigned initial_num_total_rejected_cs;
+   unsigned num_rejected_cs;
 };
 
 struct amdgpu_cs_buffer {
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h 
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
index 2a7900a..c56c342 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
@@ -55,6 +55,7 @@ struct amdgpu_winsys {
pipe_mutex bo_fence_lock;
 
int num_cs; /* The number of command streams created. */
+   unsigned num_total_rejected_cs;
uint32_t next_bo_unique_id;
uint64_t allocated_vram;
uint64_t allocated_gtt;

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Mesa (master): radeonsi: don't declare LDS in TES

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 5d3dd70cab1d60efc70db5e1448c88d125eb6779
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d3dd70cab1d60efc70db5e1448c88d125eb6779

Author: Marek Olšák 
Date:   Fri Jan 20 00:08:35 2017 +0100

radeonsi: don't declare LDS in TES

not used since we started using the offchip tess ring

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_shader.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 10f40a9..5ca974e 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -5863,8 +5863,7 @@ static void create_function(struct si_shader_context *ctx)
LOCAL_ADDR_SPACE);
 
if ((ctx->type == PIPE_SHADER_VERTEX && shader->key.as_ls) ||
-   ctx->type == PIPE_SHADER_TESS_CTRL ||
-   ctx->type == PIPE_SHADER_TESS_EVAL)
+   ctx->type == PIPE_SHADER_TESS_CTRL)
declare_tess_lds(ctx);
 }
 

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Mesa (master): radeonsi: always set the TCL1_ACTION_ENA when invalidating L2

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 573bf0940a08e18a511e338de478f30fd95a1590
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=573bf0940a08e18a511e338de478f30fd95a1590

Author: Marek Olšák 
Date:   Fri Jan 20 01:13:39 2017 +0100

radeonsi: always set the TCL1_ACTION_ENA when invalidating L2

Some CIK-VI docs say this is the default behavior on SI. That doesn't
answer whether it's also the default behavior on CIK-VI.

Cc: 17.0 13.0 
Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_state_draw.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c 
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 837c025..d296874 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -850,11 +850,12 @@ void si_emit_cache_flush(struct si_context *sctx)
if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2 ||
(rctx->chip_class <= CIK &&
 (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
-   /* Invalidate L1 & L2. (L1 is always invalidated)
+   /* Invalidate L1 & L2. (L1 is always invalidated on SI)
 * WB must be set on VI+ when TC_ACTION is set.
 */
si_emit_surface_sync(rctx, cp_coher_cntl |
 S_0085F0_TC_ACTION_ENA(1) |
+S_0085F0_TCL1_ACTION_ENA(1) |
 S_0301F0_TC_WB_ACTION_ENA(rctx->chip_class 
>= VI));
cp_coher_cntl = 0;
sctx->b.num_L2_invalidates++;

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Mesa (master): radeonsi: preload PS inputs only if KILL is used

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 59c5da40ed2c6c56e29b562c2ee2c8705f28738b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=59c5da40ed2c6c56e29b562c2ee2c8705f28738b

Author: Marek Olšák 
Date:   Thu Jan 19 13:58:50 2017 +0100

radeonsi: preload PS inputs only if KILL is used

so that most shaders can get lower VGPR usage thanks to lazy input loading.
I think this is a more accurate constraint that prevents the black transitions
in Witcher 2.

Affected shaders (7758):
Max Waves: 57437 -> 58231 (1.38 %)

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c 
b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
index 8d19a4e..4f355e5 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
@@ -637,11 +637,15 @@ store_value_to_array(struct lp_build_tgsi_context 
*bld_base,
 
 /* If this is true, preload FS inputs at the beginning of shaders. Otherwise,
  * reload them at each use. This must be true if the shader is using
- * derivatives, because all inputs should be loaded in the WQM mode.
+ * derivatives and KILL, because KILL can leave the WQM and then a lazy
+ * input load isn't in the WQM anymore.
  */
 static bool si_preload_fs_inputs(struct si_shader_context *ctx)
 {
-   return ctx->shader->selector->info.uses_derivatives;
+   struct si_shader_selector *sel = ctx->shader->selector;
+
+   return sel->info.uses_derivatives &&
+  sel->info.uses_kill;
 }
 
 static LLVMValueRef

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Mesa (master): gallium/radeon: adjust the rule for using the LINEAR_ALIGNED layout

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 7b32ae4df5bc19c378598d6a950a6019fa64ece6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b32ae4df5bc19c378598d6a950a6019fa64ece6

Author: Marek Olšák 
Date:   Fri Jan 20 17:57:38 2017 +0100

gallium/radeon: adjust the rule for using the LINEAR_ALIGNED layout

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeon/r600_texture.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/r600_texture.c 
b/src/gallium/drivers/radeon/r600_texture.c
index cba4e7d..0b77c82 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -1184,7 +1184,9 @@ r600_choose_tiling(struct r600_common_screen *rscreen,
/* Textures with a very small height are recommended to be 
linear. */
if (templ->target == PIPE_TEXTURE_1D ||
templ->target == PIPE_TEXTURE_1D_ARRAY ||
-   templ->height0 <= 4)
+   /* Only very thin and long 2D textures should benefit from
+* linear_aligned. */
+   (templ->width0 > 8 && templ->height0 <= 2))
return RADEON_SURF_MODE_LINEAR_ALIGNED;
 
/* Textures likely to be mapped often. */

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Mesa (mesa_12/jenkins): docs: add release notes for 12.0.6

[Emil Velikov]

Module: Mesa
Branch: mesa_12/jenkins
Commit: 555885a0bf64d49bc6c31c0aaeb636c24ef61102
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=555885a0bf64d49bc6c31c0aaeb636c24ef61102

Author: Emil Velikov 
Date:   Tue Jan 24 01:32:02 2017 +

docs: add release notes for 12.0.6

Signed-off-by: Emil Velikov 

---

 docs/relnotes/12.0.6.html | 147 ++
 1 file changed, 147 insertions(+)

diff --git a/docs/relnotes/12.0.6.html b/docs/relnotes/12.0.6.html
new file mode 100644
index 000..82edd9f
--- /dev/null
+++ b/docs/relnotes/12.0.6.html
@@ -0,0 +1,147 @@
+http://www.w3.org/TR/html4/loose.dtd";>
+
+
+  
+  Mesa Release Notes
+  
+
+
+
+
+  The Mesa 3D Graphics Library
+
+
+
+
+
+Mesa 12.0.6 Release Notes / January 23, 2016
+
+
+Mesa 12.0.6 is a bug fix release which fixes bugs found since the 12.0.5 
release.
+
+
+Mesa 12.0.6 implements the OpenGL 4.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.3.  OpenGL
+4.3 is only available if requested at context creation
+because compatibility contexts are not supported.
+
+
+
+SHA256 checksums
+
+TBD
+
+
+
+New features
+None
+
+
+Bug fixes
+
+This list is likely incomplete.
+
+
+
+https://bugs.freedesktop.org/show_bug.cgi?id=92234";>Bug 92234 
- [BDW] GPU hang in Shogun2
+
+https://bugs.freedesktop.org/show_bug.cgi?id=95130";>Bug 95130 
- Derivatives of gl_Color wrong when helper pixels used
+
+https://bugs.freedesktop.org/show_bug.cgi?id=98329";>Bug 98329 
- [dEQP, EGL, SKL, BDW, BSW] 
dEQP-EGL.functional.image.render_multiple_contexts.gles2_renderbuffer_depth16_depth_buffer
+
+https://bugs.freedesktop.org/show_bug.cgi?id=99030";>Bug 99030 
- [HSW, regression] transform feedback fails on Linux 4.8
+
+https://bugs.freedesktop.org/show_bug.cgi?id=99354";>Bug 99354 
- [G71] "Assertion `bkref' failed" reproducible with glmark2
+
+
+
+Changes
+
+Chad Versace (3):
+
+  i965/mt: Disable aux surfaces after making miptree shareable
+  i965/mt: Disable HiZ when sharing depth buffer externally (v2)
+  anv: Handle vkGetPhysicalDeviceQueueFamilyProperties with count == 0
+
+
+Emil Velikov (5):
+
+  docs: add sha256 checksums for 12.0.5
+  get-typod-pick-list.sh: add new script
+  automake: use shared llvm libs for make distcheck
+  egl/wayland: use the destroy_window_callback for swrast
+  Update version to 12.0.6
+
+
+Fredrik Höglund (1):
+
+  dri3: Fix MakeCurrent without a default framebuffer
+
+
+Ilia Mirkin (1):
+
+  nouveau: take extra push space into account for pushbuf_space calls
+
+
+Jason Ekstrand (19):
+
+  spirv/nir: Fix some texture opcode asserts
+  spirv/nir: Add support for shadow samplers that return vec4
+  spirv/nir: Properly handle gather components
+  anv/pipeline: Set binding_table.gather_texture_start
+  nir: Add a helper for determining the type of a texture source
+  nir/lower_tex: Add some helpers for working with tex sources
+  nir/lower_tex: Add support for lowering coordinate offsets
+  i965/nir: Enable NIR lowering of txf and rect offsets
+  i965: Get rid of the do_lower_unnormalized_offsets pass
+  spirv/nir: Don't increment coord_components for array lod queries
+  anv/image: Assert that the image format is actually supported
+  spirv/nir: Move opcode selection higher up in handle_texture
+  spirv/nir: Refactor type handling in handle_texture
+  nir/spirv: Refactor coordinate handling in handle_texture
+  spirv/nir: Handle texture projectors
+  spirv/nir: Add support for ImageQuerySamples
+  anv/device: Return the right error for failed maps
+  anv/device: Implicitly unmap memory objects in FreeMemory
+  anv/descriptor_set: Write the state offset in the surface state free 
list.
+
+
+Kenneth Graunke (2):
+
+  spirv: Move cursor before calling vtn_ssa_value() in phi 2nd pass.
+  i965: Properly flush in hsw_pause_transform_feedback().
+
+
+Marek Olšák (6):
+
+  cso: don't release sampler states that are bound
+  radeonsi: always restore sampler states when unbinding sampler views
+  radeonsi: fix incorrect FMASK checking in bind_sampler_states
+  radeonsi: disable CE on SI + AMDGPU
+  radeonsi: disable the constant engine (CE) on Carrizo and Stoney
+  gallium/radeon: fix the draw-calls HUD query
+
+
+Matt Turner (3):
+
+  i965/fs: Rename opt_copy_propagate -> opt_copy_propagation.
+  i965/fs: Add unit tests for copy propagation pass.
+  i965/fs: Reject copy propagation into SEL if not min/max.
+
+
+Michel Dänzer (1):
+
+  cso: Don't restore nr_samplers in cso_restore_fragment_samplers
+
+
+Nicolai Hähnle (1):
+
+  radeonsi: enable WQM in PS prolog when needed
+
+
+
+
+
+

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Mesa (12.0): i965: Properly flush in hsw_pause_transform_feedback().

[Emil Velikov]

Module: Mesa
Branch: 12.0
Commit: 806de4a22484cfa027af40e87742bd775a7c318f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=806de4a22484cfa027af40e87742bd775a7c318f

Author: Kenneth Graunke 
Date:   Fri Jan  6 00:09:53 2017 -0800

i965: Properly flush in hsw_pause_transform_feedback().

Fixes a number of transform feedback tests when run with Linux 4.8,
which allows us to use the MI_LOAD_REGISTER_REG command, at which point
we started using this new broken path.

ES3-CTS.functional.transform_feedback.array_element.interleaved.lines.*
and Piglit's arb_transform_feedback2/draw-auto are both fixed by this
patch, for example.

Thanks to Chris Wilson for catching this mistake!

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99030
Signed-off-by: Kenneth Graunke 
Reviewed-by: Anuj Phogat 
(cherry picked from commit 2138347a45fa6dad1934b1c58a9e7d7f53194828)

---

 src/mesa/drivers/dri/i965/hsw_sol.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/hsw_sol.c 
b/src/mesa/drivers/dri/i965/hsw_sol.c
index e299b02..b0dd150 100644
--- a/src/mesa/drivers/dri/i965/hsw_sol.c
+++ b/src/mesa/drivers/dri/i965/hsw_sol.c
@@ -201,6 +201,9 @@ hsw_pause_transform_feedback(struct gl_context *ctx,
   (struct brw_transform_feedback_object *) obj;
 
if (brw->is_haswell) {
+  /* Flush any drawing so that the counters have the right values. */
+  brw_emit_mi_flush(brw);
+
   /* Save the SOL buffer offset register values. */
   for (int i = 0; i < BRW_MAX_XFB_STREAMS; i++) {
  BEGIN_BATCH(3);

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Mesa (12.0): egl/wayland: use the destroy_window_callback for swrast

[Emil Velikov]

Module: Mesa
Branch: 12.0
Commit: 689ca381b5f7ee799ded0431416cd4dd666e873a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=689ca381b5f7ee799ded0431416cd4dd666e873a

Author: Emil Velikov 
Date:   Mon Nov 28 18:25:18 2016 +

egl/wayland: use the destroy_window_callback for swrast

As described in commit 690ead4a135 ("egl/wayland-egl: Fix for segfault
in dri2_wl_destroy_surface.") if we attempt to destroy a EGL surface
attached to already destroyed Wayland window we'll get a segfault.

v2: set the correct callback alongside the window->private. (Dan)

Cc: Daniel Stone 
Cc: "12.0 13.0" 
Signed-off-by: Emil Velikov 
Reviewed-by: Daniel Stone 
(cherry picked from commit bfd63143502ff03ceae903f959a6f41666b849bc)

---

 src/egl/drivers/dri2/platform_wayland.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/egl/drivers/dri2/platform_wayland.c 
b/src/egl/drivers/dri2/platform_wayland.c
index 1a295d5..fd4bbf5 100644
--- a/src/egl/drivers/dri2/platform_wayland.c
+++ b/src/egl/drivers/dri2/platform_wayland.c
@@ -1706,6 +1706,8 @@ dri2_wl_swrast_create_window_surface(_EGLDriver *drv, 
_EGLDisplay *disp,
   dri2_surf->format = WL_SHM_FORMAT_ARGB;
 
dri2_surf->wl_win = window;
+   dri2_surf->wl_win->private = dri2_surf;
+   dri2_surf->wl_win->destroy_window_callback = destroy_window_callback;
 
dri2_surf->base.Width = -1;
dri2_surf->base.Height = -1;

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Mesa (12.0): docs: add release notes for 12.0.6

[Emil Velikov]

Module: Mesa
Branch: 12.0
Commit: 555885a0bf64d49bc6c31c0aaeb636c24ef61102
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=555885a0bf64d49bc6c31c0aaeb636c24ef61102

Author: Emil Velikov 
Date:   Tue Jan 24 01:32:02 2017 +

docs: add release notes for 12.0.6

Signed-off-by: Emil Velikov 

---

 docs/relnotes/12.0.6.html | 147 ++
 1 file changed, 147 insertions(+)

diff --git a/docs/relnotes/12.0.6.html b/docs/relnotes/12.0.6.html
new file mode 100644
index 000..82edd9f
--- /dev/null
+++ b/docs/relnotes/12.0.6.html
@@ -0,0 +1,147 @@
+http://www.w3.org/TR/html4/loose.dtd";>
+
+
+  
+  Mesa Release Notes
+  
+
+
+
+
+  The Mesa 3D Graphics Library
+
+
+
+
+
+Mesa 12.0.6 Release Notes / January 23, 2016
+
+
+Mesa 12.0.6 is a bug fix release which fixes bugs found since the 12.0.5 
release.
+
+
+Mesa 12.0.6 implements the OpenGL 4.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.3.  OpenGL
+4.3 is only available if requested at context creation
+because compatibility contexts are not supported.
+
+
+
+SHA256 checksums
+
+TBD
+
+
+
+New features
+None
+
+
+Bug fixes
+
+This list is likely incomplete.
+
+
+
+https://bugs.freedesktop.org/show_bug.cgi?id=92234";>Bug 92234 
- [BDW] GPU hang in Shogun2
+
+https://bugs.freedesktop.org/show_bug.cgi?id=95130";>Bug 95130 
- Derivatives of gl_Color wrong when helper pixels used
+
+https://bugs.freedesktop.org/show_bug.cgi?id=98329";>Bug 98329 
- [dEQP, EGL, SKL, BDW, BSW] 
dEQP-EGL.functional.image.render_multiple_contexts.gles2_renderbuffer_depth16_depth_buffer
+
+https://bugs.freedesktop.org/show_bug.cgi?id=99030";>Bug 99030 
- [HSW, regression] transform feedback fails on Linux 4.8
+
+https://bugs.freedesktop.org/show_bug.cgi?id=99354";>Bug 99354 
- [G71] "Assertion `bkref' failed" reproducible with glmark2
+
+
+
+Changes
+
+Chad Versace (3):
+
+  i965/mt: Disable aux surfaces after making miptree shareable
+  i965/mt: Disable HiZ when sharing depth buffer externally (v2)
+  anv: Handle vkGetPhysicalDeviceQueueFamilyProperties with count == 0
+
+
+Emil Velikov (5):
+
+  docs: add sha256 checksums for 12.0.5
+  get-typod-pick-list.sh: add new script
+  automake: use shared llvm libs for make distcheck
+  egl/wayland: use the destroy_window_callback for swrast
+  Update version to 12.0.6
+
+
+Fredrik Höglund (1):
+
+  dri3: Fix MakeCurrent without a default framebuffer
+
+
+Ilia Mirkin (1):
+
+  nouveau: take extra push space into account for pushbuf_space calls
+
+
+Jason Ekstrand (19):
+
+  spirv/nir: Fix some texture opcode asserts
+  spirv/nir: Add support for shadow samplers that return vec4
+  spirv/nir: Properly handle gather components
+  anv/pipeline: Set binding_table.gather_texture_start
+  nir: Add a helper for determining the type of a texture source
+  nir/lower_tex: Add some helpers for working with tex sources
+  nir/lower_tex: Add support for lowering coordinate offsets
+  i965/nir: Enable NIR lowering of txf and rect offsets
+  i965: Get rid of the do_lower_unnormalized_offsets pass
+  spirv/nir: Don't increment coord_components for array lod queries
+  anv/image: Assert that the image format is actually supported
+  spirv/nir: Move opcode selection higher up in handle_texture
+  spirv/nir: Refactor type handling in handle_texture
+  nir/spirv: Refactor coordinate handling in handle_texture
+  spirv/nir: Handle texture projectors
+  spirv/nir: Add support for ImageQuerySamples
+  anv/device: Return the right error for failed maps
+  anv/device: Implicitly unmap memory objects in FreeMemory
+  anv/descriptor_set: Write the state offset in the surface state free 
list.
+
+
+Kenneth Graunke (2):
+
+  spirv: Move cursor before calling vtn_ssa_value() in phi 2nd pass.
+  i965: Properly flush in hsw_pause_transform_feedback().
+
+
+Marek Olšák (6):
+
+  cso: don't release sampler states that are bound
+  radeonsi: always restore sampler states when unbinding sampler views
+  radeonsi: fix incorrect FMASK checking in bind_sampler_states
+  radeonsi: disable CE on SI + AMDGPU
+  radeonsi: disable the constant engine (CE) on Carrizo and Stoney
+  gallium/radeon: fix the draw-calls HUD query
+
+
+Matt Turner (3):
+
+  i965/fs: Rename opt_copy_propagate -> opt_copy_propagation.
+  i965/fs: Add unit tests for copy propagation pass.
+  i965/fs: Reject copy propagation into SEL if not min/max.
+
+
+Michel Dänzer (1):
+
+  cso: Don't restore nr_samplers in cso_restore_fragment_samplers
+
+
+Nicolai Hähnle (1):
+
+  radeonsi: enable WQM in PS prolog when needed
+
+
+
+
+
+

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Mesa (12.0): anv: Handle vkGetPhysicalDeviceQueueFamilyProperties with count == 0

[Emil Velikov]

Module: Mesa
Branch: 12.0
Commit: 2b87bb9b90b30f8f5aeca4098f9ab27369d5aebc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b87bb9b90b30f8f5aeca4098f9ab27369d5aebc

Author: Chad Versace 
Date:   Tue Dec 27 10:25:58 2016 -0800

anv: Handle vkGetPhysicalDeviceQueueFamilyProperties with count == 0

The spec implicitly allows the incoming count to be 0. From the Vulkan
1.0.38 spec, Section 4.1 Physical Devices:

If the value referenced by pQueueFamilyPropertyCount is not 0 [then
do stuff].

Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Anuj Phogat 
Reviewed-by: Jason Ekstrand 
(cherry picked from commit d6545f234593fb00d02fdc07f9b2a803d2b569f6)

---

 src/intel/vulkan/anv_device.c | 9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 45dff1d..ab9380a 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -583,7 +583,14 @@ void anv_GetPhysicalDeviceQueueFamilyProperties(
   return;
}
 
-   assert(*pCount >= 1);
+   /* The spec implicitly allows the incoming count to be 0. From the Vulkan
+* 1.0.38 spec, Section 4.1 Physical Devices:
+*
+* If the value referenced by pQueueFamilyPropertyCount is not 0 [then
+* do stuff].
+*/
+   if (*pCount == 0)
+  return;
 
*pQueueFamilyProperties = (VkQueueFamilyProperties) {
   .queueFlags = VK_QUEUE_GRAPHICS_BIT |

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Mesa (12.0): Update version to 12.0.6

[Emil Velikov]

Module: Mesa
Branch: 12.0
Commit: ab6240595330ab32d0f34b7ec00edf76a0a66872
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ab6240595330ab32d0f34b7ec00edf76a0a66872

Author: Emil Velikov 
Date:   Tue Jan 24 01:28:48 2017 +

Update version to 12.0.6

Signed-off-by: Emil Velikov 

---

 VERSION | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/VERSION b/VERSION
index 16ec1fb..587d59e 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-12.0.5
+12.0.6

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Mesa (master): gallium: add TGSI_PROPERTY_MUL_ZERO_WINS

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: a2b2cd81d16b929a9699ebebc8023aec258622fd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a2b2cd81d16b929a9699ebebc8023aec258622fd

Author: Ilia Mirkin 
Date:   Sat Jan 14 18:39:41 2017 -0500

gallium: add TGSI_PROPERTY_MUL_ZERO_WINS

This will be useful for proper D3D9 emulation, where this behavior is
expected by some shaders.

Signed-off-by: Ilia Mirkin 
Reviewed-by: Nicolai Hähnle 
Reviewed-by: Axel Davy 

---

 src/gallium/auxiliary/tgsi/tgsi_strings.c  |  3 ++-
 src/gallium/docs/source/tgsi.rst   | 17 +++--
 src/gallium/include/pipe/p_shader_tokens.h |  1 +
 3 files changed, 18 insertions(+), 3 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_strings.c 
b/src/gallium/auxiliary/tgsi/tgsi_strings.c
index 536a4c8..cebc1b4 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_strings.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_strings.c
@@ -148,7 +148,8 @@ const char *tgsi_property_names[TGSI_PROPERTY_COUNT] =
"NEXT_SHADER",
"CS_FIXED_BLOCK_WIDTH",
"CS_FIXED_BLOCK_HEIGHT",
-   "CS_FIXED_BLOCK_DEPTH"
+   "CS_FIXED_BLOCK_DEPTH",
+   "MUL_ZERO_WINS",
 };
 
 const char *tgsi_return_type_names[TGSI_RETURN_TYPE_COUNT] =
diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst
index b981278..341b41f 100644
--- a/src/gallium/docs/source/tgsi.rst
+++ b/src/gallium/docs/source/tgsi.rst
@@ -3547,13 +3547,26 @@ Which shader stage will MOST LIKELY follow after this 
shader when the shader
 is bound. This is only a hint to the driver and doesn't have to be precise.
 Only set for VS and TES.
 
-TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH / HEIGHT / DEPTH
-"""
+CS_FIXED_BLOCK_WIDTH / HEIGHT / DEPTH
+"
 
 Threads per block in each dimension, if known at compile time. If the block 
size
 is known all three should be at least 1. If it is unknown they should all be 
set
 to 0 or not set.
 
+MUL_ZERO_WINS
+"
+
+The MUL TGSI operation (FP32 multiplication) will return 0 if either
+of the operands are equal to 0. That means that 0 * Inf = 0. This
+should be set the same way for an entire pipeline. Note that this
+applies not only to the literal MUL TGSI opcode, but all FP32
+multiplications implied by other operations, such as MAD, FMA, DP2,
+DP3, DP4, DPH, DST, LOG, LRP, XPD, and possibly others. If there is a
+mismatch between shaders, then it is unspecified whether this behavior
+will be enabled.
+
+
 Texture Sampling and Texture Formats
 
 
diff --git a/src/gallium/include/pipe/p_shader_tokens.h 
b/src/gallium/include/pipe/p_shader_tokens.h
index b2d440a..1c8d87c 100644
--- a/src/gallium/include/pipe/p_shader_tokens.h
+++ b/src/gallium/include/pipe/p_shader_tokens.h
@@ -290,6 +290,7 @@ enum tgsi_property_name {
TGSI_PROPERTY_CS_FIXED_BLOCK_WIDTH,
TGSI_PROPERTY_CS_FIXED_BLOCK_HEIGHT,
TGSI_PROPERTY_CS_FIXED_BLOCK_DEPTH,
+   TGSI_PROPERTY_MUL_ZERO_WINS,
TGSI_PROPERTY_COUNT,
 };
 

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Mesa (master): nvc0: add support for MUL_ZERO_WINS property

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: 8c764a2321ad51dacd5538b0a59f3ca446d80747
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c764a2321ad51dacd5538b0a59f3ca446d80747

Author: Ilia Mirkin 
Date:   Sat Jan 14 18:55:25 2017 -0500

nvc0: add support for MUL_ZERO_WINS property

This sets the dnz flag on all the relevant multiplication operations. At
emission time, this will only be supported by nvc0+, so nv50 will need a
different solution.

Signed-off-by: Ilia Mirkin 

---

 .../drivers/nouveau/codegen/nv50_ir_driver.h   |  1 +
 .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp  | 30 --
 .../drivers/nouveau/codegen/nv50_ir_peephole.cpp   |  1 +
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c |  2 +-
 4 files changed, 25 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
index a038801..65d0904 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_driver.h
@@ -177,6 +177,7 @@ struct nv50_ir_prog_info
   uint8_t backFaceColor[2];  /* input/output indices of back face colour */
   uint8_t globalAccess;  /* 1 for read, 2 for wr, 3 for rw */
   bool fp64; /* program uses fp64 math */
+  bool mul_zero_wins;/* program wants for x*0 = 0 */
   bool nv50styleSurfaces;/* generate gX[] access for raw buffers */
   uint16_t texBindBase;  /* base address for tex handles (nve4) */
   uint16_t fbtexBindBase;/* base address for fbtex handle (nve4) */
diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 64bfd08..6320e52 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -1166,6 +1166,9 @@ void Source::scanProperty(const struct tgsi_full_property 
*prop)
case TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL:
   info->prop.fp.earlyFragTests = prop->u[0].Data;
   break;
+   case TGSI_PROPERTY_MUL_ZERO_WINS:
+  info->io.mul_zero_wins = prop->u[0].Data;
+  break;
default:
   INFO("unhandled TGSI property %d\n", prop->Property.PropertyName);
   break;
@@ -2058,12 +2061,14 @@ Converter::buildDot(int dim)
Value *src0 = fetchSrc(0, 0), *src1 = fetchSrc(1, 0);
Value *dotp = getScratch();
 
-   mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1);
+   mkOp2(OP_MUL, TYPE_F32, dotp, src0, src1)
+  ->dnz = info->io.mul_zero_wins;
 
for (int c = 1; c < dim; ++c) {
   src0 = fetchSrc(0, c);
   src1 = fetchSrc(1, c);
-  mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp);
+  mkOp3(OP_MAD, TYPE_F32, dotp, src0, src1, dotp)
+ ->dnz = info->io.mul_zero_wins;
}
return dotp;
 }
@@ -3033,6 +3038,8 @@ Converter::handleInstruction(const struct 
tgsi_full_instruction *insn)
  src1 = fetchSrc(1, c);
  geni = mkOp2(op, dstTy, dst0[c], src0, src1);
  geni->subOp = tgsi::opcodeToSubOp(tgsi.getOpcode());
+ if (op == OP_MUL && dstTy == TYPE_F32)
+geni->dnz = info->io.mul_zero_wins;
   }
   break;
case TGSI_OPCODE_MAD:
@@ -3043,7 +3050,9 @@ Converter::handleInstruction(const struct 
tgsi_full_instruction *insn)
  src0 = fetchSrc(0, c);
  src1 = fetchSrc(1, c);
  src2 = fetchSrc(2, c);
- mkOp3(op, dstTy, dst0[c], src0, src1, src2);
+ geni = mkOp3(op, dstTy, dst0[c], src0, src1, src2);
+ if (dstTy == TYPE_F32)
+geni->dnz = info->io.mul_zero_wins;
   }
   break;
case TGSI_OPCODE_MOV:
@@ -3142,7 +3151,8 @@ Converter::handleInstruction(const struct 
tgsi_full_instruction *insn)
   if (dst0[1]) {
  mkOp1(OP_EX2, TYPE_F32, dst0[1], val1);
  mkOp1(OP_RCP, TYPE_F32, dst0[1], dst0[1]);
- mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0);
+ mkOp2(OP_MUL, TYPE_F32, dst0[1], dst0[1], src0)
+->dnz = info->io.mul_zero_wins;
   }
   if (dst0[3])
  loadImm(dst0[3], 1.0f);
@@ -3175,7 +3185,8 @@ Converter::handleInstruction(const struct 
tgsi_full_instruction *insn)
   if (dst0[1]) {
  src0 = fetchSrc(0, 1);
  src1 = fetchSrc(1, 1);
- mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1);
+ mkOp2(OP_MUL, TYPE_F32, dst0[1], src0, src1)
+->dnz = info->io.mul_zero_wins;
   }
   if (dst0[2])
  mkMov(dst0[2], fetchSrc(0, 2));
@@ -3188,7 +3199,8 @@ Converter::handleInstruction(const struct 
tgsi_full_instruction *insn)
  src1 = fetchSrc(1, c);
  src2 = fetchSrc(2, c);
  mkOp3(OP_MAD, TYPE_F32, dst0[c],
-   mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2);
+   mkOp2v(OP_SUB, TYPE_F32, getSSA(), src1, src2), src0, src2)
+->dnz = info->io.mul_zero_wins;
   }
   break;
case TGSI_OPC

Mesa (master): st/nine: set the MUL_ZERO_WINS flag when supported

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: e1346f25bf6e40496c8db868fe03e20b900c41e4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e1346f25bf6e40496c8db868fe03e20b900c41e4

Author: Ilia Mirkin 
Date:   Sun Jan 15 12:03:55 2017 -0500

st/nine: set the MUL_ZERO_WINS flag when supported

Signed-off-by: Ilia Mirkin 
Reviewed-by: Axel Davy 

---

 src/gallium/state_trackers/nine/nine_shader.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/state_trackers/nine/nine_shader.c 
b/src/gallium/state_trackers/nine/nine_shader.c
index 0a75c07..95bc6ec 100644
--- a/src/gallium/state_trackers/nine/nine_shader.c
+++ b/src/gallium/state_trackers/nine/nine_shader.c
@@ -3564,6 +3564,9 @@ nine_translate_shader(struct NineDevice9 *device, struct 
nine_shader_info *info,
 ureg_property(tx->ureg, TGSI_PROPERTY_FS_COORD_PIXEL_CENTER, 
TGSI_FS_COORD_PIXEL_CENTER_INTEGER);
 }
 
+if (GET_CAP(TGSI_MUL_ZERO_WINS))
+   ureg_property(tx->ureg, TGSI_PROPERTY_MUL_ZERO_WINS, 1);
+
 while (!sm1_parse_eof(tx) && !tx->failure)
 sm1_parse_instruction(tx);
 tx->parse++; /* for byte_size */

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Mesa (master): nv50: add support for MUL_ZERO_WINS property

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: b755f2f233e621d8fa066d5e7dfd1b24f8ecf46d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b755f2f233e621d8fa066d5e7dfd1b24f8ecf46d

Author: Ilia Mirkin 
Date:   Sat Jan 14 18:55:25 2017 -0500

nv50: add support for MUL_ZERO_WINS property

This is simply keyed off the vertex shader, as that's guaranteed to be
present in any pipeline.

Signed-off-by: Ilia Mirkin 

---

 src/gallium/drivers/nouveau/nv50/nv50_program.c | 2 +-
 src/gallium/drivers/nouveau/nv50/nv50_program.h | 2 ++
 src/gallium/drivers/nouveau/nv50/nv50_screen.c  | 2 +-
 src/gallium/drivers/nouveau/nv50/nv50_screen.h  | 1 +
 src/gallium/drivers/nouveau/nv50/nv50_vbo.c | 6 ++
 5 files changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.c 
b/src/gallium/drivers/nouveau/nv50/nv50_program.c
index ea5febd..76d06ae 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_program.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_program.c
@@ -380,7 +380,7 @@ nv50_program_translate(struct nv50_program *prog, uint16_t 
chipset,
prog->interps = info->bin.fixupData;
prog->max_gpr = MAX2(4, (info->bin.maxGPR >> 1) + 1);
prog->tls_space = info->bin.tlsSpace;
-
+   prog->mul_zero_wins = info->io.mul_zero_wins;
prog->vp.need_vertex_id = info->io.vertexId < PIPE_MAX_SHADER_INPUTS;
 
prog->vp.clip_enable = (1 << info->io.clipDistances) - 1;
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_program.h 
b/src/gallium/drivers/nouveau/nv50/nv50_program.h
index 009d41f..2b45b09 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_program.h
+++ b/src/gallium/drivers/nouveau/nv50/nv50_program.h
@@ -108,6 +108,8 @@ struct nv50_program {
   unsigned num_syms;
} cp;
 
+   bool mul_zero_wins;
+
void *fixups; /* relocation records */
void *interps; /* interpolation records */
 
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
index 12c15ad..d09b41a 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c
@@ -198,6 +198,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
case PIPE_CAP_STRING_MARKER:
case PIPE_CAP_CULL_DISTANCE:
case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
+   case PIPE_CAP_TGSI_MUL_ZERO_WINS:
   return 1;
case PIPE_CAP_SEAMLESS_CUBE_MAP:
   return 1; /* class_3d >= NVA0_3D_CLASS; */
@@ -259,7 +260,6 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
case PIPE_CAP_NATIVE_FENCE_FD:
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
case PIPE_CAP_TGSI_FS_FBFETCH:
-   case PIPE_CAP_TGSI_MUL_ZERO_WINS:
   return 0;
 
case PIPE_CAP_VENDOR_ID:
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.h 
b/src/gallium/drivers/nouveau/nv50/nv50_screen.h
index 370d8f5..6f3b40c 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_screen.h
+++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.h
@@ -54,6 +54,7 @@ struct nv50_graph_state {
uint8_t prim_size;
uint16_t scissor;
bool seamless_cube_map;
+   bool mul_zero_wins;
 };
 
 struct nv50_screen {
diff --git a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c 
b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
index 4c46ed0..227038e 100644
--- a/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
+++ b/src/gallium/drivers/nouveau/nv50/nv50_vbo.c
@@ -824,6 +824,12 @@ nv50_draw_vbo(struct pipe_context *pipe, const struct 
pipe_draw_info *info)
   PUSH_DATA (push, nv50->seamless_cube_map ? 
NVA0_3D_TEX_MISC_SEAMLESS_CUBE_MAP : 0);
}
 
+   if (nv50->vertprog->mul_zero_wins != nv50->state.mul_zero_wins) {
+  nv50->state.mul_zero_wins = nv50->vertprog->mul_zero_wins;
+  BEGIN_NV04(push, NV50_3D(UNK1690), 1);
+  PUSH_DATA (push, 0x0001 * !!nv50->state.mul_zero_wins);
+   }
+
if (nv50->vbo_fifo) {
   nv50_push_vbo(nv50, info);
   push->kick_notify = nv50_default_kick_notify;

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Mesa (master): gallium: add PIPE_CAP_TGSI_MUL_ZERO_WINS

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: 6e40938fbc724856e3fe71b9686621c84baccba1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e40938fbc724856e3fe71b9686621c84baccba1

Author: Ilia Mirkin 
Date:   Mon Jan 16 22:14:38 2017 -0500

gallium: add PIPE_CAP_TGSI_MUL_ZERO_WINS

Signed-off-by: Ilia Mirkin 
Reviewed-by: Nicolai Hähnle 
Reviewed-by: Axel Davy 

---

 src/gallium/docs/source/screen.rst   | 2 ++
 src/gallium/drivers/etnaviv/etnaviv_screen.c | 1 +
 src/gallium/drivers/freedreno/freedreno_screen.c | 1 +
 src/gallium/drivers/i915/i915_screen.c   | 1 +
 src/gallium/drivers/ilo/ilo_screen.c | 1 +
 src/gallium/drivers/llvmpipe/lp_screen.c | 1 +
 src/gallium/drivers/nouveau/nv30/nv30_screen.c   | 1 +
 src/gallium/drivers/nouveau/nv50/nv50_screen.c   | 1 +
 src/gallium/drivers/nouveau/nvc0/nvc0_screen.c   | 1 +
 src/gallium/drivers/r300/r300_screen.c   | 1 +
 src/gallium/drivers/r600/r600_pipe.c | 1 +
 src/gallium/drivers/radeonsi/si_pipe.c   | 1 +
 src/gallium/drivers/softpipe/sp_screen.c | 1 +
 src/gallium/drivers/svga/svga_screen.c   | 1 +
 src/gallium/drivers/swr/swr_screen.cpp   | 1 +
 src/gallium/drivers/vc4/vc4_screen.c | 1 +
 src/gallium/drivers/virgl/virgl_screen.c | 1 +
 src/gallium/include/pipe/p_defines.h | 1 +
 18 files changed, 19 insertions(+)

diff --git a/src/gallium/docs/source/screen.rst 
b/src/gallium/docs/source/screen.rst
index 5ae2596..2bfcd9f 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -371,6 +371,8 @@ The integer capabilities:
   and lowering.
 * ``PIPE_CAP_TGSI_FS_FBFETCH``: Whether a fragment shader can use the FBFETCH
   opcode to retrieve the current value in the framebuffer.
+* ``PIPE_CAP_TGSI_MUL_ZERO_WINS``: Whether TGSI shaders support the
+  ``TGSI_PROPERTY_MUL_ZERO_WINS`` shader property.
 
 
 .. _pipe_capf:
diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c 
b/src/gallium/drivers/etnaviv/etnaviv_screen.c
index fa76226..66c530d 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_screen.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c
@@ -240,6 +240,7 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
case PIPE_CAP_NATIVE_FENCE_FD:
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
case PIPE_CAP_TGSI_FS_FBFETCH:
+   case PIPE_CAP_TGSI_MUL_ZERO_WINS:
   return 0;
 
/* Stream output. */
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c 
b/src/gallium/drivers/freedreno/freedreno_screen.c
index 1b2c588..a1c026c 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -297,6 +297,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
case PIPE_CAP_TGSI_FS_FBFETCH:
+   case PIPE_CAP_TGSI_MUL_ZERO_WINS:
return 0;
 
case PIPE_CAP_MAX_VIEWPORTS:
diff --git a/src/gallium/drivers/i915/i915_screen.c 
b/src/gallium/drivers/i915/i915_screen.c
index 8ab6cd9..7889873 100644
--- a/src/gallium/drivers/i915/i915_screen.c
+++ b/src/gallium/drivers/i915/i915_screen.c
@@ -298,6 +298,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap 
cap)
case PIPE_CAP_NATIVE_FENCE_FD:
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
case PIPE_CAP_TGSI_FS_FBFETCH:
+   case PIPE_CAP_TGSI_MUL_ZERO_WINS:
   return 0;
 
case PIPE_CAP_MAX_VIEWPORTS:
diff --git a/src/gallium/drivers/ilo/ilo_screen.c 
b/src/gallium/drivers/ilo/ilo_screen.c
index 20a4ee3..6018cd1 100644
--- a/src/gallium/drivers/ilo/ilo_screen.c
+++ b/src/gallium/drivers/ilo/ilo_screen.c
@@ -521,6 +521,7 @@ ilo_get_param(struct pipe_screen *screen, enum pipe_cap 
param)
case PIPE_CAP_NATIVE_FENCE_FD:
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
case PIPE_CAP_TGSI_FS_FBFETCH:
+   case PIPE_CAP_TGSI_MUL_ZERO_WINS:
   return 0;
 
case PIPE_CAP_VENDOR_ID:
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c 
b/src/gallium/drivers/llvmpipe/lp_screen.c
index 02f14af..89a1dc8 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -342,6 +342,7 @@ llvmpipe_get_param(struct pipe_screen *screen, enum 
pipe_cap param)
case PIPE_CAP_NATIVE_FENCE_FD:
case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
case PIPE_CAP_TGSI_FS_FBFETCH:
+   case PIPE_CAP_TGSI_MUL_ZERO_WINS:
   return 0;
}
/* should only get here on unhandled cases */
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c 
b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
index 56bde41..b6c2636 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
@@ -207,6 +207,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
case PIPE_CAP_NATIVE_FENCE_FD:
case PIPE

Mesa: tag mesa-12.0.6: mesa-12.0.6

[Emil Velikov]

Module: Mesa
Branch: refs/tags/mesa-12.0.6
Tag:fb8374912a958b86102f8e64a69ce4e74ce38319
URL:
http://cgit.freedesktop.org/mesa/mesa/tag/?id=fb8374912a958b86102f8e64a69ce4e74ce38319

Tagger: Emil Velikov 
Date:   Tue Jan 24 01:45:09 2017 +

mesa-12.0.6
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Mesa (12.0): docs: add sha256 checksums for 12.0.6

[Emil Velikov]

Module: Mesa
Branch: 12.0
Commit: 36e3f2542d3cde1fe4f7ca0be83dc49d941cb988
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=36e3f2542d3cde1fe4f7ca0be83dc49d941cb988

Author: Emil Velikov 
Date:   Tue Jan 24 02:02:48 2017 +

docs: add sha256 checksums for 12.0.6

Signed-off-by: Emil Velikov 

---

 docs/relnotes/12.0.6.html | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/docs/relnotes/12.0.6.html b/docs/relnotes/12.0.6.html
index 82edd9f..b06b3d1 100644
--- a/docs/relnotes/12.0.6.html
+++ b/docs/relnotes/12.0.6.html
@@ -31,7 +31,8 @@ because compatibility contexts are not supported.
 
 SHA256 checksums
 
-TBD
+65339ba5d76a45225b8b56f9a1da9db15c569e1d163760faa2921da0a8461741  
mesa-12.0.6.tar.gz
+7d6da9744c1022a4c2ab6ad01a206984d00443fb691568011d01b3dd97e36448  
mesa-12.0.6.tar.xz
 
 
 

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Mesa (12.0): docs: use correct year for the 12.0.6 release notes

[Emil Velikov]

Module: Mesa
Branch: 12.0
Commit: 13953f012dfc7f89dbb07f1eda856aa5353347cc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=13953f012dfc7f89dbb07f1eda856aa5353347cc

Author: Emil Velikov 
Date:   Tue Jan 24 02:05:20 2017 +

docs: use correct year for the 12.0.6 release notes

Signed-off-by: Emil Velikov 

---

 docs/relnotes/12.0.6.html | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/relnotes/12.0.6.html b/docs/relnotes/12.0.6.html
index b06b3d1..14dd8db 100644
--- a/docs/relnotes/12.0.6.html
+++ b/docs/relnotes/12.0.6.html
@@ -14,7 +14,7 @@
 
 
 
-Mesa 12.0.6 Release Notes / January 23, 2016
+Mesa 12.0.6 Release Notes / January 23, 2017
 
 
 Mesa 12.0.6 is a bug fix release which fixes bugs found since the 12.0.5 
release.

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Mesa (master): docs: add sha256 checksums for 12.0.6

[Emil Velikov]

Module: Mesa
Branch: master
Commit: c16e7e0a60a749649bd796b2a6b7c12b01c9c30f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c16e7e0a60a749649bd796b2a6b7c12b01c9c30f

Author: Emil Velikov 
Date:   Tue Jan 24 02:02:48 2017 +

docs: add sha256 checksums for 12.0.6

Signed-off-by: Emil Velikov 
(cherry picked from commit 36e3f2542d3cde1fe4f7ca0be83dc49d941cb988)

---

 docs/relnotes/12.0.6.html | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/docs/relnotes/12.0.6.html b/docs/relnotes/12.0.6.html
index 82edd9f..b06b3d1 100644
--- a/docs/relnotes/12.0.6.html
+++ b/docs/relnotes/12.0.6.html
@@ -31,7 +31,8 @@ because compatibility contexts are not supported.
 
 SHA256 checksums
 
-TBD
+65339ba5d76a45225b8b56f9a1da9db15c569e1d163760faa2921da0a8461741  
mesa-12.0.6.tar.gz
+7d6da9744c1022a4c2ab6ad01a206984d00443fb691568011d01b3dd97e36448  
mesa-12.0.6.tar.xz
 
 
 

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Mesa (master): docs: add news item and link release notes for 12.0.6

[Emil Velikov]

Module: Mesa
Branch: master
Commit: 530cd248f546f9c227cce6a027818d13938d4f6b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=530cd248f546f9c227cce6a027818d13938d4f6b

Author: Emil Velikov 
Date:   Tue Jan 24 02:13:42 2017 +

docs: add news item and link release notes for 12.0.6

Signed-off-by: Emil Velikov 

---

 docs/index.html| 11 +++
 docs/relnotes.html |  1 +
 2 files changed, 12 insertions(+)

diff --git a/docs/index.html b/docs/index.html
index 6e55f80..2520841 100644
--- a/docs/index.html
+++ b/docs/index.html
@@ -16,6 +16,17 @@
 
 News
 
+January 23, 2017
+
+Mesa 12.0.6 is released.
+This is a bug-fix release.
+
+NOTE: This is an extra release for the 12.0 stable branch, as per developers'
+feedback. It is anticipated that 12.0.6 will be the final release in the 12.0
+series. Users of 12.0 are encouraged to migrate to the 13.0 series in order
+to obtain future fixes.
+
+
 January 5, 2017
 
 Mesa 13.0.3 is released.
diff --git a/docs/relnotes.html b/docs/relnotes.html
index 056b0ad..49d6ca8 100644
--- a/docs/relnotes.html
+++ b/docs/relnotes.html
@@ -21,6 +21,7 @@ The release notes summarize what's new or changed in each 
Mesa release.
 
 
 
+12.0.6 release notes
 13.0.3 release notes
 12.0.5 release notes
 13.0.2 release notes

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Mesa (master): docs: add release notes for 12.0.6

[Emil Velikov]

Module: Mesa
Branch: master
Commit: b1137cb9dee7afe8bd9ec92e65db95bacdc030d5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b1137cb9dee7afe8bd9ec92e65db95bacdc030d5

Author: Emil Velikov 
Date:   Tue Jan 24 01:32:02 2017 +

docs: add release notes for 12.0.6

Signed-off-by: Emil Velikov 
(cherry picked from commit 555885a0bf64d49bc6c31c0aaeb636c24ef61102)

---

 docs/relnotes/12.0.6.html | 147 ++
 1 file changed, 147 insertions(+)

diff --git a/docs/relnotes/12.0.6.html b/docs/relnotes/12.0.6.html
new file mode 100644
index 000..82edd9f
--- /dev/null
+++ b/docs/relnotes/12.0.6.html
@@ -0,0 +1,147 @@
+http://www.w3.org/TR/html4/loose.dtd";>
+
+
+  
+  Mesa Release Notes
+  
+
+
+
+
+  The Mesa 3D Graphics Library
+
+
+
+
+
+Mesa 12.0.6 Release Notes / January 23, 2016
+
+
+Mesa 12.0.6 is a bug fix release which fixes bugs found since the 12.0.5 
release.
+
+
+Mesa 12.0.6 implements the OpenGL 4.3 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.3.  OpenGL
+4.3 is only available if requested at context creation
+because compatibility contexts are not supported.
+
+
+
+SHA256 checksums
+
+TBD
+
+
+
+New features
+None
+
+
+Bug fixes
+
+This list is likely incomplete.
+
+
+
+https://bugs.freedesktop.org/show_bug.cgi?id=92234";>Bug 92234 
- [BDW] GPU hang in Shogun2
+
+https://bugs.freedesktop.org/show_bug.cgi?id=95130";>Bug 95130 
- Derivatives of gl_Color wrong when helper pixels used
+
+https://bugs.freedesktop.org/show_bug.cgi?id=98329";>Bug 98329 
- [dEQP, EGL, SKL, BDW, BSW] 
dEQP-EGL.functional.image.render_multiple_contexts.gles2_renderbuffer_depth16_depth_buffer
+
+https://bugs.freedesktop.org/show_bug.cgi?id=99030";>Bug 99030 
- [HSW, regression] transform feedback fails on Linux 4.8
+
+https://bugs.freedesktop.org/show_bug.cgi?id=99354";>Bug 99354 
- [G71] "Assertion `bkref' failed" reproducible with glmark2
+
+
+
+Changes
+
+Chad Versace (3):
+
+  i965/mt: Disable aux surfaces after making miptree shareable
+  i965/mt: Disable HiZ when sharing depth buffer externally (v2)
+  anv: Handle vkGetPhysicalDeviceQueueFamilyProperties with count == 0
+
+
+Emil Velikov (5):
+
+  docs: add sha256 checksums for 12.0.5
+  get-typod-pick-list.sh: add new script
+  automake: use shared llvm libs for make distcheck
+  egl/wayland: use the destroy_window_callback for swrast
+  Update version to 12.0.6
+
+
+Fredrik Höglund (1):
+
+  dri3: Fix MakeCurrent without a default framebuffer
+
+
+Ilia Mirkin (1):
+
+  nouveau: take extra push space into account for pushbuf_space calls
+
+
+Jason Ekstrand (19):
+
+  spirv/nir: Fix some texture opcode asserts
+  spirv/nir: Add support for shadow samplers that return vec4
+  spirv/nir: Properly handle gather components
+  anv/pipeline: Set binding_table.gather_texture_start
+  nir: Add a helper for determining the type of a texture source
+  nir/lower_tex: Add some helpers for working with tex sources
+  nir/lower_tex: Add support for lowering coordinate offsets
+  i965/nir: Enable NIR lowering of txf and rect offsets
+  i965: Get rid of the do_lower_unnormalized_offsets pass
+  spirv/nir: Don't increment coord_components for array lod queries
+  anv/image: Assert that the image format is actually supported
+  spirv/nir: Move opcode selection higher up in handle_texture
+  spirv/nir: Refactor type handling in handle_texture
+  nir/spirv: Refactor coordinate handling in handle_texture
+  spirv/nir: Handle texture projectors
+  spirv/nir: Add support for ImageQuerySamples
+  anv/device: Return the right error for failed maps
+  anv/device: Implicitly unmap memory objects in FreeMemory
+  anv/descriptor_set: Write the state offset in the surface state free 
list.
+
+
+Kenneth Graunke (2):
+
+  spirv: Move cursor before calling vtn_ssa_value() in phi 2nd pass.
+  i965: Properly flush in hsw_pause_transform_feedback().
+
+
+Marek Olšák (6):
+
+  cso: don't release sampler states that are bound
+  radeonsi: always restore sampler states when unbinding sampler views
+  radeonsi: fix incorrect FMASK checking in bind_sampler_states
+  radeonsi: disable CE on SI + AMDGPU
+  radeonsi: disable the constant engine (CE) on Carrizo and Stoney
+  gallium/radeon: fix the draw-calls HUD query
+
+
+Matt Turner (3):
+
+  i965/fs: Rename opt_copy_propagate -> opt_copy_propagation.
+  i965/fs: Add unit tests for copy propagation pass.
+  i965/fs: Reject copy propagation into SEL if not min/max.
+
+
+Michel Dänzer (1):
+
+  cso: Don't restore nr_samplers in cso_restore_fragment_samplers
+
+
+Nicolai Hähnle (1):
+
+  radeonsi: enable WQM in PS prolog when needed
+
+
+
+
+
+

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Mesa (master): docs: use correct year for the 12.0.6 release notes

[Emil Velikov]

Module: Mesa
Branch: master
Commit: 9b16bd8b6c1b383378145ae8e493be0853816287
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b16bd8b6c1b383378145ae8e493be0853816287

Author: Emil Velikov 
Date:   Tue Jan 24 02:05:20 2017 +

docs: use correct year for the 12.0.6 release notes

Signed-off-by: Emil Velikov 
(cherry picked from commit 13953f012dfc7f89dbb07f1eda856aa5353347cc)

---

 docs/relnotes/12.0.6.html | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/relnotes/12.0.6.html b/docs/relnotes/12.0.6.html
index b06b3d1..14dd8db 100644
--- a/docs/relnotes/12.0.6.html
+++ b/docs/relnotes/12.0.6.html
@@ -14,7 +14,7 @@
 
 
 
-Mesa 12.0.6 Release Notes / January 23, 2016
+Mesa 12.0.6 Release Notes / January 23, 2017
 
 
 Mesa 12.0.6 is a bug fix release which fixes bugs found since the 12.0.5 
release.

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Mesa (master): docs/releasing: remove stray "cd"

[Emil Velikov]

Module: Mesa
Branch: master
Commit: 9924cdecd968b456eb67683279eb91ffe6d2d13a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9924cdecd968b456eb67683279eb91ffe6d2d13a

Author: Emil Velikov 
Date:   Tue Jan 24 00:58:54 2017 +

docs/releasing: remove stray "cd"

Signed-off-by: Emil Velikov 

---

 docs/releasing.html | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/releasing.html b/docs/releasing.html
index d650910..2ed66a1 100644
--- a/docs/releasing.html
+++ b/docs/releasing.html
@@ -345,7 +345,7 @@ Here is one solution that I've been using.
tar -xaf mesa-$__version.tar.xz && cd mesa-$__version 
&& scons && cd ..
 
# Test the automake binaries
-   rm -rf cd mesa-$__version
+   rm -rf mesa-$__version
tar -xaf mesa-$__version.tar.xz && cd mesa-$__version
./configure \
--with-dri-drivers=i965,swrast \

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Mesa (master): gbm: Move getters to match order in header file (trivial)

[Ben Widawsky]

Module: Mesa
Branch: master
Commit: bb9ff98b4c3fb9e090168bddd6e476e7f24831f8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb9ff98b4c3fb9e090168bddd6e476e7f24831f8

Author: Ben Widawsky 
Date:   Wed Oct 19 14:52:12 2016 -0700

gbm: Move getters to match order in header file (trivial)

Other things are out of order, but I need to add a getter so I'm just
fixing those.

This helps people adding to GBM know where the right place to put things
is.

Signed-off-by: Ben Widawsky 
Reviewed-by: Eric Engestrom 
Acked-by: Daniel Stone 

---

 src/gbm/main/gbm.c | 22 +++---
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/gbm/main/gbm.c b/src/gbm/main/gbm.c
index 9ef1990..00113fa 100644
--- a/src/gbm/main/gbm.c
+++ b/src/gbm/main/gbm.c
@@ -181,6 +181,17 @@ gbm_bo_get_format(struct gbm_bo *bo)
return bo->format;
 }
 
+/** Get the gbm device used to create the buffer object
+ *
+ * \param bo The buffer object
+ * \return Returns the gbm device with which the buffer object was created
+ */
+GBM_EXPORT struct gbm_device *
+gbm_bo_get_device(struct gbm_bo *bo)
+{
+   return bo->gbm;
+}
+
 /** Get the handle of the buffer object
  *
  * This is stored in the platform generic union gbm_bo_handle type. However
@@ -232,17 +243,6 @@ gbm_bo_write(struct gbm_bo *bo, const void *buf, size_t 
count)
return bo->gbm->bo_write(bo, buf, count);
 }
 
-/** Get the gbm device used to create the buffer object
- *
- * \param bo The buffer object
- * \return Returns the gbm device with which the buffer object was created
- */
-GBM_EXPORT struct gbm_device *
-gbm_bo_get_device(struct gbm_bo *bo)
-{
-   return bo->gbm;
-}
-
 /** Set the user data associated with a buffer object
  *
  * \param bo The buffer object

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Mesa (master): gbm: Fix width height getters return type (trivial)

[Ben Widawsky]

Module: Mesa
Branch: master
Commit: e63ab36d0e13ce41d37734ac5c02bc80a3141021
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e63ab36d0e13ce41d37734ac5c02bc80a3141021

Author: Ben Widawsky 
Date:   Wed Oct 26 12:23:32 2016 -0700

gbm: Fix width height getters return type (trivial)

v2: Other way round... to make consistent, make both return type have
the fixed width - uint32_t.

Cc: Daniel Stone 
Signed-off-by: Ben Widawsky 
Reviewed-by: Eric Engestrom 
Acked-by: Daniel Stone 

---

 src/gbm/main/gbm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gbm/main/gbm.c b/src/gbm/main/gbm.c
index 00113fa..e96297e 100644
--- a/src/gbm/main/gbm.c
+++ b/src/gbm/main/gbm.c
@@ -137,7 +137,7 @@ gbm_create_device(int fd)
  * \return The width of the allocated buffer object
  *
  */
-GBM_EXPORT unsigned int
+GBM_EXPORT uint32_t
 gbm_bo_get_width(struct gbm_bo *bo)
 {
return bo->width;
@@ -148,7 +148,7 @@ gbm_bo_get_width(struct gbm_bo *bo)
  * \param bo The buffer object
  * \return The height of the allocated buffer object
  */
-GBM_EXPORT unsigned int
+GBM_EXPORT uint32_t
 gbm_bo_get_height(struct gbm_bo *bo)
 {
return bo->height;

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