Mesa (master): radv: make sizes & offsets 32 bit in radv_descriptor_update_template_entry.
Module: Mesa Branch: master Commit: e20eb91e2bfef045d6806838e6453bc6ddb2e238 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e20eb91e2bfef045d6806838e6453bc6ddb2e238 Author: Bas Nieuwenhuizen Date: Thu Apr 13 23:49:00 2017 +0200 radv: make sizes & offsets 32 bit in radv_descriptor_update_template_entry. v2: Also convert the calculations. Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Fredrik Höglund --- src/amd/vulkan/radv_descriptor_set.c | 4 ++-- src/amd/vulkan/radv_private.h| 10 +- 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/amd/vulkan/radv_descriptor_set.c b/src/amd/vulkan/radv_descriptor_set.c index c048a4c7f5..f585061b4f 100644 --- a/src/amd/vulkan/radv_descriptor_set.c +++ b/src/amd/vulkan/radv_descriptor_set.c @@ -775,8 +775,8 @@ VkResult radv_CreateDescriptorUpdateTemplateKHR(VkDevice _device, const uint32_t buffer_offset = binding_layout->buffer_offset + binding_layout->buffer_count * entry->dstArrayElement; const uint32_t *immutable_samplers = NULL; - uint16_t dst_offset; - uint16_t dst_stride; + uint32_t dst_offset; + uint32_t dst_stride; /* dst_offset is an offset into dynamic_descriptors when the descriptor is dynamic, and an offset into mapped_ptr otherwise */ diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 00190e7eee..2afc0cbedf 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -576,16 +576,16 @@ struct radv_descriptor_update_template_entry { VkDescriptorType descriptor_type; /* The number of descriptors to update */ - uint16_t descriptor_count; + uint32_t descriptor_count; /* Into mapped_ptr or dynamic_descriptors, in units of the respective array */ - uint16_t dst_offset; + uint32_t dst_offset; /* In dwords. Not valid/used for dynamic descriptors */ - uint16_t dst_stride; + uint32_t dst_stride; - uint16_t buffer_offset; - uint16_t buffer_count; + uint32_t buffer_offset; + uint32_t buffer_count; /* Only valid for combined image samplers and samplers */ uint16_t has_sampler; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): swr: add linux to scons build
Module: Mesa Branch: master Commit: 870760e02e7388455c4af4e15f9e4c7e680e4b4d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=870760e02e7388455c4af4e15f9e4c7e680e4b4d Author: George Kyriazis Date: Thu Apr 13 08:44:08 2017 -0500 swr: add linux to scons build Make swr compile for both linux and windows. Reviewed-by: Tim Rowley --- src/gallium/drivers/swr/SConscript| 7 +-- src/gallium/targets/libgl-xlib/SConscript | 2 +- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/swr/SConscript b/src/gallium/drivers/swr/SConscript index eca5dba830..5e3784b51f 100644 --- a/src/gallium/drivers/swr/SConscript +++ b/src/gallium/drivers/swr/SConscript @@ -17,11 +17,6 @@ if env['LLVM_VERSION'] < distutils.version.LooseVersion('3.9'): env['swr'] = False Return() -if env['platform'] != 'windows': -print "warning: swr scons build only supports windows: not building swr" -env['swr'] = False -Return() - env.MSVC2013Compat() env = env.Clone() @@ -205,7 +200,7 @@ envavx2.Append(CPPDEFINES = ['KNOB_ARCH=KNOB_ARCH_AVX2']) if env['platform'] == 'windows': envavx2.Append(CCFLAGS = ['/arch:AVX2']) else: -envavx2.Append(CCFLAGS = ['-mavx2']) +envavx2.Append(CCFLAGS = ['-mavx2', '-mfma', '-mbmi2', '-mf16c']) swrAVX2 = envavx2.SharedLibrary( target = 'swrAVX2', diff --git a/src/gallium/targets/libgl-xlib/SConscript b/src/gallium/targets/libgl-xlib/SConscript index d01bb3c256..a81ac79325 100644 --- a/src/gallium/targets/libgl-xlib/SConscript +++ b/src/gallium/targets/libgl-xlib/SConscript @@ -49,7 +49,7 @@ if env['llvm']: env.Prepend(LIBS = [llvmpipe]) if env['swr']: -env.Append(CPPDEFINES = 'HAVE_SWR') +env.Append(CPPDEFINES = 'GALLIUM_SWR') env.Prepend(LIBS = [swr]) if env['platform'] != 'darwin': ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): freedreno/ir3: move 'keeps' to block level
Module: Mesa Branch: master Commit: 75afd2586f86231dbf929ec19d3bded88c9ea3a1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=75afd2586f86231dbf929ec19d3bded88c9ea3a1 Author: Rob Clark Date: Tue Apr 4 20:29:53 2017 -0400 freedreno/ir3: move 'keeps' to block level For things like SSBOs and atomics we'll want to track this at a block level. Signed-off-by: Rob Clark --- src/gallium/drivers/freedreno/ir3/ir3.h | 12 ++-- src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c | 4 ++-- src/gallium/drivers/freedreno/ir3/ir3_cp.c | 10 +- src/gallium/drivers/freedreno/ir3/ir3_depth.c| 8 src/gallium/drivers/freedreno/ir3/ir3_group.c| 8 +--- 5 files changed, 22 insertions(+), 20 deletions(-) diff --git a/src/gallium/drivers/freedreno/ir3/ir3.h b/src/gallium/drivers/freedreno/ir3/ir3.h index c205c8fac4..480b27ce5d 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3.h +++ b/src/gallium/drivers/freedreno/ir3/ir3.h @@ -369,12 +369,6 @@ struct ir3 { unsigned predicates_count, predicates_sz; struct ir3_instruction **predicates; - /* Track instructions which do not write a register but other- -* wise must not be discarded (such as kill, stg, etc) -*/ - unsigned keeps_count, keeps_sz; - struct ir3_instruction **keeps; - /* Track texture sample instructions which need texture state * patched in (for astc-srgb workaround): */ @@ -435,6 +429,12 @@ struct ir3_block { uint16_t start_ip, end_ip; + /* Track instructions which do not write a register but other- +* wise must not be discarded (such as kill, stg, etc) +*/ + unsigned keeps_count, keeps_sz; + struct ir3_instruction **keeps; + /* used for per-pass extra block data. Mainly used right * now in RA step to track livein/liveout. */ diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c index 7932a6f18a..22619e852c 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c @@ -1308,7 +1308,7 @@ emit_intrinsic(struct ir3_compile *ctx, nir_intrinsic_instr *intr) kill = ir3_KILL(b, cond, 0); array_insert(ctx->ir, ctx->ir->predicates, kill); - array_insert(ctx->ir, ctx->ir->keeps, kill); + array_insert(b, b->keeps, kill); ctx->so->has_kill = true; break; @@ -1972,7 +1972,7 @@ emit_stream_out(struct ir3_compile *ctx) stg->cat6.type = TYPE_U32; stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4; - array_insert(ctx->ir, ctx->ir->keeps, stg); + array_insert(ctx->block, ctx->block->keeps, stg); } } diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cp.c b/src/gallium/drivers/freedreno/ir3/ir3_cp.c index 71e02615c7..a9023ce571 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_cp.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_cp.c @@ -576,15 +576,15 @@ ir3_cp(struct ir3 *ir, struct ir3_shader_variant *so) } } - for (unsigned i = 0; i < ir->keeps_count; i++) { - instr_cp(&ctx, ir->keeps[i]); - ir->keeps[i] = eliminate_output_mov(ir->keeps[i]); - } - list_for_each_entry (struct ir3_block, block, &ir->block_list, node) { if (block->condition) { instr_cp(&ctx, block->condition); block->condition = eliminate_output_mov(block->condition); } + + for (unsigned i = 0; i < block->keeps_count; i++) { + instr_cp(&ctx, block->keeps[i]); + block->keeps[i] = eliminate_output_mov(block->keeps[i]); + } } } diff --git a/src/gallium/drivers/freedreno/ir3/ir3_depth.c b/src/gallium/drivers/freedreno/ir3/ir3_depth.c index 1b8a446ca6..be39027b6a 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_depth.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_depth.c @@ -159,11 +159,11 @@ ir3_depth(struct ir3 *ir) if (ir->outputs[i]) ir3_instr_depth(ir->outputs[i]); - for (i = 0; i < ir->keeps_count; i++) - ir3_instr_depth(ir->keeps[i]); - - /* We also need to account for if-condition: */ list_for_each_entry (struct ir3_block, block, &ir->block_list, node) { + for (i = 0; i < block->keeps_count; i++) + ir3_instr_depth(block->keeps[i]); + + /* We also need to account for if-condition: */ if (block->condition) ir3_instr_depth(block->condition); } diff --git a/src/gallium/drivers/freedreno/ir3/ir3_group.c b/src/gallium/drive
Mesa (master): nir/print: add compute shader info
Module: Mesa Branch: master Commit: 9fc3e7137ac5566afd3f287ea67c0cdf3c3bfe97 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9fc3e7137ac5566afd3f287ea67c0cdf3c3bfe97 Author: Rob Clark Date: Thu Apr 6 11:56:23 2017 -0400 nir/print: add compute shader info Signed-off-by: Rob Clark Reviewed-by: Alejandro Piñeiro --- src/compiler/nir/nir_print.c | 13 + 1 file changed, 13 insertions(+) diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c index af10555712..e6c5c9c830 100644 --- a/src/compiler/nir/nir_print.c +++ b/src/compiler/nir/nir_print.c @@ -1169,6 +1169,19 @@ nir_print_shader_annotated(nir_shader *shader, FILE *fp, if (shader->info->label) fprintf(fp, "label: %s\n", shader->info->label); + switch (shader->stage) { + case MESA_SHADER_COMPUTE: + fprintf(fp, "local-size: %u, %u, %u%s\n", + shader->info->cs.local_size[0], + shader->info->cs.local_size[1], + shader->info->cs.local_size[2], + shader->info->cs.local_size_variable ? " (variable)" : ""); + fprintf(fp, "shared-size: %u\n", shader->info->cs.shared_size); + break; + default: + break; + } + fprintf(fp, "inputs: %u\n", shader->num_inputs); fprintf(fp, "outputs: %u\n", shader->num_outputs); fprintf(fp, "uniforms: %u\n", shader->num_uniforms); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): freedreno/ir3: convert dynamic arrays to ralloc
Module: Mesa Branch: master Commit: 331bd3b5e10f189b1e8cd6fdf087a892efa9a6b8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=331bd3b5e10f189b1e8cd6fdf087a892efa9a6b8 Author: Rob Clark Date: Tue Apr 4 20:22:57 2017 -0400 freedreno/ir3: convert dynamic arrays to ralloc Want to move one of these under ir3_block, so that gives a reason to migrate the remaining malloc/realloc to ralloc. Signed-off-by: Rob Clark --- src/gallium/drivers/freedreno/ir3/ir3.c | 10 ++ src/gallium/drivers/freedreno/ir3/ir3.h | 4 ++-- src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c | 8 3 files changed, 8 insertions(+), 14 deletions(-) diff --git a/src/gallium/drivers/freedreno/ir3/ir3.c b/src/gallium/drivers/freedreno/ir3/ir3.c index 7c925ee7cb..c5a030282d 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3.c +++ b/src/gallium/drivers/freedreno/ir3/ir3.c @@ -63,12 +63,6 @@ struct ir3 * ir3_create(struct ir3_compiler *compiler, void ir3_destroy(struct ir3 *shader) { - /* TODO convert the dynamic array to ralloc too: */ - free(shader->indirects); - free(shader->predicates); - free(shader->baryfs); - free(shader->keeps); - free(shader->astc_srgb); ralloc_free(shader); } @@ -626,7 +620,7 @@ static void insert_instr(struct ir3_block *block, list_addtail(&instr->node, &block->instr_list); if (is_input(instr)) - array_insert(shader->baryfs, instr); + array_insert(shader, shader->baryfs, instr); } struct ir3_block * ir3_block_create(struct ir3 *shader) @@ -729,7 +723,7 @@ ir3_instr_set_address(struct ir3_instruction *instr, if (instr->address != addr) { struct ir3 *ir = instr->block->shader; instr->address = addr; - array_insert(ir->indirects, instr); + array_insert(ir, ir->indirects, instr); } } diff --git a/src/gallium/drivers/freedreno/ir3/ir3.h b/src/gallium/drivers/freedreno/ir3/ir3.h index e0d0eeebc8..c205c8fac4 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3.h +++ b/src/gallium/drivers/freedreno/ir3/ir3.h @@ -854,10 +854,10 @@ static inline unsigned ir3_cat3_absneg(opc_t opc) } } -#define array_insert(arr, val) do { \ +#define array_insert(ctx, arr, val) do { \ if (arr ## _count == arr ## _sz) { \ arr ## _sz = MAX2(2 * arr ## _sz, 16); \ - arr = realloc(arr, arr ## _sz * sizeof(arr[0])); \ + arr = reralloc_size(ctx, arr, arr ## _sz * sizeof(arr[0])); \ } \ arr[arr ##_count++] = val; \ } while (0) diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c index fd4a1d6ecc..7932a6f18a 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler_nir.c @@ -1306,9 +1306,9 @@ emit_intrinsic(struct ir3_compile *ctx, nir_intrinsic_instr *intr) cond->regs[0]->num = regid(REG_P0, 0); kill = ir3_KILL(b, cond, 0); - array_insert(ctx->ir->predicates, kill); + array_insert(ctx->ir, ctx->ir->predicates, kill); - array_insert(ctx->ir->keeps, kill); + array_insert(ctx->ir, ctx->ir->keeps, kill); ctx->so->has_kill = true; break; @@ -1583,7 +1583,7 @@ emit_tex(struct ir3_compile *ctx, nir_tex_instr *tex) sam = ir3_SAM(b, opc, type, TGSI_WRITEMASK_W, flags, tex_idx, tex_idx, col0, col1); - array_insert(ctx->ir->astc_srgb, sam); + array_insert(ctx->ir, ctx->ir->astc_srgb, sam); /* fixup .w component: */ split_dest(b, &dst[3], sam, 3, 1); @@ -1972,7 +1972,7 @@ emit_stream_out(struct ir3_compile *ctx) stg->cat6.type = TYPE_U32; stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4; - array_insert(ctx->ir->keeps, stg); + array_insert(ctx->ir, ctx->ir->keeps, stg); } } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): freedreno: enable draw/batch reordering by default
Module: Mesa Branch: master Commit: 0b613c20aa9675a2fc434742c1eed0efb572aa01 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b613c20aa9675a2fc434742c1eed0efb572aa01 Author: Rob Clark Date: Fri Apr 7 10:02:53 2017 -0400 freedreno: enable draw/batch reordering by default Probably should have flipped the switch a long time ago, since it doesn't seem to cause any problems and is a nice perf boost in a number of cases. Signed-off-by: Rob Clark --- src/gallium/drivers/freedreno/freedreno_screen.c | 4 ++-- src/gallium/drivers/freedreno/freedreno_util.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index cc6b148965..b0af139b66 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -76,7 +76,7 @@ static const struct debug_named_value debug_options[] = { {"flush", FD_DBG_FLUSH, "Force flush after every draw"}, {"deqp", FD_DBG_DEQP, "Enable dEQP hacks"}, {"nir", FD_DBG_NIR,"Prefer NIR as native IR"}, - {"reorder", FD_DBG_REORDER,"Enable reordering for draws/blits"}, + {"inorder", FD_DBG_INORDER,"Disable reordering for draws/blits"}, {"bstat", FD_DBG_BSTAT, "Print batch stats at context destroy"}, {"nogrow",FD_DBG_NOGROW, "Disable \"growable\" cmdstream buffers, even if kernel supports it"}, DEBUG_NAMED_VALUE_END @@ -707,7 +707,7 @@ fd_screen_create(struct fd_device *dev) * buffers would be too much otherwise. */ if ((screen->gpu_id >= 300) && (fd_device_version(dev) >= FD_VERSION_UNLIMITED_CMDS)) - screen->reorder = !!(fd_mesa_debug & FD_DBG_REORDER); + screen->reorder = !(fd_mesa_debug & FD_DBG_INORDER); fd_bc_init(&screen->batch_cache); diff --git a/src/gallium/drivers/freedreno/freedreno_util.h b/src/gallium/drivers/freedreno/freedreno_util.h index 08bc5d7ba4..a9b38c9375 100644 --- a/src/gallium/drivers/freedreno/freedreno_util.h +++ b/src/gallium/drivers/freedreno/freedreno_util.h @@ -77,7 +77,7 @@ enum adreno_stencil_op fd_stencil_op(unsigned op); #define FD_DBG_FLUSH0x1000 #define FD_DBG_DEQP 0x2000 #define FD_DBG_NIR 0x4000 -#define FD_DBG_REORDER 0x8000 +#define FD_DBG_INORDER 0x8000 #define FD_DBG_BSTAT 0x1 #define FD_DBG_NOGROW 0x2 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): gallium/docs: small correction about register files for atomics
Module: Mesa Branch: master Commit: 16d493f1e7a58e8e1f6e665ac5e21f1b35b1f8f1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=16d493f1e7a58e8e1f6e665ac5e21f1b35b1f8f1 Author: Rob Clark Date: Wed Apr 12 11:47:22 2017 -0400 gallium/docs: small correction about register files for atomics These can operate on MEMORY[], in addition to BUFFER[] and IMAGE[] Signed-off-by: Rob Clark Reviewed-by: Marek Olšák Reviewed-by: Nicolai Hähnle --- src/gallium/docs/source/tgsi.rst | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst index f68d349a48..89acb521ce 100644 --- a/src/gallium/docs/source/tgsi.rst +++ b/src/gallium/docs/source/tgsi.rst @@ -2553,6 +2553,8 @@ after lookup. Resource Access Opcodes ^^^ +For these opcodes, the resource can be a BUFFER, IMAGE, or MEMORY. + .. opcode:: LOAD - Fetch data from a shader buffer or image Syntax: ``LOAD dst, resource, address`` @@ -2704,8 +2706,8 @@ These opcodes provide atomic variants of some common arithmetic and logical operations. In this context atomicity means that another concurrent memory access operation that affects the same memory location is guaranteed to be performed strictly before or after the -entire execution of the atomic operation. The resource may be a buffer -or an image. In the case of an image, the offset works the same as for +entire execution of the atomic operation. The resource may be a BUFFER, +IMAGE, or MEMORY. In the case of an image, the offset works the same as for ``LOAD`` and ``STORE``, specified above. These atomic operations may only be used with 32-bit integer image formats. ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): freedreno/ir3: small re-order
Module: Mesa Branch: master Commit: b5cc88af5ecfc4872e2344832d2a7280cedcf010 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5cc88af5ecfc4872e2344832d2a7280cedcf010 Author: Rob Clark Date: Wed Apr 5 16:02:36 2017 -0400 freedreno/ir3: small re-order Small re-order of switch statement to handled op-code categories in order. Signed-off-by: Rob Clark --- src/gallium/drivers/freedreno/ir3/ir3_cp.c | 47 +++--- 1 file changed, 23 insertions(+), 24 deletions(-) diff --git a/src/gallium/drivers/freedreno/ir3/ir3_cp.c b/src/gallium/drivers/freedreno/ir3/ir3_cp.c index a9023ce571..7bb858df4d 100644 --- a/src/gallium/drivers/freedreno/ir3/ir3_cp.c +++ b/src/gallium/drivers/freedreno/ir3/ir3_cp.c @@ -111,36 +111,12 @@ static bool valid_flags(struct ir3_instruction *instr, unsigned n, if (flags & IR3_REG_RELATIV) return false; - /* clear flags that are 'ok' */ switch (opc_cat(instr->opc)) { case 1: valid_flags = IR3_REG_IMMED | IR3_REG_CONST | IR3_REG_RELATIV; if (flags & ~valid_flags) return false; break; - case 5: - /* no flags allowed */ - if (flags) - return false; - break; - case 6: - valid_flags = IR3_REG_IMMED; - if (flags & ~valid_flags) - return false; - - if (flags & IR3_REG_IMMED) { - /* doesn't seem like we can have immediate src for store -* instructions: -* -* TODO this restriction could also apply to load instructions, -* but for load instructions this arg is the address (and not -* really sure any good way to test a hard-coded immed addr src) -*/ - if (is_store(instr) && (n == 1)) - return false; - } - - break; case 2: valid_flags = ir3_cat2_absneg(instr->opc) | IR3_REG_CONST | IR3_REG_RELATIV; @@ -197,6 +173,29 @@ static bool valid_flags(struct ir3_instruction *instr, unsigned n, if (flags & (IR3_REG_SABS | IR3_REG_SNEG)) return false; break; + case 5: + /* no flags allowed */ + if (flags) + return false; + break; + case 6: + valid_flags = IR3_REG_IMMED; + if (flags & ~valid_flags) + return false; + + if (flags & IR3_REG_IMMED) { + /* doesn't seem like we can have immediate src for store +* instructions: +* +* TODO this restriction could also apply to load instructions, +* but for load instructions this arg is the address (and not +* really sure any good way to test a hard-coded immed addr src) +*/ + if (is_store(instr) && (n == 1)) + return false; + } + + break; } return true; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (17.0): 28 new commits
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e032a434fab936d9f9c47d52f3a8e0fcd50ae0f Author: Fabio Estevam Date: Sat Mar 4 19:07:27 2017 -0300 loader: Move non-error message to debug level Currently when running mesa on imx6 the following loader warnings are seen: MESA-LOADER: device is not located on the PCI bus MESA-LOADER: device is not located on the PCI bus MESA-LOADER: device is not located on the PCI bus Using display 0x1920948 with EGL version 1.4 As this is not an error message, change it to debug level in order to have a cleaner log output. Signed-off-by: Fabio Estevam Reviewed-by: Emil Velikov (cherry picked from commit 78c57726335fe22cb4579bcf562d2394adc234b5) Nominated-by: Rob Clark (IRC) URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7d3c71d649348e0454c9a1a180cfeefcbea6452 Author: Alex Smith Date: Thu Mar 30 21:03:58 2017 +0200 radv: Invalidate L2 for TRANSFER_WRITE barriers CP DMA and PKT3_WRITE_DATA (in CmdUpdateBuffer) don't (currently) write through L2. Therefore, to make these writes visible to later accesses we must invalidate L2 rather than just writing it back, to avoid the possibility that stale data is read through L2. Signed-off-by: Alex Smith Reviewed-by: Bas Nieuwenhuizen Cc: "17.0" [Bas: patch is a backport for 17.0 of the cherry-pick below] (cherry picked from commit bc5d587a80b64fb3e0a5ea8067e6317fbca2bbc5) URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a6114f0c4e619a1192062dc8dce91a67032faeb1 Author: Julien Isorce Date: Wed Mar 15 17:40:25 2017 + radeon_drm_bo: explicitly check return value of drmCommandWriteRead CID 1313492 Signed-off-by: Julien Isorce Reviewed-by: Marek Olšák (cherry picked from commit 521860b2a92bab6394546e6af8709c07e2292033) Nominated-by: Emil Velikov URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0f51d37f733f8b6ecbe444fbf2536cd403d3f285 Author: Julien Isorce Date: Mon Feb 27 13:42:17 2017 + radeon: initialize hole variable before calling container_of Like in a few other places in that radeon_drm_bo.c file. CID 715739. Signed-off-by: Julien Isorce Reviewed-by: Marek Olšák (cherry picked from commit ce27b27c38acd5a92cf45e7ddc2434f2c04191ee) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99515 Nominated-by: Mauro Rossi URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b2bcb6826ff8855e96117c9523821336a3be88a Author: Julien Isorce Date: Fri Mar 10 17:20:56 2017 + winsys/radeon: check null return from radeon_cs_create_fence in cs_flush Follow-up of patch: "radeon_cs_create_fence: check null return from radeon_winsys_bo_create" radeon_drm_cs_flush radeon_cs_create_fence radeon_winsys_bo_create Signed-off-by: Julien Isorce Signed-off-by: Marek Olšák (cherry picked from commit d08c0930af8aaef5bdf80df618bb906e0b349830) [Emil Velikov: resolve trivial conflicts] Nominated-by: Emil Velikov Signed-off-by: Emil Velikov Conflicts: src/gallium/winsys/radeon/drm/radeon_drm_cs.c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=99468c236f09211fcc4716efd400c039079c9a40 Author: Julien Isorce Date: Fri Mar 10 17:16:05 2017 + winsys/radeon: check null in radeon_cs_create_fence Fixes the following segmentation fault: radeon_drm_cs_add_buffer (bo=0x0) at radeon_drm_cs.c -> if (!bo->handle) (gdb) bt 0 radeon_drm_cs_add_buffer (bo=0x0) at radeon_drm_cs.c 1 0x7fffe73575de in radeon_cs_create_fence radeon_drm_cs.c 2 0x7fffe7358c48 in radeon_drm_cs_flush radeon_drm_cs.c Signed-off-by: Julien Isorce Signed-off-by: Marek Olšák (cherry picked from commit d09edb01468ca385b6a8ffe29ac434dc42a78d07) Nominated-by: Emil Velikov URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0a73ddda801c6cde0183735625dea95842f9c27 Author: Emil Velikov Date: Wed Apr 12 12:05:25 2017 +0100 Revert "freedreno: fix memory leak" This reverts commit c57a03585052e3bd7d61d1307cae9a922e663c20. As requested by Rob Clark "This seems to be causing a performance regression (reported by Nicolas).. and the leak it fixes is quite hypothetical. (Ie. hit by apps that destroy/create context many times.) On master, I think this can be solved by switching on 'reorder' by default but that is probably too much of a behaviour change for stable." URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f3ae08bd44533aac51134dee4c8ed94a0a86a966 Author: Jerome Duval Date: Wed Feb 22 16:02:51 2017 + haiku/winsys: fix dt prototype args Add the missing front_private, introduced with earlier commit. (cherry picked from commit 62e27170a7f7a90091b4
Mesa (master): radv: report timestampPeriod correctly
Module: Mesa Branch: master Commit: 1b2fe7ce45a508fa080e6bf93b820e6217beed83 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b2fe7ce45a508fa080e6bf93b820e6217beed83 Author: Grazvydas Ignotas Date: Fri Apr 14 20:00:26 2017 +0300 radv: report timestampPeriod correctly The kernel returns frequency in kHz, so to convert to nanosecond interval that Vulkan uses the dividend should be 100.0 and not 10.0. This fixes the GPU graph in DOOM and matches the amdgpu-pro blob. Fixes: f4e499ec791 "radv: add initial non-conformant radv vulkan driver" Signed-off-by: Grazvydas Ignotas Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c| 2 +- src/amd/vulkan/radv_radeon_winsys.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 8783ad4e1b..6251498364 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -653,7 +653,7 @@ void radv_GetPhysicalDeviceProperties( .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT, .maxSampleMaskWords = 1, .timestampComputeAndGraphics = false, - .timestampPeriod = 10.0 / pdevice->rad_info.clock_crystal_freq, + .timestampPeriod = 100.0 / pdevice->rad_info.clock_crystal_freq, .maxClipDistances = 8, .maxCullDistances = 8, .maxCombinedClipAndCullDistances = 8, diff --git a/src/amd/vulkan/radv_radeon_winsys.h b/src/amd/vulkan/radv_radeon_winsys.h index 9f2430f75d..f6bab7410d 100644 --- a/src/amd/vulkan/radv_radeon_winsys.h +++ b/src/amd/vulkan/radv_radeon_winsys.h @@ -95,7 +95,7 @@ struct radeon_info { uint32_tcompute_rings; uint32_tvce_fw_version; uint32_tvce_harvest_config; - uint32_tclock_crystal_freq; + uint32_tclock_crystal_freq; /* in kHz */ /* Kernel info. */ uint32_tdrm_major; /* version */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: remove irrelevant comment
Module: Mesa Branch: master Commit: bffdb434b7cc086c7bdaba27b7289dca4bae3e5e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bffdb434b7cc086c7bdaba27b7289dca4bae3e5e Author: Grazvydas Ignotas Date: Fri Apr 14 19:54:35 2017 +0300 radv: remove irrelevant comment A leftover from anv. Signed-off-by: Grazvydas Ignotas Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c index 6251498364..12040a04eb 100644 --- a/src/amd/vulkan/radv_device.c +++ b/src/amd/vulkan/radv_device.c @@ -676,7 +676,7 @@ void radv_GetPhysicalDeviceProperties( .deviceID = pdevice->rad_info.pci_id, .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU, .limits = limits, - .sparseProperties = {0}, /* Broadwell doesn't do sparse. */ + .sparseProperties = {0}, }; strcpy(pProperties->deviceName, pdevice->name); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): swr: Removed unnecessary PIPE_BIND flags from swr_is_format_supported
Module: Mesa Branch: master Commit: 91a7f0b3afaa88e787d7b80df491928e037967a4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=91a7f0b3afaa88e787d7b80df491928e037967a4 Author: Bruce Cherniak Date: Wed Apr 12 18:53:01 2017 -0500 swr: Removed unnecessary PIPE_BIND flags from swr_is_format_supported Removed unnecessary and probably wrong PIPE_BIND_SCANOUT and PIPE_BIND_SHARED flags in favor of check on single PIPE_BIND_DISPLAY_TARGET flag. Reference llvmpipe change Reviewed-by: Tim Rowley --- src/gallium/drivers/swr/swr_screen.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/gallium/drivers/swr/swr_screen.cpp b/src/gallium/drivers/swr/swr_screen.cpp index 3d3d103415..87fd898eb1 100644 --- a/src/gallium/drivers/swr/swr_screen.cpp +++ b/src/gallium/drivers/swr/swr_screen.cpp @@ -103,8 +103,7 @@ swr_is_format_supported(struct pipe_screen *screen, if (sample_count > 1) return FALSE; - if (bind - & (PIPE_BIND_DISPLAY_TARGET | PIPE_BIND_SCANOUT | PIPE_BIND_SHARED)) { + if (bind & PIPE_BIND_DISPLAY_TARGET) { if (!winsys->is_displaytarget_format_supported(winsys, bind, format)) return FALSE; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): swr: update gallium driver docs
Module: Mesa Branch: master Commit: 4dcfa83114df1026c715c2eb8a6168084fd2e5ac URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4dcfa83114df1026c715c2eb8a6168084fd2e5ac Author: Tim Rowley Date: Thu Apr 13 13:10:18 2017 -0500 swr: update gallium driver docs v2: add back scons section, mention additional built swr libraries Reviewed-by: Bruce Cherniak --- src/gallium/docs/source/drivers/openswr.rst | 2 +- src/gallium/docs/source/drivers/openswr/usage.rst | 16 +++- 2 files changed, 12 insertions(+), 6 deletions(-) diff --git a/src/gallium/docs/source/drivers/openswr.rst b/src/gallium/docs/source/drivers/openswr.rst index 84aa51f5d8..e254d7bcea 100644 --- a/src/gallium/docs/source/drivers/openswr.rst +++ b/src/gallium/docs/source/drivers/openswr.rst @@ -7,7 +7,7 @@ geometry heavy workloads there is a considerable speedup over llvmpipe, which is to be expected as the geometry frontend of llvmpipe is single threaded. -This rasterizer is x86 specific and requires AVX or AVX2. The driver +This rasterizer is x86 specific and requires AVX or above. The driver fits into the gallium framework, and reuses gallivm for doing the TGSI to vectorized llvm-IR conversion of the shader kernels. diff --git a/src/gallium/docs/source/drivers/openswr/usage.rst b/src/gallium/docs/source/drivers/openswr/usage.rst index e55b4211a5..61c30c27c4 100644 --- a/src/gallium/docs/source/drivers/openswr/usage.rst +++ b/src/gallium/docs/source/drivers/openswr/usage.rst @@ -4,8 +4,9 @@ Usage Requirements -* An x86 processor with AVX or AVX2 -* LLVM version 3.6 or later +* An x86 processor with AVX or above +* LLVM version 3.9 or later +* C++14 capable compiler Building @@ -18,13 +19,18 @@ configure time, for example: :: Using ^ -On Linux, building will create a drop-in alternative for libGL.so into:: +On Linux, building with autotools will create a drop-in alternative +for libGL.so into:: lib/gallium/libGL.so + lib/gallium/libswrAVX.so + lib/gallium/libswrAVX2.so -or:: +Alternatively, building with SCons will produce:: - build/foo/gallium/targets/libgl-xlib/libGL.so + build/linux-x86_64/gallium/targets/libgl-xlib/libGL.so + build/linux-x86_64/gallium/drivers/swr/libswrAVX.so + build/linux-x86_64/gallium/drivers/swr/libswrAVX2.so To use it set the LD_LIBRARY_PATH environment variable accordingly. ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): swr: Enable MSAA in OpenSWR software renderer
Module: Mesa Branch: master Commit: 1832ef6cd9bdce4f546128c0b77d7acd6fd898a7 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1832ef6cd9bdce4f546128c0b77d7acd6fd898a7 Author: Bruce Cherniak Date: Thu Apr 13 17:40:11 2017 -0500 swr: Enable MSAA in OpenSWR software renderer This patch enables multisample antialiasing in the OpenSWR software renderer. MSAA is a proof-of-concept/work-in-progress with bug fixes and performance on the way. We wanted to get the changes out now to allow several customers to begin experimenting with MSAA in a software renderer. So as not to impact current customers, MSAA is turned off by default - previous functionality and performance remain intact. It is easily enabled via environment variables, as described below. It has only been tested with the glx-lib winsys. The intention is to enable other state-trackers, both Windows and Linux and more fully support FBOs. There are 2 environment variables that affect behavior: * SWR_MSAA_FORCE_ENABLE - force MSAA on, for apps that are not designed for MSAA... Beware, results will vary. This is mainly for testing. * SWR_MSAA_MAX_SAMPLE_COUNT - sets maximum supported number of samples (1,2,4,8,16), or 0 to disable MSAA altogether. (The default is currently 0.) Reviewed-by: George Kyriazis --- src/gallium/drivers/swr/swr_context.cpp | 90 +- src/gallium/drivers/swr/swr_context.h | 3 + src/gallium/drivers/swr/swr_resource.h | 4 + src/gallium/drivers/swr/swr_screen.cpp | 159 +--- src/gallium/drivers/swr/swr_screen.h| 8 ++ src/gallium/drivers/swr/swr_state.cpp | 74 +-- 6 files changed, 313 insertions(+), 25 deletions(-) diff --git a/src/gallium/drivers/swr/swr_context.cpp b/src/gallium/drivers/swr/swr_context.cpp index 6f46d666ac..aa5cca8e65 100644 --- a/src/gallium/drivers/swr/swr_context.cpp +++ b/src/gallium/drivers/swr/swr_context.cpp @@ -267,20 +267,104 @@ swr_resource_copy(struct pipe_context *pipe, } +/* XXX: This resolve is incomplete and suboptimal. It will be removed once the + * pipelined resolve blit works. */ +void +swr_do_msaa_resolve(struct pipe_resource *src_resource, +struct pipe_resource *dst_resource) +{ + /* This is a pretty dumb inline resolve. It only supports 8-bit formats +* (ex RGBA8/BGRA8) - which are most common display formats anyway. +*/ + + /* quick check for 8-bit and number of components */ + uint8_t bits_per_component = + util_format_get_component_bits(src_resource->format, +UTIL_FORMAT_COLORSPACE_RGB, 0); + + /* Unsupported resolve format */ + assert(src_resource->format == dst_resource->format); + assert(bits_per_component == 8); + if ((src_resource->format != dst_resource->format) || + (bits_per_component != 8)) { + return; + } + + uint8_t src_num_comps = util_format_get_nr_components(src_resource->format); + + SWR_SURFACE_STATE *src_surface = &swr_resource(src_resource)->swr; + SWR_SURFACE_STATE *dst_surface = &swr_resource(dst_resource)->swr; + + uint32_t *src, *dst, offset; + uint32_t num_samples = src_surface->numSamples; + float recip_num_samples = 1.0f / num_samples; + for (uint32_t y = 0; y < src_surface->height; y++) { + for (uint32_t x = 0; x < src_surface->width; x++) { + float r = 0.0f; + float g = 0.0f; + float b = 0.0f; + float a = 0.0f; + for (uint32_t sampleNum = 0; sampleNum < num_samples; sampleNum++) { +offset = ComputeSurfaceOffset(x, y, 0, 0, sampleNum, 0, src_surface); +src = (uint32_t *) src_surface->pBaseAddress + offset/src_num_comps; +const uint32_t sample = *src; +r += (float)((sample >> 24) & 0xff) / 255.0f * recip_num_samples; +g += (float)((sample >> 16) & 0xff) / 255.0f * recip_num_samples; +b += (float)((sample >> 8) & 0xff) / 255.0f * recip_num_samples; +a += (float)((sample ) & 0xff) / 255.0f * recip_num_samples; + } + uint32_t result = 0; + result = ((uint8_t)(r * 255.0f) & 0xff) << 24; + result |= ((uint8_t)(g * 255.0f) & 0xff) << 16; + result |= ((uint8_t)(b * 255.0f) & 0xff) << 8; + result |= ((uint8_t)(a * 255.0f) & 0xff); + offset = ComputeSurfaceOffset(x, y, 0, 0, 0, 0, src_surface); + dst = (uint32_t *) dst_surface->pBaseAddress + offset/src_num_comps; + *dst = result; + } + } +} + + static void swr_blit(struct pipe_context *pipe, const struct pipe_blit_info *blit_info) { struct swr_context *ctx = swr_context(pipe); + /* Make a copy of the const blit_info, so we can modify it */ struct pipe_blit_info info = *blit_info; - if (blit_info->render_condition_enable && !swr_check_render_cond(pipe)) + if (info.render_condition_enable && !swr_check_render_cond(pipe)) return; if (info.src.resource->nr_samples > 1 && info.dst.res
Mesa (master): swr: Align swr_context allocation to SIMD alignment.
Module: Mesa Branch: master Commit: 97bbb7b6a3afadc22ef956f507f70998629fe99a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=97bbb7b6a3afadc22ef956f507f70998629fe99a Author: Bruce Cherniak Date: Wed Apr 12 18:43:25 2017 -0500 swr: Align swr_context allocation to SIMD alignment. The context now contains SIMD vectors which must be aligned (specifically samplePositions in the rastState in the derived state). Failure to align can result in segv crash on unaligned memory access in vector instructions. Reviewed-by: Tim Rowley --- src/gallium/drivers/swr/swr_context.cpp | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/swr/swr_context.cpp b/src/gallium/drivers/swr/swr_context.cpp index 8c5a2692db..6f46d666ac 100644 --- a/src/gallium/drivers/swr/swr_context.cpp +++ b/src/gallium/drivers/swr/swr_context.cpp @@ -386,7 +386,7 @@ swr_destroy(struct pipe_context *pipe) if (screen->pipe == pipe) screen->pipe = NULL; - FREE(ctx); + AlignedFree(ctx); } @@ -452,7 +452,10 @@ swr_UpdateStatsFE(HANDLE hPrivateContext, const SWR_STATS_FE *pStats) struct pipe_context * swr_create_context(struct pipe_screen *p_screen, void *priv, unsigned flags) { - struct swr_context *ctx = CALLOC_STRUCT(swr_context); + struct swr_context *ctx = (struct swr_context *) + AlignedMalloc(sizeof(struct swr_context), KNOB_SIMD_BYTES); + memset(ctx, 0, sizeof(struct swr_context)); + ctx->blendJIT = new std::unordered_map; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv/blorp: Flush the texture cache in UpdateBuffer
Module: Mesa Branch: master Commit: 939337e49fb8a6e16f83e4e030743f91b1b05cc5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=939337e49fb8a6e16f83e4e030743f91b1b05cc5 Author: Jason Ekstrand Date: Fri Mar 31 15:33:51 2017 -0700 anv/blorp: Flush the texture cache in UpdateBuffer Reviewed-by: Lionel Landwerlin Cc: "13.0 17.0" --- src/intel/vulkan/anv_blorp.c | 7 +++ 1 file changed, 7 insertions(+) diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c index 4904ee3a5f..1755663e2a 100644 --- a/src/intel/vulkan/anv_blorp.c +++ b/src/intel/vulkan/anv_blorp.c @@ -690,12 +690,19 @@ void anv_CmdUpdateBuffer( assert(max_update_size < MAX_SURFACE_DIM * 4); + /* We're about to read data that was written from the CPU. Flush the +* texture cache so we don't get anything stale. +*/ + cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT; + while (dataSize) { const uint32_t copy_size = MIN2(dataSize, max_update_size); struct anv_state tmp_data = anv_cmd_buffer_alloc_dynamic_state(cmd_buffer, copy_size, 64); + anv_state_flush(cmd_buffer->device, tmp_data); + memcpy(tmp_data.map, pData, copy_size); int bs = 16; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel/blorp: Add a blorp_emit_dynamic macro
Module: Mesa Branch: master Commit: 4495b917e2caa1c8482f2c8e3a7fea7061f9c6a0 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4495b917e2caa1c8482f2c8e3a7fea7061f9c6a0 Author: Jason Ekstrand Date: Sat Sep 10 14:15:51 2016 -0700 intel/blorp: Add a blorp_emit_dynamic macro This makes it much easier to throw together a bit of dynamic state. It also automatically handles flushing so you don't accidentally forget. Reviewed-by: Alejandro Piñeiro --- src/intel/blorp/blorp_genX_exec.h | 114 +- 1 file changed, 50 insertions(+), 64 deletions(-) diff --git a/src/intel/blorp/blorp_genX_exec.h b/src/intel/blorp/blorp_genX_exec.h index 47febafb9b..bbc391d9f2 100644 --- a/src/intel/blorp/blorp_genX_exec.h +++ b/src/intel/blorp/blorp_genX_exec.h @@ -120,6 +120,18 @@ _blorp_combine_address(struct blorp_batch *batch, void *location, _dw ? _dw + 1 : NULL; /* Array starts at dw[1] */ \ }) +#define STRUCT_ZERO(S) ({ struct S t; memset(&t, 0, sizeof(t)); t; }) + +#define blorp_emit_dynamic(batch, state, name, align, offset) \ + for (struct state name = STRUCT_ZERO(state), \ +*_dst = blorp_alloc_dynamic_state(batch, \ + _blorp_cmd_length(state) * 4, \ + align, offset); \ +__builtin_expect(_dst != NULL, 1); \ +_blorp_cmd_pack(state)(batch, (void *)_dst, &name), \ +blorp_flush_range(batch, _dst, _blorp_cmd_length(state) * 4), \ +_dst = NULL) + /* 3DSTATE_URB * 3DSTATE_URB_VS * 3DSTATE_URB_HS @@ -846,26 +858,19 @@ static uint32_t blorp_emit_blend_state(struct blorp_batch *batch, const struct blorp_params *params) { - struct GENX(BLEND_STATE) blend; - memset(&blend, 0, sizeof(blend)); - - for (unsigned i = 0; i < params->num_draw_buffers; ++i) { - blend.Entry[i].PreBlendColorClampEnable = true; - blend.Entry[i].PostBlendColorClampEnable = true; - blend.Entry[i].ColorClampRange = COLORCLAMP_RTFORMAT; - - blend.Entry[i].WriteDisableRed = params->color_write_disable[0]; - blend.Entry[i].WriteDisableGreen = params->color_write_disable[1]; - blend.Entry[i].WriteDisableBlue = params->color_write_disable[2]; - blend.Entry[i].WriteDisableAlpha = params->color_write_disable[3]; - } - uint32_t offset; - void *state = blorp_alloc_dynamic_state(batch, - GENX(BLEND_STATE_length) * 4, - 64, &offset); - GENX(BLEND_STATE_pack)(NULL, state, &blend); - blorp_flush_range(batch, state, GENX(BLEND_STATE_length) * 4); + blorp_emit_dynamic(batch, GENX(BLEND_STATE), blend, 64, &offset) { + for (unsigned i = 0; i < params->num_draw_buffers; ++i) { + blend.Entry[i].PreBlendColorClampEnable = true; + blend.Entry[i].PostBlendColorClampEnable = true; + blend.Entry[i].ColorClampRange = COLORCLAMP_RTFORMAT; + + blend.Entry[i].WriteDisableRed = params->color_write_disable[0]; + blend.Entry[i].WriteDisableGreen = params->color_write_disable[1]; + blend.Entry[i].WriteDisableBlue = params->color_write_disable[2]; + blend.Entry[i].WriteDisableAlpha = params->color_write_disable[3]; + } + } #if GEN_GEN >= 7 blorp_emit(batch, GENX(3DSTATE_BLEND_STATE_POINTERS), sp) { @@ -889,18 +894,12 @@ static uint32_t blorp_emit_color_calc_state(struct blorp_batch *batch, const struct blorp_params *params) { - struct GENX(COLOR_CALC_STATE) cc = { 0 }; - + uint32_t offset; + blorp_emit_dynamic(batch, GENX(COLOR_CALC_STATE), cc, 64, &offset) { #if GEN_GEN <= 8 - cc.StencilReferenceValue = params->stencil_ref; + cc.StencilReferenceValue = params->stencil_ref; #endif - - uint32_t offset; - void *state = blorp_alloc_dynamic_state(batch, - GENX(COLOR_CALC_STATE_length) * 4, - 64, &offset); - GENX(COLOR_CALC_STATE_pack)(NULL, state, &cc); - blorp_flush_range(batch, state, GENX(COLOR_CALC_STATE_length) * 4); + } #if GEN_GEN >= 7 blorp_emit(batch, GENX(3DSTATE_CC_STATE_POINTERS), sp) { @@ -1126,31 +1125,25 @@ static void blorp_emit_sampler_state(struct blorp_batch *batch, const struct blorp_params *params) { - struct GENX(SAMPLER_STATE) sampler = { - .MipModeFilter = MIPFILTER_NONE, - .MagModeFilter = MAPFILTER_LINEAR, - .MinModeFilter = MAPFILTER_LINEAR, - .MinLOD = 0, - .MaxLOD = 0, - .TCXAddressControlMode = TCM_CLAMP, - .TCYAddressControlMode = TCM_CLAMP, - .TCZAddressControlMode = TCM_CLAMP, - .MaximumAnisotropy = RATIO21, - .RAddressMinFilterRoundingEnable = true, - .RAddressMagFilterRoundingEnable = true, - .VAddr
Mesa (master): anv/cmd_buffer: Flush the VF cache at the top of all primaries
Module: Mesa Branch: master Commit: e1f6fb8021bcdd407fae77917502891b9239f53c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e1f6fb8021bcdd407fae77917502891b9239f53c Author: Jason Ekstrand Date: Fri Mar 31 15:33:39 2017 -0700 anv/cmd_buffer: Flush the VF cache at the top of all primaries Reviewed-by: Lionel Landwerlin Cc: "13.0 17.0" --- src/intel/vulkan/genX_cmd_buffer.c | 12 1 file changed, 12 insertions(+) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index b78b13d88e..7318b6b688 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -597,6 +597,18 @@ genX(BeginCommandBuffer)( genX(cmd_buffer_emit_state_base_address)(cmd_buffer); + /* We sometimes store vertex data in the dynamic state buffer for blorp +* operations and our dynamic state stream may re-use data from previous +* command buffers. In order to prevent stale cache data, we flush the VF +* cache. We could do this on every blorp call but that's not really +* needed as all of the data will get written by the CPU prior to the GPU +* executing anything. The chances are fairly high that they will use +* blorp at least once per primary command buffer so it shouldn't be +* wasted. +*/ + if (cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY) + cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_VF_CACHE_INVALIDATE_BIT; + VkResult result = VK_SUCCESS; if (cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT) { ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv: Limit VkDeviceMemory objects to 2GB
Module: Mesa Branch: master Commit: 475bab0330fd947db0e9a67771632e0da5631030 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=475bab0330fd947db0e9a67771632e0da5631030 Author: Jason Ekstrand Date: Tue Apr 11 08:33:19 2017 -0700 anv: Limit VkDeviceMemory objects to 2GB Reviewed-by: Juan A. Suarez Romero --- src/intel/vulkan/anv_device.c | 20 1 file changed, 20 insertions(+) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 35ef4c486b..ee9c48fa73 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -1539,6 +1539,26 @@ VkResult anv_AllocateMemory( assert(pAllocateInfo->memoryTypeIndex == 0 || (!device->info.has_llc && pAllocateInfo->memoryTypeIndex < 2)); + /* The kernel relocation API has a limitation of a 32-bit delta value +* applied to the address before it is written which, in spite of it being +* unsigned, is treated as signed . Because of the way that this maps to +* the Vulkan API, we cannot handle an offset into a buffer that does not +* fit into a signed 32 bits. The only mechanism we have for dealing with +* this at the moment is to limit all VkDeviceMemory objects to a maximum +* of 2GB each. The Vulkan spec allows us to do this: +* +*"Some platforms may have a limit on the maximum size of a single +*allocation. For example, certain systems may fail to create +*allocations with a size greater than or equal to 4GB. Such a limit is +*implementation-dependent, and if such a failure occurs then the error +*VK_ERROR_OUT_OF_DEVICE_MEMORY should be returned." +* +* We don't use vk_error here because it's not an error so much as an +* indication to the application that the allocation is too large. +*/ + if (pAllocateInfo->allocationSize > (1ull << 31)) + return VK_ERROR_OUT_OF_DEVICE_MEMORY; + /* FINISHME: Fail if allocation request exceeds heap size. */ mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): configure.ac: add --enable-sanitize option
Module: Mesa Branch: master Commit: 8b5d477aa820e52ed622c329933550c561ab1c93 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b5d477aa820e52ed622c329933550c561ab1c93 Author: Nicolai Hähnle Date: Mon Apr 3 11:17:48 2017 +0200 configure.ac: add --enable-sanitize option Enable code sanitizers by adding -fsanitize=$foo flags for the compiler and linker. In addition, this also disables checking for undefined symbols: running the address sanitizer requires additional symbols which should be provided by a preloaded libasan.so (preloaded for hooking into malloc & friends globally), and the undefined symbols check gets tripped up by that. Running the tests works normally via `make check`, but shows additional failures with the address sanitizer due to memory leaks that seem to be mostly leaks in the tests themselves. I believe those failures should really be fixed. In the mean-time, you can set export ASAN_OPTIONS=detect_leaks=0 to only check for more serious error types. v2: - fail reasonably when an unsupported sanitize flag is given (Eric Engestrom) Reviewed-by: Bartosz Tomczyk (v1) Reviewed-by: Eric Engestrom Reviewed-by: Emil Velikov --- configure.ac | 28 +++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 7246c6017a..957991cef7 100644 --- a/configure.ac +++ b/configure.ac @@ -515,6 +515,12 @@ AC_ARG_ENABLE([profile], [enable_profile=no] ) +AC_ARG_ENABLE([sanitize], +[AS_HELP_STRING([--enable-sanitize@<:@=address|undefined@:>@], +[enable code sanitizer @<:@default=disabled@:>@])], +[enable_sanitize="$enableval"], +[enable_sanitize=no]) + if test "x$enable_profile" = xyes; then DEFINES="$DEFINES -DPROFILE" if test "x$GCC" = xyes; then @@ -550,6 +556,21 @@ else DEFINES="$DEFINES -DNDEBUG" fi +if test "x$enable_sanitize" != xno; then +if test "x$enable_profile" = xyes; then +AC_MSG_WARN([Sanitize and Profile are enabled at the same time]) +fi + +CFLAGS="$CFLAGS -fsanitize=$enable_sanitize" +CXXFLAGS="$CXXFLAGS -fsanitize=$enable_sanitize" +LDFLAGS="$LDFLAGS -fsanitize=$enable_sanitize" + +AC_LINK_IFELSE( +[AC_LANG_SOURCE([int main(){return 0;}])], +[], +[AC_MSG_FAILURE([sanitize flags '$enable_sanitize' not supported])]) +fi + dnl dnl Check if linker supports -Bsymbolic dnl @@ -590,7 +611,12 @@ case "$host_os" in openbsd* | darwin* ) LD_NO_UNDEFINED="" ;; *) -LD_NO_UNDEFINED="-Wl,--no-undefined" ;; +if test "x$enable_sanitize" = xno; then +LD_NO_UNDEFINED="-Wl,--no-undefined" +else +LD_NO_UNDEFINED="" +fi +;; esac AC_SUBST([LD_NO_UNDEFINED]) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): tgsi: clarify TGSI_SEMANTIC_{LAYER,VIEWPORT_INDEX}
Module: Mesa Branch: master Commit: f3d2cf6c1ff6ccf16c2a471f8f05c4ed5a734ae4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f3d2cf6c1ff6ccf16c2a471f8f05c4ed5a734ae4 Author: Nicolai Hähnle Date: Thu Apr 13 22:13:55 2017 +0200 tgsi: clarify TGSI_SEMANTIC_{LAYER,VIEWPORT_INDEX} Depending on pipe caps they can be writable in all vertex processing stages, but only the output of the last stage counts. Reviewed-by: Marek Olšák Reviewed-by: Edward O'Callaghan --- src/gallium/docs/source/tgsi.rst | 10 ++ 1 file changed, 10 insertions(+) diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst index 89acb521ce..e740476ff0 100644 --- a/src/gallium/docs/source/tgsi.rst +++ b/src/gallium/docs/source/tgsi.rst @@ -3212,6 +3212,11 @@ For geometry shaders, this semantic label indicates that an output contains the index of the viewport (and scissor) to use. This is an integer value, and only the X component is used. +If PIPE_CAP_TGSI_VS_LAYER_VIEWPORT or PIPE_CAP_TGSI_TES_LAYER_VIEWPORT is +supported, then this semantic label can also be used in vertex or +tessellation evaluation shaders, respectively. Only the value written in the +last vertex processing stage is used. + TGSI_SEMANTIC_LAYER """ @@ -3221,6 +3226,11 @@ contains the layer value to use for the color and depth/stencil surfaces. This is an integer value, and only the X component is used. (Also known as rendertarget array index.) +If PIPE_CAP_TGSI_VS_LAYER_VIEWPORT or PIPE_CAP_TGSI_TES_LAYER_VIEWPORT is +supported, then this semantic label can also be used in vertex or +tessellation evaluation shaders, respectively. Only the value written in the +last vertex processing stage is used. + TGSI_SEMANTIC_CULLDIST "" ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): gallium: add PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
Module: Mesa Branch: master Commit: 17f24a9b752fa3f7a412ca05ae7029d142785e59 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=17f24a9b752fa3f7a412ca05ae7029d142785e59 Author: Nicolai Hähnle Date: Thu Apr 13 21:54:54 2017 +0200 gallium: add PIPE_CAP_TGSI_TES_LAYER_VIEWPORT Reviewed-by: Marek Olšák Reviewed-by: Edward O'Callaghan --- src/gallium/docs/source/screen.rst | 3 +++ src/gallium/drivers/etnaviv/etnaviv_screen.c | 1 + src/gallium/drivers/freedreno/freedreno_screen.c | 1 + src/gallium/drivers/i915/i915_screen.c | 1 + src/gallium/drivers/llvmpipe/lp_screen.c | 1 + src/gallium/drivers/nouveau/nv30/nv30_screen.c | 1 + src/gallium/drivers/nouveau/nv50/nv50_screen.c | 1 + src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 1 + src/gallium/drivers/r300/r300_screen.c | 1 + src/gallium/drivers/r600/r600_pipe.c | 1 + src/gallium/drivers/radeonsi/si_pipe.c | 1 + src/gallium/drivers/softpipe/sp_screen.c | 1 + src/gallium/drivers/svga/svga_screen.c | 1 + src/gallium/drivers/swr/swr_screen.cpp | 1 + src/gallium/drivers/vc4/vc4_screen.c | 1 + src/gallium/drivers/virgl/virgl_screen.c | 1 + src/gallium/include/pipe/p_defines.h | 1 + 17 files changed, 19 insertions(+) diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst index c1b2982283..bb2803a40c 100644 --- a/src/gallium/docs/source/screen.rst +++ b/src/gallium/docs/source/screen.rst @@ -386,6 +386,9 @@ The integer capabilities: most 64KB. * ``PIPE_CAP_TGSI_BALLOT``: Whether the BALLOT and READ_* opcodes as well as the SUBGROUP_* semantics are supported. +* ``PIPE_CAP_TGSI_TES_LAYER_VIEWPORT``: Whether ``TGSI_SEMANTIC_LAYER`` and + ``TGSI_SEMANTIC_VIEWPORT_INDEX`` are supported as tessellation evaluation + shader outputs. .. _pipe_capf: diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c b/src/gallium/drivers/etnaviv/etnaviv_screen.c index 8a0051dfa6..55d22c6aba 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_screen.c +++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c @@ -249,6 +249,7 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: case PIPE_CAP_TGSI_BALLOT: + case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: return 0; /* Stream output. */ diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index b0af139b66..9b3ca4d51b 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -306,6 +306,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: case PIPE_CAP_TGSI_BALLOT: + case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: return 0; case PIPE_CAP_MAX_VIEWPORTS: diff --git a/src/gallium/drivers/i915/i915_screen.c b/src/gallium/drivers/i915/i915_screen.c index ce5348a4b3..139b5d8963 100644 --- a/src/gallium/drivers/i915/i915_screen.c +++ b/src/gallium/drivers/i915/i915_screen.c @@ -305,6 +305,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap) case PIPE_CAP_TGSI_CLOCK: case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: case PIPE_CAP_TGSI_BALLOT: + case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: return 0; case PIPE_CAP_MAX_VIEWPORTS: diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c index 5fe6ae5083..85449ab490 100644 --- a/src/gallium/drivers/llvmpipe/lp_screen.c +++ b/src/gallium/drivers/llvmpipe/lp_screen.c @@ -351,6 +351,7 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param) case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: case PIPE_CAP_TGSI_BALLOT: + case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: return 0; } /* should only get here on unhandled cases */ diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c b/src/gallium/drivers/nouveau/nv30/nv30_screen.c index 95464f7cdc..24b6b60bc6 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c @@ -215,6 +215,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE: case PIPE_CAP_TGSI_BALLOT: + case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: return 0; case PIPE_CAP_VENDOR_ID: diff --git a/src/gallium/drivers/nouveau/nv50/nv50_screen.c b/src/gallium/drivers/nouveau/nv50/nv50_screen.c index 76999495fd..f691b4766c 100644 --- a/src/gallium/drivers/nouveau/nv50/nv50_screen.c +++ b/src/gallium/drivers/nouveau/nv50/nv50_screen.c @@ -267,6 +267,7 @@ nv50_screen_get_param(struct pipe_screen *pscreen,
Mesa (master): st/mesa: enable ARB_shader_viewport_layer_array
Module: Mesa Branch: master Commit: 4127f38baece7a3f2b454c5ca8f2b7cbdefd8b38 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=4127f38baece7a3f2b454c5ca8f2b7cbdefd8b38 Author: Nicolai Hähnle Date: Thu Apr 13 21:47:00 2017 +0200 st/mesa: enable ARB_shader_viewport_layer_array Reviewed-by: Marek Olšák Reviewed-by: Edward O'Callaghan --- src/mesa/state_tracker/st_extensions.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/mesa/state_tracker/st_extensions.c b/src/mesa/state_tracker/st_extensions.c index 8b623606dc..1df2ba7616 100644 --- a/src/mesa/state_tracker/st_extensions.c +++ b/src/mesa/state_tracker/st_extensions.c @@ -1129,6 +1129,11 @@ void st_init_extensions(struct pipe_screen *screen, extensions->AMD_vertex_shader_viewport_index = GL_TRUE; } + if (extensions->AMD_vertex_shader_layer && + extensions->AMD_vertex_shader_viewport_index && + screen->get_param(screen, PIPE_CAP_TGSI_TES_LAYER_VIEWPORT)) + extensions->ARB_shader_viewport_layer_array = GL_TRUE; + /* ARB_framebuffer_no_attachments */ if (screen->get_param(screen, PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT) && ((consts->MaxSamples >= 4 && consts->MaxFramebufferLayers >= 2048) || ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): gallium/ddebug: dump missing members of pipe_draw_info
Module: Mesa Branch: master Commit: d15b1f6e2d8b250656e7023d48cdfd623511154e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d15b1f6e2d8b250656e7023d48cdfd623511154e Author: Nicolai Hähnle Date: Fri Apr 7 16:14:52 2017 +0200 gallium/ddebug: dump missing members of pipe_draw_info Reviewed-by: Marek Olšák --- src/gallium/auxiliary/util/u_dump_state.c | 5 + src/gallium/drivers/ddebug/dd_draw.c | 2 ++ 2 files changed, 7 insertions(+) diff --git a/src/gallium/auxiliary/util/u_dump_state.c b/src/gallium/auxiliary/util/u_dump_state.c index 06d5e788fa..105e5c4bc3 100644 --- a/src/gallium/auxiliary/util/u_dump_state.c +++ b/src/gallium/auxiliary/util/u_dump_state.c @@ -926,6 +926,8 @@ util_dump_draw_info(FILE *stream, const struct pipe_draw_info *state) util_dump_member(stream, uint, state, start_instance); util_dump_member(stream, uint, state, instance_count); + util_dump_member(stream, uint, state, drawid); + util_dump_member(stream, uint, state, vertices_per_patch); util_dump_member(stream, int, state, index_bias); @@ -939,6 +941,9 @@ util_dump_draw_info(FILE *stream, const struct pipe_draw_info *state) util_dump_member(stream, ptr, state, indirect); util_dump_member(stream, uint, state, indirect_offset); + util_dump_member(stream, uint, state, indirect_stride); + util_dump_member(stream, uint, state, indirect_count); + util_dump_member(stream, uint, state, indirect_params_offset); util_dump_struct_end(stream); } diff --git a/src/gallium/drivers/ddebug/dd_draw.c b/src/gallium/drivers/ddebug/dd_draw.c index 5cbc2b9e48..6e96c7247a 100644 --- a/src/gallium/drivers/ddebug/dd_draw.c +++ b/src/gallium/drivers/ddebug/dd_draw.c @@ -220,6 +220,8 @@ dd_dump_draw_vbo(struct dd_draw_state *dstate, struct pipe_draw_info *info, FILE count_from_stream_output); if (info->indirect) DUMP_M(resource, info, indirect); + if (info->indirect_params) + DUMP_M(resource, info, indirect_params); fprintf(f, "\n"); /* TODO: dump active queries */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: handle ignored LAYER and VIEWPORT_INDEX writes
Module: Mesa Branch: master Commit: d5e53f348ea97c3ee6d843fd3b4cfa8afdf24818 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5e53f348ea97c3ee6d843fd3b4cfa8afdf24818 Author: Nicolai Hähnle Date: Thu Apr 13 22:14:20 2017 +0200 radeonsi: handle ignored LAYER and VIEWPORT_INDEX writes Reviewed-by: Marek Olšák Reviewed-by: Edward O'Callaghan --- src/gallium/drivers/radeonsi/si_shader.c | 20 1 file changed, 20 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index 0bda187cfd..00264b5796 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -2686,6 +2686,26 @@ static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base) LLVMValueRef *out_ptr = ctx->outputs[i]; unsigned name = info->output_semantic_name[i]; unsigned index = info->output_semantic_index[i]; + + /* The ARB_shader_viewport_layer_array spec contains the +* following issue: +* +*2) What happens if gl_ViewportIndex or gl_Layer is +*written in the vertex shader and a geometry shader is +*present? +* +*RESOLVED: The value written by the last vertex processing +*stage is used. If the last vertex processing stage +*(vertex, tessellation evaluation or geometry) does not +*statically assign to gl_ViewportIndex or gl_Layer, index +*or layer zero is assumed. +* +* So writes to those outputs in VS-as-LS are simply ignored. +*/ + if (name == TGSI_SEMANTIC_LAYER || + name == TGSI_SEMANTIC_VIEWPORT_INDEX) + continue; + int param = si_shader_io_get_unique_index(name, index); LLVMValueRef dw_addr = LLVMBuildAdd(gallivm->builder, base_dw_addr, LLVMConstInt(ctx->i32, param * 4, 0), ""); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: cope with missing disassembly
Module: Mesa Branch: master Commit: d6588d9962e8bf3965f2d333101ea8179a176d19 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6588d9962e8bf3965f2d333101ea8179a176d19 Author: Nicolai Hähnle Date: Fri Mar 31 13:03:03 2017 +0200 radeonsi: cope with missing disassembly For robustness and testing purposes. Reviewed-by: Marek Olšák --- src/gallium/drivers/radeonsi/si_state_shaders.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c b/src/gallium/drivers/radeonsi/si_state_shaders.c index 78c7495ce8..c52ffd90f7 100644 --- a/src/gallium/drivers/radeonsi/si_state_shaders.c +++ b/src/gallium/drivers/radeonsi/si_state_shaders.c @@ -113,7 +113,8 @@ static void *si_get_shader_binary(struct si_shader *shader) /* There is always a size of data followed by the data itself. */ unsigned relocs_size = shader->binary.reloc_count * sizeof(shader->binary.relocs[0]); - unsigned disasm_size = strlen(shader->binary.disasm_string) + 1; + unsigned disasm_size = shader->binary.disasm_string ? + strlen(shader->binary.disasm_string) + 1 : 0; unsigned llvm_ir_size = shader->binary.llvm_ir_string ? strlen(shader->binary.llvm_ir_string) + 1 : 0; unsigned size = ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: enable ARB_shader_viewport_layer_array
Module: Mesa Branch: master Commit: 2ac03e90fb653944d985b513ecf5240cff2e680a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ac03e90fb653944d985b513ecf5240cff2e680a Author: Nicolai Hähnle Date: Thu Apr 13 22:16:26 2017 +0200 radeonsi: enable ARB_shader_viewport_layer_array Reviewed-by: Marek Olšák Reviewed-by: Edward O'Callaghan --- docs/features.txt | 2 +- docs/relnotes/17.1.0.html | 1 + src/gallium/drivers/radeonsi/si_pipe.c | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/docs/features.txt b/docs/features.txt index a2d7785827..7ca5fd3015 100644 --- a/docs/features.txt +++ b/docs/features.txt @@ -297,7 +297,7 @@ Khronos, ARB, and OES extensions that are not part of any OpenGL or OpenGL ES ve GL_ARB_shader_draw_parameters DONE (i965, nvc0, radeonsi) GL_ARB_shader_group_vote DONE (nvc0, radeonsi) GL_ARB_shader_stencil_export DONE (i965/gen9+, radeonsi, softpipe, llvmpipe, swr) - GL_ARB_shader_viewport_layer_arrayDONE (i965/gen6+) + GL_ARB_shader_viewport_layer_arrayDONE (i965/gen6+, radeonsi) GL_ARB_sparse_buffer DONE (radeonsi/CIK+) GL_ARB_sparse_texture not started GL_ARB_sparse_texture2not started diff --git a/docs/relnotes/17.1.0.html b/docs/relnotes/17.1.0.html index 8f237ed527..82086d59c1 100644 --- a/docs/relnotes/17.1.0.html +++ b/docs/relnotes/17.1.0.html @@ -48,6 +48,7 @@ Note: some of the new features are only available with certain drivers. GL_ARB_shader_ballot on nvc0, radeonsi GL_ARB_shader_clock on nv50, nvc0, radeonsi GL_ARB_shader_group_vote on radeonsi +GL_ARB_shader_viewport_layer_array on radeonsi GL_ARB_sparse_buffer on radeonsi/CIK+ GL_ARB_transform_feedback2 on i965/gen6 GL_ARB_transform_feedback_overflow_query on i965/gen6+ diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index 29552499d5..f0e24c29cb 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -421,6 +421,7 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS: case PIPE_CAP_DOUBLES: case PIPE_CAP_TGSI_TEX_TXF_LZ: + case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: return 1; case PIPE_CAP_INT64: @@ -506,7 +507,6 @@ static int si_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_TGSI_MUL_ZERO_WINS: case PIPE_CAP_UMA: case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE: - case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT: return 0; case PIPE_CAP_QUERY_BUFFER_OBJECT: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv/blorp: Properly handle VK_ATTACHMENT_UNUSED
Module: Mesa Branch: master Commit: 220974b38dfcd557f4a6bc723e4b5d15add39f84 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=220974b38dfcd557f4a6bc723e4b5d15add39f84 Author: Jason Ekstrand Date: Thu Apr 6 14:15:55 2017 -0700 anv/blorp: Properly handle VK_ATTACHMENT_UNUSED The Vulkan driver was originally written under the assumption that VK_ATTACHMENT_UNUSED was basically just for depth-stencil attachments. However, the way things fell together, VK_ATTACHMENT_UNUSED can be used anywhere in the subpass description. The blorp-based clear and resolve code has a bunch of places where we walk lists of attachments and we weren't handling VK_ATTACHMENT_UNUSED everywhere. This commit should fix all of them. Reviewed-by: Nanley Chery Cc: --- src/intel/vulkan/anv_blorp.c | 27 ++- 1 file changed, 22 insertions(+), 5 deletions(-) diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c index 1755663e2a..257ed9bbcf 100644 --- a/src/intel/vulkan/anv_blorp.c +++ b/src/intel/vulkan/anv_blorp.c @@ -1108,14 +1108,19 @@ subpass_needs_clear(const struct anv_cmd_buffer *cmd_buffer) for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) { uint32_t a = cmd_state->subpass->color_attachments[i].attachment; + if (a == VK_ATTACHMENT_UNUSED) + continue; + + assert(a < cmd_state->pass->attachment_count); if (cmd_state->attachments[a].pending_clear_aspects) { return true; } } - if (ds != VK_ATTACHMENT_UNUSED && - cmd_state->attachments[ds].pending_clear_aspects) { - return true; + if (ds != VK_ATTACHMENT_UNUSED) { + assert(ds < cmd_state->pass->attachment_count); + if (cmd_state->attachments[ds].pending_clear_aspects) + return true; } return false; @@ -1147,6 +1152,10 @@ anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer) struct anv_framebuffer *fb = cmd_buffer->state.framebuffer; for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) { const uint32_t a = cmd_state->subpass->color_attachments[i].attachment; + if (a == VK_ATTACHMENT_UNUSED) + continue; + + assert(a < cmd_state->pass->attachment_count); struct anv_attachment_state *att_state = &cmd_state->attachments[a]; if (!att_state->pending_clear_aspects) @@ -1206,6 +1215,7 @@ anv_cmd_buffer_clear_subpass(struct anv_cmd_buffer *cmd_buffer) } const uint32_t ds = cmd_state->subpass->depth_stencil_attachment.attachment; + assert(ds == VK_ATTACHMENT_UNUSED || ds < cmd_state->pass->attachment_count); if (ds != VK_ATTACHMENT_UNUSED && cmd_state->attachments[ds].pending_clear_aspects) { @@ -1520,8 +1530,12 @@ anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer) blorp_batch_init(&cmd_buffer->device->blorp, &batch, cmd_buffer, 0); for (uint32_t i = 0; i < subpass->color_count; ++i) { - ccs_resolve_attachment(cmd_buffer, &batch, - subpass->color_attachments[i].attachment); + const uint32_t att = subpass->color_attachments[i].attachment; + if (att == VK_ATTACHMENT_UNUSED) + continue; + + assert(att < cmd_buffer->state.pass->attachment_count); + ccs_resolve_attachment(cmd_buffer, &batch, att); } if (subpass->has_resolve) { @@ -1540,6 +1554,9 @@ anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer *cmd_buffer) if (dst_att == VK_ATTACHMENT_UNUSED) continue; + assert(src_att < cmd_buffer->state.pass->attachment_count); + assert(dst_att < cmd_buffer->state.pass->attachment_count); + if (cmd_buffer->state.attachments[dst_att].pending_clear_aspects) { /* From the Vulkan 1.0 spec: * ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv/cmd_buffer: Use the null surface state for ATTACHMENT_UNUSED
Module: Mesa Branch: master Commit: 21d2ca72d88e00ddf37c7e1030472e184a038195 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=21d2ca72d88e00ddf37c7e1030472e184a038195 Author: Jason Ekstrand Date: Fri Apr 7 10:33:25 2017 -0700 anv/cmd_buffer: Use the null surface state for ATTACHMENT_UNUSED Reviewed-by: Nanley Chery Cc: --- src/intel/vulkan/genX_cmd_buffer.c | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index fcebd4d006..13baf76b7e 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -1122,8 +1122,20 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer, assert(stage == MESA_SHADER_FRAGMENT); assert(binding->binding == 0); if (binding->index < subpass->color_count) { -const unsigned att = subpass->color_attachments[binding->index].attachment; -surface_state = cmd_buffer->state.attachments[att].color_rt_state; +const unsigned att = + subpass->color_attachments[binding->index].attachment; + +/* From the Vulkan 1.0.46 spec: + * + *"If any color or depth/stencil attachments are + *VK_ATTACHMENT_UNUSED, then no writes occur for those + *attachments." + */ +if (att == VK_ATTACHMENT_UNUSED) { + surface_state = cmd_buffer->state.null_surface_state; +} else { + surface_state = cmd_buffer->state.attachments[att].color_rt_state; +} } else { surface_state = cmd_buffer->state.null_surface_state; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): anv/cmd_buffer: Always set up a null surface state
Module: Mesa Branch: master Commit: 02eca8b6f897a0c7ab5f2a6ff5d204cf379681f6 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=02eca8b6f897a0c7ab5f2a6ff5d204cf379681f6 Author: Jason Ekstrand Date: Fri Apr 7 10:31:01 2017 -0700 anv/cmd_buffer: Always set up a null surface state We're about to start requiring it in yet another case and calculating exactly when one is needed is starting to get prohibitively expensive. A single surface state doesn't take up that much space so we may as well create one all the time. Reviewed-by: Nanley Chery Cc: --- src/intel/vulkan/genX_cmd_buffer.c | 50 +++--- 1 file changed, 19 insertions(+), 31 deletions(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 7318b6b688..fcebd4d006 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -411,23 +411,15 @@ genX(cmd_buffer_setup_attachments)(struct anv_cmd_buffer *cmd_buffer, VK_ERROR_OUT_OF_HOST_MEMORY); } - bool need_null_state = false; - unsigned num_states = 0; + /* Reserve one for the NULL state. */ + unsigned num_states = 1; for (uint32_t i = 0; i < pass->attachment_count; ++i) { - if (vk_format_is_color(pass->attachments[i].format)) { + if (vk_format_is_color(pass->attachments[i].format)) num_states++; - } else { - /* We need a null state for any depth-stencil-only subpasses. - * Importantly, this includes depth/stencil clears so we create one - * whenever we have depth or stencil - */ - need_null_state = true; - } if (need_input_attachment_state(&pass->attachments[i])) num_states++; } - num_states += need_null_state; const uint32_t ss_stride = align_u32(isl_dev->ss.size, isl_dev->ss.align); state->render_pass_states = @@ -437,11 +429,9 @@ genX(cmd_buffer_setup_attachments)(struct anv_cmd_buffer *cmd_buffer, struct anv_state next_state = state->render_pass_states; next_state.alloc_size = isl_dev->ss.size; - if (need_null_state) { - state->null_surface_state = next_state; - next_state.offset += ss_stride; - next_state.map += ss_stride; - } + state->null_surface_state = next_state; + next_state.offset += ss_stride; + next_state.map += ss_stride; for (uint32_t i = 0; i < pass->attachment_count; ++i) { if (vk_format_is_color(pass->attachments[i].format)) { @@ -463,24 +453,22 @@ genX(cmd_buffer_setup_attachments)(struct anv_cmd_buffer *cmd_buffer, ANV_FROM_HANDLE(anv_framebuffer, framebuffer, begin->framebuffer); assert(pass->attachment_count == framebuffer->attachment_count); - if (need_null_state) { - struct GENX(RENDER_SURFACE_STATE) null_ss = { -.SurfaceType = SURFTYPE_NULL, -.SurfaceArray = framebuffer->layers > 0, -.SurfaceFormat = ISL_FORMAT_R8G8B8A8_UNORM, + struct GENX(RENDER_SURFACE_STATE) null_ss = { + .SurfaceType = SURFTYPE_NULL, + .SurfaceArray = framebuffer->layers > 0, + .SurfaceFormat = ISL_FORMAT_R8G8B8A8_UNORM, #if GEN_GEN >= 8 -.TileMode = YMAJOR, + .TileMode = YMAJOR, #else -.TiledSurface = true, + .TiledSurface = true, #endif -.Width = framebuffer->width - 1, -.Height = framebuffer->height - 1, -.Depth = framebuffer->layers - 1, -.RenderTargetViewExtent = framebuffer->layers - 1, - }; - GENX(RENDER_SURFACE_STATE_pack)(NULL, state->null_surface_state.map, - &null_ss); - } + .Width = framebuffer->width - 1, + .Height = framebuffer->height - 1, + .Depth = framebuffer->layers - 1, + .RenderTargetViewExtent = framebuffer->layers - 1, + }; + GENX(RENDER_SURFACE_STATE_pack)(NULL, state->null_surface_state.map, + &null_ss); for (uint32_t i = 0; i < pass->attachment_count; ++i) { struct anv_render_pass_attachment *att = &pass->attachments[i]; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: remove the temp descriptor set infrastructure
Module: Mesa Branch: master Commit: c1dd5d0b01e7d4a74b408ad834f84d1914779a44 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c1dd5d0b01e7d4a74b408ad834f84d1914779a44 Author: Fredrik Höglund Date: Fri Apr 14 00:27:00 2017 +0200 radv: remove the temp descriptor set infrastructure It is no longer used. Signed-off-by: Fredrik Höglund Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_descriptor_set.c | 94 +++- src/amd/vulkan/radv_private.h| 10 2 files changed, 28 insertions(+), 76 deletions(-) diff --git a/src/amd/vulkan/radv_descriptor_set.c b/src/amd/vulkan/radv_descriptor_set.c index f585061b4f..48cb8c2a30 100644 --- a/src/amd/vulkan/radv_descriptor_set.c +++ b/src/amd/vulkan/radv_descriptor_set.c @@ -257,7 +257,6 @@ void radv_DestroyPipelineLayout( static VkResult radv_descriptor_set_create(struct radv_device *device, struct radv_descriptor_pool *pool, - struct radv_cmd_buffer *cmd_buffer, const struct radv_descriptor_set_layout *layout, struct radv_descriptor_set **out_set) { @@ -288,51 +287,38 @@ radv_descriptor_set_create(struct radv_device *device, if (layout->size) { uint32_t layout_size = align_u32(layout->size, 32); set->size = layout->size; - if (!cmd_buffer) { - /* try to allocate linearly first, so that we don't spend -* time looking for gaps if the app only allocates & -* resets via the pool. */ - if (pool->current_offset + layout_size <= pool->size) { - set->bo = pool->bo; - set->mapped_ptr = (uint32_t*)(pool->mapped_ptr + pool->current_offset); - set->va = device->ws->buffer_get_va(set->bo) + pool->current_offset; - pool->current_offset += layout_size; - list_addtail(&set->vram_list, &pool->vram_list); - } else { - uint64_t offset = 0; - struct list_head *prev = &pool->vram_list; - struct radv_descriptor_set *cur; - LIST_FOR_EACH_ENTRY(cur, &pool->vram_list, vram_list) { - uint64_t start = (uint8_t*)cur->mapped_ptr - pool->mapped_ptr; - if (start - offset >= layout_size) - break; - - offset = start + cur->size; - prev = &cur->vram_list; - } - if (pool->size - offset < layout_size) { - vk_free2(&device->alloc, NULL, set->dynamic_descriptors); - vk_free2(&device->alloc, NULL, set); - return vk_error(VK_ERROR_OUT_OF_POOL_MEMORY_KHR); - } - set->bo = pool->bo; - set->mapped_ptr = (uint32_t*)(pool->mapped_ptr + offset); - set->va = device->ws->buffer_get_va(set->bo) + offset; - list_add(&set->vram_list, prev); - } + /* try to allocate linearly first, so that we don't spend +* time looking for gaps if the app only allocates & +* resets via the pool. */ + if (pool->current_offset + layout_size <= pool->size) { + set->bo = pool->bo; + set->mapped_ptr = (uint32_t*)(pool->mapped_ptr + pool->current_offset); + set->va = device->ws->buffer_get_va(set->bo) + pool->current_offset; + pool->current_offset += layout_size; + list_addtail(&set->vram_list, &pool->vram_list); } else { - unsigned bo_offset; - if (!radv_cmd_buffer_upload_alloc(cmd_buffer, set->size, 32, - &bo_offset, - (void**)&set->mapped_ptr)) { + uint64_t offset = 0; + struct list_head *prev = &pool->vram_list; + struct radv_descriptor_set *cur; + LIST_FOR_EACH_ENTRY(cur, &pool->vram_list, vram_list) { + uint64_t start = (uint8_t*)cur->mapped_ptr - pool->mapped_ptr; + if (start - offset >= layout_size) + break; + + offset = start + cur->siz
Mesa (master): radv: use push descriptors in meta
Module: Mesa Branch: master Commit: 5ab5d1bee4f01c56c9f87a43b82fd65473b75473 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ab5d1bee4f01c56c9f87a43b82fd65473b75473 Author: Fredrik Höglund Date: Fri Apr 14 00:26:59 2017 +0200 radv: use push descriptors in meta Use push descriptors instead of temp descriptor sets. Signed-off-by: Fredrik Höglund Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_meta_blit.c | 51 +++--- src/amd/vulkan/radv_meta_blit2d.c | 94 +-- src/amd/vulkan/radv_meta_buffer.c | 122 ++ src/amd/vulkan/radv_meta_bufimage.c | 295 +++--- src/amd/vulkan/radv_meta_resolve_cs.c | 81 +- src/amd/vulkan/radv_query.c | 74 - 6 files changed, 301 insertions(+), 416 deletions(-) diff --git a/src/amd/vulkan/radv_meta_blit.c b/src/amd/vulkan/radv_meta_blit.c index 228aefaf4b..a3256ab05c 100644 --- a/src/amd/vulkan/radv_meta_blit.c +++ b/src/amd/vulkan/radv_meta_blit.c @@ -307,31 +307,6 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer, .addressModeW = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE, }, &cmd_buffer->pool->alloc, &sampler); - VkDescriptorSet set; - radv_temp_descriptor_set_create(cmd_buffer->device, cmd_buffer, - device->meta_state.blit.ds_layout, - &set); - - radv_UpdateDescriptorSets(radv_device_to_handle(device), - 1, /* writeCount */ - (VkWriteDescriptorSet[]) { - { - .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET, - .dstSet = set, - .dstBinding = 0, - .dstArrayElement = 0, - .descriptorCount = 1, - .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER, - .pImageInfo = (VkDescriptorImageInfo[]) { - { - .sampler = sampler, - .imageView = radv_image_view_to_handle(src_iview), - .imageLayout = VK_IMAGE_LAYOUT_GENERAL, - }, - } - } - }, 0, NULL); - VkFramebuffer fb; radv_CreateFramebuffer(radv_device_to_handle(device), &(VkFramebufferCreateInfo) { @@ -439,10 +414,26 @@ meta_emit_blit(struct radv_cmd_buffer *cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline); } - radv_CmdBindDescriptorSets(radv_cmd_buffer_to_handle(cmd_buffer), - VK_PIPELINE_BIND_POINT_GRAPHICS, - device->meta_state.blit.pipeline_layout, 0, 1, - &set, 0, NULL); + radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS, + device->meta_state.blit.pipeline_layout, + 0, /* set */ + 1, /* descriptorWriteCount */ + (VkWriteDescriptorSet[]) { + { + .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET, + .dstBinding = 0, + .dstArrayElement = 0, + .descriptorCount = 1, + .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER, + .pImageInfo = (VkDescriptorImageInfo[]) { + { + .sampler = sampler, + .imageView = radv_image_view_to_handle(src_iview), + .imageLayout = VK_IMAGE_LAYOUT_GENERAL, + }, + } +
Mesa (master): radv: add private push descriptors for meta
Module: Mesa Branch: master Commit: f95caae504a894d804257674538640a9178dceb2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f95caae504a894d804257674538640a9178dceb2 Author: Fredrik Höglund Date: Fri Apr 14 00:26:58 2017 +0200 radv: add private push descriptors for meta This allows meta to use push descriptors without disturbing user push descriptors. radv_meta_push_descriptor_set differs from vkCmdPushDescriptorSetKHR in that partial updates are not supported; all descriptors used in subsequent draw commands must be pushed at the same time. Signed-off-by: Fredrik Höglund Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_cmd_buffer.c | 33 + src/amd/vulkan/radv_private.h| 8 2 files changed, 41 insertions(+) diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index f03e3dff34..31d04e535d 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -1981,6 +1981,39 @@ static bool radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer, return true; } +void radv_meta_push_descriptor_set( + struct radv_cmd_buffer* cmd_buffer, + VkPipelineBindPoint pipelineBindPoint, + VkPipelineLayout _layout, + uint32_t set, + uint32_t descriptorWriteCount, + const VkWriteDescriptorSet* pDescriptorWrites) +{ + RADV_FROM_HANDLE(radv_pipeline_layout, layout, _layout); + struct radv_descriptor_set *push_set = &cmd_buffer->meta_push_descriptors; + unsigned bo_offset; + + assert(layout->set[set].layout->flags & VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR); + + push_set->size = layout->set[set].layout->size; + push_set->layout = layout->set[set].layout; + + if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->size, 32, + &bo_offset, + (void**) &push_set->mapped_ptr)) + return; + + push_set->va = cmd_buffer->device->ws->buffer_get_va(cmd_buffer->upload.upload_bo); + push_set->va += bo_offset; + + radv_update_descriptor_sets(cmd_buffer->device, cmd_buffer, + radv_descriptor_set_to_handle(push_set), + descriptorWriteCount, pDescriptorWrites, 0, NULL); + + cmd_buffer->state.descriptors[set] = push_set; + cmd_buffer->state.descriptors_dirty |= (1 << set); +} + void radv_CmdPushDescriptorSetKHR( VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h index 2afc0cbedf..bff8845bc7 100644 --- a/src/amd/vulkan/radv_private.h +++ b/src/amd/vulkan/radv_private.h @@ -787,6 +787,7 @@ struct radv_cmd_buffer { uint32_t dynamic_buffers[4 * MAX_DYNAMIC_BUFFERS]; VkShaderStageFlags push_constant_stages; struct radv_push_descriptor_set push_descriptors; + struct radv_descriptor_set meta_push_descriptors; struct radv_cmd_buffer_upload upload; @@ -1410,6 +1411,13 @@ radv_update_descriptor_set_with_template(struct radv_device *device, VkDescriptorUpdateTemplateKHR descriptorUpdateTemplate, const void *pData); +void radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer, + VkPipelineBindPoint pipelineBindPoint, + VkPipelineLayout _layout, + uint32_t set, + uint32_t descriptorWriteCount, + const VkWriteDescriptorSet *pDescriptorWrites); + void radv_initialise_cmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image, uint32_t value); void radv_initialize_dcc(struct radv_cmd_buffer *cmd_buffer, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add missing initialization for userptr buffers
Module: Mesa Branch: master Commit: 39f51b5db9404b166fa7c1845a348f427c03a8f1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=39f51b5db9404b166fa7c1845a348f427c03a8f1 Author: Nicolai Hähnle Date: Wed Apr 12 17:05:56 2017 +0200 radeonsi: add missing initialization for userptr buffers Fix the accounting for memory usage of userptr buffers, which has been wrong forever (or at least for a long time). Also initialize flags. Without this initialization, the sparse buffer flag might end up being set, which leads to staging buffers being used unnecessarily (and incorrectly) in transfers to or from userptr buffers. This works around VM faults that occur with the radeon kernel module when running piglit ./bin/amd_pinned_memory decrement-offset map-buffer -auto Fixes: e077c5fe6579 ("gallium/radeon: transfers and invalidation for sparse buffers") Reported-by: Michel Dänzer Reviewed-by: Marek Olšák --- src/gallium/drivers/radeon/r600_buffer_common.c | 4 1 file changed, 4 insertions(+) diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c b/src/gallium/drivers/radeon/r600_buffer_common.c index 0e93404c01..b2289e26f7 100644 --- a/src/gallium/drivers/radeon/r600_buffer_common.c +++ b/src/gallium/drivers/radeon/r600_buffer_common.c @@ -612,6 +612,7 @@ r600_buffer_from_user_memory(struct pipe_screen *screen, struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ); rbuffer->domains = RADEON_DOMAIN_GTT; + rbuffer->flags = 0; util_range_add(&rbuffer->valid_buffer_range, 0, templ->width0); /* Convert a user pointer to a buffer. */ @@ -627,5 +628,8 @@ r600_buffer_from_user_memory(struct pipe_screen *screen, else rbuffer->gpu_address = 0; + rbuffer->vram_usage = 0; + rbuffer->gart_usage = templ->width0; + return &rbuffer->b.b; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): nir: Destination component count of shader_clock intrinsic is 2
Module: Mesa Branch: master Commit: ff29f488d4a2d05cdefbca7d675c479b2a1780a0 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff29f488d4a2d05cdefbca7d675c479b2a1780a0 Author: Boyan Ding Date: Wed Apr 12 21:14:22 2017 +0800 nir: Destination component count of shader_clock intrinsic is 2 This fixes the following error when using ARB_shader_clock on i965: vec1 32 ssa_0 = intrinsic shader_clock () () () intrinsic store_var (ssa_0) (clock_retval) (3) /* wrmask=xy */ error: src->ssa->num_components == num_components (nir/nir_validate.c:204) Signed-off-by: Boyan Ding Reviewed-by: Jason Ekstrand Cc: mesa-sta...@lists.freedesktop.org --- src/compiler/glsl/glsl_to_nir.cpp | 3 ++- src/compiler/nir/nir_intrinsics.h | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp index f0557f985b..870d457681 100644 --- a/src/compiler/glsl/glsl_to_nir.cpp +++ b/src/compiler/glsl/glsl_to_nir.cpp @@ -930,7 +930,8 @@ nir_visitor::visit(ir_call *ir) nir_builder_instr_insert(&b, &instr->instr); break; case nir_intrinsic_shader_clock: - nir_ssa_dest_init(&instr->instr, &instr->dest, 1, 32, NULL); + nir_ssa_dest_init(&instr->instr, &instr->dest, 2, 32, NULL); + instr->num_components = 2; nir_builder_instr_insert(&b, &instr->instr); break; case nir_intrinsic_store_ssbo: { diff --git a/src/compiler/nir/nir_intrinsics.h b/src/compiler/nir/nir_intrinsics.h index 105c56f759..3a519a73dd 100644 --- a/src/compiler/nir/nir_intrinsics.h +++ b/src/compiler/nir/nir_intrinsics.h @@ -91,7 +91,7 @@ BARRIER(memory_barrier) * The latter can be used as code motion barrier, which is currently not * feasible with NIR. */ -INTRINSIC(shader_clock, 0, ARR(0), true, 1, 0, 0, xx, xx, xx, NIR_INTRINSIC_CAN_ELIMINATE) +INTRINSIC(shader_clock, 0, ARR(0), true, 2, 0, 0, xx, xx, xx, NIR_INTRINSIC_CAN_ELIMINATE) /* * Memory barrier with semantics analogous to the compute shader ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): 30 new commits
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8973ae3162aec112b22cdf58f47d0ee12c4a09cd Author: Samuel Iglesias Gonsálvez Date: Wed Apr 5 06:23:43 2017 +0200 docs/relnotes: add GL_ARB_gpu_shader_fp64 support on i965/ivybridge Signed-off-by: Samuel Iglesias Gonsálvez Acked-by: Francisco Jerez URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef49dda2df94c8060047b845a3a027460c45ba7c Author: Samuel Iglesias Gonsálvez Date: Tue Oct 11 10:59:52 2016 +0200 docs: mark GL_ARB_gpu_shader_fp64 and OpenGL 4.0 as supported by i965/gen7+ Signed-off-by: Samuel Iglesias Gonsálvez Acked-by: Francisco Jerez URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a494afdb8e09640956743649354fbb7147231d1d Author: Samuel Iglesias Gonsálvez Date: Fri Aug 26 07:39:04 2016 +0200 i965: enable OpenGL 4.0 to Ivybridge/Baytrail Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Francisco Jerez URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd0a6b2fc2ef6e04ffb262072821113cb49cd530 Author: Samuel Iglesias Gonsálvez Date: Fri Aug 26 07:37:42 2016 +0200 i965: enable ARB_gpu_shader_fp64 for Ivybridge/Baytrail Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Francisco Jerez URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2eeb1b0ad9453ba135b72aaeec6c0d4dbf9ac87c Author: Matt Turner Date: Fri Jan 20 13:35:33 2017 -0800 i965: Use correct VertStride on align16 instructions. In commit c35fa7a, we changed the "width" of DF source registers to 2, which is conceptually fine. Unfortunately a VertStride of 2 is not allowed by align16 instructions on IVB/BYT, and the regular VertStride of 4 works fine in any case. See generated_tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/vs-round-double.shader_test for example: cmp.ge.f0(8)g18<1>DFg1<0>.xyxyDF-g8<2>DF{ align16 1Q }; ERROR: In Align16 mode, only VertStride of 0 or 4 is allowed cmp.ge.f0(8)g19<1>DFg1<0>.xyxyDF-g9<2>DF{ align16 2N }; ERROR: In Align16 mode, only VertStride of 0 or 4 is allowed v2: - Add spec quote (Curro). - Change the condition to only BRW_VERTICAL_STRIDE_2 (Curro) Reviewed-by: Samuel Iglesias Gonsálvez Reviewed-by: Francisco Jerez URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8441e2276912d353d4fc6c0cf6b781ab5153ee7 Author: Samuel Iglesias Gonsálvez Date: Fri Mar 17 11:57:25 2017 +0100 i965/vec4/dce: improve track of partial flag register writes This is required for correctness in presence of multiple 4-wide flag writes (e.g. 4-wide instructions with a conditional mod set) which update a different portion of the same 8-bit flag subregister. Right now we keep track of flag dataflow with 8-bit granularity and consider flag writes to have killed any previous definition of the same subregister even if the write was less than 8 channels wide, which can cause live flag register updates to be dead code-eliminated incorrectly. Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Francisco Jerez URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c1fc8fad47f60bda857fc45c4052c5f4effe0d84 Author: Samuel Iglesias Gonsálvez Date: Fri Mar 17 11:55:49 2017 +0100 i965/vec4: don't do horizontal stride on some register file types horiz_offset() shouldn't be doing anything for scalar registers, because all channels of any SIMD instructions will end up reading or writing the same component of the register, so shifting the register offset would be wrong. Signed-off-by: Samuel Iglesias Gonsálvez [ Francisco Jerez: Re-implement in terms of is_uniform() for simplicity. Pass argument by const reference. Clarify commit message. ] Reviewed-by: Francisco Jerez URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=21e8e3a8484241508ac2c250fc4367234fa337df Author: Matt Turner Date: Fri Jan 20 13:35:32 2017 -0800 i965/vec4: Fix exec size for MOVs {SET,PICK}_{HIGH,LOW}_32BIT. Otherwise for a pack_double_2x32_split opcode, we emit: vec1 64 ssa_135 = pack_double_2x32_split ssa_133, ssa_134 mov(8) g5<1>UD g5<4>.xUD { align16 1Q compacted }; mov(8) g7<2>UD g5<4,4,1>UD { align1 1Q }; ERROR: When the destination spans two registers, the source must span two registers (exceptions for scalar source and packed-word to packed-dword expansion) mov(8) g8<2>UD g5.4<4,4,1>UD { align1 2N }; ERROR: The offset from the two source registers must be the same mov(8) g5<1>UD g6<4>.xUD { align16 1Q compacted }; mov(8)
Mesa (master): swr: Add polygon stipple support
Module: Mesa Branch: master Commit: d7a1f01db36f32f8fbf47535d3969bcb57dae91d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7a1f01db36f32f8fbf47535d3969bcb57dae91d Author: George Kyriazis Date: Fri Mar 31 20:09:57 2017 -0500 swr: Add polygon stipple support Add polygon stipple functionality to the fragment shader. Explicitly turn off polygon stipple for lines and points, since we do them using tris. Reviewed-by: Bruce Cherniak --- src/gallium/drivers/swr/swr_context.h | 4 ++- src/gallium/drivers/swr/swr_shader.cpp | 56 ++ src/gallium/drivers/swr/swr_shader.h | 1 + src/gallium/drivers/swr/swr_state.cpp | 27 ++-- src/gallium/drivers/swr/swr_state.h| 5 +++ 5 files changed, 84 insertions(+), 9 deletions(-) diff --git a/src/gallium/drivers/swr/swr_context.h b/src/gallium/drivers/swr/swr_context.h index 233d95ab16..4de20c1c1b 100644 --- a/src/gallium/drivers/swr/swr_context.h +++ b/src/gallium/drivers/swr/swr_context.h @@ -98,6 +98,8 @@ struct swr_draw_context { float userClipPlanes[PIPE_MAX_CLIP_PLANES][4]; + uint32_t polyStipple[32]; + SWR_SURFACE_STATE renderTargets[SWR_NUM_ATTACHMENTS]; void *pStats; }; @@ -127,7 +129,7 @@ struct swr_context { struct pipe_constant_buffer constants[PIPE_SHADER_TYPES][PIPE_MAX_CONSTANT_BUFFERS]; struct pipe_framebuffer_state framebuffer; - struct pipe_poly_stipple poly_stipple; + struct swr_poly_stipple poly_stipple; struct pipe_scissor_state scissor; SWR_RECT swr_scissor; struct pipe_sampler_view * diff --git a/src/gallium/drivers/swr/swr_shader.cpp b/src/gallium/drivers/swr/swr_shader.cpp index 6fc0596ed6..d8f551291c 100644 --- a/src/gallium/drivers/swr/swr_shader.cpp +++ b/src/gallium/drivers/swr/swr_shader.cpp @@ -165,6 +165,9 @@ swr_generate_fs_key(struct swr_jit_fs_key &key, sizeof(key.vs_output_semantic_idx)); swr_generate_sampler_key(swr_fs->info, ctx, PIPE_SHADER_FRAGMENT, key); + + key.poly_stipple_enable = ctx->rasterizer->poly_stipple_enable && + ctx->poly_stipple.prim_is_poly; } void @@ -1099,17 +1102,58 @@ BuilderSWR::CompileFS(struct swr_context *ctx, swr_jit_fs_key &key) memset(&system_values, 0, sizeof(system_values)); struct lp_build_mask_context mask; + bool uses_mask = false; - if (swr_fs->info.base.uses_kill) { - Value *mask_val = LOAD(pPS, {0, SWR_PS_CONTEXT_activeMask}, "activeMask"); + if (swr_fs->info.base.uses_kill || + key.poly_stipple_enable) { + Value *vActiveMask = NULL; + if (swr_fs->info.base.uses_kill) { + vActiveMask = LOAD(pPS, {0, SWR_PS_CONTEXT_activeMask}, "activeMask"); + } + if (key.poly_stipple_enable) { + // first get fragment xy coords and clip to stipple bounds + Value *vXf = LOAD(pPS, {0, SWR_PS_CONTEXT_vX, PixelPositions_UL}); + Value *vYf = LOAD(pPS, {0, SWR_PS_CONTEXT_vY, PixelPositions_UL}); + Value *vXu = FP_TO_UI(vXf, mSimdInt32Ty); + Value *vYu = FP_TO_UI(vYf, mSimdInt32Ty); + + // stipple pattern is 32x32, which means that one line of stipple + // is stored in one word: + // vXstipple is bit offset inside 32-bit stipple word + // vYstipple is word index is stipple array + Value *vXstipple = AND(vXu, VIMMED1(0x1f)); // & (32-1) + Value *vYstipple = AND(vYu, VIMMED1(0x1f)); // & (32-1) + + // grab stipple pattern base address + Value *stipplePtr = GEP(hPrivateData, {0, swr_draw_context_polyStipple, 0}); + stipplePtr = BITCAST(stipplePtr, mInt8PtrTy); + + // peform a gather to grab stipple words for each lane + Value *vStipple = GATHERDD(VUNDEF_I(), stipplePtr, vYstipple, +VIMMED1(0x), C((char)4)); + + // create a mask with one bit corresponding to the x stipple + // and AND it with the pattern, to see if we have a bit + Value *vBitMask = LSHR(VIMMED1(0x8000), vXstipple); + Value *vStippleMask = AND(vStipple, vBitMask); + vStippleMask = ICMP_NE(vStippleMask, VIMMED1(0)); + vStippleMask = VMASK(vStippleMask); + + if (swr_fs->info.base.uses_kill) { +vActiveMask = AND(vActiveMask, vStippleMask); + } else { +vActiveMask = vStippleMask; + } + } lp_build_mask_begin( - &mask, gallivm, lp_type_float_vec(32, 32 * 8), wrap(mask_val)); + &mask, gallivm, lp_type_float_vec(32, 32 * 8), wrap(vActiveMask)); + uses_mask = true; } lp_build_tgsi_soa(gallivm, swr_fs->pipe.tokens, lp_type_float_vec(32, 32 * 8), - swr_fs->info.base.uses_kill ? &mask : NULL, // mask + uses_mask ? &mask : NULL, // mask wrap(consts_ptr), wrap(const_sizes_ptr), &system_values, @@ -1172,13 +12
Mesa (master): etnaviv: resolve tile status when flushing resource
Module: Mesa Branch: master Commit: dda956340ce9f7d04866eb6909455f24fae94724 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dda956340ce9f7d04866eb6909455f24fae94724 Author: Philipp Zabel Date: Wed Apr 12 16:13:37 2017 +0200 etnaviv: resolve tile status when flushing resource When passing render buffers from EGL clients to a wayland compositor, the resource tile status must be resolved because otherwise the tile status is lost in the transfer and cleared parts of the buffer will contain old contents. The same applies when sampling directly from a renderable resource. lst: Add seqno tracking, to skip flush when not needed. Fixes: aadcb5e94b35 ("etnaviv: enable TS, but disable autodisable") Signed-off-by: Philipp Zabel Signed-off-by: Lucas Stach Reviewed-by: Christian Gmeiner --- src/gallium/drivers/etnaviv/etnaviv_clear_blit.c | 3 +++ src/gallium/drivers/etnaviv/etnaviv_resource.h | 8 2 files changed, 11 insertions(+) diff --git a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c index a089fed13c..528b57389d 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c +++ b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c @@ -597,6 +597,9 @@ etna_flush_resource(struct pipe_context *pctx, struct pipe_resource *prsc) etna_resource_older(etna_resource(rsc->scanout->prime), rsc)) { etna_copy_resource(pctx, rsc->scanout->prime, prsc, 0, 0); etna_resource(rsc->scanout->prime)->seqno = rsc->seqno; + } else if (etna_resource_needs_flush(rsc)) { + etna_copy_resource(pctx, prsc, prsc, 0, 0); + rsc->flush_seqno = rsc->seqno; } } diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.h b/src/gallium/drivers/etnaviv/etnaviv_resource.h index a6c6a78269..a8d42ee1a0 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_resource.h +++ b/src/gallium/drivers/etnaviv/etnaviv_resource.h @@ -61,6 +61,7 @@ struct etna_resource { struct pipe_resource base; struct renderonly_scanout *scanout; uint32_t seqno; + uint32_t flush_seqno; /* only lod 0 used for non-texture buffers */ /* Layout for surface (tiled, multitiled, split tiled, ...) */ @@ -97,6 +98,13 @@ etna_resource_older(struct etna_resource *a, struct etna_resource *b) return (int)(a->seqno - b->seqno) < 0; } +/* returns TRUE if the resource needs a resolve to itself */ +static inline bool +etna_resource_needs_flush(struct etna_resource *res) +{ + return (int)(res->seqno - res->flush_seqno) > 0; +} + /* is the resource only used on the sampler? */ static inline bool etna_resource_sampler_only(const struct pipe_resource *pres) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): etnaviv: stop repeatedly resolving an unchanged resource into its scanout prime buffer
Module: Mesa Branch: master Commit: f30aab76961564e2f0ce34af7d7b38ec43535877 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f30aab76961564e2f0ce34af7d7b38ec43535877 Author: Philipp Zabel Date: Wed Apr 12 16:13:36 2017 +0200 etnaviv: stop repeatedly resolving an unchanged resource into its scanout prime buffer Before resolving a resource into its scanout prime buffer, check that the prime resource is actually older. If it is not, the resolve is an expensive no-op, and we better skip it. Signed-off-by: Philipp Zabel Reviewed-by: Christian Gmeiner --- src/gallium/drivers/etnaviv/etnaviv_clear_blit.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c index d555884d3f..a089fed13c 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c +++ b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c @@ -593,8 +593,11 @@ etna_flush_resource(struct pipe_context *pctx, struct pipe_resource *prsc) { struct etna_resource *rsc = etna_resource(prsc); - if (rsc->scanout) + if (rsc->scanout && + etna_resource_older(etna_resource(rsc->scanout->prime), rsc)) { etna_copy_resource(pctx, rsc->scanout->prime, prsc, 0, 0); + etna_resource(rsc->scanout->prime)->seqno = rsc->seqno; + } } void ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): etnaviv: Add chipMinorFeatures4 and 5
Module: Mesa Branch: master Commit: 9e4d049f402af93dafe55865dcfd87c96659b7ba URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e4d049f402af93dafe55865dcfd87c96659b7ba Author: Wladimir J. van der Laan Date: Fri Apr 14 09:39:52 2017 +0200 etnaviv: Add chipMinorFeatures4 and 5 Request chipMinorFeatures bitfields 4 and 5 from the drm driver. Signed-off-by: Wladimir J. van der Laan Reviewed-by: Christian Gmeiner --- src/gallium/drivers/etnaviv/etnaviv_screen.c | 12 src/gallium/drivers/etnaviv/etnaviv_screen.h | 4 +++- 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c b/src/gallium/drivers/etnaviv/etnaviv_screen.c index 55d22c6aba..d4e4c7f699 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_screen.c +++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c @@ -800,6 +800,18 @@ etna_screen_create(struct etna_device *dev, struct etna_gpu *gpu, } screen->features[4] = val; + if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_5, &val)) { + DBG("could not get ETNA_GPU_FEATURES_5"); + goto fail; + } + screen->features[5] = val; + + if (etna_gpu_get_param(screen->gpu, ETNA_GPU_FEATURES_6, &val)) { + DBG("could not get ETNA_GPU_FEATURES_6"); + goto fail; + } + screen->features[6] = val; + if (!etna_get_specs(screen)) goto fail; diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.h b/src/gallium/drivers/etnaviv/etnaviv_screen.h index c33a9e32fa..a606e5d708 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_screen.h +++ b/src/gallium/drivers/etnaviv/etnaviv_screen.h @@ -44,6 +44,8 @@ enum viv_features_word { viv_chipMinorFeatures1 = 2, viv_chipMinorFeatures2 = 3, viv_chipMinorFeatures3 = 4, + viv_chipMinorFeatures4 = 5, + viv_chipMinorFeatures5 = 6, VIV_FEATURES_WORD_COUNT /* Must be last */ }; @@ -69,7 +71,7 @@ struct etna_screen { uint32_t model; uint32_t revision; - uint32_t features[5]; + uint32_t features[VIV_FEATURES_WORD_COUNT]; struct etna_specs specs; }; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): etnaviv: SINGLE_BUFFER support on GC3000
Module: Mesa Branch: master Commit: 6a8d5ab932e525f16e744b4f13c4f6a7fa636ecf URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a8d5ab932e525f16e744b4f13c4f6a7fa636ecf Author: Wladimir J. van der Laan Date: Fri Apr 14 09:44:27 2017 +0200 etnaviv: SINGLE_BUFFER support on GC3000 This patch adds support for the SINGLE_BUFFER feature on GC3000 GPUs, which allows rendering to a single buffer using multiple pixel pipes. This feature is always used when it is available, which means that multi-tiled formats are no longer being used in that case, and all buffers will be normal (super)tiled. This mimics the behavior of the blob on GC3000. - Because the same format can be used to render to and texture from, this avoids an extra resolve pass when rendering to texture. - i.MX6qp includes a PRE which can scan-out directly from tiled formats, avoiding untiling overhead. Signed-off-by: Wladimir J. van der Laan Reviewed-by: Christian Gmeiner --- src/gallium/drivers/etnaviv/etnaviv_context.c | 3 ++ src/gallium/drivers/etnaviv/etnaviv_emit.c | 6 ++-- src/gallium/drivers/etnaviv/etnaviv_internal.h | 3 ++ src/gallium/drivers/etnaviv/etnaviv_resource.c | 8 +- src/gallium/drivers/etnaviv/etnaviv_rs.c | 39 +++--- src/gallium/drivers/etnaviv/etnaviv_screen.c | 4 +++ src/gallium/drivers/etnaviv/etnaviv_state.c| 10 +-- src/gallium/drivers/etnaviv/etnaviv_surface.c | 18 8 files changed, 63 insertions(+), 28 deletions(-) diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.c b/src/gallium/drivers/etnaviv/etnaviv_context.c index 555aa12765..f2f709cbf2 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_context.c +++ b/src/gallium/drivers/etnaviv/etnaviv_context.c @@ -293,6 +293,9 @@ etna_cmd_stream_reset_notify(struct etna_cmd_stream *stream, void *priv) etna_set_state(stream, VIVS_RA_EARLY_DEPTH, 0x0031); etna_set_state(stream, VIVS_PA_W_CLIP_LIMIT, 0x3401); + /* Enable SINGLE_BUFFER for resolve, if supported */ + etna_set_state(stream, VIVS_RS_SINGLE_BUFFER, COND(ctx->specs.single_buffer, VIVS_RS_SINGLE_BUFFER_ENABLE)); + ctx->dirty = ~0L; /* go through all the used resources and clear their status flag */ diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.c b/src/gallium/drivers/etnaviv/etnaviv_emit.c index af74cbb4c5..7ced5fcd11 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_emit.c +++ b/src/gallium/drivers/etnaviv/etnaviv_emit.c @@ -603,10 +603,12 @@ etna_emit_state(struct etna_context *ctx) if (unlikely(dirty & (ETNA_DIRTY_STENCIL_REF))) { /*014A0*/ EMIT_STATE(PE_STENCIL_CONFIG_EXT, ctx->stencil_ref.PE_STENCIL_CONFIG_EXT); } + if (unlikely(dirty & (ETNA_DIRTY_BLEND | ETNA_DIRTY_FRAMEBUFFER))) { + struct etna_blend_state *blend = etna_blend_state(ctx->blend); + /*014A4*/ EMIT_STATE(PE_LOGIC_OP, blend->PE_LOGIC_OP | ctx->framebuffer.PE_LOGIC_OP); + } if (unlikely(dirty & (ETNA_DIRTY_BLEND))) { struct etna_blend_state *blend = etna_blend_state(ctx->blend); - - /*014A4*/ EMIT_STATE(PE_LOGIC_OP, blend->PE_LOGIC_OP); for (int x = 0; x < 2; ++x) { /*014A8*/ EMIT_STATE(PE_DITHER(x), blend->PE_DITHER[x]); } diff --git a/src/gallium/drivers/etnaviv/etnaviv_internal.h b/src/gallium/drivers/etnaviv/etnaviv_internal.h index 2f09d555bc..2f8dacbce5 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_internal.h +++ b/src/gallium/drivers/etnaviv/etnaviv_internal.h @@ -72,6 +72,8 @@ struct etna_specs { unsigned has_shader_range_registers : 1; /* has the new sin/cos functions */ unsigned has_new_sin_cos : 1; + /* supports single-buffer rendering with multiple pixel pipes */ + unsigned single_buffer : 1; /* can use any kind of wrapping mode on npot textures */ unsigned npot_tex_any_wrap; /* number of bits per TS tile */ @@ -191,6 +193,7 @@ struct compiled_framebuffer_state { uint32_t TS_COLOR_CLEAR_VALUE; struct etna_reloc TS_COLOR_STATUS_BASE; struct etna_reloc TS_COLOR_SURFACE_BASE; + uint32_t PE_LOGIC_OP; bool msaa_mode; /* adds input (and possible temp) to PS */ }; diff --git a/src/gallium/drivers/etnaviv/etnaviv_resource.c b/src/gallium/drivers/etnaviv/etnaviv_resource.c index 5f2b63f97c..db9acacae2 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_resource.c +++ b/src/gallium/drivers/etnaviv/etnaviv_resource.c @@ -249,9 +249,15 @@ etna_resource_create(struct pipe_screen *pscreen, if (util_format_is_compressed(templat->format)) layout = ETNA_LAYOUT_LINEAR; } else if (templat->target != PIPE_BUFFER) { - bool want_multitiled = screen->specs.pixel_pipes > 1; + bool want_multitiled = false; bool want_supertiled = screen->specs.can_supertile && !DBG_ENABLED(ETNA_DBG_NO_SUPERTILE); + /* When this GPU supports single-buffer rendering, don't ever enable + * multi-tiling. This replicates the blob behavior on GC3000. + */ + if (!screen-
Mesa (master): etnaviv: Update includes from rnndb
Module: Mesa Branch: master Commit: 1dcb1d49254dabd3989ad4ec5004b540683529b2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1dcb1d49254dabd3989ad4ec5004b540683529b2 Author: Wladimir J. van der Laan Date: Fri Apr 14 09:41:03 2017 +0200 etnaviv: Update includes from rnndb Update to etna_viv commit 8486a97. austriancoder: changed patch to include isa redefinition fix. Signed-off-by: Wladimir J. van der Laan Reviewed-by: Christian Gmeiner --- src/gallium/drivers/etnaviv/hw/cmdstream.xml.h | 2 +- src/gallium/drivers/etnaviv/hw/common.xml.h| 10 ++-- src/gallium/drivers/etnaviv/hw/isa.xml.h | 75 +- src/gallium/drivers/etnaviv/hw/state.xml.h | 10 ++-- src/gallium/drivers/etnaviv/hw/state_3d.xml.h | 14 ++--- 5 files changed, 91 insertions(+), 20 deletions(-) diff --git a/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h b/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h index 4e78eba694..d4da03016e 100644 --- a/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h +++ b/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h @@ -10,7 +10,7 @@ git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: - cmdstream.xml ( 14313 bytes, from 2016-11-17 18:46:23) - copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22) -- common.xml( 23473 bytes, from 2016-12-11 10:32:13) +- common.xml( 23473 bytes, from 2017-01-07 14:27:54) Copyright (C) 2012-2016 by the following authors: - Wladimir J. van der Laan diff --git a/src/gallium/drivers/etnaviv/hw/common.xml.h b/src/gallium/drivers/etnaviv/hw/common.xml.h index 0f99db275d..8b73fd8128 100644 --- a/src/gallium/drivers/etnaviv/hw/common.xml.h +++ b/src/gallium/drivers/etnaviv/hw/common.xml.h @@ -8,15 +8,15 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- state.xml ( 19930 bytes, from 2016-12-14 15:25:40) -- common.xml( 23473 bytes, from 2016-12-11 10:32:13) -- state_hi.xml ( 26403 bytes, from 2016-12-14 06:43:27) +- state.xml ( 19930 bytes, from 2017-01-07 14:27:54) +- common.xml( 23473 bytes, from 2017-01-07 14:27:54) +- state_hi.xml ( 26403 bytes, from 2017-01-07 14:27:54) - copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22) - state_2d.xml ( 51552 bytes, from 2016-10-29 07:29:22) -- state_3d.xml ( 66957 bytes, from 2016-12-15 11:31:03) +- state_3d.xml ( 66964 bytes, from 2017-04-13 12:38:05) - state_vg.xml ( 5975 bytes, from 2016-10-29 07:29:22) -Copyright (C) 2012-2016 by the following authors: +Copyright (C) 2012-2017 by the following authors: - Wladimir J. van der Laan - Christian Gmeiner - Lucas Stach diff --git a/src/gallium/drivers/etnaviv/hw/isa.xml.h b/src/gallium/drivers/etnaviv/hw/isa.xml.h index c604b4407d..31706807e3 100644 --- a/src/gallium/drivers/etnaviv/hw/isa.xml.h +++ b/src/gallium/drivers/etnaviv/hw/isa.xml.h @@ -8,10 +8,10 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng git clone git://0x04.net/rules-ng-ng The rules-ng-ng source files this header was generated from are: -- isa.xml ( 30048 bytes, from 2016-12-12 13:26:33) +- isa.xml ( 34392 bytes, from 2017-04-13 12:44:36) - copyright.xml ( 1597 bytes, from 2016-10-29 07:29:22) -Copyright (C) 2012-2016 by the following authors: +Copyright (C) 2012-2017 by the following authors: - Wladimir J. van der Laan - Christian Gmeiner - Lucas Stach @@ -77,14 +77,54 @@ DEALINGS IN THE SOFTWARE. #define INST_OPCODE_FLOOR 0x0025 #define INST_OPCODE_CEIL 0x0026 #define INST_OPCODE_SIGN 0x0027 +#define INST_OPCODE_ADDLO 0x0028 +#define INST_OPCODE_MULLO 0x0029 +#define INST_OPCODE_BARRIER0x002a +#define INST_OPCODE_SWIZZLE0x002b +#define INST_OPCODE_I2I 0x002c #define INST_OPCODE_I2F 0x002d #define INST_OPCODE_F2I 0x002e +#define INST_OPCODE_F2IRND 0x002f +#define INST_OPCODE_F2I7 0x0030 #define INST_OPCODE_CMP 0x0031 #define INST_OPCODE_LOAD 0x0032 #define INST_OPCODE_STORE 0x0033 +#define INST_OPCODE_COPYSIGN 0x0034 +#define INST_OPCODE_GETEXP 0x0035 +#define INST_OPCODE_GETMANT0x0036 +#define INST_OPCODE_NAN 0x0
Mesa (master): swr: Fix swr osmesa build
Module: Mesa Branch: master Commit: b9d4256e11dc462e0870a8d0a7b544604ddcaa5a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9d4256e11dc462e0870a8d0a7b544604ddcaa5a Author: George Kyriazis Date: Fri Apr 14 13:56:09 2017 -0500 swr: Fix swr osmesa build Use GALLIUM_SWR to standardize Reviewed-by: Emil Velikov --- src/gallium/targets/osmesa/SConscript | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/targets/osmesa/SConscript b/src/gallium/targets/osmesa/SConscript index 47937a23d2..7be1b48c0b 100644 --- a/src/gallium/targets/osmesa/SConscript +++ b/src/gallium/targets/osmesa/SConscript @@ -31,7 +31,7 @@ if env['llvm']: env.Prepend(LIBS = [llvmpipe]) if env['swr']: -env.Append(CPPDEFINES = 'HAVE_SWR') +env.Append(CPPDEFINES = 'GALLIUM_SWR') env.Prepend(LIBS = [swr]) if env['platform'] == 'windows': ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: enable OpenGL 4.2 in Ivybridge
Module: Mesa Branch: master Commit: 1877982aca7d50541618a8997fdd72c5286b4b67 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1877982aca7d50541618a8997fdd72c5286b4b67 Author: Juan A. Suarez Romero Date: Wed Mar 29 11:41:35 2017 +0200 i965: enable OpenGL 4.2 in Ivybridge Reviewed-by: Andreas Boll Reviewed-by: Francisco Jerez --- src/mesa/drivers/dri/i965/intel_extensions.c | 2 +- src/mesa/drivers/dri/i965/intel_screen.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index fc974b9860..0133fa1006 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -139,7 +139,7 @@ intelInitExtensions(struct gl_context *ctx) else if (brw->is_haswell && can_do_pipelined_register_writes(brw->screen)) ctx->Const.GLSLVersion = 450; else if (brw->gen >= 7 && can_do_pipelined_register_writes(brw->screen)) - ctx->Const.GLSLVersion = 400; + ctx->Const.GLSLVersion = 420; else if (brw->gen >= 6) ctx->Const.GLSLVersion = 330; else diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 9e536f58b3..39e463d264 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -1654,7 +1654,7 @@ set_max_gl_versions(struct intel_screen *screen) case 7: dri_screen->max_gl_core_version = 33; if (can_do_pipelined_register_writes(screen)) { - dri_screen->max_gl_core_version = screen->devinfo.is_haswell ? 42 : 40; + dri_screen->max_gl_core_version = 42; if (screen->devinfo.is_haswell && can_do_compute_dispatch(screen)) dri_screen->max_gl_core_version = 43; if (screen->devinfo.is_haswell && can_do_mi_math_and_lrr(screen)) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): docs: mark GL_ARB_vertex_attrib_64bit and OpenGL 4.2 as supported by i965/gen7+
Module: Mesa Branch: master Commit: 96dfc014fd33a4f38e31fa1d4c9c4ea52d85a0b8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=96dfc014fd33a4f38e31fa1d4c9c4ea52d85a0b8 Author: Francisco Jerez Date: Fri Apr 14 15:59:52 2017 -0700 docs: mark GL_ARB_vertex_attrib_64bit and OpenGL 4.2 as supported by i965/gen7+ v2 (Andreas Boll): - Mark GL 4.1 as supported by i965/gen7+ - Mark GL_ARB_shader_precision as supported by i965/gen7+ - Update release notes Reviewed-by: Andreas Boll Reviewed-by: Francisco Jerez --- docs/features.txt | 8 docs/relnotes/17.1.0.html | 3 +++ 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/docs/features.txt b/docs/features.txt index 3dd4094865..5f63632e82 100644 --- a/docs/features.txt +++ b/docs/features.txt @@ -136,17 +136,17 @@ GL 4.0, GLSL 4.00 --- all DONE: i965/gen7+, nvc0, r600, radeonsi GL_ARB_transform_feedback3DONE (i965/gen7+, llvmpipe, softpipe, swr) -GL 4.1, GLSL 4.10 --- all DONE: i965/hsw+, nvc0, r600, radeonsi +GL 4.1, GLSL 4.10 --- all DONE: i965/gen7+, nvc0, r600, radeonsi GL_ARB_ES2_compatibility DONE (i965, nv50, llvmpipe, softpipe, swr) GL_ARB_get_program_binary DONE (0 binary formats) GL_ARB_separate_shader_objectsDONE (all drivers) - GL_ARB_shader_precision DONE (i965/hsw+, all drivers that support GLSL 4.10) - GL_ARB_vertex_attrib_64bitDONE (i965/hsw+, llvmpipe, softpipe) + GL_ARB_shader_precision DONE (i965/gen7+, all drivers that support GLSL 4.10) + GL_ARB_vertex_attrib_64bitDONE (i965/gen7+, llvmpipe, softpipe) GL_ARB_viewport_array DONE (i965, nv50, llvmpipe, softpipe) -GL 4.2, GLSL 4.20 -- all DONE: i965/hsw+, nvc0, radeonsi +GL 4.2, GLSL 4.20 -- all DONE: i965/gen7+, nvc0, radeonsi GL_ARB_texture_compression_bptc DONE (i965, r600) GL_ARB_compressed_texture_pixel_storage DONE (all drivers) diff --git a/docs/relnotes/17.1.0.html b/docs/relnotes/17.1.0.html index ba21b61f91..4f3e0030a8 100644 --- a/docs/relnotes/17.1.0.html +++ b/docs/relnotes/17.1.0.html @@ -44,15 +44,18 @@ Note: some of the new features are only available with certain drivers. +OpenGL 4.2 on i965/ivb GL_ARB_gpu_shader_fp64 on i965/ivybridge GL_ARB_gpu_shader_int64 on i965/gen8+, nvc0, radeonsi, softpipe, llvmpipe GL_ARB_shader_ballot on nvc0, radeonsi GL_ARB_shader_clock on nv50, nvc0, radeonsi GL_ARB_shader_group_vote on radeonsi +GL_ARB_shader_precision on i965/ivb GL_ARB_shader_viewport_layer_array on radeonsi GL_ARB_sparse_buffer on radeonsi/CIK+ GL_ARB_transform_feedback2 on i965/gen6 GL_ARB_transform_feedback_overflow_query on i965/gen6+ +GL_ARB_vertex_attrib_64bit on i965/ivb GL_NV_fill_rectangle on nvc0 Geometry shaders enabled on swr ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: enable ARB_shader_precision in gen7+
Module: Mesa Branch: master Commit: 92d4dc76eaec64e99194f3d2afcc55eb7c7b46ba URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=92d4dc76eaec64e99194f3d2afcc55eb7c7b46ba Author: Samuel Iglesias Gonsálvez Date: Mon Oct 17 14:40:06 2016 + i965: enable ARB_shader_precision in gen7+ Reviewed-by: Andreas Boll Reviewed-by: Francisco Jerez --- src/mesa/drivers/dri/i965/intel_extensions.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index 53b5eaf8a0..fc974b9860 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -216,6 +216,7 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.ARB_shader_clock = true; ctx->Extensions.ARB_shader_image_load_store = true; ctx->Extensions.ARB_shader_image_size = true; + ctx->Extensions.ARB_shader_precision = true; ctx->Extensions.ARB_shader_texture_image_samples = true; ctx->Extensions.ARB_tessellation_shader = true; ctx->Extensions.ARB_texture_compression_bptc = true; @@ -245,7 +246,6 @@ intelInitExtensions(struct gl_context *ctx) } if (brw->gen >= 8 || brw->is_haswell) { - ctx->Extensions.ARB_shader_precision = true; ctx->Extensions.ARB_stencil_texturing = true; ctx->Extensions.ARB_texture_stencil8 = true; ctx->Extensions.OES_geometry_shader = true; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: enable ARB_vertex_attrib_64bit for gen7+
Module: Mesa Branch: master Commit: 0aed1212ae54c3286c7f6e155c129b1973723c46 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0aed1212ae54c3286c7f6e155c129b1973723c46 Author: Juan A. Suarez Romero Date: Fri Oct 21 16:57:25 2016 +0200 i965: enable ARB_vertex_attrib_64bit for gen7+ Reviewed-by: Andreas Boll Reviewed-by: Francisco Jerez --- src/mesa/drivers/dri/i965/intel_extensions.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index 467a0d3e84..53b5eaf8a0 100644 --- a/src/mesa/drivers/dri/i965/intel_extensions.c +++ b/src/mesa/drivers/dri/i965/intel_extensions.c @@ -221,6 +221,7 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.ARB_texture_compression_bptc = true; ctx->Extensions.ARB_texture_view = true; ctx->Extensions.ARB_shader_storage_buffer_object = true; + ctx->Extensions.ARB_vertex_attrib_64bit = true; ctx->Extensions.EXT_shader_samples_identical = true; ctx->Extensions.OES_primitive_bounding_box = true; ctx->Extensions.OES_texture_buffer = true; @@ -247,7 +248,6 @@ intelInitExtensions(struct gl_context *ctx) ctx->Extensions.ARB_shader_precision = true; ctx->Extensions.ARB_stencil_texturing = true; ctx->Extensions.ARB_texture_stencil8 = true; - ctx->Extensions.ARB_vertex_attrib_64bit = true; ctx->Extensions.OES_geometry_shader = true; ctx->Extensions.OES_texture_cube_map_array = true; ctx->Extensions.OES_viewport_array = true; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): etnaviv: native fence fd support
Module: Mesa Branch: master Commit: 36f21017237ab536db74c84e0f778d3a58271c75 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=36f21017237ab536db74c84e0f778d3a58271c75 Author: Philipp Zabel Date: Wed Apr 12 12:31:01 2017 +0200 etnaviv: native fence fd support This adds native fence fd support to etnaviv, similarly to commit 0b98e84e9ba0 ("freedreno: native fence fd"), enabled for kernel driver version 1.1 or later. Signed-off-by: Philipp Zabel Reviewed-By: Wladimir J. van der Laan Reviewed-by: Christian Gmeiner --- configure.ac | 2 +- src/gallium/drivers/etnaviv/etnaviv_context.c | 14 +++-- src/gallium/drivers/etnaviv/etnaviv_context.h | 1 + src/gallium/drivers/etnaviv/etnaviv_fence.c | 45 +-- src/gallium/drivers/etnaviv/etnaviv_fence.h | 14 - src/gallium/drivers/etnaviv/etnaviv_screen.c | 12 ++- src/gallium/drivers/etnaviv/etnaviv_screen.h | 2 ++ 7 files changed, 83 insertions(+), 7 deletions(-) diff --git a/configure.ac b/configure.ac index 957991cef7..ef19733423 100644 --- a/configure.ac +++ b/configure.ac @@ -80,7 +80,7 @@ LIBDRM_NVVIEUX_REQUIRED=2.4.66 LIBDRM_NOUVEAU_REQUIRED=2.4.66 LIBDRM_FREEDRENO_REQUIRED=2.4.74 LIBDRM_VC4_REQUIRED=2.4.69 -LIBDRM_ETNAVIV_REQUIRED=2.4.74 +LIBDRM_ETNAVIV_REQUIRED=2.4.80 dnl Versions for external dependencies DRI2PROTO_REQUIRED=2.8 diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.c b/src/gallium/drivers/etnaviv/etnaviv_context.c index f2f709cbf2..cfbc906542 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_context.c +++ b/src/gallium/drivers/etnaviv/etnaviv_context.c @@ -73,6 +73,9 @@ etna_context_destroy(struct pipe_context *pctx) slab_destroy_child(&ctx->transfer_pool); + if (ctx->in_fence_fd != -1) + close(ctx->in_fence_fd); + FREE(pctx); } @@ -275,11 +278,14 @@ etna_flush(struct pipe_context *pctx, struct pipe_fence_handle **fence, enum pipe_flush_flags flags) { struct etna_context *ctx = etna_context(pctx); + int out_fence_fd = -1; - etna_cmd_stream_flush(ctx->stream); + etna_cmd_stream_flush2(ctx->stream, ctx->in_fence_fd, + (flags & PIPE_FLUSH_FENCE_FD) ? &out_fence_fd : + NULL); if (fence) - *fence = etna_fence_create(pctx); + *fence = etna_fence_create(pctx, out_fence_fd); } static void @@ -356,10 +362,14 @@ etna_context_create(struct pipe_screen *pscreen, void *priv, unsigned flags) /* Set sensible defaults for state */ etna_cmd_stream_reset_notify(ctx->stream, ctx); + ctx->in_fence_fd = -1; + pctx->destroy = etna_context_destroy; pctx->draw_vbo = etna_draw_vbo; pctx->flush = etna_flush; pctx->set_debug_callback = etna_set_debug_callback; + pctx->create_fence_fd = etna_create_fence_fd; + pctx->fence_server_sync = etna_fence_server_sync; /* creation of compile states */ pctx->create_blend_state = etna_blend_state_create; diff --git a/src/gallium/drivers/etnaviv/etnaviv_context.h b/src/gallium/drivers/etnaviv/etnaviv_context.h index 9e00d34d23..56b57b55a8 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_context.h +++ b/src/gallium/drivers/etnaviv/etnaviv_context.h @@ -178,6 +178,7 @@ struct etna_context { } stats; struct pipe_debug_callback debug; + int in_fence_fd; }; static inline struct etna_context * diff --git a/src/gallium/drivers/etnaviv/etnaviv_fence.c b/src/gallium/drivers/etnaviv/etnaviv_fence.c index 02f520b8b3..65402aaa3b 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_fence.c +++ b/src/gallium/drivers/etnaviv/etnaviv_fence.c @@ -25,6 +25,8 @@ *Rob Clark */ +#include + #include "etnaviv_fence.h" #include "etnaviv_context.h" #include "etnaviv_screen.h" @@ -36,16 +38,25 @@ struct pipe_fence_handle { struct pipe_reference reference; struct etna_context *ctx; struct etna_screen *screen; + int fence_fd; uint32_t timestamp; }; static void +etna_fence_destroy(struct pipe_fence_handle *fence) +{ + if (fence->fence_fd != -1) + close(fence->fence_fd); + FREE(fence); +} + +static void etna_screen_fence_reference(struct pipe_screen *pscreen, struct pipe_fence_handle **ptr, struct pipe_fence_handle *fence) { if (pipe_reference(&(*ptr)->reference, &fence->reference)) - FREE(*ptr); + etna_fence_destroy(*ptr); *ptr = fence; } @@ -54,14 +65,42 @@ static boolean etna_screen_fence_finish(struct pipe_screen *pscreen, struct pipe_context *ctx, struct pipe_fence_handle *fence, uint64_t timeout) { + if (fence->fence_fd != -1) { + int ret = sync_wait(fence->fence_fd, timeout / 100); + return ret == 0; + } + if (etna_pipe_wait_ns(fence->screen->pipe, fence->timestamp, timeout)) return false; return true; } +void +etna_create_fence_fd(struct pipe_context *pctx, + st
Mesa (master): anv: Add the pci_id into the shader cache UUID
Module: Mesa Branch: master Commit: d2d6cf6c8387ac06c8559027f57683a61b48671b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2d6cf6c8387ac06c8559027f57683a61b48671b Author: Jason Ekstrand Date: Fri Feb 24 16:36:00 2017 -0800 anv: Add the pci_id into the shader cache UUID This prevents a user from using a cache created on one hardware generation on a different one. Of course, with Intel hardware, this requires moving their drive from one machine to another but it's still possible and we should prevent it. Reviewed-by: Chad Versace Cc: mesa-sta...@lists.freedesktop.org --- src/intel/vulkan/anv_device.c | 20 +++- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index ee9c48fa73..8f4625ba00 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -34,6 +34,7 @@ #include "util/strtod.h" #include "util/debug.h" #include "util/build_id.h" +#include "util/mesa-sha1.h" #include "util/vk_util.h" #include "genxml/gen7_pack.h" @@ -97,17 +98,26 @@ anv_compute_heap_size(int fd, uint64_t *heap_size) } static bool -anv_device_get_cache_uuid(void *uuid) +anv_device_get_cache_uuid(void *uuid, uint16_t pci_id) { const struct build_id_note *note = build_id_find_nhdr("libvulkan_intel.so"); if (!note) return false; - unsigned len = build_id_length(note); - if (len < VK_UUID_SIZE) + unsigned build_id_len = build_id_length(note); + if (build_id_len < 20) /* It should be a SHA-1 */ return false; - memcpy(uuid, build_id_data(note), VK_UUID_SIZE); + struct mesa_sha1 sha1_ctx; + uint8_t sha1[20]; + STATIC_ASSERT(VK_UUID_SIZE <= sizeof(sha1)); + + _mesa_sha1_init(&sha1_ctx); + _mesa_sha1_update(&sha1_ctx, build_id_data(note), build_id_len); + _mesa_sha1_update(&sha1_ctx, &pci_id, sizeof(pci_id)); + _mesa_sha1_final(&sha1_ctx, sha1); + + memcpy(uuid, sha1, VK_UUID_SIZE); return true; } @@ -192,7 +202,7 @@ anv_physical_device_init(struct anv_physical_device *device, if (result != VK_SUCCESS) goto fail; - if (!anv_device_get_cache_uuid(device->uuid)) { + if (!anv_device_get_cache_uuid(device->uuid, device->chipset_id)) { result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED, "cannot generate UUID"); goto fail; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl: don' t run the GLSL pre-processor when we are skipping compilation
Module: Mesa Branch: master Commit: 9f0dd85aa65b5eba783d6023b51deacd529cf918 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f0dd85aa65b5eba783d6023b51deacd529cf918 Author: Timothy Arceri Date: Mon Apr 10 11:48:49 2017 +1000 glsl: don't run the GLSL pre-processor when we are skipping compilation This moves the hashing of shader source for the cache lookup to before the preprocessor. In our experience, shaders are unlikely to hash the same after preprocessing if they didn't hash the same before, so we can skip preprocessing for cache hits. Improves Deus Ex start-up times with a warm cache from ~30 seconds to ~22 seconds. Also fixes the leaking of state. V2: fix indentation v3: add the value of MESA_EXTENSION_OVERRIDE to the hash of the shader. Tested-by (v2): Grazvydas Ignotas Tested-by: Dieter Nützel Reviewed-by: Eric Anholt --- src/compiler/glsl/glsl_parser_extras.cpp | 19 ++- src/compiler/glsl/shader_cache.cpp | 10 ++ 2 files changed, 20 insertions(+), 9 deletions(-) diff --git a/src/compiler/glsl/glsl_parser_extras.cpp b/src/compiler/glsl/glsl_parser_extras.cpp index ca74b559dc..eb12efff8a 100644 --- a/src/compiler/glsl/glsl_parser_extras.cpp +++ b/src/compiler/glsl/glsl_parser_extras.cpp @@ -2005,18 +2005,9 @@ void _mesa_glsl_compile_shader(struct gl_context *ctx, struct gl_shader *shader, bool dump_ast, bool dump_hir, bool force_recompile) { - struct _mesa_glsl_parse_state *state = - new(shader) _mesa_glsl_parse_state(ctx, shader->Stage, shader); const char *source = force_recompile && shader->FallbackSource ? shader->FallbackSource : shader->Source; - if (ctx->Const.GenerateTemporaryNames) - (void) p_atomic_cmpxchg(&ir_variable::temporaries_allocate_names, - false, true); - - state->error = glcpp_preprocess(state, &source, &state->info_log, - add_builtin_defines, state, ctx); - if (!force_recompile) { if (ctx->Cache) { char buf[41]; @@ -2050,6 +2041,16 @@ _mesa_glsl_compile_shader(struct gl_context *ctx, struct gl_shader *shader, } } + struct _mesa_glsl_parse_state *state = + new(shader) _mesa_glsl_parse_state(ctx, shader->Stage, shader); + + if (ctx->Const.GenerateTemporaryNames) + (void) p_atomic_cmpxchg(&ir_variable::temporaries_allocate_names, + false, true); + + state->error = glcpp_preprocess(state, &source, &state->info_log, + add_builtin_defines, state, ctx); + if (!state->error) { _mesa_glsl_lexer_ctor(state, source); _mesa_glsl_parse(state); diff --git a/src/compiler/glsl/shader_cache.cpp b/src/compiler/glsl/shader_cache.cpp index e51fecd651..738e5488ac 100644 --- a/src/compiler/glsl/shader_cache.cpp +++ b/src/compiler/glsl/shader_cache.cpp @@ -1319,6 +1319,16 @@ shader_cache_read_program_metadata(struct gl_context *ctx, ctx->API, ctx->Const.GLSLVersion, ctx->Const.ForceGLSLVersion); + /* We run the preprocessor on shaders after hashing them, so we need to +* add any extension override vars to the hash. If we don't do this the +* preprocessor could result in different output and we could load the +* wrong shader. +*/ + char *ext_override = getenv("MESA_EXTENSION_OVERRIDE"); + if (ext_override) { + ralloc_asprintf_append(&buf, "ext:%s", ext_override); + } + /* DRI config options may also change the output from the compiler so * include them as an input to sha1 creation. */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl: delay optimisations on individual shaders when cache is available
Module: Mesa Branch: master Commit: c2bc0aa7b188708e702bc3eaac5389793cbb85a8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2bc0aa7b188708e702bc3eaac5389793cbb85a8 Author: Timothy Arceri Date: Mon Apr 10 11:48:48 2017 +1000 glsl: delay optimisations on individual shaders when cache is available Due to a max limit of 65,536 entries on the index table that we use to decide if we can skip compiling individual shaders, it is very likely we will have collisions. To avoid doing too much work when the linked program may be in the cache this patch delays calling the optimisations until link time. Improves cold cache start-up times on Deus Ex by ~20 seconds. When deleting the cache index to simulate a worst case scenario of collisions in the index, warm cache start-up time improves by ~45 seconds. V2: fix indentation, make sure to call optimisations on cache fallback, make sure optimisations get called for XFB. Tested-by: Grazvydas Ignotas Tested-by: Dieter Nützel Reviewed-by: Nicolai Hähnle --- src/compiler/glsl/glsl_parser_extras.cpp | 166 +-- src/compiler/glsl/linker.cpp | 3 - src/compiler/glsl/shader_cache.cpp | 2 +- src/mesa/main/mtypes.h | 3 +- 4 files changed, 96 insertions(+), 78 deletions(-) diff --git a/src/compiler/glsl/glsl_parser_extras.cpp b/src/compiler/glsl/glsl_parser_extras.cpp index 4629e78efa..ca74b559dc 100644 --- a/src/compiler/glsl/glsl_parser_extras.cpp +++ b/src/compiler/glsl/glsl_parser_extras.cpp @@ -1922,6 +1922,85 @@ do_late_parsing_checks(struct _mesa_glsl_parse_state *state) } } +static void +opt_shader_and_create_symbol_table(struct gl_context *ctx, + struct gl_shader *shader) +{ + assert(shader->CompileStatus != compile_failure && + !shader->ir->is_empty()); + + struct gl_shader_compiler_options *options = + &ctx->Const.ShaderCompilerOptions[shader->Stage]; + + /* Do some optimization at compile time to reduce shader IR size +* and reduce later work if the same shader is linked multiple times +*/ + if (ctx->Const.GLSLOptimizeConservatively) { + /* Run it just once. */ + do_common_optimization(shader->ir, false, false, options, + ctx->Const.NativeIntegers); + } else { + /* Repeat it until it stops making changes. */ + while (do_common_optimization(shader->ir, false, false, options, +ctx->Const.NativeIntegers)) + ; + } + + validate_ir_tree(shader->ir); + + enum ir_variable_mode other; + switch (shader->Stage) { + case MESA_SHADER_VERTEX: + other = ir_var_shader_in; + break; + case MESA_SHADER_FRAGMENT: + other = ir_var_shader_out; + break; + default: + /* Something invalid to ensure optimize_dead_builtin_uniforms + * doesn't remove anything other than uniforms or constants. + */ + other = ir_var_mode_count; + break; + } + + optimize_dead_builtin_variables(shader->ir, other); + + validate_ir_tree(shader->ir); + + /* Retain any live IR, but trash the rest. */ + reparent_ir(shader->ir, shader->ir); + + /* Destroy the symbol table. Create a new symbol table that contains only +* the variables and functions that still exist in the IR. The symbol +* table will be used later during linking. +* +* There must NOT be any freed objects still referenced by the symbol +* table. That could cause the linker to dereference freed memory. +* +* We don't have to worry about types or interface-types here because those +* are fly-weights that are looked up by glsl_type. +*/ + foreach_in_list (ir_instruction, ir, shader->ir) { + switch (ir->ir_type) { + case ir_type_function: + shader->symbols->add_function((ir_function *) ir); + break; + case ir_type_variable: { + ir_variable *const var = (ir_variable *) ir; + + if (var->data.mode != ir_var_temporary) +shader->symbols->add_variable(var); + break; + } + default: + break; + } + } + + _mesa_glsl_initialize_derived_variables(ctx, shader); +} + void _mesa_glsl_compile_shader(struct gl_context *ctx, struct gl_shader *shader, bool dump_ast, bool dump_hir, bool force_recompile) @@ -1963,6 +2042,12 @@ _mesa_glsl_compile_shader(struct gl_context *ctx, struct gl_shader *shader, */ if (shader->CompileStatus == compile_success) return; + + if (shader->CompileStatus == compiled_no_opts) { + opt_shader_and_create_symbol_table(ctx, shader); + shader->CompileStatus = compile_success; + return; + } } if (!state->error) { @@ -1993,51 +2078,6 @@ _mesa_glsl_compile_shader(struct gl_context *ctx, struct gl_shader *shader, } } - - if (!state->error && !shader->ir->is_empty()) { - struct gl_