Mesa (master): st/mesa: Fix inversed test in st_api_destroy_drawable

2017-07-26 Thread Michel Dänzer 
Module: Mesa
Branch: master
Commit: 57132d126f2e129fc2959dcc2c0a8126389d07ba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=57132d126f2e129fc2959dcc2c0a8126389d07ba

Author: Michel Dänzer 
Date:   Thu Jul 27 11:12:24 2017 +0900

st/mesa: Fix inversed test in st_api_destroy_drawable

Fixes a drawable leak.

Fixes: bbc29393d3be ("st/mesa: create framebuffer iface hash table per
  st manager")
Bugzilla: https://bugs.freedesktop.org/101930
Tested-by: Nick Sarnie 
Reviewed-by: Brian Paul 

---

 src/mesa/state_tracker/st_manager.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_manager.c 
b/src/mesa/state_tracker/st_manager.c
index 6447403fc6..97bf89fc65 100644
--- a/src/mesa/state_tracker/st_manager.c
+++ b/src/mesa/state_tracker/st_manager.c
@@ -583,7 +583,7 @@ static void
 st_api_destroy_drawable(struct st_api *stapi,
 struct st_framebuffer_iface *stfbi)
 {
-   if (stfbi)
+   if (!stfbi)
   return;
 
st_framebuffer_iface_remove(stfbi->state_manager, stfbi);

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Mesa (master): radv/ac: port SI TC L1 write corruption fix.

2017-07-26 Thread Dave Airlie 
Module: Mesa
Branch: master
Commit: e77ff11ffe1a52b8e17a847f263746c849db3f11
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e77ff11ffe1a52b8e17a847f263746c849db3f11

Author: Dave Airlie 
Date:   Wed Jul 26 02:34:54 2017 +0100

radv/ac: port SI TC L1 write corruption fix.

This ports 72e46c988 to radv.
radeonsi: apply a TC L1 write corruption workaround for SI

Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver)
Reviewed-by: Bas Nieuwenhuizen 
Signed-off-by: Dave Airlie 

---

 src/amd/common/ac_nir_to_llvm.c | 8 +---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index a427f484b5..d6b450f8ee 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3400,7 +3400,10 @@ static void visit_image_store(struct nir_to_llvm_context 
*ctx,
char intrinsic_name[64];
const nir_variable *var = instr->variables[0]->var;
const struct glsl_type *type = glsl_without_array(var->type);
-
+   LLVMValueRef glc = ctx->i1false;
+   bool force_glc = ctx->options->chip_class == SI;
+   if (force_glc)
+   glc = ctx->i1true;
if (ctx->stage == MESA_SHADER_FRAGMENT)
ctx->shader_info->fs.writes_memory = true;
 
@@ -3410,7 +3413,7 @@ static void visit_image_store(struct nir_to_llvm_context 
*ctx,
params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, 
instr->src[0]),
LLVMConstInt(ctx->i32, 0, 
false), ""); /* vindex */
params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
-   params[4] = ctx->i1false;  /* glc */
+   params[4] = glc;  /* glc */
params[5] = ctx->i1false;  /* slc */
ac_build_intrinsic(>ac, 
"llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
   params, 6, 0);
@@ -3418,7 +3421,6 @@ static void visit_image_store(struct nir_to_llvm_context 
*ctx,
bool is_da = glsl_sampler_type_is_array(type) ||
 glsl_get_sampler_dim(type) == 
GLSL_SAMPLER_DIM_CUBE;
LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
-   LLVMValueRef glc = ctx->i1false;
LLVMValueRef slc = ctx->i1false;
 
params[0] = to_float(>ac, get_src(ctx, instr->src[2]));

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Mesa (master): radv/winsys: fix padding command stream for SI

2017-07-26 Thread Dave Airlie 
Module: Mesa
Branch: master
Commit: d4b079e708b8e4dab45f2f8467b2a8a4c37bbfa6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d4b079e708b8e4dab45f2f8467b2a8a4c37bbfa6

Author: Dave Airlie 
Date:   Wed Jul 26 03:25:24 2017 +0100

radv/winsys: fix padding command stream for SI

We were adding pad to size after creating the object, so we could
submit a CS bigger than the bo created for it.

Reviewed-by: Bas Nieuwenhuizen 
Signed-off-by: Dave Airlie 

---

 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index 0d89b950d2..ad4b0b3f9d 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -841,7 +841,7 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct 
radeon_winsys_ctx *_ctx,
uint32_t *ptr;
unsigned cnt = 0;
unsigned size = 0;
-
+   unsigned pad_words = 0;
if (preamble_cs)
size += preamble_cs->cdw;
 
@@ -850,6 +850,10 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct 
radeon_winsys_ctx *_ctx,
++cnt;
}
 
+   while(!size || (size & 7)) {
+   size++;
+   pad_words++;
+   }
assert(cnt);
 
bo = ws->buffer_create(ws, 4 * size, 4096, RADEON_DOMAIN_GTT, 
RADEON_FLAG_CPU_ACCESS);
@@ -867,10 +871,8 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct 
radeon_winsys_ctx *_ctx,
 
}
 
-   while(!size || (size & 7)) {
+   for (unsigned j = 0; j < pad_words; ++j)
*ptr++ = pad_word;
-   ++size;
-   }
 
memset(, 0, sizeof(request));
 

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Mesa (master): radv/ac: realign SI workaround with radeonsi.

2017-07-26 Thread Dave Airlie 
Module: Mesa
Branch: master
Commit: a81e99f50a718790de379087c9f5a636e32b2a28
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a81e99f50a718790de379087c9f5a636e32b2a28

Author: Dave Airlie 
Date:   Wed Jul 26 02:32:39 2017 +0100

radv/ac: realign SI workaround with radeonsi.

This ports: da7453666ae
radeonsi: don't apply the Z export bug workaround to Hainan
to radv.

Just noticed in passing.

Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver)
Reviewed-by: Bas Nieuwenhuizen 
Signed-off-by: Dave Airlie 

---

 src/amd/common/ac_nir_to_llvm.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 9a69066afa..a427f484b5 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -5815,10 +5815,11 @@ si_export_mrt_z(struct nir_to_llvm_context *ctx,
args.enabled_channels |= 0x4;
}
 
-   /* SI (except OLAND) has a bug that it only looks
+   /* SI (except OLAND and HAINAN) has a bug that it only looks
 * at the X writemask component. */
if (ctx->options->chip_class == SI &&
-   ctx->options->family != CHIP_OLAND)
+   ctx->options->family != CHIP_OLAND &&
+   ctx->options->family != CHIP_HAINAN)
args.enabled_channels |= 0x1;
 
ac_build_export(>ac, );

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Mesa (master): i965: Expose get_num_logical_layers outside of intel_mipmap_tree.c.

2017-07-26 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: e1d4030b0bc1c5ec4e48afcd6895b48b9ab5bfea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e1d4030b0bc1c5ec4e48afcd6895b48b9ab5bfea

Author: Kenneth Graunke 
Date:   Mon Jul 24 11:44:46 2017 -0700

i965: Expose get_num_logical_layers outside of intel_mipmap_tree.c.

I want to use it in brw_clear.c.

Reviewed-by: Lionel Landwerlin 

---

 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 10 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  3 +++
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index ed7cb8e215..628d80c0ff 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -393,8 +393,8 @@ intel_lower_compressed_format(struct brw_context *brw, 
mesa_format format)
}
 }
 
-static unsigned
-get_num_logical_layers(const struct intel_mipmap_tree *mt, unsigned level)
+unsigned
+brw_get_num_logical_layers(const struct intel_mipmap_tree *mt, unsigned level)
 {
if (mt->surf.dim == ISL_SURF_DIM_3D)
   return minify(mt->surf.logical_level0_px.depth, level);
@@ -440,7 +440,7 @@ create_aux_state_map(struct intel_mipmap_tree *mt,
 
uint32_t total_slices = 0;
for (uint32_t level = 0; level < levels; level++)
-  total_slices += get_num_logical_layers(mt, level);
+  total_slices += brw_get_num_logical_layers(mt, level);
 
const size_t per_level_array_size = levels * sizeof(enum isl_aux_state *);
 
@@ -458,7 +458,7 @@ create_aux_state_map(struct intel_mipmap_tree *mt,
enum isl_aux_state *s = data + per_level_array_size;
for (uint32_t level = 0; level < levels; level++) {
   per_level_arr[level] = s;
-  const unsigned level_layers = get_num_logical_layers(mt, level);
+  const unsigned level_layers = brw_get_num_logical_layers(mt, level);
   for (uint32_t a = 0; a < level_layers; a++)
  *(s++) = initial;
}
@@ -1871,7 +1871,7 @@ miptree_layer_range_length(const struct intel_mipmap_tree 
*mt, uint32_t level,
 {
assert(level <= mt->last_level);
 
-   const uint32_t total_num_layers = get_num_logical_layers(mt, level);
+   const uint32_t total_num_layers = brw_get_num_logical_layers(mt, level);
assert(start_layer < total_num_layers);
if (num_layers == INTEL_REMAINING_LAYERS)
   num_layers = total_num_layers - start_layer;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 3628345c4e..2179318413 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -419,6 +419,9 @@ intel_depth_format_for_depthstencil_format(mesa_format 
format);
 mesa_format
 intel_lower_compressed_format(struct brw_context *brw, mesa_format format);
 
+unsigned
+brw_get_num_logical_layers(const struct intel_mipmap_tree *mt, unsigned level);
+
 /** \brief Assert that the level and layer are valid for the miptree. */
 void
 intel_miptree_check_level_layer(const struct intel_mipmap_tree *mt,

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Mesa (master): i965: Only do depth resolves prior to clearing when needed

2017-07-26 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: 6db193701e7d03e0eadd54fc3e1b3d75719bc4ae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6db193701e7d03e0eadd54fc3e1b3d75719bc4ae

Author: Jason Ekstrand 
Date:   Wed Jun 14 18:54:28 2017 -0700

i965: Only do depth resolves prior to clearing when needed

When changing the clear value, we need to resolve any fast cleared data.

Previously, we were performing resolves on every slice with HiZ enabled.
We only need to resolve slices that a) have fast clear data, and b)
aren't about to be cleared to the new color.  In the latter case, we
were actually doing a resolve, and then a fast clear - when we could
skip both, causing the existing fast cleared area to be updated to the
new clear value for no additional work.

This patch stops using intel_miptree_prepare_access in favor of a more
optimal open coded loop that knows about our clear operation.

v2: (by Ken) Rebase on islification, write a real commit message.

Reviewed-by: Kenneth Graunke 
Reviewed-by: Lionel Landwerlin 

---

 src/mesa/drivers/dri/i965/brw_clear.c | 39 ---
 1 file changed, 36 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c 
b/src/mesa/drivers/dri/i965/brw_clear.c
index 772d7c3399..0429b3b6f5 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -165,9 +165,42 @@ brw_fast_clear_depth(struct gl_context *ctx)
 * flags out of the HiZ buffer into the real depth buffer.
 */
if (mt->fast_clear_color.f32[0] != ctx->Depth.Clear) {
-  intel_miptree_prepare_access(brw, mt, 0, INTEL_REMAINING_LEVELS,
-   0, INTEL_REMAINING_LAYERS,
-   ISL_AUX_USAGE_HIZ, false);
+  for (uint32_t level = mt->first_level; level <= mt->last_level; level++) 
{
+ if (!intel_miptree_level_has_hiz(mt, level))
+continue;
+
+ const unsigned level_layers = brw_get_num_logical_layers(mt, level);
+
+ for (uint32_t layer = 0; layer < level_layers; layer++) {
+if (level == depth_irb->mt_level &&
+layer >= depth_irb->mt_layer &&
+layer < depth_irb->mt_layer + num_layers) {
+   /* We're going to clear this layer anyway.  Leave it alone. */
+   continue;
+}
+
+enum isl_aux_state aux_state =
+   intel_miptree_get_aux_state(mt, level, layer);
+
+if (aux_state != ISL_AUX_STATE_CLEAR &&
+aux_state != ISL_AUX_STATE_COMPRESSED_CLEAR) {
+   /* This slice doesn't have any fast-cleared bits. */
+   continue;
+}
+
+/* If we got here, then the level may have fast-clear bits that
+ * use the old clear value.  We need to do a depth resolve to get
+ * rid of their use of the clear value before we can change it.
+ * Fortunately, few applications ever change their depth clear
+ * value so this shouldn't happen often.
+ */
+intel_hiz_exec(brw, mt, level, layer, 1,
+   BLORP_HIZ_OP_DEPTH_RESOLVE);
+intel_miptree_set_aux_state(brw, mt, level, layer, 1,
+ISL_AUX_STATE_RESOLVED);
+ }
+  }
+
   mt->fast_clear_color.f32[0] = ctx->Depth.Clear;
}
 

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Mesa (master): i965/clear: Don't perform redundant depth clears

2017-07-26 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: f6e478c213c30203e9623d5657fd3789cf6368f3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f6e478c213c30203e9623d5657fd3789cf6368f3

Author: Jason Ekstrand 
Date:   Wed Jun 14 18:54:29 2017 -0700

i965/clear: Don't perform redundant depth clears

We already have this little optimization for color clears.  Now that
we're actually tracking whether or not a slice has any fast-clear
blocks, it's easy enough to add for depth clears too.

Improves performance of GFXBench 4 TRex at 1920x1080 by:
- Skylake GT4: 0.905932% +/- 0.0620197% (n = 30)
- Apollolake:  0.382434% +/- 0.1134730% (n = 25)

v2: (by Ken) Rebase and drop intel_mipmap_tree.c changes, as they're
no longer necessary (other patches already landed to do that part)

Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_clear.c | 34 +++---
 1 file changed, 31 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c 
b/src/mesa/drivers/dri/i965/brw_clear.c
index 0429b3b6f5..5eb2423792 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -204,9 +204,37 @@ brw_fast_clear_depth(struct gl_context *ctx)
   mt->fast_clear_color.f32[0] = ctx->Depth.Clear;
}
 
-   intel_hiz_exec(brw, mt, depth_irb->mt_level,
-  depth_irb->mt_layer, num_layers,
-  BLORP_HIZ_OP_DEPTH_CLEAR);
+   bool need_clear = false;
+   for (unsigned a = 0; a < num_layers; a++) {
+  enum isl_aux_state aux_state =
+ intel_miptree_get_aux_state(mt, depth_irb->mt_level,
+ depth_irb->mt_layer + a);
+
+  if (aux_state != ISL_AUX_STATE_CLEAR) {
+ need_clear = true;
+ break;
+  }
+   }
+
+   if (!need_clear) {
+  /* If all of the layers we intend to clear are already in the clear
+   * state then simply updating the miptree fast clear value is sufficient
+   * to change their clear value.
+   */
+  return true;
+   }
+
+   for (unsigned a = 0; a < num_layers; a++) {
+  enum isl_aux_state aux_state =
+ intel_miptree_get_aux_state(mt, depth_irb->mt_level,
+ depth_irb->mt_layer + a);
+
+  if (aux_state != ISL_AUX_STATE_CLEAR) {
+ intel_hiz_exec(brw, mt, depth_irb->mt_level,
+depth_irb->mt_layer + a, 1,
+BLORP_HIZ_OP_DEPTH_CLEAR);
+  }
+   }
 
/* Now, the HiZ buffer contains data that needs to be resolved to the depth
 * buffer.

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Mesa (master): gallium/radeon: make S_FIXED function signed and move it to shared code

2017-07-26 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: 433f6f7ac9ed6624fec02cc055c3bfa247dba185
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=433f6f7ac9ed6624fec02cc055c3bfa247dba185

Author: Marek Olšák 
Date:   Tue Jul 25 17:29:58 2017 +0200

gallium/radeon: make S_FIXED function signed and move it to shared code

This fixes a bug uncovered by:
2412c4c81ea0488df865817a0de91ec46e359b72
util: Make CLAMP turn NaN into MIN.

Cc: 17.2 
Reviewed-by: Roland Scheidegger 
Reviewed-by: Kenneth Graunke 
Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/r600/r600_pipe.h  | 4 
 src/gallium/drivers/radeon/r600_pipe_common.h | 5 +
 src/gallium/drivers/radeonsi/si_state.c   | 5 -
 3 files changed, 5 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_pipe.h 
b/src/gallium/drivers/r600/r600_pipe.h
index 3fa7d77d37..c9294a7c58 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -925,10 +925,6 @@ static inline void radeon_set_ctl_const(struct 
radeon_winsys_cs *cs, unsigned re
 /*
  * common helpers
  */
-static inline uint32_t S_FIXED(float value, uint32_t frac_bits)
-{
-   return value * (1 << frac_bits);
-}
 
 /* 12.4 fixed-point */
 static inline unsigned r600_pack_float_12p4(float x)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 5c761f3ee4..c2fb3690d2 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -1006,4 +1006,9 @@ vi_dcc_enabled(struct r600_texture *tex, unsigned level)
(((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | 
   \
 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
 
+static inline int S_FIXED(float value, unsigned frac_bits)
+{
+   return value * (1 << frac_bits);
+}
+
 #endif
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 7e3d1a02e0..42d81e7446 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -74,11 +74,6 @@ static unsigned si_map_swizzle(unsigned swizzle)
}
 }
 
-static uint32_t S_FIXED(float value, uint32_t frac_bits)
-{
-   return value * (1 << frac_bits);
-}
-
 /* 12.4 fixed-point */
 static unsigned si_pack_float_12p4(float x)
 {

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Mesa (master): st/mesa: also clamp and quantize per-unit lod bias

2017-07-26 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: 033b4e434057a6cc885f443792167dfabfb077b6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=033b4e434057a6cc885f443792167dfabfb077b6

Author: Marek Olšák 
Date:   Tue Jul 25 17:33:05 2017 +0200

st/mesa: also clamp and quantize per-unit lod bias

Reviewed-by: Samuel Pitoiset 
Reviewed-by: Nicolai Hähnle 

---

 src/mesa/state_tracker/st_atom_sampler.c | 7 ---
 src/mesa/state_tracker/st_cb_texture.c   | 2 +-
 src/mesa/state_tracker/st_texture.h  | 1 +
 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/mesa/state_tracker/st_atom_sampler.c 
b/src/mesa/state_tracker/st_atom_sampler.c
index 208b6f7a1d..d9e8de3c9e 100644
--- a/src/mesa/state_tracker/st_atom_sampler.c
+++ b/src/mesa/state_tracker/st_atom_sampler.c
@@ -105,6 +105,7 @@ void
 st_convert_sampler(const struct st_context *st,
const struct gl_texture_object *texobj,
const struct gl_sampler_object *msamp,
+   float tex_unit_lod_bias,
struct pipe_sampler_state *sampler)
 {
memset(sampler, 0, sizeof(*sampler));
@@ -119,7 +120,7 @@ st_convert_sampler(const struct st_context *st,
if (texobj->Target != GL_TEXTURE_RECTANGLE_ARB)
   sampler->normalized_coords = 1;
 
-   sampler->lod_bias = msamp->LodBias;
+   sampler->lod_bias = msamp->LodBias + tex_unit_lod_bias;
/* Reduce the number of states by allowing only the values that AMD GCN
 * can represent. Apps use lod_bias for smooth transitions to bigger mipmap
 * levels.
@@ -241,9 +242,9 @@ st_convert_sampler_from_unit(const struct st_context *st,
 
msamp = _mesa_get_samplerobj(ctx, texUnit);
 
-   st_convert_sampler(st, texobj, msamp, sampler);
+   st_convert_sampler(st, texobj, msamp, ctx->Texture.Unit[texUnit].LodBias,
+  sampler);
 
-   sampler->lod_bias += ctx->Texture.Unit[texUnit].LodBias;
sampler->seamless_cube_map |= ctx->Texture.CubeMapSeamless;
 }
 
diff --git a/src/mesa/state_tracker/st_cb_texture.c 
b/src/mesa/state_tracker/st_cb_texture.c
index d0a7b55c58..db2913ed9e 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -2972,7 +2972,7 @@ st_NewTextureHandle(struct gl_context *ctx, struct 
gl_texture_object *texObj,
   if (!st_finalize_texture(ctx, pipe, texObj, 0))
  return 0;
 
-  st_convert_sampler(st, texObj, sampObj, );
+  st_convert_sampler(st, texObj, sampObj, 0, );
   view = st_get_texture_sampler_view_from_stobj(st, stObj, sampObj, 0);
} else {
   view = st_get_buffer_sampler_view_from_stobj(st, stObj);
diff --git a/src/mesa/state_tracker/st_texture.h 
b/src/mesa/state_tracker/st_texture.h
index a6f6ee8ebe..8448f4c6f0 100644
--- a/src/mesa/state_tracker/st_texture.h
+++ b/src/mesa/state_tracker/st_texture.h
@@ -281,6 +281,7 @@ void
 st_convert_sampler(const struct st_context *st,
const struct gl_texture_object *texobj,
const struct gl_sampler_object *msamp,
+   float tex_unit_lod_bias,
struct pipe_sampler_state *sampler);
 
 void

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Mesa (master): radeonsi: decrease the number of compiler threads

2017-07-26 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: ed2b3f5c81b76281ff0e4728928ac55944b930b8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed2b3f5c81b76281ff0e4728928ac55944b930b8

Author: Marek Olšák 
Date:   Mon Jul 24 23:56:30 2017 +0200

radeonsi: decrease the number of compiler threads

Cc: 17.2 
Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_pipe.c | 2 +-
 src/gallium/drivers/radeonsi/si_pipe.h | 9 +++--
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 2b0f9d3415..067efb963a 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -970,7 +970,7 @@ struct pipe_screen *radeonsi_screen_create(struct 
radeon_winsys *ws,
 
if (!util_queue_init(>shader_compiler_queue_low_priority,
 "si_shader_low",
-32, num_compiler_threads,
+32, num_compiler_threads_lowprio,
 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
   si_destroy_shader_cache(sscreen);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h 
b/src/gallium/drivers/radeonsi/si_pipe.h
index c028aba308..d25705b0c6 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -113,10 +113,15 @@ struct si_screen {
 
/* Shader compiler queue for multithreaded compilation. */
struct util_queue   shader_compiler_queue;
-   LLVMTargetMachineReftm[4]; /* used by the queue only */
+   /* Use at most 3 normal compiler threads on quadcore and better.
+* Hyperthreaded CPUs report the number of threads, but we want
+* the number of cores. */
+   LLVMTargetMachineReftm[3]; /* used by the queue only */
 
struct util_queue   shader_compiler_queue_low_priority;
-   LLVMTargetMachineReftm_low_priority[4];
+   /* Use at most 2 low priority threads on quadcore and better.
+* We want to minimize the impact on multithreaded Mesa. */
+   LLVMTargetMachineReftm_low_priority[2]; /* at most 2 
threads */
 };
 
 struct si_blend_color {

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Mesa (master): ac/surface: fix hybrid graphics where APU=GFX9, dGPU=older

2017-07-26 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: 5e81df0f103667d888bd346e148843f510a80adc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e81df0f103667d888bd346e148843f510a80adc

Author: Marek Olšák 
Date:   Tue Jul 25 00:08:55 2017 +0200

ac/surface: fix hybrid graphics where APU=GFX9, dGPU=older

v2: don't do it for compressed textures (bpp = 0)

Cc: 17.2 
Reviewed-by: Alex Deucher  (v1)
Reviewed-by: Nicolai Hähnle  (v1)

---

 src/amd/common/ac_surface.c | 12 
 1 file changed, 12 insertions(+)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index cd3d7b715c..26f3729adf 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -257,6 +257,18 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
AddrSurfInfoIn->width = u_minify(config->info.width, level);
AddrSurfInfoIn->height = u_minify(config->info.height, level);
 
+   /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
+* because GFX9 needs linear alignment of 256 bytes.
+*/
+   if (config->info.levels == 1 &&
+   AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED &&
+   AddrSurfInfoIn->bpp) {
+   unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
+
+   assert(util_is_power_of_two(AddrSurfInfoIn->bpp));
+   AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
+   }
+
if (config->is_3d)
AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
else if (config->is_cube)

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Mesa (master): st/mesa: fix unconditional return in st_framebuffer_iface_remove

2017-07-26 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: 914f11e75b8ebe8a0faab76ce25fe185ab580eee
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=914f11e75b8ebe8a0faab76ce25fe185ab580eee

Author: Marek Olšák 
Date:   Tue Jul 25 18:28:06 2017 +0200

st/mesa: fix unconditional return in st_framebuffer_iface_remove

Noticed by James Legg @ Feral.

Cc: 17.2 
Reviewed-by: Samuel Pitoiset 

---

 src/mesa/state_tracker/st_manager.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_manager.c 
b/src/mesa/state_tracker/st_manager.c
index 834bcc9f8c..6447403fc6 100644
--- a/src/mesa/state_tracker/st_manager.c
+++ b/src/mesa/state_tracker/st_manager.c
@@ -560,7 +560,7 @@ st_framebuffer_iface_remove(struct st_manager *smapi,
   (struct st_manager_private *)smapi->st_manager_private;
struct hash_entry *entry;
 
-   if (!smPriv || !smPriv->stfbi_ht);
+   if (!smPriv || !smPriv->stfbi_ht)
   return;
 
mtx_lock(>st_mutex);

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Mesa (master): drirc: whitelist glthread for Mount and Blade Warband

2017-07-26 Thread Marek Olšák 
Module: Mesa
Branch: master
Commit: a7617a49fbde2fcfccdab22886aeabdbf8abb8e4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7617a49fbde2fcfccdab22886aeabdbf8abb8e4

Author: Marek Olšák 
Date:   Wed Jul 26 15:21:45 2017 +0200

drirc: whitelist glthread for Mount and Blade Warband

From 25-26 min fps to 31, used the game in conjuction with a mod (full
invasion 2) beaumaris castle map and 200 bots.

---

 src/mesa/drivers/dri/common/drirc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/common/drirc 
b/src/mesa/drivers/dri/common/drirc
index 30ac9c839b..5ce0308d0d 100644
--- a/src/mesa/drivers/dri/common/drirc
+++ b/src/mesa/drivers/dri/common/drirc
@@ -205,6 +205,9 @@ TODO: document the other workarounds.
 
 
 
+
+
+
 
 
 

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Mesa (master): egl: move KHR_no_error vs debug/ robustness check further down

2017-07-26 Thread Emil Velikov 
Module: Mesa
Branch: master
Commit: 39bf7756b9a56b4827fecabfca00a8139feecd25
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=39bf7756b9a56b4827fecabfca00a8139feecd25

Author: Grigori Goronzy 
Date:   Wed Jul 19 23:51:55 2017 +0200

egl: move KHR_no_error vs debug/robustness check further down

We'll fail to flag an error if the context flags appear after the
no-error attribute in the context attribute list.

Delay the check to after attribute parsing to fix this.

Fixes: 4909519a665 ("egl: Add EGL_KHR_create_context_no_error support")
Cc: mesa-sta...@lists.freedesktop.org
[Emil Velikov: add fixes/stable tags, commit message polish]
Reviewed-by: Emil Velikov 

---

 src/egl/main/eglcontext.c | 21 ++---
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/src/egl/main/eglcontext.c b/src/egl/main/eglcontext.c
index 1a8e9bda1a..1b03160439 100644
--- a/src/egl/main/eglcontext.c
+++ b/src/egl/main/eglcontext.c
@@ -328,17 +328,6 @@ _eglParseContextAttribList(_EGLContext *ctx, _EGLDisplay 
*dpy,
 break;
  }
 
- /* The EGL_KHR_create_context_no_error spec says:
-  *
-  *"BAD_MATCH is generated if the EGL_CONTEXT_OPENGL_NO_ERROR_KHR 
is TRUE at
-  *the same time as a debug or robustness context is specified."
-  */
- if (ctx->Flags & EGL_CONTEXT_OPENGL_DEBUG_BIT_KHR ||
- ctx->Flags & EGL_CONTEXT_OPENGL_ROBUST_ACCESS_BIT_KHR) {
-err = EGL_BAD_MATCH;
-break;
- }
-
  /* Canonicalize value to EGL_TRUE/EGL_FALSE definitions */
  ctx->NoError = !!val;
  break;
@@ -489,6 +478,16 @@ _eglParseContextAttribList(_EGLContext *ctx, _EGLDisplay 
*dpy,
   break;
}
 
+   /* The EGL_KHR_create_context_no_error spec says:
+*
+*"BAD_MATCH is generated if the EGL_CONTEXT_OPENGL_NO_ERROR_KHR is 
TRUE at
+*the same time as a debug or robustness context is specified."
+*/
+   if (ctx->NoError && (ctx->Flags & EGL_CONTEXT_OPENGL_DEBUG_BIT_KHR ||
+ctx->Flags & 
EGL_CONTEXT_OPENGL_ROBUST_ACCESS_BIT_KHR)) {
+  err = EGL_BAD_MATCH;
+   }
+
if ((ctx->Flags & ~(EGL_CONTEXT_OPENGL_DEBUG_BIT_KHR
   | EGL_CONTEXT_OPENGL_FORWARD_COMPATIBLE_BIT_KHR
   | EGL_CONTEXT_OPENGL_ROBUST_ACCESS_BIT_KHR)) != 0) {

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Mesa (master): radv: rename physical_device->uuid[] to cache_uuid[]

2017-07-26 Thread Timothy Arceri 
Module: Mesa
Branch: master
Commit: a973b9a9f8fe50f3d34d00fbf104e19d00f12560
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a973b9a9f8fe50f3d34d00fbf104e19d00f12560

Author: Andres Rodriguez 
Date:   Wed Jul 12 18:45:29 2017 -0400

radv: rename physical_device->uuid[] to cache_uuid[]

We have a few UUIDs, so lets be more specific.

Signed-off-by: Andres Rodriguez 
Reviewed-by: Timothy Arceri 

---

 src/amd/vulkan/radv_device.c | 4 ++--
 src/amd/vulkan/radv_pipeline_cache.c | 4 ++--
 src/amd/vulkan/radv_private.h| 2 +-
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 5244c157c3..752d70be4b 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -311,7 +311,7 @@ radv_physical_device_init(struct radv_physical_device 
*device,
goto fail;
}
 
-   if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
+   if (radv_device_get_cache_uuid(device->rad_info.family, 
device->cache_uuid)) {
radv_finish_wsi(device);
device->ws->destroy(device->ws);
result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
@@ -775,7 +775,7 @@ void radv_GetPhysicalDeviceProperties(
};
 
strcpy(pProperties->deviceName, pdevice->name);
-   memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
+   memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, 
VK_UUID_SIZE);
 }
 
 void radv_GetPhysicalDeviceProperties2KHR(
diff --git a/src/amd/vulkan/radv_pipeline_cache.c 
b/src/amd/vulkan/radv_pipeline_cache.c
index e57c99b8e9..86479f6623 100644
--- a/src/amd/vulkan/radv_pipeline_cache.c
+++ b/src/amd/vulkan/radv_pipeline_cache.c
@@ -332,7 +332,7 @@ radv_pipeline_cache_load(struct radv_pipeline_cache *cache,
return;
if (header.device_id != device->physical_device->rad_info.pci_id)
return;
-   if (memcmp(header.uuid, device->physical_device->uuid, VK_UUID_SIZE) != 
0)
+   if (memcmp(header.uuid, device->physical_device->cache_uuid, 
VK_UUID_SIZE) != 0)
return;
 
char *end = (void *) data + size;
@@ -431,7 +431,7 @@ VkResult radv_GetPipelineCacheData(
header->header_version = VK_PIPELINE_CACHE_HEADER_VERSION_ONE;
header->vendor_id = 0x1002;
header->device_id = device->physical_device->rad_info.pci_id;
-   memcpy(header->uuid, device->physical_device->uuid, VK_UUID_SIZE);
+   memcpy(header->uuid, device->physical_device->cache_uuid, VK_UUID_SIZE);
p += header->header_size;
 
struct cache_entry *entry;
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 8cd5ec0046..21a8d410f0 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -267,8 +267,8 @@ struct radv_physical_device {
struct radeon_info rad_info;
charpath[20];
const char *name;
-   uint8_t uuid[VK_UUID_SIZE];
uint8_t device_uuid[VK_UUID_SIZE];
+   uint8_t cache_uuid[VK_UUID_SIZE];
 
int local_fd;
struct wsi_device   wsi_device;

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Mesa (master): radeonsi: fix detection of DRAW_INDIRECT_MULTI on SI

2017-07-26 Thread Nicolai Hähnle 
Module: Mesa
Branch: master
Commit: 65fbaab0b74b6b5a2ac483d48beeefa0a29ff15e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=65fbaab0b74b6b5a2ac483d48beeefa0a29ff15e

Author: Nicolai Hähnle 
Date:   Tue Jul 25 16:47:27 2017 +0200

radeonsi: fix detection of DRAW_INDIRECT_MULTI on SI

The firmware version numbers for SI were wrong. The new numbers are probably
too conservative (we don't have a definitive answer by the firmware team),
but DRAW_INDIRECT_MULTI has been confirmed to work with these versions on
Tahiti (by Gustaw) and on Verde (by myself).

While this is technically adding a feature, it's a feature we thought we had
for a long time. The change is small enough and we're early enough in the 17.2
release cycle that it should still go in.

Reported-by: Gustaw Smolarczyk 
Cc: 17.2 
Acked-by: Alex Deucher 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_pipe.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 0bc30027ea..2b0f9d3415 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1002,8 +1002,8 @@ struct pipe_screen *radeonsi_screen_create(struct 
radeon_winsys *ws,
 sscreen->b.info.pfp_fw_version >= 211 &&
 sscreen->b.info.me_fw_version >= 173) ||
(sscreen->b.chip_class == SI &&
-sscreen->b.info.pfp_fw_version >= 121 &&
-sscreen->b.info.me_fw_version >= 87);
+sscreen->b.info.pfp_fw_version >= 79 &&
+sscreen->b.info.me_fw_version >= 142);
 
sscreen->has_ds_bpermute = sscreen->b.chip_class >= VI;
sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 
&&

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Mesa (master): radeonsi/gfx9: reduce max threads per block to 1024 on gfx9+

2017-07-26 Thread Nicolai Hähnle 
Module: Mesa
Branch: master
Commit: a0e6b9a2db5aa5f06a4f60d270aca8344e7d8b3f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0e6b9a2db5aa5f06a4f60d270aca8344e7d8b3f

Author: Nicolai Hähnle 
Date:   Tue Jul 25 14:32:03 2017 +0200

radeonsi/gfx9: reduce max threads per block to 1024 on gfx9+

The number of supported waves per thread group has been reduced to 16
with gfx9. Trying to use 32 waves causes hangs, and barriers might
not work correctly with > 16 waves.

Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeon/r600_pipe_common.c | 39 ---
 1 file changed, 24 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index fd67d9ae1b..cc52d6ba39 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -1024,6 +1024,25 @@ const char *r600_get_llvm_processor_name(enum 
radeon_family family)
}
 }
 
+static unsigned get_max_threads_per_block(struct r600_common_screen *screen,
+ enum pipe_shader_ir ir_type)
+{
+   if (ir_type != PIPE_SHADER_IR_TGSI)
+   return 256;
+
+   /* Only 16 waves per thread-group on gfx9. */
+   if (screen->chip_class >= GFX9)
+   return 1024;
+
+   /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
+* round number.
+*/
+   if (screen->chip_class >= SI)
+   return 2048;
+
+   return 256;
+}
+
 static int r600_get_compute_param(struct pipe_screen *screen,
 enum pipe_shader_ir ir_type,
 enum pipe_compute_cap param,
@@ -1078,27 +1097,17 @@ static int r600_get_compute_param(struct pipe_screen 
*screen,
case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
if (ret) {
uint64_t *block_size = ret;
-   if (rscreen->chip_class >= SI &&
-   ir_type == PIPE_SHADER_IR_TGSI) {
-   block_size[0] = 2048;
-   block_size[1] = 2048;
-   block_size[2] = 2048;
-   } else {
-   block_size[0] = 256;
-   block_size[1] = 256;
-   block_size[2] = 256;
-   }
+   unsigned threads_per_block = 
get_max_threads_per_block(rscreen, ir_type);
+   block_size[0] = threads_per_block;
+   block_size[1] = threads_per_block;
+   block_size[2] = threads_per_block;
}
return 3 * sizeof(uint64_t);
 
case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
if (ret) {
uint64_t *max_threads_per_block = ret;
-   if (rscreen->chip_class >= SI &&
-   ir_type == PIPE_SHADER_IR_TGSI)
-   *max_threads_per_block = 2048;
-   else
-   *max_threads_per_block = 256;
+   *max_threads_per_block = 
get_max_threads_per_block(rscreen, ir_type);
}
return sizeof(uint64_t);
case PIPE_COMPUTE_CAP_ADDRESS_BITS:

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Mesa (master): anv/cmd_buffer: fix off by one error in assertion

2017-07-26 Thread Iago Toral Quiroga 
Module: Mesa
Branch: master
Commit: a848e693efc8e2a1d355dc1076409968b374153f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a848e693efc8e2a1d355dc1076409968b374153f

Author: Iago Toral Quiroga 
Date:   Wed Jul 19 12:49:33 2017 +0200

anv/cmd_buffer: fix off by one error in assertion

Cc: "17.2" 
Reviewed-by: Lionel Landwerlin 

---

 src/intel/vulkan/anv_cmd_buffer.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index 7317674843..3b59af8f6f 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -566,7 +566,7 @@ void anv_CmdBindVertexBuffers(
/* We have to defer setting up vertex buffer since we need the buffer
 * stride from the pipeline. */
 
-   assert(firstBinding + bindingCount < MAX_VBS);
+   assert(firstBinding + bindingCount <= MAX_VBS);
for (uint32_t i = 0; i < bindingCount; i++) {
   vb[firstBinding + i].buffer = anv_buffer_from_handle(pBuffers[i]);
   vb[firstBinding + i].offset = pOffsets[i];

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Mesa (master): anv: only expose up to 28 vertex attributes

2017-07-26 Thread Iago Toral Quiroga 
Module: Mesa
Branch: master
Commit: 31f1863ace73d31a579e5c36252a957818ad09cf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=31f1863ace73d31a579e5c36252a957818ad09cf

Author: Iago Toral Quiroga 
Date:   Fri Jul 21 08:32:24 2017 +0200

anv: only expose up to 28 vertex attributes

The EU limit of 128 GRFs should allow 32 vertex elements of 4 GRFs.
However, the maximum allowed value of "Vertex URB Entry Read Length"
in SIMD8 is 15. And 15 * 8 = 120 gives us a limit of 30 vertex elements.
Because we also need to reserve a vertex buffer to upload
VertexIndex/InstanceIndex and another to upload DrawID when needed,
we can only expose 28.

Cc: "17.2" 
Reviewed-by: Lionel Landwerlin 

---

 src/intel/vulkan/anv_private.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index faf7849891..86c430397c 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -89,7 +89,7 @@ struct gen_l3_config;
  */
 #define ANV_HZ_FC_VAL 1.0f
 
-#define MAX_VBS 31
+#define MAX_VBS 28
 #define MAX_SETS 8
 #define MAX_RTS  8
 #define MAX_VIEWPORTS   16

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