Mesa (master): st/glsl_to_nir: delay adding built-in uniforms to Parameters list
Module: Mesa
Branch: master
Commit: f6c0504abc486536175ce879042df7110861152e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f6c0504abc486536175ce879042df7110861152e
Author: Timothy Arceri
Date: Wed Nov 1 14:15:22 2017 +1100
st/glsl_to_nir: delay adding built-in uniforms to Parameters list
Delaying adding built-in uniforms until after we convert to NIR
gives us a better chance to optimise them away. Also NIR allows
us to iterate over the uniforms directly so should be faster.
Reviewed-by: Nicolai Hähnle
---
src/mesa/state_tracker/st_glsl_to_nir.cpp | 68 +++---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 +-
2 files changed, 34 insertions(+), 36 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 5b37d2cd63..bbef830a2e 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -242,6 +242,39 @@ st_glsl_to_nir(struct st_context *st, struct gl_program
*prog,
nir = glsl_to_nir(shader_program, stage, options);
+ /* Make a pass over the IR to add state references for any built-in
+* uniforms that are used. This has to be done now (during linking).
+* Code generation doesn't happen until the first time this shader is
+* used for rendering. Waiting until then to generate the parameters is
+* too late. At that point, the values for the built-in uniforms won't
+* get sent to the shader.
+*/
+ nir_foreach_variable(var, &nir->uniforms) {
+ if (strncmp(var->name, "gl_", 3) == 0) {
+ const nir_state_slot *const slots = var->state_slots;
+ assert(var->state_slots != NULL);
+
+ for (unsigned int i = 0; i < var->num_state_slots; i++) {
+_mesa_add_state_reference(prog->Parameters,
+ (gl_state_index *)slots[i].tokens);
+ }
+ }
+ }
+
+ /* Avoid reallocation of the program parameter list, because the uniform
+* storage is only associated with the original parameter list.
+* This should be enough for Bitmap and DrawPixels constants.
+*/
+ _mesa_reserve_parameter_storage(prog->Parameters, 8);
+
+ /* This has to be done last. Any operation the can cause
+* prog->ParameterValues to get reallocated (e.g., anything that adds a
+* program constant) has to happen before creating this linkage.
+*/
+ _mesa_associate_uniform_storage(st->ctx, shader_program, prog, true);
+
+ st_set_prog_affected_state_flags(prog);
+
NIR_PASS_V(nir, nir_lower_io_to_temporaries,
nir_shader_get_entrypoint(nir),
true, true);
@@ -388,29 +421,6 @@ st_nir_get_mesa_program(struct gl_context *ctx,
_mesa_generate_parameters_list_for_uniforms(ctx, shader_program, shader,
prog->Parameters);
- /* Make a pass over the IR to add state references for any built-in
-* uniforms that are used. This has to be done now (during linking).
-* Code generation doesn't happen until the first time this shader is
-* used for rendering. Waiting until then to generate the parameters is
-* too late. At that point, the values for the built-in uniforms won't
-* get sent to the shader.
-*/
- foreach_in_list(ir_instruction, node, shader->ir) {
- ir_variable *var = node->as_variable();
-
- if ((var == NULL) || (var->data.mode != ir_var_uniform) ||
- (strncmp(var->name, "gl_", 3) != 0))
- continue;
-
- const ir_state_slot *const slots = var->get_state_slots();
- assert(slots != NULL);
-
- for (unsigned int i = 0; i < var->get_num_state_slots(); i++) {
- _mesa_add_state_reference(prog->Parameters,
- (gl_state_index *) slots[i].tokens);
- }
- }
-
if (ctx->_Shader->Flags & GLSL_DUMP) {
_mesa_log("\n");
_mesa_log("GLSL IR for linked %s program %d:\n",
@@ -423,18 +433,6 @@ st_nir_get_mesa_program(struct gl_context *ctx,
prog->ExternalSamplersUsed = gl_external_samplers(prog);
_mesa_update_shader_textures_used(shader_program, prog);
- /* Avoid reallocation of the program parameter list, because the uniform
-* storage is only associated with the original parameter list.
-* This should be enough for Bitmap and DrawPixels constants.
-*/
- _mesa_reserve_parameter_storage(prog->Parameters, 8);
-
- /* This has to be done last. Any operation the can cause
-* prog->ParameterValues to get reallocated (e.g., anything that adds a
-* program constant) has to happen before creating this linkage.
-*/
- _mesa_associate_uniform_storage(ctx, shader_program, prog, true);
-
struct st_vertex_program *stvp;
struct st_common_program *stp;
struct st_fragment_program *stfp;
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 54e1961830..fd9df61f4f 100644
--- a/src/mesa/st
Mesa (master): st/glsl_to_nir: generate NIR earlier
Module: Mesa
Branch: master
Commit: c980a3aa31335b9198814f7bb98e9cde01895444
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c980a3aa31335b9198814f7bb98e9cde01895444
Author: Timothy Arceri
Date: Wed Nov 1 17:28:09 2017 +1100
st/glsl_to_nir: generate NIR earlier
We want to use nir_shader_gather_info() the GLSL IR version might
be including varyings that NIR later eliminates. To do this we
need to generate NIR before we we start using the in/out bitmasks.
Reviewed-by: Nicolai Hähnle
---
src/mesa/state_tracker/st_glsl_to_nir.cpp | 6 +
src/mesa/state_tracker/st_program.c | 45 ++-
2 files changed, 14 insertions(+), 37 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index bbef830a2e..d59e472584 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -407,6 +407,7 @@ st_nir_get_mesa_program(struct gl_context *ctx,
struct gl_shader_program *shader_program,
struct gl_linked_shader *shader)
{
+ struct st_context *st = st_context(ctx);
struct gl_program *prog;
validate_ir_tree(shader->ir);
@@ -462,6 +463,11 @@ st_nir_get_mesa_program(struct gl_context *ctx,
return NULL;
}
+ struct st_common_program *st_comm_prog = (struct st_common_program *)prog;
+ nir_shader *nir = st_glsl_to_nir(st, prog, shader_program, shader->Stage);
+ st_comm_prog->tgsi.type = PIPE_SHADER_IR_NIR;
+ st_comm_prog->tgsi.ir.nir = nir;
+
return prog;
}
diff --git a/src/mesa/state_tracker/st_program.c
b/src/mesa/state_tracker/st_program.c
index 25a849bb18..e3649a8b7c 100644
--- a/src/mesa/state_tracker/st_program.c
+++ b/src/mesa/state_tracker/st_program.c
@@ -447,12 +447,6 @@ st_translate_vertex_program(struct st_context *st,
}
if (stvp->shader_program) {
- nir_shader *nir = st_glsl_to_nir(st, &stvp->Base, stvp->shader_program,
- MESA_SHADER_VERTEX);
-
- stvp->tgsi.type = PIPE_SHADER_IR_NIR;
- stvp->tgsi.ir.nir = nir;
-
struct gl_program *prog = stvp->shader_program->last_vert_prog;
if (prog) {
st_translate_stream_output_info2(prog->sh.LinkedTransformFeedback,
@@ -895,15 +889,9 @@ st_translate_fragment_program(struct st_context *st,
}
}
- if (stfp->shader_program) {
- nir_shader *nir = st_glsl_to_nir(st, &stfp->Base, stfp->shader_program,
- MESA_SHADER_FRAGMENT);
-
- stfp->tgsi.type = PIPE_SHADER_IR_NIR;
- stfp->tgsi.ir.nir = nir;
-
+ /* We have already compiler to NIR so just return */
+ if (stfp->shader_program)
return true;
- }
ureg = ureg_create_with_screen(PIPE_SHADER_FRAGMENT, st->pipe->screen);
if (ureg == NULL)
@@ -1681,15 +1669,9 @@ st_translate_tessctrl_program(struct st_context *st,
{
struct ureg_program *ureg;
- if (sttcp->shader_program) {
- nir_shader *nir = st_glsl_to_nir(st, &sttcp->Base, sttcp->shader_program,
- MESA_SHADER_TESS_EVAL);
-
- sttcp->tgsi.type = PIPE_SHADER_IR_NIR;
- sttcp->tgsi.ir.nir = nir;
-
+ /* We have already compiler to NIR so just return */
+ if (sttcp->shader_program)
return true;
- }
ureg = ureg_create_with_screen(PIPE_SHADER_TESS_CTRL, st->pipe->screen);
if (ureg == NULL)
@@ -1716,15 +1698,9 @@ st_translate_tesseval_program(struct st_context *st,
{
struct ureg_program *ureg;
- if (sttep->shader_program) {
- nir_shader *nir = st_glsl_to_nir(st, &sttep->Base, sttep->shader_program,
- MESA_SHADER_TESS_EVAL);
-
- sttep->tgsi.type = PIPE_SHADER_IR_NIR;
- sttep->tgsi.ir.nir = nir;
-
+ /* We have already compiler to NIR so just return */
+ if (sttep->shader_program)
return true;
- }
ureg = ureg_create_with_screen(PIPE_SHADER_TESS_EVAL, st->pipe->screen);
if (ureg == NULL)
@@ -1770,14 +1746,9 @@ st_translate_compute_program(struct st_context *st,
struct pipe_shader_state prog;
if (stcp->shader_program) {
- nir_shader *nir = st_glsl_to_nir(st, &stcp->Base, stcp->shader_program,
- MESA_SHADER_COMPUTE);
-
/* no compute variants: */
- st_finalize_nir(st, &stcp->Base, stcp->shader_program, nir);
-
- stcp->tgsi.ir_type = PIPE_SHADER_IR_NIR;
- stcp->tgsi.prog = nir;
+ st_finalize_nir(st, &stcp->Base, stcp->shader_program,
+ (struct nir_shader *) stcp->tgsi.prog);
return true;
}
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Mesa (master): st/glsl_to_nir: use nir_shader_gather_info()
Module: Mesa
Branch: master
Commit: 36be8c2fcf94f5d800aed6c3d39ef23b226fd0d5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=36be8c2fcf94f5d800aed6c3d39ef23b226fd0d5
Author: Timothy Arceri
Date: Wed Nov 1 20:32:12 2017 +1100
st/glsl_to_nir: use nir_shader_gather_info()
Use the NIR helper rather than the GLSL IR helper to get in/out
masks. This allows us to ignore varyings removed by NIR
optimisations.
Reviewed-by: Nicolai Hähnle
---
src/mesa/state_tracker/st_glsl_to_nir.cpp | 18 ++
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index d59e472584..7f4651a3cc 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -273,16 +273,12 @@ st_glsl_to_nir(struct st_context *st, struct gl_program
*prog,
*/
_mesa_associate_uniform_storage(st->ctx, shader_program, prog, true);
- st_set_prog_affected_state_flags(prog);
-
NIR_PASS_V(nir, nir_lower_io_to_temporaries,
nir_shader_get_entrypoint(nir),
true, true);
NIR_PASS_V(nir, nir_lower_global_vars_to_local);
NIR_PASS_V(nir, nir_split_var_copies);
NIR_PASS_V(nir, nir_lower_var_copies);
- NIR_PASS_V(nir, st_nir_lower_builtin);
- NIR_PASS_V(nir, nir_lower_atomics, shader_program);
/* fragment shaders may need : */
if (stage == MESA_SHADER_FRAGMENT) {
@@ -309,6 +305,16 @@ st_glsl_to_nir(struct st_context *st, struct gl_program
*prog,
}
}
+ NIR_PASS_V(nir, nir_lower_system_values);
+
+ nir_shader_gather_info(nir, nir_shader_get_entrypoint(nir));
+ prog->info = nir->info;
+
+ st_set_prog_affected_state_flags(prog);
+
+ NIR_PASS_V(nir, st_nir_lower_builtin);
+ NIR_PASS_V(nir, nir_lower_atomics, shader_program);
+
if (st->ctx->_Shader->Flags & GLSL_DUMP) {
_mesa_log("\n");
_mesa_log("NIR IR for linked %s program %d:\n",
@@ -394,8 +400,6 @@ st_finalize_nir(struct st_context *st, struct gl_program
*prog,
st_nir_assign_uniform_locations(prog, shader_program,
&nir->uniforms, &nir->num_uniforms);
- NIR_PASS_V(nir, nir_lower_system_values);
-
if (screen->get_param(screen, PIPE_CAP_NIR_SAMPLERS_AS_DEREF))
NIR_PASS_V(nir, nir_lower_samplers_as_deref, shader_program);
else
@@ -416,8 +420,6 @@ st_nir_get_mesa_program(struct gl_context *ctx,
prog->Parameters = _mesa_new_parameter_list();
- do_set_program_inouts(shader->ir, prog, shader->Stage);
-
_mesa_copy_linked_program_data(shader_program, shader);
_mesa_generate_parameters_list_for_uniforms(ctx, shader_program, shader,
prog->Parameters);
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Mesa (master): amd/addrlib: update to latest version
Module: Mesa Branch: master Commit: 7f33e94e43a647d71a9f930cf3180e5abb529edd URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f33e94e43a647d71a9f930cf3180e5abb529edd Author: Marek Olšák Date: Tue Nov 7 00:56:13 2017 +0100 amd/addrlib: update to latest version This uses C++11 initializer lists. I just overwrote all Mesa files with internal addrlib and discarded hunks that we should probably keep, but I might have missed something. The code depending on ADDR_AM_BUILD is removed. We can add it back next time if needed. Acked-by: Nicolai Hähnle --- src/amd/Makefile.sources |6 +- src/amd/addrlib/addrinterface.cpp |4 +- src/amd/addrlib/addrinterface.h | 83 +- src/amd/addrlib/amdgpu_asic_addr.h| 129 ++ src/amd/addrlib/core/addrcommon.h | 14 +- src/amd/addrlib/core/addrelemlib.cpp | 34 +- src/amd/addrlib/core/addrlib.cpp | 11 +- src/amd/addrlib/core/addrlib.h| 123 +- src/amd/addrlib/core/addrlib1.cpp | 73 +- src/amd/addrlib/core/addrlib2.cpp | 183 +-- src/amd/addrlib/core/addrlib2.h | 86 +- src/amd/addrlib/gfx9/coord.cpp| 16 +- src/amd/addrlib/gfx9/coord.h | 16 +- src/amd/addrlib/gfx9/gfx9addrlib.cpp | 1084 ++-- src/amd/addrlib/gfx9/gfx9addrlib.h| 86 +- src/amd/addrlib/gfx9/rbmap.cpp| 1388 - src/amd/addrlib/gfx9/rbmap.h | 142 --- src/amd/addrlib/inc/chip/gfx9/gfx9_gb_reg.h |8 + src/amd/addrlib/inc/chip/r800/si_gb_reg.h |8 + src/amd/addrlib/inc/lnx_common_defs.h | 129 -- src/amd/addrlib/meson.build |4 +- src/amd/addrlib/r800/ciaddrlib.cpp| 47 +- src/amd/addrlib/r800/ciaddrlib.h | 38 +- src/amd/addrlib/r800/egbaddrlib.cpp | 656 +- src/amd/addrlib/r800/siaddrlib.cpp| 22 +- src/amd/addrlib/r800/siaddrlib.h | 44 +- src/amd/common/ac_surface.c | 53 +- src/amd/common/amdgpu_id.h| 198 --- src/amd/vulkan/radv_device.c |1 - src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c |1 - src/amd/vulkan/winsys/amdgpu/radv_amdgpu_winsys.c |1 - src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c |1 - 32 files changed, 1354 insertions(+), 3335 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=7f33e94e43a647d71a9f930cf3180e5abb529edd ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): braodcom/vc5: Flush the job when it grows over 1GB.
Module: Mesa
Branch: master
Commit: 3bfcd31e9816813dad0ef7ec82b0fb62dd0271a0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3bfcd31e9816813dad0ef7ec82b0fb62dd0271a0
Author: Eric Anholt
Date: Tue Nov 7 11:05:16 2017 -0800
braodcom/vc5: Flush the job when it grows over 1GB.
Fixes GL_OUT_OF_MEMORY from streaming-texture-leak (and will hopefully
keep piglit from ooming on my no-swap platform, as well).
---
src/gallium/drivers/vc5/vc5_context.h | 3 +++
src/gallium/drivers/vc5/vc5_draw.c| 6 ++
src/gallium/drivers/vc5/vc5_job.c | 1 +
3 files changed, 10 insertions(+)
diff --git a/src/gallium/drivers/vc5/vc5_context.h
b/src/gallium/drivers/vc5/vc5_context.h
index 4917153fd4..73fb0d0bc5 100644
--- a/src/gallium/drivers/vc5/vc5_context.h
+++ b/src/gallium/drivers/vc5/vc5_context.h
@@ -205,6 +205,9 @@ struct vc5_job {
*/
struct set *bos;
+/** Sum of the sizes of the BOs referenced by the job. */
+uint32_t referenced_size;
+
struct set *write_prscs;
/* Size of the submit.bo_handles array. */
diff --git a/src/gallium/drivers/vc5/vc5_draw.c
b/src/gallium/drivers/vc5/vc5_draw.c
index 6f45b63405..f834207863 100644
--- a/src/gallium/drivers/vc5/vc5_draw.c
+++ b/src/gallium/drivers/vc5/vc5_draw.c
@@ -479,6 +479,12 @@ vc5_draw_vbo(struct pipe_context *pctx, const struct
pipe_draw_info *info)
vc5_job_add_bo(job, rsc->bo);
}
+if (job->referenced_size > 768 * 1024 * 1024) {
+perf_debug("Flushing job with %dkb to try to free up memory\n",
+job->referenced_size / 1024);
+vc5_flush(pctx);
+}
+
if (V3D_DEBUG & V3D_DEBUG_ALWAYS_FLUSH)
vc5_flush(pctx);
}
diff --git a/src/gallium/drivers/vc5/vc5_job.c
b/src/gallium/drivers/vc5/vc5_job.c
index 46c85e7edf..0141802b43 100644
--- a/src/gallium/drivers/vc5/vc5_job.c
+++ b/src/gallium/drivers/vc5/vc5_job.c
@@ -118,6 +118,7 @@ vc5_job_add_bo(struct vc5_job *job, struct vc5_bo *bo)
vc5_bo_reference(bo);
_mesa_set_add(job->bos, bo);
+job->referenced_size += bo->size;
uint32_t *bo_handles = (void *)(uintptr_t)job->submit.bo_handles;
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Mesa (master): broadcom/vc5: Fix scheduling for a non-SFU R4 write after a dead R4 write.
Module: Mesa
Branch: master
Commit: dfff9ce45ef9e2ba61814d7a75b896bbaf970557
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dfff9ce45ef9e2ba61814d7a75b896bbaf970557
Author: Eric Anholt
Date: Tue Nov 7 09:51:56 2017 -0800
broadcom/vc5: Fix scheduling for a non-SFU R4 write after a dead R4 write.
The v3d_qpu_writes_r*() were only checking for fixed-function accumulator
writes, not normal ALU writes to those regs.
Fixes fs-discard-exit-2 on simulation (but not HW).
---
src/broadcom/compiler/qpu_schedule.c | 8 +---
src/broadcom/qpu/qpu_instr.c | 30 --
2 files changed, 33 insertions(+), 5 deletions(-)
diff --git a/src/broadcom/compiler/qpu_schedule.c
b/src/broadcom/compiler/qpu_schedule.c
index dd221e027e..799da80590 100644
--- a/src/broadcom/compiler/qpu_schedule.c
+++ b/src/broadcom/compiler/qpu_schedule.c
@@ -201,13 +201,15 @@ process_waddr_deps(struct schedule_state *state, struct
schedule_node *n,
case V3D_QPU_WADDR_R0:
case V3D_QPU_WADDR_R1:
case V3D_QPU_WADDR_R2:
-case V3D_QPU_WADDR_R3:
-case V3D_QPU_WADDR_R4:
-case V3D_QPU_WADDR_R5:
add_write_dep(state,
&state->last_r[waddr - V3D_QPU_WADDR_R0],
n);
break;
+case V3D_QPU_WADDR_R3:
+case V3D_QPU_WADDR_R4:
+case V3D_QPU_WADDR_R5:
+/* Handled by v3d_qpu_writes_r*() checks below. */
+break;
case V3D_QPU_WADDR_VPM:
case V3D_QPU_WADDR_VPMU:
diff --git a/src/broadcom/qpu/qpu_instr.c b/src/broadcom/qpu/qpu_instr.c
index 7499170de3..7695e0b935 100644
--- a/src/broadcom/qpu/qpu_instr.c
+++ b/src/broadcom/qpu/qpu_instr.c
@@ -602,6 +602,18 @@ v3d_qpu_magic_waddr_is_tsy(enum v3d_qpu_waddr waddr)
bool
v3d_qpu_writes_r3(const struct v3d_qpu_instr *inst)
{
+if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
+if (inst->alu.add.magic_write &&
+inst->alu.add.waddr == V3D_QPU_WADDR_R3) {
+return true;
+}
+
+if (inst->alu.mul.magic_write &&
+inst->alu.mul.waddr == V3D_QPU_WADDR_R3) {
+return true;
+}
+}
+
return inst->sig.ldvary || inst->sig.ldvpm;
}
@@ -613,12 +625,14 @@ v3d_qpu_writes_r4(const struct v3d_qpu_instr *inst)
if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
if (inst->alu.add.magic_write &&
-v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr)) {
+(inst->alu.add.waddr == V3D_QPU_WADDR_R4 ||
+ v3d_qpu_magic_waddr_is_sfu(inst->alu.add.waddr))) {
return true;
}
if (inst->alu.mul.magic_write &&
-v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr)) {
+(inst->alu.mul.waddr == V3D_QPU_WADDR_R4 ||
+ v3d_qpu_magic_waddr_is_sfu(inst->alu.mul.waddr))) {
return true;
}
}
@@ -629,6 +643,18 @@ v3d_qpu_writes_r4(const struct v3d_qpu_instr *inst)
bool
v3d_qpu_writes_r5(const struct v3d_qpu_instr *inst)
{
+if (inst->type == V3D_QPU_INSTR_TYPE_ALU) {
+if (inst->alu.add.magic_write &&
+inst->alu.add.waddr == V3D_QPU_WADDR_R5) {
+return true;
+}
+
+if (inst->alu.mul.magic_write &&
+inst->alu.mul.waddr == V3D_QPU_WADDR_R5) {
+return true;
+}
+}
+
return inst->sig.ldvary || inst->sig.ldunif;
}
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Mesa (master): broadcom/vc5: Add occlusion query support.
Module: Mesa
Branch: master
Commit: 4f33344e7a6b988fbbc4a0802dacf5cab487e408
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f33344e7a6b988fbbc4a0802dacf5cab487e408
Author: Eric Anholt
Date: Mon Nov 6 15:41:40 2017 -0800
broadcom/vc5: Add occlusion query support.
Fixes all of piglit's OQ tests.
---
src/broadcom/cle/v3d_packet_v33.xml | 4 ++
src/gallium/drivers/vc5/vc5_context.c | 1 +
src/gallium/drivers/vc5/vc5_context.h | 11
src/gallium/drivers/vc5/vc5_draw.c| 3 ++
src/gallium/drivers/vc5/vc5_emit.c| 9
src/gallium/drivers/vc5/vc5_job.c | 20 ++--
src/gallium/drivers/vc5/vc5_query.c | 97 +--
7 files changed, 125 insertions(+), 20 deletions(-)
diff --git a/src/broadcom/cle/v3d_packet_v33.xml
b/src/broadcom/cle/v3d_packet_v33.xml
index 2b0665537e..165e489d4c 100644
--- a/src/broadcom/cle/v3d_packet_v33.xml
+++ b/src/broadcom/cle/v3d_packet_v33.xml
@@ -329,6 +329,10 @@
+
+
+
+
diff --git a/src/gallium/drivers/vc5/vc5_context.c
b/src/gallium/drivers/vc5/vc5_context.c
index f80020ab31..d27f41bb5f 100644
--- a/src/gallium/drivers/vc5/vc5_context.c
+++ b/src/gallium/drivers/vc5/vc5_context.c
@@ -162,6 +162,7 @@ vc5_context_create(struct pipe_screen *pscreen, void *priv,
unsigned flags)
V3D_DEBUG |= saved_shaderdb_flag;
vc5->sample_mask = (1 << VC5_MAX_SAMPLES) - 1;
+vc5->active_queries = true;
return &vc5->base;
diff --git a/src/gallium/drivers/vc5/vc5_context.h
b/src/gallium/drivers/vc5/vc5_context.h
index 298dfacf87..2fec7a77da 100644
--- a/src/gallium/drivers/vc5/vc5_context.h
+++ b/src/gallium/drivers/vc5/vc5_context.h
@@ -77,6 +77,7 @@ void vc5_job_add_bo(struct vc5_job *job, struct vc5_bo *bo);
#define VC5_DIRTY_COMPILED_FS (1 << 25)
#define VC5_DIRTY_FS_INPUTS (1 << 26)
#define VC5_DIRTY_STREAMOUT (1 << 27)
+#define VC5_DIRTY_OQ(1 << 28)
#define VC5_MAX_FS_INPUTS 64
@@ -262,6 +263,13 @@ struct vc5_job {
*/
bool needs_flush;
+/**
+ * Set if there is a nonzero address for OCCLUSION_QUERY_COUNTER. If
+ * so, we need to disable it and flush before ending the CL, to keep
+ * the next tile from starting with it enabled.
+ */
+bool oq_enabled;
+
bool uses_early_z;
/**
@@ -353,12 +361,15 @@ struct vc5_context {
*/
uint8_t blend_dst_alpha_one;
+bool active_queries;
+
struct pipe_poly_stipple stipple;
struct pipe_clip_state clip;
struct pipe_viewport_state viewport;
struct vc5_constbuf_stateobj constbuf[PIPE_SHADER_TYPES];
struct vc5_vertexbuf_stateobj vertexbuf;
struct vc5_streamout_stateobj streamout;
+struct vc5_bo *current_oq;
/** @} */
};
diff --git a/src/gallium/drivers/vc5/vc5_draw.c
b/src/gallium/drivers/vc5/vc5_draw.c
index edc5285915..8020e26802 100644
--- a/src/gallium/drivers/vc5/vc5_draw.c
+++ b/src/gallium/drivers/vc5/vc5_draw.c
@@ -93,6 +93,9 @@ vc5_start_draw(struct vc5_context *vc5)
/* There's definitely nothing in the VCD cache we want. */
cl_emit(&job->bcl, FLUSH_VCD_CACHE, bin);
+/* Disable any leftover OQ state from another job. */
+cl_emit(&job->bcl, OCCLUSION_QUERY_COUNTER, counter);
+
/* "Binning mode lists must have a Start Tile Binning item (6) after
* any prefix state data before the binning list proper starts."
*/
diff --git a/src/gallium/drivers/vc5/vc5_emit.c
b/src/gallium/drivers/vc5/vc5_emit.c
index de4737eeec..a4a1af7ddf 100644
--- a/src/gallium/drivers/vc5/vc5_emit.c
+++ b/src/gallium/drivers/vc5/vc5_emit.c
@@ -492,4 +492,13 @@ vc5_emit_state(struct pipe_context *pctx)
/* XXX? */
}
}
+
+if (vc5->dirty & VC5_DIRTY_OQ) {
+cl_emit(&job->bcl, OCCLUSION_QUERY_COUNTER, counter) {
+job->oq_enabled = vc5->active_queries &&
vc5->current_oq;
+if (job->oq_enabled) {
+counter.address = cl_address(vc5->current_oq,
0);
+}
+}
+}
}
diff --git a/src/gallium/drivers/vc5/vc5_job.c
b/src/gallium/drivers/vc5/vc5_job.c
index ed1a64be89..46c85e7edf 100644
--- a/src/gallium/drivers/vc5/vc5_job.c
+++ b/src/gallium/drivers/vc5/vc5_job.c
@@ -381,7 +381,17 @@ vc5_job_submit(struct vc5_context *vc5, struct vc5_job
*job)
vc5_emit_rcl(job);
if (cl_offset(&job->bcl) > 0) {
-vc5_cl_ensure_space_with_branch(&job->bcl, 2);
+vc5_cl_ensure_space_with_branch(&job->bcl,
+7 +
+
cl_packet_length(OCCLUSION_QUERY_COUNTER));
+
+if (job->oq_enabled) {
+/* Disable the OQ at the end
Mesa (master): broadcom/vc5: Fix pausing of transform feedback.
Module: Mesa Branch: master Commit: 80da60947b65b792edc95671147b00bfe53f9101 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=80da60947b65b792edc95671147b00bfe53f9101 Author: Eric Anholt Date: Tue Nov 7 10:13:04 2017 -0800 broadcom/vc5: Fix pausing of transform feedback. Gallium disables it by removing the streamout buffers, not by binding a program that doesn't have TF outputs. Fixes piglit "ext_transform_feedback2/counting with pause" --- src/gallium/drivers/vc5/vc5_draw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/vc5/vc5_draw.c b/src/gallium/drivers/vc5/vc5_draw.c index 55a2e49b98..6f45b63405 100644 --- a/src/gallium/drivers/vc5/vc5_draw.c +++ b/src/gallium/drivers/vc5/vc5_draw.c @@ -379,7 +379,7 @@ vc5_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info) * flag set. */ uint32_t prim_tf_enable = 0; -if (vc5->prog.bind_vs->num_tf_outputs) +if (vc5->streamout.num_targets) prim_tf_enable = (V3D_PRIM_POINTS_TF - V3D_PRIM_POINTS); vc5_tf_statistics_record(vc5, info, prim_tf_enable); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): broadcom/vc5: Do 16-bit unpacking of integer texture returns properly.
Module: Mesa
Branch: master
Commit: 50906e4583357920b49c78c25787403c5b4836d0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=50906e4583357920b49c78c25787403c5b4836d0
Author: Eric Anholt
Date: Tue Nov 7 10:34:42 2017 -0800
broadcom/vc5: Do 16-bit unpacking of integer texture returns properly.
We were doing f16 unpacks, which trashed "1" values. Fixes many piglit
texwrap GL_EXT_texture_integer cases.
---
src/broadcom/compiler/nir_to_vir.c | 37 +
1 file changed, 29 insertions(+), 8 deletions(-)
diff --git a/src/broadcom/compiler/nir_to_vir.c
b/src/broadcom/compiler/nir_to_vir.c
index 43ee84d5bb..4b176960b0 100644
--- a/src/broadcom/compiler/nir_to_vir.c
+++ b/src/broadcom/compiler/nir_to_vir.c
@@ -477,14 +477,35 @@ ntq_emit_tex(struct v3d_compile *c, nir_tex_instr *instr)
STATIC_ASSERT(PIPE_SWIZZLE_X == 0);
chan = return_values[i / 2];
-enum v3d_qpu_input_unpack unpack;
-if (i & 1)
-unpack = V3D_QPU_UNPACK_H;
-else
-unpack = V3D_QPU_UNPACK_L;
-
-chan = vir_FMOV(c, chan);
-vir_set_unpack(c->defs[chan.index], 0, unpack);
+if (nir_alu_type_get_base_type(instr->dest_type) ==
+nir_type_float) {
+enum v3d_qpu_input_unpack unpack;
+if (i & 1)
+unpack = V3D_QPU_UNPACK_H;
+else
+unpack = V3D_QPU_UNPACK_L;
+
+chan = vir_FMOV(c, chan);
+vir_set_unpack(c->defs[chan.index], 0, unpack);
+} else {
+/* If we're unpacking the low field, shift it
+ * up to the top first.
+ */
+if ((i & 1) == 0) {
+chan = vir_SHL(c, chan,
+ vir_uniform_ui(c, 16));
+}
+
+/* Do proper sign extension to a 32-bit int. */
+if
(nir_alu_type_get_base_type(instr->dest_type) ==
+nir_type_int) {
+chan = vir_ASR(c, chan,
+ vir_uniform_ui(c, 16));
+} else {
+chan = vir_SHR(c, chan,
+ vir_uniform_ui(c, 16));
+}
+}
} else {
chan = vir_MOV(c, return_values[i]);
}
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Mesa (master): broadcom/vc5: Add support for GL_RASTERIZER_DISCARD
Module: Mesa
Branch: master
Commit: 25d199f67dce2698aa8a9c3a4010d90a44d3a894
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=25d199f67dce2698aa8a9c3a4010d90a44d3a894
Author: Eric Anholt
Date: Tue Nov 7 10:08:59 2017 -0800
broadcom/vc5: Add support for GL_RASTERIZER_DISCARD
Fixes piglit discard-drawarrays.
---
src/gallium/drivers/vc5/vc5_emit.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/vc5/vc5_emit.c
b/src/gallium/drivers/vc5/vc5_emit.c
index a4a1af7ddf..b84ddd6647 100644
--- a/src/gallium/drivers/vc5/vc5_emit.c
+++ b/src/gallium/drivers/vc5/vc5_emit.c
@@ -262,9 +262,11 @@ vc5_emit_state(struct pipe_context *pctx)
VC5_DIRTY_COMPILED_FS)) {
cl_emit(&job->bcl, CONFIGURATION_BITS, config) {
config.enable_forward_facing_primitive =
+!vc5->rasterizer->base.rasterizer_discard &&
!(vc5->rasterizer->base.cull_face &
PIPE_FACE_FRONT);
config.enable_reverse_facing_primitive =
+!vc5->rasterizer->base.rasterizer_discard &&
!(vc5->rasterizer->base.cull_face &
PIPE_FACE_BACK);
/* This seems backwards, but it's what gets the
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Mesa (master): broadcom/vc5: Add partial transform feedback query support.
Module: Mesa
Branch: master
Commit: 9ccb6621be2f40a74f75efe30d83b7813e3c3f56
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ccb6621be2f40a74f75efe30d83b7813e3c3f56
Author: Eric Anholt
Date: Mon Nov 6 16:59:05 2017 -0800
broadcom/vc5: Add partial transform feedback query support.
We have to compute the queries in software, so we're counting the
primitives by hand. We still need to make sure to not increment the
PRIMITIVES_EMITTED if we overflowed, but leave that for later.
---
src/gallium/drivers/vc5/vc5_context.h | 3 ++
src/gallium/drivers/vc5/vc5_draw.c| 21 +
src/gallium/drivers/vc5/vc5_query.c | 57 ---
3 files changed, 64 insertions(+), 17 deletions(-)
diff --git a/src/gallium/drivers/vc5/vc5_context.h
b/src/gallium/drivers/vc5/vc5_context.h
index 2fec7a77da..4917153fd4 100644
--- a/src/gallium/drivers/vc5/vc5_context.h
+++ b/src/gallium/drivers/vc5/vc5_context.h
@@ -363,6 +363,9 @@ struct vc5_context {
bool active_queries;
+uint32_t tf_prims_generated;
+uint32_t prims_generated;
+
struct pipe_poly_stipple stipple;
struct pipe_clip_state clip;
struct pipe_viewport_state viewport;
diff --git a/src/gallium/drivers/vc5/vc5_draw.c
b/src/gallium/drivers/vc5/vc5_draw.c
index 8020e26802..55a2e49b98 100644
--- a/src/gallium/drivers/vc5/vc5_draw.c
+++ b/src/gallium/drivers/vc5/vc5_draw.c
@@ -270,6 +270,25 @@ vc5_emit_gl_shader_state(struct vc5_context *vc5,
job->shader_rec_count++;
}
+/**
+ * Computes the various transform feedback statistics, since they can't be
+ * recorded by CL packets.
+ */
+static void
+vc5_tf_statistics_record(struct vc5_context *vc5,
+ const struct pipe_draw_info *info,
+ bool prim_tf)
+{
+uint32_t prims = u_prims_for_vertices(info->mode, info->count);
+
+vc5->prims_generated += prims;
+
+if (prim_tf) {
+/* XXX: Only count if we didn't overflow. */
+vc5->tf_prims_generated += prims;
+}
+}
+
static void
vc5_draw_vbo(struct pipe_context *pctx, const struct pipe_draw_info *info)
{
@@ -363,6 +382,8 @@ vc5_draw_vbo(struct pipe_context *pctx, const struct
pipe_draw_info *info)
if (vc5->prog.bind_vs->num_tf_outputs)
prim_tf_enable = (V3D_PRIM_POINTS_TF - V3D_PRIM_POINTS);
+vc5_tf_statistics_record(vc5, info, prim_tf_enable);
+
/* Note that the primitive type fields match with OpenGL/gallium
* definitions, up to but not including QUADS.
*/
diff --git a/src/gallium/drivers/vc5/vc5_query.c
b/src/gallium/drivers/vc5/vc5_query.c
index a412b38408..5ec9be2e35 100644
--- a/src/gallium/drivers/vc5/vc5_query.c
+++ b/src/gallium/drivers/vc5/vc5_query.c
@@ -24,12 +24,13 @@
/**
* Gallium query object support.
*
- * So far we just support occlusion queries. The HW has native support for
- * them, with the query result being loaded and stored by the TLB unit.
+ * The HW has native support for occlusion queries, with the query result
+ * being loaded and stored by the TLB unit. From a SW perspective, we have to
+ * be careful to make sure that the jobs that need to be tracking queries are
+ * bracketed by the start and end of counting, even across FBO transitions.
*
- * From a SW perspective, we have to be careful to make sure that the jobs
- * that need to be tracking queries are bracketed by the start and end of
- * counting, even across FBO transitions.
+ * For the transform feedback PRIMITIVES_GENERATED/WRITTEN queries, we have to
+ * do the calculations in software at draw time.
*/
#include "vc5_context.h"
@@ -39,6 +40,8 @@ struct vc5_query
{
enum pipe_query_type type;
struct vc5_bo *bo;
+
+uint32_t start, end;
};
static struct pipe_query *
@@ -46,10 +49,6 @@ vc5_create_query(struct pipe_context *pctx, unsigned
query_type, unsigned index)
{
struct vc5_query *q = calloc(1, sizeof(*q));
-assert(query_type == PIPE_QUERY_OCCLUSION_COUNTER ||
- query_type == PIPE_QUERY_OCCLUSION_PREDICATE ||
- query_type == PIPE_QUERY_OCCLUSION_PREDICATE_CONSERVATIVE);
-
q->type = query_type;
/* Note that struct pipe_query isn't actually defined anywhere. */
@@ -71,13 +70,22 @@ vc5_begin_query(struct pipe_context *pctx, struct
pipe_query *query)
struct vc5_context *vc5 = vc5_context(pctx);
struct vc5_query *q = (struct vc5_query *)query;
-q->bo = vc5_bo_alloc(vc5->screen, 4096, "query");
-
-uint32_t *map = vc5_bo_map(q->bo);
-*map = 0;
+switch (q->type) {
+case PIPE_QUERY_PRIMITIVES_GENERATED:
+q->start = vc5->prims_generated;
+break;
+case PIPE_QUERY_PRIMITIVES_EMITTED:
+q->start = vc5->tf_prims_generated;
+break;
+default:
+q->bo = vc5_b
Mesa (master): 51 new commits
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d002950e5491f971cbaa77ac80a698e5d746295a Author: Jason Ekstrand Date: Thu Nov 2 15:59:58 2017 -0700 intel/fs/nir: Return Q types from brw_reg_type_for_bit_size Reviewed-by: Samuel Iglesias Gonsálvez URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dee58ecd2e3b23d1a3d2cdffb99d3dd314421b39 Author: Jason Ekstrand Date: Thu Nov 2 18:32:39 2017 -0700 intel/fs/nir: Use Q immediates for load_const on gen8+ Reviewed-by: Samuel Iglesias Gonsálvez URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9bb34892bf99a6f2285f792519f51cefe5c219ee Author: Jason Ekstrand Date: Thu Nov 2 18:30:04 2017 -0700 intel/fs/nir: Setup immediates based on type in i2b and f2b Reviewed-by: Samuel Iglesias Gonsálvez URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1cb210f4bc412a9c1fef12e05ea9d9fe8995f4d5 Author: Jason Ekstrand Date: Thu Nov 2 18:29:03 2017 -0700 intel/reg: Add helpers for 64-bit integer immediates Reviewed-by: Samuel Iglesias Gonsálvez URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=df81b81fb91f45e6da0c504ee672d45829c41d06 Author: Jason Ekstrand Date: Wed Aug 23 17:43:36 2017 -0700 compiler/nir_types: Handle vectors in glsl_get_array_element Most of NIR doesn't allow doing array indexing on a vector (though it does on a matrix). However, nir_lower_io handles it just fine and this behavior is needed for shared variables in Vulkan. This commit makes glsl_get_array_element do something sensible for vector types and makes nir_validate happy with them. Reviewed-by: Lionel Landwerlin Reviewed-by: Iago Toral Quiroga URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad5809555bc215f468424215e8dddc7083bf Author: Jason Ekstrand Date: Fri Sep 1 16:40:28 2017 -0700 nir: Validate base types on array dereferences We were already validating that the parent type goes along with the child type but we weren't actually validating that the parent type is reasonable. This fixes that. Acked-by: Lionel Landwerlin Reviewed-by: Iago Toral Quiroga URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ab9220edd69fcb7016e15d4d96186eac524b45a4 Author: Jason Ekstrand Date: Tue Aug 22 18:57:56 2017 -0700 nir,intel/compiler: Use a fixed subgroup size The GL_ARB_shader_ballot spec says that gl_SubGroupSizeARB is declared as a uniform. This means that it cannot change across an invocation such as a draw call or a compute dispatch. For compute shaders, we're ok because we only ever use one dispatch size. For fragment, however, the hardware dynamically chooses between SIMD8 and SIMD16 which violates the spec. Instead, let's just pick a subgroup size based on the shader stage. The fixed size we choose for compute shaders is a bit higher than strictly needed but there's no real harm in that. The advantage is that, if they do anything interesting with the value, NIR will see it as an immediate and can optimize better. Acked-by: Lionel Landwerlin Reviewed-by: Iago Toral Quiroga URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a026458020e947cc5d864cfb5b19660836b2d613 Author: Jason Ekstrand Date: Tue Aug 22 18:44:51 2017 -0700 nir/lower_subgroups: Lower ballot intrinsics to the specified bit size Ballot intrinsics return a bitfield of subgroups. In GLSL and some SPIR-V extensions, they return a uint64_t. In SPV_KHR_shader_ballot, they return a uvec4. Also, some back-ends would rather pass around 32-bit values because it's easier than messing with 64-bit all the time. To solve this mess, we make nir_lower_subgroups take a new parameter called ballot_bit_size and it lowers whichever thing it gets in from the source language (uint64_t or uvec4) to a scalar with the specified number of bits. This replaces a chunk of the old lowering code. Reviewed-by: Lionel Landwerlin Reviewed-by: Iago Toral Quiroga URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c2bf020fd649957597d074cf2390d6de029ddd0 Author: Jason Ekstrand Date: Tue Oct 31 14:42:33 2017 -0700 nir/builder: Add a nir_imm_intN_t helper This lets you easily build integer immediates of arbitrary bit size. Reviewed-by: Iago Toral Quiroga Reviewed-by: Lionel Landwerlin URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b35faba426acc111741aa69752cb87185e548aa Author: Jason Ekstrand Date: Tue Aug 22 14:09:37 2017 -0700 nir/lower_system_values: Lower SUBGROUP_*_MASK based on type The SUBGROUP_*_MASK system values are uint64_t when coming in from GLSL but uvec4 when coming in from SPIR-V. Lowering based on type allows us to nicely handle both. Reviewed-by: Lionel Landwerlin Reviewed-by: Iago Toral Quiroga URL: h
Mesa (master): 22 new commits
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd24f4890f7f4b4a2c2c6e92163f655904b8709a Author: Eric Anholt Date: Thu Nov 2 19:04:12 2017 -0700 broadcom/vc5: Skip emitting textures that aren't used. Fixes crashes when ARB_fp uses texture[1] but not 0, as in piglit's fp-fragment-position. URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d5e62dcfaeb2382f42116612e24f7240f1e521d Author: Eric Anholt Date: Thu Nov 2 18:49:58 2017 -0700 broadcom/vc5: Add missing SRGBA8 ETC2 support. Fixes piglit oes_compressed_etc2_texture-miptree srgb8-alpha8. URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6079f7c3c3ce30277ce671b9679186f243a5e570 Author: Eric Anholt Date: Thu Nov 2 18:45:07 2017 -0700 broadcom/vc5: Disable early Z test when the FS writes Z. Fixes piglit early-z. URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=eeb9e80272cb0dd795c4197962f2af3398747dda Author: Eric Anholt Date: Thu Nov 2 12:49:46 2017 -0700 broadcom/vc5: Shift the min/max lod fields by the BASE_LEVEL. The lod clamping is what limits you between base and last level, and the base level field is just there to help decide where the min/mag change happens. Fixes tex-miplevel-selection GL2:texture() URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=521e1d0275e7b237ee676e0426be1b734f270944 Author: Eric Anholt Date: Thu Nov 2 12:24:17 2017 -0700 broadcom/vc5: Add support for anisotropic filtering. URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a266f78741bfdf6802b49df77d4611d6084408e9 Author: Eric Anholt Date: Thu Nov 2 12:19:10 2017 -0700 broadcom/vc5: Fix mipmap filtering enums. The ordering of the values was even less obvious than I thought, with both the mip filter and the min filter being in different bits depending on whether the mip filter is none. Fixes piglit fs-textureLod-miplevels.shader_test URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=73ec70bf13a939e687ddf9c2a7e08962042a09eb Author: Eric Anholt Date: Thu Nov 2 11:47:30 2017 -0700 broadcom/vc5: Fix height padding of small UIF slices. The HW doesn't pad the slice's height to make a full 4x4 group of UIF blocks. We just need to pad to columns, and the start of the next column appears in the bottom of the previous column's last block. Fixes piglit fs-textureOffset-2D. URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e23c6991bed6597c777b145a3f24b79e1d28be56 Author: Eric Anholt Date: Wed Nov 1 17:55:52 2017 -0700 broadcom/vc5: Print the actual offsets in HW for our resource layout debug. The alignment of level 0 is non-obvious, so it's hard to turn a faulting address into a slice without this. URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=426c352336182557f6c845481a38638182faacdf Author: Eric Anholt Date: Wed Nov 1 17:22:17 2017 -0700 broadcom/vc5: Set the available VS outputs to match the FS inputs. Fixes piglit glsl-es-3.00/minimum-maximums.txt. URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f1797928fd7333c193b26d11e25b9b58d8116ec8 Author: Eric Anholt Date: Wed Nov 1 15:29:58 2017 -0700 broadcom/vc5: Set the max texture LOD bias. The field is signed 8.8, so the usual 16.0f fits. Fixes piglit gl-2.1-minmax. URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=47bd9dac197ab47313cfb48a60f7a9e3a2ac3877 Author: Eric Anholt Date: Wed Nov 1 15:28:04 2017 -0700 broadcom/vc5: Fix translation of stencil ops. They aren't quite in the same order as the gallium defines. Fixes piglit gl-2.0-two-sided-stencil. URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3be820477fbec5e771d6a35148d08a7507533cfd Author: Eric Anholt Date: Wed Nov 1 15:18:34 2017 -0700 broadcom/vc5: Move stencil state packing to the CSO. Only the stencil ref comes in as dynamic state at emit time. URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3da39f22975703ad3688bfb4b658d219147ce9a1 Author: Eric Anholt Date: Wed Nov 1 14:39:47 2017 -0700 broadcom/vc5: Introduce a helper for pre-packing our V3DXX structs. This is so much more pleasant to write than the manual V3D33_whatever_pack() calls, and will be useful for when we start doing actual per-V3D compiles. URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=078b163a9c581e5b0e7bcc7436f0bf569cbc020d Author: Eric Anholt Date: Wed Nov 1 15:16:59 2017 -0700 broadcom/vc5: Add a cl_emit() variant for merging with a pre-packed struct. Cleans up the hand-written code, at the cost of another ugly macro. URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=735b844b1b32a440738b1a6096ea3aa4df6b52a7 Author: Eric Anholt Date: Wed Nov 1 14:04:45 2017 -0700 broadcom/vc5: Skip emitting depth offset while disabled. The enable flag is also in the
Mesa (master): anv: Remove unused variable 'gen'
Module: Mesa
Branch: master
Commit: 012b54c6b108542787ac6ca0790c78744311f576
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=012b54c6b108542787ac6ca0790c78744311f576
Author: Chad Versace
Date: Thu Nov 2 15:34:04 2017 -0700
anv: Remove unused variable 'gen'
In anv_physical_device_get_format_properties().
Reviewed-by: Jason Ekstrand
Reviewed-by: Lionel Landwerlin
---
src/intel/vulkan/anv_formats.c | 4
1 file changed, 4 deletions(-)
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index cece065398..cfff0991be 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -541,10 +541,6 @@ anv_physical_device_get_format_properties(struct
anv_physical_device *physical_d
VkFormat vk_format,
VkFormatProperties *out_properties)
{
- int gen = physical_device->info.gen * 10;
- if (physical_device->info.is_haswell)
- gen += 5;
-
const struct anv_format *format = anv_get_format(vk_format);
VkFormatFeatureFlags linear = 0, tiled = 0, buffer = 0;
if (format == NULL) {
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Mesa (master): anv: Suffix anv-private 'VK' tokens with 'ANV'
Module: Mesa
Branch: master
Commit: 3ea37d0a2aa33a37b292b82e83526361f71ffd7e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ea37d0a2aa33a37b292b82e83526361f71ffd7e
Author: Chad Versace
Date: Thu Nov 2 16:05:45 2017 -0700
anv: Suffix anv-private 'VK' tokens with 'ANV'
I saw VK_IMAGE_ASPECT_ANY_COLOR_BIT while hacking anv_formats.c and got
confused. "Huh? What extension added that?". No extension defines it;
anv_private.h defines it.
To remove confusion, rename the anv-private VK tokens as if they were
extension tokens with the ANV vendor suffix.
I found only two such tokens:
VK_IMAGE_ASPECT_ANY_COLOR_BIT
VK_IMAGE_ASPECT_PLANES_BITS
Reviewed-by: Jason Ekstrand
Reviewed-by: Lionel Landwerlin
---
src/intel/vulkan/anv_blorp.c | 6 +++---
src/intel/vulkan/anv_formats.c | 2 +-
src/intel/vulkan/anv_image.c | 18 +-
src/intel/vulkan/anv_private.h | 12 ++--
src/intel/vulkan/genX_cmd_buffer.c | 24
5 files changed, 31 insertions(+), 31 deletions(-)
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 70e1b2b022..6deb3509cc 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -777,7 +777,7 @@ void anv_CmdClearColorImage(
if (pRanges[r].aspectMask == 0)
continue;
- assert(pRanges[r].aspectMask & VK_IMAGE_ASPECT_ANY_COLOR_BIT);
+ assert(pRanges[r].aspectMask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
struct blorp_surf surf;
get_blorp_surf_for_anv_image(image, pRanges[r].aspectMask,
@@ -1068,7 +1068,7 @@ void anv_CmdClearAttachments(
BLORP_BATCH_NO_EMIT_DEPTH_STENCIL);
for (uint32_t a = 0; a < attachmentCount; ++a) {
- if (pAttachments[a].aspectMask & VK_IMAGE_ASPECT_ANY_COLOR_BIT) {
+ if (pAttachments[a].aspectMask & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) {
assert(pAttachments[a].aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
clear_color_attachment(cmd_buffer, &batch,
&pAttachments[a],
@@ -1668,7 +1668,7 @@ anv_ccs_resolve(struct anv_cmd_buffer * const cmd_buffer,
/* The resolved subresource range must have a CCS buffer. */
assert(level < anv_image_aux_levels(image, aspect));
assert(layer_count <= anv_image_aux_layers(image, aspect, level));
- assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT && image->samples ==
1);
+ assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV && image->samples
== 1);
/* Create a binding table for this surface state. */
uint32_t binding_table;
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index cfff0991be..b8c9cacb42 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -430,7 +430,7 @@ anv_get_format_plane(const struct gen_device_info *devinfo,
VkFormat vk_format,
return plane_format;
}
- assert((aspect & ~VK_IMAGE_ASPECT_ANY_COLOR_BIT) == 0);
+ assert((aspect & ~VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) == 0);
const struct isl_format_layout *isl_layout =
isl_format_get_layout(plane_format.isl_format);
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index cd96bfd0d6..73777d86a4 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -209,7 +209,7 @@ add_fast_clear_state_buffer(struct anv_image *image,
{
assert(image && device);
assert(image->planes[plane].aux_surface.isl.size > 0 &&
- image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT);
+ image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
/* The offset to the buffer of clear values must be dword-aligned for GPU
* memcpy operations. It is located immediately after the auxiliary surface.
@@ -394,7 +394,7 @@ make_surface(const struct anv_device *dev,
add_surface(image, &image->planes[plane].aux_surface, plane);
image->planes[plane].aux_usage = ISL_AUX_USAGE_HIZ;
}
- } else if ((aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT) && vk_info->samples ==
1) {
+ } else if ((aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) && vk_info->samples
== 1) {
/* TODO: Disallow compression with :
*
* 1) non multiplanar images (We appear to hit a sampler bug with
@@ -451,7 +451,7 @@ make_surface(const struct anv_device *dev,
}
}
}
- } else if ((aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT) && vk_info->samples >
1) {
+ } else if ((aspect & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV) && vk_info->samples
> 1) {
assert(!(vk_info->usage & VK_IMAGE_USAGE_STORAGE_BIT));
assert(image->planes[plane].aux_surface.isl.size == 0);
ok = isl_surf_get_mcs_surf(&dev->isl_dev,
@@ -751,7 +751,7 @@ anv_layout_to_aux_usage(const struct gen_device_info *
const devinfo,
/* The following switch currently only handles depth stencil aspects.
* TODO: Handle the color aspect.
*/
- if (image->aspects & VK_I
Mesa (master): radeonsi/gfx9: don't set gs_table_depth
Module: Mesa
Branch: master
Commit: c29f5fe41cea2d31188c363f039f0d55d0fff79b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c29f5fe41cea2d31188c363f039f0d55d0fff79b
Author: Marek Olšák
Date: Tue Nov 7 03:29:36 2017 +0100
radeonsi/gfx9: don't set gs_table_depth
Reviewed-by: Nicolai Hähnle
---
src/gallium/drivers/radeonsi/si_pipe.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index d39e412de9..649a72e0fc 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -866,6 +866,10 @@ static void si_destroy_screen(struct pipe_screen* pscreen)
static bool si_init_gs_info(struct si_screen *sscreen)
{
+ /* gs_table_depth is not used by GFX9 */
+ if (sscreen->b.chip_class >= GFX9)
+ return true;
+
switch (sscreen->b.family) {
case CHIP_OLAND:
case CHIP_HAINAN:
@@ -887,8 +891,6 @@ static bool si_init_gs_info(struct si_screen *sscreen)
case CHIP_POLARIS10:
case CHIP_POLARIS11:
case CHIP_POLARIS12:
- case CHIP_VEGA10:
- case CHIP_RAVEN:
sscreen->gs_table_depth = 32;
return true;
default:
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Mesa (master): radeonsi: use ac_create_target_machine
Module: Mesa
Branch: master
Commit: cde664ab81dba8c7f0fa15ef6e28aac463719ac5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cde664ab81dba8c7f0fa15ef6e28aac463719ac5
Author: Marek Olšák
Date: Tue Nov 7 03:50:19 2017 +0100
radeonsi: use ac_create_target_machine
Reviewed-by: Nicolai Hähnle
---
src/amd/common/ac_llvm_util.c | 7 +--
src/amd/common/ac_llvm_util.h | 3 +++
src/gallium/drivers/radeonsi/si_pipe.c | 22 +++---
3 files changed, 15 insertions(+), 17 deletions(-)
diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c
index fb2bc11874..429904c040 100644
--- a/src/amd/common/ac_llvm_util.c
+++ b/src/amd/common/ac_llvm_util.c
@@ -128,8 +128,11 @@ LLVMTargetMachineRef ac_create_target_machine(enum
radeon_family family, enum ac
LLVMTargetRef target = ac_get_llvm_target(triple);
snprintf(features, sizeof(features),
-"+DumpCode,+vgpr-spilling,-fp32-denormals%s",
-tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "");
+
"+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s%s",
+tm_options & AC_TM_SISCHED ? ",+si-scheduler" : "",
+tm_options & AC_TM_FORCE_ENABLE_XNACK ? ",+xnack" : "",
+tm_options & AC_TM_FORCE_DISABLE_XNACK ? ",-xnack" : "",
+tm_options & AC_TM_PROMOTE_ALLOCA_TO_SCRATCH ?
",-promote-alloca" : "");
LLVMTargetMachineRef tm = LLVMCreateTargetMachine(
target,
diff --git a/src/amd/common/ac_llvm_util.h b/src/amd/common/ac_llvm_util.h
index d4b3915ffa..7c8b6b0a13 100644
--- a/src/amd/common/ac_llvm_util.h
+++ b/src/amd/common/ac_llvm_util.h
@@ -57,6 +57,9 @@ enum ac_func_attr {
enum ac_target_machine_options {
AC_TM_SUPPORTS_SPILL = (1 << 0),
AC_TM_SISCHED = (1 << 1),
+ AC_TM_FORCE_ENABLE_XNACK = (1 << 2),
+ AC_TM_FORCE_DISABLE_XNACK = (1 << 3),
+ AC_TM_PROMOTE_ALLOCA_TO_SCRATCH = (1 << 4),
};
const char *ac_get_llvm_processor_name(enum radeon_family family);
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index e96380ce40..1ca5ca38df 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -145,21 +145,13 @@ static void si_emit_string_marker(struct pipe_context
*ctx,
static LLVMTargetMachineRef
si_create_llvm_target_machine(struct si_screen *sscreen)
{
- const char *triple = "amdgcn--";
- char features[256];
-
- snprintf(features, sizeof(features),
-
"+DumpCode,+vgpr-spilling,-fp32-denormals,+fp64-denormals%s%s%s",
-sscreen->b.chip_class >= GFX9 ? ",+xnack" : ",-xnack",
-sscreen->llvm_has_working_vgpr_indexing ? "" :
",-promote-alloca",
-sscreen->b.debug_flags & DBG(SI_SCHED) ? ",+si-scheduler" :
"");
-
- return LLVMCreateTargetMachine(ac_get_llvm_target(triple), triple,
-
ac_get_llvm_processor_name(sscreen->b.family),
- features,
- LLVMCodeGenLevelDefault,
- LLVMRelocDefault,
- LLVMCodeModelDefault);
+ enum ac_target_machine_options tm_options =
+ (sscreen->b.debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
+ (sscreen->b.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
+ (sscreen->b.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
+ (!sscreen->llvm_has_working_vgpr_indexing ?
AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0);
+
+ return ac_create_target_machine(sscreen->b.family, tm_options);
}
static void si_set_log_context(struct pipe_context *ctx,
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Mesa (master): radeonsi: add si_screen::has_ls_vgpr_init_bug
Module: Mesa
Branch: master
Commit: 33000e7c437510bac44a42102d74554aa1259f18
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=33000e7c437510bac44a42102d74554aa1259f18
Author: Marek Olšák
Date: Tue Nov 7 03:52:34 2017 +0100
radeonsi: add si_screen::has_ls_vgpr_init_bug
Reviewed-by: Nicolai Hähnle
---
src/gallium/drivers/radeonsi/si_pipe.c | 2 ++
src/gallium/drivers/radeonsi/si_pipe.h | 1 +
src/gallium/drivers/radeonsi/si_shader.c | 3 +--
src/gallium/drivers/radeonsi/si_state_draw.c | 2 +-
4 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index 1ca5ca38df..391997db84 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1074,6 +1074,8 @@ struct pipe_screen *radeonsi_screen_create(struct
radeon_winsys *ws,
sscreen->b.family <=
CHIP_POLARIS12) ||
sscreen->b.family == CHIP_VEGA10 ||
sscreen->b.family == CHIP_RAVEN;
+ sscreen->has_ls_vgpr_init_bug = sscreen->b.family == CHIP_VEGA10 ||
+ sscreen->b.family == CHIP_RAVEN;
if (sscreen->b.debug_flags & DBG(DPBB)) {
sscreen->dpbb_allowed = true;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index ab82064571..6be51bb3ec 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -97,6 +97,7 @@ struct si_screen {
boolcommutative_blend_add;
boolclear_db_cache_before_clear;
boolhas_msaa_sample_loc_bug;
+ boolhas_ls_vgpr_init_bug;
booldpbb_allowed;
booldfsm_allowed;
boolllvm_has_working_vgpr_indexing;
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 6bc08dd389..c95f8d7ed7 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -6882,8 +6882,7 @@ static void si_build_vs_prolog_function(struct
si_shader_context *ctx,
si_init_exec_from_input(ctx, 3, 0);
if (key->vs_prolog.as_ls &&
- (ctx->screen->b.family == CHIP_VEGA10 ||
-ctx->screen->b.family == CHIP_RAVEN)) {
+ ctx->screen->has_ls_vgpr_init_bug) {
/* If there are no HS threads, SPI loads the LS VGPRs
* starting at VGPR 0. Shift them back to where they
* belong.
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 994ed58a1b..53f33ca0e1 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1282,7 +1282,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
}
if (sctx->tes_shader.cso &&
- (sctx->b.family == CHIP_VEGA10 || sctx->b.family == CHIP_RAVEN)) {
+ sctx->screen->has_ls_vgpr_init_bug) {
/* Determine whether the LS VGPR fix should be applied.
*
* It is only required when num input CPs > num output CPs,
___
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Mesa (master): radeonsi: use ac_get_llvm_processor_name
Module: Mesa
Branch: master
Commit: 81f81fdb54001903078af7df6c9e8f2d4ff46294
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=81f81fdb54001903078af7df6c9e8f2d4ff46294
Author: Marek Olšák
Date: Tue Nov 7 03:43:38 2017 +0100
radeonsi: use ac_get_llvm_processor_name
Reviewed-by: Nicolai Hähnle
---
src/amd/common/ac_llvm_util.c | 2 +-
src/amd/common/ac_llvm_util.h | 2 ++
src/gallium/drivers/radeon/r600_pipe_common.c | 37 ++-
src/gallium/drivers/radeon/r600_pipe_common.h | 1 -
src/gallium/drivers/radeonsi/si_pipe.c| 4 +--
5 files changed, 7 insertions(+), 39 deletions(-)
diff --git a/src/amd/common/ac_llvm_util.c b/src/amd/common/ac_llvm_util.c
index 675926ea67..fb2bc11874 100644
--- a/src/amd/common/ac_llvm_util.c
+++ b/src/amd/common/ac_llvm_util.c
@@ -74,7 +74,7 @@ LLVMTargetRef ac_get_llvm_target(const char *triple)
return target;
}
-static const char *ac_get_llvm_processor_name(enum radeon_family family)
+const char *ac_get_llvm_processor_name(enum radeon_family family)
{
switch (family) {
case CHIP_TAHITI:
diff --git a/src/amd/common/ac_llvm_util.h b/src/amd/common/ac_llvm_util.h
index cc4fe3bd63..d4b3915ffa 100644
--- a/src/amd/common/ac_llvm_util.h
+++ b/src/amd/common/ac_llvm_util.h
@@ -58,6 +58,8 @@ enum ac_target_machine_options {
AC_TM_SUPPORTS_SPILL = (1 << 0),
AC_TM_SISCHED = (1 << 1),
};
+
+const char *ac_get_llvm_processor_name(enum radeon_family family);
LLVMTargetMachineRef ac_create_target_machine(enum radeon_family family, enum
ac_target_machine_options tm_options);
LLVMTargetRef ac_get_llvm_target(const char *triple);
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 478f626b29..aa72187c57 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -33,6 +33,7 @@
#include "vl/vl_decoder.h"
#include "vl/vl_video_buffer.h"
#include "radeon/radeon_video.h"
+#include "amd/common/ac_llvm_util.h"
#include "amd/common/sid.h"
#include
#include
@@ -996,40 +997,6 @@ static int r600_get_video_param(struct pipe_screen *screen,
}
}
-const char *si_get_llvm_processor_name(enum radeon_family family)
-{
- switch (family) {
- case CHIP_TAHITI: return "tahiti";
- case CHIP_PITCAIRN: return "pitcairn";
- case CHIP_VERDE: return "verde";
- case CHIP_OLAND: return "oland";
- case CHIP_HAINAN: return "hainan";
- case CHIP_BONAIRE: return "bonaire";
- case CHIP_KABINI: return "kabini";
- case CHIP_KAVERI: return "kaveri";
- case CHIP_HAWAII: return "hawaii";
- case CHIP_MULLINS:
- return "mullins";
- case CHIP_TONGA: return "tonga";
- case CHIP_ICELAND: return "iceland";
- case CHIP_CARRIZO: return "carrizo";
- case CHIP_FIJI:
- return "fiji";
- case CHIP_STONEY:
- return "stoney";
- case CHIP_POLARIS10:
- return "polaris10";
- case CHIP_POLARIS11:
- case CHIP_POLARIS12: /* same as polaris11 */
- return "polaris11";
- case CHIP_VEGA10:
- case CHIP_RAVEN:
- return "gfx900";
- default:
- return "";
- }
-}
-
static unsigned get_max_threads_per_block(struct r600_common_screen *screen,
enum pipe_shader_ir ir_type)
{
@@ -1064,7 +1031,7 @@ static int r600_get_compute_param(struct pipe_screen
*screen,
else
triple = "amdgcn-mesa-mesa3d";
- gpu = si_get_llvm_processor_name(rscreen->family);
+ gpu = ac_get_llvm_processor_name(rscreen->family);
if (ret) {
sprintf(ret, "%s-%s", gpu, triple);
}
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index a7fec373fc..f803ee4633 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -717,7 +717,6 @@ void si_screen_clear_buffer(struct r600_common_screen
*rscreen, struct pipe_reso
uint64_t offset, uint64_t size, unsigned value);
struct pipe_resource *si_resource_create_common(struct pipe_screen *screen,
const struct pipe_resource
*templ);
-const char *si_get_llvm_processor_name(enum radeon_family family);
void si_need_dma_space(struct r600_common_context *ctx, unsigned num_dw,
struct r600_resource *dst, struct r600_resource *src);
void si_save_cs(struct radeon_winsys *ws, struct radeon_winsys_cs *cs,
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index 649a72e0fc..e96380ce40 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/driv
Mesa (master): radeonsi/gfx9: limit the scissor bug workaround to Vega10 and Raven only
Module: Mesa
Branch: master
Commit: e616743dabe4cdee789c7ad8386fbe9195cbb0ca
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e616743dabe4cdee789c7ad8386fbe9195cbb0ca
Author: Marek Olšák
Date: Tue Nov 7 16:12:56 2017 +0100
radeonsi/gfx9: limit the scissor bug workaround to Vega10 and Raven only
Reviewed-by: Nicolai Hähnle
---
src/gallium/drivers/radeonsi/si_state_draw.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index b17828e81f..994ed58a1b 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1405,11 +1405,11 @@ void si_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
if (!si_upload_vertex_buffer_descriptors(sctx))
return;
- /* GFX9 scissor bug workaround. This must be done before VPORT scissor
-* registers are changed. There is also a more efficient but more
-* involved alternative workaround.
+ /* Vega10/Raven scissor bug workaround. This must be done before VPORT
+* scissor registers are changed. There is also a more efficient but
+* more involved alternative workaround.
*/
- if (sctx->b.chip_class == GFX9 &&
+ if ((sctx->b.family == CHIP_VEGA10 || sctx->b.family == CHIP_RAVEN) &&
si_is_atom_dirty(sctx, &sctx->scissors.atom)) {
sctx->b.flags |= SI_CONTEXT_PS_PARTIAL_FLUSH;
si_emit_cache_flush(sctx);
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Mesa (master): mesa: fix deleting the dummy ATI_fs
Module: Mesa
Branch: master
Commit: cf47dfe8f18e5398dc55ead6c1495c14c3dec938
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cf47dfe8f18e5398dc55ead6c1495c14c3dec938
Author: Miklós Máté
Date: Fri Nov 3 02:01:42 2017 +0100
mesa: fix deleting the dummy ATI_fs
The DummyShader is used by GenFragmentShadersATI() as a placeholder to
mark IDs as allocated. Context cleanup wants to delete everything in
ctx->Shared->ATIShaders, and crashes on these placeholders with this
backtrace:
==15060== Invalid free() / delete / delete[] / realloc()
==15060==at 0x482F478: free (vg_replace_malloc.c:530)
==15060==by 0x57694F4: _mesa_delete_ati_fragment_shader (atifragshader.c:68)
==15060==by 0x58B33AB: delete_fragshader_cb (shared.c:208)
==15060==by 0x5838836: _mesa_HashDeleteAll (hash.c:295)
==15060==by 0x58B365F: free_shared_state (shared.c:377)
==15060==by 0x58B3BC2: _mesa_reference_shared_state (shared.c:469)
==15060==by 0x578687F: _mesa_free_context_data (context.c:1366)
==15060==by 0x595E9EC: st_destroy_context (st_context.c:642)
==15060==by 0x5987057: st_context_destroy (st_manager.c:772)
==15060==by 0x5B018B6: dri_destroy_context (dri_context.c:217)
==15060==by 0x5B006D3: driDestroyContext (dri_util.c:511)
==15060==by 0x4A1CBE6: dri3_destroy_context (dri3_glx.c:170)
==15060== Address 0x7b5dae0 is 0 bytes inside data symbol "DummyShader"
Also, DeleteFragmentShadersATI() should not assert on DummyShader, just
remove the hash entry.
Normally one would define a shader after GenFragmentShadersATI(), and
BindFragmentShaderATI() replaces the placeholder with a real object.
However, the specification doesn't say that one has to define a shader
for each allocated ID.
Signed-off-by: Miklós Máté
Signed-off-by: Marek Olšák
---
src/mesa/main/atifragshader.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/atifragshader.c b/src/mesa/main/atifragshader.c
index 27d8b86477..49ddb6e5af 100644
--- a/src/mesa/main/atifragshader.c
+++ b/src/mesa/main/atifragshader.c
@@ -60,6 +60,10 @@ void
_mesa_delete_ati_fragment_shader(struct gl_context *ctx, struct
ati_fragment_shader *s)
{
GLuint i;
+
+ if (s == &DummyShader)
+ return;
+
for (i = 0; i < MAX_NUM_PASSES_ATI; i++) {
free(s->Instructions[i]);
free(s->SetupInst[i]);
@@ -295,7 +299,6 @@ _mesa_DeleteFragmentShaderATI(GLuint id)
if (prog) {
prog->RefCount--;
if (prog->RefCount <= 0) {
- assert(prog != &DummyShader);
_mesa_delete_ati_fragment_shader(ctx, prog);
}
}
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Mesa (master): radeonsi: remove unused field in the PCI ID table
Module: Mesa Branch: master Commit: 24e90047088599e686b636fde9bda3a96f34a35c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=24e90047088599e686b636fde9bda3a96f34a35c Author: Marek Olšák Date: Tue Nov 7 15:27:43 2017 +0100 radeonsi: remove unused field in the PCI ID table Reviewed-by: Alex Deucher --- include/pci_ids/radeonsi_pci_ids.h| 458 +++--- src/amd/common/ac_gpu_info.c | 2 +- src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 2 +- src/loader/pci_id_driver_map.h| 2 +- 4 files changed, 232 insertions(+), 232 deletions(-) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index 9453c1c391..6a3594eabc 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -1,229 +1,229 @@ -CHIPSET(0x6780, TAHITI_6780, TAHITI) -CHIPSET(0x6784, TAHITI_6784, TAHITI) -CHIPSET(0x6788, TAHITI_6788, TAHITI) -CHIPSET(0x678A, TAHITI_678A, TAHITI) -CHIPSET(0x6790, TAHITI_6790, TAHITI) -CHIPSET(0x6791, TAHITI_6791, TAHITI) -CHIPSET(0x6792, TAHITI_6792, TAHITI) -CHIPSET(0x6798, TAHITI_6798, TAHITI) -CHIPSET(0x6799, TAHITI_6799, TAHITI) -CHIPSET(0x679A, TAHITI_679A, TAHITI) -CHIPSET(0x679B, TAHITI_679B, TAHITI) -CHIPSET(0x679E, TAHITI_679E, TAHITI) -CHIPSET(0x679F, TAHITI_679F, TAHITI) - -CHIPSET(0x6800, PITCAIRN_6800, PITCAIRN) -CHIPSET(0x6801, PITCAIRN_6801, PITCAIRN) -CHIPSET(0x6802, PITCAIRN_6802, PITCAIRN) -CHIPSET(0x6806, PITCAIRN_6806, PITCAIRN) -CHIPSET(0x6808, PITCAIRN_6808, PITCAIRN) -CHIPSET(0x6809, PITCAIRN_6809, PITCAIRN) -CHIPSET(0x6810, PITCAIRN_6810, PITCAIRN) -CHIPSET(0x6811, PITCAIRN_6811, PITCAIRN) -CHIPSET(0x6816, PITCAIRN_6816, PITCAIRN) -CHIPSET(0x6817, PITCAIRN_6817, PITCAIRN) -CHIPSET(0x6818, PITCAIRN_6818, PITCAIRN) -CHIPSET(0x6819, PITCAIRN_6819, PITCAIRN) -CHIPSET(0x684C, PITCAIRN_684C, PITCAIRN) - -CHIPSET(0x6820, VERDE_6820, VERDE) -CHIPSET(0x6821, VERDE_6821, VERDE) -CHIPSET(0x6822, VERDE_6822, VERDE) -CHIPSET(0x6823, VERDE_6823, VERDE) -CHIPSET(0x6824, VERDE_6824, VERDE) -CHIPSET(0x6825, VERDE_6825, VERDE) -CHIPSET(0x6826, VERDE_6826, VERDE) -CHIPSET(0x6827, VERDE_6827, VERDE) -CHIPSET(0x6828, VERDE_6828, VERDE) -CHIPSET(0x6829, VERDE_6829, VERDE) -CHIPSET(0x682A, VERDE_682A, VERDE) -CHIPSET(0x682B, VERDE_682B, VERDE) -CHIPSET(0x682C, VERDE_682C, VERDE) -CHIPSET(0x682D, VERDE_682D, VERDE) -CHIPSET(0x682F, VERDE_682F, VERDE) -CHIPSET(0x6830, VERDE_6830, VERDE) -CHIPSET(0x6831, VERDE_6831, VERDE) -CHIPSET(0x6835, VERDE_6835, VERDE) -CHIPSET(0x6837, VERDE_6837, VERDE) -CHIPSET(0x6838, VERDE_6838, VERDE) -CHIPSET(0x6839, VERDE_6839, VERDE) -CHIPSET(0x683B, VERDE_683B, VERDE) -CHIPSET(0x683D, VERDE_683D, VERDE) -CHIPSET(0x683F, VERDE_683F, VERDE) - -CHIPSET(0x6600, OLAND_6600, OLAND) -CHIPSET(0x6601, OLAND_6601, OLAND) -CHIPSET(0x6602, OLAND_6602, OLAND) -CHIPSET(0x6603, OLAND_6603, OLAND) -CHIPSET(0x6604, OLAND_6604, OLAND) -CHIPSET(0x6605, OLAND_6605, OLAND) -CHIPSET(0x6606, OLAND_6606, OLAND) -CHIPSET(0x6607, OLAND_6607, OLAND) -CHIPSET(0x6608, OLAND_6608, OLAND) -CHIPSET(0x6610, OLAND_6610, OLAND) -CHIPSET(0x6611, OLAND_6611, OLAND) -CHIPSET(0x6613, OLAND_6613, OLAND) -CHIPSET(0x6617, OLAND_6617, OLAND) -CHIPSET(0x6620, OLAND_6620, OLAND) -CHIPSET(0x6621, OLAND_6621, OLAND) -CHIPSET(0x6623, OLAND_6623, OLAND) -CHIPSET(0x6631, OLAND_6631, OLAND) - -CHIPSET(0x6660, HAINAN_6660, HAINAN) -CHIPSET(0x6663, HAINAN_6663, HAINAN) -CHIPSET(0x6664, HAINAN_6664, HAINAN) -CHIPSET(0x6665, HAINAN_6665, HAINAN) -CHIPSET(0x6667, HAINAN_6667, HAINAN) -CHIPSET(0x666F, HAINAN_666F, HAINAN) - -CHIPSET(0x6640, BONAIRE_6640, BONAIRE) -CHIPSET(0x6641, BONAIRE_6641, BONAIRE) -CHIPSET(0x6646, BONAIRE_6646, BONAIRE) -CHIPSET(0x6647, BONAIRE_6647, BONAIRE) -CHIPSET(0x6649, BONAIRE_6649, BONAIRE) -CHIPSET(0x6650, BONAIRE_6650, BONAIRE) -CHIPSET(0x6651, BONAIRE_6651, BONAIRE) -CHIPSET(0x6658, BONAIRE_6658, BONAIRE) -CHIPSET(0x665C, BONAIRE_665C, BONAIRE) -CHIPSET(0x665D, BONAIRE_665D, BONAIRE) -CHIPSET(0x665F, BONAIRE_665F, BONAIRE) - -CHIPSET(0x9830, KABINI_9830, KABINI) -CHIPSET(0x9831, KABINI_9831, KABINI) -CHIPSET(0x9832, KABINI_9832, KABINI) -CHIPSET(0x9833, KABINI_9833, KABINI) -CHIPSET(0x9834, KABINI_9834, KABINI) -CHIPSET(0x9835, KABINI_9835, KABINI) -CHIPSET(0x9836, KABINI_9836, KABINI) -CHIPSET(0x9837, KABINI_9837, KABINI) -CHIPSET(0x9838, KABINI_9838, KABINI) -CHIPSET(0x9839, KABINI_9839, KABINI) -CHIPSET(0x983A, KABINI_983A, KABINI) -CHIPSET(0x983B, KABINI_983B, KABINI) -CHIPSET(0x983C, KABINI_983C, KABINI) -CHIPSET(0x983D, KABINI_983D, KABINI) -CHIPSET(0x983E, KABINI_983E, KABINI) -CHIPSET(0x983F, KABINI_983F, KABINI) - -CHIPSET(0x9850, MULLINS_9850, MULLINS) -CHIPSET(0x9851, MULLINS_9851, MULLINS) -CHIPSET(0x9852, MULLINS_9852, MULLINS) -CHIPSET(0x9853, MULLINS_9853, MULLINS) -CHIPSET(0x9854, MULLINS_9854, MULLINS) -CHIPSET(0x9855, MULLINS_9855, MULLINS) -CHIPSET(0x9856, MULLINS_9856, MULLINS) -CHIPSET(0x9857, MULLINS_9857, MULLINS) -CHIPSET(0x9
Mesa (master): gallium: Guard assertions by NDEBUG instead of DEBUG
Module: Mesa Branch: master Commit: cd3b55ad07dbf1a7cfd3b30109d0562bea692576 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd3b55ad07dbf1a7cfd3b30109d0562bea692576 Author: Michel Dänzer Date: Tue Nov 7 10:48:12 2017 +0100 gallium: Guard assertions by NDEBUG instead of DEBUG This matches the standard assert.h header. Reviewed-by: Eric Engestrom Reviewed-by: Marek Olšák --- src/gallium/auxiliary/util/u_debug.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/util/u_debug.h b/src/gallium/auxiliary/util/u_debug.h index 63940b7225..d2ea89f59c 100644 --- a/src/gallium/auxiliary/util/u_debug.h +++ b/src/gallium/auxiliary/util/u_debug.h @@ -185,7 +185,7 @@ void _debug_assert_fail(const char *expr, * For non debug builds the assert macro will expand to a no-op, so do not * call functions with side effects in the assert expression. */ -#ifdef DEBUG +#ifndef NDEBUG #define debug_assert(expr) ((expr) ? (void)0 : _debug_assert_fail(#expr, __FILE__, __LINE__, __FUNCTION__)) #else #define debug_assert(expr) (void)(0 && (expr)) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa: tag mesa-17.3.0-rc3: mesa-17.3.0-rc3
Module: Mesa Branch: refs/tags/mesa-17.3.0-rc3 Tag:3a46e8bbdbe49b22c6c285aef695409f52dbbbc8 URL: http://cgit.freedesktop.org/mesa/mesa/tag/?id=3a46e8bbdbe49b22c6c285aef695409f52dbbbc8 Tagger: Emil Velikov Date: Tue Nov 7 12:14:04 2017 + mesa-17.3.0-rc3 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (17.3): i965: Check CCS_E compatibility for texture view rendering
Module: Mesa
Branch: 17.3
Commit: 14c40ebd0f232fe75f90251642ffd19b83f4aa48
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=14c40ebd0f232fe75f90251642ffd19b83f4aa48
Author: Nanley Chery
Date: Thu Oct 26 16:05:52 2017 -0700
i965: Check CCS_E compatibility for texture view rendering
Only use CCS_E to render to a texture that is CCS_E-compatible with the
original texture's miptree (linear) format. This prevents render
operations from writing data that can't be decoded with the original
miptree format.
On Gen10, with the new CCS_E-enabled formats handled, this enables the
driver to pass the arb_texture_view-rendering-formats piglit test.
v2. Add a TODO for texturing. (Jason)
Cc:
Signed-off-by: Nanley Chery
Reviewed-by: Jason Ekstrand
(cherry picked from commit 9e849eb8bb97259136b40dc2b06f42a81cfd3dae)
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 29 +--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 78c29bce8f..ae596c7202 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -241,6 +241,27 @@ intel_miptree_supports_hiz(const struct brw_context *brw,
}
}
+/**
+ * Return true if the format that will be used to access the miptree is
+ * CCS_E-compatible with the miptree's linear/non-sRGB format.
+ *
+ * Why use the linear format? Well, although the miptree may be specified with
+ * an sRGB format, the usage of that color space/format can be toggled. Since
+ * our HW tends to support more linear formats than sRGB ones, we use this
+ * format variant for check for CCS_E compatibility.
+ */
+static bool
+format_ccs_e_compat_with_miptree(const struct gen_device_info *devinfo,
+ const struct intel_mipmap_tree *mt,
+ enum isl_format access_format)
+{
+ assert(mt->aux_usage == ISL_AUX_USAGE_CCS_E);
+
+ mesa_format linear_format = _mesa_get_srgb_format_linear(mt->format);
+ enum isl_format isl_format = brw_isl_format_for_mesa_format(linear_format);
+ return isl_formats_are_ccs_e_compatible(devinfo, isl_format, access_format);
+}
+
static bool
intel_miptree_supports_ccs_e(struct brw_context *brw,
const struct intel_mipmap_tree *mt)
@@ -2549,6 +2570,7 @@ can_texture_with_ccs(struct brw_context *brw,
if (mt->aux_usage != ISL_AUX_USAGE_CCS_E)
return false;
+ /* TODO: Replace with format_ccs_e_compat_with_miptree for better perf. */
if (!isl_formats_are_ccs_e_compatible(&brw->screen->devinfo,
mt->surf.format, view_format)) {
perf_debug("Incompatible sampling format (%s) for rbc (%s)\n",
@@ -2666,8 +2688,11 @@ intel_miptree_render_aux_usage(struct brw_context *brw,
return mt->mcs_buf ? ISL_AUX_USAGE_CCS_D : ISL_AUX_USAGE_NONE;
case ISL_AUX_USAGE_CCS_E: {
- /* If the format supports CCS_E, then we can just use it */
- if (isl_format_supports_ccs_e(&brw->screen->devinfo, render_format))
+ /* If the format supports CCS_E and is compatible with the miptree,
+ * then we can use it.
+ */
+ if (format_ccs_e_compat_with_miptree(&brw->screen->devinfo,
+ mt, render_format))
return ISL_AUX_USAGE_CCS_E;
/* Otherwise, we have to fall back to CCS_D */
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Mesa (17.3): intel/compiler/gen9: Pixel shader header only workaround
Module: Mesa
Branch: 17.3
Commit: f0951a6aa9a357179d493eb1a7c1e2476ed046fe
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0951a6aa9a357179d493eb1a7c1e2476ed046fe
Author: Topi Pohjolainen
Date: Wed Oct 25 16:50:11 2017 +0300
intel/compiler/gen9: Pixel shader header only workaround
Fixes intermittent GPU hangs on Broxton with an Intel internal
test case.
There are plenty of similar fragment shaders in piglit that do
not use any varyings and any uniforms. According to the
documentation special timing is needed between pipeline stages.
Apparently we just don't hit that with piglit. Even with the
failing test case one doesn't always get the hang.
Moreover, according to the error states the hang happens
significantly later than the execution of the problematic shader.
There are multiple render cycles (primitive submissions) in between.
I've also seen error states where the ACTHD points outside the
batch. Almost as if the hardware writes somewhere that gets used
later on. That would also explain why piglit doesn't suffer from
this - most tests kick off one render cycle and any corruption
is left unseen.
v2 (Ken): Instead of enabling push constants, enable one of the
inputs (PSIZ).
v3 (Ken, Jason): Use LAYER instead making vulkan emit_3dstate_sbe()
happy.
Cc: "17.3 17.2"
Reviewed-by: Kenneth Graunke
Signed-off-by: Topi Pohjolainen
(cherry picked from commit 97e01adfd549c260efd615289938265306d42a05)
---
src/intel/compiler/brw_fs.cpp | 29 +
1 file changed, 29 insertions(+)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 4616529abc..2dee841c09 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -6166,6 +6166,31 @@ fs_visitor::run_gs()
return !failed;
}
+/* From the SKL PRM, Volume 16, Workarounds:
+ *
+ * 0877 3D Pixel Shader Hang possible when pixel shader dispatched with
+ * only header phases (R0-R2)
+ *
+ * WA: Enable a non-header phase (e.g. push constant) when dispatch would
+ * have been header only.
+ *
+ * Instead of enabling push constants one can alternatively enable one of the
+ * inputs. Here one simply chooses "layer" which shouldn't impose much
+ * overhead.
+ */
+static void
+gen9_ps_header_only_workaround(struct brw_wm_prog_data *wm_prog_data)
+{
+ if (wm_prog_data->num_varying_inputs)
+ return;
+
+ if (wm_prog_data->base.curb_read_length)
+ return;
+
+ wm_prog_data->urb_setup[VARYING_SLOT_LAYER] = 0;
+ wm_prog_data->num_varying_inputs = 1;
+}
+
bool
fs_visitor::run_fs(bool allow_spilling, bool do_rep_send)
{
@@ -6229,6 +6254,10 @@ fs_visitor::run_fs(bool allow_spilling, bool do_rep_send)
optimize();
assign_curb_setup();
+
+ if (devinfo->gen >= 9)
+ gen9_ps_header_only_workaround(wm_prog_data);
+
assign_urb_setup();
fixup_3src_null_dest();
___
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Mesa (17.3): pdate version to 17.3.0-rc3
Module: Mesa Branch: 17.3 Commit: 19b62847e0c3465c81efa949fea41b32a0c8c0dc URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=19b62847e0c3465c81efa949fea41b32a0c8c0dc Author: Emil Velikov Date: Tue Nov 7 11:51:45 2017 + pdate version to 17.3.0-rc3 Signed-off-by: Emil Velikov --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index 00ea172fd7..0c573cb72b 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -17.3.0-rc2 +17.3.0-rc3 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (17.3): etnaviv: don't do resolve-in-place without valid TS
Module: Mesa
Branch: 17.3
Commit: 71571aab1432faedf2cd01163fab1aad22d2931c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=71571aab1432faedf2cd01163fab1aad22d2931c
Author: Wladimir J. van der Laan
Date: Wed Nov 1 11:17:53 2017 +0100
etnaviv: don't do resolve-in-place without valid TS
GC3000 resolve-in-place assumes that the TS state is configured.
If it is not, this will result in MMU errors. This is especially
apparent when using glGenMipmaps().
Fixes: 78ade659569e ("etnaviv: Do GC3000 resolve-in-place when possible")
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Wladimir J. van der Laan
Tested-by: Chris Healy
Signed-off-by: Lucas Stach
(cherry picked from commit 8fbd82f464f26a56167f7962174b2b69756a105a)
---
src/gallium/drivers/etnaviv/etnaviv_clear_blit.c | 4
src/gallium/drivers/etnaviv/etnaviv_emit.c | 4
src/gallium/drivers/etnaviv/etnaviv_rs.c | 1 +
src/gallium/drivers/etnaviv/etnaviv_rs.h | 2 ++
4 files changed, 11 insertions(+)
diff --git a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
index 7b3fc1822b..21f50b7c2e 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
@@ -555,6 +555,7 @@ etna_try_rs_blit(struct pipe_context *pctx,
}
/* Set up color TS to source surface before blit, if needed */
+ bool source_ts_valid = false;
if (src->levels[blit_info->src.level].ts_size &&
src->levels[blit_info->src.level].ts_valid) {
struct etna_reloc reloc;
@@ -579,6 +580,8 @@ etna_try_rs_blit(struct pipe_context *pctx,
etna_set_state(ctx->stream, VIVS_TS_COLOR_CLEAR_VALUE,
src->levels[blit_info->src.level].clear_value);
+
+ source_ts_valid = true;
} else {
etna_set_state(ctx->stream, VIVS_TS_MEM_CONFIG, ts_mem_config);
}
@@ -593,6 +596,7 @@ etna_try_rs_blit(struct pipe_context *pctx,
.source_stride = src_lev->stride,
.source_padded_width = src_lev->padded_width,
.source_padded_height = src_lev->padded_height,
+ .source_ts_valid = source_ts_valid,
.dest_format = translate_rs_format(dst_format),
.dest_tiling = dst->layout,
.dest = dst->bo,
diff --git a/src/gallium/drivers/etnaviv/etnaviv_emit.c
b/src/gallium/drivers/etnaviv/etnaviv_emit.c
index 707b1e7349..5397aa33ce 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_emit.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_emit.c
@@ -171,6 +171,10 @@ etna_submit_rs_state(struct etna_context *ctx,
struct etna_cmd_stream *stream = ctx->stream;
struct etna_coalesce coalesce;
+ if (cs->RS_KICKER_INPLACE && !cs->source_ts_valid)
+ /* Inplace resolve is no-op if TS is not configured */
+ return;
+
ctx->stats.rs_operations++;
if (cs->RS_KICKER_INPLACE) {
diff --git a/src/gallium/drivers/etnaviv/etnaviv_rs.c
b/src/gallium/drivers/etnaviv/etnaviv_rs.c
index c9072c2645..60c2c39101 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_rs.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_rs.c
@@ -133,6 +133,7 @@ etna_compile_rs_state(struct etna_context *ctx, struct
compiled_rs_state *cs,
/* Total number of tiles (same as for autodisable) */
cs->RS_KICKER_INPLACE = rs->source_padded_width *
rs->source_padded_height / 16;
}
+ cs->source_ts_valid = rs->source_ts_valid;
}
void
diff --git a/src/gallium/drivers/etnaviv/etnaviv_rs.h
b/src/gallium/drivers/etnaviv/etnaviv_rs.h
index 171d3fa009..41a596055f 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_rs.h
+++ b/src/gallium/drivers/etnaviv/etnaviv_rs.h
@@ -33,6 +33,7 @@
struct rs_state {
uint8_t downsample_x : 1; /* Downsample in x direction */
uint8_t downsample_y : 1; /* Downsample in y direction */
+ uint8_t source_ts_valid : 1;
uint8_t source_format; /* RS_FORMAT_XXX */
uint8_t source_tiling; /* ETNA_LAYOUT_XXX */
@@ -61,6 +62,7 @@ struct rs_state {
/* treat this as opaque structure */
struct compiled_rs_state {
+ uint8_t source_ts_valid : 1;
uint32_t RS_CONFIG;
uint32_t RS_SOURCE_STRIDE;
uint32_t RS_DEST_STRIDE;
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Mesa (17.3): radv: add cache items to in memory cache when reading from disk
Module: Mesa
Branch: 17.3
Commit: b4bf9f6a41881b3a8cb63bd23d15ac0c08df4982
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b4bf9f6a41881b3a8cb63bd23d15ac0c08df4982
Author: Timothy Arceri
Date: Thu Oct 26 09:35:48 2017 +1100
radv: add cache items to in memory cache when reading from disk
Otherwise we will leak them, load duplicates from disk rather
than memory and never write items loaded from disk to the apps
pipeline cache.
Fixes: fd24be134ffd 'radv: make use of on-disk cache'
Reviewed-by: Bas Nieuwenhuizen
(cherry picked from commit 1e84e53712aed4892fbaf98e6f26ffdf76f06165)
Squashed with commit:
radv: use correct alloc function when loading from disk
Fixes regression in:
dEQP-VK.api.object_management.alloc_callback_fail.graphics_pipeline
Fixes: 1e84e53712ae "radv: add cache items to in memory cache when reading from
disk"
Reviewed-by: Bas Nieuwenhuizen
(cherry picked from commit e92405c55aa885bee5dfb05fac032cab5e419290)
---
src/amd/vulkan/radv_pipeline_cache.c | 154 +++
1 file changed, 84 insertions(+), 70 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline_cache.c
b/src/amd/vulkan/radv_pipeline_cache.c
index 9ba9a3b61b..2bf63793f6 100644
--- a/src/amd/vulkan/radv_pipeline_cache.c
+++ b/src/amd/vulkan/radv_pipeline_cache.c
@@ -170,6 +170,75 @@ radv_pipeline_cache_search(struct radv_pipeline_cache
*cache,
return entry;
}
+static void
+radv_pipeline_cache_set_entry(struct radv_pipeline_cache *cache,
+ struct cache_entry *entry)
+{
+ const uint32_t mask = cache->table_size - 1;
+ const uint32_t start = entry->sha1_dw[0];
+
+ /* We'll always be able to insert when we get here. */
+ assert(cache->kernel_count < cache->table_size / 2);
+
+ for (uint32_t i = 0; i < cache->table_size; i++) {
+ const uint32_t index = (start + i) & mask;
+ if (!cache->hash_table[index]) {
+ cache->hash_table[index] = entry;
+ break;
+ }
+ }
+
+ cache->total_size += entry_size(entry);
+ cache->kernel_count++;
+}
+
+
+static VkResult
+radv_pipeline_cache_grow(struct radv_pipeline_cache *cache)
+{
+ const uint32_t table_size = cache->table_size * 2;
+ const uint32_t old_table_size = cache->table_size;
+ const size_t byte_size = table_size * sizeof(cache->hash_table[0]);
+ struct cache_entry **table;
+ struct cache_entry **old_table = cache->hash_table;
+
+ table = malloc(byte_size);
+ if (table == NULL)
+ return VK_ERROR_OUT_OF_HOST_MEMORY;
+
+ cache->hash_table = table;
+ cache->table_size = table_size;
+ cache->kernel_count = 0;
+ cache->total_size = 0;
+
+ memset(cache->hash_table, 0, byte_size);
+ for (uint32_t i = 0; i < old_table_size; i++) {
+ struct cache_entry *entry = old_table[i];
+ if (!entry)
+ continue;
+
+ radv_pipeline_cache_set_entry(cache, entry);
+ }
+
+ free(old_table);
+
+ return VK_SUCCESS;
+}
+
+static void
+radv_pipeline_cache_add_entry(struct radv_pipeline_cache *cache,
+ struct cache_entry *entry)
+{
+ if (cache->kernel_count == cache->table_size / 2)
+ radv_pipeline_cache_grow(cache);
+
+ /* Failing to grow that hash table isn't fatal, but may mean we don't
+* have enough space to add this new kernel. Only add it if there's
room.
+*/
+ if (cache->kernel_count < cache->table_size / 2)
+ radv_pipeline_cache_set_entry(cache, entry);
+}
+
bool
radv_create_shader_variants_from_pipeline_cache(struct radv_device *device,
struct radv_pipeline_cache
*cache,
@@ -201,6 +270,21 @@ radv_create_shader_variants_from_pipeline_cache(struct
radv_device *device,
if (!entry) {
pthread_mutex_unlock(&cache->mutex);
return false;
+ } else {
+ size_t size = entry_size(entry);
+ struct cache_entry *new_entry = vk_alloc(&cache->alloc,
size, 8,
+
VK_SYSTEM_ALLOCATION_SCOPE_CACHE);
+ if (!new_entry) {
+ free(entry);
+ pthread_mutex_unlock(&cache->mutex);
+ return false;
+ }
+
+ memcpy(new_entry, entry, entry_size(entry));
+ free(entry);
+ entry = new_entry;
+
+ radv_pipeline_cache_add_entry(cache, new_entry);
}
}
@@ -246,76 +330,6 @@ radv_create_shader_variants_from_pipeline_cache(struct
radv_device *device,
return true;
}
-
-static void
-radv_pipeli
Mesa (17.3): i965: fix blorp stage_prog_data->param leak
Module: Mesa
Branch: 17.3
Commit: 7826bc95387f4e0da029b9ec73a91d20d82a718b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7826bc95387f4e0da029b9ec73a91d20d82a718b
Author: Tapani Pälli
Date: Fri Oct 27 14:49:40 2017 +0300
i965: fix blorp stage_prog_data->param leak
Patch uses mem_ctx for allocation to ensure param array gets freed
later.
==6164== 48 bytes in 1 blocks are definitely lost in loss record 61 of 193
==6164==at 0x4C2EB6B: malloc (vg_replace_malloc.c:299)
==6164==by 0x12E31C6C: ralloc_size (ralloc.c:121)
==6164==by 0x130189F1: fs_visitor::assign_constant_locations()
(brw_fs.cpp:2095)
==6164==by 0x13022D32: fs_visitor::optimize() (brw_fs.cpp:5715)
==6164==by 0x13024D5A: fs_visitor::run_fs(bool, bool) (brw_fs.cpp:6229)
==6164==by 0x1302549A: brw_compile_fs (brw_fs.cpp:6570)
==6164==by 0x130C4B07: blorp_compile_fs (blorp.c:194)
==6164==by 0x130D384B: blorp_params_get_clear_kernel (blorp_clear.c:79)
==6164==by 0x130D3C56: blorp_fast_clear (blorp_clear.c:332)
==6164==by 0x12EFA439: do_single_blorp_clear (brw_blorp.c:1261)
==6164==by 0x12EFC4AF: brw_blorp_clear_color (brw_blorp.c:1326)
==6164==by 0x12EFF72B: brw_clear (brw_clear.c:297)
Fixes: 8d90e28839 ("intel/compiler: Allocate pull_param in
assign_constant_locations")
Signed-off-by: Tapani Pälli
Reviewed-by: Lionel Landwerlin
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit 446c5726ecb968d06a6607e0df42be1cb74948c4)
---
src/intel/compiler/brw_fs.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 2dee841c09..e546792255 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -2092,7 +2092,7 @@ fs_visitor::assign_constant_locations()
*/
uint32_t *param = stage_prog_data->param;
stage_prog_data->nr_params = num_push_constants;
- stage_prog_data->param = ralloc_array(NULL, uint32_t, num_push_constants);
+ stage_prog_data->param = ralloc_array(mem_ctx, uint32_t,
num_push_constants);
if (num_pull_constants > 0) {
stage_prog_data->nr_pull_params = num_pull_constants;
stage_prog_data->pull_param = ralloc_array(NULL, uint32_t,
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Mesa (17.3): i965: Fix ARB_indirect_parameters logic.
Module: Mesa
Branch: 17.3
Commit: d5cc7e47a8ad6c3ebaeecb733190d19966d49109
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5cc7e47a8ad6c3ebaeecb733190d19966d49109
Author: Plamena Manolova
Date: Mon Oct 30 21:14:24 2017 +
i965: Fix ARB_indirect_parameters logic.
This patch modifies the ARB_indirect_parameters logic in
brw_draw_prims, so that our implementation isn't affected if
another application attempts to use predicates. Previously we
were using a predicate with a DELTAS_EQUAL comparison operation
and relying on the MI_PREDICATE_DATA register being 0. Our code
to initialize MI_PREDICATE_DATA to 0 was incorrect, so we were
accidentally using whatever value was written there. Because the
kernel does not initialize the MI_PREDICATE_DATA register on
hardware context creation, we might inherit the value from whatever
context was last running on the GPU (likely another process).
The Haswell command parser also does not currently allow us to write
the MI_PREDICATE_DATA register. Rather than fixing this and requiring
an updated kernel, we switch to a different approach which uses a
SRCS_EQUAL predicate that makes no assumptions about the states of any
of the predicate registers.
Fixes Piglit's spec/arb_indirect_parameters/tf-count-arrays test.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103085
Signed-off-by: Plamena Manolova
Reviewed-by: Kenneth Graunke
(cherry picked from commit 048d4c45c94eb8d99f2a53f3bf200b2c6a9f9629)
---
src/mesa/drivers/dri/i965/brw_draw.c | 47
1 file changed, 16 insertions(+), 31 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 1e5c4993c5..ecd1d670d0 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -875,7 +875,6 @@ brw_draw_prims(struct gl_context *ctx,
struct brw_context *brw = brw_context(ctx);
const struct gl_vertex_array **arrays = ctx->Array._DrawArrays;
int predicate_state = brw->predicate.state;
- int combine_op = MI_PREDICATE_COMBINEOP_SET;
struct brw_transform_feedback_object *xfb_obj =
(struct brw_transform_feedback_object *) gl_xfb_obj;
@@ -919,49 +918,35 @@ brw_draw_prims(struct gl_context *ctx,
* to it.
*/
-if (brw->draw.draw_params_count_bo &&
-predicate_state == BRW_PREDICATE_STATE_USE_BIT) {
- /* We need to empty the MI_PREDICATE_DATA register since it might
- * already be set.
- */
-
- BEGIN_BATCH(4);
- OUT_BATCH(MI_PREDICATE_DATA);
- OUT_BATCH(0u);
- OUT_BATCH(MI_PREDICATE_DATA + 4);
- OUT_BATCH(0u);
- ADVANCE_BATCH();
-
- /* We need to combine the results of both predicates.*/
- combine_op = MI_PREDICATE_COMBINEOP_AND;
- }
-
for (i = 0; i < nr_prims; i++) {
/* Implementation of ARB_indirect_parameters via predicates */
if (brw->draw.draw_params_count_bo) {
- struct brw_bo *draw_id_bo = NULL;
- uint32_t draw_id_offset;
-
- intel_upload_data(brw, &prims[i].draw_id, 4, 4, &draw_id_bo,
- &draw_id_offset);
-
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_FLUSH_ENABLE);
+ /* Upload the current draw count from the draw parameters buffer to
+ * MI_PREDICATE_SRC0.
+ */
brw_load_register_mem(brw, MI_PREDICATE_SRC0,
brw->draw.draw_params_count_bo,
brw->draw.draw_params_count_offset);
- brw_load_register_mem(brw, MI_PREDICATE_SRC1, draw_id_bo,
- draw_id_offset);
+ /* Zero the top 32-bits of MI_PREDICATE_SRC0 */
+ brw_load_register_imm32(brw, MI_PREDICATE_SRC0 + 4, 0);
+ /* Upload the id of the current primitive to MI_PREDICATE_SRC1. */
+ brw_load_register_imm64(brw, MI_PREDICATE_SRC1, prims[i].draw_id);
BEGIN_BATCH(1);
- OUT_BATCH(GEN7_MI_PREDICATE |
- MI_PREDICATE_LOADOP_LOADINV | combine_op |
- MI_PREDICATE_COMPAREOP_DELTAS_EQUAL);
+ if (i == 0 && brw->predicate.state != BRW_PREDICATE_STATE_USE_BIT) {
+OUT_BATCH(GEN7_MI_PREDICATE | MI_PREDICATE_LOADOP_LOADINV |
+ MI_PREDICATE_COMBINEOP_SET |
+ MI_PREDICATE_COMPAREOP_SRCS_EQUAL);
+ } else {
+OUT_BATCH(GEN7_MI_PREDICATE |
+ MI_PREDICATE_LOADOP_LOAD | MI_PREDICATE_COMBINEOP_XOR |
+ MI_PREDICATE_COMPAREOP_SRCS_EQUAL);
+ }
ADVANCE_BATCH();
brw->predicate.state = BRW_PREDICATE_STATE_USE_BIT;
-
- brw_bo_unreference(draw_id_bo);
}
brw_draw_single_prim(ctx, arrays, &prims[i], i, xfb_obj, stream,
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Mesa (17.3): intel/fs: Alloc pull constants off mem_ctx
Module: Mesa
Branch: 17.3
Commit: 383b3603482616765e0716fd42a0698772b36d0f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=383b3603482616765e0716fd42a0698772b36d0f
Author: Jason Ekstrand
Date: Wed Nov 1 07:57:21 2017 -0700
intel/fs: Alloc pull constants off mem_ctx
It doesn't actually matter since the only user of push constants, i965,
ralloc_steals it back to NULL but it's more consistent and probably
fixes memory leaks in some error cases.
Reviewed-by: Lionel Landwerlin
Reviewed-by: Tapani Pälli
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit 7b4387519c382cffef9c62efcfe71cfde905)
---
src/intel/compiler/brw_fs.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index e546792255..21ff030908 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -2095,7 +2095,7 @@ fs_visitor::assign_constant_locations()
stage_prog_data->param = ralloc_array(mem_ctx, uint32_t,
num_push_constants);
if (num_pull_constants > 0) {
stage_prog_data->nr_pull_params = num_pull_constants;
- stage_prog_data->pull_param = ralloc_array(NULL, uint32_t,
+ stage_prog_data->pull_param = ralloc_array(mem_ctx, uint32_t,
num_pull_constants);
}
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Mesa (17.3): radeonsi: fix culldist_writemask in nir path
Module: Mesa Branch: 17.3 Commit: 9710fbbcdfbc0d99424a333d692cae14a88a7863 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9710fbbcdfbc0d99424a333d692cae14a88a7863 Author: Timothy Arceri Date: Tue Oct 31 14:19:18 2017 +1100 radeonsi: fix culldist_writemask in nir path The shared si_create_shader_selector() code already offsets the mask. Fixes the following piglit tests: arb_cull_distance/clip-cull-3.shader_test arb_cull_distance/clip-cull-4.shader_test Fixes: 29d7bdd179bb (radeonsi: scan NIR shaders to obtain required info) Reviewed-by: Marek Olšák (cherry picked from commit e80bbd6f52341cbf9363f3c0c8b7ad3be851b1e6) --- src/gallium/drivers/radeonsi/si_shader_nir.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c b/src/gallium/drivers/radeonsi/si_shader_nir.c index e186661caf..7a88227381 100644 --- a/src/gallium/drivers/radeonsi/si_shader_nir.c +++ b/src/gallium/drivers/radeonsi/si_shader_nir.c @@ -302,8 +302,7 @@ void si_nir_scan_shader(const struct nir_shader *nir, info->num_written_clipdistance = nir->info.clip_distance_array_size; info->num_written_culldistance = nir->info.cull_distance_array_size; info->clipdist_writemask = u_bit_consecutive(0, info->num_written_clipdistance); - info->culldist_writemask = u_bit_consecutive(info->num_written_clipdistance, - info->num_written_culldistance); + info->culldist_writemask = u_bit_consecutive(0, info->num_written_culldistance); if (info->processor == PIPE_SHADER_FRAGMENT) info->uses_kill = nir->info.fs.uses_discard; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (17.3): i915g: make gears run again.
Module: Mesa
Branch: 17.3
Commit: 9b44ef94b4ed3960d9220a156b21b261e4cc320c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b44ef94b4ed3960d9220a156b21b261e4cc320c
Author: Dave Airlie
Date: Fri May 26 11:24:59 2017 +1000
i915g: make gears run again.
We need to validate some structs exist before we dirty the states, and
avoid the problem in some other places.
Fixes: e027935a7 ("st/mesa: don't update unrelated states in non-draw calls
such as Clear")
(cherry picked from commit cc69f2385ee5405cd1bef746d3e9006fc5430545)
---
src/gallium/drivers/i915/i915_state_derived.c | 17 +
src/gallium/drivers/i915/i915_state_dynamic.c | 3 ++-
src/gallium/drivers/i915/i915_state_immediate.c | 6 --
src/gallium/drivers/i915/i915_state_static.c| 2 +-
4 files changed, 24 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/i915/i915_state_derived.c
b/src/gallium/drivers/i915/i915_state_derived.c
index dbfbc84c9e..7809010d94 100644
--- a/src/gallium/drivers/i915/i915_state_derived.c
+++ b/src/gallium/drivers/i915/i915_state_derived.c
@@ -216,6 +216,23 @@ void i915_update_derived(struct i915_context *i915)
if (I915_DBG_ON(DBG_ATOMS))
i915_dump_dirty(i915, __FUNCTION__);
+ if (!i915->fs) {
+ i915->dirty &= ~(I915_NEW_FS_CONSTANTS | I915_NEW_FS);
+ i915->hardware_dirty &= ~(I915_HW_PROGRAM | I915_HW_CONSTANTS);
+ }
+
+ if (!i915->vs)
+ i915->dirty &= ~I915_NEW_VS;
+
+ if (!i915->blend)
+ i915->dirty &= ~I915_NEW_BLEND;
+
+ if (!i915->rasterizer)
+ i915->dirty &= ~I915_NEW_RASTERIZER;
+
+ if (!i915->depth_stencil)
+ i915->dirty &= ~I915_NEW_DEPTH_STENCIL;
+
for (i = 0; atoms[i]; i++)
if (atoms[i]->dirty & i915->dirty)
atoms[i]->update(i915);
diff --git a/src/gallium/drivers/i915/i915_state_dynamic.c
b/src/gallium/drivers/i915/i915_state_dynamic.c
index 85b2721567..434b09d4e0 100644
--- a/src/gallium/drivers/i915/i915_state_dynamic.c
+++ b/src/gallium/drivers/i915/i915_state_dynamic.c
@@ -213,7 +213,8 @@ static void upload_STIPPLE(struct i915_context *i915)
/* I915_NEW_RASTERIZER
*/
- st[1] |= i915->rasterizer->st;
+ if (i915->rasterizer)
+ st[1] |= i915->rasterizer->st;
/* I915_NEW_STIPPLE
*/
diff --git a/src/gallium/drivers/i915/i915_state_immediate.c
b/src/gallium/drivers/i915/i915_state_immediate.c
index b6007acdd1..14566a4bec 100644
--- a/src/gallium/drivers/i915/i915_state_immediate.c
+++ b/src/gallium/drivers/i915/i915_state_immediate.c
@@ -168,11 +168,13 @@ static void upload_S6(struct i915_context *i915)
/* I915_NEW_BLEND
*/
- LIS6 |= i915->blend->LIS6;
+ if (i915->blend)
+ LIS6 |= i915->blend->LIS6;
/* I915_NEW_DEPTH
*/
- LIS6 |= i915->depth_stencil->depth_LIS6;
+ if (i915->depth_stencil)
+ LIS6 |= i915->depth_stencil->depth_LIS6;
set_immediate(i915, I915_IMMEDIATE_S6, LIS6);
}
diff --git a/src/gallium/drivers/i915/i915_state_static.c
b/src/gallium/drivers/i915/i915_state_static.c
index 9a7ea227ec..88b418b1ac 100644
--- a/src/gallium/drivers/i915/i915_state_static.c
+++ b/src/gallium/drivers/i915/i915_state_static.c
@@ -216,7 +216,7 @@ static void update_dst_buf_vars(struct i915_context *i915)
zformat = translate_depth_format(depth_surface->format);
if (is->is_i945 && tex->tiling != I915_TILE_NONE
-&& !i915->fs->info.writes_z)
+ && (i915->fs && !i915->fs->info.writes_z))
early_z = CLASSIC_EARLY_DEPTH;
} else
zformat = 0;
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Mesa (17.3): nir/opt_intrinsics: Fix values for gl_SubGroupG{e, t}MaskARB
Module: Mesa
Branch: 17.3
Commit: 4c82f2c3a965f4be23dc3a58edf4db28cf20a3cc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c82f2c3a965f4be23dc3a58edf4db28cf20a3cc
Author: Neil Roberts
Date: Tue Oct 31 15:05:33 2017 +0100
nir/opt_intrinsics: Fix values for gl_SubGroupG{e,t}MaskARB
Previously the values were calculated by just shifting ~0 by the
invocation ID. This would end up including bits that are higher than
gl_SubGroupSizeARB. The corresponding CTS test effectively requires that
these high bits be zero so it was failing. There is a Piglit test as
well but this appears to checking the wrong values so it passes.
For the two greater-than bitmasks, this patch adds an extra mask with
(~0>>(64-gl_SubGroupSizeARB)) to force these bits to zero.
Fixes: KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102680#c3
Reviewed-by: Jason Ekstrand
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Neil Roberts
(cherry picked from commit b697ece10aa041b8653eb184d73dcf5b846729a3)
---
src/compiler/nir/nir_opt_intrinsics.c | 24 ++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git a/src/compiler/nir/nir_opt_intrinsics.c
b/src/compiler/nir/nir_opt_intrinsics.c
index f12dc8779c..68c004111e 100644
--- a/src/compiler/nir/nir_opt_intrinsics.c
+++ b/src/compiler/nir/nir_opt_intrinsics.c
@@ -28,6 +28,26 @@
* \file nir_opt_intrinsics.c
*/
+static nir_ssa_def *
+high_subgroup_mask(nir_builder *b,
+ nir_ssa_def *count,
+ uint64_t base_mask)
+{
+ /* group_mask could probably be calculated more efficiently but we want to
+* be sure not to shift by 64 if the subgroup size is 64 because the GLSL
+* shift operator is undefined in that case. In any case if we were worried
+* about efficency this should probably be done further down because the
+* subgroup size is likely to be known at compile time.
+*/
+ nir_ssa_def *subgroup_size = nir_load_subgroup_size(b);
+ nir_ssa_def *all_bits = nir_imm_int64(b, ~0ull);
+ nir_ssa_def *shift = nir_isub(b, nir_imm_int(b, 64), subgroup_size);
+ nir_ssa_def *group_mask = nir_ushr(b, all_bits, shift);
+ nir_ssa_def *higher_bits = nir_ishl(b, nir_imm_int64(b, base_mask), count);
+
+ return nir_iand(b, higher_bits, group_mask);
+}
+
static bool
opt_intrinsics_impl(nir_function_impl *impl)
{
@@ -95,10 +115,10 @@ opt_intrinsics_impl(nir_function_impl *impl)
replacement = nir_ishl(&b, nir_imm_int64(&b, 1ull), count);
break;
case nir_intrinsic_load_subgroup_ge_mask:
- replacement = nir_ishl(&b, nir_imm_int64(&b, ~0ull), count);
+ replacement = high_subgroup_mask(&b, count, ~0ull);
break;
case nir_intrinsic_load_subgroup_gt_mask:
- replacement = nir_ishl(&b, nir_imm_int64(&b, ~1ull), count);
+ replacement = high_subgroup_mask(&b, count, ~1ull);
break;
case nir_intrinsic_load_subgroup_le_mask:
replacement = nir_inot(&b, nir_ishl(&b, nir_imm_int64(&b,
~1ull), count));
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Mesa (17.3): radv: Don't expose heaps with 0 memory.
Module: Mesa
Branch: 17.3
Commit: 2516c3217ded38a9d025d90502cf5b029593c66c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2516c3217ded38a9d025d90502cf5b029593c66c
Author: Bas Nieuwenhuizen
Date: Wed Nov 1 09:26:48 2017 +0100
radv: Don't expose heaps with 0 memory.
It confuses CTS. This pregenerates the heap info into the
physical device, so we can use it for translating contiguous
indices into our "standard" ones.
This also makes the WSI a bit smarter in case the first preferred
heap does not exist.
Reviewed-by: Dave Airlie
CC:
(cherry picked from commit 806721429afa090380bf39a4958fe4e21c63816c)
---
src/amd/vulkan/radv_device.c | 135 ++
src/amd/vulkan/radv_private.h | 3 +
src/amd/vulkan/radv_wsi.c | 16 -
3 files changed, 101 insertions(+), 53 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 19ff8fec64..abdbdeb601 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -104,6 +104,75 @@ get_chip_name(enum radeon_family family)
}
}
+static void
+radv_physical_device_init_mem_types(struct radv_physical_device *device)
+{
+ STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
+ uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
+ device->rad_info.vram_vis_size);
+
+ int vram_index = -1, visible_vram_index = -1, gart_index = -1;
+ device->memory_properties.memoryHeapCount = 0;
+ if (device->rad_info.vram_size - visible_vram_size > 0) {
+ vram_index = device->memory_properties.memoryHeapCount++;
+ device->memory_properties.memoryHeaps[vram_index] =
(VkMemoryHeap) {
+ .size = device->rad_info.vram_size - visible_vram_size,
+ .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
+ };
+ }
+ if (visible_vram_size) {
+ visible_vram_index =
device->memory_properties.memoryHeapCount++;
+ device->memory_properties.memoryHeaps[visible_vram_index] =
(VkMemoryHeap) {
+ .size = visible_vram_size,
+ .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
+ };
+ }
+ if (device->rad_info.gart_size > 0) {
+ gart_index = device->memory_properties.memoryHeapCount++;
+ device->memory_properties.memoryHeaps[gart_index] =
(VkMemoryHeap) {
+ .size = device->rad_info.gart_size,
+ .flags = 0,
+ };
+ }
+
+ STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
+ unsigned type_count = 0;
+ if (vram_index >= 0) {
+ device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
+ device->memory_properties.memoryTypes[type_count++] =
(VkMemoryType) {
+ .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
+ .heapIndex = vram_index,
+ };
+ }
+ if (gart_index >= 0) {
+ device->mem_type_indices[type_count] =
RADV_MEM_TYPE_GTT_WRITE_COMBINE;
+ device->memory_properties.memoryTypes[type_count++] =
(VkMemoryType) {
+ .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
+ VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
+ .heapIndex = gart_index,
+ };
+ }
+ if (visible_vram_index >= 0) {
+ device->mem_type_indices[type_count] =
RADV_MEM_TYPE_VRAM_CPU_ACCESS;
+ device->memory_properties.memoryTypes[type_count++] =
(VkMemoryType) {
+ .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
+ VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
+ VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
+ .heapIndex = visible_vram_index,
+ };
+ }
+ if (gart_index >= 0) {
+ device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
+ device->memory_properties.memoryTypes[type_count++] =
(VkMemoryType) {
+ .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
+ VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
+ VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
+ .heapIndex = gart_index,
+ };
+ }
+ device->memory_properties.memoryTypeCount = type_count;
+}
+
static VkResult
radv_physical_device_init(struct radv_physical_device *device,
struct radv_instance *instance,
@@ -190,6 +259,7 @@ radv_physical_device_init(struct radv_physical_device
*device,
*/
device->has_clear_state = device->rad_info.chip_class >= CIK;
+ radv_physical_device_init_mem_types(device);
return VK_SUCCESS;
fail:
@@ -780,49 +850,7 @@ void radv_GetPhysicalDeviceMem
Mesa (17.3): disk_cache: Fix issue reading GLSL metadata
Module: Mesa Branch: 17.3 Commit: a12ca3b231a6454d8adf5da916af363c321b5f1a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a12ca3b231a6454d8adf5da916af363c321b5f1a Author: Jordan Justen Date: Fri Oct 13 22:04:52 2017 -0700 disk_cache: Fix issue reading GLSL metadata This would cause the read of the metadata content to fail, which would prevent the linking from being skipped. Seen on Rocket League with i965 shader cache. Fixes: b86ecea3446e "util/disk_cache: write cache item metadata to disk" Cc: Timothy Arceri Signed-off-by: Jordan Justen Reviewed-by: Timothy Arceri Reviewed-by: Jason Ekstrand Reviewed-by: Kenneth Graunke (cherry picked from commit e5b141634cff3aa1f68699f39a2c3794261a32b1) --- src/util/disk_cache.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/util/disk_cache.c b/src/util/disk_cache.c index e38cacb259..fde6e2e097 100644 --- a/src/util/disk_cache.c +++ b/src/util/disk_cache.c @@ -1110,7 +1110,7 @@ disk_cache_get(struct disk_cache *cache, const cache_key key, size_t *size) * TODO: pass the metadata back to the caller and do some basic * validation. */ - cache_item_md_size += sizeof(cache_key); + cache_item_md_size += num_keys * sizeof(cache_key); ret = lseek(fd, num_keys * sizeof(cache_key), SEEK_CUR); if (ret == -1) goto fail; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (17.3): r600/sb: bail out if prepare_alu_group() doesn' t find a proper scheduling
Module: Mesa
Branch: 17.3
Commit: 13bfb83b31adcd457ddd9ee8a198fa99eb7ba1cf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=13bfb83b31adcd457ddd9ee8a198fa99eb7ba1cf
Author: Gert Wollny
Date: Mon Oct 16 21:06:26 2017 +0200
r600/sb: bail out if prepare_alu_group() doesn't find a proper scheduling
It is possible that the optimizer ends up in an infinite loop in
post_scheduler::schedule_alu(), because post_scheduler::prepare_alu_group()
does not find a proper scheduling. This can be deducted from
pending.count() being larger than zero and not getting smaller.
This patch works around this problem by signalling this failure so that the
optimizers bails out and the un-optimized shader is used.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103142
Cc:
Signed-off-by: Gert Wollny
Signed-off-by: Dave Airlie
(cherry picked from commit 69eee511c631a8372803f175bd6f5a9551230424)
---
src/gallium/drivers/r600/sb/sb_sched.cpp | 43
src/gallium/drivers/r600/sb/sb_sched.h | 8 +++---
2 files changed, 31 insertions(+), 20 deletions(-)
diff --git a/src/gallium/drivers/r600/sb/sb_sched.cpp
b/src/gallium/drivers/r600/sb/sb_sched.cpp
index 5113b75684..2fbec2f77e 100644
--- a/src/gallium/drivers/r600/sb/sb_sched.cpp
+++ b/src/gallium/drivers/r600/sb/sb_sched.cpp
@@ -711,22 +711,24 @@ void alu_group_tracker::update_flags(alu_node* n) {
}
int post_scheduler::run() {
- run_on(sh.root);
- return 0;
+ return run_on(sh.root) ? 0 : 1;
}
-void post_scheduler::run_on(container_node* n) {
-
+bool post_scheduler::run_on(container_node* n) {
+ int r = true;
for (node_riterator I = n->rbegin(), E = n->rend(); I != E; ++I) {
if (I->is_container()) {
if (I->subtype == NST_BB) {
bb_node* bb = static_cast(*I);
- schedule_bb(bb);
+ r = schedule_bb(bb);
} else {
- run_on(static_cast(*I));
+ r = run_on(static_cast(*I));
}
+ if (!r)
+ break;
}
}
+ return r;
}
void post_scheduler::init_uc_val(container_node *c, value *v) {
@@ -758,7 +760,7 @@ unsigned post_scheduler::init_ucm(container_node *c, node
*n) {
return F == ucm.end() ? 0 : F->second;
}
-void post_scheduler::schedule_bb(bb_node* bb) {
+bool post_scheduler::schedule_bb(bb_node* bb) {
PSC_DUMP(
sblog << "scheduling BB " << bb->id << "\n";
if (!pending.empty())
@@ -791,8 +793,10 @@ void post_scheduler::schedule_bb(bb_node* bb) {
if (n->is_alu_clause()) {
n->remove();
- process_alu(static_cast(n));
- continue;
+ bool r = process_alu(static_cast(n));
+ if (r)
+ continue;
+ return false;
}
n->remove();
@@ -800,6 +804,7 @@ void post_scheduler::schedule_bb(bb_node* bb) {
}
this->cur_bb = NULL;
+ return true;
}
void post_scheduler::init_regmap() {
@@ -933,10 +938,10 @@ void post_scheduler::process_fetch(container_node *c) {
cur_bb->push_front(c);
}
-void post_scheduler::process_alu(container_node *c) {
+bool post_scheduler::process_alu(container_node *c) {
if (c->empty())
- return;
+ return true;
ucm.clear();
alu.reset();
@@ -973,7 +978,7 @@ void post_scheduler::process_alu(container_node *c) {
}
}
- schedule_alu(c);
+ return schedule_alu(c);
}
void post_scheduler::update_local_interferences() {
@@ -1135,15 +1140,20 @@ void post_scheduler::emit_clause() {
emit_index_registers();
}
-void post_scheduler::schedule_alu(container_node *c) {
+bool post_scheduler::schedule_alu(container_node *c) {
assert(!ready.empty() || !ready_copies.empty());
- while (1) {
-
+ bool improving = true;
+ int last_pending = pending.count();
+ while (improving) {
prev_regmap = regmap;
-
if (!prepare_alu_group()) {
+
+ int new_pending = pending.count();
+ improving = (new_pending < last_pending) ||
(last_pending == 0);
+ last_pending = new_pending;
+
if (alu.current_idx[0] || alu.current_idx[1]) {
regmap = prev_regmap;
emit_clause();
@@ -1186,6 +1196,7 @@ void post_scheduler::schedule_alu(container_node *c) {
dump::dump_op_list(&pending);
assert(!"unscheduled pending instructions");
}
+ return improving;
}
void post_scheduler::a
Mesa (17.3): Android: move drivers' symlinks to /vendor (v2)
Module: Mesa
Branch: 17.3
Commit: 77839e9ba8d963ef4933a7f4eaadc76c0676e39a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=77839e9ba8d963ef4933a7f4eaadc76c0676e39a
Author: Mauro Rossi
Date: Fri Oct 27 21:54:14 2017 +0200
Android: move drivers' symlinks to /vendor (v2)
Having moved gallium_dri.so library to /vendor/lib/dri
also symlinks need to be coherently created using TARGET_OUT_VENDOR instead of
TARGET_OUT
or all non Intel drivers will not be loaded with Android N and earlier,
thus causing SurfaceFlinger SIGABRT
(v2) simplification of post install command
Fixes: c3f75d483c ("Android: move libraries to /vendor")
Cc: 17.3
Reviewed-by: Tapani Pälli (v1)
Reviewed-by: Rob Herring (v1)
Reviewed-by: Emil Velikov
(cherry picked from commit 7dae419aa7c34af820c08896acef3b65d855188e)
---
src/gallium/targets/dri/Android.mk | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/gallium/targets/dri/Android.mk
b/src/gallium/targets/dri/Android.mk
index e40288c21b..5a3fda65d4 100644
--- a/src/gallium/targets/dri/Android.mk
+++ b/src/gallium/targets/dri/Android.mk
@@ -68,8 +68,9 @@ LOCAL_SHARED_LIBRARIES += $(sort $(GALLIUM_SHARED_LIBS))
ifneq ($(filter 5 6 7, $(MESA_ANDROID_MAJOR_VERSION)),)
LOCAL_POST_INSTALL_CMD := \
$(foreach l, lib $(if $(filter true,$(TARGET_IS_64_BIT)),lib64), \
- mkdir -p $(TARGET_OUT)/$(l)/$(MESA_DRI_MODULE_REL_PATH); \
- $(foreach d, $(GALLIUM_TARGET_DRIVERS), ln -sf gallium_dri.so
$(TARGET_OUT)/$(l)/$(MESA_DRI_MODULE_REL_PATH)/$(d)_dri.so;) \
+ $(eval MESA_DRI_MODULE_PATH :=
$(TARGET_OUT_VENDOR)/$(l)/$(MESA_DRI_MODULE_REL_PATH)) \
+ mkdir -p $(MESA_DRI_MODULE_PATH); \
+ $(foreach d, $(GALLIUM_TARGET_DRIVERS), ln -sf gallium_dri.so
$(MESA_DRI_MODULE_PATH)/$(d)_dri.so;) \
)
else
LOCAL_MODULE_SYMLINKS := $(foreach d, $(GALLIUM_TARGET_DRIVERS), $(d)_dri.so)
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Mesa (master): meson: standardize .so version to major.minor.patch
Module: Mesa
Branch: master
Commit: 5be1b1a8ce6c635cf0310d2b97056a2b8f11a601
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5be1b1a8ce6c635cf0310d2b97056a2b8f11a601
Author: Eric Engestrom
Date: Thu Nov 2 23:24:00 2017 +
meson: standardize .so version to major.minor.patch
This `version` field defines the filename for the .so.
The plan .so as well as .so.$major are always symlinks to this.
Unless I'm mistaken, only the major is ever used, so this shouldn't
matter, but for consistency with autotools (and in case it does matter),
let's always have all 3 major.minor.patch components.
(The soname isn't affected, and is always .so.$major)
Signed-off-by: Eric Engestrom
Reviewed-by: Dylan Baker
---
src/egl/meson.build| 2 +-
src/gallium/targets/osmesa/meson.build | 2 +-
src/gbm/meson.build| 2 +-
src/glx/meson.build| 2 +-
src/mapi/es1api/meson.build| 2 +-
src/mapi/es2api/meson.build| 2 +-
src/mapi/shared-glapi/meson.build | 1 +
src/mesa/drivers/osmesa/meson.build| 2 +-
8 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/src/egl/meson.build b/src/egl/meson.build
index 67ca8cef92..36b1d9e41b 100644
--- a/src/egl/meson.build
+++ b/src/egl/meson.build
@@ -145,7 +145,7 @@ if not with_glvnd
egl_lib_version = '1.0.0'
else
egl_lib_name = 'EGL_mesa'
- egl_lib_version = '0'
+ egl_lib_version = '0.0.0'
files_egl += [g_egldispatchstubs_h, g_egldispatchstubs_c]
files_egl += files('main/eglglvnd.c', 'main/egldispatchstubs.c')
install_data(
diff --git a/src/gallium/targets/osmesa/meson.build
b/src/gallium/targets/osmesa/meson.build
index b4b3911ffd..72f77724e4 100644
--- a/src/gallium/targets/osmesa/meson.build
+++ b/src/gallium/targets/osmesa/meson.build
@@ -62,7 +62,7 @@ libosmesa = shared_library(
pkg.generate(
name : 'osmesa',
description : 'Mesa Off-screen Rendering Library',
- version : '8',
+ version : '8.0.0',
libraries : libosmesa,
libraries_private : gl_priv_libs,
)
diff --git a/src/gbm/meson.build b/src/gbm/meson.build
index 437896ef7f..f25f317202 100644
--- a/src/gbm/meson.build
+++ b/src/gbm/meson.build
@@ -57,7 +57,7 @@ libgbm = shared_library(
link_args : [ld_args_gc_sections],
link_with : [links_gbm, libloader, libmesa_util, libxmlconfig],
dependencies : [deps_gbm, dep_dl],
- version : '1.0',
+ version : '1.0.0',
install : true,
)
diff --git a/src/glx/meson.build b/src/glx/meson.build
index 573316c942..01ebc56773 100644
--- a/src/glx/meson.build
+++ b/src/glx/meson.build
@@ -112,7 +112,7 @@ if not with_glvnd
gl_lib_version = '1.2.0'
else
gl_lib_name = 'GLX_mesa'
- gl_lib_version = '0'
+ gl_lib_version = '0.0.0'
files_libglx += files(
'g_glxglvnddispatchfuncs.c',
'g_glxglvnddispatchindices.h',
diff --git a/src/mapi/es1api/meson.build b/src/mapi/es1api/meson.build
index 84a21cd6b7..8d95aee02f 100644
--- a/src/mapi/es1api/meson.build
+++ b/src/mapi/es1api/meson.build
@@ -36,7 +36,7 @@ libglesv1_cm = shared_library(
include_directories : [inc_src, inc_include, inc_mapi],
link_with : libglapi,
dependencies : [dep_thread, dep_libdrm, dep_m, dep_dl],
- version : '1.1',
+ version : '1.1.0',
install : true,
)
diff --git a/src/mapi/es2api/meson.build b/src/mapi/es2api/meson.build
index 3d6888a4b8..7e868d77b3 100644
--- a/src/mapi/es2api/meson.build
+++ b/src/mapi/es2api/meson.build
@@ -36,7 +36,7 @@ libgles2 = shared_library(
include_directories : [inc_src, inc_include, inc_mapi],
link_with : libglapi,
dependencies : [dep_thread, dep_libdrm, dep_m, dep_dl],
- version : '2',
+ version : '2.0.0',
install : true,
)
diff --git a/src/mapi/shared-glapi/meson.build
b/src/mapi/shared-glapi/meson.build
index 0d88de0545..05fd53b7a2 100644
--- a/src/mapi/shared-glapi/meson.build
+++ b/src/mapi/shared-glapi/meson.build
@@ -44,6 +44,7 @@ libglapi = shared_library(
link_args : [ld_args_gc_sections],
include_directories : [inc_src, inc_include, inc_mapi],
dependencies : [dep_thread, dep_selinux],
+ version : '0.0.0',
install : true,
)
diff --git a/src/mesa/drivers/osmesa/meson.build
b/src/mesa/drivers/osmesa/meson.build
index 407cda7e94..a406bb3c21 100644
--- a/src/mesa/drivers/osmesa/meson.build
+++ b/src/mesa/drivers/osmesa/meson.build
@@ -42,7 +42,7 @@ libosmesa = shared_library(
pkg.generate(
name : 'osmesa',
description : 'Mesa Off-screen Rendering Library',
- version : '8',
+ version : '8.0.0',
libraries : libosmesa,
libraries_private : gl_priv_libs,
)
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Mesa (master): meson: drop GLESv1 .so version back to 1.0.0
Module: Mesa Branch: master Commit: cc15460e182148292be877bec5a8a61cec57377d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc15460e182148292be877bec5a8a61cec57377d Author: Eric Engestrom Date: Thu Nov 2 23:38:09 2017 + meson: drop GLESv1 .so version back to 1.0.0 autotools generates libGLESv1_CM.so.1.0.0, so let's make sure meson does the same. Signed-off-by: Eric Engestrom Reviewed-by: Dylan Baker --- src/mapi/es1api/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mapi/es1api/meson.build b/src/mapi/es1api/meson.build index 8d95aee02f..e8b9066a5f 100644 --- a/src/mapi/es1api/meson.build +++ b/src/mapi/es1api/meson.build @@ -36,7 +36,7 @@ libglesv1_cm = shared_library( include_directories : [inc_src, inc_include, inc_mapi], link_with : libglapi, dependencies : [dep_thread, dep_libdrm, dep_m, dep_dl], - version : '1.1.0', + version : '1.0.0', install : true, ) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): meson: only turn on Mesa's DEBUG for buildtype==debug
Module: Mesa
Branch: master
Commit: 1e6f9ea21230229c0256d8189427411298132638
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e6f9ea21230229c0256d8189427411298132638
Author: Eric Engestrom
Date: Mon Nov 6 17:18:06 2017 +
meson: only turn on Mesa's DEBUG for buildtype==debug
As discussed in this thread:
https://lists.freedesktop.org/archives/mesa-dev/2017-November/175104.html
Cc: Dylan Baker
Signed-off-by: Eric Engestrom
Acked-by: Andres Rodriguez
Reviewed-by: Chad Versace
Reviewed-by: Matt Turner
Tested-by: Chad Versace
---
meson.build | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/meson.build b/meson.build
index 6e9a799704..44e062e01e 100644
--- a/meson.build
+++ b/meson.build
@@ -349,8 +349,8 @@ if cc.get_id() == 'gcc' and cc.version().version_compare('<
4.4.6')
error('When using GCC, version 4.4.6 or later is required.')
endif
-# Define DEBUG for debug and debugoptimized builds
-if get_option('buildtype').startswith('debug')
+# Define DEBUG for debug builds only (debugoptimized is not included on this
one)
+if get_option('buildtype') == 'debug'
pre_args += '-DDEBUG'
endif
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Mesa (master): meson: switch default build type to debugoptimized
Module: Mesa Branch: master Commit: d5597f09c6a18a3ed2dd76657dd2e60806a6e4b2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5597f09c6a18a3ed2dd76657dd2e60806a6e4b2 Author: Eric Engestrom Date: Mon Nov 6 16:49:27 2017 + meson: switch default build type to debugoptimized As discussed in this thread: https://lists.freedesktop.org/archives/mesa-dev/2017-November/175104.html Cc: Emil Velikov Cc: Ilia Mirkin Cc: Michel Dänzer Cc: Christian Schmidbauer Cc: Eero Tamminen Cc: Ernst Sjöstrand Signed-off-by: Eric Engestrom Acked-by: Matt Turner Acked-by: Andres Rodriguez Acked-by: Emil Velikov Reviewed-by: Dylan Baker Reviewed-by: Chad Versace Tested-by: Chad Versace --- meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/meson.build b/meson.build index 3ceaec483a..6e9a799704 100644 --- a/meson.build +++ b/meson.build @@ -24,7 +24,7 @@ project( version : '17.3.0-devel', license : 'MIT', meson_version : '>= 0.42', - default_options : ['c_std=c99', 'cpp_std=c++11'] + default_options : ['buildtype=debugoptimized', 'c_std=c99', 'cpp_std=c++11'] ) # Arguments for the preprocessor, put these in a separate array from the C and ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
