date:20171222

Mesa (master): Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+"

2017-12-22 Thread Anuj Phogat

Module: Mesa
Branch: master
Commit: 2d0457203871c843ebfc90fb895b65a9b14cd9bb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d0457203871c843ebfc90fb895b65a9b14cd9bb

Author: Anuj Phogat 
Date:   Fri Dec 22 13:54:08 2017 -0800

Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+"

This reverts commit 9cd60fce9c22737000a8f8dc711141f8a523fe75.
Above commit caused 2000+ piglit tests to assert fail. Disabling
the align1 mode on gen10 for now to avoid failures.

Cc: Matt Turner 
Cc: Rafael Antognolli 
Signed-off-by: Anuj Phogat 
Tested-by: Rafael Antognolli 

---

 src/intel/compiler/brw_fs_generator.cpp | 12 
 1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/src/intel/compiler/brw_fs_generator.cpp 
b/src/intel/compiler/brw_fs_generator.cpp
index 679c1f1916..6a3b2dcf8a 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1758,15 +1758,13 @@ fs_generator::generate_code(const cfg_t *cfg, int 
dispatch_width)
 
   case BRW_OPCODE_MAD:
  assert(devinfo->gen >= 6);
- if (devinfo->gen < 10)
-brw_set_default_access_mode(p, BRW_ALIGN_16);
+brw_set_default_access_mode(p, BRW_ALIGN_16);
  brw_MAD(p, dst, src[0], src[1], src[2]);
 break;
 
   case BRW_OPCODE_LRP:
  assert(devinfo->gen >= 6);
- if (devinfo->gen < 10)
-brw_set_default_access_mode(p, BRW_ALIGN_16);
+brw_set_default_access_mode(p, BRW_ALIGN_16);
  brw_LRP(p, dst, src[0], src[1], src[2]);
 break;
 
@@ -1864,8 +1862,7 @@ fs_generator::generate_code(const cfg_t *cfg, int 
dispatch_width)
 
   case BRW_OPCODE_BFE:
  assert(devinfo->gen >= 7);
- if (devinfo->gen < 10)
-brw_set_default_access_mode(p, BRW_ALIGN_16);
+ brw_set_default_access_mode(p, BRW_ALIGN_16);
  brw_BFE(p, dst, src[0], src[1], src[2]);
  break;
 
@@ -1875,8 +1872,7 @@ fs_generator::generate_code(const cfg_t *cfg, int 
dispatch_width)
  break;
   case BRW_OPCODE_BFI2:
  assert(devinfo->gen >= 7);
- if (devinfo->gen < 10)
-brw_set_default_access_mode(p, BRW_ALIGN_16);
+ brw_set_default_access_mode(p, BRW_ALIGN_16);
  brw_BFI2(p, dst, src[0], src[1], src[2]);
  break;
 

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Mesa (master): docs: add release notes for 17.2.8

2017-12-22 Thread Andres Gomez

Module: Mesa
Branch: master
Commit: d18f00e160d3c2799630b758cfde42c381557d24
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d18f00e160d3c2799630b758cfde42c381557d24

Author: Andres Gomez 
Date:   Fri Dec 22 22:39:47 2017 +0200

docs: add release notes for 17.2.8

Signed-off-by: Andres Gomez 
(cherry picked from commit 3482790712e92d660706952f9ff282d904415941)

---

 docs/relnotes/17.2.8.html | 111 ++
 1 file changed, 111 insertions(+)

diff --git a/docs/relnotes/17.2.8.html b/docs/relnotes/17.2.8.html
new file mode 100644
index 00..a209b352e3
--- /dev/null
+++ b/docs/relnotes/17.2.8.html
@@ -0,0 +1,111 @@
+http://www.w3.org/TR/html4/loose.dtd;>
+
+
+  
+  Mesa Release Notes
+  
+
+
+
+
+  The Mesa 3D Graphics Library
+
+
+
+
+
+Mesa 17.2.8 Release Notes / December 22, 2017
+
+
+Mesa 17.2.8 is a bug fix release which fixes bugs found since the 17.2.7 
release.
+
+
+Mesa 17.2.8 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is only available if requested at context creation
+because compatibility contexts are not supported.
+
+
+
+SHA256 checksums
+
+TBD
+
+
+
+New features
+None
+
+
+Bug fixes
+
+
+
+https://bugs.freedesktop.org/show_bug.cgi?id=102710;>Bug 
102710 - vkCmdBlitImage with arrayLayers  1 fails
+
+https://bugs.freedesktop.org/show_bug.cgi?id=103007;>Bug 
103007 - [OpenGL CTS] [HSW] 
KHR-GL45.gpu_shader_fp64.fp64.max_uniform_components fails
+
+https://bugs.freedesktop.org/show_bug.cgi?id=103544;>Bug 
103544 - Graphical glitches r600 in game this war of mine linux native
+
+https://bugs.freedesktop.org/show_bug.cgi?id=103579;>Bug 
103579 - Vertex shader causes compiler to crash in SPIRV-to-NIR
+
+
+
+
+Changes
+
+Andres Gomez (6):
+
+  cherry-ignore: swr: Fix KNOB_MAX_WORKER_THREADS thread creation 
override.
+  cherry-ignore: added 17.3 nominations.
+  cherry-ignore: radv: port merge tess info from anv
+  cherry-ignore: main: Clear shader program data whenever ProgramBinary is 
called
+  cherry-ignore: r600: set DX10_CLAMP for compute shader too
+  Update version to 17.2.8
+
+
+Bas Nieuwenhuizen (2):
+
+  spirv: Fix loading an entire block at once.
+  radv: Fix multi-layer blits.
+
+
+Brian Paul (2):
+
+  xlib: call _mesa_warning() instead of fprintf()
+  gallium/aux: include nr_samples in util_resource_size() computation
+
+
+Emil Velikov (1):
+
+  docs: add sha256 checksums for 17.2.7
+
+
+Iago Toral Quiroga (1):
+
+  i965/vec4: use a temp register to compute offsets for pull loads
+
+
+Leo Liu (1):
+
+  radeon/vce: move destroy command before feedback command
+
+
+Matt Turner (2):
+
+  util: Assume little endian in the absence of platform-specific 
handling
+  util: Add a SHA1 unit test program
+
+
+Roland Scheidegger (2):
+
+  r600: use min_dx10/max_dx10 instead of min/max
+  r600: use DX10_CLAMP bit in shader setup
+
+
+
+
+
+

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Mesa (master): docs: add sha256 checksums for 17.2.8

2017-12-22 Thread Andres Gomez

Module: Mesa
Branch: master
Commit: 7f4ea112ce9667d7ca38d731f12b37d1f80e7ba2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f4ea112ce9667d7ca38d731f12b37d1f80e7ba2

Author: Andres Gomez 
Date:   Sat Dec 23 00:54:11 2017 +0200

docs: add sha256 checksums for 17.2.8

Signed-off-by: Andres Gomez 
(cherry picked from commit 3281775ab9993d700a0a01a2823b6e7c72fce150)

---

 docs/relnotes/17.2.8.html | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/docs/relnotes/17.2.8.html b/docs/relnotes/17.2.8.html
index a209b352e3..6e53285845 100644
--- a/docs/relnotes/17.2.8.html
+++ b/docs/relnotes/17.2.8.html
@@ -31,7 +31,8 @@ because compatibility contexts are not supported.
 
 SHA256 checksums
 
-TBD
+c715c3a3d6fe26a69c096f573ec416e038a548f0405e3befedd5136517527a84  
mesa-17.2.8.tar.gz
+6e940345cceaadfd805d701ed2b956589fa77fe8c39991da30ed51ea6b9d095f  
mesa-17.2.8.tar.xz
 
 
 

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Mesa (master): docs: update calendar, add news item and link release notes for 17.2.8

2017-12-22 Thread Andres Gomez

Module: Mesa
Branch: master
Commit: 466011e46ad7ce0a8072dc26804ad0f5e4adf878
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=466011e46ad7ce0a8072dc26804ad0f5e4adf878

Author: Andres Gomez 
Date:   Sat Dec 23 00:59:22 2017 +0200

docs: update calendar, add news item and link release notes for 17.2.8

Signed-off-by: Andres Gomez 

---

 docs/index.html| 6 ++
 docs/release-calendar.html | 7 ---
 docs/relnotes.html | 1 +
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/docs/index.html b/docs/index.html
index 5fa047c638..65b216311e 100644
--- a/docs/index.html
+++ b/docs/index.html
@@ -16,6 +16,12 @@
 
 News
 
+December 22, 2017
+
+Mesa 17.2.8 is released.
+This is a bug-fix release.
+
+
 December 21, 2017
 
 Mesa 17.3.1 is released.
diff --git a/docs/release-calendar.html b/docs/release-calendar.html
index fe887e0b21..4ec0120da3 100644
--- a/docs/release-calendar.html
+++ b/docs/release-calendar.html
@@ -39,13 +39,6 @@ if you'd like to nominate a patch in the next stable release.
 Notes
 
 
-17.2
-2017-12-22
-17.2.8
-Andres Gomez
-Final planned release for the 17.2 series
-
-
 17.3
 2017-12-29
 17.3.2
diff --git a/docs/relnotes.html b/docs/relnotes.html
index d92f1349cf..c9f8c31431 100644
--- a/docs/relnotes.html
+++ b/docs/relnotes.html
@@ -21,6 +21,7 @@ The release notes summarize what's new or changed in each 
Mesa release.
 
 
 
+17.2.8 release notes
 17.3.1 release notes
 17.2.7 release notes
 17.3.0 release notes

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Mesa (17.2): docs: add sha256 checksums for 17.2.8

2017-12-22 Thread Andres Gomez

Module: Mesa
Branch: 17.2
Commit: 3281775ab9993d700a0a01a2823b6e7c72fce150
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3281775ab9993d700a0a01a2823b6e7c72fce150

Author: Andres Gomez 
Date:   Sat Dec 23 00:54:11 2017 +0200

docs: add sha256 checksums for 17.2.8

Signed-off-by: Andres Gomez 

---

 docs/relnotes/17.2.8.html | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/docs/relnotes/17.2.8.html b/docs/relnotes/17.2.8.html
index a209b352e3..6e53285845 100644
--- a/docs/relnotes/17.2.8.html
+++ b/docs/relnotes/17.2.8.html
@@ -31,7 +31,8 @@ because compatibility contexts are not supported.
 
 SHA256 checksums
 
-TBD
+c715c3a3d6fe26a69c096f573ec416e038a548f0405e3befedd5136517527a84  
mesa-17.2.8.tar.gz
+6e940345cceaadfd805d701ed2b956589fa77fe8c39991da30ed51ea6b9d095f  
mesa-17.2.8.tar.xz
 
 
 

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Mesa: tag mesa-17.2.8: mesa-17.2.8

2017-12-22 Thread Andres Gomez

Module: Mesa
Branch: refs/tags/mesa-17.2.8
Tag:451a93fa1224ad7bc8bf234fe20c249be51f5db0
URL:
http://cgit.freedesktop.org/mesa/mesa/tag/?id=451a93fa1224ad7bc8bf234fe20c249be51f5db0

Tagger: Andres Gomez 
Date:   Sat Dec 23 00:47:37 2017 +0200

mesa-17.2.8
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Mesa (17.2): Update version to 17.2.8

2017-12-22 Thread Andres Gomez

Module: Mesa
Branch: 17.2
Commit: fb618171b6c4956004e7768b48e3d4e6a3a32a6b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb618171b6c4956004e7768b48e3d4e6a3a32a6b

Author: Andres Gomez 
Date:   Fri Dec 22 22:34:12 2017 +0200

Update version to 17.2.8

Signed-off-by: Andres Gomez 

---

 VERSION | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/VERSION b/VERSION
index 34efe787fe..e048c65cfb 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-17.2.7
+17.2.8

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Mesa (17.2): docs: add release notes for 17.2.8

2017-12-22 Thread Andres Gomez

Module: Mesa
Branch: 17.2
Commit: 3482790712e92d660706952f9ff282d904415941
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3482790712e92d660706952f9ff282d904415941

Author: Andres Gomez 
Date:   Fri Dec 22 22:39:47 2017 +0200

docs: add release notes for 17.2.8

Signed-off-by: Andres Gomez 

---

 docs/relnotes/17.2.8.html | 111 ++
 1 file changed, 111 insertions(+)

diff --git a/docs/relnotes/17.2.8.html b/docs/relnotes/17.2.8.html
new file mode 100644
index 00..a209b352e3
--- /dev/null
+++ b/docs/relnotes/17.2.8.html
@@ -0,0 +1,111 @@
+http://www.w3.org/TR/html4/loose.dtd;>
+
+
+  
+  Mesa Release Notes
+  
+
+
+
+
+  The Mesa 3D Graphics Library
+
+
+
+
+
+Mesa 17.2.8 Release Notes / December 22, 2017
+
+
+Mesa 17.2.8 is a bug fix release which fixes bugs found since the 17.2.7 
release.
+
+
+Mesa 17.2.8 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is only available if requested at context creation
+because compatibility contexts are not supported.
+
+
+
+SHA256 checksums
+
+TBD
+
+
+
+New features
+None
+
+
+Bug fixes
+
+
+
+https://bugs.freedesktop.org/show_bug.cgi?id=102710;>Bug 
102710 - vkCmdBlitImage with arrayLayers  1 fails
+
+https://bugs.freedesktop.org/show_bug.cgi?id=103007;>Bug 
103007 - [OpenGL CTS] [HSW] 
KHR-GL45.gpu_shader_fp64.fp64.max_uniform_components fails
+
+https://bugs.freedesktop.org/show_bug.cgi?id=103544;>Bug 
103544 - Graphical glitches r600 in game this war of mine linux native
+
+https://bugs.freedesktop.org/show_bug.cgi?id=103579;>Bug 
103579 - Vertex shader causes compiler to crash in SPIRV-to-NIR
+
+
+
+
+Changes
+
+Andres Gomez (6):
+
+  cherry-ignore: swr: Fix KNOB_MAX_WORKER_THREADS thread creation 
override.
+  cherry-ignore: added 17.3 nominations.
+  cherry-ignore: radv: port merge tess info from anv
+  cherry-ignore: main: Clear shader program data whenever ProgramBinary is 
called
+  cherry-ignore: r600: set DX10_CLAMP for compute shader too
+  Update version to 17.2.8
+
+
+Bas Nieuwenhuizen (2):
+
+  spirv: Fix loading an entire block at once.
+  radv: Fix multi-layer blits.
+
+
+Brian Paul (2):
+
+  xlib: call _mesa_warning() instead of fprintf()
+  gallium/aux: include nr_samples in util_resource_size() computation
+
+
+Emil Velikov (1):
+
+  docs: add sha256 checksums for 17.2.7
+
+
+Iago Toral Quiroga (1):
+
+  i965/vec4: use a temp register to compute offsets for pull loads
+
+
+Leo Liu (1):
+
+  radeon/vce: move destroy command before feedback command
+
+
+Matt Turner (2):
+
+  util: Assume little endian in the absence of platform-specific 
handling
+  util: Add a SHA1 unit test program
+
+
+Roland Scheidegger (2):
+
+  r600: use min_dx10/max_dx10 instead of min/max
+  r600: use DX10_CLAMP bit in shader setup
+
+
+
+
+
+

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Mesa (master): freedreno: set missing internal_format when importing texture

2017-12-22 Thread Ilia Mirkin

Module: Mesa
Branch: master
Commit: 0dbdb070705ea063430ed4ff1fbdbc87d86165ea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0dbdb070705ea063430ed4ff1fbdbc87d86165ea

Author: Ilia Mirkin 
Date:   Fri Dec 22 00:27:50 2017 -0500

freedreno: set missing internal_format when importing texture

Fixes running piglits without -fbo. Probably lots of other stuff too.

Signed-off-by: Ilia Mirkin 
Reviewed-by: Rob Clark 

---

 src/gallium/drivers/freedreno/freedreno_resource.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/drivers/freedreno/freedreno_resource.c 
b/src/gallium/drivers/freedreno/freedreno_resource.c
index cb13f671c4..daa162c166 100644
--- a/src/gallium/drivers/freedreno/freedreno_resource.c
+++ b/src/gallium/drivers/freedreno/freedreno_resource.c
@@ -832,6 +832,7 @@ fd_resource_from_handle(struct pipe_screen *pscreen,
if (!rsc->bo)
goto fail;
 
+   rsc->internal_format = tmpl->format;
rsc->cpp = util_format_get_blocksize(tmpl->format);
slice->pitch = handle->stride / rsc->cpp;
slice->offset = handle->offset;

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Mesa (master): radv: reduce the number of small surfaces that need CMASK or DCC

2017-12-22 Thread Samuel Pitoiset

Module: Mesa
Branch: master
Commit: 79c495aa377c486b220da538558177208999283d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=79c495aa377c486b220da538558177208999283d

Author: Samuel Pitoiset 
Date:   Thu Dec 21 17:45:23 2017 +0100

radv: reduce the number of small surfaces that need CMASK or DCC

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/amd/vulkan/radv_image.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index efd17e4889..15410f140e 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -813,7 +813,7 @@ static inline bool
 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
 {
if (image->info.samples <= 1 &&
-   image->info.width <= 512 && image->info.height <= 512) {
+   image->info.width * image->info.height <= 512 * 512) {
/* Do not enable CMASK or DCC for small surfaces where the cost
 * of the eliminate pass can be higher than the benefit of fast
 * clear. RadeonSI does this, but the image threshold is

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Mesa (master): amd/common: pass the family to ac_llvm_context_init()

2017-12-22 Thread Samuel Pitoiset

Module: Mesa
Branch: master
Commit: 03ef2641469286423e587d17b2952713ffe48585
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=03ef2641469286423e587d17b2952713ffe48585

Author: Samuel Pitoiset 
Date:   Thu Dec 21 17:53:14 2017 +0100

amd/common: pass the family to ac_llvm_context_init()

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/amd/common/ac_llvm_build.c  | 3 ++-
 src/amd/common/ac_llvm_build.h  | 3 ++-
 src/amd/common/ac_nir_to_llvm.c | 6 --
 src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c | 3 ++-
 4 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index b407678c3b..c74a47a799 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -47,11 +47,12 @@
  */
 void
 ac_llvm_context_init(struct ac_llvm_context *ctx, LLVMContextRef context,
-enum chip_class chip_class)
+enum chip_class chip_class, enum radeon_family family)
 {
LLVMValueRef args[1];
 
ctx->chip_class = chip_class;
+   ctx->family = family;
 
ctx->context = context;
ctx->module = NULL;
diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index 4a570c41bc..6427d5315a 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -74,13 +74,14 @@ struct ac_llvm_context {
LLVMValueRef empty_md;
 
enum chip_class chip_class;
+   enum radeon_family family;
 
LLVMValueRef lds;
 };
 
 void
 ac_llvm_context_init(struct ac_llvm_context *ctx, LLVMContextRef context,
-enum chip_class chip_class);
+enum chip_class chip_class, enum radeon_family family);
 
 unsigned ac_get_type_size(LLVMTypeRef type);
 
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index cbc6d1b61b..6586537105 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -6561,7 +6561,8 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
ctx.context = LLVMContextCreate();
ctx.module = LLVMModuleCreateWithNameInContext("shader", ctx.context);
 
-   ac_llvm_context_init(, ctx.context, options->chip_class);
+   ac_llvm_context_init(, ctx.context, options->chip_class,
+options->family);
ctx.ac.module = ctx.module;
LLVMSetTarget(ctx.module, options->supports_spill ? 
"amdgcn-mesa-mesa3d" : "amdgcn--");
 
@@ -6943,7 +6944,8 @@ void ac_create_gs_copy_shader(LLVMTargetMachineRef tm,
ctx.options = options;
ctx.shader_info = shader_info;
 
-   ac_llvm_context_init(, ctx.context, options->chip_class);
+   ac_llvm_context_init(, ctx.context, options->chip_class,
+options->family);
ctx.ac.module = ctx.module;
 
ctx.is_gs_copy_shader = true;
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c 
b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
index 0843b3c63c..2ca036e67d 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
@@ -1167,7 +1167,8 @@ void si_llvm_context_init(struct si_shader_context *ctx,
ctx->gallivm.builder = lp_create_builder(ctx->gallivm.context,
 float_mode);
 
-   ac_llvm_context_init(>ac, ctx->gallivm.context, 
sscreen->info.chip_class);
+   ac_llvm_context_init(>ac, ctx->gallivm.context,
+sscreen->info.chip_class, sscreen->info.family);
ctx->ac.module = ctx->gallivm.module;
ctx->ac.builder = ctx->gallivm.builder;
 

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Mesa (master): amd/common: add ac_export_mrt_z() helper

2017-12-22 Thread Samuel Pitoiset

Module: Mesa
Branch: master
Commit: 38f9b87af24762d932891e67ff25db97cdbde6b5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=38f9b87af24762d932891e67ff25db97cdbde6b5

Author: Samuel Pitoiset 
Date:   Thu Dec 21 17:53:15 2017 +0100

amd/common: add ac_export_mrt_z() helper

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/amd/common/ac_nir_to_llvm.c  | 64 +++-
 src/amd/common/ac_shader_util.c  | 72 
 src/amd/common/ac_shader_util.h  |  6 +++
 src/gallium/drivers/radeonsi/si_shader.c | 61 +--
 4 files changed, 84 insertions(+), 119 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 6586537105..87f1918c5e 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -6200,67 +6200,13 @@ si_export_mrt_color(struct nir_to_llvm_context *ctx,
 }
 
 static void
-si_export_mrt_z(struct nir_to_llvm_context *ctx,
-   LLVMValueRef depth, LLVMValueRef stencil,
-   LLVMValueRef samplemask)
+radv_export_mrt_z(struct nir_to_llvm_context *ctx,
+ LLVMValueRef depth, LLVMValueRef stencil,
+ LLVMValueRef samplemask)
 {
struct ac_export_args args;
 
-   args.enabled_channels = 0;
-   args.valid_mask = 1;
-   args.done = 1;
-   args.target = V_008DFC_SQ_EXP_MRTZ;
-   args.compr = false;
-
-   args.out[0] = LLVMGetUndef(ctx->ac.f32); /* R, depth */
-   args.out[1] = LLVMGetUndef(ctx->ac.f32); /* G, stencil test val[0:7], 
stencil op val[8:15] */
-   args.out[2] = LLVMGetUndef(ctx->ac.f32); /* B, sample mask */
-   args.out[3] = LLVMGetUndef(ctx->ac.f32); /* A, alpha to mask */
-
-   unsigned format = ac_get_spi_shader_z_format(depth != NULL,
-stencil != NULL,
-samplemask != NULL);
-
-   if (format == V_028710_SPI_SHADER_UINT16_ABGR) {
-   assert(!depth);
-   args.compr = 1; /* COMPR flag */
-
-   if (stencil) {
-   /* Stencil should be in X[23:16]. */
-   stencil = ac_to_integer(>ac, stencil);
-   stencil = LLVMBuildShl(ctx->builder, stencil,
-  LLVMConstInt(ctx->ac.i32, 16, 
0), "");
-   args.out[0] = ac_to_float(>ac, stencil);
-   args.enabled_channels |= 0x3;
-   }
-   if (samplemask) {
-   /* SampleMask should be in Y[15:0]. */
-   args.out[1] = samplemask;
-   args.enabled_channels |= 0xc;
-   }
-   } else {
-   if (depth) {
-   args.out[0] = depth;
-   args.enabled_channels |= 0x1;
-   }
-
-   if (stencil) {
-   args.out[1] = stencil;
-   args.enabled_channels |= 0x2;
-   }
-
-   if (samplemask) {
-   args.out[2] = samplemask;
-   args.enabled_channels |= 0x4;
-   }
-   }
-
-   /* SI (except OLAND and HAINAN) has a bug that it only looks
-* at the X writemask component. */
-   if (ctx->options->chip_class == SI &&
-   ctx->options->family != CHIP_OLAND &&
-   ctx->options->family != CHIP_HAINAN)
-   args.enabled_channels |= 0x1;
+   ac_export_mrt_z(>ac, depth, stencil, samplemask, );
 
ac_build_export(>ac, );
 }
@@ -6308,7 +6254,7 @@ handle_fs_outputs_post(struct nir_to_llvm_context *ctx)
for (unsigned i = 0; i < index; i++)
ac_build_export(>ac, _args[i]);
if (depth || stencil || samplemask)
-   si_export_mrt_z(ctx, depth, stencil, samplemask);
+   radv_export_mrt_z(ctx, depth, stencil, samplemask);
else if (!index) {
si_export_mrt_color(ctx, NULL, V_008DFC_SQ_EXP_NULL, true, 
_args[0]);
ac_build_export(>ac, _args[0]);
diff --git a/src/amd/common/ac_shader_util.c b/src/amd/common/ac_shader_util.c
index 12f86dc677..531395f4f6 100644
--- a/src/amd/common/ac_shader_util.c
+++ b/src/amd/common/ac_shader_util.c
@@ -22,7 +22,10 @@
  */
 
 #include 
+#include 
+#include 
 
+#include "ac_nir_to_llvm.h"
 #include "ac_shader_util.h"
 #include "sid.h"
 
@@ -105,3 +108,72 @@ ac_vgt_gs_mode(unsigned gs_max_vert_out, enum chip_class 
chip_class)
   S_028A40_GS_WRITE_OPTIMIZE(1) |
   S_028A40_ONCHIP(chip_class >= GFX9 ? 1 : 0);
 }
+
+void
+ac_export_mrt_z(struct ac_llvm_context *ctx, LLVMValueRef depth,
+   LLVMValueRef stencil, LLVMValueRef samplemask,
+   struct ac_export_args

Mesa (master): Revert "i965/fs: Use align1 mode on ternary instructions on Gen10+"

Mesa (master): docs: add release notes for 17.2.8

Mesa (master): docs: add sha256 checksums for 17.2.8

Mesa (master): docs: update calendar, add news item and link release notes for 17.2.8

Mesa (17.2): docs: add sha256 checksums for 17.2.8

Mesa: tag mesa-17.2.8: mesa-17.2.8

Mesa (17.2): Update version to 17.2.8

Mesa (17.2): docs: add release notes for 17.2.8

Mesa (master): freedreno: set missing internal_format when importing texture

Mesa (master): radv: reduce the number of small surfaces that need CMASK or DCC

Mesa (master): amd/common: pass the family to ac_llvm_context_init()

Mesa (master): amd/common: add ac_export_mrt_z() helper

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