Mesa (master): radv: Generate VK_ANDROID_native_buffer.
Module: Mesa
Branch: master
Commit: e344cd81783255eb5de762e5bd56bd4dfe8ae0c2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e344cd81783255eb5de762e5bd56bd4dfe8ae0c2
Author: Bas Nieuwenhuizen
Date: Thu Jan 4 18:38:30 2018 +0100
radv: Generate VK_ANDROID_native_buffer.
Reviewed-by: Dave Airlie
---
src/amd/vulkan/Makefile.am | 6 +-
src/amd/vulkan/radv_entrypoints_gen.py | 4 +++-
src/amd/vulkan/radv_extensions.py | 1 +
3 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
index 6b352aebf9..e1a04e8c7f 100644
--- a/src/amd/vulkan/Makefile.am
+++ b/src/amd/vulkan/Makefile.am
@@ -106,11 +106,14 @@ nodist_EXTRA_libvulkan_radeon_la_SOURCES = dummy.cpp
libvulkan_radeon_la_SOURCES = $(VULKAN_GEM_FILES)
vulkan_api_xml = $(top_srcdir)/src/vulkan/registry/vk.xml
+vk_android_native_buffer_xml =
$(top_srcdir)/src/vulkan/registry/vk_android_native_buffer.xml
radv_entrypoints.c: radv_entrypoints_gen.py radv_extensions.py
$(vulkan_api_xml)
$(MKDIR_GEN)
$(AM_V_GEN)$(PYTHON2) $(srcdir)/radv_entrypoints_gen.py \
- --xml $(vulkan_api_xml) --outdir $(builddir)
+ --xml $(vulkan_api_xml) \
+ --xml $(vk_android_native_buffer_xml) \
+ --outdir $(builddir)
radv_entrypoints.h: radv_entrypoints.c
radv_extensions.c: radv_extensions.py \
@@ -118,6 +121,7 @@ radv_extensions.c: radv_extensions.py \
$(MKDIR_GEN)
$(AM_V_GEN)$(PYTHON2) $(srcdir)/radv_extensions.py \
--xml $(vulkan_api_xml) \
+ --xml $(vk_android_native_buffer_xml) \
--out $@
vk_format_table.c: vk_format_table.py \
diff --git a/src/amd/vulkan/radv_entrypoints_gen.py
b/src/amd/vulkan/radv_entrypoints_gen.py
index f8f99d00b7..c981c0be13 100644
--- a/src/amd/vulkan/radv_entrypoints_gen.py
+++ b/src/amd/vulkan/radv_entrypoints_gen.py
@@ -237,7 +237,9 @@ def get_entrypoints(doc, entrypoints_to_defines,
start_index):
if extension.attrib['name'] not in supported:
continue
-assert extension.attrib['supported'] == 'vulkan'
+if extension.attrib['supported'] != 'vulkan':
+continue
+
for command in extension.findall('./require/command'):
enabled_commands.add(command.attrib['name'])
diff --git a/src/amd/vulkan/radv_extensions.py
b/src/amd/vulkan/radv_extensions.py
index f11540a5c9..ab34c01cb6 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -50,6 +50,7 @@ class Extension:
# the those extension strings, then tests dEQP-VK.api.info.instance.extensions
# and dEQP-VK.api.info.device fail due to the duplicated strings.
EXTENSIONS = [
+Extension('VK_ANDROID_native_buffer', 5, 'ANDROID &&
device->rad_info.has_syncobj_wait_for_submit'),
Extension('VK_KHR_bind_memory2', 1, True),
Extension('VK_KHR_dedicated_allocation', 1, True),
Extension('VK_KHR_descriptor_update_template',1, True),
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Mesa (master): ac/nir: Use correct 32-bit component writemask for 64-bit SSBO stores.
Module: Mesa
Branch: master
Commit: f4211e6f9314b225cdcdc799e0c123b3dceee9eb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f4211e6f9314b225cdcdc799e0c123b3dceee9eb
Author: Bas Nieuwenhuizen
Date: Wed Jan 17 14:23:17 2018 +0100
ac/nir: Use correct 32-bit component writemask for 64-bit SSBO stores.
Fixes: 91074bb11bda "radv/ac: Implement Float64 SSBO stores."
Tested-by: Timothy Arceri
Acked-by: Timothy Arceri
---
src/amd/common/ac_nir_to_llvm.c | 22 +-
1 file changed, 13 insertions(+), 9 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 0bebfea972..90cb4a6eea 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2434,6 +2434,16 @@ static LLVMValueRef visit_get_buffer_size(struct
ac_nir_context *ctx,
return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index,
false), false);
}
+
+static uint32_t widen_mask(uint32_t mask, unsigned multiplier)
+{
+ uint32_t new_mask = 0;
+ for(unsigned i = 0; i < 32 && (1u << i) <= mask; ++i)
+ if (mask & (1u << i))
+ new_mask |= ((1u << multiplier) - 1u) << (i *
multiplier);
+ return new_mask;
+}
+
static void visit_store_ssbo(struct ac_nir_context *ctx,
nir_intrinsic_instr *instr)
{
@@ -2455,6 +2465,8 @@ static void visit_store_ssbo(struct ac_nir_context *ctx,
if (components_32bit > 1)
data_type = LLVMVectorType(ctx->ac.f32, components_32bit);
+ writemask = widen_mask(writemask, elem_size_mult);
+
base_data = ac_to_float(&ctx->ac, src_data);
base_data = trim_vector(&ctx->ac, base_data, instr->num_components);
base_data = LLVMBuildBitCast(ctx->ac.builder, base_data,
@@ -2474,9 +2486,6 @@ static void visit_store_ssbo(struct ac_nir_context *ctx,
count = 2;
}
- start *= elem_size_mult;
- count *= elem_size_mult;
-
if (count > 4) {
writemask |= ((1u << (count - 4)) - 1u) << (start + 4);
count = 4;
@@ -3266,17 +3275,12 @@ visit_store_var(struct ac_nir_context *ctx,
NULL, NULL, &const_index, &indir_index);
if (get_elem_bits(&ctx->ac, LLVMTypeOf(src)) == 64) {
- int old_writemask = writemask;
src = LLVMBuildBitCast(ctx->ac.builder, src,
LLVMVectorType(ctx->ac.f32,
ac_get_llvm_num_components(src) * 2),
"");
- writemask = 0;
- for (unsigned chan = 0; chan < 4; chan++) {
- if (old_writemask & (1 << chan))
- writemask |= 3u << (2 * chan);
- }
+ writemask = widen_mask(writemask, 2);
}
switch (instr->variables[0]->var->data.mode) {
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Mesa (master): ac/nir: Fix vector extraction if source vector has >4 elements.
Module: Mesa
Branch: master
Commit: 32170d87e3b7bee37234b44ff787ff60fcd3a9aa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=32170d87e3b7bee37234b44ff787ff60fcd3a9aa
Author: Bas Nieuwenhuizen
Date: Wed Jan 17 14:33:39 2018 +0100
ac/nir: Fix vector extraction if source vector has >4 elements.
v2: Add forgotten argument and start offset.
Fixes: 91074bb11bda "radv/ac: Implement Float64 SSBO stores."
Tested-by: Timothy Arceri
Acked-by: Timothy Arceri
---
src/amd/common/ac_nir_to_llvm.c | 48 +++--
1 file changed, 32 insertions(+), 16 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 90cb4a6eea..2aef51be85 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2444,6 +2444,36 @@ static uint32_t widen_mask(uint32_t mask, unsigned
multiplier)
return new_mask;
}
+static LLVMValueRef extract_vector_range(struct ac_llvm_context *ctx,
LLVMValueRef src,
+ unsigned start, unsigned count)
+{
+ LLVMTypeRef type = LLVMTypeOf(src);
+
+ if (LLVMGetTypeKind(type) != LLVMVectorTypeKind) {
+ assert(start == 0);
+ assert(count == 1);
+ return src;
+ }
+
+ unsigned src_elements = LLVMGetVectorSize(type);
+ assert(start < src_elements);
+ assert(start + count <= src_elements);
+
+ if (start == 0 && count == src_elements)
+ return src;
+
+ if (count == 1)
+ return LLVMBuildExtractElement(ctx->builder, src,
LLVMConstInt(ctx->i32, start, false), "");
+
+ assert(count <= 8);
+ LLVMValueRef indices[8];
+ for (unsigned i = 0; i < count; ++i)
+ indices[i] = LLVMConstInt(ctx->i32, start + i, false);
+
+ LLVMValueRef swizzle = LLVMConstVector(indices, count);
+ return LLVMBuildShuffleVector(ctx->builder, src, src, swizzle, "");
+}
+
static void visit_store_ssbo(struct ac_nir_context *ctx,
nir_intrinsic_instr *instr)
{
@@ -2476,7 +2506,7 @@ static void visit_store_ssbo(struct ac_nir_context *ctx,
int start, count;
LLVMValueRef data;
LLVMValueRef offset;
- LLVMValueRef tmp;
+
u_bit_scan_consecutive_range(&writemask, &start, &count);
/* Due to an LLVM limitation, split 3-element writes
@@ -2493,28 +2523,14 @@ static void visit_store_ssbo(struct ac_nir_context *ctx,
if (count == 4) {
store_name = "llvm.amdgcn.buffer.store.v4f32";
- data = base_data;
} else if (count == 2) {
- tmp = LLVMBuildExtractElement(ctx->ac.builder,
- base_data,
LLVMConstInt(ctx->ac.i32, start, false), "");
- data = LLVMBuildInsertElement(ctx->ac.builder,
LLVMGetUndef(ctx->ac.v2f32), tmp,
- ctx->ac.i32_0, "");
-
- tmp = LLVMBuildExtractElement(ctx->ac.builder,
- base_data,
LLVMConstInt(ctx->ac.i32, start + 1, false), "");
- data = LLVMBuildInsertElement(ctx->ac.builder, data,
tmp,
- ctx->ac.i32_1, "");
store_name = "llvm.amdgcn.buffer.store.v2f32";
} else {
assert(count == 1);
- if (ac_get_llvm_num_components(base_data) > 1)
- data = LLVMBuildExtractElement(ctx->ac.builder,
base_data,
-
LLVMConstInt(ctx->ac.i32, start, false), "");
- else
- data = base_data;
store_name = "llvm.amdgcn.buffer.store.f32";
}
+ data = extract_vector_range(&ctx->ac, base_data, start, count);
offset = base_offset;
if (start != 0) {
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Mesa (master): radv: Add create image flag to not use DCC/CMASK.
Module: Mesa
Branch: master
Commit: a3e241ed07feae592d1fd83db388252816a32849
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a3e241ed07feae592d1fd83db388252816a32849
Author: Bas Nieuwenhuizen
Date: Thu Jan 4 18:38:31 2018 +0100
radv: Add create image flag to not use DCC/CMASK.
If we import an image, we might not have space in the
buffer for CMASK, even though it is compatible.
Reviewed-by: Dave Airlie
---
src/amd/vulkan/radv_image.c | 43 ---
src/amd/vulkan/radv_private.h | 1 +
2 files changed, 25 insertions(+), 19 deletions(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 316ce2e2ba..d69ae8af48 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -923,29 +923,34 @@ radv_image_create(VkDevice _device,
image->size = image->surface.surf_size;
image->alignment = image->surface.surf_alignment;
- /* Try to enable DCC first. */
- if (radv_image_can_enable_dcc(image)) {
- radv_image_alloc_dcc(image);
- } else {
- /* When DCC cannot be enabled, try CMASK. */
- image->surface.dcc_size = 0;
- if (radv_image_can_enable_cmask(image)) {
- radv_image_alloc_cmask(device, image);
+ if (!create_info->no_metadata_planes) {
+ /* Try to enable DCC first. */
+ if (radv_image_can_enable_dcc(image)) {
+ radv_image_alloc_dcc(image);
+ } else {
+ /* When DCC cannot be enabled, try CMASK. */
+ image->surface.dcc_size = 0;
+ if (radv_image_can_enable_cmask(image)) {
+ radv_image_alloc_cmask(device, image);
+ }
}
- }
- /* Try to enable FMASK for multisampled images. */
- if (radv_image_can_enable_fmask(image)) {
- radv_image_alloc_fmask(device, image);
- } else {
- /* Otherwise, try to enable HTILE for depth surfaces. */
- if (radv_image_can_enable_htile(image) &&
- !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
- radv_image_alloc_htile(image);
- image->tc_compatible_htile = image->surface.flags &
RADEON_SURF_TC_COMPATIBLE_HTILE;
+ /* Try to enable FMASK for multisampled images. */
+ if (radv_image_can_enable_fmask(image)) {
+ radv_image_alloc_fmask(device, image);
} else {
- image->surface.htile_size = 0;
+ /* Otherwise, try to enable HTILE for depth surfaces. */
+ if (radv_image_can_enable_htile(image) &&
+ !(device->instance->debug_flags &
RADV_DEBUG_NO_HIZ)) {
+ radv_image_alloc_htile(image);
+ image->tc_compatible_htile =
image->surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
+ } else {
+ image->surface.htile_size = 0;
+ }
}
+ } else {
+ image->surface.dcc_size = 0;
+ image->surface.htile_size = 0;
}
if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index d51a669b38..c8a673756f 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1460,6 +1460,7 @@ struct radv_image_view {
struct radv_image_create_info {
const VkImageCreateInfo *vk_info;
bool scanout;
+ bool no_metadata_planes;
};
VkResult radv_image_create(VkDevice _device,
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Mesa (master): ac/nir: Fix TCS output LDS offsets.
Module: Mesa
Branch: master
Commit: 4a9fd90e1e7ebbb8015d964474d476093ed9c3a4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a9fd90e1e7ebbb8015d964474d476093ed9c3a4
Author: Bas Nieuwenhuizen
Date: Fri Jan 19 01:20:12 2018 +0100
ac/nir: Fix TCS output LDS offsets.
When a channel was not set we also did not increase the LDS address,
while that obviously should happen.
The output loading code was inadvertently fixed which resulted in a
mismatch causing the SaschaWillems tessellation demo to result
in corrupt rendering.
Fixes: 7898eb9a60 "ac: rework load_tcs_{inputs,outputs}"
Reviewed-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index cd400376a0..0bebfea972 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2968,16 +2968,17 @@ store_tcs_output(struct ac_shader_abi *abi,
continue;
LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan -
component);
- if (store_lds || is_tess_factor)
- ac_lds_store(&ctx->ac, dw_addr, value);
+ if (store_lds || is_tess_factor) {
+ LLVMValueRef dw_addr_chan =
+ LLVMBuildAdd(ctx->builder, dw_addr,
+
LLVMConstInt(ctx->ac.i32, chan, false), "");
+ ac_lds_store(&ctx->ac, dw_addr_chan, value);
+ }
if (!is_tess_factor && writemask != 0xF)
ac_build_buffer_store_dword(&ctx->ac,
ctx->hs_ring_tess_offchip, value, 1,
buf_addr, ctx->oc_lds,
4 * (base + chan), 1, 0,
true, false);
-
- dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
- ctx->ac.i32_1, "");
}
if (writemask == 0xF) {
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Mesa (master): radv: Implement VK_ANDROID_native_buffer.
Module: Mesa
Branch: master
Commit: b1444c9ccb06661d932969302d19166df442818c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b1444c9ccb06661d932969302d19166df442818c
Author: Bas Nieuwenhuizen
Date: Thu Jan 4 18:38:32 2018 +0100
radv: Implement VK_ANDROID_native_buffer.
Passes
dEQP-VK.api.smoke.*
dEQP-VK.wsi.android.*
with android-cts-7.1_r12 .
Unlike the initial anv implementation this does
use syncobjs instead of waiting on the CPU.
This is missing meson build coverage for now.
One possible todo is that linux 4.15 now has a
sycall that allows us to export amdgpu fence to
a sync_file, which allows us not to force all
fences and semaphores to use syncobjs. However,
I had trouble with my kernel crashing regularly
with NULL pointers, and I'm not sure how beneficial
it is in the first place given that intel uses
syncobjs for all fences if available.
Reviewed-by: Dave Airlie
---
src/amd/vulkan/Makefile.am | 7 +
src/amd/vulkan/Makefile.sources | 3 +
src/amd/vulkan/meson.build | 4 +-
src/amd/vulkan/radv_android.c | 366
src/amd/vulkan/radv_device.c| 7 +-
src/amd/vulkan/radv_image.c | 12 ++
src/amd/vulkan/radv_private.h | 12 ++
7 files changed, 407 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
index e1a04e8c7f..a4e23cd28e 100644
--- a/src/amd/vulkan/Makefile.am
+++ b/src/amd/vulkan/Makefile.am
@@ -99,6 +99,13 @@ VULKAN_LIB_DEPS += \
$(WAYLAND_CLIENT_LIBS)
endif
+if HAVE_PLATFORM_ANDROID
+AM_CPPFLAGS += $(ANDROID_CPPFLAGS)
+AM_CFLAGS += $(ANDROID_CFLAGS)
+VULKAN_LIB_DEPS += $(ANDROID_LIBS)
+VULKAN_SOURCES += $(VULKAN_ANDROID_FILES)
+endif
+
noinst_LTLIBRARIES = libvulkan_common.la
libvulkan_common_la_SOURCES = $(VULKAN_SOURCES)
diff --git a/src/amd/vulkan/Makefile.sources b/src/amd/vulkan/Makefile.sources
index c9d172c3b1..a510d88d96 100644
--- a/src/amd/vulkan/Makefile.sources
+++ b/src/amd/vulkan/Makefile.sources
@@ -69,6 +69,9 @@ VULKAN_FILES := \
vk_format.h \
$(RADV_WS_AMDGPU_FILES)
+VULKAN_ANDROID_FILES := \
+ radv_android.c
+
VULKAN_WSI_WAYLAND_FILES := \
radv_wsi_wayland.c
diff --git a/src/amd/vulkan/meson.build b/src/amd/vulkan/meson.build
index 74f6399ed7..0a7b7c0bf3 100644
--- a/src/amd/vulkan/meson.build
+++ b/src/amd/vulkan/meson.build
@@ -31,10 +31,10 @@ radv_entrypoints = custom_target(
radv_extensions_c = custom_target(
'radv_extensions.c',
- input : ['radv_extensions.py', vk_api_xml],
+ input : ['radv_extensions.py', vk_api_xml, vk_android_native_buffer_xml],
output : ['radv_extensions.c'],
command : [
-prog_python2, '@INPUT0@', '--xml', '@INPUT1@', '--out', '@OUTPUT@',
+prog_python2, '@INPUT0@', '--xml', '@INPUT1@', '--xml', '@INPUT2@',
'--out', '@OUTPUT@',
],
)
diff --git a/src/amd/vulkan/radv_android.c b/src/amd/vulkan/radv_android.c
new file mode 100644
index 00..09da601dac
--- /dev/null
+++ b/src/amd/vulkan/radv_android.c
@@ -0,0 +1,366 @@
+/*
+ * Copyright © 2017, Google Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include
+#include
+#include
+#include
+#include
+#include
+
+#include "radv_private.h"
+
+static int radv_hal_open(const struct hw_module_t* mod, const char* id, struct
hw_device_t** dev);
+static int radv_hal_close(struct hw_device_t *dev);
+
+static void UNUSED
+static_asserts(void)
+{
+ STATIC_ASSERT(HWVULKAN_DISPATCH_MAGIC == ICD_LOADER_MAGIC);
+}
+
+PUBLIC struct hwvulkan_module_t HAL_MODULE_INFO_SYM = {
+ .common = {
+ .tag = HARDWARE_MODULE_TAG,
+ .module_api_version = HWVULKAN_MODULE_API_VERSION_0_1,
+ .hal_api_version = HARDWARE_MAKE_API_VERSION(1, 0),
+ .id = HWVULKAN_HARDWARE_MODULE_ID,
+ .name = "AMD Vulkan HAL",
+ .author = "Google",
+
Mesa (master): gallivm: support avx512 (16x32) in interleave2_half
Module: Mesa
Branch: master
Commit: f76ca91ae07040fe661ecb215b2e6bf43dc16283
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f76ca91ae07040fe661ecb215b2e6bf43dc16283
Author: George Kyriazis
Date: Tue Jan 16 18:06:34 2018 -0600
gallivm: support avx512 (16x32) in interleave2_half
lp_build_interleave2_half was not doing the right thing for avx512-style
16-wide loads.
This path is hit in the swr driver with a 16-wide vertex shader. It is
called from lp_build_transpose_aos, when doing texel fetches and the
fetched data needs to be transposed to one component per output register.
Special-case the post-load swizzle operations for avx512 16x32 (16-wide
32-bit values) so that we move the xyzw components correctly to the outputs.
Reviewed-by: Roland Scheidegger
---
src/gallium/auxiliary/gallivm/lp_bld_pack.c | 40 +++--
1 file changed, 38 insertions(+), 2 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_pack.c
b/src/gallium/auxiliary/gallivm/lp_bld_pack.c
index e8d4fcdf2f..7879826422 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_pack.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_pack.c
@@ -129,6 +129,31 @@ lp_build_const_unpack_shuffle_half(struct gallivm_state
*gallivm,
}
/**
+ * Similar to lp_build_const_unpack_shuffle_half, but for AVX512
+ * See comment above lp_build_interleave2_half for more details.
+ */
+static LLVMValueRef
+lp_build_const_unpack_shuffle_16wide(struct gallivm_state *gallivm,
+ unsigned lo_hi)
+{
+ LLVMValueRef elems[LP_MAX_VECTOR_LENGTH];
+ unsigned i, j;
+
+ assert(lo_hi < 2);
+
+ // for the following lo_hi setting, convert 0 -> f to:
+ // 0: 0 16 4 20 8 24 12 28 1 17 5 21 9 25 13 29
+ // 1: 2 18 6 22 10 26 14 30 3 19 7 23 11 27 15 31
+ for (i = 0; i < 16; i++) {
+ j = ((i&0x06)<<1) + ((i&1)<<4) + (i>>3) + (lo_hi<<1);
+
+ elems[i] = lp_build_const_int32(gallivm, j);
+ }
+
+ return LLVMConstVector(elems, 16);
+}
+
+/**
* Build shuffle vectors that match PACKxx (SSE) instructions or
* VPERM (Altivec).
*/
@@ -325,8 +350,8 @@ lp_build_interleave2(struct gallivm_state *gallivm,
}
/**
- * Interleave vector elements but with 256 bit,
- * treats it as interleave with 2 concatenated 128 bit vectors.
+ * Interleave vector elements but with 256 (or 512) bit,
+ * treats it as interleave with 2 concatenated 128 (or 256) bit vectors.
*
* This differs to lp_build_interleave2 as that function would do the
following (for lo):
* a0 b0 a1 b1 a2 b2 a3 b3, and this does not compile into an AVX unpack
instruction.
@@ -343,6 +368,14 @@ lp_build_interleave2(struct gallivm_state *gallivm,
*
* And interleave-hi would result in:
* a2 b2 a3 b3 a6 b6 a7 b7
+ *
+ * For 512 bits, the following are true:
+ *
+ * Interleave-lo would result in (capital letters denote hex indices):
+ * a0 b0 a1 b1 a4 b4 a5 b5 a8 b8 a9 b9 aC bC aD bD
+ *
+ * Interleave-hi would result in:
+ * a2 b2 a3 b3 a6 b6 a7 b7 aA bA aB bB aE bE aF bF
*/
LLVMValueRef
lp_build_interleave2_half(struct gallivm_state *gallivm,
@@ -354,6 +387,9 @@ lp_build_interleave2_half(struct gallivm_state *gallivm,
if (type.length * type.width == 256) {
LLVMValueRef shuffle = lp_build_const_unpack_shuffle_half(gallivm,
type.length, lo_hi);
return LLVMBuildShuffleVector(gallivm->builder, a, b, shuffle, "");
+ } else if ((type.length == 16) && (type.width == 32)) {
+ LLVMValueRef shuffle = lp_build_const_unpack_shuffle_16wide(gallivm,
lo_hi);
+ return LLVMBuildShuffleVector(gallivm->builder, a, b, shuffle, "");
} else {
return lp_build_interleave2(gallivm, type, a, b, lo_hi);
}
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Mesa (master): meson: ensure that xmlpool_options.h is generated for targets that need it
Module: Mesa
Branch: master
Commit: 26bde1e354041558aae7b2ab004531055b4562b6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=26bde1e354041558aae7b2ab004531055b4562b6
Author: Dylan Baker
Date: Wed Jan 17 16:08:51 2018 -0800
meson: ensure that xmlpool_options.h is generated for targets that need it
Currently a couple of gallium targets race with xmlpool_options.h being
generated, don't do that.
Signed-off-by: Dylan Baker
Reviewed-by: Eric Anholt
---
src/gallium/auxiliary/pipe-loader/meson.build | 4 ++--
src/gallium/targets/d3dadapter9/meson.build | 2 +-
src/gallium/targets/pipe-loader/meson.build | 18 +-
3 files changed, 12 insertions(+), 12 deletions(-)
diff --git a/src/gallium/auxiliary/pipe-loader/meson.build
b/src/gallium/auxiliary/pipe-loader/meson.build
index 869a293514..32e8188c68 100644
--- a/src/gallium/auxiliary/pipe-loader/meson.build
+++ b/src/gallium/auxiliary/pipe-loader/meson.build
@@ -37,7 +37,7 @@ endif
libpipe_loader_static = static_library(
'pipe_loader_static',
- files_pipe_loader,
+ [files_pipe_loader, xmlpool_options_h],
include_directories : [
inc_util, inc_loader, inc_gallium, inc_include, inc_src, inc_gallium_aux,
inc_gallium_winsys,
@@ -53,7 +53,7 @@ libpipe_loader_static = static_library(
libpipe_loader_dynamic = static_library(
'pipe_loader_dynamic',
- files_pipe_loader,
+ [files_pipe_loader, xmlpool_options_h],
include_directories : [
inc_util, inc_loader, inc_gallium, inc_include, inc_src, inc_gallium_aux,
inc_gallium_winsys,
diff --git a/src/gallium/targets/d3dadapter9/meson.build
b/src/gallium/targets/d3dadapter9/meson.build
index 27a8797221..61bb5649ae 100644
--- a/src/gallium/targets/d3dadapter9/meson.build
+++ b/src/gallium/targets/d3dadapter9/meson.build
@@ -47,7 +47,7 @@ endif
libgallium_nine = shared_library(
'd3dadapter9',
- files('description.c', 'getproc.c', 'drm.c'),
+ [files('description.c', 'getproc.c', 'drm.c'), xmlpool_options_h],
include_directories : [
inc_include, inc_src, inc_loader, inc_mapi, inc_mesa, inc_util,
inc_dri_common, inc_gallium, inc_gallium_aux, inc_gallium_winsys,
diff --git a/src/gallium/targets/pipe-loader/meson.build
b/src/gallium/targets/pipe-loader/meson.build
index 6141d4374f..25b26a34ca 100644
--- a/src/gallium/targets/pipe-loader/meson.build
+++ b/src/gallium/targets/pipe-loader/meson.build
@@ -47,21 +47,21 @@ endif
pipe_loader_install_dir = join_paths(get_option('libdir'), 'gallium-pipe')
pipe_loaders = [
- [with_gallium_i915, 'i915', driver_i915, []],
- [with_gallium_nouveau, 'nouveau', driver_nouveau, []],
- [with_gallium_r300, 'r300', driver_r300, []],
- [with_gallium_r600, 'r600', driver_r600, []],
- [with_gallium_radeonsi, 'radeonsi', driver_radeonsi, [libxmlconfig]],
- [with_gallium_freedreno, 'msm', driver_freedreno, []],
- [with_gallium_svga, 'vmwgfx', driver_svga, []],
- [with_gallium_softpipe, 'swrast', [driver_swrast, driver_swr], [libwsw,
libws_null]],
+ [with_gallium_i915, 'i915', driver_i915, [], []],
+ [with_gallium_nouveau, 'nouveau', driver_nouveau, [], []],
+ [with_gallium_r300, 'r300', driver_r300, [], []],
+ [with_gallium_r600, 'r600', driver_r600, [], []],
+ [with_gallium_radeonsi, 'radeonsi', driver_radeonsi, [libxmlconfig],
[xmlpool_options_h]],
+ [with_gallium_freedreno, 'msm', driver_freedreno, [], []],
+ [with_gallium_svga, 'vmwgfx', driver_svga, [], []],
+ [with_gallium_softpipe, 'swrast', [driver_swrast, driver_swr], [libwsw,
libws_null], []],
]
foreach x : pipe_loaders
if x[0]
shared_library(
'pipe_@0@'.format(x[1]),
- 'pipe_@0@.c'.format(x[1]),
+ ['pipe_@0@.c'.format(x[1]), x[4]],
c_args : [pipe_loader_comp_args, c_vis_args],
cpp_args : [pipe_loader_comp_args, cpp_vis_args],
link_args : pipe_loader_link_args,
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Mesa (master): vbo: fix VBO optimization regression
Module: Mesa
Branch: master
Commit: 9e6efdd1776cb76386d8aa774926c77aa2db7804
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e6efdd1776cb76386d8aa774926c77aa2db7804
Author: Brian Paul
Date: Wed Jan 17 15:15:54 2018 -0700
vbo: fix VBO optimization regression
The optimization in change 8e4efdc895ea ("vbo: optimize some display
list drawing") missed the loopback case. This is used when the
glBegin/End primitive doesn't have a uniform set of vertex attributes.
The new Piglit gl-1.0-dlist-materials test hits this.
So check the aligned_vertex_buffer_offset(list) value and adjust the
buffer offset accordingly.
We also need to remove the 'start == 0' assertion in the loopback
code since it no longer applies.
Reviewed-by: Roland Scheidegger
---
src/mesa/vbo/vbo_save_draw.c | 5 -
src/mesa/vbo/vbo_save_loopback.c | 6 +++---
2 files changed, 7 insertions(+), 4 deletions(-)
diff --git a/src/mesa/vbo/vbo_save_draw.c b/src/mesa/vbo/vbo_save_draw.c
index f5c4a900b3..ddf911700f 100644
--- a/src/mesa/vbo/vbo_save_draw.c
+++ b/src/mesa/vbo/vbo_save_draw.c
@@ -240,8 +240,11 @@ loopback_vertex_list(struct gl_context *ctx,
list->vertex_store->bufferobj,
MAP_INTERNAL);
+ unsigned buffer_offset =
+ aligned_vertex_buffer_offset(list) ? 0 : list->buffer_offset;
+
vbo_loopback_vertex_list(ctx,
-(const GLfloat *)(buffer + list->buffer_offset),
+(const GLfloat *) (buffer + buffer_offset),
list->attrsz,
list->prims,
list->prim_count,
diff --git a/src/mesa/vbo/vbo_save_loopback.c b/src/mesa/vbo/vbo_save_loopback.c
index 1dae91b0b7..9c0e937fe4 100644
--- a/src/mesa/vbo/vbo_save_loopback.c
+++ b/src/mesa/vbo/vbo_save_loopback.c
@@ -107,17 +107,17 @@ loopback_prim(struct gl_context *ctx,
GLuint k;
if (0)
- printf("loopback prim %s(%s,%s) verts %d..%d\n",
+ printf("loopback prim %s(%s,%s) verts %d..%d vsize %d\n",
_mesa_lookup_prim_by_nr(prim->mode),
prim->begin ? "begin" : "..",
prim->end ? "end" : "..",
- start, end);
+ start, end,
+ vertex_size);
if (prim->begin) {
CALL_Begin(GET_DISPATCH(), (prim->mode));
}
else {
- assert(start == 0);
start += wrap_count;
}
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Mesa (master): radv: Use correct bindings for inputRate in key generation.
Module: Mesa
Branch: master
Commit: bd5c942cefc9f58aa6e8f6a9452f65e9d0d9d93a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd5c942cefc9f58aa6e8f6a9452f65e9d0d9d93a
Author: Bas Nieuwenhuizen
Date: Thu Jan 18 15:35:11 2018 +0100
radv: Use correct bindings for inputRate in key generation.
The bindings also have an index field.
Fixes: 49d035122e "radv: Add single pipeline cache key."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104677
Reviewed-by: Dave Airlie
Reviewed-by: Samuel Pitoiset
---
src/amd/vulkan/radv_pipeline.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index c3c17af850..5f824796fe 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1726,10 +1726,16 @@ radv_generate_graphics_pipeline_key(struct
radv_pipeline *pipeline,
key.has_multiview_view_index = has_view_index;
+ uint32_t binding_input_rate = 0;
+ for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount;
++i) {
+ if (input_state->pVertexBindingDescriptions[i].inputRate)
+ binding_input_rate |= 1u <<
input_state->pVertexBindingDescriptions[i].binding;
+ }
+
for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount;
++i) {
unsigned binding;
binding = input_state->pVertexAttributeDescriptions[i].binding;
- if (input_state->pVertexBindingDescriptions[binding].inputRate)
+ if (binding_input_rate & (1u << binding))
key.instance_rate_inputs |= 1u <<
input_state->pVertexAttributeDescriptions[i].location;
}
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Mesa (master): ac: fix visit_ssa_undef() for doubles
Module: Mesa
Branch: master
Commit: 3bccb5dba9415f98f7a3dbb7c43a5eace64b4ec6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3bccb5dba9415f98f7a3dbb7c43a5eace64b4ec6
Author: Timothy Arceri
Date: Thu Jan 18 12:01:33 2018 +1100
ac: fix visit_ssa_undef() for doubles
V2: use LLVMIntTypeInContext()
Fixes: f4e499ec7914 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/common/ac_nir_to_llvm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 02a46dab4d..cd400376a0 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -5055,12 +5055,13 @@ static void visit_ssa_undef(struct ac_nir_context *ctx,
const nir_ssa_undef_instr *instr)
{
unsigned num_components = instr->def.num_components;
+ LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context,
instr->def.bit_size);
LLVMValueRef undef;
if (num_components == 1)
- undef = LLVMGetUndef(ctx->ac.i32);
+ undef = LLVMGetUndef(type);
else {
- undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32,
num_components));
+ undef = LLVMGetUndef(LLVMVectorType(type, num_components));
}
_mesa_hash_table_insert(ctx->defs, &instr->def, undef);
}
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Mesa: tag mesa-17.3.3: mesa-17.3.3
Module: Mesa Branch: refs/tags/mesa-17.3.3 Tag:d2c312d1ff86e83fed32c69f53aa09fb56d06c5e URL: http://cgit.freedesktop.org/mesa/mesa/tag/?id=d2c312d1ff86e83fed32c69f53aa09fb56d06c5e Tagger: Juan A. Suarez Romero Date: Thu Jan 18 22:11:47 2018 +0100 mesa-17.3.3 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (17.3): docs: add sha256 checksums for 17.3.3
Module: Mesa Branch: 17.3 Commit: bc1503b13fcf8190262757ea7f86613e14e25981 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bc1503b13fcf8190262757ea7f86613e14e25981 Author: Juan A. Suarez Romero Date: Thu Jan 18 22:34:34 2018 +0100 docs: add sha256 checksums for 17.3.3 Signed-off-by: Juan A. Suarez Romero --- docs/relnotes/17.3.3.html | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/docs/relnotes/17.3.3.html b/docs/relnotes/17.3.3.html index 7f81cb82e4..350701a53a 100644 --- a/docs/relnotes/17.3.3.html +++ b/docs/relnotes/17.3.3.html @@ -31,7 +31,8 @@ because compatibility contexts are not supported. SHA256 checksums -TBD +c733d37a161501cd81dc9b309ccb613753b98eafc6d35e0847548a6642749772 mesa-17.3.3.tar.gz +41bac5de0ef6adc1f41a1ec0f80c19e361298ce02fa81b5f9ba4fdca33a9379b mesa-17.3.3.tar.xz ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: Replace an assert with unreachable.
Module: Mesa
Branch: master
Commit: 0f89f9b8eb4b4f40d9359ebc98ed7f92cd889a83
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0f89f9b8eb4b4f40d9359ebc98ed7f92cd889a83
Author: Bas Nieuwenhuizen
Date: Wed Jan 17 23:23:02 2018 +0100
radv: Replace an assert with unreachable.
Otherwise we get uninitialized variable warnings for es_vgpr_comp_cnt.
Reviewed-by: Samuel Pitoiset
---
src/amd/vulkan/radv_shader.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 9819a522d7..3bcaac168a 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -424,7 +424,7 @@ radv_fill_shader_variant(struct radv_device *device,
} else if (es_type == MESA_SHADER_TESS_EVAL) {
es_vgpr_comp_cnt = 3;
} else {
- assert(!"invalid shader ES type");
+ unreachable("invalid shader ES type");
}
/* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
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Mesa (master): radv: Remove DCC check on CS resolve dst image.
Module: Mesa Branch: master Commit: e417ab212b17505aa3bd40d9b57c2c2b27ae75b0 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e417ab212b17505aa3bd40d9b57c2c2b27ae75b0 Author: Bas Nieuwenhuizen Date: Wed Jan 17 23:21:42 2018 +0100 radv: Remove DCC check on CS resolve dst image. Gives a warning when the assert is disabled, and not even necessarily true. Reviewed-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_resolve_cs.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/src/amd/vulkan/radv_meta_resolve_cs.c b/src/amd/vulkan/radv_meta_resolve_cs.c index 7c569aa920..5b3bc89832 100644 --- a/src/amd/vulkan/radv_meta_resolve_cs.c +++ b/src/amd/vulkan/radv_meta_resolve_cs.c @@ -503,11 +503,8 @@ radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer) dest_att.attachment == VK_ATTACHMENT_UNUSED) continue; - struct radv_image *dst_img = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment->image; struct radv_image_view *src_iview = cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment; - assert(!dst_img->surface.dcc_size); - VkImageSubresourceRange range; range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT; range.baseMipLevel = 0; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (17.3): docs: add release notes for 17.3.3
Module: Mesa Branch: 17.3 Commit: 80f5f279b3f9fc752ba35b1cb2878a936f8ace90 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=80f5f279b3f9fc752ba35b1cb2878a936f8ace90 Author: Juan A. Suarez Romero Date: Thu Jan 18 20:02:46 2018 + docs: add release notes for 17.3.3 Signed-off-by: Juan A. Suarez Romero --- docs/relnotes/17.3.3.html | 150 ++ 1 file changed, 150 insertions(+) diff --git a/docs/relnotes/17.3.3.html b/docs/relnotes/17.3.3.html new file mode 100644 index 00..7f81cb82e4 --- /dev/null +++ b/docs/relnotes/17.3.3.html @@ -0,0 +1,150 @@ +http://www.w3.org/TR/html4/loose.dtd";> + + + + Mesa Release Notes + + + + + + The Mesa 3D Graphics Library + + + + + +Mesa 17.3.3 Release Notes / January 18, 2018 + + +Mesa 17.3.3 is a bug fix release which fixes bugs found since the 17.3.2 release. + + +Mesa 17.3.3 implements the OpenGL 4.5 API, but the version reported by +glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) / +glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used. +Some drivers don't support all the features required in OpenGL 4.5. OpenGL +4.5 is only available if requested at context creation +because compatibility contexts are not supported. + + + +SHA256 checksums + +TBD + + + +New features +None + + +Bug fixes + + + +https://bugs.freedesktop.org/show_bug.cgi?id=104214";>Bug 104214 - Dota crashes when switching from game to desktop + +https://bugs.freedesktop.org/show_bug.cgi?id=104492";>Bug 104492 - Compute Shader: Wrong alignment when assigning struct value to structured SSBO + +https://bugs.freedesktop.org/show_bug.cgi?id=104551";>Bug 104551 - Check if Mako templates for Python are installed + + + + +Changes + +Alex Smith (3): + + anv: Add missing unlock in anv_scratch_pool_alloc + anv: Take write mask into account in has_color_buffer_write_enabled + anv: Make sure state on primary is correct after CmdExecuteCommands + + +Andres Gomez (1): + + anv: Import mako templates only during execution of anv_extensions + + +Bas Nieuwenhuizen (11): + + radv: Invert condition for all samples identical during resolve. + radv: Flush caches before subpass resolve. + radv: Fix fragment resolve destination offset. + radv: Use correct framebuffer size for partial FS resolves. + radv: Always use fragment resolve if dest uses DCC. + Revert "radv/gfx9: fix block compression texture views." + radv: Use correct HTILE expanded words. + radv: Allow writing 0 scissors. + ac/nir: Handle loading data from compact arrays. + radv: Invalidate L1 for VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT. + ac/nir: Sanitize location_frac for local variables. + + +Dave Airlie (8): + + radv: fix events on compute queues. + radv: fix pipeline statistics end query on compute queue + radv/gfx9: fix 3d image to image transfers on compute queues. + radv/gfx9: fix 3d image clears on compute queues + radv/gfx9: fix buffer to image for 3d images on compute queues + radv/gfx9: fix block compression texture views. + radv/gfx9: use a bigger hammer to flush cb/db caches. + radv/gfx9: use correct swizzle parameter to work out border swizzle. + + +Emil Velikov (1): + + docs: add sha256 checksums for 17.3.2 + + +Florian Will (1): + + glsl: Respect std430 layout in lower_buffer_access + + +Juan A. Suarez Romero (6): + + cherry-ignore: intel/fs: Use the original destination region for int MUL lowering + cherry-ignore: i965/fs: Use UW types when using V immediates + cherry-ignore: main: Clear shader program data whenever ProgramBinary is called + cherry-ignore: egl: pass the dri2_dpy to the $plat_teardown functions + cherry-ignore: vulkan/wsi: free cmd pools + Update version to 17.3.3 + + +Józef Kucia (1): + + radeonsi: fix alpha-to-coverage if color writes are disabled + + +Kenneth Graunke (2): + + i965: Require space for MI_BATCHBUFFER_END. + i965: Torch public intel_batchbuffer_emit_dword/float helpers. + + +Lucas Stach (1): + + etnaviv: disable in-place resolve for non-supertiled surfaces + + +Samuel Iglesias Gonsálvez (1): + + anv: VkDescriptorSetLayoutBinding can have descriptorCount == 0 + + +Thomas Hellstrom (1): + + loader/dri3: Avoid freeing renderbuffers in use + + +Tim Rowley (1): + + swr/rast: fix invalid sign masks in avx512 simdlib code + + + + + + ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (17.3): Update version to 17.3.3
Module: Mesa Branch: 17.3 Commit: 2adb90f40a75e7fd17b9370ced1c338096246233 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2adb90f40a75e7fd17b9370ced1c338096246233 Author: Juan A. Suarez Romero Date: Thu Jan 18 19:52:51 2018 + Update version to 17.3.3 Signed-off-by: Juan A. Suarez Romero --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index fd9b308ed8..d1c738c5f5 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -17.3.2 +17.3.3 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): ac/nir: account for view index in the user sgpr allocation.
Module: Mesa
Branch: master
Commit: 3153d742078d9842d867e8affddf0b157de762f0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3153d742078d9842d867e8affddf0b157de762f0
Author: Dave Airlie
Date: Thu Jan 18 02:31:40 2018 +
ac/nir: account for view index in the user sgpr allocation.
The view index user sgpr wasn't being accounted for properly,
this refactors out the code to decide if it's required and then
uses that info to account for it.
Fixes: 180c1b924e (ac/nir: Add shader support for multiviews.)
Reviewed-by: Bas Nieuwenhuizen
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 42 +
1 file changed, 34 insertions(+), 8 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index c53fb5cb1c..02a46dab4d 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -543,8 +543,31 @@ struct user_sgpr_info {
bool indirect_all_descriptor_sets;
};
+static bool needs_view_index_sgpr(struct nir_to_llvm_context *ctx,
+ gl_shader_stage stage)
+{
+ switch (stage) {
+ case MESA_SHADER_VERTEX:
+ if (ctx->shader_info->info.needs_multiview_view_index ||
+ (!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls
&& ctx->options->key.has_multiview_view_index))
+ return true;
+ break;
+ case MESA_SHADER_TESS_EVAL:
+ if (ctx->shader_info->info.needs_multiview_view_index ||
(!ctx->options->key.tes.as_es && ctx->options->key.has_multiview_view_index))
+ return true;
+ case MESA_SHADER_GEOMETRY:
+ case MESA_SHADER_TESS_CTRL:
+ if (ctx->shader_info->info.needs_multiview_view_index)
+ return true;
+ default:
+ break;
+ }
+ return false;
+}
+
static void allocate_user_sgprs(struct nir_to_llvm_context *ctx,
gl_shader_stage stage,
+ bool needs_view_index,
struct user_sgpr_info *user_sgpr_info)
{
memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
@@ -600,6 +623,9 @@ static void allocate_user_sgprs(struct nir_to_llvm_context
*ctx,
break;
}
+ if (needs_view_index)
+ user_sgpr_info->sgpr_count++;
+
if (ctx->shader_info->info.loads_push_constants)
user_sgpr_info->sgpr_count += 2;
@@ -771,8 +797,8 @@ static void create_function(struct nir_to_llvm_context *ctx,
struct user_sgpr_info user_sgpr_info;
struct arg_info args = {};
LLVMValueRef desc_sets;
-
- allocate_user_sgprs(ctx, stage, &user_sgpr_info);
+ bool needs_view_index = needs_view_index_sgpr(ctx, stage);
+ allocate_user_sgprs(ctx, stage, needs_view_index, &user_sgpr_info);
if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
add_arg(&args, ARG_SGPR, const_array(ctx->ac.v4i32, 16),
@@ -810,7 +836,7 @@ static void create_function(struct nir_to_llvm_context *ctx,
declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
previous_stage, &args);
- if (ctx->shader_info->info.needs_multiview_view_index ||
(!ctx->options->key.vs.as_es && !ctx->options->key.vs.as_ls &&
ctx->options->key.has_multiview_view_index))
+ if (needs_view_index)
add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->view_index);
if (ctx->options->key.vs.as_es)
add_arg(&args, ARG_SGPR, ctx->ac.i32,
@@ -854,7 +880,7 @@ static void create_function(struct nir_to_llvm_context *ctx,
&ctx->tcs_out_layout);
add_arg(&args, ARG_SGPR, ctx->ac.i32,
&ctx->tcs_in_layout);
- if (ctx->shader_info->info.needs_multiview_view_index)
+ if (needs_view_index)
add_arg(&args, ARG_SGPR, ctx->ac.i32,
&ctx->view_index);
@@ -879,7 +905,7 @@ static void create_function(struct nir_to_llvm_context *ctx,
&ctx->tcs_out_layout);
add_arg(&args, ARG_SGPR, ctx->ac.i32,
&ctx->tcs_in_layout);
- if (ctx->shader_info->info.needs_multiview_view_index)
+ if (needs_view_index)
add_arg(&args, ARG_SGPR, ctx->ac.i32,
&ctx->view_index);
@@ -898,7 +924,7 @@ static void create_function(struct nir_to_llvm_context *ctx,
&args, &desc_sets);
add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->tcs_offchip_layout);
Mesa (master): r600: enable ARB_enhanced_layouts
Module: Mesa Branch: master Commit: 5758a8c4027459fa5b51d47b4aba95c5126f3bfe URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5758a8c4027459fa5b51d47b4aba95c5126f3bfe Author: Dave Airlie Date: Thu Jan 18 14:09:38 2018 +1000 r600: enable ARB_enhanced_layouts Only one piglit test fails, sso-vs-gs-fs-array-interleave There are 3 tests using ssbo without checking sizes failing also but those are test bugs. Reviewed-by: Roland Scheidegger Signed-off-by: Dave Airlie --- docs/features.txt| 4 ++-- docs/relnotes/17.4.0.html| 1 + src/gallium/drivers/r600/r600_pipe.c | 2 +- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/docs/features.txt b/docs/features.txt index e9b7be554b..4b2bf2c69f 100644 --- a/docs/features.txt +++ b/docs/features.txt @@ -193,11 +193,11 @@ GL 4.4, GLSL 4.40 -- all DONE: i965/gen8+, nvc0, radeonsi GL_MAX_VERTEX_ATTRIB_STRIDE DONE (all drivers) GL_ARB_buffer_storage DONE (freedreno, i965, nv50, r600, llvmpipe, swr) GL_ARB_clear_texture DONE (i965, nv50, r600, llvmpipe, softpipe, swr) - GL_ARB_enhanced_layouts DONE (i965, nv50, llvmpipe, softpipe) + GL_ARB_enhanced_layouts DONE (i965, nv50, r600, llvmpipe, softpipe) - compile-time constant expressions DONE - explicit byte offsets for blocksDONE - forced alignment within blocks DONE - - specified vec4-slot component numbers DONE (i965, nv50, llvmpipe, softpipe) + - specified vec4-slot component numbers DONE - specified transform/feedback layout DONE - input/output block locationsDONE GL_ARB_multi_bind DONE (all drivers) diff --git a/docs/relnotes/17.4.0.html b/docs/relnotes/17.4.0.html index 1adbb3e1cf..412c0fc455 100644 --- a/docs/relnotes/17.4.0.html +++ b/docs/relnotes/17.4.0.html @@ -50,6 +50,7 @@ Note: some of the new features are only available with certain drivers. GL_ARB_shader_storage_buffer_object on r600/evergreen+ GL_ARB_compute_shader on r600/evergreen+ GL_ARB_cull_distance on r600/evergreen+ +GL_ARB_enhanced_layouts on r600/evergreen+ GL_ARB_bindless_texture on nvc0/kepler OpenGL 4.3 on r600/evergreen with hw fp64 support Support 1 binary format for GL_ARB_get_program_binary on i965 diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index c146383360..e7f8ae83ec 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -351,6 +351,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_SAMPLER_VIEW_TARGET: case PIPE_CAP_TGSI_PACK_HALF_FLOAT: case PIPE_CAP_TGSI_CLOCK: + case PIPE_CAP_TGSI_ARRAY_COMPONENTS: return family >= CHIP_CEDAR ? 1 : 0; case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS: return family >= CHIP_CEDAR ? 4 : 0; @@ -387,7 +388,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES: case PIPE_CAP_TGSI_VOTE: case PIPE_CAP_MAX_WINDOW_RECTANGLES: - case PIPE_CAP_TGSI_ARRAY_COMPONENTS: case PIPE_CAP_TGSI_CAN_READ_OUTPUTS: case PIPE_CAP_NATIVE_FENCE_FD: case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel: Future-proof ring names for aubinator_error_decode
Module: Mesa
Branch: master
Commit: 34499e8ddce09a55210e776700ee6de2fc6df6b2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=34499e8ddce09a55210e776700ee6de2fc6df6b2
Author: Chris Wilson
Date: Wed Jan 17 15:41:25 2018 +
intel: Future-proof ring names for aubinator_error_decode
The kernel is moving to a $class$instance naming scheme in preparation
for accommodating more rings in the future in a consistent manner. It is
already using the naming scheme internally, and now we are looking at
updating some soft-ABI such as the error state to use the new naming
scheme. This of course means we need to teach aubinator_error_decode how
to map both sets of ring names onto its register maps.
Signed-off-by: Chris Wilson
Cc: Michel Thierry
Cc: Michal Wajdeczko
Cc: Tvrtko Ursulin
Cc: Lionel Landwerlin
Cc: Kenneth Graunke
Reviewed-by: Kenneth Graunke
Reviewed-by: Michel Thierry
---
src/intel/tools/aubinator_error_decode.c | 122 +--
1 file changed, 98 insertions(+), 24 deletions(-)
diff --git a/src/intel/tools/aubinator_error_decode.c
b/src/intel/tools/aubinator_error_decode.c
index 9dd70790e1..01c6a7a365 100644
--- a/src/intel/tools/aubinator_error_decode.c
+++ b/src/intel/tools/aubinator_error_decode.c
@@ -74,40 +74,95 @@ print_register(struct gen_spec *spec, const char *name,
uint32_t reg)
}
struct ring_register_mapping {
- const char *ring_name;
+ unsigned ring_class;
+ unsigned ring_instance;
const char *register_name;
};
+enum {
+ RCS,
+ BCS,
+ VCS,
+ VECS,
+};
+
static const struct ring_register_mapping acthd_registers[] = {
- { "blt", "BCS_ACTHD_UDW" },
- { "bsd", "VCS_ACTHD_UDW" },
- { "bsd2", "VCS2_ACTHD_UDW" },
- { "render", "ACTHD_UDW" },
- { "vebox", "VECS_ACTHD_UDW" },
+ { BCS, 0, "BCS_ACTHD_UDW" },
+ { VCS, 0, "VCS_ACTHD_UDW" },
+ { VCS, 1, "VCS2_ACTHD_UDW" },
+ { RCS, 0, "ACTHD_UDW" },
+ { VECS, 0, "VECS_ACTHD_UDW" },
};
static const struct ring_register_mapping ctl_registers[] = {
- { "blt", "BCS_RING_BUFFER_CTL" },
- { "bsd", "VCS_RING_BUFFER_CTL" },
- { "bsd2", "VCS2_RING_BUFFER_CTL" },
- { "render", "RCS_RING_BUFFER_CTL" },
- { "vebox", "VECS_RING_BUFFER_CTL" },
+ { BCS, 0, "BCS_RING_BUFFER_CTL" },
+ { VCS, 0, "VCS_RING_BUFFER_CTL" },
+ { VCS, 1, "VCS2_RING_BUFFER_CTL" },
+ { RCS, 0, "RCS_RING_BUFFER_CTL" },
+ { VECS, 0, "VECS_RING_BUFFER_CTL" },
};
static const struct ring_register_mapping fault_registers[] = {
- { "blt", "BCS_FAULT_REG" },
- { "bsd", "VCS_FAULT_REG" },
- { "render", "RCS_FAULT_REG" },
- { "vebox", "VECS_FAULT_REG" },
+ { BCS, 0, "BCS_FAULT_REG" },
+ { VCS, 0, "VCS_FAULT_REG" },
+ { RCS, 0, "RCS_FAULT_REG" },
+ { VECS, 0, "VECS_FAULT_REG" },
};
+static int ring_name_to_class(const char *ring_name,
+ unsigned int *class)
+{
+ static const char *class_names[] = {
+ [RCS] = "rcs",
+ [BCS] = "bcs",
+ [VCS] = "vcs",
+ [VECS] = "vecs",
+ };
+ for (size_t i = 0; i < ARRAY_SIZE(class_names); i++) {
+ if (strcmp(ring_name, class_names[i]))
+ continue;
+
+ *class = i;
+ return atoi(ring_name + strlen(class_names[i]));
+ }
+
+ static const struct {
+ const char *name;
+ unsigned int class;
+ int instance;
+ } legacy_names[] = {
+ { "render", RCS, 0 },
+ { "blt", BCS, 0 },
+ { "bsd", VCS, 0 },
+ { "bsd2", VCS, 1 },
+ { "vebox", VECS, 0 },
+ };
+ for (size_t i = 0; i < ARRAY_SIZE(legacy_names); i++) {
+ if (strcmp(ring_name, legacy_names[i].name))
+ continue;
+
+ *class = legacy_names[i].class;
+ return legacy_names[i].instance;
+ }
+
+ return -1;
+}
+
static const char *
register_name_from_ring(const struct ring_register_mapping *mapping,
unsigned nb_mapping,
const char *ring_name)
{
+ unsigned int class;
+ int instance;
+
+ instance = ring_name_to_class(ring_name, &class);
+ if (instance < 0)
+ return NULL;
+
for (unsigned i = 0; i < nb_mapping; i++) {
- if (strcmp(mapping[i].ring_name, ring_name) == 0)
+ if (mapping[i].ring_class == class &&
+ mapping[i].ring_instance == instance)
return mapping[i].register_name;
}
return NULL;
@@ -117,16 +172,35 @@ static const char *
instdone_register_for_ring(const struct gen_device_info *devinfo,
const char *ring_name)
{
- if (strcmp(ring_name, "blt") == 0)
- return "BCS_INSTDONE";
- else if (strcmp(ring_name, "vebox") == 0)
- return "VECS_INSTDONE";
- else if (strcmp(ring_name, "bsd") == 0)
- return "VCS_INSTDONE";
- else if (strcmp(ring_name, "render") == 0) {
+ unsigned int class;
+ int instance;
+
+ instance = ring_name_to_class(ring_name, &class);
+ if (instance < 0)
+ return NULL;
+
+ switch (class) {
+ case RCS:
if (devinfo->gen == 6)
return "INSTDONE_2"
Mesa (master): i965: Bind null render targets for shadow sampling + color.
Module: Mesa
Branch: master
Commit: 3e18c53e59457f585de217208e1745f2683be0b9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e18c53e59457f585de217208e1745f2683be0b9
Author: Kenneth Graunke
Date: Wed Jan 17 14:16:04 2018 -0800
i965: Bind null render targets for shadow sampling + color.
Portal 2 appears to bind RGBA_UNORM textures to a sampler2DShadow,
and calls shadow2D() on it. This causes undefined behavior in OpenGL.
Unfortunately, our sampler appears to hang in this scenario, which is
not acceptable. Just give them a null surface instead, which returns
all zeroes.
Fixes GPU hangs in Portal 2 on Kabylake.
Huge thanks to Jason Ekstrand for noticing this crazy behavior while
sifting through crash dumps.
Cc: mesa-sta...@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104487
Reviewed-by: Topi Pohjolainen
Reviewed-by: Jason Ekstrand
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 33 +++-
1 file changed, 32 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index adf60a840b..38af6bc0de 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -1095,6 +1095,14 @@ const struct brw_tracked_state
brw_renderbuffer_read_surfaces = {
.emit = update_renderbuffer_read_surfaces,
};
+static bool
+is_depth_texture(struct intel_texture_object *iobj)
+{
+ GLenum base_format = _mesa_get_format_base_format(iobj->_Format);
+ return base_format == GL_DEPTH_COMPONENT ||
+ (base_format == GL_DEPTH_STENCIL && !iobj->base.StencilSampling);
+}
+
static void
update_stage_texture_surfaces(struct brw_context *brw,
const struct gl_program *prog,
@@ -1121,9 +1129,32 @@ update_stage_texture_surfaces(struct brw_context *brw,
if (prog->SamplersUsed & (1 << s)) {
const unsigned unit = prog->SamplerUnits[s];
const bool used_by_txf = prog->info.textures_used_by_txf & (1 << s);
+ struct gl_texture_object *obj = ctx->Texture.Unit[unit]._Current;
+ struct intel_texture_object *iobj = intel_texture_object(obj);
/* _NEW_TEXTURE */
- if (ctx->Texture.Unit[unit]._Current) {
+ if (!obj)
+continue;
+
+ if ((prog->ShadowSamplers & (1 << s)) && !is_depth_texture(iobj)) {
+/* A programming note for the sample_c message says:
+ *
+ *"The Surface Format of the associated surface must be
+ * indicated as supporting shadow mapping as indicated in the
+ * surface format table."
+ *
+ * Accessing non-depth textures via a sampler*Shadow type is
+ * undefined. GLSL 4.50 page 162 says:
+ *
+ *"If a shadow texture call is made to a sampler that does not
+ * represent a depth texture, then results are undefined."
+ *
+ * We give them a null surface (zeros) for undefined. We've seen
+ * GPU hangs with color buffers and sample_c, so we try and avoid
+ * those with this hack.
+ */
+emit_null_surface_state(brw, NULL, surf_offset + s);
+ } else {
brw_update_texture_surface(ctx, unit, surf_offset + s, for_gather,
used_by_txf, plane);
}
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Mesa (master): anv/query: implement multiview interactions
Module: Mesa
Branch: master
Commit: 7ec6e4e68980c575b0818304920a8a8829ebd240
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ec6e4e68980c575b0818304920a8a8829ebd240
Author: Iago Toral Quiroga
Date: Thu Jan 4 03:45:56 2018 +0100
anv/query: implement multiview interactions
From the Vulkan spec with KHX extensions:
"If queries are used while executing a render pass instance that has
multiview enabled, the query uses N consecutive query indices
in the query pool (starting at query) where N is the number of bits
set in the view mask in the subpass the query is used in.
How the numerical results of the query are distributed among the
queries is implementation-dependent. For example, some implementations
may write each view's results to a distinct query, while other
implementations may write the total result to the first query and write
zero to the other queries. However, the sum of the results in all the
queries must accurately reflect the total result of the query summed
over all views. Applications can sum the results from all the queries to
compute the total result."
In our case we only really emit a single query (in the first query index)
that stores the aggregated result for all views, but we still need to manage
availability for all the other query indices involved, even if we don't
actually use them.
This is relevant when clients call vkGetQueryPoolResults and pass all N
queries to retrieve the results. In that scenario, without this patch,
we will never see queries other than the first being available since we
never emit them.
v2: we need the same treatment for timestamp queries.
v3 (Jason):
- Better an if instead of an early return.
- We can't write to this memory in the CPU, we should use
MI_STORE_DATA_IMM and emit_query_availability (Jason).
v4 (Jason):
- No need to take the value to write as parameter, just hard code it to 0.
Fixes test failures in some work-in-progress CTS multiview+query tests.
Reviewed-by: Jason Ekstrand
---
src/intel/vulkan/genX_query.c | 54 +++
1 file changed, 54 insertions(+)
diff --git a/src/intel/vulkan/genX_query.c b/src/intel/vulkan/genX_query.c
index 7683d0d1e3..266163474b 100644
--- a/src/intel/vulkan/genX_query.c
+++ b/src/intel/vulkan/genX_query.c
@@ -322,6 +322,30 @@ emit_query_availability(struct anv_cmd_buffer *cmd_buffer,
}
}
+/**
+ * Goes through a series of consecutive query indices in the given pool
+ * setting all element values to 0 and emitting them as available.
+ */
+static void
+emit_zero_queries(struct anv_cmd_buffer *cmd_buffer,
+ struct anv_query_pool *pool,
+ uint32_t first_index, uint32_t num_queries)
+{
+ const uint32_t num_elements = pool->stride / sizeof(uint64_t);
+
+ for (uint32_t i = 0; i < num_queries; i++) {
+ uint32_t slot_offset = (first_index + i) * pool->stride;
+ for (uint32_t j = 1; j < num_elements; j++) {
+ anv_batch_emit(&cmd_buffer->batch, GENX(MI_STORE_DATA_IMM), sdi) {
+sdi.Address.bo = &pool->bo;
+sdi.Address.offset = slot_offset + j * sizeof(uint64_t);
+sdi.ImmediateData = 0ull;
+ }
+ }
+ emit_query_availability(cmd_buffer, &pool->bo, slot_offset);
+ }
+}
+
void genX(CmdResetQueryPool)(
VkCommandBuffer commandBuffer,
VkQueryPool queryPool,
@@ -462,6 +486,21 @@ void genX(CmdEndQuery)(
default:
unreachable("");
}
+
+ /* When multiview is active the spec requires that N consecutive query
+* indices are used, where N is the number of active views in the subpass.
+* The spec allows that we only write the results to one of the queries
+* but we still need to manage result availability for all the query
indices.
+* Since we only emit a single query for all active views in the
+* first index, mark the other query indices as being already available
+* with result 0.
+*/
+ if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
+ const uint32_t num_queries =
+ _mesa_bitcount(cmd_buffer->state.subpass->view_mask);
+ if (num_queries > 1)
+ emit_zero_queries(cmd_buffer, pool, query + 1, num_queries - 1);
+ }
}
#define TIMESTAMP 0x2358
@@ -504,6 +543,21 @@ void genX(CmdWriteTimestamp)(
}
emit_query_availability(cmd_buffer, &pool->bo, offset);
+
+ /* When multiview is active the spec requires that N consecutive query
+* indices are used, where N is the number of active views in the subpass.
+* The spec allows that we only write the results to one of the queries
+* but we still need to manage result availability for all the query
indices.
+* Since we only emit a single query for all active views in the
+* first index, mark the other query indices as being already available
+* with result 0.
+*/
+ if (cmd_buffer
Mesa (master): broadcom: add missing headers to the tarball
Module: Mesa Branch: master Commit: 393cf04fa4c7137a00b3616ab4ee2d25b39a263a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=393cf04fa4c7137a00b3616ab4ee2d25b39a263a Author: Emil Velikov Date: Wed Jan 17 16:27:52 2018 + broadcom: add missing headers to the tarball Signed-off-by: Emil Velikov --- src/broadcom/Makefile.sources | 7 +-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/src/broadcom/Makefile.sources b/src/broadcom/Makefile.sources index 25bab6ad06..e2bd075fbd 100644 --- a/src/broadcom/Makefile.sources +++ b/src/broadcom/Makefile.sources @@ -13,11 +13,14 @@ BROADCOM_GENXML_XML_FILES = \ BROADCOM_FILES = \ cle/v3d_packet_helpers.h \ - common/v3d_debug.c \ - common/v3d_debug.h \ + cle/v3dx_pack.h\ clif/clif_dump.c \ clif/clif_dump.h \ + clif/clif_private.h \ + common/v3d_debug.c \ + common/v3d_debug.h \ common/v3d_device_info.h \ + common/v3d_macros.h \ compiler/nir_to_vir.c \ compiler/vir.c \ compiler/vir_dump.c \ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): vc5: add missing files to the tarball
Module: Mesa Branch: master Commit: c9b2cb78972dd874edd5c612e6a221fb1f4d6e50 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c9b2cb78972dd874edd5c612e6a221fb1f4d6e50 Author: Emil Velikov Date: Wed Jan 17 16:34:48 2018 + vc5: add missing files to the tarball Signed-off-by: Emil Velikov --- src/gallium/drivers/vc5/Makefile.sources | 5 + 1 file changed, 5 insertions(+) diff --git a/src/gallium/drivers/vc5/Makefile.sources b/src/gallium/drivers/vc5/Makefile.sources index f5cd8d79f8..bc145806cc 100644 --- a/src/gallium/drivers/vc5/Makefile.sources +++ b/src/gallium/drivers/vc5/Makefile.sources @@ -9,6 +9,7 @@ C_SOURCES := \ vc5_drm.h \ vc5_fence.c \ vc5_formats.c \ + vc5_format_table.h \ vc5_job.c \ vc5_program.c \ vc5_query.c \ @@ -17,14 +18,18 @@ C_SOURCES := \ vc5_screen.c \ vc5_screen.h \ vc5_simulator.c \ + vc5_simulator_wrapper.c \ + vc5_simulator_wrapper.h \ vc5_tiling.c \ vc5_tiling.h \ vc5_uniforms.c \ $() VC5_PER_VERSION_SOURCES = \ + v3dx_context.h \ v3dx_format_table.c \ v3dx_simulator.c \ + v3dx_simulator.h \ vc5_draw.c \ vc5_emit.c \ vc5_rcl.c \ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600: add support for ARB_shader_clock.
Module: Mesa
Branch: master
Commit: 9041730d1c0f5bb88866c4448306eaffb0f4d761
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9041730d1c0f5bb88866c4448306eaffb0f4d761
Author: Dave Airlie
Date: Tue Nov 21 07:29:09 2017 +1000
r600: add support for ARB_shader_clock.
Reviewed-by: Gert Wollny
Signed-off-by: Dave Airlie
---
docs/features.txt | 2 +-
src/gallium/drivers/r600/r600_pipe.c | 2 +-
src/gallium/drivers/r600/r600_shader.c | 29 ++---
src/gallium/drivers/r600/r600_sq.h | 3 ++-
4 files changed, 30 insertions(+), 6 deletions(-)
diff --git a/docs/features.txt b/docs/features.txt
index 980140f60d..e9b7be554b 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -305,7 +305,7 @@ Khronos, ARB, and OES extensions that are not part of any
OpenGL or OpenGL ES ve
GL_ARB_sample_locations not started
GL_ARB_seamless_cubemap_per_texture DONE (i965, nvc0,
radeonsi, r600, softpipe, swr)
GL_ARB_shader_ballot DONE (i965/gen8+,
nvc0, radeonsi)
- GL_ARB_shader_clock DONE (i965/gen7+,
nv50, nvc0, radeonsi)
+ GL_ARB_shader_clock DONE (i965/gen7+,
nv50, nvc0, r600, radeonsi)
GL_ARB_shader_stencil_export DONE (i965/gen9+,
r600, radeonsi, softpipe, llvmpipe, swr)
GL_ARB_shader_viewport_layer_arrayDONE (i965/gen6+,
nvc0, radeonsi)
GL_ARB_sparse_buffer DONE (radeonsi/CIK+)
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index 6572d76d64..c146383360 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -350,6 +350,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum
pipe_cap param)
case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
case PIPE_CAP_SAMPLER_VIEW_TARGET:
case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
+ case PIPE_CAP_TGSI_CLOCK:
return family >= CHIP_CEDAR ? 1 : 0;
case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
return family >= CHIP_CEDAR ? 4 : 0;
@@ -394,7 +395,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum
pipe_cap param)
case PIPE_CAP_INT64:
case PIPE_CAP_INT64_DIVMOD:
case PIPE_CAP_TGSI_TEX_TXF_LZ:
- case PIPE_CAP_TGSI_CLOCK:
case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
case PIPE_CAP_TGSI_BALLOT:
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index ab18a6e08e..623e6f7f70 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -10190,6 +10190,29 @@ static int tgsi_bfe(struct r600_shader_ctx *ctx)
return 0;
}
+static int tgsi_clock(struct r600_shader_ctx *ctx)
+{
+ struct tgsi_full_instruction *inst =
&ctx->parse.FullToken.FullInstruction;
+ struct r600_bytecode_alu alu;
+ int r;
+
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ tgsi_dst(ctx, &inst->Dst[0], 0, &alu.dst);
+ alu.src[0].sel = EG_V_SQ_ALU_SRC_TIME_LO;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ memset(&alu, 0, sizeof(struct r600_bytecode_alu));
+ alu.op = ALU_OP1_MOV;
+ tgsi_dst(ctx, &inst->Dst[0], 1, &alu.dst);
+ alu.src[0].sel = EG_V_SQ_ALU_SRC_TIME_HI;
+ r = r600_bytecode_add_alu(ctx->bc, &alu);
+ if (r)
+ return r;
+ return 0;
+}
+
static const struct r600_shader_tgsi_instruction
r600_shader_tgsi_instruction[] = {
[TGSI_OPCODE_ARL] = { ALU_OP0_NOP, tgsi_r600_arl},
[TGSI_OPCODE_MOV] = { ALU_OP1_MOV, tgsi_op2},
@@ -10226,7 +10249,7 @@ static const struct r600_shader_tgsi_instruction
r600_shader_tgsi_instruction[]
[TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
[31]= { ALU_OP0_NOP, tgsi_unsupported},
[32]= { ALU_OP0_NOP, tgsi_unsupported},
- [33]= { ALU_OP0_NOP, tgsi_unsupported},
+ [TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_unsupported},
[34]= { ALU_OP0_NOP, tgsi_unsupported},
[35]= { ALU_OP0_NOP, tgsi_unsupported},
[TGSI_OPCODE_COS] = { ALU_OP1_COS, tgsi_trig},
@@ -10424,7 +10447,7 @@ static const struct r600_shader_tgsi_instruction
eg_shader_tgsi_instruction[] =
[TGSI_OPCODE_POW] = { ALU_OP0_NOP, tgsi_pow},
[31]= { ALU_OP0_NOP, tgsi_unsupported},
[32]= { ALU_OP0_NOP, tgsi_unsupported},
- [33]= { ALU_OP0_NOP, tgsi_unsupported},
+ [TGSI_OPCODE_CLOCK] = { ALU_OP0_NOP, tgsi_clock},
[34]= { ALU_OP0_NOP,
Mesa (master): anv: return VK_ERROR_OUT_OF_DEVICE_MEMORY when surface size is out of HW limits
Module: Mesa Branch: master Commit: eac629deb68115e9ab520212c1af779eca4f38a3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=eac629deb68115e9ab520212c1af779eca4f38a3 Author: Samuel Iglesias Gonsálvez Date: Fri Jan 12 09:41:17 2018 +0100 anv: return VK_ERROR_OUT_OF_DEVICE_MEMORY when surface size is out of HW limits Signed-off-by: Samuel Iglesias Gonsálvez Reviewed-by: Jason Ekstrand --- src/intel/vulkan/anv_image.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c index 4d13e05e11..72e408764d 100644 --- a/src/intel/vulkan/anv_image.c +++ b/src/intel/vulkan/anv_image.c @@ -335,10 +335,8 @@ make_surface(const struct anv_device *dev, .usage = usage, .tiling_flags = tiling_flags); - /* isl_surf_init() will fail only if provided invalid input. Invalid input -* is illegal in Vulkan. -*/ - assert(ok); + if (!ok) + return VK_ERROR_OUT_OF_DEVICE_MEMORY; image->planes[plane].aux_usage = ISL_AUX_USAGE_NONE; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): ac: fix nir_intrinsic_get_buffer_size for radeonsi
Module: Mesa
Branch: master
Commit: 409e15f26fd245dfa6645214c433cfe4e7b9a988
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=409e15f26fd245dfa6645214c433cfe4e7b9a988
Author: Timothy Arceri
Date: Tue Jan 16 18:02:37 2018 +1100
ac: fix nir_intrinsic_get_buffer_size for radeonsi
Reviewed-by: Samuel Pitoiset
Reviewed-by: Nicolai Hähnle
---
src/amd/common/ac_nir_to_llvm.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 25ce06138b..1dc64f87cc 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2404,9 +2404,9 @@ static LLVMValueRef visit_load_push_constant(struct
nir_to_llvm_context *ctx,
static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
const nir_intrinsic_instr *instr)
{
- LLVMValueRef ptr = get_src(ctx, instr->src[0]);
+ LLVMValueRef index = get_src(ctx, instr->src[0]);
- return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""),
false);
+ return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index,
false), false);
}
static void visit_store_ssbo(struct ac_nir_context *ctx,
nir_intrinsic_instr *instr)
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Mesa (master): r600/sb: use different stacks for tracking lds and queue usage.
Module: Mesa
Branch: master
Commit: 3bb2b2cc451651247307ceb6f08ab06909437984
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3bb2b2cc451651247307ceb6f08ab06909437984
Author: Dave Airlie
Date: Wed Jan 10 05:49:16 2018 +
r600/sb: use different stacks for tracking lds and queue usage.
The normal ssa renumbering isn't sufficient for LDS queue access,
this uses two stacks, one for the lds queue, and one for the
lds r/w ordering.
The LDS oq values are incremented in their use in a linear
fashion.
The LDS rw values are incremented in their definitions and used
in the next lds operation to ensure reordering doesn't occur.
Acked-By: Roland Scheidegger
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/sb/sb_pass.h | 4
src/gallium/drivers/r600/sb/sb_ssa_builder.cpp | 23 ---
2 files changed, 24 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/r600/sb/sb_pass.h
b/src/gallium/drivers/r600/sb/sb_pass.h
index b5818039c2..a21b0bf997 100644
--- a/src/gallium/drivers/r600/sb/sb_pass.h
+++ b/src/gallium/drivers/r600/sb/sb_pass.h
@@ -634,7 +634,11 @@ class ssa_rename : public vpass {
typedef sb_map def_map;
def_map def_count;
+ def_map lds_oq_count;
+ def_map lds_rw_count;
std::stack rename_stack;
+ std::stack rename_lds_oq_stack;
+ std::stack rename_lds_rw_stack;
typedef std::map val_map;
val_map values;
diff --git a/src/gallium/drivers/r600/sb/sb_ssa_builder.cpp
b/src/gallium/drivers/r600/sb/sb_ssa_builder.cpp
index 3ad628bb68..5cd41c2aab 100644
--- a/src/gallium/drivers/r600/sb/sb_ssa_builder.cpp
+++ b/src/gallium/drivers/r600/sb/sb_ssa_builder.cpp
@@ -132,6 +132,8 @@ bool ssa_prepare::visit(depart_node& n, bool enter) {
int ssa_rename::init() {
rename_stack.push(def_map());
+ rename_lds_oq_stack.push(def_map());
+ rename_lds_rw_stack.push(def_map());
return 0;
}
@@ -287,8 +289,16 @@ void ssa_rename::pop() {
value* ssa_rename::rename_use(node *n, value* v) {
if (v->version)
return v;
+ unsigned index;
+ if (v->is_lds_access()) {
+ index = get_index(rename_lds_rw_stack.top(), v);
+ } else if (v->is_lds_oq()) {
+ index = new_index(lds_oq_count, v);
+ set_index(rename_lds_oq_stack.top(), v, index);
+ } else {
+ index = get_index(rename_stack.top(), v);
+ }
- unsigned index = get_index(rename_stack.top(), v);
v = sh.get_value_version(v, index);
// if (alu) instruction is predicated and source arg comes from psi node
@@ -313,8 +323,15 @@ value* ssa_rename::rename_use(node *n, value* v) {
}
value* ssa_rename::rename_def(node *n, value* v) {
- unsigned index = new_index(def_count, v);
- set_index(rename_stack.top(), v, index);
+ unsigned index;
+
+ if (v->is_lds_access()) {
+ index = new_index(lds_rw_count, v);
+ set_index(rename_lds_rw_stack.top(), v, index);
+ } else {
+ index = new_index(def_count, v);
+ set_index(rename_stack.top(), v, index);
+ }
value *r = sh.get_value_version(v, index);
return r;
}
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Mesa (master): i965: Pass brw_growing_bo to grow_buffer().
Module: Mesa
Branch: master
Commit: d139b5e4ccf0da19f37428434bf0ef7c76c85049
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d139b5e4ccf0da19f37428434bf0ef7c76c85049
Author: Kenneth Graunke
Date: Sun Jan 7 22:40:13 2018 -0800
i965: Pass brw_growing_bo to grow_buffer().
Cleaner.
Reviewed-by: Iago Toral Quiroga
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 877f68ee7c..b4fcd92b6b 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -288,16 +288,16 @@ replace_bo_in_reloc_list(struct brw_reloc_list *rlist,
*/
static void
grow_buffer(struct brw_context *brw,
-struct brw_bo **bo_ptr,
-uint32_t **map_ptr,
+struct brw_growing_bo *grow,
unsigned existing_bytes,
unsigned new_size)
{
struct intel_batchbuffer *batch = &brw->batch;
struct brw_bufmgr *bufmgr = brw->bufmgr;
+ struct brw_bo *bo = grow->bo;
- uint32_t *old_map = *map_ptr;
- struct brw_bo *old_bo = *bo_ptr;
+ uint32_t *old_map = grow->map;
+ struct brw_bo *old_bo = grow->bo;
struct brw_bo *new_bo =
brw_bo_alloc(bufmgr, old_bo->name, new_size, old_bo->align);
@@ -307,7 +307,7 @@ grow_buffer(struct brw_context *brw,
/* Copy existing data to the new larger buffer */
if (batch->use_shadow_copy) {
- new_map = realloc(*map_ptr, new_size);
+ new_map = realloc(old_map, new_size);
} else {
new_map = brw_bo_map(brw, new_bo, MAP_READ | MAP_WRITE);
memcpy(new_map, old_map, existing_bytes);
@@ -353,8 +353,8 @@ grow_buffer(struct brw_context *brw,
/* Drop the *bo_ptr reference. This should free the old BO. */
brw_bo_unreference(old_bo);
- *bo_ptr = new_bo;
- *map_ptr = new_map;
+ grow->bo = new_bo;
+ grow->map = new_map;
}
void
@@ -377,8 +377,7 @@ intel_batchbuffer_require_space(struct brw_context *brw,
GLuint sz,
const unsigned new_size =
MIN2(batch->batch.bo->size + batch->batch.bo->size / 2,
MAX_BATCH_SIZE);
- grow_buffer(brw, &batch->batch.bo, &batch->batch.map,
- batch_used, new_size);
+ grow_buffer(brw, &batch->batch, batch_used, new_size);
batch->map_next = (void *) batch->batch.map + batch_used;
assert(batch_used + sz < batch->batch.bo->size);
}
@@ -1079,8 +1078,7 @@ brw_state_batch(struct brw_context *brw,
const unsigned new_size =
MIN2(batch->state.bo->size + batch->state.bo->size / 2,
MAX_STATE_SIZE);
- grow_buffer(brw, &batch->state.bo, &batch->state.map,
- batch->state_used, new_size);
+ grow_buffer(brw, &batch->state, batch->state_used, new_size);
assert(offset + size < batch->state.bo->size);
}
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Mesa (master): i965/screen: Allow drirc to set 'allow_rgb10_configs' again.
Module: Mesa
Branch: master
Commit: d67ef485804cab53499dd763db136070ef107a16
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d67ef485804cab53499dd763db136070ef107a16
Author: Mario Kleiner
Date: Thu Jan 18 08:16:20 2018 +0200
i965/screen: Allow drirc to set 'allow_rgb10_configs' again.
Since setup of ALLOW_RGB10_CONFIGS was moved to i965's own
brw_config_options.xml, this was hard-coded to false and
could not be overriden by drirc. Add some parsing into
i965's private screen->optionCache to enable drirc again.
Fixes: b391fb26df9f1b ("dri_util: remove ALLOW_RGB10_CONFIGS option (v2)")
Signed-off-by: Mario Kleiner
Cc: Marek Olšák
Cc: Tapani Pälli
Reviewed-by: Marek Olšák
Reviewed-by: Tapani Pälli
---
src/mesa/drivers/dri/i965/intel_screen.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index 190d8ecb11..9dbda5142e 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -2395,7 +2395,12 @@ __DRIconfig **intelInitScreen2(__DRIscreen *dri_screen)
return NULL;
}
/* parse information in __driConfigOptions */
- driParseOptionInfo(&screen->optionCache, brw_config_options.xml);
+ driOptionCache options;
+ memset(&options, 0, sizeof(options));
+
+ driParseOptionInfo(&options, brw_config_options.xml);
+ driParseConfigFiles(&screen->optionCache, &options, dri_screen->myNum,
"i965");
+ driDestroyOptionCache(&options);
screen->driScrnPriv = dri_screen;
dri_screen->driverPrivate = (void *) screen;
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Mesa (master): mesa/st: translate SO info in glsl_to_nir() case
Module: Mesa
Branch: master
Commit: 4c69961daf45a6a64970e5831bd362307dca0cb2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c69961daf45a6a64970e5831bd362307dca0cb2
Author: Rob Clark
Date: Wed Jan 10 03:54:14 2018 +0100
mesa/st: translate SO info in glsl_to_nir() case
This was handled for VS, but not for GS.
Fixes for gallium drivers using nir:
spec@arb_gpu_shader5@arb_gpu_shader5-xfb-streams-without-invocations
spec@arb_gpu_shader5@arb_gpu_shader5-xfb-streams*
spec@arb_transform_feedback3@arb_transform_feedback3-ext_interleaved_two_bufs_gs*
spec@ext_transform_feedback@geometry-shaders-basic
spec@ext_transform_feedback@* use_gs
spec@glsl-1.50@execution@geometry@primitive-id*
spec@glsl-1.50@execution@geometry@tri-strip-ordering-with-prim-restart
gl_triangle_strip *
spec@glsl-1.50@transform-feedback-builtins
spec@glsl-1.50@transform-feedback-type-and-size
v2: don't call st_translate_program_stream_output) for TCS
v3: drop scanning patch outputs as TCS can't output xfb
Signed-off-by: Rob Clark
Reviewed-by: Timothy Arceri
Tested-by: Karol Herbst
---
src/mesa/state_tracker/st_program.c | 47 +
1 file changed, 43 insertions(+), 4 deletions(-)
diff --git a/src/mesa/state_tracker/st_program.c
b/src/mesa/state_tracker/st_program.c
index 77136edbb9..883813d6c0 100644
--- a/src/mesa/state_tracker/st_program.c
+++ b/src/mesa/state_tracker/st_program.c
@@ -1425,6 +1425,40 @@ st_translate_program_common(struct st_context *st,
}
}
+/**
+ * Update stream-output info for GS/TCS/TES. Normally this is done in
+ * st_translate_program_common() but that is not called for glsl_to_nir
+ * case.
+ */
+static void
+st_translate_program_stream_output(struct gl_program *prog,
+ struct pipe_stream_output_info
*stream_output)
+{
+ if (!prog->sh.LinkedTransformFeedback)
+ return;
+
+ ubyte outputMapping[VARYING_SLOT_TESS_MAX];
+ GLuint attr;
+ uint num_outputs = 0;
+
+ memset(outputMapping, 0, sizeof(outputMapping));
+
+ /*
+* Determine number of outputs, the (default) output register
+* mapping and the semantic information for each output.
+*/
+ for (attr = 0; attr < VARYING_SLOT_MAX; attr++) {
+ if (prog->info.outputs_written & BITFIELD64_BIT(attr)) {
+ GLuint slot = num_outputs++;
+
+ outputMapping[attr] = slot;
+ }
+ }
+
+ st_translate_stream_output_info2(prog->sh.LinkedTransformFeedback,
+outputMapping,
+stream_output);
+}
/**
* Translate a geometry program to create a new variant.
@@ -1436,8 +1470,10 @@ st_translate_geometry_program(struct st_context *st,
struct ureg_program *ureg;
/* We have already compiled to NIR so just return */
- if (stgp->shader_program)
+ if (stgp->shader_program) {
+ st_translate_program_stream_output(&stgp->Base,
&stgp->tgsi.stream_output);
return true;
+ }
ureg = ureg_create_with_screen(PIPE_SHADER_GEOMETRY, st->pipe->screen);
if (ureg == NULL)
@@ -1493,6 +1529,7 @@ st_get_basic_variant(struct st_context *st,
tgsi.ir.nir = nir_shader_clone(NULL, prog->tgsi.ir.nir);
st_finalize_nir(st, &prog->Base, prog->shader_program,
tgsi.ir.nir);
+tgsi.stream_output = prog->tgsi.stream_output;
} else
tgsi = prog->tgsi;
/* fill in new variant */
@@ -1533,7 +1570,7 @@ st_translate_tessctrl_program(struct st_context *st,
{
struct ureg_program *ureg;
- /* We have already compiler to NIR so just return */
+ /* We have already compiled to NIR so just return */
if (sttcp->shader_program)
return true;
@@ -1562,9 +1599,11 @@ st_translate_tesseval_program(struct st_context *st,
{
struct ureg_program *ureg;
- /* We have already compiler to NIR so just return */
- if (sttep->shader_program)
+ /* We have already compiled to NIR so just return */
+ if (sttep->shader_program) {
+ st_translate_program_stream_output(&sttep->Base,
&sttep->tgsi.stream_output);
return true;
+ }
ureg = ureg_create_with_screen(PIPE_SHADER_TESS_EVAL, st->pipe->screen);
if (ureg == NULL)
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Mesa (master): radv/ws: get rid of useless return value
Module: Mesa
Branch: master
Commit: 6785034a707ca6f93295e18616e5bc360adfb700
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6785034a707ca6f93295e18616e5bc360adfb700
Author: Dave Airlie
Date: Thu Jan 18 01:37:59 2018 +
radv/ws: get rid of useless return value
This also used boolean, so nice to kill that.
Reviewed-by: Bas Nieuwenhuizen
Signed-off-by: Dave Airlie
---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index 0ee56f9144..5632b1d4ee 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -175,14 +175,13 @@ static void radv_amdgpu_cs_destroy(struct
radeon_winsys_cs *rcs)
free(cs);
}
-static boolean radv_amdgpu_init_cs(struct radv_amdgpu_cs *cs,
- enum ring_type ring_type)
+static void radv_amdgpu_init_cs(struct radv_amdgpu_cs *cs,
+ enum ring_type ring_type)
{
for (int i = 0; i < ARRAY_SIZE(cs->buffer_hash_table); ++i)
cs->buffer_hash_table[i] = -1;
cs->hw_ip = ring_to_hw_ip(ring_type);
- return true;
}
static struct radeon_winsys_cs *
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Mesa (master): r600/sb: add tess/compute initial state registers.
Module: Mesa
Branch: master
Commit: 05f5282d6388feb58b7f5bd24394d68c29e33aad
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=05f5282d6388feb58b7f5bd24394d68c29e33aad
Author: Dave Airlie
Date: Thu Dec 7 03:31:41 2017 +
r600/sb: add tess/compute initial state registers.
This stops them being optimised out.
Reviewed-by: Roland Scheidegger
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/sb/sb_bc_parser.cpp | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
index ae92a767b4..de3984f596 100644
--- a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
@@ -149,11 +149,14 @@ int bc_parser::parse_decls() {
}
}
- if (sh->target == TARGET_VS || sh->target == TARGET_ES || sh->target ==
TARGET_HS)
+ if (sh->target == TARGET_VS || sh->target == TARGET_ES || sh->target ==
TARGET_HS || sh->target == TARGET_LS)
sh->add_input(0, 1, 0x0F);
else if (sh->target == TARGET_GS) {
sh->add_input(0, 1, 0x0F);
sh->add_input(1, 1, 0x0F);
+ } else if (sh->target == TARGET_COMPUTE) {
+ sh->add_input(0, 1, 0x0F);
+ sh->add_input(1, 1, 0x0F);
}
bool ps_interp = ctx.hw_class >= HW_CLASS_EVERGREEN
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Mesa (master): r600/sb: lds ops have no dst register.
Module: Mesa
Branch: master
Commit: 1ca2eb3bf32dbb6781343d82ee4c72caa4c4e8d5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1ca2eb3bf32dbb6781343d82ee4c72caa4c4e8d5
Author: Dave Airlie
Date: Wed Jan 10 03:56:37 2018 +
r600/sb: lds ops have no dst register.
Although these are op3s they don't have a dst reg.
Acked-By: Roland Scheidegger
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/sb/sb_bc_dump.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/sb/sb_bc_dump.cpp
b/src/gallium/drivers/r600/sb/sb_bc_dump.cpp
index 72a1b24467..3b5d9e77b2 100644
--- a/src/gallium/drivers/r600/sb/sb_bc_dump.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_dump.cpp
@@ -232,7 +232,7 @@ static void print_dst(sb_ostream &s, bc_alu &alu)
reg_char = 'T';
}
- if (alu.write_mask || alu.op_ptr->src_count == 3) {
+ if (alu.write_mask || (alu.op_ptr->src_count == 3 && alu.op <
LDS_OP2_LDS_ADD)) {
s << reg_char;
print_sel(s, sel, alu.dst_rel, alu.index_mode, 0);
} else {
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Mesa (master): r600/sb: add gcm support to avoid clause between lds read/queue read
Module: Mesa
Branch: master
Commit: 5002dd40520deba025d81c824d41e292db344a7b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5002dd40520deba025d81c824d41e292db344a7b
Author: Dave Airlie
Date: Wed Jan 10 04:30:23 2018 +
r600/sb: add gcm support to avoid clause between lds read/queue read
You have to schedule LDS_READ_RET _, x and MOV reg, LDS_OQ_A_POP
in the same basic block/clause. This makes sure once we've issues
and MOV we don't add another block until we balance it with an
LDS read.
Acked-By: Roland Scheidegger
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/sb/sb_gcm.cpp | 15 ++-
src/gallium/drivers/r600/sb/sb_pass.h | 4 +++-
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/sb/sb_gcm.cpp
b/src/gallium/drivers/r600/sb/sb_gcm.cpp
index fbebe3427d..7776a10fc8 100644
--- a/src/gallium/drivers/r600/sb/sb_gcm.cpp
+++ b/src/gallium/drivers/r600/sb/sb_gcm.cpp
@@ -366,6 +366,9 @@ void gcm::bu_sched_bb(bb_node* bb) {
continue;
}
+ if (sq != SQ_ALU && outstanding_lds_oq)
+ continue;
+
if (!bu_ready_next[sq].empty())
bu_ready[sq].splice(bu_ready[sq].end(),
bu_ready_next[sq]);
@@ -388,7 +391,7 @@ void gcm::bu_sched_bb(bb_node* bb) {
}
// simple heuristic to limit register pressure,
- if (sq == SQ_ALU && live_count > rp_threshold &&
+ if (sq == SQ_ALU && live_count > rp_threshold
&& !outstanding_lds_oq &&
(!bu_ready[SQ_TEX].empty() ||
!bu_ready[SQ_VTX].empty() ||
!bu_ready_next[SQ_TEX].empty()
||
@@ -423,6 +426,12 @@ void gcm::bu_sched_bb(bb_node* bb) {
check_alu_ready_count(24))
break;
+
+ if (sq == SQ_ALU && n->consumes_lds_oq() &&
+ (bu_ready[SQ_TEX].size() ||
bu_ready[SQ_VTX].size() || bu_ready[SQ_GDS].size())) {
+ GCM_DUMP( sblog << "switching
scheduling due to lds op\n"; );
+ break;
+ }
bu_ready[sq].pop_front();
if (sq != SQ_CF) {
@@ -513,6 +522,10 @@ void gcm::bu_schedule(container_node* c, node* n) {
assert(op_map[n].bottom_bb == bu_bb);
+ if (n->produces_lds_oq())
+ outstanding_lds_oq--;
+ if (n->consumes_lds_oq())
+ outstanding_lds_oq++;
bu_release_defs(n->src, true);
bu_release_defs(n->dst, false);
diff --git a/src/gallium/drivers/r600/sb/sb_pass.h
b/src/gallium/drivers/r600/sb/sb_pass.h
index e878f8c70c..b5818039c2 100644
--- a/src/gallium/drivers/r600/sb/sb_pass.h
+++ b/src/gallium/drivers/r600/sb/sb_pass.h
@@ -223,6 +223,7 @@ class gcm : public pass {
sched_queue ready;
sched_queue ready_above;
+ unsigned outstanding_lds_oq;
container_node pending;
struct op_info {
@@ -263,7 +264,8 @@ public:
gcm(shader &sh) : pass(sh),
bu_ready(), bu_ready_next(), bu_ready_early(),
- ready(), op_map(), uses(), nuc_stk(1), ucs_level(),
+ ready(), outstanding_lds_oq(),
+ op_map(), uses(), nuc_stk(1), ucs_level(),
bu_bb(), pending_defs(), pending_nodes(), cur_sq(),
live(), live_count(), pending_exec_mask_update() {}
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Mesa (master): r600/sb: hit the scheduler with a big hammer to avoid lds splits.
Module: Mesa
Branch: master
Commit: 71a50de4fcf8202b500d51916100e8e905de3c44
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=71a50de4fcf8202b500d51916100e8e905de3c44
Author: Dave Airlie
Date: Wed Jan 10 04:38:07 2018 +
r600/sb: hit the scheduler with a big hammer to avoid lds splits.
This tries to avoid an lds queue read getting scheduled separately
from an lds ret read, the non-sb code uses the same style of hammer,
this isn't foolproof.
We can do better, but it's a bit tricky, as you have to scan ahead
and either schedule more lds oq moves and more lds reads and that
could lead to you running out of space anyways.
Acked-By: Roland Scheidegger
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/sb/sb_sched.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/gallium/drivers/r600/sb/sb_sched.cpp
b/src/gallium/drivers/r600/sb/sb_sched.cpp
index 26e4811b1c..1feef585df 100644
--- a/src/gallium/drivers/r600/sb/sb_sched.cpp
+++ b/src/gallium/drivers/r600/sb/sb_sched.cpp
@@ -2034,6 +2034,9 @@ bool alu_clause_tracker::check_clause_limits() {
// ...and index registers
reserve_slots += (current_idx[0] != NULL) + (current_idx[1] != NULL);
+ if (gt.get_consumes_lds_oqa() && !outstanding_lds_oqa_reads)
+ reserve_slots += 60;
+
if (slot_count + slots > MAX_ALU_SLOTS - reserve_slots)
return false;
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Mesa (master): ac: fix buffer overflow bug in 64bit SSBO loads
Module: Mesa Branch: master Commit: e2b9296146746635cd631c5212ae56f0cd270820 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2b9296146746635cd631c5212ae56f0cd270820 Author: Timothy Arceri Date: Tue Jan 16 17:45:30 2018 +1100 ac: fix buffer overflow bug in 64bit SSBO loads Fixes: 441ee1e65b04 "radv/ac: Implement Float64 SSBO loads" Reviewed-by: Marek Olšák --- src/amd/common/ac_nir_to_llvm.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index 1dc64f87cc..e07330ca5c 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -2588,8 +2588,11 @@ static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx, ctx->ac.i1false, }; - results[i] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0); + int idx = i; + if (instr->dest.ssa.bit_size == 64) + idx = i > 1 ? 1 : 0; + results[idx] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0); } assume(results[0]); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600/sb: add initial support for parsing lds operations.
Module: Mesa
Branch: master
Commit: 9f3a1e9b0c75a202ede2718bd4d2b2a61b539e5d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f3a1e9b0c75a202ede2718bd4d2b2a61b539e5d
Author: Dave Airlie
Date: Wed Jan 10 04:20:52 2018 +
r600/sb: add initial support for parsing lds operations.
This handles parsing the LDS ops and queue accessess.
Acked-By: Roland Scheidegger
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/sb/sb_bc_parser.cpp | 52 ++--
1 file changed, 50 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
index 8ab4083a3c..970e4141d5 100644
--- a/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_parser.cpp
@@ -384,7 +384,40 @@ int bc_parser::prepare_alu_group(cf_node* cf,
alu_group_node *g) {
unsigned flags = n->bc.op_ptr->flags;
- if (flags & AF_PRED) {
+ if (flags & AF_LDS) {
+ bool need_rw = false, need_oqa = false, need_oqb =
false;
+ int ndst = 0, ncount = 0;
+
+ /* all non-read operations have side effects */
+ if (n->bc.op != LDS_OP2_LDS_READ2_RET &&
+ n->bc.op != LDS_OP1_LDS_READ_REL_RET &&
+ n->bc.op != LDS_OP1_LDS_READ_RET) {
+ n->flags |= NF_DONT_KILL;
+ ndst++;
+ need_rw = true;
+ }
+
+ if (n->bc.op >= LDS_OP2_LDS_ADD_RET && n->bc.op <=
LDS_OP1_LDS_USHORT_READ_RET) {
+ need_oqa = true;
+ ndst++;
+ }
+
+ if (n->bc.op == LDS_OP2_LDS_READ2_RET || n->bc.op ==
LDS_OP1_LDS_READ_REL_RET) {
+ need_oqb = true;
+ ndst++;
+ }
+
+ n->dst.resize(ndst);
+ if (need_oqa)
+ n->dst[ncount++] =
sh->get_special_value(SV_LDS_OQA);
+ if (need_oqb)
+ n->dst[ncount++] =
sh->get_special_value(SV_LDS_OQB);
+ if (need_rw)
+ n->dst[ncount++] =
sh->get_special_value(SV_LDS_RW);
+
+ n->flags |= NF_DONT_MOVE | NF_DONT_HOIST;
+
+ } else if (flags & AF_PRED) {
n->dst.resize(3);
if (n->bc.update_pred)
n->dst[1] = sh->get_special_value(SV_ALU_PRED);
@@ -417,7 +450,7 @@ int bc_parser::prepare_alu_group(cf_node* cf,
alu_group_node *g) {
n->flags |= NF_DONT_HOIST;
- } else if (n->bc.op_ptr->src_count == 3 || n->bc.write_mask) {
+ } else if ((n->bc.op_ptr->src_count == 3 || n->bc.write_mask)
&& !(flags & AF_LDS)) {
assert(!n->bc.dst_rel || n->bc.index_mode ==
INDEX_AR_X);
value *v = sh->get_gpr_value(false, n->bc.dst_gpr,
n->bc.dst_chan,
@@ -487,6 +520,21 @@ int bc_parser::prepare_alu_group(cf_node* cf,
alu_group_node *g) {
// param index as equal instructions and leave
only one of them
n->src[s] =
sh->get_special_ro_value(sel_chan(src.sel,
n->bc.slot));
+ } else if (ctx.is_lds_oq(src.sel)) {
+ switch (src.sel) {
+ case ALU_SRC_LDS_OQ_A:
+ case ALU_SRC_LDS_OQ_B:
+ assert(!"Unsupported LDS queue access
in SB");
+ break;
+ case ALU_SRC_LDS_OQ_A_POP:
+ n->src[s] =
sh->get_special_value(SV_LDS_OQA);
+ break;
+ case ALU_SRC_LDS_OQ_B_POP:
+ n->src[s] =
sh->get_special_value(SV_LDS_OQB);
+ break;
+ }
+ n->flags |= NF_DONT_HOIST | NF_DONT_MOVE;
+
} else {
switch (src.sel) {
case ALU_SRC_0:
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Mesa (master): r600/sb: disable if conversion for hs
Module: Mesa Branch: master Commit: 795512b235730c2ddb834b3082170521abb59811 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=795512b235730c2ddb834b3082170521abb59811 Author: Dave Airlie Date: Wed Jan 10 03:57:52 2018 + r600/sb: disable if conversion for hs This fixes bad interactions with the LDS special values. Acked-By: Roland Scheidegger Signed-off-by: Dave Airlie --- src/gallium/drivers/r600/sb/sb_core.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/r600/sb/sb_core.cpp b/src/gallium/drivers/r600/sb/sb_core.cpp index cdc2862d36..5049b67784 100644 --- a/src/gallium/drivers/r600/sb/sb_core.cpp +++ b/src/gallium/drivers/r600/sb/sb_core.cpp @@ -191,7 +191,7 @@ int r600_sb_bytecode_process(struct r600_context *rctx, // if conversion breaks the dependency tracking between CF_EMIT ops when it removes // the phi nodes for SV_GEOMETRY_EMIT. Just disable it for GS - if (sh->target != TARGET_GS) + if (sh->target != TARGET_GS && sh->target != TARGET_HS) SB_RUN_PASS(if_conversion, 1); // if_conversion breaks info about uses, but next pass (peephole) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600/sb: add lds related peepholes.
Module: Mesa
Branch: master
Commit: 44a27cdceca0b835d964ca16db68721816ae868f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=44a27cdceca0b835d964ca16db68721816ae868f
Author: Dave Airlie
Date: Wed Jan 10 06:08:48 2018 +
r600/sb: add lds related peepholes.
if no destination:
a) convert _RET instructions to non _RET variants if no dst
b) set src0 to undefined if it's a READ, this should get DCE then.
Acked-By: Roland Scheidegger
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/sb/sb_peephole.cpp | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/sb/sb_peephole.cpp
b/src/gallium/drivers/r600/sb/sb_peephole.cpp
index 49a6965b1f..4390a8f525 100644
--- a/src/gallium/drivers/r600/sb/sb_peephole.cpp
+++ b/src/gallium/drivers/r600/sb/sb_peephole.cpp
@@ -68,7 +68,14 @@ void peephole::run_on(container_node* c) {
if (n->is_alu_inst()) {
alu_node *a = static_cast(n);
- if (a->bc.op_ptr->flags &
+ if (a->bc.op_ptr->flags & AF_LDS) {
+ if (!a->dst[0]) {
+ if (a->bc.op >=
LDS_OP2_LDS_ADD_RET && a->bc.op <= LDS_OP3_LDS_MSKOR_RET)
+ a->bc.set_op(a->bc.op -
LDS_OP2_LDS_ADD_RET + LDS_OP2_LDS_ADD);
+ if (a->bc.op ==
LDS_OP1_LDS_READ_RET)
+ a->src[0] =
sh.get_undef_value();
+ }
+ } else if (a->bc.op_ptr->flags &
(AF_PRED | AF_SET | AF_CMOV |
AF_KILL)) {
optimize_cc_op(a);
} else if (a->bc.op == ALU_OP1_FLT_TO_INT) {
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Mesa (master): r600/sb: adding lds oq tracking to the scheduler
Module: Mesa
Branch: master
Commit: 46549bd6b62f251c588bead63866721f7cf9ea1c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=46549bd6b62f251c588bead63866721f7cf9ea1c
Author: Dave Airlie
Date: Wed Jan 10 04:36:37 2018 +
r600/sb: adding lds oq tracking to the scheduler
This adds support for tracking the lds oq read/writes
so can avoid scheduling other things in between.
This patch just adds the tracking and assert to show
problems.
Acked-By: Roland Scheidegger
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/sb/sb_sched.cpp | 13 ++---
src/gallium/drivers/r600/sb/sb_sched.h | 5 +
2 files changed, 15 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/r600/sb/sb_sched.cpp
b/src/gallium/drivers/r600/sb/sb_sched.cpp
index 6d7ab671ff..26e4811b1c 100644
--- a/src/gallium/drivers/r600/sb/sb_sched.cpp
+++ b/src/gallium/drivers/r600/sb/sb_sched.cpp
@@ -312,7 +312,7 @@ alu_group_tracker::alu_group_tracker(shader &sh)
gpr(), lt(), slots(),
max_slots(sh.get_ctx().is_cayman() ? 4 : 5),
has_mova(), uses_ar(), has_predset(), has_kill(),
- updates_exec_mask(), chan_count(), interp_param(), next_id() {
+ updates_exec_mask(), consumes_lds_oqa(), produces_lds_oqa(),
chan_count(), interp_param(), next_id() {
available_slots = sh.get_ctx().has_trans ? 0x1F : 0x0F;
}
@@ -680,6 +680,8 @@ void alu_group_tracker::reset(bool keep_packed) {
memset(slots, 0, sizeof(slots));
vmap.clear();
next_id = 0;
+ produces_lds_oqa = 0;
+ consumes_lds_oqa = 0;
has_mova = false;
uses_ar = false;
has_predset = false;
@@ -703,7 +705,8 @@ void alu_group_tracker::update_flags(alu_node* n) {
has_mova |= (flags & AF_MOVA);
has_predset |= (flags & AF_ANY_PRED);
uses_ar |= n->uses_ar();
-
+ consumes_lds_oqa |= n->consumes_lds_oq();
+ produces_lds_oqa |= n->produces_lds_oq();
if (flags & AF_ANY_PRED) {
if (n->dst[2] != NULL)
updates_exec_mask = true;
@@ -1958,6 +1961,7 @@ void alu_kcache_tracker::reset() {
void alu_clause_tracker::reset() {
group = 0;
slot_count = 0;
+ outstanding_lds_oqa_reads = 0;
grp0.reset();
grp1.reset();
}
@@ -1966,7 +1970,7 @@ alu_clause_tracker::alu_clause_tracker(shader &sh)
: sh(sh), kt(sh.get_ctx().hw_class), slot_count(),
grp0(sh), grp1(sh),
group(), clause(),
- push_exec_mask(),
+ push_exec_mask(), outstanding_lds_oqa_reads(),
current_ar(), current_pr(), current_idx() {}
void alu_clause_tracker::emit_group() {
@@ -1988,6 +1992,8 @@ void alu_clause_tracker::emit_group() {
clause->push_front(g);
+ outstanding_lds_oqa_reads += grp().get_consumes_lds_oqa();
+ outstanding_lds_oqa_reads -= grp().get_produces_lds_oqa();
slot_count += grp().slot_count();
new_group();
@@ -2000,6 +2006,7 @@ void alu_clause_tracker::emit_clause(container_node *c) {
kt.init_clause(clause->bc);
+ assert(!outstanding_lds_oqa_reads);
assert(!current_ar);
assert(!current_pr);
diff --git a/src/gallium/drivers/r600/sb/sb_sched.h
b/src/gallium/drivers/r600/sb/sb_sched.h
index 5a2663442b..91a34e078d 100644
--- a/src/gallium/drivers/r600/sb/sb_sched.h
+++ b/src/gallium/drivers/r600/sb/sb_sched.h
@@ -127,6 +127,8 @@ class alu_group_tracker {
bool has_kill;
bool updates_exec_mask;
+ bool consumes_lds_oqa;
+ bool produces_lds_oqa;
unsigned chan_count[4];
// param index + 1 (0 means that group doesn't refer to Params)
@@ -166,6 +168,8 @@ public:
unsigned literal_slot_count() { return (literal_count() + 1) >> 1; };
unsigned slot_count() { return inst_count() + literal_slot_count(); }
+ bool get_consumes_lds_oqa() { return consumes_lds_oqa; }
+ bool get_produces_lds_oqa() { return produces_lds_oqa; }
alu_group_node* emit();
rp_kcache_tracker& kcache() { return kc; }
@@ -212,6 +216,7 @@ class alu_clause_tracker {
bool push_exec_mask;
+ unsigned outstanding_lds_oqa_reads;
public:
container_node conflict_nodes;
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Mesa (master): r600/sb: fix a bug emitting ar load from a constant.
Module: Mesa
Branch: master
Commit: 68b976bd91d1a23d2d04f383ab194980b5084970
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=68b976bd91d1a23d2d04f383ab194980b5084970
Author: Dave Airlie
Date: Wed Jan 10 03:41:57 2018 +
r600/sb: fix a bug emitting ar load from a constant.
Some tess shaders were doing MOVA_INT _, c0.x on cayman, and then
hitting an assert in sb_bc_finalize.cpp:translate_kcache.
This makes sure the toplevel kcache tracker gets updated,
and the clause gets fixed up.
Reviewed-by: Roland Scheidegger
Cc:
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/sb/sb_sched.cpp | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/gallium/drivers/r600/sb/sb_sched.cpp
b/src/gallium/drivers/r600/sb/sb_sched.cpp
index 2fbec2f77e..4158317765 100644
--- a/src/gallium/drivers/r600/sb/sb_sched.cpp
+++ b/src/gallium/drivers/r600/sb/sb_sched.cpp
@@ -1130,6 +1130,9 @@ void post_scheduler::emit_clause() {
if (alu.current_ar) {
emit_load_ar();
process_group();
+ if (!alu.check_clause_limits()) {
+ // Can't happen since clause only contains
MOVA/CF_SET_IDX0/1
+ }
alu.emit_group();
}
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Mesa (master): r600: emit 0 gds_op for tf write.
Module: Mesa
Branch: master
Commit: 2bd01adf146b3a16179a5b1305444305ce26ed2e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2bd01adf146b3a16179a5b1305444305ce26ed2e
Author: Dave Airlie
Date: Wed Jan 10 02:54:33 2018 +
r600: emit 0 gds_op for tf write.
This field is ignored for tf writes so should be 0.
Reviewed-by: Roland Scheidegger
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/eg_asm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/eg_asm.c
b/src/gallium/drivers/r600/eg_asm.c
index 8f9d1b85f2..f8651bdff5 100644
--- a/src/gallium/drivers/r600/eg_asm.c
+++ b/src/gallium/drivers/r600/eg_asm.c
@@ -225,9 +225,10 @@ int eg_bytecode_gds_build(struct r600_bytecode *bc, struct
r600_bytecode_gds *gd
{
unsigned gds_op = (r600_isa_fetch_opcode(bc->isa->hw_class, gds->op) >>
8) & 0x3f;
unsigned opcode;
- if (gds->op == FETCH_OP_TF_WRITE)
+ if (gds->op == FETCH_OP_TF_WRITE) {
opcode = 5;
- else
+ gds_op = 0;
+ } else
opcode = 4;
bc->bytecode[id++] = S_SQ_MEM_GDS_WORD0_MEM_INST(2) |
S_SQ_MEM_GDS_WORD0_MEM_OP(opcode) |
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Mesa (master): r600/sb: start adding GDS support
Module: Mesa
Branch: master
Commit: da977ad9074707932b9dc1f7c52b5427ce920c13
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=da977ad9074707932b9dc1f7c52b5427ce920c13
Author: Dave Airlie
Date: Thu Dec 7 02:14:45 2017 +
r600/sb: start adding GDS support
This adds support for GDS ops to sb backend.
This seems to work for atomics and tess factor writes.
Acked-By: Roland Scheidegger
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_isa.h| 2 +-
src/gallium/drivers/r600/sb/sb_bc.h| 7
src/gallium/drivers/r600/sb/sb_bc_builder.cpp | 44 +-
src/gallium/drivers/r600/sb/sb_bc_decoder.cpp | 9 +-
src/gallium/drivers/r600/sb/sb_bc_dump.cpp | 13 ++--
src/gallium/drivers/r600/sb/sb_bc_finalize.cpp | 7
src/gallium/drivers/r600/sb/sb_bc_parser.cpp | 11 +--
src/gallium/drivers/r600/sb/sb_dump.cpp| 1 +
src/gallium/drivers/r600/sb/sb_gcm.cpp | 20 +---
src/gallium/drivers/r600/sb/sb_ir.h| 3 +-
src/gallium/drivers/r600/sb/sb_peephole.cpp| 14 +++-
src/gallium/drivers/r600/sb/sb_ra_init.cpp | 2 ++
src/gallium/drivers/r600/sb/sb_shader.cpp | 3 ++
13 files changed, 123 insertions(+), 13 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_isa.h
b/src/gallium/drivers/r600/r600_isa.h
index b5a36b4e80..f6e26976c5 100644
--- a/src/gallium/drivers/r600/r600_isa.h
+++ b/src/gallium/drivers/r600/r600_isa.h
@@ -115,7 +115,7 @@ enum alu_op_flags
AF_CC_LE= (5U << AF_CC_SHIFT),
};
-/* flags for FETCH instructions (TEX/VTX) */
+/* flags for FETCH instructions (TEX/VTX/GDS) */
enum fetch_op_flags
{
FF_GDS = (1<<0),
diff --git a/src/gallium/drivers/r600/sb/sb_bc.h
b/src/gallium/drivers/r600/sb/sb_bc.h
index fed041cf50..fc3fa5082d 100644
--- a/src/gallium/drivers/r600/sb/sb_bc.h
+++ b/src/gallium/drivers/r600/sb/sb_bc.h
@@ -401,6 +401,7 @@ enum sched_queue_id {
SQ_ALU,
SQ_TEX,
SQ_VTX,
+ SQ_GDS,
SQ_NUM
};
@@ -580,6 +581,11 @@ struct bc_fetch {
unsigned mega_fetch:1;
unsigned src2_gpr:7; /* for GDS */
+ unsigned alloc_consume:1;
+ unsigned uav_id:4;
+ unsigned uav_index_mode:2;
+ unsigned bcast_first_req:1;
+
void set_op(unsigned op) { this->op = op; op_ptr = r600_isa_fetch(op); }
};
@@ -966,6 +972,7 @@ private:
int build_fetch_clause(cf_node *n);
int build_fetch_tex(fetch_node *n);
int build_fetch_vtx(fetch_node *n);
+ int build_fetch_gds(fetch_node *n);
};
} // namespace r600_sb
diff --git a/src/gallium/drivers/r600/sb/sb_bc_builder.cpp
b/src/gallium/drivers/r600/sb/sb_bc_builder.cpp
index b0df3d9a54..ea91e197c0 100644
--- a/src/gallium/drivers/r600/sb/sb_bc_builder.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_builder.cpp
@@ -129,7 +129,9 @@ int bc_builder::build_fetch_clause(cf_node* n) {
I != E; ++I) {
fetch_node *f = static_cast(*I);
- if (f->bc.op_ptr->flags & FF_VTX)
+ if (f->bc.op_ptr->flags & FF_GDS)
+ build_fetch_gds(f);
+ else if (f->bc.op_ptr->flags & FF_VTX)
build_fetch_vtx(f);
else
build_fetch_tex(f);
@@ -558,6 +560,46 @@ int bc_builder::build_fetch_tex(fetch_node* n) {
return 0;
}
+int bc_builder::build_fetch_gds(fetch_node *n) {
+ const bc_fetch &bc = n->bc;
+ const fetch_op_info *fop = bc.op_ptr;
+ unsigned gds_op = (ctx.fetch_opcode(bc.op) >> 8) & 0x3f;
+ unsigned mem_op = 4;
+ assert(fop->flags && FF_GDS);
+
+ if (bc.op == FETCH_OP_TF_WRITE) {
+ mem_op = 5;
+ gds_op = 0;
+ }
+
+ bb << MEM_GDS_WORD0_EGCM()
+ .MEM_INST(2)
+ .MEM_OP(mem_op)
+ .SRC_GPR(bc.src_gpr)
+ .SRC_SEL_X(bc.src_sel[0])
+ .SRC_SEL_Y(bc.src_sel[1])
+ .SRC_SEL_Z(bc.src_sel[2]);
+
+ bb << MEM_GDS_WORD1_EGCM()
+ .DST_GPR(bc.dst_gpr)
+ .DST_REL_MODE(bc.dst_rel)
+ .GDS_OP(gds_op)
+ .SRC_GPR(bc.src2_gpr)
+ .UAV_INDEX_MODE(bc.uav_index_mode)
+ .UAV_ID(bc.uav_id)
+ .ALLOC_CONSUME(bc.alloc_consume)
+ .BCAST_FIRST_REQ(bc.bcast_first_req);
+
+ bb << MEM_GDS_WORD2_EGCM()
+ .DST_SEL_X(bc.dst_sel[0])
+ .DST_SEL_Y(bc.dst_sel[1])
+ .DST_SEL_Z(bc.dst_sel[2])
+ .DST_SEL_W(bc.dst_sel[3]);
+
+ bb << 0;
+ return 0;
+}
+
int bc_builder::build_fetch_vtx(fetch_node* n) {
const bc_fetch &bc = n->bc;
const fetch_op_info *fop = bc.op_ptr;
diff --git a/src/gallium/drivers/r600/sb/sb_bc_decoder.cpp
b/src/gallium/drivers/r600/sb/sb_bc_decoder.cpp
index 8712abe5f7..1fa580e66d 100644
--- a/src/gallium
Mesa (master): r600/sb: handle lds special dest registers.
Module: Mesa
Branch: master
Commit: 046cf68cadd04a1e1eb89476614c334ac702f0ce
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=046cf68cadd04a1e1eb89476614c334ac702f0ce
Author: Dave Airlie
Date: Wed Jan 10 04:25:41 2018 +
r600/sb: handle lds special dest registers.
This adds lds to the geom emit handling
Acked-By: Roland Scheidegger
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/sb/sb_bc_finalize.cpp | 2 +-
src/gallium/drivers/r600/sb/sb_sched.cpp | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
b/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
index d377a3950a..099b295f18 100644
--- a/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
@@ -294,7 +294,7 @@ void bc_finalizer::finalize_alu_group(alu_group_node* g,
node *prev_node) {
value *d = n->dst.empty() ? NULL : n->dst[0];
if (d && d->is_special_reg()) {
- assert((n->bc.op_ptr->flags & AF_MOVA) ||
d->is_geometry_emit());
+ assert((n->bc.op_ptr->flags & AF_MOVA) ||
d->is_geometry_emit() || d->is_lds_oq() || d->is_lds_access());
d = NULL;
}
diff --git a/src/gallium/drivers/r600/sb/sb_sched.cpp
b/src/gallium/drivers/r600/sb/sb_sched.cpp
index 4158317765..6d7ab671ff 100644
--- a/src/gallium/drivers/r600/sb/sb_sched.cpp
+++ b/src/gallium/drivers/r600/sb/sb_sched.cpp
@@ -1663,7 +1663,7 @@ unsigned post_scheduler::try_add_instruction(node *n) {
value *d = a->dst.empty() ? NULL : a->dst[0];
if (d && d->is_special_reg()) {
- assert((a->bc.op_ptr->flags & AF_MOVA) ||
d->is_geometry_emit());
+ assert((a->bc.op_ptr->flags & AF_MOVA) ||
d->is_geometry_emit() || d->is_lds_oq() || d->is_lds_access());
d = NULL;
}
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Mesa (master): r600/sb: update last_cf if alu is the last clause
Module: Mesa
Branch: master
Commit: 2f2cef385fd0f96f5cca3d5ccc48184bbc681831
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f2cef385fd0f96f5cca3d5ccc48184bbc681831
Author: Dave Airlie
Date: Wed Jan 10 03:46:50 2018 +
r600/sb: update last_cf if alu is the last clause
It's rare to have a final alu clause on normal shaders (exports)
but tess shaders write to LDS as their output, so we see some
alu clauses, and the CF_END get put in the wrong place.
This makes sure to update last_cf correctly.
Acked-By: Roland Scheidegger
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/sb/sb_bc_finalize.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
b/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
index c20640e476..2ec4db624a 100644
--- a/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
@@ -266,6 +266,7 @@ void bc_finalizer::run_on(container_node* c) {
}
}
}
+ last_cf = c;
} else if (n->is_fetch_inst()) {
finalize_fetch(static_cast(n));
} else if (n->is_cf_inst()) {
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Mesa (master): radv: Initialize DCC on transition from preinitialized.
Module: Mesa
Branch: master
Commit: 2ce11ac11fee594ca01608c4006b38c0c8ea37ff
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2ce11ac11fee594ca01608c4006b38c0c8ea37ff
Author: Bas Nieuwenhuizen
Date: Thu Jan 11 13:21:50 2018 +0100
radv: Initialize DCC on transition from preinitialized.
Looks like the decompress does not handle invalid encodings well,
which happens with random memory. Of course apps should not use it
with random memory, but they are allowed to
Fixes: 44fcf58744 "radv: Disable DCC for GENERAL layout and compute transfer
dest."
Reviewed-by: Dave Airlie
---
src/amd/vulkan/radv_cmd_buffer.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 67799a13cc..172f95e7c9 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -4026,7 +4026,9 @@ static void radv_handle_dcc_image_transition(struct
radv_cmd_buffer *cmd_buffer,
unsigned dst_queue_mask,
const VkImageSubresourceRange
*range)
{
- if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
+ if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) {
+ radv_initialize_dcc(cmd_buffer, image, 0xu);
+ } else if (src_layout == VK_IMAGE_LAYOUT_UNDEFINED) {
radv_initialize_dcc(cmd_buffer, image,
radv_layout_dcc_compressed(image,
dst_layout, dst_queue_mask) ?
0x20202020u : 0xu);
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Mesa (master): r600/shader: only emit add instruction if param has a value.
Module: Mesa
Branch: master
Commit: 7efcafce7c6dd3dc9e71c7d35d6f7ebfd88f106b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7efcafce7c6dd3dc9e71c7d35d6f7ebfd88f106b
Author: Dave Airlie
Date: Wed Jan 10 02:56:15 2018 +
r600/shader: only emit add instruction if param has a value.
Just saves a pointless a = a + 0;
Reviewed-by: Roland Scheidegger
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/r600_shader.c | 14 --
1 file changed, 8 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 623e6f7f70..cfc3400f92 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -2864,12 +2864,14 @@ static int r600_tess_factor_read(struct r600_shader_ctx
*ctx,
if (r)
return r;
- r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
- temp_reg, 0,
- temp_reg, 0,
- V_SQ_ALU_SRC_LITERAL, param * 16);
- if (r)
- return r;
+ if (param) {
+ r = single_alu_op2(ctx, ALU_OP2_ADD_INT,
+ temp_reg, 0,
+ temp_reg, 0,
+ V_SQ_ALU_SRC_LITERAL, param * 16);
+ if (r)
+ return r;
+ }
do_lds_fetch_values(ctx, temp_reg, dreg, ((1u << nc) - 1));
return 0;
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Mesa (master): r600/sb: introduce special register values for lds support.
Module: Mesa
Branch: master
Commit: 09c1c13c4442148e45a4aeac3425382bbe90e8cd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=09c1c13c4442148e45a4aeac3425382bbe90e8cd
Author: Dave Airlie
Date: Wed Jan 10 03:52:50 2018 +
r600/sb: introduce special register values for lds support.
For LDS read/write ordering we use the LDS_RW value, reads
will wait on previous writes.
For LDS read/read from LDS queue ordering we use the LDS_OQ
values, we define two for now, though initially we'll just
support OQA.
Also add the check for the lds oq values
Acked-By: Roland Scheidegger
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/sb/sb_bc.h | 4
src/gallium/drivers/r600/sb/sb_ir.h | 27 ++-
src/gallium/drivers/r600/sb/sb_valtable.cpp | 3 +++
3 files changed, 33 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/sb/sb_bc.h
b/src/gallium/drivers/r600/sb/sb_bc.h
index fc3fa5082d..3a3bae9d44 100644
--- a/src/gallium/drivers/r600/sb/sb_bc.h
+++ b/src/gallium/drivers/r600/sb/sb_bc.h
@@ -722,6 +722,10 @@ public:
return ((sel >= 128 && sel < 192) || (sel >= 256 && sel < 320));
}
+ bool is_lds_oq(unsigned sel) {
+ return (sel >= 0xdb && sel <= 0xde);
+ }
+
const char * get_hw_class_name();
const char * get_hw_chip_name();
diff --git a/src/gallium/drivers/r600/sb/sb_ir.h
b/src/gallium/drivers/r600/sb/sb_ir.h
index 2390babfcf..bee947504e 100644
--- a/src/gallium/drivers/r600/sb/sb_ir.h
+++ b/src/gallium/drivers/r600/sb/sb_ir.h
@@ -42,7 +42,10 @@ enum special_regs {
SV_EXEC_MASK,
SV_AR_INDEX,
SV_VALID_MASK,
- SV_GEOMETRY_EMIT
+ SV_GEOMETRY_EMIT,
+ SV_LDS_RW,
+ SV_LDS_OQA,
+ SV_LDS_OQB,
};
class node;
@@ -495,6 +498,12 @@ public:
bool is_geometry_emit() {
return is_special_reg() && select == sel_chan(SV_GEOMETRY_EMIT,
0);
}
+ bool is_lds_access() {
+ return is_special_reg() && select == sel_chan(SV_LDS_RW, 0);
+ }
+ bool is_lds_oq() {
+ return is_special_reg() && (select == sel_chan(SV_LDS_OQA, 0)
|| select == sel_chan(SV_LDS_OQB, 0));
+ }
node* any_def() {
assert(!(def && adef));
@@ -833,6 +842,22 @@ public:
return vec_uses_ar(dst) || vec_uses_ar(src);
}
+ bool vec_uses_lds_oq(vvec &vv) {
+ for (vvec::iterator I = vv.begin(), E = vv.end(); I != E; ++I) {
+ value *v = *I;
+ if (v && v->is_lds_oq())
+ return true;
+ }
+ return false;
+ }
+
+ bool consumes_lds_oq() {
+ return vec_uses_lds_oq(src);
+ }
+
+ bool produces_lds_oq() {
+ return vec_uses_lds_oq(dst);
+ }
region_node* get_parent_region();
diff --git a/src/gallium/drivers/r600/sb/sb_valtable.cpp
b/src/gallium/drivers/r600/sb/sb_valtable.cpp
index a85537c2ad..41cfbf0946 100644
--- a/src/gallium/drivers/r600/sb/sb_valtable.cpp
+++ b/src/gallium/drivers/r600/sb/sb_valtable.cpp
@@ -56,6 +56,9 @@ sb_ostream& operator << (sb_ostream &o, value &v) {
case SV_EXEC_MASK: o << "EM"; break;
case SV_VALID_MASK: o << "VM"; break;
case SV_GEOMETRY_EMIT: o << "GEOMETRY_EMIT"; break;
+ case SV_LDS_RW: o << "LDS_RW"; break;
+ case SV_LDS_OQA: o << "LDS_OQA"; break;
+ case SV_LDS_OQB: o << "LDS_OQB"; break;
default: o << "???specialreg"; break;
}
break;
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Mesa (master): i965: Replace cpu_map pointers with a "use_shadow_copy" boolean.
Module: Mesa
Branch: master
Commit: 02c1c25b1a620a336f2e18d39bba188635363f24
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=02c1c25b1a620a336f2e18d39bba188635363f24
Author: Kenneth Graunke
Date: Fri Jan 5 11:44:50 2018 -0800
i965: Replace cpu_map pointers with a "use_shadow_copy" boolean.
Having a boolean for "we're using malloc'd shadow copies for all
buffers" is cleaner than having a cpu_map pointer for each. It was
okay when we had one buffer, but this is more obvious.
Reviewed-by: Iago Toral Quiroga
---
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 39 +--
2 files changed, 20 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 3cbc2e8c13..79e9f49a38 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -473,7 +473,6 @@ struct brw_reloc_list {
struct brw_growing_bo {
struct brw_bo *bo;
uint32_t *map;
- uint32_t *cpu_map;
};
struct intel_batchbuffer {
@@ -492,6 +491,7 @@ struct intel_batchbuffer {
uint32_t state_used;
enum brw_gpu_ring ring;
+ bool use_shadow_copy;
bool use_batch_first;
bool needs_sol_reset;
bool state_base_address_emitted;
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index a17e169925..bfb50053e7 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -83,12 +83,12 @@ intel_batchbuffer_init(struct brw_context *brw)
struct intel_batchbuffer *batch = &brw->batch;
const struct gen_device_info *devinfo = &screen->devinfo;
- if (!devinfo->has_llc) {
- batch->batch.cpu_map = malloc(BATCH_SZ);
- batch->batch.map = batch->batch.cpu_map;
+ batch->use_shadow_copy = !devinfo->has_llc;
+
+ if (batch->use_shadow_copy) {
+ batch->batch.map = malloc(BATCH_SZ);
batch->map_next = batch->batch.map;
- batch->state.cpu_map = malloc(STATE_SZ);
- batch->state.map = batch->state.cpu_map;
+ batch->state.map = malloc(STATE_SZ);
}
init_reloc_list(&batch->batch_relocs, 250);
@@ -174,7 +174,7 @@ intel_batchbuffer_reset(struct brw_context *brw)
batch->last_bo = batch->batch.bo;
batch->batch.bo = brw_bo_alloc(bufmgr, "batchbuffer", BATCH_SZ, 4096);
- if (!batch->batch.cpu_map) {
+ if (!batch->use_shadow_copy) {
batch->batch.map =
brw_bo_map(brw, batch->batch.bo, MAP_READ | MAP_WRITE);
}
@@ -183,7 +183,7 @@ intel_batchbuffer_reset(struct brw_context *brw)
batch->state.bo = brw_bo_alloc(bufmgr, "statebuffer", STATE_SZ, 4096);
batch->state.bo->kflags =
can_do_exec_capture(screen) ? EXEC_OBJECT_CAPTURE : 0;
- if (!batch->state.cpu_map) {
+ if (!batch->use_shadow_copy) {
batch->state.map =
brw_bo_map(brw, batch->state.bo, MAP_READ | MAP_WRITE);
}
@@ -243,8 +243,10 @@ intel_batchbuffer_reset_to_saved(struct brw_context *brw)
void
intel_batchbuffer_free(struct intel_batchbuffer *batch)
{
- free(batch->batch.cpu_map);
- free(batch->state.cpu_map);
+ if (batch->use_shadow_copy) {
+ free(batch->batch.map);
+ free(batch->state.map);
+ }
for (int i = 0; i < batch->exec_count; i++) {
brw_bo_unreference(batch->exec_bos[i]);
@@ -284,7 +286,6 @@ static void
grow_buffer(struct brw_context *brw,
struct brw_bo **bo_ptr,
uint32_t **map_ptr,
-uint32_t **cpu_map_ptr,
unsigned existing_bytes,
unsigned new_size)
{
@@ -301,8 +302,8 @@ grow_buffer(struct brw_context *brw,
perf_debug("Growing %s - ran out of space\n", old_bo->name);
/* Copy existing data to the new larger buffer */
- if (*cpu_map_ptr) {
- *cpu_map_ptr = new_map = realloc(*cpu_map_ptr, new_size);
+ if (batch->use_shadow_copy) {
+ new_map = realloc(*map_ptr, new_size);
} else {
new_map = brw_bo_map(brw, new_bo, MAP_READ | MAP_WRITE);
memcpy(new_map, old_map, existing_bytes);
@@ -373,7 +374,7 @@ intel_batchbuffer_require_space(struct brw_context *brw,
GLuint sz,
MIN2(batch->batch.bo->size + batch->batch.bo->size / 2,
MAX_BATCH_SIZE);
grow_buffer(brw, &batch->batch.bo, &batch->batch.map,
- &batch->batch.cpu_map, batch_used, new_size);
+ batch_used, new_size);
batch->map_next = (void *) batch->batch.map + batch_used;
assert(batch_used + sz < batch->batch.bo->size);
}
@@ -806,14 +807,12 @@ submit_batch(struct brw_context *brw, int in_fence_fd,
int *out_fence_fd)
struct intel_batchbuffer *batch = &brw->batch;
int ret = 0;
- if (batch->batch.cpu_map) {
+ if (batch->use_shadow_copy) {
void *bo_map = brw_bo_map(brw, batch->batch.bo, MAP_WRITE);
- memcpy(bo_map, batch->batch.cpu_map, 4 * USED_BATCH(*batch));
- }
+
Mesa (master): r600/sb: handle LDS operations in folding.
Module: Mesa
Branch: master
Commit: d72590032f4a73f824c425fbe926d4b0c4ea13e1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d72590032f4a73f824c425fbe926d4b0c4ea13e1
Author: Dave Airlie
Date: Wed Jan 10 04:25:20 2018 +
r600/sb: handle LDS operations in folding.
Don't try and fold LDS using expressions.
Acked-By: Roland Scheidegger
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/sb/sb_expr.cpp | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/gallium/drivers/r600/sb/sb_expr.cpp
b/src/gallium/drivers/r600/sb/sb_expr.cpp
index 7a5d62c8e8..7d43ef1d1d 100644
--- a/src/gallium/drivers/r600/sb/sb_expr.cpp
+++ b/src/gallium/drivers/r600/sb/sb_expr.cpp
@@ -74,6 +74,8 @@ bool expr_handler::equal(value *l, value *r) {
assert(l != r);
+ if (l->is_lds_access() || r->is_lds_access())
+ return false;
if (l->gvalue() == r->gvalue())
return true;
@@ -383,8 +385,14 @@ bool expr_handler::fold_alu_op1(alu_node& n) {
if (n.src.empty())
return false;
+ /* don't fold LDS instructions */
+ if (n.bc.op_ptr->flags & AF_LDS)
+ return false;
+
value* v0 = n.src[0]->gvalue();
+ if (v0->is_lds_oq() || v0->is_lds_access())
+ return false;
assert(v0 && n.dst[0]);
if (!v0->is_const()) {
@@ -942,6 +950,9 @@ bool expr_handler::fold_alu_op3(alu_node& n) {
value* v1 = n.src[1]->gvalue();
value* v2 = n.src[2]->gvalue();
+ /* LDS instructions look like op3 with no dst - don't fold. */
+ if (!n.dst[0])
+ return false;
assert(v0 && v1 && v2 && n.dst[0]);
bool isc0 = v0->is_const();
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Mesa (master): r600/sb: schedule LDS ops in appropriate places.
Module: Mesa
Branch: master
Commit: 8cfec333c08a9518735d261cc9d6a96d64276f1c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8cfec333c08a9518735d261cc9d6a96d64276f1c
Author: Dave Airlie
Date: Wed Jan 10 04:41:02 2018 +
r600/sb: schedule LDS ops in appropriate places.
So LDS ops have to be SLOT_X,
and LDS OQ reads have read port restrictions so we try
and force those into only having one per slot and avoiding
bank swizzles.
Acked-By: Roland Scheidegger
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/sb/sb_bc.h | 3 +++
src/gallium/drivers/r600/sb/sb_sched.cpp | 4
2 files changed, 7 insertions(+)
diff --git a/src/gallium/drivers/r600/sb/sb_bc.h
b/src/gallium/drivers/r600/sb/sb_bc.h
index 3a3bae9d44..b35671bf0f 100644
--- a/src/gallium/drivers/r600/sb/sb_bc.h
+++ b/src/gallium/drivers/r600/sb/sb_bc.h
@@ -711,6 +711,9 @@ public:
mask = 0x0F;
if (!is_cayman() && (slot_flags & AF_S))
mask |= 0x10;
+ /* Force LDS_IDX ops into SLOT_X */
+ if (op_ptr->opcode[0] == -1 && ((op_ptr->opcode[1] & 0xFF) ==
0x11))
+ mask = 0x01;
return mask;
}
diff --git a/src/gallium/drivers/r600/sb/sb_sched.cpp
b/src/gallium/drivers/r600/sb/sb_sched.cpp
index 1feef585df..f5fd84d54a 100644
--- a/src/gallium/drivers/r600/sb/sb_sched.cpp
+++ b/src/gallium/drivers/r600/sb/sb_sched.cpp
@@ -461,6 +461,10 @@ bool alu_group_tracker::try_reserve(alu_node* n) {
if (n->uses_ar() && has_mova)
return false;
+ if (consumes_lds_oqa)
+ return false;
+ if (n->consumes_lds_oq() && available_slots != (sh.get_ctx().has_trans
? 0x1F : 0x0F))
+ return false;
for (unsigned i = 0; i < nsrc; ++i) {
unsigned last_id = next_id;
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Mesa (master): i965: Make a helper for recreating growing buffers.
Module: Mesa
Branch: master
Commit: 81ca8e69e327f07f57d597fa6ce23ff67b932de8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=81ca8e69e327f07f57d597fa6ce23ff67b932de8
Author: Kenneth Graunke
Date: Sat Jan 6 20:34:35 2018 -0800
i965: Make a helper for recreating growing buffers.
Now that we have two of these, we're duplicating a bunch of this logic.
The next commit will add more logic, which would make the duplication
seem worse.
This ends up setting EXEC_OBJECT_CAPTURE on the batch, which isn't
necessary (it's already captured), but it should be harmless.
Reviewed-by: Iago Toral Quiroga
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 30 +++
1 file changed, 17 insertions(+), 13 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index bfb50053e7..877f68ee7c 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -161,32 +161,36 @@ add_exec_bo(struct intel_batchbuffer *batch, struct
brw_bo *bo)
}
static void
-intel_batchbuffer_reset(struct brw_context *brw)
+recreate_growing_buffer(struct brw_context *brw,
+struct brw_growing_bo *grow,
+const char *name, unsigned size)
{
struct intel_screen *screen = brw->screen;
struct intel_batchbuffer *batch = &brw->batch;
struct brw_bufmgr *bufmgr = screen->bufmgr;
+ grow->bo = brw_bo_alloc(bufmgr, name, size, 4096);
+ grow->bo->kflags = can_do_exec_capture(screen) ? EXEC_OBJECT_CAPTURE : 0;
+
+ if (!batch->use_shadow_copy)
+ grow->map = brw_bo_map(brw, grow->bo, MAP_READ | MAP_WRITE);
+}
+
+static void
+intel_batchbuffer_reset(struct brw_context *brw)
+{
+ struct intel_batchbuffer *batch = &brw->batch;
+
if (batch->last_bo != NULL) {
brw_bo_unreference(batch->last_bo);
batch->last_bo = NULL;
}
batch->last_bo = batch->batch.bo;
- batch->batch.bo = brw_bo_alloc(bufmgr, "batchbuffer", BATCH_SZ, 4096);
- if (!batch->use_shadow_copy) {
- batch->batch.map =
- brw_bo_map(brw, batch->batch.bo, MAP_READ | MAP_WRITE);
- }
+ recreate_growing_buffer(brw, &batch->batch, "batchbuffer", BATCH_SZ);
batch->map_next = batch->batch.map;
- batch->state.bo = brw_bo_alloc(bufmgr, "statebuffer", STATE_SZ, 4096);
- batch->state.bo->kflags =
- can_do_exec_capture(screen) ? EXEC_OBJECT_CAPTURE : 0;
- if (!batch->use_shadow_copy) {
- batch->state.map =
- brw_bo_map(brw, batch->state.bo, MAP_READ | MAP_WRITE);
- }
+ recreate_growing_buffer(brw, &batch->state, "statebuffer", STATE_SZ);
/* Avoid making 0 a valid state offset - otherwise the decoder will try
* and decode data when we use offset 0 as a null pointer.
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Mesa (master): ac: tidy up array indexing logic
Module: Mesa Branch: master Commit: 9248f72c4e8513fdf4ac4cac4b78c9f06621046a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9248f72c4e8513fdf4ac4cac4b78c9f06621046a Author: Timothy Arceri Date: Thu Jan 18 15:46:35 2018 +1100 ac: tidy up array indexing logic Reviewed-by: Bas Nieuwenhuizen --- src/amd/common/ac_nir_to_llvm.c | 6 +- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c index e07330ca5c..c53fb5cb1c 100644 --- a/src/amd/common/ac_nir_to_llvm.c +++ b/src/amd/common/ac_nir_to_llvm.c @@ -2588,11 +2588,7 @@ static LLVMValueRef visit_load_buffer(struct ac_nir_context *ctx, ctx->ac.i1false, }; - int idx = i; - if (instr->dest.ssa.bit_size == 64) - idx = i > 1 ? 1 : 0; - - results[idx] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0); + results[i > 0 ? 1 : 0] = ac_build_intrinsic(&ctx->ac, load_name, data_type, params, 5, 0); } assume(results[0]); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600/sb: add finalising for lds output queue special values.
Module: Mesa
Branch: master
Commit: c314b0a27ac3f957a92863df3e5bc462432b0262
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c314b0a27ac3f957a92863df3e5bc462432b0262
Author: Dave Airlie
Date: Wed Jan 10 04:22:28 2018 +
r600/sb: add finalising for lds output queue special values.
We need to convert these to the hw special registers.
Acked-By: Roland Scheidegger
Signed-off-by: Dave Airlie
---
src/gallium/drivers/r600/sb/sb_bc_finalize.cpp | 12
1 file changed, 12 insertions(+)
diff --git a/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
b/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
index 2ec4db624a..d377a3950a 100644
--- a/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
+++ b/src/gallium/drivers/r600/sb/sb_bc_finalize.cpp
@@ -428,6 +428,18 @@ bool bc_finalizer::finalize_alu_src(alu_group_node* g,
alu_node* a, alu_group_no
src.chan = k.chan();
break;
}
+ case VLK_SPECIAL_REG:
+ if (v->select.sel() == SV_LDS_OQA) {
+ src.sel = ALU_SRC_LDS_OQ_A_POP;
+ src.chan = 0;
+ } else if (v->select.sel() == SV_LDS_OQB) {
+ src.sel = ALU_SRC_LDS_OQ_B_POP;
+ src.chan = 0;
+ } else {
+ src.sel = ALU_SRC_0;
+ src.chan = 0;
+ }
+ break;
case VLK_PARAM:
case VLK_SPECIAL_CONST:
src.sel = v->select.sel();
___
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Mesa (master): intel/fs: Optimize and simplify the copy propagation dataflow logic.
Module: Mesa
Branch: master
Commit: 11674dad8acef294bc920e7f02ef45185420fbce
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=11674dad8acef294bc920e7f02ef45185420fbce
Author: Francisco Jerez
Date: Mon Dec 18 15:22:04 2017 -0800
intel/fs: Optimize and simplify the copy propagation dataflow logic.
Previously the dataflow propagation algorithm would calculate the ACP
live-in and -out sets in a two-pass fixed-point algorithm. The first
pass would update the live-out sets of all basic blocks of the program
based on their live-in sets, while the second pass would update the
live-in sets based on the live-out sets. This is incredibly
inefficient in the typical case where the CFG of the program is
approximately acyclic, because it can take up to 2*n passes for an ACP
entry introduced at the top of the program to reach the bottom (where
n is the number of basic blocks in the program), until which point the
algorithm won't be able to reach a fixed point.
The same effect can be achieved in a single pass by computing the
live-in and -out sets in lock-step, because that makes sure that
processing of any basic block will pick up the updated live-out sets
of the lexically preceding blocks. This gives the dataflow
propagation algorithm effectively O(n) run-time instead of O(n^2) in
the acyclic case.
The time spent in dataflow propagation is reduced by 30x in the
GLES31.functional.ssbo.layout.random.all_shared_buffer.5 dEQP
test-case on my CHV system (the improvement is likely to be of the
same order of magnitude on other platforms). This more than reverses
an apparent run-time regression in this test-case from my previous
copy-propagation undefined-value handling patch, which was ultimately
caused by the additional work introduced in that commit to account for
undefined values being multiplied by a huge quadratic factor.
According to Chad this test was failing on CHV due to a 30s time-out
imposed by the Android CTS (this was the case regardless of my
undefined-value handling patch, even though my patch substantially
exacerbated the issue). On my CHV system this patch reduces the
overall run-time of the test by approximately 12x, getting us to
around 13s, well below the time-out.
v2: Initialize live-out set to the universal set to avoid rather
pessimistic dataflow estimation in shaders with cycles (Addresses
performance regression reported by Eero in GpuTest Piano).
Performance numbers given above still apply. No shader-db changes
with respect to master.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104271
Reported-by: Chad Versace
Reviewed-by: Ian Romanick
---
src/intel/compiler/brw_fs_copy_propagation.cpp | 35 --
1 file changed, 11 insertions(+), 24 deletions(-)
diff --git a/src/intel/compiler/brw_fs_copy_propagation.cpp
b/src/intel/compiler/brw_fs_copy_propagation.cpp
index af5635eace..92cc0a8de5 100644
--- a/src/intel/compiler/brw_fs_copy_propagation.cpp
+++ b/src/intel/compiler/brw_fs_copy_propagation.cpp
@@ -186,8 +186,7 @@ fs_copy_prop_dataflow::setup_initial_values()
/* Populate the initial values for the livein and liveout sets. For the
* block at the start of the program, livein = 0 and liveout = copy.
-* For the others, set liveout to 0 (the empty set) and livein to ~0
-* (the universal set).
+* For the others, set liveout and livein to ~0 (the universal set).
*/
foreach_block (block, cfg) {
if (block->parents.is_empty()) {
@@ -197,7 +196,7 @@ fs_copy_prop_dataflow::setup_initial_values()
}
} else {
for (int i = 0; i < bitset_words; i++) {
-bd[block->num].liveout[i] = 0u;
+bd[block->num].liveout[i] = ~0u;
bd[block->num].livein[i] = ~0u;
}
}
@@ -228,34 +227,17 @@ fs_copy_prop_dataflow::run()
do {
progress = false;
- /* Update liveout for all blocks. */
foreach_block (block, cfg) {
if (block->parents.is_empty())
continue;
for (int i = 0; i < bitset_words; i++) {
const BITSET_WORD old_liveout = bd[block->num].liveout[i];
-
-bd[block->num].liveout[i] =
- bd[block->num].copy[i] | (bd[block->num].livein[i] &
- ~bd[block->num].kill[i]);
-
-if (old_liveout != bd[block->num].liveout[i])
- progress = true;
- }
- }
-
- /* Update livein for all blocks. If a copy is live out of all parent
- * blocks, it's live coming in to this block.
- */
- foreach_block (block, cfg) {
- if (block->parents.is_empty())
-continue;
-
- for (int i = 0; i < bitset_words; i++) {
-const BITSET_WORD old_livein = bd[block->num].livein[i];
BITSET_WORD livein_from_any_block = 0;
+/* Update livein for this block. If a copy is live out of all
+ * parent blocks, it's live coming
Mesa (master): gallium: remove PIPE_CAP_TEXTURE_SHADOW_MAP
Module: Mesa Branch: master Commit: e871abe452ad40efcccb0bab6b88fc31d0551e29 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e871abe452ad40efcccb0bab6b88fc31d0551e29 Author: Marek Olšák Date: Wed Jan 10 13:45:33 2018 +0100 gallium: remove PIPE_CAP_TEXTURE_SHADOW_MAP Reviewed-by: Roland Scheidegger Tested-by: Dieter Nützel --- src/gallium/docs/source/screen.rst | 3 --- src/gallium/drivers/etnaviv/etnaviv_screen.c | 1 - src/gallium/drivers/freedreno/freedreno_screen.c | 1 - src/gallium/drivers/i915/i915_screen.c | 1 - src/gallium/drivers/llvmpipe/lp_screen.c | 2 -- src/gallium/drivers/nouveau/nv30/nv30_screen.c | 1 - src/gallium/drivers/nouveau/nv50/nv50_screen.c | 1 - src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 1 - src/gallium/drivers/r300/r300_screen.c | 1 - src/gallium/drivers/r600/r600_pipe.c | 1 - src/gallium/drivers/radeonsi/si_get.c| 1 - src/gallium/drivers/softpipe/sp_screen.c | 2 -- src/gallium/drivers/svga/svga_screen.c | 2 -- src/gallium/drivers/swr/swr_screen.cpp | 1 - src/gallium/drivers/vc4/vc4_screen.c | 1 - src/gallium/drivers/vc5/vc5_screen.c | 1 - src/gallium/drivers/virgl/virgl_screen.c | 2 -- src/gallium/include/pipe/p_defines.h | 1 - src/mesa/state_tracker/st_extensions.c | 6 +++--- 19 files changed, 3 insertions(+), 27 deletions(-) diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst index d275c82426..0f4e36e680 100644 --- a/src/gallium/docs/source/screen.rst +++ b/src/gallium/docs/source/screen.rst @@ -32,9 +32,6 @@ The integer capabilities: bound. * ``PIPE_CAP_OCCLUSION_QUERY``: Whether occlusion queries are available. * ``PIPE_CAP_QUERY_TIME_ELAPSED``: Whether PIPE_QUERY_TIME_ELAPSED queries are available. -* ``PIPE_CAP_TEXTURE_SHADOW_MAP``: indicates whether the fragment shader hardware - can do the depth texture / Z comparison operation in TEX instructions - for shadow testing. * ``PIPE_CAP_TEXTURE_SWIZZLE``: Whether swizzling through sampler views is supported. * ``PIPE_CAP_MAX_TEXTURE_2D_LEVELS``: The maximum number of mipmap levels available diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c b/src/gallium/drivers/etnaviv/etnaviv_screen.c index 3b01455f41..70dea1f333 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_screen.c +++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c @@ -127,7 +127,6 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) /* Supported features (boolean caps). */ case PIPE_CAP_ANISOTROPIC_FILTER: case PIPE_CAP_POINT_SPRITE: - case PIPE_CAP_TEXTURE_SHADOW_MAP: case PIPE_CAP_BLEND_EQUATION_SEPARATE: case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT: case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER: diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 85cff6586b..839f2bcc9c 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -169,7 +169,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: case PIPE_CAP_ANISOTROPIC_FILTER: case PIPE_CAP_POINT_SPRITE: - case PIPE_CAP_TEXTURE_SHADOW_MAP: case PIPE_CAP_BLEND_EQUATION_SEPARATE: case PIPE_CAP_TEXTURE_SWIZZLE: case PIPE_CAP_MIXED_COLORBUFFER_FORMATS: diff --git a/src/gallium/drivers/i915/i915_screen.c b/src/gallium/drivers/i915/i915_screen.c index 0f39a6756d..54fa77652c 100644 --- a/src/gallium/drivers/i915/i915_screen.c +++ b/src/gallium/drivers/i915/i915_screen.c @@ -199,7 +199,6 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap) case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES: case PIPE_CAP_POINT_SPRITE: case PIPE_CAP_PRIMITIVE_RESTART: /* draw module */ - case PIPE_CAP_TEXTURE_SHADOW_MAP: case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR: case PIPE_CAP_BLEND_EQUATION_SEPARATE: case PIPE_CAP_TGSI_INSTANCEID: diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c index 8fb192f6af..b5b4d29b3d 100644 --- a/src/gallium/drivers/llvmpipe/lp_screen.c +++ b/src/gallium/drivers/llvmpipe/lp_screen.c @@ -133,8 +133,6 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param) return 1; case PIPE_CAP_TEXTURE_MIRROR_CLAMP: return 1; - case PIPE_CAP_TEXTURE_SHADOW_MAP: - return 1; case PIPE_CAP_TEXTURE_SWIZZLE: return 1; case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c b/src/gallium/drivers/nouveau/nv30/nv30_screen.c index fd17c48f27..ee6fd4897f 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c @@ -81,7 +81,6 @@ nv30_screen_get_param(struct pipe
Mesa (master): st/mesa: expose ARB_sync unconditionally
Module: Mesa
Branch: master
Commit: e411d2572b01a919883ca513413fc026f2ebbfb1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e411d2572b01a919883ca513413fc026f2ebbfb1
Author: Marek Olšák
Date: Tue Jan 9 15:48:52 2018 +0100
st/mesa: expose ARB_sync unconditionally
All drivers support it.
Reviewed-by: Roland Scheidegger
Tested-by: Dieter Nützel
---
src/mesa/state_tracker/st_extensions.c | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/src/mesa/state_tracker/st_extensions.c
b/src/mesa/state_tracker/st_extensions.c
index 208a08323d..51062f6d0d 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -873,7 +873,8 @@ void st_init_extensions(struct pipe_screen *screen,
extensions->ARB_internalformat_query = GL_TRUE;
extensions->ARB_internalformat_query2 = GL_TRUE;
extensions->ARB_map_buffer_range = GL_TRUE;
- extensions->ARB_texture_border_clamp = GL_TRUE; /* XXX temp */
+ extensions->ARB_sync = GL_TRUE;
+ extensions->ARB_texture_border_clamp = GL_TRUE;
extensions->ARB_texture_cube_map = GL_TRUE;
extensions->ARB_texture_env_combine = GL_TRUE;
extensions->ARB_texture_env_crossbar = GL_TRUE;
@@ -1021,10 +1022,6 @@ void st_init_extensions(struct pipe_screen *screen,
extensions->OES_geometry_shader = GL_TRUE;
}
- if (screen->fence_finish) {
- extensions->ARB_sync = GL_TRUE;
- }
-
/* Needs PIPE_CAP_SAMPLE_SHADING + all the sample-related bits of
* ARB_gpu_shader5. This enables all the per-sample shading ES extensions.
*/
___
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Mesa (master): st/mesa: assume that user constant buffers are always supported
Module: Mesa
Branch: master
Commit: 85bbcdda34164865c8e603899a81463f1ad55ecf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=85bbcdda34164865c8e603899a81463f1ad55ecf
Author: Marek Olšák
Date: Wed Jan 10 20:03:28 2018 +0100
st/mesa: assume that user constant buffers are always supported
Reviewed-by: Roland Scheidegger
Tested-by: Dieter Nützel
---
src/mesa/state_tracker/st_atom_constbuf.c | 19 +++
src/mesa/state_tracker/st_context.c | 2 --
src/mesa/state_tracker/st_context.h | 1 -
src/mesa/state_tracker/st_pbo.c | 18 +++---
4 files changed, 6 insertions(+), 34 deletions(-)
diff --git a/src/mesa/state_tracker/st_atom_constbuf.c
b/src/mesa/state_tracker/st_atom_constbuf.c
index 497d33fc34..0a6b23aff3 100644
--- a/src/mesa/state_tracker/st_atom_constbuf.c
+++ b/src/mesa/state_tracker/st_atom_constbuf.c
@@ -101,22 +101,9 @@ void st_upload_constants(struct st_context *st, struct
gl_program *prog)
_mesa_shader_write_subroutine_indices(st->ctx, stage);
- /* We always need to get a new buffer, to keep the drivers simple and
- * avoid gratuitous rendering synchronization.
- * Let's use a user buffer to avoid an unnecessary copy.
- */
- if (!st->has_user_constbuf) {
- cb.buffer = NULL;
- cb.user_buffer = NULL;
- u_upload_data(st->pipe->const_uploader, 0, paramBytes,
- st->ctx->Const.UniformBufferOffsetAlignment,
- params->ParameterValues, &cb.buffer_offset, &cb.buffer);
- u_upload_unmap(st->pipe->const_uploader);
- } else {
- cb.buffer = NULL;
- cb.user_buffer = params->ParameterValues;
- cb.buffer_offset = 0;
- }
+ cb.buffer = NULL;
+ cb.user_buffer = params->ParameterValues;
+ cb.buffer_offset = 0;
cb.buffer_size = paramBytes;
if (ST_DEBUG & DEBUG_CONSTANTS) {
diff --git a/src/mesa/state_tracker/st_context.c
b/src/mesa/state_tracker/st_context.c
index a7b2cfc12b..3ba4847926 100644
--- a/src/mesa/state_tracker/st_context.c
+++ b/src/mesa/state_tracker/st_context.c
@@ -372,8 +372,6 @@ st_create_context_priv(struct gl_context *ctx, struct
pipe_context *pipe,
st->dirty = ST_ALL_STATES_MASK;
- st->has_user_constbuf =
- screen->get_param(screen, PIPE_CAP_USER_CONSTANT_BUFFERS);
st->can_bind_const_buffer_as_vertex =
screen->get_param(screen, PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX);
diff --git a/src/mesa/state_tracker/st_context.h
b/src/mesa/state_tracker/st_context.h
index 9f33eed8f3..0258bed36b 100644
--- a/src/mesa/state_tracker/st_context.h
+++ b/src/mesa/state_tracker/st_context.h
@@ -110,7 +110,6 @@ struct st_context
boolean has_shareable_shaders;
boolean has_half_float_packing;
boolean has_multi_draw_indirect;
- boolean has_user_constbuf;
boolean can_bind_const_buffer_as_vertex;
/**
diff --git a/src/mesa/state_tracker/st_pbo.c b/src/mesa/state_tracker/st_pbo.c
index 303c8535b2..628e3ca64a 100644
--- a/src/mesa/state_tracker/st_pbo.c
+++ b/src/mesa/state_tracker/st_pbo.c
@@ -259,21 +259,9 @@ st_pbo_draw(struct st_context *st, const struct
st_pbo_addresses *addr,
{
struct pipe_constant_buffer cb;
- if (!st->has_user_constbuf) {
- cb.buffer = NULL;
- cb.user_buffer = NULL;
- u_upload_data(st->pipe->const_uploader, 0, sizeof(addr->constants),
- st->ctx->Const.UniformBufferOffsetAlignment,
- &addr->constants, &cb.buffer_offset, &cb.buffer);
- if (!cb.buffer)
-return false;
-
- u_upload_unmap(st->pipe->const_uploader);
- } else {
- cb.buffer = NULL;
- cb.user_buffer = &addr->constants;
- cb.buffer_offset = 0;
- }
+ cb.buffer = NULL;
+ cb.user_buffer = &addr->constants;
+ cb.buffer_offset = 0;
cb.buffer_size = sizeof(addr->constants);
cso_set_constant_buffer(cso, PIPE_SHADER_FRAGMENT, 0, &cb);
___
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Mesa (master): gallium: remove PIPE_CAP_USER_CONSTANT_BUFFERS
Module: Mesa Branch: master Commit: 63b231309e829aa6f9289fd30c71a6d301ab5c0a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=63b231309e829aa6f9289fd30c71a6d301ab5c0a Author: Marek Olšák Date: Wed Jan 10 20:03:54 2018 +0100 gallium: remove PIPE_CAP_USER_CONSTANT_BUFFERS Reviewed-by: Roland Scheidegger Tested-by: Dieter Nützel --- src/gallium/docs/source/screen.rst | 4 src/gallium/drivers/etnaviv/etnaviv_screen.c | 1 - src/gallium/drivers/freedreno/freedreno_screen.c | 3 --- src/gallium/drivers/i915/i915_screen.c | 1 - src/gallium/drivers/llvmpipe/lp_screen.c | 2 -- src/gallium/drivers/nouveau/nv30/nv30_screen.c | 1 - src/gallium/drivers/nouveau/nv50/nv50_screen.c | 1 - src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 1 - src/gallium/drivers/r300/r300_screen.c | 1 - src/gallium/drivers/r600/r600_pipe.c | 1 - src/gallium/drivers/radeonsi/si_get.c| 1 - src/gallium/drivers/softpipe/sp_screen.c | 1 - src/gallium/drivers/svga/svga_screen.c | 2 -- src/gallium/drivers/swr/swr_screen.cpp | 1 - src/gallium/drivers/vc4/vc4_screen.c | 1 - src/gallium/drivers/vc5/vc5_screen.c | 1 - src/gallium/drivers/virgl/virgl_screen.c | 2 -- src/gallium/include/pipe/p_defines.h | 1 - 18 files changed, 26 deletions(-) diff --git a/src/gallium/docs/source/screen.rst b/src/gallium/docs/source/screen.rst index 0f4e36e680..4475aac4a7 100644 --- a/src/gallium/docs/source/screen.rst +++ b/src/gallium/docs/source/screen.rst @@ -110,10 +110,6 @@ The integer capabilities: aligned to 4. If false, there are no restrictions on src_offset. * ``PIPE_CAP_COMPUTE``: Whether the implementation supports the compute entry points defined in pipe_context and pipe_screen. -* ``PIPE_CAP_USER_CONSTANT_BUFFERS``: Whether user-space constant buffers - are supported. If not, the state tracker must put constants into HW - resources/buffers. If user-space constant buffers are supported, the - driver must still accept HW constant buffers also. * ``PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT``: Describes the required alignment of pipe_constant_buffer::buffer_offset. * ``PIPE_CAP_START_INSTANCE``: Whether the driver supports diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c b/src/gallium/drivers/etnaviv/etnaviv_screen.c index 70dea1f333..c72793920a 100644 --- a/src/gallium/drivers/etnaviv/etnaviv_screen.c +++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c @@ -136,7 +136,6 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: - case PIPE_CAP_USER_CONSTANT_BUFFERS: case PIPE_CAP_TGSI_TEXCOORD: case PIPE_CAP_VERTEX_COLOR_UNCLAMPED: return 1; diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 839f2bcc9c..b68685989c 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -190,9 +190,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_VERTEXID_NOBASE: return is_a3xx(screen) || is_a4xx(screen); - case PIPE_CAP_USER_CONSTANT_BUFFERS: - return is_a4xx(screen) ? 0 : 1; - case PIPE_CAP_COMPUTE: return has_compute(screen); diff --git a/src/gallium/drivers/i915/i915_screen.c b/src/gallium/drivers/i915/i915_screen.c index 54fa77652c..804d1245b4 100644 --- a/src/gallium/drivers/i915/i915_screen.c +++ b/src/gallium/drivers/i915/i915_screen.c @@ -204,7 +204,6 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap) case PIPE_CAP_TGSI_INSTANCEID: case PIPE_CAP_VERTEX_COLOR_CLAMPED: case PIPE_CAP_USER_VERTEX_BUFFERS: - case PIPE_CAP_USER_CONSTANT_BUFFERS: case PIPE_CAP_MIXED_COLOR_DEPTH_BITS: return 1; diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c index b5b4d29b3d..0977f06f37 100644 --- a/src/gallium/drivers/llvmpipe/lp_screen.c +++ b/src/gallium/drivers/llvmpipe/lp_screen.c @@ -211,8 +211,6 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param) return 0; case PIPE_CAP_USER_VERTEX_BUFFERS: return 1; - case PIPE_CAP_USER_CONSTANT_BUFFERS: - return 0; case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY: diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c b/src/gallium/drivers/nouveau/nv30/nv30_screen.c index ee6fd4897f..4fecce8eff 100644 --- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c +++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c @@ -88,7 +
Mesa (master): gallium: remove PIPE_CAP_TWO_SIDED_STENCIL
Module: Mesa
Branch: master
Commit: 3778a0a5330a109c4419d1817bece714f4e39ae8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3778a0a5330a109c4419d1817bece714f4e39ae8
Author: Marek Olšák
Date: Wed Jan 10 13:40:55 2018 +0100
gallium: remove PIPE_CAP_TWO_SIDED_STENCIL
Reviewed-by: Roland Scheidegger
Tested-by: Dieter Nützel
---
src/gallium/docs/source/screen.rst | 2 --
src/gallium/drivers/etnaviv/etnaviv_screen.c | 1 -
src/gallium/drivers/freedreno/freedreno_screen.c | 1 -
src/gallium/drivers/i915/i915_screen.c | 1 -
src/gallium/drivers/llvmpipe/lp_screen.c | 2 --
src/gallium/drivers/nouveau/nv30/nv30_screen.c | 1 -
src/gallium/drivers/nouveau/nv50/nv50_screen.c | 1 -
src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 1 -
src/gallium/drivers/r300/r300_screen.c | 1 -
src/gallium/drivers/r600/r600_pipe.c | 1 -
src/gallium/drivers/radeonsi/si_get.c| 1 -
src/gallium/drivers/softpipe/sp_screen.c | 2 --
src/gallium/drivers/svga/svga_screen.c | 2 --
src/gallium/drivers/swr/swr_screen.cpp | 1 -
src/gallium/drivers/vc4/vc4_screen.c | 1 -
src/gallium/drivers/vc5/vc5_screen.c | 1 -
src/gallium/drivers/virgl/virgl_screen.c | 2 --
src/gallium/include/pipe/p_defines.h | 1 -
src/gallium/state_trackers/nine/adapter9.c | 2 +-
src/mesa/state_tracker/st_extensions.c | 5 ++---
20 files changed, 3 insertions(+), 27 deletions(-)
diff --git a/src/gallium/docs/source/screen.rst
b/src/gallium/docs/source/screen.rst
index 3cfa8e3021..d275c82426 100644
--- a/src/gallium/docs/source/screen.rst
+++ b/src/gallium/docs/source/screen.rst
@@ -24,8 +24,6 @@ The integer capabilities:
* ``PIPE_CAP_NPOT_TEXTURES``: Whether :term:`NPOT` textures may have repeat
modes,
normalized coordinates, and mipmaps.
-* ``PIPE_CAP_TWO_SIDED_STENCIL``: Whether the stencil test can also affect
back-facing
- polygons.
* ``PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS``: How many dual-source blend RTs
are support.
:ref:`Blend` for more information.
* ``PIPE_CAP_ANISOTROPIC_FILTER``: Whether textures can be filtered
anisotropically.
diff --git a/src/gallium/drivers/etnaviv/etnaviv_screen.c
b/src/gallium/drivers/etnaviv/etnaviv_screen.c
index 242ebf8512..3b01455f41 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_screen.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_screen.c
@@ -125,7 +125,6 @@ etna_screen_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
switch (param) {
/* Supported features (boolean caps). */
- case PIPE_CAP_TWO_SIDED_STENCIL:
case PIPE_CAP_ANISOTROPIC_FILTER:
case PIPE_CAP_POINT_SPRITE:
case PIPE_CAP_TEXTURE_SHADOW_MAP:
diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c
b/src/gallium/drivers/freedreno/freedreno_screen.c
index e0a9048031..85cff6586b 100644
--- a/src/gallium/drivers/freedreno/freedreno_screen.c
+++ b/src/gallium/drivers/freedreno/freedreno_screen.c
@@ -167,7 +167,6 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
/* Supported features (boolean caps). */
case PIPE_CAP_NPOT_TEXTURES:
case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
- case PIPE_CAP_TWO_SIDED_STENCIL:
case PIPE_CAP_ANISOTROPIC_FILTER:
case PIPE_CAP_POINT_SPRITE:
case PIPE_CAP_TEXTURE_SHADOW_MAP:
diff --git a/src/gallium/drivers/i915/i915_screen.c
b/src/gallium/drivers/i915/i915_screen.c
index 663e79333e..0f39a6756d 100644
--- a/src/gallium/drivers/i915/i915_screen.c
+++ b/src/gallium/drivers/i915/i915_screen.c
@@ -200,7 +200,6 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap
cap)
case PIPE_CAP_POINT_SPRITE:
case PIPE_CAP_PRIMITIVE_RESTART: /* draw module */
case PIPE_CAP_TEXTURE_SHADOW_MAP:
- case PIPE_CAP_TWO_SIDED_STENCIL:
case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
case PIPE_CAP_BLEND_EQUATION_SEPARATE:
case PIPE_CAP_TGSI_INSTANCEID:
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c
b/src/gallium/drivers/llvmpipe/lp_screen.c
index 9c3d9fbcbd..8fb192f6af 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -111,8 +111,6 @@ llvmpipe_get_param(struct pipe_screen *screen, enum
pipe_cap param)
case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
return 1;
- case PIPE_CAP_TWO_SIDED_STENCIL:
- return 1;
case PIPE_CAP_SM3:
return 1;
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
diff --git a/src/gallium/drivers/nouveau/nv30/nv30_screen.c
b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
index f915800023..fd17c48f27 100644
--- a/src/gallium/drivers/nouveau/nv30/nv30_screen.c
+++ b/src/gallium/drivers/nouveau/nv30/nv30_screen.c
@@ -76,7 +76,6 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
return 2048;
/* supporte
Mesa (master): nine: assume that user constant buffers are always supported
Module: Mesa
Branch: master
Commit: 5981a5226ea1b0075443e40bc18b2d4b3cd76d2c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5981a5226ea1b0075443e40bc18b2d4b3cd76d2c
Author: Marek Olšák
Date: Wed Jan 10 20:02:48 2018 +0100
nine: assume that user constant buffers are always supported
Tested-by: Dieter Nützel
---
src/gallium/state_trackers/nine/device9.c| 4 -
src/gallium/state_trackers/nine/device9.h| 3 -
src/gallium/state_trackers/nine/nine_ff.c| 28 +-
src/gallium/state_trackers/nine/nine_state.c | 125 +--
4 files changed, 4 insertions(+), 156 deletions(-)
diff --git a/src/gallium/state_trackers/nine/device9.c
b/src/gallium/state_trackers/nine/device9.c
index 34f903a694..127f2ae195 100644
--- a/src/gallium/state_trackers/nine/device9.c
+++ b/src/gallium/state_trackers/nine/device9.c
@@ -473,12 +473,8 @@ NineDevice9_ctor( struct NineDevice9 *This,
/* Allocate upload helper for drivers that suck (from st pov ;). */
This->driver_caps.user_vbufs = GET_PCAP(USER_VERTEX_BUFFERS) &&
!This->csmt_active;
-This->driver_caps.user_cbufs = GET_PCAP(USER_CONSTANT_BUFFERS);
This->driver_caps.user_sw_vbufs =
This->screen_sw->get_param(This->screen_sw, PIPE_CAP_USER_VERTEX_BUFFERS);
-This->driver_caps.user_sw_cbufs =
This->screen_sw->get_param(This->screen_sw, PIPE_CAP_USER_CONSTANT_BUFFERS);
This->vertex_uploader = This->csmt_active ?
This->pipe_secondary->stream_uploader : This->context.pipe->stream_uploader;
-if (!This->driver_caps.user_cbufs)
-This->constbuf_alignment = GET_PCAP(CONSTANT_BUFFER_OFFSET_ALIGNMENT);
This->driver_caps.window_space_position_support =
GET_PCAP(TGSI_VS_WINDOW_SPACE_POSITION);
This->driver_caps.vs_integer = pScreen->get_shader_param(pScreen,
PIPE_SHADER_VERTEX, PIPE_SHADER_CAP_INTEGERS);
This->driver_caps.ps_integer = pScreen->get_shader_param(pScreen,
PIPE_SHADER_FRAGMENT, PIPE_SHADER_CAP_INTEGERS);
diff --git a/src/gallium/state_trackers/nine/device9.h
b/src/gallium/state_trackers/nine/device9.h
index c5fd8f76c6..4cce29a28e 100644
--- a/src/gallium/state_trackers/nine/device9.h
+++ b/src/gallium/state_trackers/nine/device9.h
@@ -127,9 +127,7 @@ struct NineDevice9
struct {
boolean user_vbufs;
-boolean user_cbufs;
boolean user_sw_vbufs;
-boolean user_sw_cbufs;
boolean window_space_position_support;
boolean vs_integer;
boolean ps_integer;
@@ -141,7 +139,6 @@ struct NineDevice9
} driver_bugs;
struct u_upload_mgr *vertex_uploader;
-unsigned constbuf_alignment;
struct nine_range_pool range_pool;
diff --git a/src/gallium/state_trackers/nine/nine_ff.c
b/src/gallium/state_trackers/nine/nine_ff.c
index 39fcb8b159..eb673e4aff 100644
--- a/src/gallium/state_trackers/nine/nine_ff.c
+++ b/src/gallium/state_trackers/nine/nine_ff.c
@@ -2060,19 +2060,7 @@ nine_ff_update(struct NineDevice9 *device)
cb.user_buffer = device->ff.vs_const;
cb.buffer_size = NINE_FF_NUM_VS_CONST * 4 * sizeof(float);
-if (!device->driver_caps.user_cbufs) {
-context->pipe_data.cb_vs_ff.buffer_size = cb.buffer_size;
-u_upload_data(device->context.pipe->const_uploader,
- 0,
- cb.buffer_size,
- device->constbuf_alignment,
- cb.user_buffer,
- &context->pipe_data.cb_vs_ff.buffer_offset,
- &context->pipe_data.cb_vs_ff.buffer);
-u_upload_unmap(device->context.pipe->const_uploader);
-context->pipe_data.cb_vs_ff.user_buffer = NULL;
-} else
-context->pipe_data.cb_vs_ff = cb;
+context->pipe_data.cb_vs_ff = cb;
context->commit |= NINE_STATE_COMMIT_CONST_VS;
}
@@ -2084,19 +2072,7 @@ nine_ff_update(struct NineDevice9 *device)
cb.user_buffer = device->ff.ps_const;
cb.buffer_size = NINE_FF_NUM_PS_CONST * 4 * sizeof(float);
-if (!device->driver_caps.user_cbufs) {
-context->pipe_data.cb_ps_ff.buffer_size = cb.buffer_size;
-u_upload_data(device->context.pipe->const_uploader,
- 0,
- cb.buffer_size,
- device->constbuf_alignment,
- cb.user_buffer,
- &context->pipe_data.cb_ps_ff.buffer_offset,
- &context->pipe_data.cb_ps_ff.buffer);
-u_upload_unmap(device->context.pipe->const_uploader);
-context->pipe_data.cb_ps_ff.user_buffer = NULL;
-} else
-context->pipe_data.cb_ps_ff = cb;
+context->pipe_data.cb_ps_ff = cb;
context->commit |= NINE_STATE_COMMIT_CONST_PS;
}
diff --git a/src/gallium/state_trackers/nine/nine_state.c
b/src/gallium/state_trackers/nine/nine_state.c
index a9a41af66e..26b2dea3bd 100644
---
