Mesa (master): nvc0: collapse output slots to have adjacent registers

[Ilia Mirkin]

Module: Mesa
Branch: master
Commit: e683a797c6881ddb3b07cad8fdb84f77c6655c95
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e683a797c6881ddb3b07cad8fdb84f77c6655c95

Author: Ilia Mirkin 
Date:   Mon Feb  5 00:15:58 2018 -0500

nvc0: collapse output slots to have adjacent registers

The hardware skips over unallocated slots, so we have to make sure those
registers are packed together.

Fixes KHR-GL45.enhanced_layouts.fragment_data_location_api

Signed-off-by: Ilia Mirkin 
Tested-by: Karol Herbst 

---

 src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c 
b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
index e6157f550d..9520d984bb 100644
--- a/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
+++ b/src/gallium/drivers/nouveau/nvc0/nvc0_program.c
@@ -134,10 +134,20 @@ nvc0_fp_assign_output_slots(struct nv50_ir_prog_info 
*info)
unsigned count = info->prop.fp.numColourResults * 4;
unsigned i, c;
 
+   /* Compute the relative position of each color output, since skipped MRT
+* positions will not have registers allocated to them.
+*/
+   unsigned colors[8] = {0};
+   for (i = 0; i < info->numOutputs; ++i)
+  if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
+ colors[info->out[i].si] = 1;
+   for (i = 0, c = 0; i < 8; i++)
+  if (colors[i])
+ colors[i] = c++;
for (i = 0; i < info->numOutputs; ++i)
   if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
  for (c = 0; c < 4; ++c)
-info->out[i].slot[c] = info->out[i].si * 4 + c;
+info->out[i].slot[c] = colors[info->out[i].si] * 4 + c;
 
if (info->io.sampleMask < PIPE_MAX_SHADER_OUTPUTS)
   info->out[info->io.sampleMask].slot[0] = count++;
@@ -474,7 +484,7 @@ nvc0_fp_gen_header(struct nvc0_program *fp, struct 
nv50_ir_prog_info *info)
 
for (i = 0; i < info->numOutputs; ++i) {
   if (info->out[i].sn == TGSI_SEMANTIC_COLOR)
- fp->hdr[18] |= 0xf << info->out[i].slot[0];
+ fp->hdr[18] |= 0xf << (4 * info->out[i].si);
}
 
/* There are no "regular" attachments, but the shader still needs to be

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Mesa (master): radv: merge tess rings into a single bo

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 1fc19a0f274e83a4066d9ea0741ea854288f5a15
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1fc19a0f274e83a4066d9ea0741ea854288f5a15

Author: Dave Airlie 
Date:   Sun Feb 25 23:23:45 2018 +

radv: merge tess rings into a single bo

Inspired by a passing commit to radeonsi.

Reviewed-by: Samuel Pitoiset 
Signed-off-by: Dave Airlie 

---

 src/amd/vulkan/radv_device.c  | 92 ++-
 src/amd/vulkan/radv_private.h |  3 +-
 2 files changed, 39 insertions(+), 56 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index f197b7f484..763c4e41c8 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -1066,10 +1066,8 @@ radv_queue_finish(struct radv_queue *queue)
queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
if (queue->gsvs_ring_bo)
queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
-   if (queue->tess_factor_ring_bo)
-   queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
-   if (queue->tess_offchip_ring_bo)
-   queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
+   if (queue->tess_rings_bo)
+   queue->device->ws->buffer_destroy(queue->tess_rings_bo);
if (queue->compute_scratch_bo)
queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
 }
@@ -1396,22 +1394,22 @@ fill_geom_tess_rings(struct radv_queue *queue,
 uint32_t gsvs_ring_size,
 struct radeon_winsys_bo *gsvs_ring_bo,
 uint32_t tess_factor_ring_size,
-struct radeon_winsys_bo *tess_factor_ring_bo,
+uint32_t tess_offchip_ring_offset,
 uint32_t tess_offchip_ring_size,
-struct radeon_winsys_bo *tess_offchip_ring_bo)
+struct radeon_winsys_bo *tess_rings_bo)
 {
uint64_t esgs_va = 0, gsvs_va = 0;
-   uint64_t tess_factor_va = 0, tess_offchip_va = 0;
+   uint64_t tess_va = 0, tess_offchip_va = 0;
uint32_t *desc = [4];
 
if (esgs_ring_bo)
esgs_va = radv_buffer_get_va(esgs_ring_bo);
if (gsvs_ring_bo)
gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
-   if (tess_factor_ring_bo)
-   tess_factor_va = radv_buffer_get_va(tess_factor_ring_bo);
-   if (tess_offchip_ring_bo)
-   tess_offchip_va = radv_buffer_get_va(tess_offchip_ring_bo);
+   if (tess_rings_bo) {
+   tess_va = radv_buffer_get_va(tess_rings_bo);
+   tess_offchip_va = tess_va + tess_offchip_ring_offset;
+   }
 
/* stride 0, num records - size, add tid, swizzle, elsize4,
   index stride 64 */
@@ -1488,8 +1486,8 @@ fill_geom_tess_rings(struct radv_queue *queue,
S_008F0C_ADD_TID_ENABLE(true);
desc += 4;
 
-   desc[0] = tess_factor_va;
-   desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
+   desc[0] = tess_va;
+   desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
S_008F04_STRIDE(0) |
S_008F04_SWIZZLE_ENABLE(false);
desc[2] = tess_factor_ring_size;
@@ -1598,13 +1596,13 @@ radv_get_preamble_cs(struct radv_queue *queue,
struct radeon_winsys_bo *compute_scratch_bo = NULL;
struct radeon_winsys_bo *esgs_ring_bo = NULL;
struct radeon_winsys_bo *gsvs_ring_bo = NULL;
-   struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
-   struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
+   struct radeon_winsys_bo *tess_rings_bo = NULL;
struct radeon_winsys_cs *dest_cs[3] = {0};
bool add_tess_rings = false, add_sample_positions = false;
unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
unsigned max_offchip_buffers;
unsigned hs_offchip_param = 0;
+   unsigned tess_offchip_ring_offset;
uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | 
RADEON_FLAG_NO_INTERPROCESS_SHARING;
if (!queue->has_tess_rings) {
if (needs_tess_rings)
@@ -1617,6 +1615,7 @@ radv_get_preamble_cs(struct radv_queue *queue,
tess_factor_ring_size = 32768 * 
queue->device->physical_device->rad_info.max_se;
hs_offchip_param = radv_get_hs_offchip_param(queue->device,
 _offchip_buffers);
+   tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
tess_offchip_ring_size = max_offchip_buffers *
queue->device->tess_offchip_block_dw_size * 4;
 
@@ -1684,33 +1683,25 @@ radv_get_preamble_cs(struct radv_queue *queue,
}
 
if (add_tess_rings) {
-   tess_factor_ring_bo = 
queue->device->ws->buffer_create(queue->device->ws,
- 

Mesa (master): radv: expose async compute on SI

[Dave Airlie]

Module: Mesa
Branch: master
Commit: 250468f6b7bb85b6c0097120ec9860d9185fd03a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=250468f6b7bb85b6c0097120ec9860d9185fd03a

Author: Dave Airlie 
Date:   Mon Feb 26 20:51:55 2018 +

radv: expose async compute on SI

It looks like we had all the pieces in place for this,
just never tested it and turned it on.

I don't see any CTS regressions and the computeshader
demo runs.

Acked-by: Bas Nieuwenhuizen 
Signed-off-by: Dave Airlie 

---

 src/amd/vulkan/radv_device.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 763c4e41c8..92865122ad 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -880,7 +880,6 @@ static void 
radv_get_physical_device_queue_family_properties(
int num_queue_families = 1;
int idx;
if (pdevice->rad_info.num_compute_rings > 0 &&
-   pdevice->rad_info.chip_class >= CIK &&
!(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
num_queue_families++;
 
@@ -907,7 +906,6 @@ static void 
radv_get_physical_device_queue_family_properties(
}
 
if (pdevice->rad_info.num_compute_rings > 0 &&
-   pdevice->rad_info.chip_class >= CIK &&
!(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
if (*pCount > idx) {
*pQueueFamilyProperties[idx] = 
(VkQueueFamilyProperties) {

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Mesa (master): docs: add release notes for 17.3.6

[Emil Velikov]

Module: Mesa
Branch: master
Commit: 676c58fbdbfd326e5dc9db3a23b28859950a1cac
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=676c58fbdbfd326e5dc9db3a23b28859950a1cac

Author: Emil Velikov 
Date:   Tue Feb 27 00:18:33 2018 +

docs: add release notes for 17.3.6

Signed-off-by: Emil Velikov 
(cherry picked from commit b3e5a3f35bfe5b69758ceb90f93fffbee01a5682)

---

 docs/relnotes/17.3.6.html | 83 +++
 1 file changed, 83 insertions(+)

diff --git a/docs/relnotes/17.3.6.html b/docs/relnotes/17.3.6.html
new file mode 100644
index 00..4d92a5033d
--- /dev/null
+++ b/docs/relnotes/17.3.6.html
@@ -0,0 +1,83 @@
+http://www.w3.org/TR/html4/loose.dtd;>
+
+
+  
+  Mesa Release Notes
+  
+
+
+
+
+  The Mesa 3D Graphics Library
+
+
+
+
+
+Mesa 17.3.5 Release Notes / February 19, 2018
+
+
+Mesa 17.3.6 is a bug fix release which fixes bugs found since the 17.3.5 
release.
+
+
+Mesa 17.3.6 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is only available if requested at context creation
+because compatibility contexts are not supported.
+
+
+
+SHA256 checksums
+
+TBD
+
+
+New features
+None
+
+
+Bug fixes
+
+
+
+https://bugs.freedesktop.org/show_bug.cgi?id=104383;>Bug 
104383 - [KBL] Intel GPU hang with firefox
+
+https://bugs.freedesktop.org/show_bug.cgi?id=104411;>Bug 
104411 - [CCS] lemonbar-xft GPU hang
+
+https://bugs.freedesktop.org/show_bug.cgi?id=104546;>Bug 
104546 - Crash happens when running compute pipeline after calling 
glxMakeCurrent two times
+
+
+
+
+Changes
+
+Emil Velikov (2):
+
+  docs: add sha256 checksums for 17.3.5
+  Update version to 17.3.6
+
+
+Jason Ekstrand (4):
+
+  i965/draw: Do resolves properly for textures used by TXF
+  i965: Replace draw_aux_buffer_disabled with draw_aux_usage
+  i965/draw: Set NEW_AUX_STATE when draw aux changes
+  i965: Stop disabling aux during texture preparation
+
+
+Kenneth Graunke (1):
+
+  i965: Don't disable CCS for RT dependencies when dispatching 
compute.
+
+
+Topi Pohjolainen (1):
+
+  i965: Don't try to disable render aux buffers for compute
+
+
+
+
+
+

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Mesa (master): docs: update calendar, add news and link release notes to 17.3.6

[Emil Velikov]

Module: Mesa
Branch: master
Commit: 784d81e97ee821790d1898adc5a7027050001e29
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=784d81e97ee821790d1898adc5a7027050001e29

Author: Emil Velikov 
Date:   Tue Feb 27 00:32:14 2018 +

docs: update calendar, add news and link release notes to 17.3.6

Signed-off-by: Emil Velikov 

---

 docs/index.html| 6 ++
 docs/release-calendar.html | 8 +---
 docs/relnotes.html | 1 +
 3 files changed, 8 insertions(+), 7 deletions(-)

diff --git a/docs/index.html b/docs/index.html
index d58f757ca3..4bbb3d36b1 100644
--- a/docs/index.html
+++ b/docs/index.html
@@ -16,6 +16,12 @@
 
 News
 
+February 26, 2018
+
+Mesa 17.3.6 is released.
+This is a bug-fix release.
+
+
 February 19, 2018
 
 Mesa 17.3.5 is released.
diff --git a/docs/release-calendar.html b/docs/release-calendar.html
index 43a2f9609c..25408c3604 100644
--- a/docs/release-calendar.html
+++ b/docs/release-calendar.html
@@ -39,13 +39,7 @@ if you'd like to nominate a patch in the next stable release.
 Notes
 
 
-17.3
-2018-02-23
-17.3.6
-Juan A. Suarez Romero
-
-
-
+17.3
 2018-03-09
 17.3.7
 Juan A. Suarez Romero
diff --git a/docs/relnotes.html b/docs/relnotes.html
index da072b6c8b..d28541ccf2 100644
--- a/docs/relnotes.html
+++ b/docs/relnotes.html
@@ -21,6 +21,7 @@ The release notes summarize what's new or changed in each 
Mesa release.
 
 
 
+17.3.6 release notes
 17.3.5 release notes
 17.3.4 release notes
 17.3.3 release notes

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Mesa (17.3): docs: add sha256 checksums for 17.3.6

[Emil Velikov]

Module: Mesa
Branch: 17.3
Commit: b00880973eeab5d29413eb8a27707f62904723ea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b00880973eeab5d29413eb8a27707f62904723ea

Author: Emil Velikov 
Date:   Tue Feb 27 00:28:54 2018 +

docs: add sha256 checksums for 17.3.6

Signed-off-by: Emil Velikov 

---

 docs/relnotes/17.3.6.html | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/docs/relnotes/17.3.6.html b/docs/relnotes/17.3.6.html
index 4d92a5033d..0dd1097975 100644
--- a/docs/relnotes/17.3.6.html
+++ b/docs/relnotes/17.3.6.html
@@ -31,7 +31,9 @@ because compatibility contexts are not supported.
 
 SHA256 checksums
 
-TBD
+d5e10ea3f0d11b06d2b0b235bba372a04278c39bc0e712090bda1f61842db188  
mesa-17.3.6.tar.gz
+e5915680d44ac9d05defdec529db7459ac9edd441c9845266eff2e2d3e57fbf8  
mesa-17.3.6.tar.xz
+
 
 
 New features

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Mesa (master): docs: add sha256 checksums for 17.3.6

[Emil Velikov]

Module: Mesa
Branch: master
Commit: d9391014debebe9722730484c3a2d5de7fae0499
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d9391014debebe9722730484c3a2d5de7fae0499

Author: Emil Velikov 
Date:   Tue Feb 27 00:28:54 2018 +

docs: add sha256 checksums for 17.3.6

Signed-off-by: Emil Velikov 
(cherry picked from commit b00880973eeab5d29413eb8a27707f62904723ea)

---

 docs/relnotes/17.3.6.html | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/docs/relnotes/17.3.6.html b/docs/relnotes/17.3.6.html
index 4d92a5033d..0dd1097975 100644
--- a/docs/relnotes/17.3.6.html
+++ b/docs/relnotes/17.3.6.html
@@ -31,7 +31,9 @@ because compatibility contexts are not supported.
 
 SHA256 checksums
 
-TBD
+d5e10ea3f0d11b06d2b0b235bba372a04278c39bc0e712090bda1f61842db188  
mesa-17.3.6.tar.gz
+e5915680d44ac9d05defdec529db7459ac9edd441c9845266eff2e2d3e57fbf8  
mesa-17.3.6.tar.xz
+
 
 
 New features

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Mesa: tag mesa-17.3.6: mesa-17.3.6

[Emil Velikov]

Module: Mesa
Branch: refs/tags/mesa-17.3.6
Tag:4555ad612d25c7199bab8ccc5054f8d75557324c
URL:
http://cgit.freedesktop.org/mesa/mesa/tag/?id=4555ad612d25c7199bab8ccc5054f8d75557324c

Tagger: Emil Velikov 
Date:   Tue Feb 27 00:22:55 2018 +

mesa-17.3.6
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Mesa (17.3): Update version to 17.3.6

[Emil Velikov]

Module: Mesa
Branch: 17.3
Commit: c17516c3ab61e4442a92b87bf7a8ca7c479b1ae7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c17516c3ab61e4442a92b87bf7a8ca7c479b1ae7

Author: Emil Velikov 
Date:   Tue Feb 27 00:13:31 2018 +

Update version to 17.3.6

Signed-off-by: Emil Velikov 

---

 VERSION | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/VERSION b/VERSION
index 8cd5aba540..6b82ee2616 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-17.3.5
+17.3.6

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Mesa (17.3): i965: Stop disabling aux during texture preparation

[Emil Velikov]

Module: Mesa
Branch: 17.3
Commit: a399c7fa1d5b88b25b798319db7b3ce71805d5b6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a399c7fa1d5b88b25b798319db7b3ce71805d5b6

Author: Jason Ekstrand 
Date:   Wed Jan 24 11:51:08 2018 -0800

i965: Stop disabling aux during texture preparation

Previously, we were handling self-dependencies by marking the render
buffer and then passing disable_aux=true to prepare_texture so that it
would do a resolve.  This works but ends us up doing to much resolving
in some cases.  Specifically, if we're doing something such as mipmap
generation, this would cause us to resolve all levels of the texture if
even one of them is overlapping.

Instead, this commit makes us wait until we process the framebuffer to
do these resolves and we only resolve the slices needed for rendering.
Doing this resolve puts them into the pass-through state so, even if we
do texture using CCS_E, the CCS data will effectively be ignored and the
real surface contents read.

Reviewed-by: Kenneth Graunke 
(cherry picked from commit df13588d2176dcf4800a882d926f389667772b46)

---

 src/mesa/drivers/dri/i965/brw_draw.c  | 12 +---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c |  5 ++---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  3 +--
 3 files changed, 8 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index a22c3c6ae6..edc8269bd7 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -443,15 +443,15 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool 
rendering,
  num_layers = INTEL_REMAINING_LAYERS;
   }
 
-  const bool disable_aux = rendering &&
+  if (rendering) {
  intel_disable_rb_aux_buffer(brw, draw_aux_buffer_disabled,
  tex_obj->mt, min_level, num_levels,
  "for sampling");
+  }
 
   intel_miptree_prepare_texture(brw, tex_obj->mt, view_format,
 min_level, num_levels,
-min_layer, num_layers,
-disable_aux);
+min_layer, num_layers);
 
   /* If any programs are using it with texelFetch, we may need to also do
* a prepare with an sRGB format to ensure texelFetch works "properly".
@@ -462,8 +462,7 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool 
rendering,
  if (txf_format != view_format) {
 intel_miptree_prepare_texture(brw, tex_obj->mt, txf_format,
   min_level, num_levels,
-  min_layer, num_layers,
-  disable_aux);
+  min_layer, num_layers);
  }
   }
 
@@ -535,8 +534,7 @@ brw_predraw_resolve_framebuffer(struct brw_context *brw,
  if (irb) {
 intel_miptree_prepare_texture(brw, irb->mt, irb->mt->surf.format,
   irb->mt_level, 1,
-  irb->mt_layer, irb->layer_count,
-  false);
+  irb->mt_layer, irb->layer_count);
  }
   }
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index bed6dd7ce1..a28e4ac01e 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2650,10 +2650,9 @@ intel_miptree_prepare_texture(struct brw_context *brw,
   struct intel_mipmap_tree *mt,
   enum isl_format view_format,
   uint32_t start_level, uint32_t num_levels,
-  uint32_t start_layer, uint32_t num_layers,
-  bool disable_aux)
+  uint32_t start_layer, uint32_t num_layers)
 {
-   enum isl_aux_usage aux_usage = disable_aux ? ISL_AUX_USAGE_NONE :
+   enum isl_aux_usage aux_usage =
   intel_miptree_texture_aux_usage(brw, mt, view_format);
bool clear_supported = aux_usage != ISL_AUX_USAGE_NONE;
 
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 6135af1452..7fcf09f118 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -642,8 +642,7 @@ intel_miptree_prepare_texture(struct brw_context *brw,
   struct intel_mipmap_tree *mt,
   enum isl_format view_format,
   uint32_t start_level, uint32_t num_levels,
-  uint32_t start_layer, uint32_t num_layers,
-

Mesa (17.3): docs: add release notes for 17.3.6

[Emil Velikov]

Module: Mesa
Branch: 17.3
Commit: b3e5a3f35bfe5b69758ceb90f93fffbee01a5682
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3e5a3f35bfe5b69758ceb90f93fffbee01a5682

Author: Emil Velikov 
Date:   Tue Feb 27 00:18:33 2018 +

docs: add release notes for 17.3.6

Signed-off-by: Emil Velikov 

---

 docs/relnotes/17.3.6.html | 83 +++
 1 file changed, 83 insertions(+)

diff --git a/docs/relnotes/17.3.6.html b/docs/relnotes/17.3.6.html
new file mode 100644
index 00..4d92a5033d
--- /dev/null
+++ b/docs/relnotes/17.3.6.html
@@ -0,0 +1,83 @@
+http://www.w3.org/TR/html4/loose.dtd;>
+
+
+  
+  Mesa Release Notes
+  
+
+
+
+
+  The Mesa 3D Graphics Library
+
+
+
+
+
+Mesa 17.3.5 Release Notes / February 19, 2018
+
+
+Mesa 17.3.6 is a bug fix release which fixes bugs found since the 17.3.5 
release.
+
+
+Mesa 17.3.6 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is only available if requested at context creation
+because compatibility contexts are not supported.
+
+
+
+SHA256 checksums
+
+TBD
+
+
+New features
+None
+
+
+Bug fixes
+
+
+
+https://bugs.freedesktop.org/show_bug.cgi?id=104383;>Bug 
104383 - [KBL] Intel GPU hang with firefox
+
+https://bugs.freedesktop.org/show_bug.cgi?id=104411;>Bug 
104411 - [CCS] lemonbar-xft GPU hang
+
+https://bugs.freedesktop.org/show_bug.cgi?id=104546;>Bug 
104546 - Crash happens when running compute pipeline after calling 
glxMakeCurrent two times
+
+
+
+
+Changes
+
+Emil Velikov (2):
+
+  docs: add sha256 checksums for 17.3.5
+  Update version to 17.3.6
+
+
+Jason Ekstrand (4):
+
+  i965/draw: Do resolves properly for textures used by TXF
+  i965: Replace draw_aux_buffer_disabled with draw_aux_usage
+  i965/draw: Set NEW_AUX_STATE when draw aux changes
+  i965: Stop disabling aux during texture preparation
+
+
+Kenneth Graunke (1):
+
+  i965: Don't disable CCS for RT dependencies when dispatching 
compute.
+
+
+Topi Pohjolainen (1):
+
+  i965: Don't try to disable render aux buffers for compute
+
+
+
+
+
+

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Mesa (17.3): i965: Don't try to disable render aux buffers for compute

[Emil Velikov]

Module: Mesa
Branch: 17.3
Commit: dda6a26b23c2963941d2aa446820d6ace395e602
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dda6a26b23c2963941d2aa446820d6ace395e602

Author: Topi Pohjolainen 
Date:   Tue Jan 16 14:17:00 2018 +0200

i965: Don't try to disable render aux buffers for compute

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104546
Reviewed-by: Kenneth Graunke 
Signed-off-by: Topi Pohjolainen 
(cherry picked from commit ec4bb693a0175744465f272a8bcea2db043ba1bc)

---

 src/mesa/drivers/dri/i965/brw_draw.c | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 5912e021cd..8e2ced5b3e 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -486,8 +486,10 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool 
rendering)
 tex_obj = intel_texture_object(u->TexObj);
 
 if (tex_obj && tex_obj->mt) {
-   intel_disable_rb_aux_buffer(brw, tex_obj->mt, 0, ~0,
-   "as a shader image");
+   if (rendering) {
+  intel_disable_rb_aux_buffer(brw, tex_obj->mt, 0, ~0,
+  "as a shader image");
+   }
 
intel_miptree_prepare_image(brw, tex_obj->mt);
 

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Mesa (17.3): i965/draw: Set NEW_AUX_STATE when draw aux changes

[Emil Velikov]

Module: Mesa
Branch: 17.3
Commit: c0abad571dfcd864f0fd38d0040597bdceb5a608
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0abad571dfcd864f0fd38d0040597bdceb5a608

Author: Jason Ekstrand 
Date:   Tue Jan 23 23:47:26 2018 -0800

i965/draw: Set NEW_AUX_STATE when draw aux changes

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104411
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104383
Fixes: ea0d2e98ecb369ab84e78c84709c0930ea8c293a
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Topi Pohjolainen 
Reviewed-by: Kenneth Graunke 
(cherry picked from commit 20f70ae3858bc213e052a8434f0e637eb36203c4)

---

 src/mesa/drivers/dri/i965/brw_draw.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 9def44cc45..a22c3c6ae6 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -557,7 +557,10 @@ brw_predraw_resolve_framebuffer(struct brw_context *brw,
  intel_miptree_render_aux_usage(brw, irb->mt, isl_format,
 blend_enabled,
 draw_aux_buffer_disabled[i]);
-  brw->draw_aux_usage[i] = aux_usage;
+  if (brw->draw_aux_usage[i] != aux_usage) {
+ brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;
+ brw->draw_aux_usage[i] = aux_usage;
+  }
 
   intel_miptree_prepare_render(brw, irb->mt, irb->mt_level,
irb->mt_layer, irb->layer_count,

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Mesa (17.3): i965/draw: Do resolves properly for textures used by TXF

[Emil Velikov]

Module: Mesa
Branch: 17.3
Commit: d654c58ca74aea432ccd5097210ef83a5022b87d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d654c58ca74aea432ccd5097210ef83a5022b87d

Author: Jason Ekstrand 
Date:   Tue Oct 31 16:29:22 2017 -0700

i965/draw: Do resolves properly for textures used by TXF

Reviewed-by: Iago Toral Quiroga 
Reviewed-by: Kenneth Graunke 
(cherry picked from commit 96aa5587155e7de87e80d617725cc66f6807c5d1)

---

 src/mesa/drivers/dri/i965/brw_draw.c | 41 
 1 file changed, 41 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 83ab53bd27..5912e021cd 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -40,6 +40,7 @@
 #include "swrast_setup/swrast_setup.h"
 #include "drivers/common/meta.h"
 #include "util/bitscan.h"
+#include "util/bitset.h"
 
 #include "brw_blorp.h"
 #include "brw_draw.h"
@@ -375,6 +376,20 @@ intel_disable_rb_aux_buffer(struct brw_context *brw,
return found;
 }
 
+static void
+mark_textures_used_for_txf(BITSET_WORD *used_for_txf,
+   const struct gl_program *prog)
+{
+   if (!prog)
+  return;
+
+   unsigned mask = prog->SamplersUsed & prog->info.textures_used_by_txf;
+   while (mask) {
+  int s = u_bit_scan();
+  BITSET_SET(used_for_txf, prog->SamplerUnits[s]);
+   }
+}
+
 /**
  * \brief Resolve buffers before drawing.
  *
@@ -390,6 +405,18 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool 
rendering)
memset(brw->draw_aux_buffer_disabled, 0,
   sizeof(brw->draw_aux_buffer_disabled));
 
+   BITSET_DECLARE(used_for_txf, MAX_COMBINED_TEXTURE_IMAGE_UNITS);
+   memset(used_for_txf, 0, sizeof(used_for_txf));
+   if (rendering) {
+  mark_textures_used_for_txf(used_for_txf, ctx->VertexProgram._Current);
+  mark_textures_used_for_txf(used_for_txf, ctx->TessCtrlProgram._Current);
+  mark_textures_used_for_txf(used_for_txf, ctx->TessEvalProgram._Current);
+  mark_textures_used_for_txf(used_for_txf, ctx->GeometryProgram._Current);
+  mark_textures_used_for_txf(used_for_txf, ctx->FragmentProgram._Current);
+   } else {
+  mark_textures_used_for_txf(used_for_txf, ctx->ComputeProgram._Current);
+   }
+
/* Resolve depth buffer and render cache of each enabled texture. */
int maxEnabledUnit = ctx->Texture._MaxEnabledTexImageUnit;
for (int i = 0; i <= maxEnabledUnit; i++) {
@@ -426,6 +453,20 @@ brw_predraw_resolve_inputs(struct brw_context *brw, bool 
rendering)
 min_layer, num_layers,
 disable_aux);
 
+  /* If any programs are using it with texelFetch, we may need to also do
+   * a prepare with an sRGB format to ensure texelFetch works "properly".
+   */
+  if (BITSET_TEST(used_for_txf, i)) {
+ enum isl_format txf_format =
+translate_tex_format(brw, tex_obj->_Format, GL_DECODE_EXT);
+ if (txf_format != view_format) {
+intel_miptree_prepare_texture(brw, tex_obj->mt, txf_format,
+  min_level, num_levels,
+  min_layer, num_layers,
+  disable_aux);
+ }
+  }
+
   brw_cache_flush_for_read(brw, tex_obj->mt->bo);
 
   if (tex_obj->base.StencilSampling ||

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Mesa (17.3): i965: Don't disable CCS for RT dependencies when dispatching compute.

[Emil Velikov]

Module: Mesa
Branch: 17.3
Commit: 2475b3a56c1a3224991185b6f7527ed7c86e1dd8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2475b3a56c1a3224991185b6f7527ed7c86e1dd8

Author: Kenneth Graunke 
Date:   Mon Oct 23 15:46:47 2017 -0700

i965: Don't disable CCS for RT dependencies when dispatching compute.

Compute shaders don't have access to the framebuffer, so there's no
point in worrying whether a texture is bound as a render target.

This saves a bunch of resolves in GFXBench4 Manhattan 3.1, but doesn't
seem to impact performance at all, at least on Apollolake.

Reviewed-by: Jason Ekstrand 
Reviewed-by: Iago Toral Quiroga 
(cherry picked from commit 583ce96c9429e23c33daeb7025210ef73ae51688)

---

 src/mesa/drivers/dri/i965/brw_compute.c | 2 +-
 src/mesa/drivers/dri/i965/brw_context.h | 2 +-
 src/mesa/drivers/dri/i965/brw_draw.c| 6 +++---
 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_compute.c 
b/src/mesa/drivers/dri/i965/brw_compute.c
index c1b2df590b..9be7523bab 100644
--- a/src/mesa/drivers/dri/i965/brw_compute.c
+++ b/src/mesa/drivers/dri/i965/brw_compute.c
@@ -177,7 +177,7 @@ brw_dispatch_compute_common(struct gl_context *ctx)
 
brw_validate_textures(brw);
 
-   brw_predraw_resolve_inputs(brw);
+   brw_predraw_resolve_inputs(brw, false);
 
/* Flush the batch if the batch/state buffers are nearly full.  We can
 * grow them if needed, but this is not free, so we'd like to avoid it.
diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index d6f2ed501f..386765b7f6 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1244,7 +1244,7 @@ void intel_update_renderbuffers(__DRIcontext *context,
 __DRIdrawable *drawable);
 void intel_prepare_render(struct brw_context *brw);
 
-void brw_predraw_resolve_inputs(struct brw_context *brw);
+void brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering);
 
 void intel_resolve_for_dri2_flush(struct brw_context *brw,
   __DRIdrawable *drawable);
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 19def47d09..83ab53bd27 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -382,7 +382,7 @@ intel_disable_rb_aux_buffer(struct brw_context *brw,
  * enabled depth texture, and flush the render cache for any dirty textures.
  */
 void
-brw_predraw_resolve_inputs(struct brw_context *brw)
+brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering)
 {
struct gl_context *ctx = >ctx;
struct intel_texture_object *tex_obj;
@@ -417,7 +417,7 @@ brw_predraw_resolve_inputs(struct brw_context *brw)
  num_layers = INTEL_REMAINING_LAYERS;
   }
 
-  const bool disable_aux =
+  const bool disable_aux = rendering &&
  intel_disable_rb_aux_buffer(brw, tex_obj->mt, min_level, num_levels,
  "for sampling");
 
@@ -697,7 +697,7 @@ brw_prepare_drawing(struct gl_context *ctx,
 * and finalizing textures but before setting up any hardware state for
 * this draw call.
 */
-   brw_predraw_resolve_inputs(brw);
+   brw_predraw_resolve_inputs(brw, true);
brw_predraw_resolve_framebuffer(brw);
 
/* Bind all inputs, derive varying and size information:

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Mesa (17.3): i965: Replace draw_aux_buffer_disabled with draw_aux_usage

[Emil Velikov]

Module: Mesa
Branch: 17.3
Commit: b626f342acf5db170319d6a4292468755aa6336e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b626f342acf5db170319d6a4292468755aa6336e

Author: Jason Ekstrand 
Date:   Tue Jan 23 23:13:10 2018 -0800

i965: Replace draw_aux_buffer_disabled with draw_aux_usage

Instead of keeping an array of booleans, we now hang onto an array of
isl_aux_usage enums.  This means that the thing we are passing from
brw_draw.c to surface state setup is the thing that surface state setup
actually needs instead of an input to compute what it needs.

Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Topi Pohjolainen 
Reviewed-by: Kenneth Graunke 
(cherry picked from commit e52a9f18d69c94b7cb7f81361cdb9e2582c3d742)

---

 src/mesa/drivers/dri/i965/brw_compute.c  |  2 +-
 src/mesa/drivers/dri/i965/brw_context.h  | 15 +--
 src/mesa/drivers/dri/i965/brw_draw.c | 32 
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 13 +++---
 4 files changed, 27 insertions(+), 35 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_compute.c 
b/src/mesa/drivers/dri/i965/brw_compute.c
index 9be7523bab..5ce899bcbc 100644
--- a/src/mesa/drivers/dri/i965/brw_compute.c
+++ b/src/mesa/drivers/dri/i965/brw_compute.c
@@ -177,7 +177,7 @@ brw_dispatch_compute_common(struct gl_context *ctx)
 
brw_validate_textures(brw);
 
-   brw_predraw_resolve_inputs(brw, false);
+   brw_predraw_resolve_inputs(brw, false, NULL);
 
/* Flush the batch if the batch/state buffers are nearly full.  We can
 * grow them if needed, but this is not free, so we'd like to avoid it.
diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 386765b7f6..7e57c3660c 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1210,15 +1210,11 @@ struct brw_context
 
struct brw_fast_clear_state *fast_clear_state;
 
-   /* Array of flags telling if auxiliary buffer is disabled for corresponding
-* renderbuffer. If draw_aux_buffer_disabled[i] is set then use of
-* auxiliary buffer for gl_framebuffer::_ColorDrawBuffers[i] is
-* disabled.
-* This is needed in case the same underlying buffer is also configured
-* to be sampled but with a format that the sampling engine can't treat
-* compressed or fast cleared.
+   /* Array of aux usages to use for drawing.  Aux usage for render targets is
+* a bit more complex than simply calling a single function so we need some
+* way of passing it form brw_draw.c to surface state setup.
 */
-   bool draw_aux_buffer_disabled[MAX_DRAW_BUFFERS];
+   enum isl_aux_usage draw_aux_usage[MAX_DRAW_BUFFERS];
 
__DRIcontext *driContext;
struct intel_screen *screen;
@@ -1244,7 +1240,8 @@ void intel_update_renderbuffers(__DRIcontext *context,
 __DRIdrawable *drawable);
 void intel_prepare_render(struct brw_context *brw);
 
-void brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering);
+void brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering,
+bool *draw_aux_buffer_disabled);
 
 void intel_resolve_for_dri2_flush(struct brw_context *brw,
   __DRIdrawable *drawable);
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c 
b/src/mesa/drivers/dri/i965/brw_draw.c
index 8e2ced5b3e..9def44cc45 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -345,6 +345,7 @@ brw_merge_inputs(struct brw_context *brw,
  */
 static bool
 intel_disable_rb_aux_buffer(struct brw_context *brw,
+bool *draw_aux_buffer_disabled,
 struct intel_mipmap_tree *tex_mt,
 unsigned min_level, unsigned num_levels,
 const char *usage)
@@ -364,7 +365,7 @@ intel_disable_rb_aux_buffer(struct brw_context *brw,
   if (irb && irb->mt->bo == tex_mt->bo &&
   irb->mt_level >= min_level &&
   irb->mt_level < min_level + num_levels) {
- found = brw->draw_aux_buffer_disabled[i] = true;
+ found = draw_aux_buffer_disabled[i] = true;
   }
}
 
@@ -397,14 +398,12 @@ mark_textures_used_for_txf(BITSET_WORD *used_for_txf,
  * enabled depth texture, and flush the render cache for any dirty textures.
  */
 void
-brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering)
+brw_predraw_resolve_inputs(struct brw_context *brw, bool rendering,
+   bool *draw_aux_buffer_disabled)
 {
struct gl_context *ctx = >ctx;
struct intel_texture_object *tex_obj;
 
-   memset(brw->draw_aux_buffer_disabled, 0,
-  sizeof(brw->draw_aux_buffer_disabled));
-
BITSET_DECLARE(used_for_txf, MAX_COMBINED_TEXTURE_IMAGE_UNITS);
memset(used_for_txf, 0, 

Mesa (master): meson: fix building without GL

[Dylan Baker]

Module: Mesa
Branch: master
Commit: b9636fe38aea6af1d3a30528da89069fc390b6a0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9636fe38aea6af1d3a30528da89069fc390b6a0

Author: Dylan Baker 
Date:   Mon Feb 26 08:43:54 2018 -0800

meson: fix building without GL

libgl will be undefined _glx, so move that check inside the
`if with_glx != 'disabled'` block.

v2: - Simplify commit message (Eric, Emil)

Fixes: 5c460337fd9c109 ("meson: Fix GL and EGL pkg-config files with glvnd")
Reported-by: Jason Ekstrand 
Signed-off-by: Dylan Baker 
CC: Daniel Stone 
Acked-by: Jason Ekstrand 
Untested-by: Jason Ekstrand 
Acked-by: Eric Engestrom 
Reviewed-by: Emil Velikov 

---

 src/meson.build | 19 ++-
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/src/meson.build b/src/meson.build
index b2c045fce1..19005271d7 100644
--- a/src/meson.build
+++ b/src/meson.build
@@ -82,18 +82,19 @@ if with_gallium
   subdir('gallium')
 endif
 
-# If using glvnd the pkg-config header should not point to GL_mesa, it should
-# point to GL. glvnd is only available on unix like platforms so adding -l
-# should be safe here
-# TODO: in the glvnd case glvnd itself should really be providing this.
-if with_glvnd
-  _gl = '-L${libdir} -lGL'
-else
-  _gl = libgl
-endif
 # This must be after at least mesa, glx, and gallium, since libgl will be
 # defined in one of those subdirs depending on the glx provider.
 if with_glx != 'disabled'
+  # If using glvnd the pkg-config header should not point to GL_mesa, it should
+  # point to GL. glvnd is only available on unix like platforms so adding -l
+  # should be safe here
+  # TODO: in the glvnd case glvnd itself should really be providing this.
+  if with_glvnd
+_gl = '-L${libdir} -lGL'
+  else
+_gl = libgl
+  endif
+
   pkg.generate(
 name : 'gl',
 description : 'Mesa OpenGL Library',

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Mesa (master): intel: aubinator_error_decode: fix segfault on missing register

[Lionel Landwerlin]

Module: Mesa
Branch: master
Commit: fca9f5b5851d2eeba6d030e28dd783017fef55cf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fca9f5b5851d2eeba6d030e28dd783017fef55cf

Author: Lionel Landwerlin 
Date:   Thu Feb 22 13:41:10 2018 +

intel: aubinator_error_decode: fix segfault on missing register

Some register might be missing in our genxmls. Don't try to decode
them.

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Kenneth Graunke 

---

 src/intel/tools/aubinator_error_decode.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/intel/tools/aubinator_error_decode.c 
b/src/intel/tools/aubinator_error_decode.c
index 2331114b44..017be5bbc2 100644
--- a/src/intel/tools/aubinator_error_decode.c
+++ b/src/intel/tools/aubinator_error_decode.c
@@ -65,7 +65,8 @@ print_head(unsigned int reg)
 static void
 print_register(struct gen_spec *spec, const char *name, uint32_t reg)
 {
-   struct gen_group *reg_spec = gen_spec_find_register_by_name(spec, name);
+   struct gen_group *reg_spec =
+  name ? gen_spec_find_register_by_name(spec, name) : NULL;
 
if (reg_spec) {
   gen_print_group(stdout, reg_spec, 0, , 0,

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Mesa (master): *-symbol-check: use correct `nm` path when cross-compiling

[Eric Engeström]

Module: Mesa
Branch: master
Commit: 11d45304fd20bbdf07222830e76d3f9977e803b4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=11d45304fd20bbdf07222830e76d3f9977e803b4

Author: Eric Engestrom 
Date:   Fri Feb 23 17:02:08 2018 +

*-symbol-check: use correct `nm` path when cross-compiling

Inspired-by: a similar patch for libdrm by Heiko Becker
Signed-off-by: Eric Engestrom 
Reviewed-by: Emil Velikov 

---

 configure.ac  | 1 +
 meson.build   | 3 +++
 src/egl/egl-symbols-check | 2 +-
 src/egl/meson.build   | 1 +
 src/egl/wayland/wayland-egl/meson.build   | 1 +
 src/egl/wayland/wayland-egl/wayland-egl-symbols-check | 2 +-
 src/gbm/gbm-symbols-check | 3 +--
 src/gbm/meson.build   | 1 +
 src/mapi/es1api/ABI-check | 2 +-
 src/mapi/es1api/meson.build   | 1 +
 src/mapi/es2api/ABI-check | 2 +-
 src/mapi/es2api/meson.build   | 1 +
 12 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/configure.ac b/configure.ac
index 346c813035..d8093597dd 100644
--- a/configure.ac
+++ b/configure.ac
@@ -116,6 +116,7 @@ dnl other CC/CXX flags related help
 AC_ARG_VAR([CXX11_CXXFLAGS], [Compiler flag to enable C++11 support (only 
needed if not
   enabled by default and different  from 
-std=c++11)])
 AM_PROG_CC_C_O
+AC_PROG_NM
 AM_PROG_AS
 AX_CHECK_GNU_MAKE
 AC_CHECK_PROGS([PYTHON2], [python2.7 python2 python])
diff --git a/meson.build b/meson.build
index 8cf67b8171..6f2615f9d1 100644
--- a/meson.build
+++ b/meson.build
@@ -1256,6 +1256,9 @@ endif
 
 pkg = import('pkgconfig')
 
+env_test = environment()
+env_test.set('NM', find_program('nm').path())
+
 subdir('include')
 subdir('bin')
 subdir('src')
diff --git a/src/egl/egl-symbols-check b/src/egl/egl-symbols-check
index ae867d04bc..460e61a357 100755
--- a/src/egl/egl-symbols-check
+++ b/src/egl/egl-symbols-check
@@ -8,7 +8,7 @@ then
   exit 1
 fi
 
-FUNCS=$(nm -D --defined-only $LIB | grep -o "T .*" | cut -c 3- | while read 
func; do
+FUNCS=$($NM -D --defined-only $LIB | grep -o "T .*" | cut -c 3- | while read 
func; do
 ( grep -q "^$func$" || echo $func )  

Mesa (master): nvir/gm107: consider FILE_FLAGS dependencies in SchedDataCalculatorGM107

[Karol Herbst]

Module: Mesa
Branch: master
Commit: ef308d40070014b92aaf07a228edc73bd2e85570
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef308d40070014b92aaf07a228edc73bd2e85570

Author: Karol Herbst 
Date:   Tue Dec  5 11:09:54 2017 +0100

nvir/gm107: consider FILE_FLAGS dependencies in SchedDataCalculatorGM107

currently while insterting barriers, writes and reads to FILE_FLAGS aren't
considered. This can lead to WaR hazards in some situations.

With the previous commit fixes shaders with intstructions like this:
  mad u32 $r2 $r4 $r11 $r2
  mad u32 { $r5 $c0 } $r4 $r10 $r6
  mad (SUBOP:1) u32 $r3 $r4 $r10 $r2 $c0

Affects OpenCL CTS tests on Maxwell+:
basic/test_basic intmath_long
basic/test_basic intmath_long2
basic/test_basic intmath_long4

v2: only put barriers on instructions which actually read flags

Reviewed-by: Samuel Pitoiset 
Signed-off-by: Karol Herbst 

---

 .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp| 15 ++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index 96bd276884..fafece81ad 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
@@ -3944,6 +3944,7 @@ SchedDataCalculatorGM107::needWrDepBar(const Instruction 
*insn) const
 
for (int d = 0; insn->defExists(d); ++d) {
   if (insn->def(d).getFile() == FILE_GPR ||
+  insn->def(d).getFile() == FILE_FLAGS ||
   insn->def(d).getFile() == FILE_PREDICATE)
  return true;
}
@@ -3983,6 +3984,12 @@ SchedDataCalculatorGM107::findFirstUse(const Instruction 
*bari) const
   continue;
return insn;
 }
+if (def.getFile() == FILE_FLAGS) {
+   if (insn->src(s).getFile() != FILE_FLAGS ||
+   src->reg.data.id != minGPR)
+  continue;
+   return insn;
+}
  }
   }
}
@@ -4002,7 +4009,8 @@ SchedDataCalculatorGM107::findFirstDef(const Instruction 
*bari) const
 
   for (int d = 0; insn->defExists(d); ++d) {
  const Value *def = insn->def(d).rep();
- if (insn->def(d).getFile() != FILE_GPR)
+ if (insn->def(d).getFile() != FILE_GPR &&
+ insn->def(d).getFile() != FILE_FLAGS)
 continue;
 
  minGPR = def->reg.data.id;
@@ -4010,7 +4018,12 @@ SchedDataCalculatorGM107::findFirstDef(const Instruction 
*bari) const
 
  for (int s = 0; bari->srcExists(s); ++s) {
 const Value *src = bari->src(s).rep();
+if (bari->src(s).getFile() == FILE_FLAGS &&
+insn->def(d).getFile() == FILE_FLAGS &&
+src->reg.data.id == minGPR)
+   return insn;
 if (bari->src(s).getFile() != FILE_GPR ||
+insn->def(d).getFile() != FILE_GPR ||
 src->reg.data.id + src->reg.size / 4 - 1 < minGPR ||
 src->reg.data.id > maxGPR)
continue;

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Mesa (master): nvir/gm107: iterate over all defs in SchedDataCalculatorGM107::findFirstUse

[Karol Herbst]

Module: Mesa
Branch: master
Commit: 2f07f823c9e5563156531057f1ea6e24670bba7f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f07f823c9e5563156531057f1ea6e24670bba7f

Author: Karol Herbst 
Date:   Tue Dec  5 10:32:25 2017 +0100

nvir/gm107: iterate over all defs in SchedDataCalculatorGM107::findFirstUse

In the sched data calculator we have to track first use of defs by iterating
over all defs of an instruction, not just the first one.

v2: fix minGRP and maxGRP values

Reviewed-by: Samuel Pitoiset 
Signed-off-by: Karol Herbst 

---

 .../drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 34 --
 1 file changed, 18 insertions(+), 16 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
index b1e9f941fe..96bd276884 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp
@@ -3956,31 +3956,33 @@ Instruction *
 SchedDataCalculatorGM107::findFirstUse(const Instruction *bari) const
 {
Instruction *insn, *next;
-   int minGPR, maxGPR;
 
if (!bari->defExists(0))
   return NULL;
 
-   minGPR = bari->def(0).rep()->reg.data.id;
-   maxGPR = minGPR + bari->def(0).rep()->reg.size / 4 - 1;
-
for (insn = bari->next; insn != NULL; insn = next) {
   next = insn->next;
 
   for (int s = 0; insn->srcExists(s); ++s) {
  const Value *src = insn->src(s).rep();
- if (bari->def(0).getFile() == FILE_GPR) {
-if (insn->src(s).getFile() != FILE_GPR ||
-src->reg.data.id + src->reg.size / 4 - 1 < minGPR ||
-src->reg.data.id > maxGPR)
-   continue;
-return insn;
- } else
- if (bari->def(0).getFile() == FILE_PREDICATE) {
-if (insn->src(s).getFile() != FILE_PREDICATE ||
-src->reg.data.id != minGPR)
-   continue;
-return insn;
+ for (int d = 0; bari->defExists(d); ++d) {
+const ValueDef  = bari->def(d);
+int minGPR = def.rep()->reg.data.id;
+int maxGPR = minGPR + def.rep()->reg.size / 4 - 1;
+
+if (def.getFile() == FILE_GPR) {
+   if (insn->src(s).getFile() != FILE_GPR ||
+   src->reg.data.id + src->reg.size / 4 - 1 < minGPR ||
+   src->reg.data.id > maxGPR)
+  continue;
+   return insn;
+} else
+if (def.getFile() == FILE_PREDICATE) {
+   if (insn->src(s).getFile() != FILE_PREDICATE ||
+   src->reg.data.id != minGPR)
+  continue;
+   return insn;
+}
  }
   }
}

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Mesa (master): ac/nir: use ordered float comparisons except for not equal

[Samuel Pitoiset]

Module: Mesa
Branch: master
Commit: e05507a427b79e481eb8e45d7aa3c9b4b78376bf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e05507a427b79e481eb8e45d7aa3c9b4b78376bf

Author: Samuel Pitoiset 
Date:   Fri Feb 23 14:21:06 2018 +0100

ac/nir: use ordered float comparisons except for not equal

Original patch from Timothy Arceri, I have just fixed the
not equal case locally.

This fixes one important rendering issue in Wolfenstein 2
(the cutscene transition issue).

RadeonSI uses the same ordered comparisons, so I guess that
what we should do as well.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104302
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104905
Cc: 
Signed-off-by: Samuel Pitoiset 
Reviewed-by: Marek Olšák 
Reviewed-by: Connor Abbott 

---

 src/amd/common/ac_nir_to_llvm.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 2c5a6e6cf6..8183e48bd3 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1797,16 +1797,16 @@ static void visit_alu(struct ac_nir_context *ctx, const 
nir_alu_instr *instr)
result = emit_int_cmp(>ac, LLVMIntUGE, src[0], src[1]);
break;
case nir_op_feq:
-   result = emit_float_cmp(>ac, LLVMRealUEQ, src[0], src[1]);
+   result = emit_float_cmp(>ac, LLVMRealOEQ, src[0], src[1]);
break;
case nir_op_fne:
result = emit_float_cmp(>ac, LLVMRealUNE, src[0], src[1]);
break;
case nir_op_flt:
-   result = emit_float_cmp(>ac, LLVMRealULT, src[0], src[1]);
+   result = emit_float_cmp(>ac, LLVMRealOLT, src[0], src[1]);
break;
case nir_op_fge:
-   result = emit_float_cmp(>ac, LLVMRealUGE, src[0], src[1]);
+   result = emit_float_cmp(>ac, LLVMRealOGE, src[0], src[1]);
break;
case nir_op_fabs:
result = emit_intrin_1f_param(>ac, "llvm.fabs",

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Mesa (master): android: vulkan/util: add dependency on libnativewindow for O and later

[Tapani Pälli]

Module: Mesa
Branch: master
Commit: 6451b0703ff3027b746d6268b98dd2b3e6698be5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6451b0703ff3027b746d6268b98dd2b3e6698be5

Author: Mauro Rossi 
Date:   Sun Feb  4 22:57:11 2018 +0100

android: vulkan/util: add dependency on libnativewindow for O and later

Similar to 90dd6e5 ("Android: egl: add dependency on libnativewindow")

Fixes the following building error:

In file included from 
out/target/product/x86_64/obj_x86/STATIC_LIBRARIES/libmesa_vulkan_util_intermediates/util/vk_enum_to_str.c:26:
external/mesa/include/vulkan/vk_android_native_buffer.h:22:10: fatal error: 
'system/window.h' file not found
 ^
1 error generated.

Cc: "18.0" 
Reviewed-by: Emil Velikov 

---

 src/vulkan/Android.mk | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/vulkan/Android.mk b/src/vulkan/Android.mk
index 6d6df938ab..70b23eae08 100644
--- a/src/vulkan/Android.mk
+++ b/src/vulkan/Android.mk
@@ -59,5 +59,9 @@ $(LOCAL_GENERATED_SOURCES): 
$(MESA_TOP)/src/vulkan/util/gen_enum_to_str.py \
 LOCAL_EXPORT_C_INCLUDE_DIRS := \
 $(intermediates)
 
+ifeq ($(filter $(MESA_ANDROID_MAJOR_VERSION), 4 5 6 7),)
+LOCAL_SHARED_LIBRARIES += libnativewindow
+endif
+
 include $(MESA_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)

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Mesa (master): android: anv: add dependency on libnativewindow for O and later

[Tapani Pälli]

Module: Mesa
Branch: master
Commit: d448954228e69fd1b4000ea13e28c2ba2832db13
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d448954228e69fd1b4000ea13e28c2ba2832db13

Author: Mauro Rossi 
Date:   Mon Feb 26 14:42:47 2018 +0200

android: anv: add dependency on libnativewindow for O and later

Similar to 90dd6e5 ("Android: egl: add dependency on libnativewindow")

Fixes the following building errors:

In file included from external/mesa/src/intel/vulkan/gen7_cmd_buffer.c:30:
In file included from external/mesa/src/intel/vulkan/anv_private.h:72:
external/mesa/include/vulkan/vk_android_native_buffer.h:22:10: fatal
error: 'system/window.h' file not found
 ^
1 error generated.
...
In file included from external/mesa/src/intel/vulkan/anv_gem.c:32:
In file included from external/mesa/src/intel/vulkan/anv_private.h:72:
external/mesa/include/vulkan/vk_android_native_buffer.h:22:10: fatal
error: 'system/window.h' file not found
 ^
1 error generated.

Cc: "18.0" 
Reviewed-by: Tapani Pälli 
Reviewed-by: Emil Velikov 

---

 src/intel/Android.vulkan.mk | 22 ++
 1 file changed, 14 insertions(+), 8 deletions(-)

diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk
index 45c3633ba8..07e69d890a 100644
--- a/src/intel/Android.vulkan.mk
+++ b/src/intel/Android.vulkan.mk
@@ -85,6 +85,12 @@ ANV_INCLUDES := \
$(call 
generated-sources-dir-for,STATIC_LIBRARIES,libmesa_vulkan_common,,)/vulkan \
$(call 
generated-sources-dir-for,STATIC_LIBRARIES,libmesa_vulkan_util,,)/util
 
+ANV_SHARED_LIBRARIES := libdrm
+
+ifeq ($(filter $(MESA_ANDROID_MAJOR_VERSION), 4 5 6 7),)
+ANV_SHARED_LIBRARIES += libnativewindow
+endif
+
 #
 # libanv for gen7
 #
@@ -100,7 +106,7 @@ LOCAL_C_INCLUDES := $(ANV_INCLUDES)
 
 LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml
 
-LOCAL_SHARED_LIBRARIES := libdrm
+LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES)
 
 include $(MESA_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)
@@ -120,7 +126,7 @@ LOCAL_C_INCLUDES := $(ANV_INCLUDES)
 
 LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml
 
-LOCAL_SHARED_LIBRARIES := libdrm
+LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES)
 
 include $(MESA_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)
@@ -140,7 +146,7 @@ LOCAL_C_INCLUDES := $(ANV_INCLUDES)
 
 LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml
 
-LOCAL_SHARED_LIBRARIES := libdrm
+LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES)
 
 include $(MESA_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)
@@ -160,7 +166,7 @@ LOCAL_C_INCLUDES := $(ANV_INCLUDES)
 
 LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml
 
-LOCAL_SHARED_LIBRARIES := libdrm
+LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES)
 
 include $(MESA_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)
@@ -180,7 +186,7 @@ LOCAL_C_INCLUDES := $(ANV_INCLUDES)
 
 LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml
 
-LOCAL_SHARED_LIBRARIES := libdrm
+LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES)
 
 include $(MESA_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)
@@ -200,7 +206,7 @@ LOCAL_C_INCLUDES := $(ANV_INCLUDES)
 
 LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml
 
-LOCAL_SHARED_LIBRARIES := libdrm
+LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES)
 
 include $(MESA_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)
@@ -256,7 +262,7 @@ $(intermediates)/vulkan/anv_extensions.h:
--xml 
$(MESA_TOP)/src/vulkan/registry/vk_android_native_buffer.xml \
--out-h $@
 
-LOCAL_SHARED_LIBRARIES := libdrm
+LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES)
 
 include $(MESA_COMMON_MK)
 include $(BUILD_STATIC_LIBRARY)
@@ -304,7 +310,7 @@ LOCAL_WHOLE_STATIC_LIBRARIES := \
libmesa_intel_compiler \
libmesa_anv_entrypoints
 
-LOCAL_SHARED_LIBRARIES := libdrm libz libsync liblog
+LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES) libz libsync liblog
 
 include $(MESA_COMMON_MK)
 include $(BUILD_SHARED_LIBRARY)

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Mesa (master): android: anv/extensions: fix generated sources build

[Tapani Pälli]

Module: Mesa
Branch: master
Commit: 9a508b719be32ef10ca929250b7aafba313104c6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a508b719be32ef10ca929250b7aafba313104c6

Author: Mauro Rossi 
Date:   Sun Feb  4 22:57:09 2018 +0100

android: anv/extensions: fix generated sources build

Building rules are aligned to automake ones

The correct script to build anv_extensions.{c,h} is anv_extensions_gen.py
Generation rules for anv_extensions.c requires --out-c option
Generation rules for anv_extensions.h were missing
Necessary include paths are added to avoid following build errors:

cp: cannot stat 
'.../gen/STATIC_LIBRARIES/libmesa_vulkan_common_intermediates/vulkan/anv_extensions.c':
No such file or directory

In file included from external/mesa/src/intel/vulkan/anv_gem.c:32:
external/mesa/src/intel/vulkan/anv_private.h:75:10: fatal error: 
'anv_extensions.h' file not found
 ^~
1 error generated.

In file included from external/mesa/src/intel/vulkan/anv_batch_chain.c:30:
external/mesa/src/intel/vulkan/anv_private.h:75:10: fatal error: 
'anv_extensions.h' file not found
 ^~
1 error generated.

Fixes: dd088d4bec7 ("anv/extensions: Generate a header file with extension 
tables")
Cc: "18.0" 
Reviewed-by: Tapani Pälli 

---

 src/intel/Android.vulkan.mk | 16 +---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk
index 6fe736d397..45c3633ba8 100644
--- a/src/intel/Android.vulkan.mk
+++ b/src/intel/Android.vulkan.mk
@@ -25,7 +25,7 @@ include $(LOCAL_PATH)/Makefile.sources
 
 VK_ENTRYPOINTS_SCRIPT := $(MESA_PYTHON2) 
$(LOCAL_PATH)/vulkan/anv_entrypoints_gen.py
 
-VK_EXTENSIONS_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/vulkan/anv_extensions.py
+VK_EXTENSIONS_SCRIPT := $(MESA_PYTHON2) 
$(LOCAL_PATH)/vulkan/anv_extensions_gen.py
 
 VULKAN_COMMON_INCLUDES := \
$(MESA_TOP)/include \
@@ -82,6 +82,7 @@ ANV_INCLUDES := \
$(VULKAN_COMMON_INCLUDES) \
$(call 
generated-sources-dir-for,STATIC_LIBRARIES,libmesa_anv_entrypoints,,)/vulkan \
$(call generated-sources-dir-for,STATIC_LIBRARIES,libmesa_nir,,)/nir \
+   $(call 
generated-sources-dir-for,STATIC_LIBRARIES,libmesa_vulkan_common,,)/vulkan \
$(call 
generated-sources-dir-for,STATIC_LIBRARIES,libmesa_vulkan_util,,)/util
 
 #
@@ -232,6 +233,7 @@ LOCAL_WHOLE_STATIC_LIBRARIES := \
 
 LOCAL_GENERATED_SOURCES += $(intermediates)/vulkan/anv_entrypoints.c
 LOCAL_GENERATED_SOURCES += $(intermediates)/vulkan/anv_extensions.c
+LOCAL_GENERATED_SOURCES += $(intermediates)/vulkan/anv_extensions.h
 
 $(intermediates)/vulkan/anv_entrypoints.c:
@mkdir -p $(dir $@)
@@ -245,7 +247,14 @@ $(intermediates)/vulkan/anv_extensions.c:
$(VK_EXTENSIONS_SCRIPT) \
--xml $(MESA_TOP)/src/vulkan/registry/vk.xml \
--xml 
$(MESA_TOP)/src/vulkan/registry/vk_android_native_buffer.xml \
-   --out $@
+   --out-c $@
+
+$(intermediates)/vulkan/anv_extensions.h:
+   @mkdir -p $(dir $@)
+   $(VK_EXTENSIONS_SCRIPT) \
+   --xml $(MESA_TOP)/src/vulkan/registry/vk.xml \
+   --xml 
$(MESA_TOP)/src/vulkan/registry/vk_android_native_buffer.xml \
+   --out-h $@
 
 LOCAL_SHARED_LIBRARIES := libdrm
 
@@ -272,7 +281,8 @@ LOCAL_SRC_FILES := \
 
 LOCAL_C_INCLUDES := \
$(VULKAN_COMMON_INCLUDES) \
-   $(call 
generated-sources-dir-for,STATIC_LIBRARIES,libmesa_anv_entrypoints,,)/vulkan
+   $(call 
generated-sources-dir-for,STATIC_LIBRARIES,libmesa_anv_entrypoints,,)/vulkan \
+   $(call 
generated-sources-dir-for,STATIC_LIBRARIES,libmesa_vulkan_common,,)/vulkan
 
 LOCAL_EXPORT_C_INCLUDE_DIRS := $(MESA_TOP)/src/intel/vulkan
 

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Mesa (master): radeonsi: don't use struct si_descriptors for vertex buffer descriptors

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 8d6e6b1d7c9ad73f6d829c6c40ce20a499e334fc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d6e6b1d7c9ad73f6d829c6c40ce20a499e334fc

Author: Marek Olšák 
Date:   Sat Feb  3 16:10:25 2018 +0100

radeonsi: don't use struct si_descriptors for vertex buffer descriptors

VBO descriptor code will change a lot one day.

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_blit.c|  2 +-
 src/gallium/drivers/radeonsi/si_cp_dma.c  |  5 ++-
 src/gallium/drivers/radeonsi/si_debug.c   | 14 ++--
 src/gallium/drivers/radeonsi/si_descriptors.c | 50 +--
 src/gallium/drivers/radeonsi/si_hw_context.c  |  2 +-
 src/gallium/drivers/radeonsi/si_pipe.h|  6 +++-
 6 files changed, 46 insertions(+), 33 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 370ce04a9b..f1c4f6d1e7 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -86,7 +86,7 @@ void si_blitter_end(struct pipe_context *ctx)
/* Restore shader pointers because the VS blit shader changed all
 * non-global VS user SGPRs. */
sctx->shader_pointers_dirty |= SI_DESCS_SHADER_MASK(VERTEX);
-   sctx->vertex_buffer_pointer_dirty = true;
+   sctx->vertex_buffer_pointer_dirty = sctx->vb_descriptors_buffer != NULL;
si_mark_atom_dirty(sctx, >shader_pointers.atom);
 }
 
diff --git a/src/gallium/drivers/radeonsi/si_cp_dma.c 
b/src/gallium/drivers/radeonsi/si_cp_dma.c
index b6659267ac..15bd305a35 100644
--- a/src/gallium/drivers/radeonsi/si_cp_dma.c
+++ b/src/gallium/drivers/radeonsi/si_cp_dma.c
@@ -516,9 +516,8 @@ static void cik_prefetch_VBO_descriptors(struct si_context 
*sctx)
if (!sctx->vertex_elements)
return;
 
-   cik_prefetch_TC_L2_async(sctx, >vertex_buffers.buffer->b.b,
-sctx->vertex_buffers.gpu_address -
-sctx->vertex_buffers.buffer->gpu_address,
+   cik_prefetch_TC_L2_async(sctx, >vb_descriptors_buffer->b.b,
+sctx->vb_descriptors_offset,
 sctx->vertex_elements->desc_list_byte_size);
 }
 
diff --git a/src/gallium/drivers/radeonsi/si_debug.c 
b/src/gallium/drivers/radeonsi/si_debug.c
index 385ce3906d..1f25f4ebbe 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -740,10 +740,20 @@ static void si_dump_descriptors(struct si_context *sctx,
enabled_images = sctx->images[processor].enabled_mask;
}
 
-   if (processor == PIPE_SHADER_VERTEX) {
+   if (processor == PIPE_SHADER_VERTEX &&
+   sctx->vb_descriptors_buffer &&
+   sctx->vb_descriptors_gpu_list &&
+   sctx->vertex_elements) {
assert(info); /* only CS may not have an info struct */
+   struct si_descriptors desc = {};
 
-   si_dump_descriptor_list(sctx->screen, >vertex_buffers, 
name,
+   desc.buffer = sctx->vb_descriptors_buffer;
+   desc.list = sctx->vb_descriptors_gpu_list;
+   desc.gpu_list = sctx->vb_descriptors_gpu_list;
+   desc.element_dw_size = 4;
+   desc.num_active_slots = 
sctx->vertex_elements->desc_list_byte_size / 16;
+
+   si_dump_descriptor_list(sctx->screen, , name,
" - Vertex buffer", 4, info->num_inputs,
si_identity, log);
}
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index becd41d6ef..d1864d0cf8 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -986,7 +986,6 @@ static void si_get_buffer_from_descriptors(struct 
si_buffer_resources *buffers,
 
 static void si_vertex_buffers_begin_new_cs(struct si_context *sctx)
 {
-   struct si_descriptors *desc = >vertex_buffers;
int count = sctx->vertex_elements ? sctx->vertex_elements->count : 0;
int i;
 
@@ -1003,17 +1002,16 @@ static void si_vertex_buffers_begin_new_cs(struct 
si_context *sctx)
  RADEON_USAGE_READ, 
RADEON_PRIO_VERTEX_BUFFER);
}
 
-   if (!desc->buffer)
+   if (!sctx->vb_descriptors_buffer)
return;
radeon_add_to_buffer_list(>b, >b.gfx,
- desc->buffer, RADEON_USAGE_READ,
- RADEON_PRIO_DESCRIPTORS);
+ sctx->vb_descriptors_buffer, 
RADEON_USAGE_READ,
+ RADEON_PRIO_DESCRIPTORS);
 }
 
 bool si_upload_vertex_buffer_descriptors(struct si_context *sctx)
 {
struct si_vertex_elements *velems = sctx->vertex_elements;
-   struct si_descriptors *desc = 

Mesa (master): radeonsi: make SI_SGPR_VERTEX_BUFFERS the last user SGPR input

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 3fa7a59d69b8953843edbef8b52c681cab45dd70
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3fa7a59d69b8953843edbef8b52c681cab45dd70

Author: Marek Olšák 
Date:   Sun Oct  8 19:38:37 2017 +0200

radeonsi: make SI_SGPR_VERTEX_BUFFERS the last user SGPR input

so that it can be removed and replaced with inline VBO descriptors,
and the pointer can be packed in unused bits of VBO descriptors.
This also removes the pointer from merged TES-GS where it's useless.

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_descriptors.c   | 14 --
 src/gallium/drivers/radeonsi/si_shader.c| 16 +++-
 src/gallium/drivers/radeonsi/si_shader.h|  9 +++
 src/gallium/drivers/radeonsi/si_state_shaders.c | 34 -
 4 files changed, 53 insertions(+), 20 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index d1864d0cf8..c497c2ff14 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -2127,9 +2127,19 @@ void si_emit_graphics_shader_pointers(struct si_context 
*sctx,
 
if (sctx->vertex_buffer_pointer_dirty) {
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
-   unsigned sh_offset = sh_base[PIPE_SHADER_VERTEX] +
-SI_SGPR_VERTEX_BUFFERS * 4;
 
+   /* Find the location of the VB descriptor pointer. */
+   /* TODO: In the future, the pointer will be packed in unused
+*   bits of the first 2 VB descriptors. */
+   unsigned sh_dw_offset = SI_VS_NUM_USER_SGPR;
+   if (sctx->b.chip_class >= GFX9) {
+   if (sctx->tes_shader.cso)
+   sh_dw_offset = GFX9_TCS_NUM_USER_SGPR;
+   else if (sctx->gs_shader.cso)
+   sh_dw_offset = GFX9_GS_NUM_USER_SGPR;
+   }
+
+   unsigned sh_offset = sh_base[PIPE_SHADER_VERTEX] + sh_dw_offset 
* 4;
si_emit_shader_pointer_head(cs, sh_offset, 1);
si_emit_shader_pointer_body(sctx->screen, cs,

sctx->vb_descriptors_buffer->gpu_address +
diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 54f90fcac7..1f5af71653 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -4558,8 +4558,6 @@ static void declare_global_desc_pointers(struct 
si_shader_context *ctx,
 static void declare_vs_specific_input_sgprs(struct si_shader_context *ctx,
struct si_function_info *fninfo)
 {
-   ctx->param_vertex_buffers = add_arg(fninfo, ARG_SGPR,
-   ac_array_in_const32_addr_space(ctx->v4i32));
add_arg_assign(fninfo, ARG_SGPR, ctx->i32, >abi.base_vertex);
add_arg_assign(fninfo, ARG_SGPR, ctx->i32, >abi.start_instance);
add_arg_assign(fninfo, ARG_SGPR, ctx->i32, >abi.draw_id);
@@ -4661,6 +4659,8 @@ static void create_function(struct si_shader_context *ctx)
 
declare_per_stage_desc_pointers(ctx, , true);
declare_vs_specific_input_sgprs(ctx, );
+   ctx->param_vertex_buffers = add_arg(, ARG_SGPR,
+   ac_array_in_const32_addr_space(ctx->v4i32));
 
if (shader->key.as_es) {
ctx->param_es2gs_offset = add_arg(, ARG_SGPR, 
ctx->i32);
@@ -4733,6 +4733,10 @@ static void create_function(struct si_shader_context 
*ctx)
ctx->param_tcs_offchip_layout = add_arg(, ARG_SGPR, 
ctx->i32);
ctx->param_tcs_out_lds_offsets = add_arg(, ARG_SGPR, 
ctx->i32);
ctx->param_tcs_out_lds_layout = add_arg(, ARG_SGPR, 
ctx->i32);
+   if (!HAVE_32BIT_POINTERS) /* Align to 2 dwords. */
+   add_arg(, ARG_SGPR, ctx->i32); /* unused */
+   ctx->param_vertex_buffers = add_arg(, ARG_SGPR,
+   ac_array_in_const32_addr_space(ctx->v4i32));
 
/* VGPRs (first TCS, then VS) */
add_arg_assign(, ARG_VGPR, ctx->i32, 
>abi.tcs_patch_id);
@@ -4790,9 +4794,6 @@ static void create_function(struct si_shader_context *ctx)
ctx->param_tcs_offchip_layout = add_arg(, 
ARG_SGPR, ctx->i32);
ctx->param_tes_offchip_addr = add_arg(, 
ARG_SGPR, ctx->i32);
add_arg(, ARG_SGPR, ctx->i32); /* unused */
-   add_arg(, ARG_SGPR, ctx->i32); /* unused */
-   if (!HAVE_32BIT_POINTERS)
-   add_arg(, ARG_SGPR, ctx->i32); /* unused 
*/
ctx->param_vs_state_bits = add_arg(, ARG_SGPR, 
ctx->i32); /* unused */

Mesa (master): radeonsi: set correct num_input_sgprs for VS prolog in merged shaders

[Marek Olšák]

Module: Mesa
Branch: master
Commit: c78640ce319e323ee2fdfac0d5b4dfce797baf0a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c78640ce319e323ee2fdfac0d5b4dfce797baf0a

Author: Marek Olšák 
Date:   Wed Feb  7 01:11:10 2018 +0100

radeonsi: set correct num_input_sgprs for VS prolog in merged shaders

We need to take num_input_sgprs from VS, not the second shader.
No apps suffered from this.

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_shader.c | 48 
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 288f7434bb..54f90fcac7 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -6750,18 +6750,6 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
si_build_tcs_epilog_function(, _epilog_key);
parts[3] = ctx.main_fn;
 
-   /* VS prolog */
-   if (vs_needs_prolog) {
-   union si_shader_part_key vs_prolog_key;
-   si_get_vs_prolog_key(>info,
-
shader->info.num_input_sgprs,
-
>key.part.tcs.ls_prolog,
-shader, _prolog_key);
-   vs_prolog_key.vs_prolog.is_monolithic = true;
-   si_build_vs_prolog_function(, 
_prolog_key);
-   parts[0] = ctx.main_fn;
-   }
-
/* VS as LS main part */
struct si_shader shader_ls = {};
shader_ls.selector = ls;
@@ -6777,6 +6765,18 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
shader->info.uses_instanceid |= 
ls->info.uses_instanceid;
parts[1] = ctx.main_fn;
 
+   /* LS prolog */
+   if (vs_needs_prolog) {
+   union si_shader_part_key vs_prolog_key;
+   si_get_vs_prolog_key(>info,
+
shader_ls.info.num_input_sgprs,
+
>key.part.tcs.ls_prolog,
+shader, _prolog_key);
+   vs_prolog_key.vs_prolog.is_monolithic = true;
+   si_build_vs_prolog_function(, 
_prolog_key);
+   parts[0] = ctx.main_fn;
+   }
+
/* Reset the shader context. */
ctx.shader = shader;
ctx.type = PIPE_SHADER_TESS_CTRL;
@@ -6814,18 +6814,6 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
si_build_gs_prolog_function(, _prolog_key);
gs_prolog = ctx.main_fn;
 
-   /* ES prolog */
-   if (es->vs_needs_prolog) {
-   union si_shader_part_key vs_prolog_key;
-   si_get_vs_prolog_key(>info,
-
shader->info.num_input_sgprs,
-
>key.part.gs.vs_prolog,
-shader, _prolog_key);
-   vs_prolog_key.vs_prolog.is_monolithic = true;
-   si_build_vs_prolog_function(, 
_prolog_key);
-   es_prolog = ctx.main_fn;
-   }
-
/* ES main part */
struct si_shader shader_es = {};
shader_es.selector = es;
@@ -6841,6 +6829,18 @@ int si_compile_tgsi_shader(struct si_screen *sscreen,
shader->info.uses_instanceid |= 
es->info.uses_instanceid;
es_main = ctx.main_fn;
 
+   /* ES prolog */
+   if (es->vs_needs_prolog) {
+   union si_shader_part_key vs_prolog_key;
+   si_get_vs_prolog_key(>info,
+
shader_es.info.num_input_sgprs,
+
>key.part.gs.vs_prolog,
+shader, _prolog_key);
+   vs_prolog_key.vs_prolog.is_monolithic = true;
+   si_build_vs_prolog_function(, 
_prolog_key);
+   es_prolog = ctx.main_fn;
+   }
+
/* Reset the shader context. */

Mesa (master): radeonsi: allow fewer input SGPRs in 2nd shader of merged shaders

[Marek Olšák]

Module: Mesa
Branch: master
Commit: f852b24ce04431ecde639cefd5d86f64975894d5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f852b24ce04431ecde639cefd5d86f64975894d5

Author: Marek Olšák 
Date:   Wed Feb  7 01:09:32 2018 +0100

radeonsi: allow fewer input SGPRs in 2nd shader of merged shaders

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_shader.c | 6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 7af0bdb99c..288f7434bb 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -6600,9 +6600,13 @@ static void si_build_wrapper_function(struct 
si_shader_context *ctx,
 
if (is_sgpr)
lp_add_function_attr(parts[part], param_idx + 
1, LP_FUNC_ATTR_INREG);
+   else if (out_idx < num_out_sgpr) {
+   /* Skip returned SGPRs the current part doesn't
+* declare on the input. */
+   out_idx = num_out_sgpr;
+   }
 
assert(out_idx + param_size <= (is_sgpr ? num_out_sgpr 
: num_out));
-   assert(is_sgpr || out_idx >= num_out_sgpr);
 
if (param_size == 1)
arg = out[out_idx];

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Mesa (master): radeonsi: remove 2 unused user SGPRs from merged TES-GS with 32-bit pointers

[Marek Olšák]

Module: Mesa
Branch: master
Commit: 8799eaed993995e93714cf42c80409b5d53a9537
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8799eaed993995e93714cf42c80409b5d53a9537

Author: Marek Olšák 
Date:   Thu Feb  8 17:26:16 2018 +0100

radeonsi: remove 2 unused user SGPRs from merged TES-GS with 32-bit pointers

The effect of the last 13 commits on user SGPR counts:

Reviewed-by: Nicolai Hähnle 

---

 src/gallium/drivers/radeonsi/si_descriptors.c   |  2 +-
 src/gallium/drivers/radeonsi/si_shader.c| 30 +++--
 src/gallium/drivers/radeonsi/si_shader.h|  9 +++-
 src/gallium/drivers/radeonsi/si_state_shaders.c |  5 +++--
 4 files changed, 35 insertions(+), 11 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index c497c2ff14..4a0cc29091 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -2136,7 +2136,7 @@ void si_emit_graphics_shader_pointers(struct si_context 
*sctx,
if (sctx->tes_shader.cso)
sh_dw_offset = GFX9_TCS_NUM_USER_SGPR;
else if (sctx->gs_shader.cso)
-   sh_dw_offset = GFX9_GS_NUM_USER_SGPR;
+   sh_dw_offset = GFX9_VSGS_NUM_USER_SGPR;
}
 
unsigned sh_offset = sh_base[PIPE_SHADER_VERTEX] + sh_dw_offset 
* 4;
diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 1f5af71653..b69c1bbb24 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -3430,7 +3430,12 @@ static void si_set_es_return_value_for_gs(struct 
si_shader_context *ctx)
  8 + GFX9_SGPR_2ND_SAMPLERS_AND_IMAGES);
 #endif
 
-   unsigned vgpr = 8 + GFX9_GS_NUM_USER_SGPR;
+   unsigned vgpr;
+   if (ctx->type == PIPE_SHADER_VERTEX)
+   vgpr = 8 + GFX9_VSGS_NUM_USER_SGPR;
+   else
+   vgpr = 8 + GFX9_TESGS_NUM_USER_SGPR;
+
for (unsigned i = 0; i < 5; i++) {
unsigned param = ctx->param_gs_vtx01_offset + i;
ret = si_insert_input_ret_float(ctx, ret, param, vgpr++);
@@ -4789,12 +4794,13 @@ static void create_function(struct si_shader_context 
*ctx)
if (ctx->type == PIPE_SHADER_VERTEX) {
declare_vs_specific_input_sgprs(ctx, );
} else {
-   /* TESS_EVAL (and also GEOMETRY):
-* Declare as many input SGPRs as the VS has. */
ctx->param_tcs_offchip_layout = add_arg(, 
ARG_SGPR, ctx->i32);
ctx->param_tes_offchip_addr = add_arg(, 
ARG_SGPR, ctx->i32);
-   add_arg(, ARG_SGPR, ctx->i32); /* unused */
-   ctx->param_vs_state_bits = add_arg(, ARG_SGPR, 
ctx->i32); /* unused */
+   if (!HAVE_32BIT_POINTERS) {
+   /* Declare as many input SGPRs as the VS has. */
+   add_arg(, ARG_SGPR, ctx->i32); /* unused 
*/
+   ctx->param_vs_state_bits = add_arg(, 
ARG_SGPR, ctx->i32); /* unused */
+   }
}
 
if (!HAVE_32BIT_POINTERS) {
@@ -4822,8 +4828,15 @@ static void create_function(struct si_shader_context 
*ctx)
 
if (ctx->type == PIPE_SHADER_VERTEX ||
ctx->type == PIPE_SHADER_TESS_EVAL) {
+   unsigned num_user_sgprs;
+
+   if (ctx->type == PIPE_SHADER_VERTEX)
+   num_user_sgprs = GFX9_VSGS_NUM_USER_SGPR;
+   else
+   num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
+
/* ES return values are inputs to GS. */
-   for (i = 0; i < 8 + GFX9_GS_NUM_USER_SGPR; i++)
+   for (i = 0; i < 8 + num_user_sgprs; i++)
returns[num_returns++] = ctx->i32; /* SGPRs */
for (i = 0; i < 5; i++)
returns[num_returns++] = ctx->f32; /* VGPRs */
@@ -6342,7 +6355,10 @@ static void si_build_gs_prolog_function(struct 
si_shader_context *ctx,
si_init_function_info();
 
if (ctx->screen->info.chip_class >= GFX9) {
-   num_sgprs = 8 + GFX9_GS_NUM_USER_SGPR;
+   if (key->gs_prolog.states.gfx9_prev_is_vs)
+   num_sgprs = 8 + GFX9_VSGS_NUM_USER_SGPR;
+   else
+   num_sgprs = 8 + GFX9_TESGS_NUM_USER_SGPR;
num_vgprs = 5; /* ES inputs are not needed by GS */
} else {
num_sgprs = GFX6_GS_NUM_USER_SGPR + 2;
diff --git a/src/gallium/drivers/radeonsi/si_shader.h 

Mesa (master): build: Move wayland-protocols check into platform

[Daniel Stone]

Module: Mesa
Branch: master
Commit: d33cd875e89b894eb9f848f702ba17a70478d2b8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d33cd875e89b894eb9f848f702ba17a70478d2b8

Author: Daniel Stone 
Date:   Thu Feb 22 09:21:00 2018 +

build: Move wayland-protocols check into platform

In line with wayland-client and wayland-server, move the check for
wayland-protocols into the wayland platform branch.

Signed-off-by: Daniel Stone 
Fixes: bfa22266cd4d ("vulkan/wsi/wayland: Add support for zwp_dmabuf")
Cc: Emil Velikov 
Reported-by: Dieter Nützel 
Tested-by: Dieter Nützel 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105211

---

 configure.ac | 12 +++-
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/configure.ac b/configure.ac
index 8a9172690a..d8826cbb42 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1777,12 +1777,6 @@ if test "x$WAYLAND_SCANNER" = x; then
 AC_PATH_PROG([WAYLAND_SCANNER], [wayland-scanner], [:])
 fi
 
-PKG_CHECK_EXISTS([wayland-protocols >= $WAYLAND_PROTOCOLS_REQUIRED], 
[have_wayland_protocols=yes], [have_wayland_protocols=no])
-if test "x$have_wayland_protocols" = xyes; then
-ac_wayland_protocols_pkgdatadir=`$PKG_CONFIG --variable=pkgdatadir 
wayland-protocols`
-fi
-AC_SUBST(WAYLAND_PROTOCOLS_DATADIR, $ac_wayland_protocols_pkgdatadir)
-
 # Do per platform setups and checks
 platforms=`IFS=', '; echo $with_platforms`
 for plat in $platforms; do
@@ -1791,13 +1785,12 @@ for plat in $platforms; do
 
 PKG_CHECK_MODULES([WAYLAND_CLIENT], [wayland-client >= 
$WAYLAND_REQUIRED])
 PKG_CHECK_MODULES([WAYLAND_SERVER], [wayland-server >= 
$WAYLAND_REQUIRED])
+PKG_CHECK_MODULES([WAYLAND_PROTOCOLS], [wayland-protocols >= 
$WAYLAND_PROTOCOLS_REQUIRED])
+WAYLAND_PROTOCOLS_DATADIR=`$PKG_CONFIG --variable=pkgdatadir 
wayland-protocols`
 
 if test "x$WAYLAND_SCANNER" = "x:"; then
 AC_MSG_ERROR([wayland-scanner is needed to compile the wayland 
platform])
 fi
-if test "x$have_wayland_protocols" = xno; then
-AC_MSG_ERROR([wayland-protocols >= $WAYLAND_PROTOCOLS_REQUIRED 
is needed to compile the wayland platform])
-fi
 DEFINES="$DEFINES -DHAVE_WAYLAND_PLATFORM -DWL_HIDE_DEPRECATED"
 ;;
 
@@ -1832,6 +1825,7 @@ for plat in $platforms; do
 ;;
 esac
 done
+AC_SUBST([WAYLAND_PROTOCOLS_DATADIR])
 
 if test "x$enable_glx" != xno; then
 if ! echo "$platforms" | grep -q 'x11'; then

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Mesa (master): vulkan/wsi/wayland: Move Wayland protocol from BUILT_SOURCES

[Daniel Stone]

Module: Mesa
Branch: master
Commit: d8f19d9aa03b50feaf8583b26ff5561ea2a56101
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8f19d9aa03b50feaf8583b26ff5561ea2a56101

Author: Daniel Stone 
Date:   Fri Feb 23 11:15:11 2018 +

vulkan/wsi/wayland: Move Wayland protocol from BUILT_SOURCES

autotools wants to have the BUILT_SOURCES ready as soon as it enters the
directory, even if they are not used. This meant the build failed if
wayland-protocols was not available on the system, even if it was not
enabled.

As BUILT_SOURCES cannot be used in a conditional (cf. 166852ee957f), do
the same thing as EGL and manually encode the dependencies in the
Makefile.

Signed-off-by: Daniel Stone 
Fixes: bfa22266cd4d ("vulkan/wsi/wayland: Add support for zwp_dmabuf")
Cc: Emil Velikov 
Reported-by: Dieter Nützel 
Tested-by: Dieter Nützel 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105211

---

 src/vulkan/Makefile.am | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/vulkan/Makefile.am b/src/vulkan/Makefile.am
index c7813ce05e..cbffd769fa 100644
--- a/src/vulkan/Makefile.am
+++ b/src/vulkan/Makefile.am
@@ -58,7 +58,6 @@ AM_CPPFLAGS += \
 VULKAN_WSI_SOURCES += $(VULKAN_WSI_X11_FILES)
 endif
 
-BUILT_SOURCES += $(VULKAN_WSI_WAYLAND_GENERATED_FILES)
 CLEANFILES = $(BUILT_SOURCES)
 
 WL_DRM_XML = $(top_srcdir)/src/egl/wayland/wayland-drm/wayland-drm.xml
@@ -82,6 +81,10 @@ wsi/linux-dmabuf-unstable-v1-client-protocol.h : 
$(WL_DMABUF_XML)
$(AM_V_GEN)$(WAYLAND_SCANNER) client-header < $< > $@
 
 if HAVE_PLATFORM_WAYLAND
+wsi/linux-dmabuf-unstable-v1-protocol.lo: 
wsi/linux-dmabuf-unstable-v1-client-protocol.h
+wsi/wayland-drm-protocol.lo: wsi/wayland-drm-client-protocol.h
+wsi/wsi_common_wayland.lo: wsi/linux-dmabuf-unstable-v1-client-protocol.h 
wsi/wayland-drm-client-protocol.h
+
 AM_CPPFLAGS += \
-I$(top_builddir)/src/vulkan/wsi \
$(WAYLAND_CLIENT_CFLAGS) \

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Mesa (master): build: Move wayland-scanner check into platform

[Daniel Stone]

Module: Mesa
Branch: master
Commit: 61d6ff3ba3c0a21239641f4d5fe8d4fa9c864325
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=61d6ff3ba3c0a21239641f4d5fe8d4fa9c864325

Author: Daniel Stone 
Date:   Thu Feb 22 09:22:36 2018 +

build: Move wayland-scanner check into platform

Also only check for wayland-scanner if building for the Wayland
platform.

Signed-off-by: Daniel Stone 
Fixes: bfa22266cd4d ("vulkan/wsi/wayland: Add support for zwp_dmabuf")
Cc: Emil Velikov 
Reported-by: Dieter Nützel 
Tested-by: Dieter Nützel 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105211

---

 configure.ac | 14 +++---
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/configure.ac b/configure.ac
index d8826cbb42..346c813035 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1770,13 +1770,6 @@ if test "x$with_platforms" = xauto; then
 with_platforms=$with_egl_platforms
 fi
 
-PKG_CHECK_MODULES([WAYLAND_SCANNER], [wayland-scanner],
-WAYLAND_SCANNER=`$PKG_CONFIG --variable=wayland_scanner 
wayland-scanner`,
-WAYLAND_SCANNER='')
-if test "x$WAYLAND_SCANNER" = x; then
-AC_PATH_PROG([WAYLAND_SCANNER], [wayland-scanner], [:])
-fi
-
 # Do per platform setups and checks
 platforms=`IFS=', '; echo $with_platforms`
 for plat in $platforms; do
@@ -1788,6 +1781,13 @@ for plat in $platforms; do
 PKG_CHECK_MODULES([WAYLAND_PROTOCOLS], [wayland-protocols >= 
$WAYLAND_PROTOCOLS_REQUIRED])
 WAYLAND_PROTOCOLS_DATADIR=`$PKG_CONFIG --variable=pkgdatadir 
wayland-protocols`
 
+PKG_CHECK_MODULES([WAYLAND_SCANNER], [wayland-scanner],
+  WAYLAND_SCANNER=`$PKG_CONFIG 
--variable=wayland_scanner wayland-scanner`,
+  WAYLAND_SCANNER='')
+if test "x$WAYLAND_SCANNER" = x; then
+AC_PATH_PROG([WAYLAND_SCANNER], [wayland-scanner], [:])
+fi
+
 if test "x$WAYLAND_SCANNER" = "x:"; then
 AC_MSG_ERROR([wayland-scanner is needed to compile the wayland 
platform])
 fi

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