Mesa (master): r600/cayman: fix fragcood loading recip generation.
Module: Mesa Branch: master Commit: bf2af063c3ac1ef7b948ddfb203aea04f857fc0f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf2af063c3ac1ef7b948ddfb203aea04f857fc0f Author: Dave Airlie Date: Thu Mar 1 03:38:32 2018 + r600/cayman: fix fragcood loading recip generation. This fixes some hangs seen where the recip_ieee opcodes would end up split across the wrong slots. Cc: Signed-off-by: Dave Airlie --- src/gallium/drivers/r600/r600_shader.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index 46eeb9021f..4b44f66141 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -3768,7 +3768,7 @@ static int r600_shader_from_tgsi(struct r600_context *rctx, alu.dst.sel = shader->input[ctx.fragcoord_input].gpr; alu.dst.chan = j; alu.dst.write = (j == 3); - alu.last = 1; + alu.last = (j == 3); if ((r = r600_bytecode_add_alu(ctx.bc, &alu))) return r; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Add debugging code to dump the validation list.
Module: Mesa
Branch: master
Commit: b04c5cece7764967e834f4ca0ce5d650df5f8893
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b04c5cece7764967e834f4ca0ce5d650df5f8893
Author: Kenneth Graunke
Date: Tue Nov 28 10:07:43 2017 -0800
i965: Add debugging code to dump the validation list.
When anything goes wrong with this code, dumping the validation list
is a useful way to figure out what's happening.
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 22 ++
1 file changed, 22 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 5385347dba..c16f7c4d74 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -55,6 +55,28 @@
static void
intel_batchbuffer_reset(struct brw_context *brw);
+UNUSED static void
+dump_validation_list(struct intel_batchbuffer *batch)
+{
+ fprintf(stderr, "Validation list (length %d):\n", batch->exec_count);
+
+ for (int i = 0; i < batch->exec_count; i++) {
+ uint64_t flags = batch->validation_list[i].flags;
+ assert(batch->validation_list[i].handle ==
+ batch->exec_bos[i]->gem_handle);
+ fprintf(stderr, "[%2d]: %2d %-14s %p %s%-7s @ 0x%016llu%s
(%"PRIu64"B)\n",
+ i,
+ batch->validation_list[i].handle,
+ batch->exec_bos[i]->name,
+ batch->exec_bos[i],
+ (flags & EXEC_OBJECT_SUPPORTS_48B_ADDRESS) ? "(48b" : "(32b",
+ (flags & EXEC_OBJECT_WRITE) ? " write)" : ")",
+ batch->validation_list[i].offset,
+ (flags & EXEC_OBJECT_PINNED) ? " (pinned)" : "",
+ batch->exec_bos[i]->size);
+ }
+}
+
static bool
uint_key_compare(const void *a, const void *b)
{
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Mesa (master): i965: Allow 48-bit addressing on Gen8+.
Module: Mesa
Branch: master
Commit: cee9f3890351e24cfaa000f32fef10367c45fe64
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cee9f3890351e24cfaa000f32fef10367c45fe64
Author: Kenneth Graunke
Date: Mon Feb 12 07:18:29 2018 -0800
i965: Allow 48-bit addressing on Gen8+.
This allows most GPU objects to use the full 48-bit address space
offered by Gen8+ platforms, rather than being stuck with 32-bit.
This expands the available GPU memory from 4G to 256TB or so.
A few objects - instruction, scratch, and vertex buffers - need to
remain pinned in the low 4GB of the address space for various reasons.
We default everything to 48-bit but disable it in those cases.
Thanks to Jason Ekstrand for blazing this trail in anv first and
finding the nasty undocumented hardware issues. This patch simply
rips off all of his findings.
Reviewed-by: Jordan Justen
Acked-by: Jason Ekstrand
---
src/mesa/drivers/dri/i965/brw_bufmgr.c | 23 +
src/mesa/drivers/dri/i965/brw_misc_state.c | 13 +++--
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 23 ++---
src/mesa/drivers/dri/i965/genX_blorp_exec.c | 9
src/mesa/drivers/dri/i965/genX_state_upload.c| 60
src/mesa/drivers/dri/i965/intel_batchbuffer.c| 15 ++
src/mesa/drivers/dri/i965/intel_batchbuffer.h| 2 +
7 files changed, 127 insertions(+), 18 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index fb180289a0..2e54adb3ed 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -119,6 +119,7 @@ struct brw_bufmgr {
bool has_llc:1;
bool has_mmap_wc:1;
bool bo_reuse:1;
+ bool supports_48b_addresses:1;
};
static int bo_set_tiling_internal(struct brw_bo *bo, uint32_t tiling_mode,
@@ -409,6 +410,8 @@ retry:
bo->reusable = true;
bo->cache_coherent = bufmgr->has_llc;
bo->index = -1;
+ if (bufmgr->supports_48b_addresses)
+ bo->kflags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS;
mtx_unlock(&bufmgr->lock);
@@ -1385,6 +1388,24 @@ gem_param(int fd, int name)
return v;
}
+static bool
+gem_supports_48b_addresses(int fd)
+{
+ struct drm_i915_gem_exec_object2 obj = {
+ .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS,
+ };
+
+ struct drm_i915_gem_execbuffer2 execbuf = {
+ .buffers_ptr = (uintptr_t)&obj,
+ .buffer_count = 1,
+ .rsvd1 = 0xffu,
+ };
+
+ int ret = drmIoctl(fd, DRM_IOCTL_I915_GEM_EXECBUFFER2, &execbuf);
+
+ return ret == -1 && errno == ENOENT;
+}
+
/**
* Initializes the GEM buffer manager, which uses the kernel to allocate, map,
* and manage map buffer objections.
@@ -1418,6 +1439,8 @@ brw_bufmgr_init(struct gen_device_info *devinfo, int fd)
bufmgr->has_llc = devinfo->has_llc;
bufmgr->has_mmap_wc = gem_param(fd, I915_PARAM_MMAP_VERSION) > 0;
+ bufmgr->supports_48b_addresses =
+ devinfo->gen >= 8 && gem_supports_48b_addresses(fd);
init_cache_buckets(bufmgr);
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index c4ef6812bf..29d74876c2 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -634,6 +634,12 @@ brw_upload_state_base_address(struct brw_context *brw)
}
if (devinfo->gen >= 8) {
+ /* STATE_BASE_ADDRESS has issues with 48-bit address spaces. If the
+ * address + size as seen by STATE_BASE_ADDRESS overflows 48 bits,
+ * the GPU appears to treat all accesses to the buffer as being out
+ * of bounds and returns zero. To work around this, we pin all SBAs
+ * to the bottom 4GB.
+ */
uint32_t mocs_wb = devinfo->gen >= 9 ? SKL_MOCS_WB : BDW_MOCS_WB;
int pkt_len = devinfo->gen >= 9 ? 19 : 16;
@@ -644,15 +650,14 @@ brw_upload_state_base_address(struct brw_context *brw)
OUT_BATCH(0);
OUT_BATCH(mocs_wb << 16);
/* Surface state base address: */
- OUT_RELOC64(brw->batch.state.bo, 0, mocs_wb << 4 | 1);
+ OUT_RELOC64(brw->batch.state.bo, RELOC_32BIT, mocs_wb << 4 | 1);
/* Dynamic state base address: */
- OUT_RELOC64(brw->batch.state.bo, 0, mocs_wb << 4 | 1);
+ OUT_RELOC64(brw->batch.state.bo, RELOC_32BIT, mocs_wb << 4 | 1);
/* Indirect object base address: MEDIA_OBJECT data */
OUT_BATCH(mocs_wb << 4 | 1);
OUT_BATCH(0);
/* Instruction base address: shader kernels (incl. SIP) */
- OUT_RELOC64(brw->cache.bo, 0, mocs_wb << 4 | 1);
-
+ OUT_RELOC64(brw->cache.bo, RELOC_32BIT, mocs_wb << 4 | 1);
/* General state buffer size */
OUT_BATCH(0xf001);
/* Dynamic state buffer size */
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 23bf5a266c..af2faea3bf 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_stat
Mesa (master): i965: Shorten the name of the workaround BO.
Module: Mesa Branch: master Commit: 6712611735afa23bf11da6a3db2293ab1a589470 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6712611735afa23bf11da6a3db2293ab1a589470 Author: Kenneth Graunke Date: Mon Feb 26 15:51:04 2018 -0800 i965: Shorten the name of the workaround BO. This makes the name shorter in debug printouts. If "workaround_bo" is good enough for the code, it's probably good enough for debugging. --- src/mesa/drivers/dri/i965/brw_pipe_control.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index e5b3ffe640..2350a6148f 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -572,9 +572,7 @@ brw_init_pipe_control(struct brw_context *brw, * the gen6 workaround because it involves actually writing to * the buffer, and the kernel doesn't let us write to the batch. */ - brw->workaround_bo = brw_bo_alloc(brw->bufmgr, - "pipe_control workaround", - 4096, 4096); + brw->workaround_bo = brw_bo_alloc(brw->bufmgr, "workaround", 4096, 4096); if (brw->workaround_bo == NULL) return -ENOMEM; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel/fs: Set up sampler message headers in the visitor on gen7+
Module: Mesa
Branch: master
Commit: ff4726077d86800d33520581f154a27dac408588
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff4726077d86800d33520581f154a27dac408588
Author: Jason Ekstrand
Date: Wed Feb 28 19:57:44 2018 -0800
intel/fs: Set up sampler message headers in the visitor on gen7+
This gives the scheduler visibility into the headers which should
improve scheduling. More importantly, however, it lets the scheduler
know that the header gets written. As-is, the scheduler thinks that a
texture instruction only reads it's payload and is unaware that it may
write to the first register so it may reorder it with respect to a read
from that register. This is causing issues in a couple of Dota 2 vertex
shaders.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104923
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Francisco Jerez
---
src/intel/compiler/brw_fs.cpp | 40 +
src/intel/compiler/brw_fs_generator.cpp | 21 +++--
2 files changed, 39 insertions(+), 22 deletions(-)
diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp
index 244c6cda03..0d7988dae4 100644
--- a/src/intel/compiler/brw_fs.cpp
+++ b/src/intel/compiler/brw_fs.cpp
@@ -4192,17 +4192,15 @@ lower_sampler_logical_send_gen7(const fs_builder &bld,
fs_inst *inst, opcode op,
op == SHADER_OPCODE_SAMPLEINFO ||
is_high_sampler(devinfo, sampler)) {
/* For general texture offsets (no txf workaround), we need a header to
- * put them in. Note that we're only reserving space for it in the
- * message payload as it will be initialized implicitly by the
- * generator.
+ * put them in.
*
* TG4 needs to place its channel select in the header, for interaction
* with ARB_texture_swizzle. The sampler index is only 4-bits, so for
* larger sampler numbers we need to offset the Sampler State Pointer in
* the header.
*/
+ fs_reg header = retype(sources[0], BRW_REGISTER_TYPE_UD);
header_size = 1;
- sources[0] = fs_reg();
length++;
/* If we're requesting fewer than four channels worth of response,
@@ -4214,6 +4212,40 @@ lower_sampler_logical_send_gen7(const fs_builder &bld,
fs_inst *inst, opcode op,
unsigned mask = ~((1 << (regs_written(inst) / reg_width)) - 1) & 0xf;
inst->offset |= mask << 12;
}
+
+ /* Build the actual header */
+ const fs_builder ubld = bld.exec_all().group(8, 0);
+ const fs_builder ubld1 = ubld.group(1, 0);
+ ubld.MOV(header, retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
+ if (inst->offset) {
+ ubld1.MOV(component(header, 2), brw_imm_ud(inst->offset));
+ } else if (bld.shader->stage != MESA_SHADER_VERTEX &&
+ bld.shader->stage != MESA_SHADER_FRAGMENT) {
+ /* The vertex and fragment stages have g0.2 set to 0, so
+ * header0.2 is 0 when g0 is copied. Other stages may not, so we
+ * must set it to 0 to avoid setting undesirable bits in the
+ * message.
+ */
+ ubld1.MOV(component(header, 2), brw_imm_ud(0));
+ }
+
+ if (is_high_sampler(devinfo, sampler)) {
+ if (sampler.file == BRW_IMMEDIATE_VALUE) {
+assert(sampler.ud >= 16);
+const int sampler_state_size = 16; /* 16 bytes */
+
+ubld1.ADD(component(header, 3),
+ retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD),
+ brw_imm_ud(16 * (sampler.ud / 16) * sampler_state_size));
+ } else {
+fs_reg tmp = ubld1.vgrf(BRW_REGISTER_TYPE_UD);
+ubld1.AND(tmp, sampler, brw_imm_ud(0x0f0));
+ubld1.SHL(tmp, tmp, brw_imm_ud(4));
+ubld1.ADD(component(header, 3),
+ retype(brw_vec1_grf(0, 3), BRW_REGISTER_TYPE_UD),
+ tmp);
+ }
+ }
}
if (shadow_c.file != BAD_FILE) {
diff --git a/src/intel/compiler/brw_fs_generator.cpp
b/src/intel/compiler/brw_fs_generator.cpp
index b59c09f46e..a5a821a13b 100644
--- a/src/intel/compiler/brw_fs_generator.cpp
+++ b/src/intel/compiler/brw_fs_generator.cpp
@@ -1001,19 +1001,13 @@ fs_generator::generate_tex(fs_inst *inst, struct
brw_reg dst, struct brw_reg src
* we need to set it up explicitly and load the offset bitfield.
* Otherwise, we can use an implied move from g0 to the first message reg.
*/
- if (inst->header_size != 0) {
+ if (inst->header_size != 0 && devinfo->gen < 7) {
if (devinfo->gen < 6 && !inst->offset) {
/* Set up an implied move from g0 to the MRF. */
src = retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UW);
} else {
- struct brw_reg header_reg;
-
- if (devinfo->gen >= 7) {
-header_reg = src;
- } else {
-assert(inst->base_mrf != -1);
-header_reg = brw_message_reg(inst->base_mrf);
-
Mesa (master): ac: fix nir_intrinsic_shared_atomic_comp_swap handling
Module: Mesa
Branch: master
Commit: f5305c1b44a81d8e022997e0f2f5bd7556be7dea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5305c1b44a81d8e022997e0f2f5bd7556be7dea
Author: Timothy Arceri
Date: Thu Mar 1 20:17:38 2018 +1100
ac: fix nir_intrinsic_shared_atomic_comp_swap handling
Following on from 49879f377870 this makes sure we use the correct
src index.
Fixes cts test:
KHR-GL46.compute_shader.atomic-case3
Reviewed-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index afe17a8f11..0ffcd75c3a 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3998,7 +3998,7 @@ static LLVMValueRef visit_var_atomic(struct
ac_nir_context *ctx,
if (instr->intrinsic == nir_intrinsic_var_atomic_comp_swap ||
instr->intrinsic == nir_intrinsic_shared_atomic_comp_swap) {
- LLVMValueRef src1 = get_src(ctx, instr->src[1]);
+ LLVMValueRef src1 = get_src(ctx, instr->src[src_idx + 1]);
result = LLVMBuildAtomicCmpXchg(ctx->ac.builder,
ptr, src, src1,
LLVMAtomicOrderingSequentiallyConsistent,
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Mesa (master): st/glsl_to_nir: simplify st_nir_assign_var_locations() and fix for fs outputs
Module: Mesa
Branch: master
Commit: 13cdf4e5906f2ac7ec39d0b06abc6b5671c0693d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=13cdf4e5906f2ac7ec39d0b06abc6b5671c0693d
Author: Timothy Arceri
Date: Thu Mar 1 13:39:20 2018 +1100
st/glsl_to_nir: simplify st_nir_assign_var_locations() and fix for fs outputs
We only need to check for previously processed location on user
defined varyings as they are the only ones that support component
packing. Therefore a single instance of processed_locs can be
shared by regular varyings and patches.
For simplicity we make processed_locs an array in order to handle
dual source bleanding.
Fixes the follow piglit test on radeonsi:
tests/spec/arb_enhanced_layouts/execution/component-layout/fs-output.shader_test
Reviewed-by: Dave Airlie
---
src/mesa/state_tracker/st_glsl_to_nir.cpp | 30 +-
1 file changed, 13 insertions(+), 17 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 765c827d93..0bd9c4e4e3 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -127,8 +127,10 @@ st_nir_assign_var_locations(struct exec_list *var_list,
unsigned *size,
{
unsigned location = 0;
unsigned assigned_locations[VARYING_SLOT_TESS_MAX];
- uint64_t processed_locs = 0;
- uint32_t processed_patch_locs = 0;
+ uint64_t processed_locs[2] = {0};
+
+ const int base = stage == MESA_SHADER_FRAGMENT ?
+ (int) FRAG_RESULT_DATA0 : (int) VARYING_SLOT_VAR0;
nir_foreach_variable(var, var_list) {
@@ -138,28 +140,22 @@ st_nir_assign_var_locations(struct exec_list *var_list,
unsigned *size,
type = glsl_get_array_element(type);
}
+ /* Builtins don't allow component packing so we only need to worry about
+ * user defined varyings sharing the same location.
+ */
bool processed = false;
- if (var->data.patch &&
- var->data.location != VARYING_SLOT_TESS_LEVEL_INNER &&
- var->data.location != VARYING_SLOT_TESS_LEVEL_OUTER &&
- var->data.location != VARYING_SLOT_BOUNDING_BOX0 &&
- var->data.location != VARYING_SLOT_BOUNDING_BOX1) {
- unsigned patch_loc = var->data.location - VARYING_SLOT_PATCH0;
- if (processed_patch_locs & (1 << patch_loc))
+ if (var->data.location >= base) {
+ unsigned glsl_location = var->data.location - base;
+ if (processed_locs[var->data.index] & ((uint64_t)1 << glsl_location))
processed = true;
-
- processed_patch_locs |= (1 << patch_loc);
- } else {
- if (processed_locs & ((uint64_t)1 << var->data.location))
-processed = true;
-
- processed_locs |= ((uint64_t)1 << var->data.location);
+ else
+processed_locs[var->data.index] |= ((uint64_t)1 << glsl_location);
}
/* Because component packing allows varyings to share the same location
* we may have already have processed this location.
*/
- if (processed && var->data.location >= VARYING_SLOT_VAR0) {
+ if (processed) {
var->data.driver_location = assigned_locations[var->data.location];
*size += type_size(type);
continue;
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Mesa (master): intel/blorp: Add a helper for filling out VERTEX_BUFFER_STATE
Module: Mesa
Branch: master
Commit: ca7ab1a6a5041783edfcc4c181e7341d75dc98f7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca7ab1a6a5041783edfcc4c181e7341d75dc98f7
Author: Jason Ekstrand
Date: Sat Nov 11 13:40:03 2017 -0800
intel/blorp: Add a helper for filling out VERTEX_BUFFER_STATE
There are enough #ifs in there that it's kind-of pointless to duplicate
it for each buffer.
Reviewed-by: Samuel Iglesias Gonsálvez
---
src/intel/blorp/blorp_genX_exec.h | 69 +++
1 file changed, 33 insertions(+), 36 deletions(-)
diff --git a/src/intel/blorp/blorp_genX_exec.h
b/src/intel/blorp/blorp_genX_exec.h
index 737720a70c..cea514e0cc 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -263,53 +263,50 @@ blorp_emit_input_varying_data(struct blorp_batch *batch,
}
static void
-blorp_emit_vertex_buffers(struct blorp_batch *batch,
- const struct blorp_params *params)
+blorp_fill_vertex_buffer_state(struct blorp_batch *batch,
+ struct GENX(VERTEX_BUFFER_STATE) *vb,
+ unsigned idx,
+ struct blorp_address addr, uint32_t size,
+ uint32_t stride)
{
- struct GENX(VERTEX_BUFFER_STATE) vb[2];
- memset(vb, 0, sizeof(vb));
+ vb[idx].VertexBufferIndex = idx;
+ vb[idx].BufferStartingAddress = addr;
+ vb[idx].BufferPitch = stride;
- uint32_t size;
- blorp_emit_vertex_data(batch, params, &vb[0].BufferStartingAddress, &size);
- vb[0].VertexBufferIndex = 0;
- vb[0].BufferPitch = 3 * sizeof(float);
#if GEN_GEN >= 6
- vb[0].VertexBufferMOCS = vb[0].BufferStartingAddress.mocs;
-#endif
-#if GEN_GEN >= 7
- vb[0].AddressModifyEnable = true;
-#endif
-#if GEN_GEN >= 8
- vb[0].BufferSize = size;
-#elif GEN_GEN >= 5
- vb[0].BufferAccessType = VERTEXDATA;
- vb[0].EndAddress = vb[0].BufferStartingAddress;
- vb[0].EndAddress.offset += size - 1;
-#elif GEN_GEN == 4
- vb[0].BufferAccessType = VERTEXDATA;
- vb[0].MaxIndex = 2;
+ vb[idx].VertexBufferMOCS = addr.mocs;
#endif
- blorp_emit_input_varying_data(batch, params,
- &vb[1].BufferStartingAddress, &size);
- vb[1].VertexBufferIndex = 1;
- vb[1].BufferPitch = 0;
-#if GEN_GEN >= 6
- vb[1].VertexBufferMOCS = vb[1].BufferStartingAddress.mocs;
-#endif
#if GEN_GEN >= 7
- vb[1].AddressModifyEnable = true;
+ vb[idx].AddressModifyEnable = true;
#endif
+
#if GEN_GEN >= 8
- vb[1].BufferSize = size;
+ vb[idx].BufferSize = size;
#elif GEN_GEN >= 5
- vb[1].BufferAccessType = INSTANCEDATA;
- vb[1].EndAddress = vb[1].BufferStartingAddress;
- vb[1].EndAddress.offset += size - 1;
+ vb[idx].BufferAccessType = stride > 0 ? VERTEXDATA : INSTANCEDATA;
+ vb[idx].EndAddress = vb[idx].BufferStartingAddress;
+ vb[idx].EndAddress.offset += size - 1;
#elif GEN_GEN == 4
- vb[1].BufferAccessType = INSTANCEDATA;
- vb[1].MaxIndex = 0;
+ vb[idx].BufferAccessType = stride > 0 ? VERTEXDATA : INSTANCEDATA;
+ vb[idx].MaxIndex = stride > 0 ? size / stride : 0;
#endif
+}
+
+static void
+blorp_emit_vertex_buffers(struct blorp_batch *batch,
+ const struct blorp_params *params)
+{
+ struct GENX(VERTEX_BUFFER_STATE) vb[2];
+ memset(vb, 0, sizeof(vb));
+
+ struct blorp_address addr;
+ uint32_t size;
+ blorp_emit_vertex_data(batch, params, &addr, &size);
+ blorp_fill_vertex_buffer_state(batch, vb, 0, addr, size, 3 * sizeof(float));
+
+ blorp_emit_input_varying_data(batch, params, &addr, &size);
+ blorp_fill_vertex_buffer_state(batch, vb, 1, addr, size, 0);
const unsigned num_dwords = 1 + GENX(VERTEX_BUFFER_STATE_length) * 2;
uint32_t *dw = blorp_emitn(batch, GENX(3DSTATE_VERTEX_BUFFERS), num_dwords);
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Mesa (master): anv/cmd_buffer: Add support for MCS fast-clears and resolves
Module: Mesa
Branch: master
Commit: 00da139477fb4616ceff58410a3851d5e8701c8a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=00da139477fb4616ceff58410a3851d5e8701c8a
Author: Jason Ekstrand
Date: Fri Feb 23 21:12:35 2018 -0800
anv/cmd_buffer: Add support for MCS fast-clears and resolves
Reviewed-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/genX_cmd_buffer.c | 44 +-
1 file changed, 39 insertions(+), 5 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 47542ea4ac..98e58cadba 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -754,6 +754,29 @@ anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer,
array_layer, 1, resolve_op, true);
}
+static void
+anv_cmd_predicated_mcs_resolve(struct anv_cmd_buffer *cmd_buffer,
+ const struct anv_image *image,
+ VkImageAspectFlagBits aspect,
+ uint32_t array_layer,
+ enum isl_aux_op resolve_op,
+ enum anv_fast_clear_type fast_clear_supported)
+{
+ assert(aspect == VK_IMAGE_ASPECT_COLOR_BIT);
+ assert(resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
+
+#if GEN_GEN >= 8 || GEN_IS_HASWELL
+ anv_cmd_compute_resolve_predicate(cmd_buffer, image,
+ aspect, 0, array_layer,
+ resolve_op, fast_clear_supported);
+
+ anv_image_mcs_op(cmd_buffer, image, aspect,
+array_layer, 1, resolve_op, true);
+#else
+ unreachable("MCS resolves are unsupported on Ivybridge and Bay Trail");
+#endif
+}
+
void
genX(cmd_buffer_mark_image_written)(struct anv_cmd_buffer *cmd_buffer,
const struct anv_image *image,
@@ -1096,9 +1119,15 @@ transition_color_buffer(struct anv_cmd_buffer
*cmd_buffer,
for (uint32_t a = 0; a < level_layer_count; a++) {
uint32_t array_layer = base_layer + a;
- anv_cmd_predicated_ccs_resolve(cmd_buffer, image, aspect,
-level, array_layer, resolve_op,
-final_fast_clear);
+ if (image->samples == 1) {
+anv_cmd_predicated_ccs_resolve(cmd_buffer, image, aspect,
+ level, array_layer, resolve_op,
+ final_fast_clear);
+ } else {
+anv_cmd_predicated_mcs_resolve(cmd_buffer, image, aspect,
+ array_layer, resolve_op,
+ final_fast_clear);
+ }
}
}
@@ -3448,8 +3477,13 @@ cmd_buffer_begin_subpass(struct anv_cmd_buffer
*cmd_buffer,
assert(iview->planes[0].isl.base_level == 0);
assert(iview->planes[0].isl.base_array_layer == 0);
-anv_image_ccs_op(cmd_buffer, image, VK_IMAGE_ASPECT_COLOR_BIT,
- 0, 0, 1, ISL_AUX_OP_FAST_CLEAR, false);
+if (iview->image->samples == 1) {
+ anv_image_ccs_op(cmd_buffer, image, VK_IMAGE_ASPECT_COLOR_BIT,
+0, 0, 1, ISL_AUX_OP_FAST_CLEAR, false);
+} else {
+ anv_image_mcs_op(cmd_buffer, image, VK_IMAGE_ASPECT_COLOR_BIT,
+0, 1, ISL_AUX_OP_FAST_CLEAR, false);
+}
base_clear_layer++;
clear_layer_count--;
___
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Mesa (master): anv/blorp: Pass the clear address to blorp for subpass MSAA resolves
Module: Mesa
Branch: master
Commit: d0f701d2f1fb76b9e004c5551c33f53042df98d2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d0f701d2f1fb76b9e004c5551c33f53042df98d2
Author: Jason Ekstrand
Date: Fri Feb 23 21:11:58 2018 -0800
anv/blorp: Pass the clear address to blorp for subpass MSAA resolves
Reviewed-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_blorp.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index e71d90ac5e..8f29bc8398 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1325,6 +1325,12 @@ anv_cmd_buffer_resolve_subpass(struct anv_cmd_buffer
*cmd_buffer)
VK_IMAGE_ASPECT_COLOR_BIT,
ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
src_aux_usage, &src_surf);
+ if (src_aux_usage == ISL_AUX_USAGE_MCS) {
+src_surf.clear_color_addr = anv_to_blorp_address(
+ anv_image_get_clear_color_addr(cmd_buffer->device,
+ src_iview->image,
+ VK_IMAGE_ASPECT_COLOR_BIT));
+ }
get_blorp_surf_for_anv_image(cmd_buffer->device, dst_iview->image,
VK_IMAGE_ASPECT_COLOR_BIT,
ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
___
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Mesa (master): anv/cmd_buffer: Handle MCS identical to CCS_E in compute_aux_usage
Module: Mesa
Branch: master
Commit: a0a319f16ef376d957ae9b5f3979a4e7745a554a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0a319f16ef376d957ae9b5f3979a4e7745a554a
Author: Jason Ekstrand
Date: Fri Feb 23 20:45:26 2018 -0800
anv/cmd_buffer: Handle MCS identical to CCS_E in compute_aux_usage
This doesn't actually do anything because att_state->fast_clear is
determined based on the return value of anv_layout_to_fast_clear_type
which currently returns NONE for multisampled images.
Reviewed-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/genX_cmd_buffer.c | 14 +-
1 file changed, 5 insertions(+), 9 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index ce546249b3..3d886b06eb 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -235,14 +235,9 @@ color_attachment_compute_aux_usage(struct anv_device *
device,
*/
assert(att_state->aux_usage != ISL_AUX_USAGE_NONE);
- if (att_state->aux_usage == ISL_AUX_USAGE_MCS) {
- att_state->input_aux_usage = ISL_AUX_USAGE_MCS;
- att_state->fast_clear = false;
- return;
- }
-
- if (att_state->aux_usage == ISL_AUX_USAGE_CCS_E) {
- att_state->input_aux_usage = ISL_AUX_USAGE_CCS_E;
+ if (att_state->aux_usage == ISL_AUX_USAGE_CCS_E ||
+ att_state->aux_usage == ISL_AUX_USAGE_MCS) {
+ att_state->input_aux_usage = att_state->aux_usage;
} else {
/* From the Sky Lake PRM, RENDER_SURFACE_STATE::AuxiliarySurfaceMode:
*
@@ -274,7 +269,8 @@ color_attachment_compute_aux_usage(struct anv_device *
device,
}
}
- assert(iview->image->planes[0].aux_surface.isl.usage &
ISL_SURF_USAGE_CCS_BIT);
+ assert(iview->image->planes[0].aux_surface.isl.usage &
+ (ISL_SURF_USAGE_CCS_BIT | ISL_SURF_USAGE_MCS_BIT));
const struct isl_format_layout *view_fmtl =
isl_format_get_layout(iview->planes[0].isl.format);
___
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Mesa (master): anv/cmd_buffer: Add helpers for computing resolve predicates
Module: Mesa
Branch: master
Commit: 1805c483b1cb68c5a5dfc95f4c992f4de052224f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1805c483b1cb68c5a5dfc95f4c992f4de052224f
Author: Jason Ekstrand
Date: Fri Feb 23 21:00:52 2018 -0800
anv/cmd_buffer: Add helpers for computing resolve predicates
We'll want to re-use the complex resolve predicate computations for MCS
resolves so it's nice to have them as helper functions.
Reviewed-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/genX_cmd_buffer.c | 74 --
1 file changed, 64 insertions(+), 10 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index 3d886b06eb..47542ea4ac 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -534,19 +534,21 @@ mi_alu(uint32_t opcode, uint32_t operand1, uint32_t
operand2)
#define CS_GPR(n) (0x2600 + (n) * 8)
+/* This is only really practical on haswell and above because it requires
+ * MI math in order to get it correct.
+ */
+#if GEN_GEN >= 8 || GEN_IS_HASWELL
static void
-anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer *cmd_buffer,
- const struct anv_image *image,
- VkImageAspectFlagBits aspect,
- uint32_t level, uint32_t array_layer,
- enum isl_aux_op resolve_op,
- enum anv_fast_clear_type fast_clear_supported)
+anv_cmd_compute_resolve_predicate(struct anv_cmd_buffer *cmd_buffer,
+ const struct anv_image *image,
+ VkImageAspectFlagBits aspect,
+ uint32_t level, uint32_t array_layer,
+ enum isl_aux_op resolve_op,
+ enum anv_fast_clear_type
fast_clear_supported)
{
- const uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
struct anv_address fast_clear_type_addr =
anv_image_get_fast_clear_type_addr(cmd_buffer->device, image, aspect);
-#if GEN_GEN >= 9
/* Name some registers */
const int image_fc_reg = MI_ALU_REG0;
const int fc_imm_reg = MI_ALU_REG1;
@@ -653,7 +655,38 @@ anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer,
return;
}
-#else /* GEN_GEN <= 8 */
+ /* We use the first half of src0 for the actual predicate. Set the second
+* half of src0 and all of src1 to 0 as the predicate operation will be
+* doing an implicit src0 != src1.
+*/
+ emit_lri(&cmd_buffer->batch, MI_PREDICATE_SRC0 + 4, 0);
+ emit_lri(&cmd_buffer->batch, MI_PREDICATE_SRC1, 0);
+ emit_lri(&cmd_buffer->batch, MI_PREDICATE_SRC1 + 4, 0);
+
+ anv_batch_emit(&cmd_buffer->batch, GENX(MI_PREDICATE), mip) {
+ mip.LoadOperation= LOAD_LOADINV;
+ mip.CombineOperation = COMBINE_SET;
+ mip.CompareOperation = COMPARE_SRCS_EQUAL;
+ }
+}
+#endif /* GEN_GEN >= 8 || GEN_IS_HASWELL */
+
+#if GEN_GEN <= 8
+static void
+anv_cmd_simple_resolve_predicate(struct anv_cmd_buffer *cmd_buffer,
+ const struct anv_image *image,
+ VkImageAspectFlagBits aspect,
+ uint32_t level, uint32_t array_layer,
+ enum isl_aux_op resolve_op,
+ enum anv_fast_clear_type fast_clear_supported)
+{
+ struct anv_address fast_clear_type_addr =
+ anv_image_get_fast_clear_type_addr(cmd_buffer->device, image, aspect);
+
+ /* This only works for partial resolves and only when the clear color is
+* all or nothing. On the upside, this emits less command streamer code
+* and works on Ivybridge and Bay Trail.
+*/
assert(resolve_op == ISL_AUX_OP_PARTIAL_RESOLVE);
assert(fast_clear_supported != ANV_FAST_CLEAR_ANY);
@@ -673,7 +706,6 @@ anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer,
sdi.Address = fast_clear_type_addr;
sdi.ImmediateData= 0;
}
-#endif
/* We use the first half of src0 for the actual predicate. Set the second
* half of src0 and all of src1 to 0 as the predicate operation will be
@@ -688,6 +720,28 @@ anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer
*cmd_buffer,
mip.CombineOperation = COMBINE_SET;
mip.CompareOperation = COMPARE_SRCS_EQUAL;
}
+}
+#endif /* GEN_GEN <= 8 */
+
+static void
+anv_cmd_predicated_ccs_resolve(struct anv_cmd_buffer *cmd_buffer,
+ const struct anv_image *image,
+ VkImageAspectFlagBits aspect,
+ uint32_t level, uint32_t array_layer,
+ enum isl_aux_op resolve_op,
+ enum anv_fast_clear_type fast_clear_supported)
+{
+ const uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
+
Mesa (master): anv/blorp: Allow indirect clear colors on blorp sources on gen7
Module: Mesa Branch: master Commit: f4f95496cbe778bd4e023ec428e13171630f240d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f4f95496cbe778bd4e023ec428e13171630f240d Author: Jason Ekstrand Date: Fri Feb 23 22:05:39 2018 -0800 anv/blorp: Allow indirect clear colors on blorp sources on gen7 Reviewed-by: Samuel Iglesias Gonsálvez --- src/intel/vulkan/genX_blorp_exec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/vulkan/genX_blorp_exec.c b/src/intel/vulkan/genX_blorp_exec.c index f956715228..ac6e736664 100644 --- a/src/intel/vulkan/genX_blorp_exec.c +++ b/src/intel/vulkan/genX_blorp_exec.c @@ -205,8 +205,8 @@ genX(blorp_exec)(struct blorp_batch *batch, * indirect fast-clear colors can cause GPU hangs if we don't stall first. * See genX(cmd_buffer_mi_memcpy) for more details. */ - assert(params->src.clear_color_addr.buffer == NULL); - if (params->dst.clear_color_addr.buffer) + if (params->src.clear_color_addr.buffer || + params->dst.clear_color_addr.buffer) cmd_buffer->state.pending_pipe_bits |= ANV_PIPE_CS_STALL_BIT; #endif ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel/blorp: Add indirect clear color support to mcs_partial_resolve
Module: Mesa
Branch: master
Commit: c34feaea527b66057c7b94302ad1aa932bfb8fd4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c34feaea527b66057c7b94302ad1aa932bfb8fd4
Author: Jason Ekstrand
Date: Sat Nov 11 14:28:17 2017 -0800
intel/blorp: Add indirect clear color support to mcs_partial_resolve
This is a bit complicated because we have to get the indirect clear
color in there somehow. In order to not do any more work in the shader
than needed, we set it up as it's own vertex binding which points
directly at the clear color address specified by the client.
Acked-by: Samuel Iglesias Gonsálvez
Reviewed-by: Topi Pohjolainen
---
src/intel/blorp/blorp_clear.c | 25 +-
src/intel/blorp/blorp_genX_exec.h | 54 ---
src/intel/blorp/blorp_priv.h | 1 +
3 files changed, 70 insertions(+), 10 deletions(-)
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index dde116fa26..832e8ee26f 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -833,9 +833,18 @@ blorp_ccs_resolve(struct blorp_batch *batch,
batch->blorp->exec(batch, ¶ms);
}
+static nir_ssa_def *
+blorp_nir_bit(nir_builder *b, nir_ssa_def *src, unsigned bit)
+{
+ return nir_iand(b, nir_ushr(b, src, nir_imm_int(b, bit)),
+ nir_imm_int(b, 1));
+}
+
struct blorp_mcs_partial_resolve_key
{
enum blorp_shader_type shader_type;
+ bool indirect_clear_color;
+ bool int_format;
uint32_t num_samples;
};
@@ -845,6 +854,8 @@ blorp_params_get_mcs_partial_resolve_kernel(struct
blorp_context *blorp,
{
const struct blorp_mcs_partial_resolve_key blorp_key = {
.shader_type = BLORP_SHADER_TYPE_MCS_PARTIAL_RESOLVE,
+ .indirect_clear_color = params->dst.clear_color_addr.buffer != NULL,
+ .int_format = isl_format_has_int_channel(params->dst.view.format),
.num_samples = params->num_samples,
};
@@ -879,7 +890,18 @@ blorp_params_get_mcs_partial_resolve_kernel(struct
blorp_context *blorp,
discard->src[0] = nir_src_for_ssa(nir_inot(&b, is_clear));
nir_builder_instr_insert(&b, &discard->instr);
- nir_copy_var(&b, frag_color, v_color);
+ nir_ssa_def *clear_color = nir_load_var(&b, v_color);
+ if (blorp_key.indirect_clear_color && blorp->isl_dev->info->gen <= 8) {
+ /* Gen7-8 clear colors are stored as single 0/1 bits */
+ clear_color = nir_vec4(&b, blorp_nir_bit(&b, clear_color, 31),
+ blorp_nir_bit(&b, clear_color, 30),
+ blorp_nir_bit(&b, clear_color, 29),
+ blorp_nir_bit(&b, clear_color, 28));
+
+ if (!blorp_key.int_format)
+ clear_color = nir_i2f32(&b, clear_color);
+ }
+ nir_store_var(&b, frag_color, clear_color, 0xf);
struct brw_wm_prog_key wm_key;
brw_blorp_init_wm_prog_key(&wm_key);
@@ -925,6 +947,7 @@ blorp_mcs_partial_resolve(struct blorp_batch *batch,
params.num_samples = params.dst.surf.samples;
params.num_layers = num_layers;
+ params.dst_clear_color_as_input = surf->clear_color_addr.buffer != NULL;
memcpy(¶ms.wm_inputs.clear_color,
surf->clear_color.f32, sizeof(float) * 4);
diff --git a/src/intel/blorp/blorp_genX_exec.h
b/src/intel/blorp/blorp_genX_exec.h
index cea514e0cc..cc408ca71c 100644
--- a/src/intel/blorp/blorp_genX_exec.h
+++ b/src/intel/blorp/blorp_genX_exec.h
@@ -297,7 +297,7 @@ static void
blorp_emit_vertex_buffers(struct blorp_batch *batch,
const struct blorp_params *params)
{
- struct GENX(VERTEX_BUFFER_STATE) vb[2];
+ struct GENX(VERTEX_BUFFER_STATE) vb[3];
memset(vb, 0, sizeof(vb));
struct blorp_address addr;
@@ -308,12 +308,20 @@ blorp_emit_vertex_buffers(struct blorp_batch *batch,
blorp_emit_input_varying_data(batch, params, &addr, &size);
blorp_fill_vertex_buffer_state(batch, vb, 1, addr, size, 0);
- const unsigned num_dwords = 1 + GENX(VERTEX_BUFFER_STATE_length) * 2;
+ uint32_t num_vbs = 2;
+ if (params->dst_clear_color_as_input) {
+ blorp_fill_vertex_buffer_state(batch, vb, num_vbs++,
+ params->dst.clear_color_addr,
+
batch->blorp->isl_dev->ss.clear_value_size,
+ 0);
+ }
+
+ const unsigned num_dwords = 1 + num_vbs * GENX(VERTEX_BUFFER_STATE_length);
uint32_t *dw = blorp_emitn(batch, GENX(3DSTATE_VERTEX_BUFFERS), num_dwords);
if (!dw)
return;
- for (unsigned i = 0; i < 2; i++) {
+ for (unsigned i = 0; i < num_vbs; i++) {
GENX(VERTEX_BUFFER_STATE_pack)(batch, dw, &vb[i]);
dw += GENX(VERTEX_BUFFER_STATE_length);
}
@@ -440,21 +448,49 @@ blorp_emit_vertex_elements(struct blorp_batch *batch,
};
slot++;
- for (unsigned i = 0; i < num_varyings; ++i) {
+ if (params->dst_clear_color_as_input) {
+ /* If the caller wants the destination indirect cle
Mesa (master): anv: Enable MSAA fast-clears
Module: Mesa
Branch: master
Commit: 89f78cf333a06384728627e9755d1a9b2e3370d7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=89f78cf333a06384728627e9755d1a9b2e3370d7
Author: Jason Ekstrand
Date: Fri Feb 23 21:12:50 2018 -0800
anv: Enable MSAA fast-clears
This speeds up the Sascha Willems multisampling demo by around 25% when
using 8x or 16x MSAA.
Reviewed-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_image.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c
index a2bae7b382..922c46936a 100644
--- a/src/intel/vulkan/anv_image.c
+++ b/src/intel/vulkan/anv_image.c
@@ -952,8 +952,10 @@ anv_layout_to_fast_clear_type(const struct gen_device_info
* const devinfo,
assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
- /* Multisample fast-clear is not yet supported. */
- if (image->samples > 1)
+ /* We don't support MSAA fast-clears on Ivybridge or Bay Trail because they
+* lack the MI ALU which we need to determine the predicates.
+*/
+ if (devinfo->gen == 7 && !devinfo->is_haswell && image->samples > 1)
return ANV_FAST_CLEAR_NONE;
switch (layout) {
@@ -964,12 +966,13 @@ anv_layout_to_fast_clear_type(const struct
gen_device_info * const devinfo,
return ANV_FAST_CLEAR_NONE;
default:
- /* If the image has CCS_E enabled all the time then we can use
+ /* If the image has MCS or CCS_E enabled all the time then we can use
* fast-clear as long as the clear color is the default value of zero
* since this is the default value we program into every surface state
* used for texturing.
*/
- if (image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E)
+ if (image->planes[plane].aux_usage == ISL_AUX_USAGE_MCS ||
+ image->planes[plane].aux_usage == ISL_AUX_USAGE_CCS_E)
return ANV_FAST_CLEAR_DEFAULT_VALUE;
else
return ANV_FAST_CLEAR_NONE;
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Mesa (master): anv/blorp: Add partial clear support to anv_image_mcs_op
Module: Mesa
Branch: master
Commit: d85f05bd6f5bd56b336d5b09337d0832c91c44d2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d85f05bd6f5bd56b336d5b09337d0832c91c44d2
Author: Jason Ekstrand
Date: Sat Nov 11 14:32:21 2017 -0800
anv/blorp: Add partial clear support to anv_image_mcs_op
Reviewed-by: Samuel Iglesias Gonsálvez
---
src/intel/vulkan/anv_blorp.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index efa2ced7f2..e71d90ac5e 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -1606,6 +1606,16 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
ANV_IMAGE_LAYOUT_EXPLICIT_AUX,
ISL_AUX_USAGE_MCS, &surf);
+ if (mcs_op == ISL_AUX_OP_PARTIAL_RESOLVE) {
+ /* If we're doing a partial resolve, then we need the indirect clear
+ * color. The clear operation just stomps the CCS to a particular value
+ * and don't care about format or clear value.
+ */
+ const struct anv_address clear_color_addr =
+ anv_image_get_clear_color_addr(cmd_buffer->device, image, aspect);
+ surf.clear_color_addr = anv_to_blorp_address(clear_color_addr);
+ }
+
/* From the Sky Lake PRM Vol. 7, "Render Target Fast Clear":
*
*"After Render target fast clear, pipe-control with color cache
@@ -1630,8 +1640,11 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
0, base_layer, layer_count,
0, 0, image->extent.width, image->extent.height);
break;
- case ISL_AUX_OP_FULL_RESOLVE:
case ISL_AUX_OP_PARTIAL_RESOLVE:
+ blorp_mcs_partial_resolve(&batch, &surf, surf.surf->format,
+base_layer, layer_count);
+ break;
+ case ISL_AUX_OP_FULL_RESOLVE:
case ISL_AUX_OP_AMBIGUATE:
default:
unreachable("Unsupported MCS operation");
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Mesa (master): i965: Fix RELOC_WRITE typo in brw_store_data_imm64()
Module: Mesa
Branch: master
Commit: 7859701920adc7f25696a05ae4715a4694109e1d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7859701920adc7f25696a05ae4715a4694109e1d
Author: Andriy Khulap
Date: Thu Mar 1 10:44:28 2018 +0200
i965: Fix RELOC_WRITE typo in brw_store_data_imm64()
Fixes: 6c530ad11605
("i965: Reduce passing 2x32b of reloc_domains to 2 bits")
Signed-off-by: Andriy Khulap
Signed-off-by: Vadym Shovkoplias
Reviewed-by: Chris Wilson
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index d0999bb3ca..5385347dba 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -1397,7 +1397,7 @@ brw_store_data_imm64(struct brw_context *brw, struct
brw_bo *bo,
BEGIN_BATCH(5);
OUT_BATCH(MI_STORE_DATA_IMM | (5 - 2));
if (devinfo->gen >= 8)
- OUT_RELOC64(bo, 0, offset);
+ OUT_RELOC64(bo, RELOC_WRITE, offset);
else {
OUT_BATCH(0); /* MBZ */
OUT_RELOC(bo, RELOC_WRITE, offset);
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Mesa (master): gallium/util: use sockets on PIPE_OS_UNIX in u_network
Module: Mesa
Branch: master
Commit: 034bbaa6c0ea0ff1cfc188c6fd49fa068b80be78
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=034bbaa6c0ea0ff1cfc188c6fd49fa068b80be78
Author: Jonathan Gray
Date: Wed Feb 28 21:21:14 2018 +1100
gallium/util: use sockets on PIPE_OS_UNIX in u_network
Instead of listing all the UNIX PIPE_OS platforms just use
PIPE_OS_UNIX. Makes BSD sockets available on PIPE_OS_BSD.
Signed-off-by: Jonathan Gray
Reviewed-by: Brian Paul
---
src/gallium/auxiliary/util/u_network.c | 9 +++--
src/gallium/auxiliary/util/u_network.h | 5 +
2 files changed, 4 insertions(+), 10 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_network.c
b/src/gallium/auxiliary/util/u_network.c
index 203205dc62..e74293bb10 100644
--- a/src/gallium/auxiliary/util/u_network.c
+++ b/src/gallium/auxiliary/util/u_network.c
@@ -9,8 +9,7 @@
# include
# include
# include
-#elif defined(PIPE_OS_LINUX) || defined(PIPE_OS_HAIKU) || \
- defined(PIPE_OS_APPLE) || defined(PIPE_OS_CYGWIN) ||
defined(PIPE_OS_SOLARIS)
+#elif defined(PIPE_OS_UNIX)
# include
# include
# include
@@ -58,8 +57,7 @@ u_socket_close(int s)
if (s < 0)
return;
-#if defined(PIPE_OS_LINUX) || defined(PIPE_OS_HAIKU) \
-|| defined(PIPE_OS_APPLE) || defined(PIPE_OS_SOLARIS)
+#if defined(PIPE_OS_UNIX)
shutdown(s, SHUT_RDWR);
close(s);
#elif defined(PIPE_SUBSYSTEM_WINDOWS_USER)
@@ -181,8 +179,7 @@ u_socket_listen_on_port(uint16_t portnum)
void
u_socket_block(int s, boolean block)
{
-#if defined(PIPE_OS_LINUX) || defined(PIPE_OS_HAIKU) \
-|| defined(PIPE_OS_APPLE) || defined(PIPE_OS_SOLARIS)
+#if defined(PIPE_OS_UNIX)
int old = fcntl(s, F_GETFL, 0);
if (old == -1)
return;
diff --git a/src/gallium/auxiliary/util/u_network.h
b/src/gallium/auxiliary/util/u_network.h
index 61fe9a3c60..2b7ce3f4bd 100644
--- a/src/gallium/auxiliary/util/u_network.h
+++ b/src/gallium/auxiliary/util/u_network.h
@@ -4,10 +4,7 @@
#include "pipe/p_compiler.h"
-#if defined(PIPE_SUBSYSTEM_WINDOWS_USER)
-# define PIPE_HAVE_SOCKETS
-#elif defined(PIPE_OS_LINUX) || defined(PIPE_OS_HAIKU) || \
-defined(PIPE_OS_APPLE) || defined(PIPE_OS_SOLARIS)
+#if defined(PIPE_SUBSYSTEM_WINDOWS_USER) || defined(PIPE_OS_UNIX)
# define PIPE_HAVE_SOCKETS
#endif
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Mesa (master): util: use clock_gettime() on PIPE_OS_BSD
Module: Mesa
Branch: master
Commit: 7bea40e56652a1ded4374d92fb340b454fbac475
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7bea40e56652a1ded4374d92fb340b454fbac475
Author: Jonathan Gray
Date: Wed Feb 28 21:19:19 2018 +1100
util: use clock_gettime() on PIPE_OS_BSD
OpenBSD, FreeBSD, NetBSD and DragonFlyBSD all have clock_gettime()
so use it when PIPE_OS_BSD is defined.
Signed-off-by: Jonathan Gray
Reviewed-by: Brian Paul
---
src/util/os_time.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/util/os_time.c b/src/util/os_time.c
index 72dc7e49c0..ac488b2287 100644
--- a/src/util/os_time.c
+++ b/src/util/os_time.c
@@ -55,7 +55,7 @@
int64_t
os_time_get_nano(void)
{
-#if defined(PIPE_OS_LINUX)
+#if defined(PIPE_OS_LINUX) || defined(PIPE_OS_BSD)
struct timespec tv;
clock_gettime(CLOCK_MONOTONIC, &tv);
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Mesa (master): nir/search: Include 8 and 16-bit support in construct_value
Module: Mesa
Branch: master
Commit: 4420d8866c2892f6776d10de60fd6656376e1dd4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4420d8866c2892f6776d10de60fd6656376e1dd4
Author: Jose Maria Casanova Crespo
Date: Thu Mar 1 18:06:52 2018 +0100
nir/search: Include 8 and 16-bit support in construct_value
Reviewed-by: Jason Ekstrand
---
src/compiler/nir/nir_search.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/src/compiler/nir/nir_search.c b/src/compiler/nir/nir_search.c
index c7c52ae320..28b36b2b86 100644
--- a/src/compiler/nir/nir_search.c
+++ b/src/compiler/nir/nir_search.c
@@ -525,6 +525,9 @@ construct_value(const nir_search_value *value,
case nir_type_float:
load->def.name = ralloc_asprintf(load, "%f", c->data.d);
switch (bitsize->dest_size) {
+ case 16:
+load->value.u16[0] = _mesa_float_to_half(c->data.d);
+break;
case 32:
load->value.f32[0] = c->data.d;
break;
@@ -539,6 +542,12 @@ construct_value(const nir_search_value *value,
case nir_type_int:
load->def.name = ralloc_asprintf(load, "%" PRIi64, c->data.i);
switch (bitsize->dest_size) {
+ case 8:
+load->value.i8[0] = c->data.i;
+break;
+ case 16:
+load->value.i16[0] = c->data.i;
+break;
case 32:
load->value.i32[0] = c->data.i;
break;
@@ -553,6 +562,12 @@ construct_value(const nir_search_value *value,
case nir_type_uint:
load->def.name = ralloc_asprintf(load, "%" PRIu64, c->data.u);
switch (bitsize->dest_size) {
+ case 8:
+load->value.u8[0] = c->data.u;
+break;
+ case 16:
+load->value.u16[0] = c->data.u;
+break;
case 32:
load->value.u32[0] = c->data.u;
break;
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Mesa (master): nir/search: Support 8 and 16-bit constants in match_value
Module: Mesa
Branch: master
Commit: 99ee40fb544ce17489fc2511d44ce1026a5ec70c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=99ee40fb544ce17489fc2511d44ce1026a5ec70c
Author: Jason Ekstrand
Date: Wed Feb 28 13:15:04 2018 -0800
nir/search: Support 8 and 16-bit constants in match_value
Reviewed-by: Jose Maria Casanova Crespo
---
src/compiler/nir/nir_search.c | 20
1 file changed, 20 insertions(+)
diff --git a/src/compiler/nir/nir_search.c b/src/compiler/nir/nir_search.c
index dec56fee74..c7c52ae320 100644
--- a/src/compiler/nir/nir_search.c
+++ b/src/compiler/nir/nir_search.c
@@ -27,6 +27,7 @@
#include
#include "nir_search.h"
+#include "util/half_float.h"
struct match_state {
bool inexact_match;
@@ -194,6 +195,9 @@ match_value(const nir_search_value *value, nir_alu_instr
*instr, unsigned src,
for (unsigned i = 0; i < num_components; ++i) {
double val;
switch (load->def.bit_size) {
+case 16:
+ val = _mesa_half_to_float(load->value.u16[new_swizzle[i]]);
+ break;
case 32:
val = load->value.f32[new_swizzle[i]];
break;
@@ -213,6 +217,22 @@ match_value(const nir_search_value *value, nir_alu_instr
*instr, unsigned src,
case nir_type_uint:
case nir_type_bool32:
switch (load->def.bit_size) {
+ case 8:
+for (unsigned i = 0; i < num_components; ++i) {
+ if (load->value.u8[new_swizzle[i]] !=
+ (uint8_t)const_val->data.u)
+ return false;
+}
+return true;
+
+ case 16:
+for (unsigned i = 0; i < num_components; ++i) {
+ if (load->value.u16[new_swizzle[i]] !=
+ (uint16_t)const_val->data.u)
+ return false;
+}
+return true;
+
case 32:
for (unsigned i = 0; i < num_components; ++i) {
if (load->value.u32[new_swizzle[i]] !=
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Mesa (master): travis: make Meson find the proper llvm-config
Module: Mesa
Branch: master
Commit: b5b912dfeebabafbaff176fe4205eb74607f709b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5b912dfeebabafbaff176fe4205eb74607f709b
Author: Andres Gomez
Date: Wed Feb 28 23:18:59 2018 +0200
travis: make Meson find the proper llvm-config
Travis CI has moved to LLVM 5.0, and meson is detecting automatically
the available version in /usr/local/bin based on the PATH env variable
order preference.
As for 0.44.x, Meson cannot receive the path to the llvm-config binary
as a configuration parameter. See
https://github.com/mesonbuild/meson/issues/2887 and
https://github.com/dcbaker/meson/commit/7c8b6ee3fa42f43c9ac7dcacc61a77eca3f1bcef
We want to use the custom (APT) installed version. Therefore, let's
make Meson find our wanted version sooner than the one at
/usr/local/bin
Once this is corrected, we would still need a patch similar to:
https://lists.freedesktop.org/archives/mesa-dev/2017-December/180217.html
v2: Create the link only to the specificly wanted LLVM version (Gert).
Cc: Eric Engestrom
Cc: Dylan Baker
Cc: Emil Velikov
Cc: Juan A. Suarez Romero
Cc: Gert Wollny
Cc: Jon Turney
Signed-off-by: Andres Gomez
Reviewed-and-Tested-by: Eric Engestrom
Reviewed-by: Dylan Baker
Reviewed-by: Juan A. Suarez
Reviewed-By: Gert Wollny
Reviewed-by: Emil Velikov
---
.travis.yml | 30 ++
1 file changed, 26 insertions(+), 4 deletions(-)
diff --git a/.travis.yml b/.travis.yml
index 0ec08e5bff..823111ca53 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -34,6 +34,8 @@ matrix:
- LABEL="meson Vulkan"
- BUILD=meson
- MESON_OPTIONS="-Ddri-drivers= -Dgallium-drivers="
+- LLVM_VERSION=4.0
+- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
addons:
apt:
sources:
@@ -573,8 +575,28 @@ script:
scons $SCONS_TARGET && eval $SCONS_CHECK_COMMAND;
fi
- - if test "x$BUILD" = xmeson; then
- export CFLAGS="$CFLAGS -isystem`pwd`";
- meson _build $MESON_OPTIONS;
- ninja -C _build;
+ - |
+if test "x$BUILD" = xmeson; then
+
+ # Travis CI has moved to LLVM 5.0, and meson is detecting
+ # automatically the available version in /usr/local/bin based on
+ # the PATH env variable order preference.
+ #
+ # As for 0.44.x, Meson cannot receive the path to the
+ # llvm-config binary as a configuration parameter. See
+ # https://github.com/mesonbuild/meson/issues/2887 and
+ #
https://github.com/dcbaker/meson/commit/7c8b6ee3fa42f43c9ac7dcacc61a77eca3f1bcef
+ #
+ # We want to use the custom (APT) installed version. Therefore,
+ # let's make Meson find our wanted version sooner than the one
+ # at /usr/local/bin
+ #
+ # Once this is corrected, we would still need a patch similar
+ # to:
+ #
https://lists.freedesktop.org/archives/mesa-dev/2017-December/180217.html
+ test -f /usr/bin/$LLVM_CONFIG && ln -s /usr/bin/$LLVM_CONFIG
$HOME/prefix/bin/llvm-config
+
+ export CFLAGS="$CFLAGS -isystem`pwd`"
+ meson _build $MESON_OPTIONS
+ ninja -C _build
fi
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Mesa (master): meson: fix LLVM version detection when <= 3.4
Module: Mesa
Branch: master
Commit: 98f7650add26423d1b3e871c41ae37972b835fe1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=98f7650add26423d1b3e871c41ae37972b835fe1
Author: Andres Gomez
Date: Wed Feb 28 23:15:07 2018 +0200
meson: fix LLVM version detection when <= 3.4
3 digits versions in LLVM only started from 3.4.1 on.
Hence, even if you can perfectly build with an old LLVM (< 3.4.1) in
the system while not needing LLVM at all (auto), when passing through
the LLVM version detection code, meson will fail when accessing
"_llvm_version[2]" due to:
"Index 2 out of bounds of array of size 2."
v2: Properly compare LLVM version and set patch version to 0
if < 3.4.1 (Eric).
v3: Improve the commit log explanation (Eric).
Cc: Dylan Baker
Cc: Eric Engestrom
Signed-off-by: Andres Gomez
Reviewed-by: Dylan Baker
Reviewed-by: Emil Velikov
Reviewed-by: Eric Engestrom
---
meson.build | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/meson.build b/meson.build
index 308f64cf81..e9928a3793 100644
--- a/meson.build
+++ b/meson.build
@@ -1037,7 +1037,14 @@ if with_llvm
# that for our version checks.
# svn suffixes are stripped by meson as of 0.43, and git suffixes are
# strippped as of 0.44, but we support older meson versions.
- _llvm_patch = _llvm_version[2]
+
+ # 3 digits versions in LLVM only started from 3.4.1 on
+ if dep_llvm.version().version_compare('>= 3.4.1')
+_llvm_patch = _llvm_version[2]
+ else
+_llvm_patch = '0'
+ endif
+
if _llvm_patch.endswith('svn')
_llvm_patch = _llvm_patch.split('s')[0]
elif _llvm_patch.contains('git')
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Mesa (master): i965/sbe: fix number of inputs for active components
Module: Mesa
Branch: master
Commit: bc73016703f8f2815e000f1c100532cf6e13cd3c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bc73016703f8f2815e000f1c100532cf6e13cd3c
Author: Iago Toral Quiroga
Date: Thu Mar 1 07:59:42 2018 +0100
i965/sbe: fix number of inputs for active components
In 16631ca30ea6 we fixed gen9 active components to account for padded
inputs in the URB, which we can have with SSO programs. To do that,
instead of going through the bitfield of inputs (which doesn't include
padding information), we compute the number of inputs from the size
of the URB entry.
Unfortunately, there are some special inputs that are not stored in
the URB and that we also need to account for. These special inputs
are identified and handled during calculate_attr_overrides().
Instead of keeping track of the exact number of inputs, we just
program active components for all possible inputs like we do in
anvil.
This fixes a regression in a WebGL program that uses Point Sprite
functionality (specifically, VARYING_SLOT_PNTC).
v2:
- Add 'Fixes' tag (Mark Janes)
- make no_vue_inputs int instead of uint32_t, and add const qualifier
to num_inputs variable (Ian)
v3:
- Do not try to count inputs correctly, just program all input
slots like we do in anvil (Ken)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105224
Fixes: 16631ca30ea6 (i965/sbe: fix active components for SSO programs with over
16 inputs)
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c
b/src/mesa/drivers/dri/i965/genX_state_upload.c
index b38b61a874..e3d4b5e067 100644
--- a/src/mesa/drivers/dri/i965/genX_state_upload.c
+++ b/src/mesa/drivers/dri/i965/genX_state_upload.c
@@ -3464,10 +3464,8 @@ genX(upload_sbe)(struct brw_context *brw)
#if GEN_GEN >= 9
/* prepare the active component dwords */
- const int num_inputs = urb_entry_read_length * 2;
- for (int input_index = 0; input_index < num_inputs; input_index++) {
- sbe.AttributeActiveComponentFormat[input_index] =
ACTIVE_COMPONENT_XYZW;
- }
+ for (int i = 0; i < 32; i++)
+ sbe.AttributeActiveComponentFormat[i] = ACTIVE_COMPONENT_XYZW;
#endif
}
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Mesa (master): radv: keep track of the query pool size
Module: Mesa
Branch: master
Commit: 2fe07933bd5385f731b490ba22ee2086bfccfe63
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2fe07933bd5385f731b490ba22ee2086bfccfe63
Author: Samuel Pitoiset
Date: Wed Feb 28 20:22:29 2018 +0100
radv: keep track of the query pool size
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_private.h | 1 +
src/amd/vulkan/radv_query.c | 9 -
2 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index b76d2eb5cb..752b6a7592 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1606,6 +1606,7 @@ struct radv_query_pool {
struct radeon_winsys_bo *bo;
uint32_t stride;
uint32_t availability_offset;
+ uint64_t size;
char *ptr;
VkQueryType type;
uint32_t pipeline_stats_mask;
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index b1393a2ec7..ff2782bae8 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -748,7 +748,6 @@ VkResult radv_CreateQueryPool(
VkQueryPool*pQueryPool)
{
RADV_FROM_HANDLE(radv_device, device, _device);
- uint64_t size;
struct radv_query_pool *pool = vk_alloc2(&device->alloc, pAllocator,
sizeof(*pool), 8,
VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
@@ -774,12 +773,12 @@ VkResult radv_CreateQueryPool(
pool->type = pCreateInfo->queryType;
pool->pipeline_stats_mask = pCreateInfo->pipelineStatistics;
pool->availability_offset = pool->stride * pCreateInfo->queryCount;
- size = pool->availability_offset;
+ pool->size = pool->availability_offset;
if (pCreateInfo->queryType == VK_QUERY_TYPE_TIMESTAMP ||
pCreateInfo->queryType == VK_QUERY_TYPE_PIPELINE_STATISTICS)
- size += 4 * pCreateInfo->queryCount;
+ pool->size += 4 * pCreateInfo->queryCount;
- pool->bo = device->ws->buffer_create(device->ws, size,
+ pool->bo = device->ws->buffer_create(device->ws, pool->size,
64, RADEON_DOMAIN_GTT,
RADEON_FLAG_NO_INTERPROCESS_SHARING);
if (!pool->bo) {
@@ -794,7 +793,7 @@ VkResult radv_CreateQueryPool(
vk_free2(&device->alloc, pAllocator, pool);
return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
}
- memset(pool->ptr, 0, size);
+ memset(pool->ptr, 0, pool->size);
*pQueryPool = radv_query_pool_to_handle(pool);
return VK_SUCCESS;
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Mesa (master): radv: only emit cache flushes when the pool size is large enough
Module: Mesa
Branch: master
Commit: c27f5419f6f6aa6d51b44a99b6738fba70873604
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c27f5419f6f6aa6d51b44a99b6738fba70873604
Author: Samuel Pitoiset
Date: Wed Feb 28 20:28:53 2018 +0100
radv: only emit cache flushes when the pool size is large enough
This is an optimization which reduces the number of flushes for
small pool buffers.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_meta_buffer.c | 6 --
src/amd/vulkan/radv_private.h | 6 ++
src/amd/vulkan/radv_query.c | 14 +-
3 files changed, 15 insertions(+), 11 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_buffer.c
b/src/amd/vulkan/radv_meta_buffer.c
index e6ad235e93..2e1ba2c7b2 100644
--- a/src/amd/vulkan/radv_meta_buffer.c
+++ b/src/amd/vulkan/radv_meta_buffer.c
@@ -4,12 +4,6 @@
#include "sid.h"
#include "radv_cs.h"
-/*
- * This is the point we switch from using CP to compute shader
- * for certain buffer operations.
- */
-#define RADV_BUFFER_OPS_CS_THRESHOLD 4096
-
static nir_shader *
build_buffer_fill_shader(struct radv_device *dev)
{
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 752b6a7592..0f8ddb2e10 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -95,6 +95,12 @@ typedef uint32_t xcb_window_t;
#define NUM_DEPTH_CLEAR_PIPELINES 3
+/*
+ * This is the point we switch from using CP to compute shader
+ * for certain buffer operations.
+ */
+#define RADV_BUFFER_OPS_CS_THRESHOLD 4096
+
enum radv_mem_heap {
RADV_MEM_HEAP_VRAM,
RADV_MEM_HEAP_VRAM_CPU_ACCESS,
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index ff2782bae8..9fee4d2b49 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -1092,11 +1092,15 @@ void radv_CmdBeginQuery(
radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo, 8);
if (cmd_buffer->pending_reset_query) {
- /* Make sure to flush caches if the query pool has been
-* previously resetted using the compute shader path.
-*/
- si_emit_cache_flush(cmd_buffer);
- cmd_buffer->pending_reset_query = false;
+ if (pool->size >= RADV_BUFFER_OPS_CS_THRESHOLD) {
+ /* Only need to flush caches if the query pool size is
+* large enough to be resetted using the compute shader
+* path. Small pools don't need any cache flushes
+* because we use a CP dma clear.
+*/
+ si_emit_cache_flush(cmd_buffer);
+ cmd_buffer->pending_reset_query = false;
+ }
}
switch (pool->type) {
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Mesa (master): radv: make sure to emit cache flushes before starting a query
Module: Mesa
Branch: master
Commit: c956d0f4069cf39d8d3c57ebed8d905575e9ea34
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c956d0f4069cf39d8d3c57ebed8d905575e9ea34
Author: Samuel Pitoiset
Date: Wed Feb 28 21:47:11 2018 +0100
radv: make sure to emit cache flushes before starting a query
If the query pool has been previously resetted using the compute
shader path.
Fixes: a41e2e9cf5 ("radv: allow to use a compute shader for resetting the query
pool")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105292
Cc: "18.0"
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 7 +++
src/amd/vulkan/radv_private.h| 5 +
src/amd/vulkan/radv_query.c | 28 +---
3 files changed, 33 insertions(+), 7 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 2b41baea3d..cfdc531acd 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -1930,6 +1930,13 @@ VkResult radv_BeginCommandBuffer(
cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;
+ /* Force cache flushes before starting a new query in case the
+* corresponding pool has been resetted from a different command
+* buffer. This is because we have to flush caches between reset and
+* begin if the compute shader path has been used.
+*/
+ cmd_buffer->pending_reset_query = true;
+
return result;
}
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index c72df5a737..b76d2eb5cb 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1003,6 +1003,11 @@ struct radv_cmd_buffer {
uint32_t gfx9_fence_offset;
struct radeon_winsys_bo *gfx9_fence_bo;
uint32_t gfx9_fence_idx;
+
+ /**
+* Whether a query pool has been resetted and we have to flush caches.
+*/
+ bool pending_reset_query;
};
struct radv_image;
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index ace745e4e6..b1393a2ec7 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -1058,17 +1058,23 @@ void radv_CmdResetQueryPool(
{
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
RADV_FROM_HANDLE(radv_query_pool, pool, queryPool);
- struct radv_cmd_state *state = &cmd_buffer->state;
+ uint32_t flush_bits = 0;
- state->flush_bits |= radv_fill_buffer(cmd_buffer, pool->bo,
- firstQuery * pool->stride,
- queryCount * pool->stride, 0);
+ flush_bits |= radv_fill_buffer(cmd_buffer, pool->bo,
+ firstQuery * pool->stride,
+ queryCount * pool->stride, 0);
if (pool->type == VK_QUERY_TYPE_TIMESTAMP ||
pool->type == VK_QUERY_TYPE_PIPELINE_STATISTICS) {
- state->flush_bits |= radv_fill_buffer(cmd_buffer, pool->bo,
- pool->availability_offset
+ firstQuery * 4,
- queryCount * 4, 0);
+ flush_bits |= radv_fill_buffer(cmd_buffer, pool->bo,
+ pool->availability_offset +
firstQuery * 4,
+ queryCount * 4, 0);
+ }
+
+ if (flush_bits) {
+ /* Only need to flush caches for the compute shader path. */
+ cmd_buffer->pending_reset_query = true;
+ cmd_buffer->state.flush_bits |= flush_bits;
}
}
@@ -1086,6 +1092,14 @@ void radv_CmdBeginQuery(
radv_cs_add_buffer(cmd_buffer->device->ws, cs, pool->bo, 8);
+ if (cmd_buffer->pending_reset_query) {
+ /* Make sure to flush caches if the query pool has been
+* previously resetted using the compute shader path.
+*/
+ si_emit_cache_flush(cmd_buffer);
+ cmd_buffer->pending_reset_query = false;
+ }
+
switch (pool->type) {
case VK_QUERY_TYPE_OCCLUSION:
radeon_check_space(cmd_buffer->device->ws, cs, 7);
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