Mesa (master): broadcom/vc5: Fix padding of NPOT miplevels >= 2.

2018-03-27 Thread Eric Anholt 
Module: Mesa
Branch: master
Commit: a691fa4a1be3730f0cfc9566944bd23adb03966d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a691fa4a1be3730f0cfc9566944bd23adb03966d

Author: Eric Anholt 
Date:   Tue Mar 27 16:29:10 2018 -0700

broadcom/vc5: Fix padding of NPOT miplevels >= 2.

The power-of-two padded size that gets minified is based on level 1's
dimensions, not level 0's, which starts to differ at a width of 9.

Fixes all failures on texelFetch fs sampler2D 1x1x1-64x64x1

---

 src/gallium/drivers/vc5/vc5_resource.c | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/vc5/vc5_resource.c 
b/src/gallium/drivers/vc5/vc5_resource.c
index 1f0ddb1a29..321a14b904 100644
--- a/src/gallium/drivers/vc5/vc5_resource.c
+++ b/src/gallium/drivers/vc5/vc5_resource.c
@@ -390,9 +390,14 @@ vc5_setup_slices(struct vc5_resource *rsc)
 uint32_t width = prsc->width0;
 uint32_t height = prsc->height0;
 uint32_t depth = prsc->depth0;
-uint32_t pot_width = util_next_power_of_two(width);
-uint32_t pot_height = util_next_power_of_two(height);
-uint32_t pot_depth = util_next_power_of_two(depth);
+/* Note that power-of-two padding is based on level 1.  These are not
+ * equivalent to just util_next_power_of_two(dimension), because at a
+ * level 0 dimension of 9, the level 1 power-of-two padded value is 4,
+ * not 8.
+ */
+uint32_t pot_width = 2 * util_next_power_of_two(u_minify(width, 1));
+uint32_t pot_height = 2 * util_next_power_of_two(u_minify(height, 1));
+uint32_t pot_depth = 2 * util_next_power_of_two(u_minify(depth, 1));
 uint32_t offset = 0;
 uint32_t utile_w = vc5_utile_width(rsc->cpp);
 uint32_t utile_h = vc5_utile_height(rsc->cpp);

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Mesa (master): radeonsi/nir: set uses_bindless_samplers for samplers

2018-03-27 Thread Timothy Arceri 
Module: Mesa
Branch: master
Commit: f94b6b79be8e86be6908c7e7b93380b082433277
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f94b6b79be8e86be6908c7e7b93380b082433277

Author: Timothy Arceri 
Date:   Tue Feb 20 14:06:27 2018 +1100

radeonsi/nir: set uses_bindless_samplers for samplers

Reviewed-by: Samuel Pitoiset 
Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_shader_nir.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 6444a8b5dd..2245b39fe0 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -56,6 +56,9 @@ static void scan_instruction(struct tgsi_shader_info *info,
if (!tex->texture) {
info->samplers_declared |=
u_bit_consecutive(tex->sampler_index, 1);
+   } else {
+   if (tex->texture->var->data.bindless)
+   info->uses_bindless_samplers = true;
}
 
switch (tex->op) {

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Mesa (master): ac/radeonsi: pass bindless bool to load_sampler_desc()

2018-03-27 Thread Timothy Arceri 
Module: Mesa
Branch: master
Commit: 92fa89a08d1e9905897dfb5cd30b8d572f83e941
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=92fa89a08d1e9905897dfb5cd30b8d572f83e941

Author: Timothy Arceri 
Date:   Tue Feb 20 11:08:11 2018 +1100

ac/radeonsi: pass bindless bool to load_sampler_desc()

We also fix the base_index for bindless by using the driver
location.

Reviewed-by: Samuel Pitoiset 
Reviewed-by: Marek Olšák 

---

 src/amd/common/ac_nir_to_llvm.c  | 11 +--
 src/amd/common/ac_shader_abi.h   |  3 ++-
 src/amd/vulkan/radv_nir_to_llvm.c|  3 ++-
 src/gallium/drivers/radeonsi/si_shader_nir.c |  2 +-
 4 files changed, 14 insertions(+), 5 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 0d85d047cd..7de59efcff 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3030,6 +3030,7 @@ static LLVMValueRef get_sampler_desc(struct 
ac_nir_context *ctx,
unsigned constant_index = 0;
unsigned descriptor_set;
unsigned base_index;
+   bool bindless = false;
 
if (!deref) {
assert(tex_instr && !image);
@@ -3063,14 +3064,20 @@ static LLVMValueRef get_sampler_desc(struct 
ac_nir_context *ctx,
tail = >deref;
}
descriptor_set = deref->var->data.descriptor_set;
-   base_index = deref->var->data.binding;
+
+   if (deref->var->data.bindless) {
+   bindless = deref->var->data.bindless;
+   base_index = deref->var->data.driver_location;
+   } else {
+   base_index = deref->var->data.binding;
+   }
}
 
return ctx->abi->load_sampler_desc(ctx->abi,
  descriptor_set,
  base_index,
  constant_index, index,
- desc_type, image, write);
+ desc_type, image, write, bindless);
 }
 
 static void set_tex_fetch_args(struct ac_llvm_context *ctx,
diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index 0737d697ff..2f222cf8d6 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -157,7 +157,8 @@ struct ac_shader_abi {
  unsigned constant_index,
  LLVMValueRef index,
  enum ac_descriptor_type desc_type,
- bool image, bool write);
+ bool image, bool write,
+ bool bindless);
 
/**
 * Load a Vulkan-specific resource.
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c 
b/src/amd/vulkan/radv_nir_to_llvm.c
index c8d383e021..23b58c37b2 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -1699,7 +1699,8 @@ static LLVMValueRef radv_get_sampler_desc(struct 
ac_shader_abi *abi,
  unsigned constant_index,
  LLVMValueRef index,
  enum ac_descriptor_type desc_type,
- bool image, bool write)
+ bool image, bool write,
+ bool bindless)
 {
struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 2245b39fe0..994fee0b02 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -784,7 +784,7 @@ si_nir_load_sampler_desc(struct ac_shader_abi *abi,
 unsigned descriptor_set, unsigned base_index,
 unsigned constant_index, LLVMValueRef dynamic_index,
 enum ac_descriptor_type desc_type, bool image,
-bool write)
+bool write, bool bindless)
 {
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
LLVMBuilderRef builder = ctx->ac.builder;

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Mesa (master): st/glsl_to_nir: set driver location for bindless images and samplers

2018-03-27 Thread Timothy Arceri 
Module: Mesa
Branch: master
Commit: 5411b98d5249e6ceb79f0b9923dd142fbbce8852
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5411b98d5249e6ceb79f0b9923dd142fbbce8852

Author: Timothy Arceri 
Date:   Tue Feb 20 11:06:27 2018 +1100

st/glsl_to_nir: set driver location for bindless images and samplers

Reviewed-by: Marek Olšák 

---

 src/mesa/state_tracker/st_glsl_to_nir.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index d80b8318c1..2cd1d97bae 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -271,7 +271,8 @@ st_nir_assign_uniform_locations(struct gl_context *ctx,
   uniform->interface_type != NULL)
  continue;
 
-  if (uniform->type->is_sampler() || uniform->type->is_image()) {
+  if (!uniform->data.bindless &&
+  (uniform->type->is_sampler() || uniform->type->is_image())) {
  if (uniform->type->is_sampler())
 loc = shaderidx++;
  else

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Mesa (master): i965: Drop alignment parameter from bo_alloc_internal().

2018-03-27 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: 07ec3a2e0ffdfcc5e3ba9286e1b858a864b25ee1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=07ec3a2e0ffdfcc5e3ba9286e1b858a864b25ee1

Author: Kenneth Graunke 
Date:   Mon Mar 26 15:53:06 2018 -0700

i965: Drop alignment parameter from bo_alloc_internal().

Buffers are always page aligned on 965+ hardware; I believe this extra
parameter is a vestige from the Gen2-3 era.

All callers pass 0, and in fact we assert that the alignment is 0 unless
BO_ALLOC_BUSY is set (for some reason).  We can just drop the parameter
and set the value to 0 explicitly.

Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_bufmgr.c | 13 ++---
 1 file changed, 6 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index f698123db4..295211e89f 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -269,7 +269,7 @@ bo_alloc_internal(struct brw_bufmgr *bufmgr,
   uint64_t size,
   unsigned flags,
   uint32_t tiling_mode,
-  uint32_t stride, uint64_t alignment)
+  uint32_t stride)
 {
struct brw_bo *bo;
unsigned int page_size = getpagesize();
@@ -320,9 +320,8 @@ retry:
  bo = LIST_ENTRY(struct brw_bo, bucket->head.prev, head);
  list_del(>head);
  alloc_from_cache = true;
- bo->align = alignment;
+ bo->align = 0;
   } else {
- assert(alignment == 0);
  /* For non-render-target BOs (where we're probably
   * going to map it first thing in order to fill it
   * with data), check if the last BO in the cache is
@@ -382,7 +381,7 @@ retry:
   bo->gem_handle = create.handle;
 
   bo->bufmgr = bufmgr;
-  bo->align = alignment;
+  bo->align = 0;
 
   bo->tiling_mode = I915_TILING_NONE;
   bo->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
@@ -431,7 +430,7 @@ struct brw_bo *
 brw_bo_alloc(struct brw_bufmgr *bufmgr,
  const char *name, uint64_t size, uint64_t alignment)
 {
-   return bo_alloc_internal(bufmgr, name, size, 0, I915_TILING_NONE, 0, 0);
+   return bo_alloc_internal(bufmgr, name, size, 0, I915_TILING_NONE, 0);
 }
 
 struct brw_bo *
@@ -439,7 +438,7 @@ brw_bo_alloc_tiled(struct brw_bufmgr *bufmgr, const char 
*name,
uint64_t size, uint32_t tiling_mode, uint32_t pitch,
unsigned flags)
 {
-   return bo_alloc_internal(bufmgr, name, size, flags, tiling_mode, pitch, 0);
+   return bo_alloc_internal(bufmgr, name, size, flags, tiling_mode, pitch);
 }
 
 struct brw_bo *
@@ -480,7 +479,7 @@ brw_bo_alloc_tiled_2d(struct brw_bufmgr *bufmgr, const char 
*name,
if (tiling == I915_TILING_NONE)
   stride = 0;
 
-   return bo_alloc_internal(bufmgr, name, size, flags, tiling, stride, 0);
+   return bo_alloc_internal(bufmgr, name, size, flags, tiling, stride);
 }
 
 /**

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Mesa (master): i965: Drop BO_ALLOC_BUSY in intel_miptree_create_for_bo().

2018-03-27 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: b9a54b18f6a6f5dd8007f8490ef57ddd80e4e847
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9a54b18f6a6f5dd8007f8490ef57ddd80e4e847

Author: Kenneth Graunke 
Date:   Mon Mar 26 15:19:15 2018 -0700

i965: Drop BO_ALLOC_BUSY in intel_miptree_create_for_bo().

intel_miptree_create_for_bo does not actually allocate a BO, so
specifying allocation flags accomplishes nothing and is confusing.

Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index c6213b2162..23cb40f322 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -820,7 +820,7 @@ intel_miptree_create_for_bo(struct brw_context *brw,
 devinfo->gen >= 6 ? depth_only_format : format,
 0, 0, width, height, depth, 1, ISL_TILING_Y0_BIT,
 ISL_SURF_USAGE_DEPTH_BIT | ISL_SURF_USAGE_TEXTURE_BIT,
-BO_ALLOC_BUSY, pitch, bo);
+0, pitch, bo);
   if (!mt)
  return NULL;
 
@@ -836,7 +836,7 @@ intel_miptree_create_for_bo(struct brw_context *brw,
 ISL_TILING_W_BIT,
 ISL_SURF_USAGE_STENCIL_BIT |
 ISL_SURF_USAGE_TEXTURE_BIT,
-BO_ALLOC_BUSY, pitch, bo);
+0, pitch, bo);
   if (!mt)
  return NULL;
 

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Mesa (master): i965: Drop PIPE_CONTROL_NO_WRITE from various calls.

2018-03-27 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: 2c01215c1b2c80817cbc6bcdbecd3f19029b287d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c01215c1b2c80817cbc6bcdbecd3f19029b287d

Author: Kenneth Graunke 
Date:   Thu Nov 16 23:43:48 2017 -0800

i965: Drop PIPE_CONTROL_NO_WRITE from various calls.

This is just zero - passing nothing already gives us a post-sync
operation of "nothing".

Reviewed-by: Lionel Landwerlin 

---

 src/mesa/drivers/dri/i965/brw_misc_state.c   | 4 +---
 src/mesa/drivers/dri/i965/brw_pipe_control.c | 2 +-
 src/mesa/drivers/dri/i965/brw_program.c  | 4 +---
 src/mesa/drivers/dri/i965/gen7_l3_state.c| 5 +
 4 files changed, 4 insertions(+), 11 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c 
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 29d74876c2..05517ebf58 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -462,15 +462,13 @@ brw_emit_select_pipeline(struct brw_context *brw, enum 
brw_pipeline pipeline)
   PIPE_CONTROL_RENDER_TARGET_FLUSH |
   PIPE_CONTROL_DEPTH_CACHE_FLUSH |
   dc_flush |
-  PIPE_CONTROL_NO_WRITE |
   PIPE_CONTROL_CS_STALL);
 
   brw_emit_pipe_control_flush(brw,
   PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
   PIPE_CONTROL_CONST_CACHE_INVALIDATE |
   PIPE_CONTROL_STATE_CACHE_INVALIDATE |
-  PIPE_CONTROL_INSTRUCTION_INVALIDATE |
-  PIPE_CONTROL_NO_WRITE);
+  PIPE_CONTROL_INSTRUCTION_INVALIDATE);
 
} else {
   /* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c 
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 2350a6148f..71f79b1847 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -547,7 +547,7 @@ brw_emit_mi_flush(struct brw_context *brw)
  OUT_BATCH(0);
   ADVANCE_BATCH();
} else {
-  int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH;
+  int flags = PIPE_CONTROL_RENDER_TARGET_FLUSH;
   if (devinfo->gen >= 6) {
  flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
   PIPE_CONTROL_CONST_CACHE_INVALIDATE |
diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c
index 4ba46a3c82..23743639dc 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -277,9 +277,7 @@ brw_memory_barrier(struct gl_context *ctx, GLbitfield 
barriers)
 {
struct brw_context *brw = brw_context(ctx);
const struct gen_device_info *devinfo = >screen->devinfo;
-   unsigned bits = (PIPE_CONTROL_DATA_CACHE_FLUSH |
-PIPE_CONTROL_NO_WRITE |
-PIPE_CONTROL_CS_STALL);
+   unsigned bits = PIPE_CONTROL_DATA_CACHE_FLUSH | PIPE_CONTROL_CS_STALL;
assert(devinfo->gen >= 7 && devinfo->gen <= 11);
 
if (barriers & (GL_VERTEX_ATTRIB_ARRAY_BARRIER_BIT |
diff --git a/src/mesa/drivers/dri/i965/gen7_l3_state.c 
b/src/mesa/drivers/dri/i965/gen7_l3_state.c
index 8c8f4169e7..8c6c4c4748 100644
--- a/src/mesa/drivers/dri/i965/gen7_l3_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_l3_state.c
@@ -86,7 +86,6 @@ setup_l3_config(struct brw_context *brw, const struct 
gen_l3_config *cfg)
 */
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DATA_CACHE_FLUSH |
-   PIPE_CONTROL_NO_WRITE |
PIPE_CONTROL_CS_STALL);
 
/* ...followed by a second pipelined PIPE_CONTROL that initiates
@@ -107,15 +106,13 @@ setup_l3_config(struct brw_context *brw, const struct 
gen_l3_config *cfg)
PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_CONST_CACHE_INVALIDATE |
PIPE_CONTROL_INSTRUCTION_INVALIDATE |
-   PIPE_CONTROL_STATE_CACHE_INVALIDATE |
-   PIPE_CONTROL_NO_WRITE);
+   PIPE_CONTROL_STATE_CACHE_INVALIDATE);
 
/* Now send a third stalling flush to make sure that invalidation is
 * complete when the L3 configuration registers are modified.
 */
brw_emit_pipe_control_flush(brw,
PIPE_CONTROL_DATA_CACHE_FLUSH |
-   PIPE_CONTROL_NO_WRITE |
PIPE_CONTROL_CS_STALL);
 
if (devinfo->gen >= 8) {

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Mesa (master): i965: Drop unnecessary bo->align field.

2018-03-27 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: fb18d0dbe42150af57c562cea08eed10be6efaa5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb18d0dbe42150af57c562cea08eed10be6efaa5

Author: Kenneth Graunke 
Date:   Mon Mar 26 16:10:02 2018 -0700

i965: Drop unnecessary bo->align field.

bo->align is always 0; there's no need to waste 8 bytes storing it.
Thanks to C99 initializers zeroing fields, we can completely drop the
only read of the field altogether.

Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_bufmgr.c| 2 --
 src/mesa/drivers/dri/i965/brw_bufmgr.h| 7 ---
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 1 -
 3 files changed, 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 83c0286e0d..8ba915b179 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -320,7 +320,6 @@ retry:
  bo = LIST_ENTRY(struct brw_bo, bucket->head.prev, head);
  list_del(>head);
  alloc_from_cache = true;
- bo->align = 0;
   } else {
  /* For non-render-target BOs (where we're probably
   * going to map it first thing in order to fill it
@@ -381,7 +380,6 @@ retry:
   bo->gem_handle = create.handle;
 
   bo->bufmgr = bufmgr;
-  bo->align = 0;
 
   bo->tiling_mode = I915_TILING_NONE;
   bo->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index 65e76b27d1..68f5e0c2c8 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -56,13 +56,6 @@ struct brw_bo {
 */
uint64_t size;
 
-   /**
-* Alignment requirement for object
-*
-* Used for GTT mapping & pinning the object.
-*/
-   uint64_t align;
-
/** Buffer manager context associated with this buffer object */
struct brw_bufmgr *bufmgr;
 
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index 9147ff8293..ebc02ff389 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -170,7 +170,6 @@ add_exec_bo(struct intel_batchbuffer *batch, struct brw_bo 
*bo)
batch->validation_list[batch->exec_count] =
   (struct drm_i915_gem_exec_object2) {
  .handle = bo->gem_handle,
- .alignment = bo->align,
  .offset = bo->gtt_offset,
  .flags = bo->kflags,
   };

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Mesa (master): i965: Drop unused alignment parameter from brw_bo_alloc().

2018-03-27 Thread Kenneth Graunke 
Module: Mesa
Branch: master
Commit: 037d738a23d626f23107f7190592d575aabe17fd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=037d738a23d626f23107f7190592d575aabe17fd

Author: Kenneth Graunke 
Date:   Mon Mar 26 15:58:05 2018 -0700

i965: Drop unused alignment parameter from brw_bo_alloc().

brw_bo_alloc no longer uses this parameter, so there's no point.

Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
 src/mesa/drivers/dri/i965/brw_bufmgr.c| 2 +-
 src/mesa/drivers/dri/i965/brw_bufmgr.h| 2 +-
 src/mesa/drivers/dri/i965/brw_performance_query.c | 5 ++---
 src/mesa/drivers/dri/i965/brw_pipe_control.c  | 2 +-
 src/mesa/drivers/dri/i965/brw_program.c   | 6 +++---
 src/mesa/drivers/dri/i965/brw_program_cache.c | 4 ++--
 src/mesa/drivers/dri/i965/brw_queryobj.c  | 6 +++---
 src/mesa/drivers/dri/i965/gen6_queryobj.c | 2 +-
 src/mesa/drivers/dri/i965/gen6_sol.c  | 4 ++--
 src/mesa/drivers/dri/i965/intel_batchbuffer.c | 4 ++--
 src/mesa/drivers/dri/i965/intel_buffer_objects.c  | 6 +++---
 src/mesa/drivers/dri/i965/intel_screen.c  | 4 ++--
 src/mesa/drivers/dri/i965/intel_upload.c  | 2 +-
 14 files changed, 25 insertions(+), 26 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index a9c6dc4d50..44064fc0cf 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -827,7 +827,7 @@ blorp_get_client_bo(struct brw_context *brw,
* data which we need to copy into a BO.
*/
   struct brw_bo *bo =
- brw_bo_alloc(brw->bufmgr, "tmp_tex_subimage_src", size, 64);
+ brw_bo_alloc(brw->bufmgr, "tmp_tex_subimage_src", size);
   if (bo == NULL) {
  perf_debug("intel_texsubimage: temp bo creation failed: size = %u\n",
 size);
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c 
b/src/mesa/drivers/dri/i965/brw_bufmgr.c
index 295211e89f..83c0286e0d 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.c
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c
@@ -428,7 +428,7 @@ err:
 
 struct brw_bo *
 brw_bo_alloc(struct brw_bufmgr *bufmgr,
- const char *name, uint64_t size, uint64_t alignment)
+ const char *name, uint64_t size)
 {
return bo_alloc_internal(bufmgr, name, size, 0, I915_TILING_NONE, 0);
 }
diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.h 
b/src/mesa/drivers/dri/i965/brw_bufmgr.h
index f33b6b5a3b..65e76b27d1 100644
--- a/src/mesa/drivers/dri/i965/brw_bufmgr.h
+++ b/src/mesa/drivers/dri/i965/brw_bufmgr.h
@@ -175,7 +175,7 @@ struct brw_bo {
  * using brw_bo_map() to be used by the CPU.
  */
 struct brw_bo *brw_bo_alloc(struct brw_bufmgr *bufmgr, const char *name,
-uint64_t size, uint64_t alignment);
+uint64_t size);
 
 /**
  * Allocate a tiled buffer object.
diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index 4144aa3c9b..ef5401a21b 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1236,8 +1236,7 @@ brw_begin_perf_query(struct gl_context *ctx,
   }
 
   obj->oa.bo =
- brw_bo_alloc(brw->bufmgr, "perf. query OA MI_RPC bo",
-  MI_RPC_BO_SIZE, 64);
+ brw_bo_alloc(brw->bufmgr, "perf. query OA MI_RPC bo", MI_RPC_BO_SIZE);
 #ifdef DEBUG
   /* Pre-filling the BO helps debug whether writes landed. */
   void *map = brw_bo_map(brw, obj->oa.bo, MAP_WRITE);
@@ -1293,7 +1292,7 @@ brw_begin_perf_query(struct gl_context *ctx,
 
   obj->pipeline_stats.bo =
  brw_bo_alloc(brw->bufmgr, "perf. query pipeline stats bo",
-STATS_BO_SIZE, 64);
+  STATS_BO_SIZE);
 
   /* Take starting snapshots. */
   snapshot_statistics_registers(brw, obj, 0);
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c 
b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 71f79b1847..02278be6d6 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -572,7 +572,7 @@ brw_init_pipe_control(struct brw_context *brw,
 * the gen6 workaround because it involves actually writing to
 * the buffer, and the kernel doesn't let us write to the batch.
 */
-   brw->workaround_bo = brw_bo_alloc(brw->bufmgr, "workaround", 4096, 4096);
+   brw->workaround_bo = brw_bo_alloc(brw->bufmgr, "workaround", 4096);
if (brw->workaround_bo == NULL)
   return -ENOMEM;
 
diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c
index 23743639dc..4579a58b82 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -342,7 +342,7 @@ brw_get_scratch_bo(struct brw_context

Mesa (master): intel/fs: Don't emit a des copy for image ops with has_dest == false

2018-03-27 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: 7e38f49a8f6a1ee765613e581844f8e9af414b10
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e38f49a8f6a1ee765613e581844f8e9af414b10

Author: Jason Ekstrand 
Date:   Tue Mar 27 16:27:20 2018 -0700

intel/fs: Don't emit a des copy for image ops with has_dest == false

This was causing us to walk dest_components times over a thing with no
destination.  This happened to work because all of the image intrinsics
without a destination also happened to have dest_components == 0.  We
shouldn't be reading dest_components if has_dest == false.

Reviewed-by: Matt Turner 
Reviewed-by: Ian Romanick 

---

 src/intel/compiler/brw_fs_nir.cpp | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index f5d5399259..197d41062e 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -3848,9 +3848,12 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
nir_intrinsic_instr *instr
  get_image_atomic_op(instr->intrinsic, type));
 
   /* Assign the result. */
-  for (unsigned c = 0; c < info->dest_components; ++c)
- bld.MOV(offset(retype(dest, base_type), bld, c),
- offset(tmp, bld, c));
+  if (nir_intrinsic_infos[instr->intrinsic].has_dest) {
+ for (unsigned c = 0; c < info->dest_components; ++c) {
+bld.MOV(offset(retype(dest, base_type), bld, c),
+offset(tmp, bld, c));
+ }
+  }
   break;
}
 

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Mesa (master): nir/intrinsics: Don't report negative dest_components

2018-03-27 Thread Jason Ekstrand 
Module: Mesa
Branch: master
Commit: 5f21a7afe072f8a6e558ccc47407a0a94e0d1313
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f21a7afe072f8a6e558ccc47407a0a94e0d1313

Author: Jason Ekstrand 
Date:   Tue Mar 27 16:12:16 2018 -0700

nir/intrinsics: Don't report negative dest_components

I have no idea why but having dest_components == -1 was causing a memory
leak somewhere.  Without this, you can't get through a full shader-db
run without running out of memory.

Reviewed-by: Rob Clark 

---

 src/compiler/nir/nir_intrinsics_c.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir_intrinsics_c.py 
b/src/compiler/nir/nir_intrinsics_c.py
index 339214ac53..4410bc6346 100644
--- a/src/compiler/nir/nir_intrinsics_c.py
+++ b/src/compiler/nir/nir_intrinsics_c.py
@@ -35,7 +35,7 @@ const nir_intrinsic_info 
nir_intrinsic_infos[nir_num_intrinsics] = {
},
 % endif
.has_dest = ${"true" if opcode.has_dest else "false"},
-   .dest_components = ${opcode.dest_components},
+   .dest_components = ${max(opcode.dest_components, 0)},
.num_variables = ${opcode.num_variables},
.num_indices = ${opcode.num_indices},
 % if opcode.indices:

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Mesa (master): nvc0/ir: fix INTERP_* with indirect inputs

2018-03-27 Thread Ilia Mirkin 
Module: Mesa
Branch: master
Commit: 776e6af879318050cdf8245cd409ada7b843e358
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=776e6af879318050cdf8245cd409ada7b843e358

Author: Ilia Mirkin 
Date:   Sat Mar 24 15:15:45 2018 -0400

nvc0/ir: fix INTERP_* with indirect inputs

There were two problems, both of which are fixed now:
 - The indirect address was not being shifted by 4
 - The indirect address was being placed as an argument in the offset case

This fixes some of the new interpolateAt* piglits which now test for
these situations.

Signed-off-by: Ilia Mirkin 
Reviewed-by: Karol Herbst 

---

 src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 7 ---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp 
b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
index 09b5228127..3c5bad05fe 100644
--- a/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
+++ b/src/gallium/drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp
@@ -3083,10 +3083,11 @@ Converter::handleINTERP(Value *dst[4])
  assert(sym[c]);
  op = insn->op;
  mode = insn->ipa;
+ ptr = insn->getIndirect(0, 0);
   }
} else {
   if (src.isIndirect(0))
- ptr = fetchSrc(src.getIndirect(0), 0, NULL);
+ ptr = shiftAddress(fetchSrc(src.getIndirect(0), 0, NULL));
 
   // We can assume that the fixed index will point to an input of the same
   // interpolation type in case of an indirect.
@@ -3144,10 +3145,10 @@ Converter::handleINTERP(Value *dst[4])
   insn = mkOp1(op, TYPE_F32, dst[c], sym[c] ? sym[c] : srcToSym(src, c));
   if (op == OP_PINTERP)
  insn->setSrc(1, w);
-  if (ptr)
- insn->setIndirect(0, 0, ptr);
   if (offset)
  insn->setSrc(op == OP_PINTERP ? 2 : 1, offset);
+  if (ptr)
+ insn->setIndirect(0, 0, ptr);
 
   insn->setInterpolate(mode);
}

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Mesa (master): radeonsi/nir: fix scanning of multi-slot output varyings

2018-03-27 Thread Timothy Arceri 
Module: Mesa
Branch: master
Commit: 47eee04556c75075145fbdd0ec50844dcf080d17
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=47eee04556c75075145fbdd0ec50844dcf080d17

Author: Timothy Arceri 
Date:   Wed Feb 21 16:53:54 2018 +1100

radeonsi/nir: fix scanning of multi-slot output varyings

This fixes tcs/tes varying arrays where we dont lower indirects and
therefore don't split arrays. Here we also fix useagemask for dual
slot doubles.

Fixes a number of arb_tessellation_shader piglit tests.

Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_shader_nir.c | 236 ++-
 1 file changed, 127 insertions(+), 109 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 8b5cc13f31..82b2440d0b 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -426,32 +426,48 @@ void si_nir_scan_shader(const struct nir_shader *nir,
nir_foreach_variable(variable, >outputs) {
unsigned semantic_name, semantic_index;
 
-   if (nir->info.stage == MESA_SHADER_FRAGMENT) {
-   
tgsi_get_gl_frag_result_semantic(variable->data.location,
-   _name, _index);
+   i = variable->data.driver_location;
 
-   /* Adjust for dual source blending */
-   if (variable->data.index > 0) {
-   semantic_index++;
-   }
-   } else {
-   tgsi_get_gl_varying_semantic(variable->data.location, 
true,
-_name, 
_index);
+   const struct glsl_type *type = variable->type;
+   if (nir_is_per_vertex_io(variable, nir->info.stage)) {
+   assert(glsl_type_is_array(type));
+   type = glsl_get_array_element(type);
}
 
-   i = variable->data.driver_location;
+   unsigned attrib_count = glsl_count_attribute_slots(type, false);
+   for (unsigned k = 0; k < attrib_count; k++, i++) {
 
-   unsigned num_components = 4;
-   unsigned vector_elements = 
glsl_get_vector_elements(glsl_without_array(variable->type));
-   if (vector_elements)
-   num_components = vector_elements;
+   if (nir->info.stage == MESA_SHADER_FRAGMENT) {
+   
tgsi_get_gl_frag_result_semantic(variable->data.location + k,
+   _name, _index);
 
-   if (glsl_type_is_64bit(glsl_without_array(variable->type)))
-   num_components = MIN2(num_components * 2, 4);
+   /* Adjust for dual source blending */
+   if (variable->data.index > 0) {
+   semantic_index++;
+   }
+   } else {
+   
tgsi_get_gl_varying_semantic(variable->data.location + k, true,
+_name, 
_index);
+   }
+
+   unsigned num_components = 4;
+   unsigned vector_elements = 
glsl_get_vector_elements(glsl_without_array(variable->type));
+   if (vector_elements)
+   num_components = vector_elements;
+
+   unsigned component = variable->data.location_frac;
+   if 
(glsl_type_is_64bit(glsl_without_array(variable->type))) {
+   if 
(glsl_type_is_dual_slot(glsl_without_array(variable->type)) && k % 2) {
+   num_components = (num_components * 2) - 
4;
+   component = 0;
+   } else {
+   num_components = MIN2(num_components * 
2, 4);
+   }
+   }
 
-   ubyte usagemask = 0;
-   for (unsigned j = 0; j < num_components; j++) {
-   switch (j + variable->data.location_frac) {
+   ubyte usagemask = 0;
+   for (unsigned j = component; j < num_components + 
component; j++) {
+   switch (j) {
case 0:
usagemask |= TGSI_WRITEMASK_X;
break;
@@ -466,110 +482,112 @@ void si_nir_scan_shader(const struct nir_shader *nir,
break;
default:
unreachable("error calculating 
component index");
+

Mesa (master): st/glsl_to_nir: fix driver location for dual-slot packed doubles

2018-03-27 Thread Timothy Arceri 
Module: Mesa
Branch: master
Commit: fc51fdbcdec60f96b9bf593d74beb42e465cc277
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc51fdbcdec60f96b9bf593d74beb42e465cc277

Author: Timothy Arceri 
Date:   Wed Mar 21 11:27:19 2018 +1100

st/glsl_to_nir: fix driver location for dual-slot packed doubles

Reviewed-by: Marek Olšák 

---

 src/mesa/state_tracker/st_glsl_to_nir.cpp | 22 --
 1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 9bb99f3061..acc8942bfe 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -141,16 +141,23 @@ st_nir_assign_var_locations(struct exec_list *var_list, 
unsigned *size,
  type = glsl_get_array_element(type);
   }
 
+  unsigned var_size = type_size(type);
+
   /* Builtins don't allow component packing so we only need to worry about
* user defined varyings sharing the same location.
*/
   bool processed = false;
   if (var->data.location >= base) {
  unsigned glsl_location = var->data.location - base;
- if (processed_locs[var->data.index] & ((uint64_t)1 << glsl_location))
-processed = true;
- else
-processed_locs[var->data.index] |= ((uint64_t)1 << glsl_location);
+
+ for (unsigned i = 0; i < var_size; i++) {
+if (processed_locs[var->data.index] &
+((uint64_t)1 << (glsl_location + i)))
+   processed = true;
+else
+   processed_locs[var->data.index] |=
+  ((uint64_t)1 << (glsl_location + i));
+ }
   }
 
   /* Because component packing allows varyings to share the same location
@@ -162,9 +169,12 @@ st_nir_assign_var_locations(struct exec_list *var_list, 
unsigned *size,
  continue;
   }
 
-  assigned_locations[var->data.location] = location;
+  for (unsigned i = 0; i < var_size; i++) {
+ assigned_locations[var->data.location + i] = location + i;
+  }
+
   var->data.driver_location = location;
-  location += type_size(type);
+  location += var_size;
}
 
*size += location;

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Mesa (master): st/glsl_to_nir: correctly handle arrays packed across multiple vars

2018-03-27 Thread Timothy Arceri 
Module: Mesa
Branch: master
Commit: 48f6014903454dcb0e8e05afb41cabf2dbac0585
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=48f6014903454dcb0e8e05afb41cabf2dbac0585

Author: Timothy Arceri 
Date:   Fri Mar 23 12:17:07 2018 +1100

st/glsl_to_nir: correctly handle arrays packed across multiple vars

Fixes piglit test:
tests/spec/arb_enhanced_layouts/execution/component-layout/vs-fs-array-interleave-range.shader_test

Reviewed-by: Marek Olšák 

---

 src/mesa/state_tracker/st_glsl_to_nir.cpp | 24 +++-
 1 file changed, 23 insertions(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index acc8942bfe..d80b8318c1 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -133,6 +133,7 @@ st_nir_assign_var_locations(struct exec_list *var_list, 
unsigned *size,
const int base = stage == MESA_SHADER_FRAGMENT ?
   (int) FRAG_RESULT_DATA0 : (int) VARYING_SLOT_VAR0;
 
+   int UNUSED last_loc = 0;
nir_foreach_variable(var, var_list) {
 
   const struct glsl_type *type = var->type;
@@ -164,8 +165,29 @@ st_nir_assign_var_locations(struct exec_list *var_list, 
unsigned *size,
* we may have already have processed this location.
*/
   if (processed) {
- var->data.driver_location = assigned_locations[var->data.location];
+ unsigned driver_location = assigned_locations[var->data.location];
+ var->data.driver_location = driver_location;
  *size += type_size(type);
+
+ /* An array may be packed such that is crosses multiple other arrays
+  * or variables, we need to make sure we have allocated the elements
+  * consecutively if the previously proccessed var was shorter than
+  * the current array we are processing.
+  *
+  * NOTE: The code below assumes the var list is ordered in ascending
+  * location order.
+  */
+ assert(last_loc <= var->data.location);
+ last_loc = var->data.location;
+ unsigned last_slot_location = driver_location + var_size;
+ if (last_slot_location > location) {
+unsigned num_unallocated_slots = last_slot_location - location;
+unsigned first_unallocated_slot = var_size - num_unallocated_slots;
+for (unsigned i = first_unallocated_slot; i < 
num_unallocated_slots; i++) {
+   assigned_locations[var->data.location + i] = location;
+   location++;
+}
+ }
  continue;
   }
 

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Mesa (master): nir: fix crash in loop unroll corner case

2018-03-27 Thread Timothy Arceri 
Module: Mesa
Branch: master
Commit: 629ee690addad9b3dc8f68cfff5ae09858f31caf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=629ee690addad9b3dc8f68cfff5ae09858f31caf

Author: Timothy Arceri 
Date:   Mon Mar 26 11:41:51 2018 +1100

nir: fix crash in loop unroll corner case

When an if nesting inside anouther if is optimised away we can
end up with a loop terminator and following block that looks like
this:

if ssa_596 {
block block_5:
/* preds: block_4 */
vec1 32 ssa_601 = load_const (0x /* -nan */)
break
/* succs: block_8 */
} else {
block block_6:
/* preds: block_4 */
/* succs: block_7 */
}
block block_7:
/* preds: block_6 */
vec1 32 ssa_602 = phi block_6: ssa_552
vec1 32 ssa_603 = phi block_6: ssa_553
vec1 32 ssa_604 = iadd ssa_551, ssa_66

The problem is the phis. Loop unrolling expects the last block in
the loop to be empty once we splice the instructions in the last
block into the continue branch. The problem is we cant move phis
so here we lower the phis to regs when preparing the loop for
unrolling. As it could be possible to have multiple additional
blocks/ifs following the terminator we just convert all phis at
the top level of the loop body for simplicity.

We also add some comments to loop_prepare_for_unroll() while we
are here.

Fixes: 51daccb289eb "nir: add a loop unrolling pass"

Reviewed-by: Jason Ekstrand 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105670

---

 src/compiler/nir/nir_opt_loop_unroll.c | 17 -
 1 file changed, 12 insertions(+), 5 deletions(-)

diff --git a/src/compiler/nir/nir_opt_loop_unroll.c 
b/src/compiler/nir/nir_opt_loop_unroll.c
index 79d04f978b..ff27c06cc0 100644
--- a/src/compiler/nir/nir_opt_loop_unroll.c
+++ b/src/compiler/nir/nir_opt_loop_unroll.c
@@ -37,10 +37,10 @@
 #define LOOP_UNROLL_LIMIT 26
 
 /* Prepare this loop for unrolling by first converting to lcssa and then
- * converting the phis from the loops first block and the block that follows
- * the loop into regs.  Partially converting out of SSA allows us to unroll
- * the loop without having to keep track of and update phis along the way
- * which gets tricky and doesn't add much value over conveting to regs.
+ * converting the phis from the top level of the loop body to regs.
+ * Partially converting out of SSA allows us to unroll the loop without having
+ * to keep track of and update phis along the way which gets tricky and
+ * doesn't add much value over converting to regs.
  *
  * The loop may have a continue instruction at the end of the loop which does
  * nothing.  Once we're out of SSA, we can safely delete it so we don't have
@@ -51,13 +51,20 @@ loop_prepare_for_unroll(nir_loop *loop)
 {
nir_convert_loop_to_lcssa(loop);
 
-   nir_lower_phis_to_regs_block(nir_loop_first_block(loop));
+   /* Lower phis at the top level of the loop body */
+   foreach_list_typed_safe(nir_cf_node, node, node, >body) {
+  if (nir_cf_node_block == node->type) {
+ nir_lower_phis_to_regs_block(nir_cf_node_as_block(node));
+  }
+   }
 
+   /* Lower phis after the loop */
nir_block *block_after_loop =
   nir_cf_node_as_block(nir_cf_node_next(>cf_node));
 
nir_lower_phis_to_regs_block(block_after_loop);
 
+   /* Remove continue if its the last instruction in the loop */
nir_instr *last_instr = nir_block_last_instr(nir_loop_last_block(loop));
if (last_instr && last_instr->type == nir_instr_type_jump) {
   assert(nir_instr_as_jump(last_instr)->type == nir_jump_continue);

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Mesa (master): ac/nir_to_llvm: fix component packing for double outputs

2018-03-27 Thread Timothy Arceri 
Module: Mesa
Branch: master
Commit: 51f175028dcc69e055d7e612024f7bfe79d7ed5d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=51f175028dcc69e055d7e612024f7bfe79d7ed5d

Author: Timothy Arceri 
Date:   Wed Mar 21 12:23:08 2018 +1100

ac/nir_to_llvm: fix component packing for double outputs

We need to wait until after the writemask is widened before we
adjust it for component packing.

Together with the previous patch this fixes a number of
arb_enhanced_layouts component layout piglit tests.

Reviewed-by: Marek Olšák 

---

 src/amd/common/ac_nir_to_llvm.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index b7d29ef0b5..0d85d047cd 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1793,7 +1793,7 @@ visit_store_var(struct ac_nir_context *ctx,
int idx = instr->variables[0]->var->data.driver_location;
unsigned comp = instr->variables[0]->var->data.location_frac;
LLVMValueRef src = ac_to_float(>ac, get_src(ctx, instr->src[0]));
-   int writemask = instr->const_index[0] << comp;
+   int writemask = instr->const_index[0];
LLVMValueRef indir_index;
unsigned const_index;
get_deref_offset(ctx, instr->variables[0], false,
@@ -1808,6 +1808,8 @@ visit_store_var(struct ac_nir_context *ctx,
writemask = widen_mask(writemask, 2);
}
 
+   writemask = writemask << comp;
+
switch (instr->variables[0]->var->data.mode) {
case nir_var_shader_out:
 

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Mesa (master): radeonsi/nir: fix input processing for packed varyings

2018-03-27 Thread Timothy Arceri 
Module: Mesa
Branch: master
Commit: b260efbd5eed4fd89e7928cfc2103f058a1e86d2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b260efbd5eed4fd89e7928cfc2103f058a1e86d2

Author: Timothy Arceri 
Date:   Fri Mar 23 12:10:42 2018 +1100

radeonsi/nir: fix input processing for packed varyings

The location was only being incremented the first time we processed a
location. This meant we would incorrectly skip some elements of
an array if the first element was packed and proccessed previously
but other elements were not.

Reviewed-by: Marek Olšák 

---

 src/gallium/drivers/radeonsi/si_shader_nir.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 82b2440d0b..6444a8b5dd 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -852,7 +852,7 @@ bool si_nir_build_llvm(struct si_shader_context *ctx, 
struct nir_shader *nir)
/* Packed components share the same location so 
skip
 * them if we have already processed the 
location.
 */
-   if (processed_inputs & ((uint64_t)1 << loc)) {
+   if (processed_inputs & ((uint64_t)1 << (loc + 
i))) {
input_idx += 4;
continue;
}
@@ -870,8 +870,7 @@ bool si_nir_build_llvm(struct si_shader_context *ctx, 
struct nir_shader *nir)
bitcast_inputs(ctx, data, input_idx);
}
 
-   processed_inputs |= ((uint64_t)1 << loc);
-   loc++;
+   processed_inputs |= ((uint64_t)1 << (loc + i));
input_idx += 4;
}
}

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Mesa (master): broadcom/vc5: Fix RG16I/UI texture sampling.

2018-03-27 Thread Eric Anholt 
Module: Mesa
Branch: master
Commit: 9f1b4f620464f76c82bcf4b36514f895c59f5c17
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f1b4f620464f76c82bcf4b36514f895c59f5c17

Author: Eric Anholt 
Date:   Tue Mar 27 14:26:17 2018 -0700

broadcom/vc5: Fix RG16I/UI texture sampling.

How many times did I look at this table without noticing the missing 'G'
in the texture column?

Fixes KHR-GLES3.copy_tex_image_conversions.required.* on 7268.

---

 src/gallium/drivers/vc5/v3dx_format_table.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/vc5/v3dx_format_table.c 
b/src/gallium/drivers/vc5/v3dx_format_table.c
index 4aaf0ecd3d..cc356fc381 100644
--- a/src/gallium/drivers/vc5/v3dx_format_table.c
+++ b/src/gallium/drivers/vc5/v3dx_format_table.c
@@ -120,8 +120,8 @@ static const struct vc5_format format_table[] = {
 
 FORMAT(R16_SINT,  R16I, R16I,SWIZ_X001, 16, 0),
 FORMAT(R16_UINT,  R16UI,R16UI,   SWIZ_X001, 16, 0),
-FORMAT(R16G16_SINT,   RG16I,R16I,SWIZ_XY01, 16, 0),
-FORMAT(R16G16_UINT,   RG16UI,   R16UI,   SWIZ_XY01, 16, 0),
+FORMAT(R16G16_SINT,   RG16I,RG16I,   SWIZ_XY01, 16, 0),
+FORMAT(R16G16_UINT,   RG16UI,   RG16UI,  SWIZ_XY01, 16, 0),
 FORMAT(R16G16B16A16_SINT, RGBA16I,  RGBA16I, SWIZ_XYZW, 16, 0),
 FORMAT(R16G16B16A16_UINT, RGBA16UI, RGBA16UI,SWIZ_XYZW, 16, 0),
 

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Mesa (master): nir: fix generated nir_intrinsics.c for MSVC

2018-03-27 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: 16581904b0b325c8b6d9abe81462c33e6b99a644
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=16581904b0b325c8b6d9abe81462c33e6b99a644

Author: Rob Clark 
Date:   Tue Mar 27 14:52:55 2018 -0400

nir: fix generated nir_intrinsics.c for MSVC

Apparently it is not happy about things like: .foo = {}

So skip over initializers for empty lists.

Fixes: 76dfed8ae2d5c6c509eb2661389be3c6a25077df
Reported-by: Roland Scheidegger 
Signed-off-by: Rob Clark 

---

 src/compiler/nir/nir_intrinsics_c.py | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/compiler/nir/nir_intrinsics_c.py 
b/src/compiler/nir/nir_intrinsics_c.py
index 556db785c2..339214ac53 100644
--- a/src/compiler/nir/nir_intrinsics_c.py
+++ b/src/compiler/nir/nir_intrinsics_c.py
@@ -29,18 +29,22 @@ const nir_intrinsic_info 
nir_intrinsic_infos[nir_num_intrinsics] = {
 {
.name = "${name}",
.num_srcs = ${opcode.num_srcs},
+% if opcode.src_components:
.src_components = {
   ${", ".join(str(comp) for comp in opcode.src_components)}
},
+% endif
.has_dest = ${"true" if opcode.has_dest else "false"},
.dest_components = ${opcode.dest_components},
.num_variables = ${opcode.num_variables},
.num_indices = ${opcode.num_indices},
+% if opcode.indices:
.index_map = {
 % for i in range(len(opcode.indices)):
   [${opcode.indices[i]}] = ${i + 1},
 % endfor
 },
+% endif
.flags = ${"0" if len(opcode.flags) == 0 else " | ".join(opcode.flags)},
 },
 % endfor

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Mesa (master): docs: update calendar 18.0.0 is out

2018-03-27 Thread Emil Velikov 
Module: Mesa
Branch: master
Commit: eda2f58d15f2fe99e7c868d37280e19c70ecb511
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eda2f58d15f2fe99e7c868d37280e19c70ecb511

Author: Emil Velikov 
Date:   Tue Mar 27 19:11:45 2018 +0100

docs: update calendar 18.0.0 is out

Signed-off-by: Emil Velikov 

---

 docs/release-calendar.html | 26 --
 1 file changed, 4 insertions(+), 22 deletions(-)

diff --git a/docs/release-calendar.html b/docs/release-calendar.html
index 6d0b618176..37a523e904 100644
--- a/docs/release-calendar.html
+++ b/docs/release-calendar.html
@@ -52,38 +52,20 @@ if you'd like to nominate a patch in the next stable 
release.
 Final planned release for the 17.3 series
 
 
-18.0
-2018-01-26
-18.0.0-rc2
-Emil Velikov
-
-
-
-2018-02-02
-18.0.0-rc3
-Emil Velikov
-
-
-
-2018-02-09
-18.0.0-rc4
-Emil Velikov
-May be promoted to 18.0.0 final
-
-
-2018-02-23
+18.0
+2018-04-06
 18.0.1
 Andres Gomez
 
 
 
-2018-03-09
+2018-04-20
 18.0.2
 Andres Gomez
 
 
 
-2018-03-23
+2018-05-04
 18.0.3
 Andres Gomez
 

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Mesa (master): docs: add sha256 checksums for 18.0.0

2018-03-27 Thread Emil Velikov 
Module: Mesa
Branch: master
Commit: 62eb721ed82886884295e0a370875505f7e9c325
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=62eb721ed82886884295e0a370875505f7e9c325

Author: Emil Velikov 
Date:   Tue Mar 27 19:02:59 2018 +0100

docs: add sha256 checksums for 18.0.0

Signed-off-by: Emil Velikov 
(cherry picked from commit fb64913d195112462786c0459d12f4bc8e7adee7)

---

 docs/relnotes/18.0.0.html | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/docs/relnotes/18.0.0.html b/docs/relnotes/18.0.0.html
index 99ab27664b..2b374be632 100644
--- a/docs/relnotes/18.0.0.html
+++ b/docs/relnotes/18.0.0.html
@@ -33,7 +33,8 @@ because compatibility contexts are not supported.
 
 SHA256 checksums
 
-TBD.
+93c2d3504b2871ac2146603fb1270f341d36a39695e2950a469c5eac74f98457  
mesa-18.0.0.tar.gz
+694e5c3d37717d23258c1f88bc134223c5d1aac70518d2f9134d6df3ee791eea  
mesa-18.0.0.tar.xz
 
 
 

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Mesa (18.0): docs: add sha256 checksums for 18.0.0

2018-03-27 Thread Emil Velikov 
Module: Mesa
Branch: 18.0
Commit: fb64913d195112462786c0459d12f4bc8e7adee7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb64913d195112462786c0459d12f4bc8e7adee7

Author: Emil Velikov 
Date:   Tue Mar 27 19:02:59 2018 +0100

docs: add sha256 checksums for 18.0.0

Signed-off-by: Emil Velikov 

---

 docs/relnotes/18.0.0.html | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/docs/relnotes/18.0.0.html b/docs/relnotes/18.0.0.html
index 99ab27664b..2b374be632 100644
--- a/docs/relnotes/18.0.0.html
+++ b/docs/relnotes/18.0.0.html
@@ -33,7 +33,8 @@ because compatibility contexts are not supported.
 
 SHA256 checksums
 
-TBD.
+93c2d3504b2871ac2146603fb1270f341d36a39695e2950a469c5eac74f98457  
mesa-18.0.0.tar.gz
+694e5c3d37717d23258c1f88bc134223c5d1aac70518d2f9134d6df3ee791eea  
mesa-18.0.0.tar.xz
 
 
 

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Mesa (master): docs: add news item and link release notes for 18.0.0

2018-03-27 Thread Emil Velikov 
Module: Mesa
Branch: master
Commit: 02f89b62fea8714fe58d2a41fc245f2e105863aa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=02f89b62fea8714fe58d2a41fc245f2e105863aa

Author: Emil Velikov 
Date:   Tue Mar 27 19:08:48 2018 +0100

docs: add news item and link release notes for 18.0.0

Signed-off-by: Emil Velikov 

---

 docs/index.html| 7 +++
 docs/relnotes.html | 1 +
 2 files changed, 8 insertions(+)

diff --git a/docs/index.html b/docs/index.html
index 5c54a73646..9061c2e055 100644
--- a/docs/index.html
+++ b/docs/index.html
@@ -16,6 +16,13 @@
 
 News
 
+March 27, 2018
+
+Mesa 18.0.0 is released.  This is a
+new development release.  See the release notes for more information
+about the release.
+
+
 March 21, 2018
 
 Mesa 17.3.7 is released.
diff --git a/docs/relnotes.html b/docs/relnotes.html
index 96bf3fec45..5358ef0ef3 100644
--- a/docs/relnotes.html
+++ b/docs/relnotes.html
@@ -21,6 +21,7 @@ The release notes summarize what's new or changed in each 
Mesa release.
 
 
 
+18.0.0 release notes
 17.3.7 release notes
 17.3.6 release notes
 17.3.5 release notes

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Mesa (master): docs: Update 18.0.0 release notes

2018-03-27 Thread Emil Velikov 
Module: Mesa
Branch: master
Commit: 839fb3a696679bfe975c245fdbfa6d410f1e5843
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=839fb3a696679bfe975c245fdbfa6d410f1e5843

Author: Emil Velikov 
Date:   Tue Mar 27 17:19:58 2018 +0100

docs: Update 18.0.0 release notes

Note: the file was originally 17.4.0, yet git stuggles to detect the
move :-\

Signed-off-by: Emil Velikov 
(cherry picked from commit dceb1ce807a8b0ab32dc16b38040969bdbcc0d1b)

---

 docs/relnotes/17.4.0.html |  74 ---
 docs/relnotes/18.0.0.html | 320 ++
 2 files changed, 320 insertions(+), 74 deletions(-)

diff --git a/docs/relnotes/17.4.0.html b/docs/relnotes/17.4.0.html
deleted file mode 100644
index 6bebb514bd..00
--- a/docs/relnotes/17.4.0.html
+++ /dev/null
@@ -1,74 +0,0 @@
-http://www.w3.org/TR/html4/loose.dtd;>
-
-
-  
-  Mesa Release Notes
-  
-
-
-
-
-  The Mesa 3D Graphics Library
-
-
-
-
-
-Mesa 17.4.0 Release Notes / TBD
-
-
-Mesa 17.4.0 is a new development release.
-People who are concerned with stability and reliability should stick
-with a previous release or wait for Mesa 17.4.1.
-
-
-Mesa 17.4.0 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is only available if requested at context creation
-because compatibility contexts are not supported.
-
-
-
-SHA256 checksums
-
-TBD.
-
-
-
-New features
-
-
-Note: some of the new features are only available with certain drivers.
-
-
-
-Disk shader cache support for i965 when MESA_GLSL_CACHE_DISABLE 
environment variable is set to "0" or "false"
-GL_ARB_shader_atomic_counters and GL_ARB_shader_atomic_counter_ops on 
r600/evergreen+
-GL_ARB_shader_image_load_store and GL_ARB_shader_image_size on 
r600/evergreen+
-GL_ARB_shader_storage_buffer_object on r600/evergreen+
-GL_ARB_compute_shader on r600/evergreen+
-GL_ARB_cull_distance on r600/evergreen+
-GL_ARB_enhanced_layouts on r600/evergreen+
-GL_ARB_bindless_texture on nvc0/kepler
-OpenGL 4.3 on r600/evergreen with hw fp64 support
-Support 1 binary format for GL_ARB_get_program_binary on i965
-Cannonlake support on i965 and anv
-
-
-Bug fixes
-
-
-TBD
-
-
-Changes
-
-
-Remove incomplete GLX_MESA_set_3dfx_mode from the Xlib libGL
-
-
-
-
-
diff --git a/docs/relnotes/18.0.0.html b/docs/relnotes/18.0.0.html
new file mode 100644
index 00..99ab27664b
--- /dev/null
+++ b/docs/relnotes/18.0.0.html
@@ -0,0 +1,320 @@
+http://www.w3.org/TR/html4/loose.dtd;>
+
+
+  
+  Mesa Release Notes
+  
+
+
+
+
+  The Mesa 3D Graphics Library
+
+
+
+
+
+Mesa 17.4.0 Release Notes / March 27 2018
+
+
+Mesa 17.4.0 is a new development release.
+People who are concerned with stability and reliability should stick
+with a previous release or wait for Mesa 17.4.1.
+
+
+Mesa 17.4.0 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is only available if requested at context creation
+because compatibility contexts are not supported.
+
+
+
+SHA256 checksums
+
+TBD.
+
+
+
+New features
+
+
+Note: some of the new features are only available with certain drivers.
+
+
+
+Disk shader cache support for i965 when MESA_GLSL_CACHE_DISABLE 
environment variable is set to "0" or "false"
+GL_ARB_shader_atomic_counters and GL_ARB_shader_atomic_counter_ops on 
r600/evergreen+
+GL_ARB_shader_image_load_store and GL_ARB_shader_image_size on 
r600/evergreen+
+GL_ARB_shader_storage_buffer_object on r600/evergreen+
+GL_ARB_compute_shader on r600/evergreen+
+GL_ARB_cull_distance on r600/evergreen+
+GL_ARB_enhanced_layouts on r600/evergreen+
+GL_ARB_bindless_texture on nvc0/kepler
+OpenGL 4.3 on r600/evergreen with hw fp64 support
+Support 1 binary format for GL_ARB_get_program_binary on i965.
+(For the 18.0 release, 0 formats continue to be supported in
+compatibility profiles.)
+Cannonlake support on i965 and anv
+
+
+Bug fixes
+
+
+
+https://bugs.freedesktop.org/show_bug.cgi?id=85564;>Bug 85564 
- Dead Island rendering issues
+
+https://bugs.freedesktop.org/show_bug.cgi?id=90311;>Bug 90311 
- Fail to build libglx with clang at linking stage
+
+https://bugs.freedesktop.org/show_bug.cgi?id=92363;>Bug 92363 
- [BSW/BDW] ogles1conform Gets test fails
+
+https://bugs.freedesktop.org/show_bug.cgi?id=94739;>Bug 94739 
- Mesa 11.1.2 implementation error: bad format MESA_FORMAT_Z_FLOAT32 in 
_mesa_unpack_uint_24_8_depth_stencil_row
+
+https://bugs.freedesktop.org/show_bug.cgi?id=97532;>Bug 97532 
- Regression: GLB 2.7  Glmark-2 GLES versions segfault due to linker 
precision error (259fc505) on dead

Mesa: tag mesa-18.0.0: mesa-18.0.0

2018-03-27 Thread Emil Velikov 
Module: Mesa
Branch: refs/tags/mesa-18.0.0
Tag:d23dc99cc8ab9a31853db66d2bf09c1ff7f2594e
URL:
http://cgit.freedesktop.org/mesa/mesa/tag/?id=d23dc99cc8ab9a31853db66d2bf09c1ff7f2594e

Tagger: Emil Velikov 
Date:   Tue Mar 27 18:24:25 2018 +0100

mesa-18.0.0
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Mesa (master): nir: mako all the intrinsics

2018-03-27 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: 76dfed8ae2d5c6c509eb2661389be3c6a25077df
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=76dfed8ae2d5c6c509eb2661389be3c6a25077df

Author: Rob Clark 
Date:   Thu Mar 15 18:42:44 2018 -0400

nir: mako all the intrinsics

I threatened to do this a long time ago.. I probably *should* have done
it a long time ago when there where many fewer intrinsics.  But the
system of macro/#include magic for dealing with intrinsics is a bit
annoying, and python has the nice property of optional fxn params,
making it possible to define new intrinsics while ignoring parameters
that are not applicable (and naming optional params).  And not having to
specify various array lengths explicitly is nice too.

I think the end result makes it easier to add new intrinsics.

v2: couple small fixes found with a test program to compare the old and
new tables
v3: misc comments, don't rely on capture=true for meson.build, get rid
of system_values table to avoid return value of intrinsic() and
*mostly* remove side-effects, add autotools build support
v4: scons build

Signed-off-by: Rob Clark 
Acked-by: Dylan Baker 
Acked-by: Jason Ekstrand 

---

 src/compiler/Makefile.nir.am   |  13 +-
 src/compiler/Makefile.sources  |   4 +-
 src/compiler/SConscript.nir|  16 +
 src/compiler/nir/meson.build   |  24 +-
 src/compiler/nir/nir.h |   9 -
 src/compiler/nir/nir_builder.h |  27 +-
 src/compiler/nir/nir_builder_opcodes_h.py  |  24 +-
 src/compiler/nir/nir_intrinsics.h  | 540 
 src/compiler/nir/nir_intrinsics.py | 546 +
 src/compiler/nir/nir_intrinsics_c.py   |  68 +++
 .../nir/{nir_intrinsics.c => nir_intrinsics_h.py}  |  75 +--
 11 files changed, 727 insertions(+), 619 deletions(-)

Diff:   
http://cgit.freedesktop.org/mesa/mesa/diff/?id=76dfed8ae2d5c6c509eb2661389be3c6a25077df
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Mesa (master): nir: fix per_vertex_output intrinsic

2018-03-27 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: cc3a88e81dbceb12b79eb4ebe7a4ce5ba97fc291
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc3a88e81dbceb12b79eb4ebe7a4ce5ba97fc291

Author: Rob Clark 
Date:   Fri Mar 16 13:10:18 2018 -0400

nir: fix per_vertex_output intrinsic

This is supposed to have both BASE and COMPONENT but num_indices was
inadvertantly set to 1.

Cc: 
Signed-off-by: Rob Clark 
Reviewed-by: Jason Ekstrand 

---

 src/compiler/nir/nir_intrinsics.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir_intrinsics.h 
b/src/compiler/nir/nir_intrinsics.h
index 8f3d3bcfa2..df2790869b 100644
--- a/src/compiler/nir/nir_intrinsics.h
+++ b/src/compiler/nir/nir_intrinsics.h
@@ -505,7 +505,7 @@ LOAD(ssbo, 2, 0, xx, xx, xx, NIR_INTRINSIC_CAN_ELIMINATE)
 /* src[] = { offset }. const_index[] = { base, component } */
 LOAD(output, 1, 2, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE)
 /* src[] = { vertex, offset }. const_index[] = { base, component } */
-LOAD(per_vertex_output, 2, 1, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE)
+LOAD(per_vertex_output, 2, 2, BASE, COMPONENT, xx, NIR_INTRINSIC_CAN_ELIMINATE)
 /* src[] = { offset }. const_index[] = { base } */
 LOAD(shared, 1, 1, BASE, xx, xx, NIR_INTRINSIC_CAN_ELIMINATE)
 /* src[] = { offset }. const_index[] = { base, range } */

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Mesa (18.0): docs: Update 18.0.0 release notes

2018-03-27 Thread Emil Velikov 
Module: Mesa
Branch: 18.0
Commit: dceb1ce807a8b0ab32dc16b38040969bdbcc0d1b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dceb1ce807a8b0ab32dc16b38040969bdbcc0d1b

Author: Emil Velikov 
Date:   Tue Mar 27 17:19:58 2018 +0100

docs: Update 18.0.0 release notes

Note: the file was originally 17.4.0, yet git stuggles to detect the
move :-\

Signed-off-by: Emil Velikov 

---

 docs/relnotes/17.4.0.html |  76 ---
 docs/relnotes/18.0.0.html | 320 ++
 2 files changed, 320 insertions(+), 76 deletions(-)

diff --git a/docs/relnotes/17.4.0.html b/docs/relnotes/17.4.0.html
deleted file mode 100644
index 529774efdd..00
--- a/docs/relnotes/17.4.0.html
+++ /dev/null
@@ -1,76 +0,0 @@
-http://www.w3.org/TR/html4/loose.dtd;>
-
-
-  
-  Mesa Release Notes
-  
-
-
-
-
-  The Mesa 3D Graphics Library
-
-
-
-
-
-Mesa 17.4.0 Release Notes / TBD
-
-
-Mesa 17.4.0 is a new development release.
-People who are concerned with stability and reliability should stick
-with a previous release or wait for Mesa 17.4.1.
-
-
-Mesa 17.4.0 implements the OpenGL 4.5 API, but the version reported by
-glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
-glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
-Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
-4.5 is only available if requested at context creation
-because compatibility contexts are not supported.
-
-
-
-SHA256 checksums
-
-TBD.
-
-
-
-New features
-
-
-Note: some of the new features are only available with certain drivers.
-
-
-
-Disk shader cache support for i965 when MESA_GLSL_CACHE_DISABLE 
environment variable is set to "0" or "false"
-GL_ARB_shader_atomic_counters and GL_ARB_shader_atomic_counter_ops on 
r600/evergreen+
-GL_ARB_shader_image_load_store and GL_ARB_shader_image_size on 
r600/evergreen+
-GL_ARB_shader_storage_buffer_object on r600/evergreen+
-GL_ARB_compute_shader on r600/evergreen+
-GL_ARB_cull_distance on r600/evergreen+
-GL_ARB_enhanced_layouts on r600/evergreen+
-GL_ARB_bindless_texture on nvc0/kepler
-OpenGL 4.3 on r600/evergreen with hw fp64 support
-Support 1 binary format for GL_ARB_get_program_binary on i965.
-(For the 18.0 release, 0 formats continue to be supported in
-compatibility profiles.)
-Cannonlake support on i965 and anv
-
-
-Bug fixes
-
-
-TBD
-
-
-Changes
-
-
-Remove incomplete GLX_MESA_set_3dfx_mode from the Xlib libGL
-
-
-
-
-
diff --git a/docs/relnotes/18.0.0.html b/docs/relnotes/18.0.0.html
new file mode 100644
index 00..99ab27664b
--- /dev/null
+++ b/docs/relnotes/18.0.0.html
@@ -0,0 +1,320 @@
+http://www.w3.org/TR/html4/loose.dtd;>
+
+
+  
+  Mesa Release Notes
+  
+
+
+
+
+  The Mesa 3D Graphics Library
+
+
+
+
+
+Mesa 17.4.0 Release Notes / March 27 2018
+
+
+Mesa 17.4.0 is a new development release.
+People who are concerned with stability and reliability should stick
+with a previous release or wait for Mesa 17.4.1.
+
+
+Mesa 17.4.0 implements the OpenGL 4.5 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.5.  OpenGL
+4.5 is only available if requested at context creation
+because compatibility contexts are not supported.
+
+
+
+SHA256 checksums
+
+TBD.
+
+
+
+New features
+
+
+Note: some of the new features are only available with certain drivers.
+
+
+
+Disk shader cache support for i965 when MESA_GLSL_CACHE_DISABLE 
environment variable is set to "0" or "false"
+GL_ARB_shader_atomic_counters and GL_ARB_shader_atomic_counter_ops on 
r600/evergreen+
+GL_ARB_shader_image_load_store and GL_ARB_shader_image_size on 
r600/evergreen+
+GL_ARB_shader_storage_buffer_object on r600/evergreen+
+GL_ARB_compute_shader on r600/evergreen+
+GL_ARB_cull_distance on r600/evergreen+
+GL_ARB_enhanced_layouts on r600/evergreen+
+GL_ARB_bindless_texture on nvc0/kepler
+OpenGL 4.3 on r600/evergreen with hw fp64 support
+Support 1 binary format for GL_ARB_get_program_binary on i965.
+(For the 18.0 release, 0 formats continue to be supported in
+compatibility profiles.)
+Cannonlake support on i965 and anv
+
+
+Bug fixes
+
+
+
+https://bugs.freedesktop.org/show_bug.cgi?id=85564;>Bug 85564 
- Dead Island rendering issues
+
+https://bugs.freedesktop.org/show_bug.cgi?id=90311;>Bug 90311 
- Fail to build libglx with clang at linking stage
+
+https://bugs.freedesktop.org/show_bug.cgi?id=92363;>Bug 92363 
- [BSW/BDW] ogles1conform Gets test fails
+
+https://bugs.freedesktop.org/show_bug.cgi?id=94739;>Bug 94739 
- Mesa 11.1.2 implementation error: bad format MESA_FORMAT_Z_FLOAT32 in 
_mesa_unpack_uint_24_8_depth_stencil_row
+
+https://bugs.freedesktop.org/show_bug.cgi?id=97532;>Bug 97532 
- Regression: GLB 2.7  Glmark-2 GLES versions segfault due to linker 
precision

Mesa (18.0): Update version to 18.0.0(final)

2018-03-27 Thread Emil Velikov 
Module: Mesa
Branch: 18.0
Commit: e28e8c0ffa21f88e59679ca6372ab391425979d2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e28e8c0ffa21f88e59679ca6372ab391425979d2

Author: Emil Velikov 
Date:   Tue Mar 27 17:12:42 2018 +0100

Update version to 18.0.0(final)

Signed-off-by: Emil Velikov 

---

 VERSION | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/VERSION b/VERSION
index 593b157732..7eae4e2e91 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-18.0.0-rc5
+18.0.0

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Mesa (master): glsl_types: fix build break with intel/msvc compiler

2018-03-27 Thread Rob Clark 
Module: Mesa
Branch: master
Commit: 1e0a06000bae17e1791f55127e7527946e9b6793
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e0a06000bae17e1791f55127e7527946e9b6793

Author: Rob Clark 
Date:   Mon Mar 26 18:45:07 2018 -0400

glsl_types: fix build break with intel/msvc compiler

The VECN() macro was taking advantage of a GCC specific feature that is
not available on lesser compilers, mostly for the purposes of avoiding a
macro that encoded a return statement.

But as suggested by Ian, we could just have the macro produce the entire
method body and avoid the need for this.  So let's do that instead.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105740
Fixes: f407edf3407396379e16b0be74b8d3b85d2ad7f0
Cc: Emil Velikov 
Cc: Timothy Arceri 
Cc: Roland Scheidegger 
Cc: Ian Romanick 
Signed-off-by: Rob Clark 
Acked-by: Timothy Arceri 
Reviewed-by: Roland Scheidegger 
Reviewed-by: Ian Romanick 

---

 src/compiler/glsl_types.cpp | 107 ++--
 1 file changed, 24 insertions(+), 83 deletions(-)

diff --git a/src/compiler/glsl_types.cpp b/src/compiler/glsl_types.cpp
index b8caddb406..9d853caf72 100644
--- a/src/compiler/glsl_types.cpp
+++ b/src/compiler/glsl_types.cpp
@@ -509,89 +509,30 @@ glsl_type::vec(unsigned components, const glsl_type 
*const ts[])
return ts[n - 1];
 }
 
-#define VECN(components, sname, vname) ({\
-  static const glsl_type *const ts[] = { \
- sname ## _type, vname ## 2_type,\
- vname ## 3_type, vname ## 4_type,   \
- vname ## 8_type, vname ## 16_type,  \
-  }; \
-  glsl_type::vec(components, ts);\
-   })
-
-const glsl_type *
-glsl_type::vec(unsigned components)
-{
-   return VECN(components, float, vec);
-}
-
-const glsl_type *
-glsl_type::f16vec(unsigned components)
-{
-   return VECN(components, float16_t, f16vec);
-}
-
-const glsl_type *
-glsl_type::dvec(unsigned components)
-{
-   return VECN(components, double, dvec);
-}
-
-const glsl_type *
-glsl_type::ivec(unsigned components)
-{
-   return VECN(components, int, ivec);
-}
-
-const glsl_type *
-glsl_type::uvec(unsigned components)
-{
-   return VECN(components, uint, uvec);
-}
-
-const glsl_type *
-glsl_type::bvec(unsigned components)
-{
-   return VECN(components, bool, bvec);
-}
-
-const glsl_type *
-glsl_type::i64vec(unsigned components)
-{
-   return VECN(components, int64_t, i64vec);
-}
-
-
-const glsl_type *
-glsl_type::u64vec(unsigned components)
-{
-   return VECN(components, uint64_t, u64vec);
-}
-
-const glsl_type *
-glsl_type::i16vec(unsigned components)
-{
-   return VECN(components, int16_t, i16vec);
-}
-
-
-const glsl_type *
-glsl_type::u16vec(unsigned components)
-{
-   return VECN(components, uint16_t, u16vec);
-}
-
-const glsl_type *
-glsl_type::i8vec(unsigned components)
-{
-   return VECN(components, int8_t, i8vec);
-}
-
-
-const glsl_type *
-glsl_type::u8vec(unsigned components)
-{
-   return VECN(components, uint8_t, u8vec);
-}
+#define VECN(components, sname, vname)   \
+const glsl_type *\
+glsl_type:: vname (unsigned components)  \
+{\
+   static const glsl_type *const ts[] = {\
+  sname ## _type, vname ## 2_type,   \
+  vname ## 3_type, vname ## 4_type,  \
+  vname ## 8_type, vname ## 16_type, \
+   };\
+   return glsl_type::vec(components, ts);\
+}
+
+VECN(components, float, vec)
+VECN(components, float16_t, f16vec)
+VECN(components, double, dvec)
+VECN(components, int, ivec)
+VECN(components, uint, uvec)
+VECN(components, bool, bvec)
+VECN(components, int64_t, i64vec)
+VECN(components, uint64_t, u64vec)
+VECN(components, int16_t, i16vec)
+VECN(components, uint16_t, u16vec)
+VECN(components, int8_t, i8vec)
+VECN(components, uint8_t, u8vec)
 
 const glsl_type *
 glsl_type::get_instance(unsigned base_type, unsigned rows, unsigned columns)

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Mesa (master): mesa: add GL_HALF_FLOAT as supported type to readpixels

2018-03-27 Thread Tapani Pälli 
Module: Mesa
Branch: master
Commit: 41cf30b8bc55fdf36adac3311002dc32b6715949
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=41cf30b8bc55fdf36adac3311002dc32b6715949

Author: Lin Johnson 
Date:   Mon Mar 26 22:13:32 2018 +0800

mesa: add GL_HALF_FLOAT as supported type to readpixels

EXT_color_buffer_float spec states:

  "An INVALID_OPERATION error is generated ... if the color buffer is
   a floating-point format and type is not FLOAT, HALF FLOAT, or
   UNSIGNED_INT_10F_11F_11F_REV."

This means that GL_HALF_FLOAT type should be supported when color
buffer has floating-point format.

Fixes Android CTS test android.view.cts.PixelCopyTest.

v2: remove comments of EXT_color_buffer_half_float as
EXT_color_buffer_float can use type GL_HALF_FLOAT

Signed-off-by: Lin Johnson 
Reviewed-by: Tapani Pälli 

---

 src/mesa/main/readpix.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/main/readpix.c b/src/mesa/main/readpix.c
index 6ce340ddf9..4407f13289 100644
--- a/src/mesa/main/readpix.c
+++ b/src/mesa/main/readpix.c
@@ -920,6 +920,8 @@ read_pixels_es3_error_check(GLenum format, GLenum type,
case GL_RGBA:
   if (type == GL_FLOAT && data_type == GL_FLOAT)
  return GL_NO_ERROR; /* EXT_color_buffer_float */
+  if (type == GL_HALF_FLOAT && data_type == GL_FLOAT)
+ return GL_NO_ERROR;
   if (type == GL_UNSIGNED_BYTE && data_type == GL_UNSIGNED_NORMALIZED)
  return GL_NO_ERROR;
   if (internalFormat == GL_RGB10_A2 &&

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