date:20180410

Mesa (master): vulkan: Drop vk_android_native_buffer.xml

2018-04-10 Thread Jason Ekstrand

Module: Mesa
Branch: master
Commit: 69f447553c6cd8c9004b80c099630ce7167a0a28
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=69f447553c6cd8c9004b80c099630ce7167a0a28

Author: Jason Ekstrand 
Date:   Mon Apr  9 22:01:14 2018 -0700

vulkan: Drop vk_android_native_buffer.xml

All the information in vk_android_native_buffer.xml is now in vk.xml.
The only exception is the extension type attribute which we can work
around in the generators while we wait for the XML to be fixed.

Reviewed-by: Dylan Baker 

---

 src/Makefile.am  |  1 -
 src/amd/vulkan/Makefile.am   |  3 --
 src/amd/vulkan/meson.build   |  4 +-
 src/amd/vulkan/radv_extensions.py| 17 +++-
 src/intel/Android.vulkan.mk  |  6 +--
 src/intel/Makefile.vulkan.am | 13 ++
 src/intel/vulkan/anv_extensions_gen.py   | 17 +++-
 src/intel/vulkan/meson.build | 12 +++---
 src/vulkan/Android.mk|  4 +-
 src/vulkan/Makefile.am   |  5 +--
 src/vulkan/meson.build   |  1 -
 src/vulkan/registry/vk_android_native_buffer.xml | 52 
 12 files changed, 26 insertions(+), 109 deletions(-)

diff --git a/src/Makefile.am b/src/Makefile.am
index 014ffaf3e2..fd5ae44550 100644
--- a/src/Makefile.am
+++ b/src/Makefile.am
@@ -67,7 +67,6 @@ SUBDIRS += vulkan
 endif
 
 EXTRA_DIST += vulkan/registry/vk.xml
-EXTRA_DIST += vulkan/registry/vk_android_native_buffer.xml
 
 if HAVE_AMD_DRIVERS
 SUBDIRS += amd
diff --git a/src/amd/vulkan/Makefile.am b/src/amd/vulkan/Makefile.am
index 00b808229f..18f263ab44 100644
--- a/src/amd/vulkan/Makefile.am
+++ b/src/amd/vulkan/Makefile.am
@@ -117,13 +117,11 @@ nodist_EXTRA_libvulkan_radeon_la_SOURCES = dummy.cpp
 libvulkan_radeon_la_SOURCES = $(VULKAN_GEM_FILES)
 
 vulkan_api_xml = $(top_srcdir)/src/vulkan/registry/vk.xml
-vk_android_native_buffer_xml = 
$(top_srcdir)/src/vulkan/registry/vk_android_native_buffer.xml
 
 radv_entrypoints.c: radv_entrypoints_gen.py radv_extensions.py 
$(vulkan_api_xml)
$(MKDIR_GEN)
$(AM_V_GEN)$(PYTHON2) $(srcdir)/radv_entrypoints_gen.py \
--xml $(vulkan_api_xml) \
-   --xml $(vk_android_native_buffer_xml) \
--outdir $(builddir)
 radv_entrypoints.h: radv_entrypoints.c
 
@@ -132,7 +130,6 @@ radv_extensions.c: radv_extensions.py \
$(MKDIR_GEN)
$(AM_V_GEN)$(PYTHON2) $(srcdir)/radv_extensions.py \
--xml $(vulkan_api_xml) \
-   --xml $(vk_android_native_buffer_xml) \
--out-c radv_extensions.c \
--out-h radv_extensions.h
 radv_extensions.h: radv_extensions.c
diff --git a/src/amd/vulkan/meson.build b/src/amd/vulkan/meson.build
index c3a6a8182b..b5a99fe91e 100644
--- a/src/amd/vulkan/meson.build
+++ b/src/amd/vulkan/meson.build
@@ -31,10 +31,10 @@ radv_entrypoints = custom_target(
 
 radv_extensions_c = custom_target(
   'radv_extensions.c',
-  input : ['radv_extensions.py', vk_api_xml, vk_android_native_buffer_xml],
+  input : ['radv_extensions.py', vk_api_xml],
   output : ['radv_extensions.c', 'radv_extensions.h'],
   command : [
-prog_python2, '@INPUT0@', '--xml', '@INPUT1@', '--xml', '@INPUT2@', 
'--out-c', '@OUTPUT0@',
+prog_python2, '@INPUT0@', '--xml', '@INPUT1@', '--out-c', '@OUTPUT0@',
 '--out-h', '@OUTPUT1@'
   ],
 )
diff --git a/src/amd/vulkan/radv_extensions.py 
b/src/amd/vulkan/radv_extensions.py
index a25db637e2..a680f42dec 100644
--- a/src/amd/vulkan/radv_extensions.py
+++ b/src/amd/vulkan/radv_extensions.py
@@ -159,18 +159,13 @@ def _init_exts_from_xml(xml):
 if ext_name not in ext_name_map:
 continue
 
-# Workaround for VK_ANDROID_native_buffer. Its  element in
-# vk.xml lists it as supported="disabled" and provides only a stub
-# definition.  Its  element in Mesa's custom
-# vk_android_native_buffer.xml, though, lists it as
-# supported='android-vendor' and fully defines the extension. We want
-# to skip the  element in vk.xml.
-if ext_elem.attrib['supported'] == 'disabled':
-assert ext_name == 'VK_ANDROID_native_buffer'
-continue
-
 ext = ext_name_map[ext_name]
-ext.type = ext_elem.attrib['type']
+if ext_name == 'VK_ANDROID_native_buffer':
+# VK_ANDROID_native_buffer is missing the type specifier.  Just
+# hard-code it to be a device extension for now.
+ext.type = 'device'
+else:
+ext.type = ext_elem.attrib['type']
 
 _TEMPLATE_H = Template(COPYRIGHT + """
 #ifndef RADV_EXTENSIONS_H
diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk
index 0ec0d78a2f..09dc22875a 100644
--- a/src/intel/Android.vulkan.mk
+++ b/src/intel/Android.vulkan.mk
@@ -67,8 +67,7 @@

Mesa (master): nir/lower_atomics: Rework the main walker loop a bit

2018-04-10 Thread Jason Ekstrand

Module: Mesa
Branch: master
Commit: ae3a856c34e348f721c2d647999813801b5eb33c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ae3a856c34e348f721c2d647999813801b5eb33c

Author: Jason Ekstrand 
Date:   Tue Mar 20 15:44:16 2018 -0700

nir/lower_atomics: Rework the main walker loop a bit

This replaces some "if (...} { }" with "if (...) continue;" to reduce
nesting depth and makes nir_metadata_preserve conditional on progress
for the given impl.

Reviewed-by: Caio Marcelo de Oliveira Filho 

---

 src/compiler/nir/nir_lower_atomics.c | 24 
 1 file changed, 16 insertions(+), 8 deletions(-)

diff --git a/src/compiler/nir/nir_lower_atomics.c 
b/src/compiler/nir/nir_lower_atomics.c
index 6b046bc426..ee66aa3d7d 100644
--- a/src/compiler/nir/nir_lower_atomics.c
+++ b/src/compiler/nir/nir_lower_atomics.c
@@ -183,18 +183,26 @@ nir_lower_atomics(nir_shader *shader,
bool progress = false;
 
nir_foreach_function(function, shader) {
-  if (function->impl) {
- nir_foreach_block(block, function->impl) {
-nir_foreach_instr_safe(instr, block) {
-   if (instr->type == nir_instr_type_intrinsic)
-  progress |= lower_instr(nir_instr_as_intrinsic(instr),
-  shader_program, shader,
-  use_binding_as_idx);
-}
+  if (!function->impl)
+ continue;
+
+  bool impl_progress = false;
+
+  nir_foreach_block(block, function->impl) {
+ nir_foreach_instr_safe(instr, block) {
+if (instr->type != nir_instr_type_intrinsic)
+   continue;
+
+impl_progress |= lower_instr(nir_instr_as_intrinsic(instr),
+ shader_program, shader,
+ use_binding_as_idx);
  }
+  }
 
+  if (impl_progress) {
  nir_metadata_preserve(function->impl, nir_metadata_block_index |
nir_metadata_dominance);
+ progress = true;
   }
}
 

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Mesa (master): radv: Enable RB+ where possible.

2018-04-10 Thread Bas Nieuwenhuizen

Module: Mesa
Branch: master
Commit: ed9463815644c85c124c72111d96e256db2986b4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed9463815644c85c124c72111d96e256db2986b4

Author: Bas Nieuwenhuizen 
Date:   Mon Apr  9 11:23:21 2018 +0200

radv: Enable RB+ where possible.

According to Marek, not enabling it on Stoney has a significant
negative performance impact. (And I guess this might impact
performance on Raven as well)

The register settings are pretty much copied from radeonsi. I did
not put this in the pipeline as that would make the pipeline more
dependent on the format which mean we would have to have more
pipelines for the meta shaders.

v2: Don't clear RB+ regs if not enabled as the CLEAR_STATE packet
does already.
Reviewed-by: Samuel Pitoiset 

---

 src/amd/vulkan/radv_cmd_buffer.c | 140 +++
 src/amd/vulkan/radv_pipeline.c   |  13 ++--
 src/amd/vulkan/radv_private.h|   4 ++
 3 files changed, 151 insertions(+), 6 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 3b1d6aedc8..f73526b5fc 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -679,6 +679,142 @@ radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer,
 }
 
 static void
+radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)
+{
+   if (!cmd_buffer->device->physical_device->rbplus_allowed)
+   return;
+
+   struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;
+   struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;
+   const struct radv_subpass *subpass = cmd_buffer->state.subpass;
+
+   unsigned sx_ps_downconvert = 0;
+   unsigned sx_blend_opt_epsilon = 0;
+   unsigned sx_blend_opt_control = 0;
+
+   for (unsigned i = 0; i < subpass->color_count; ++i) {
+   if (subpass->color_attachments[i].attachment == 
VK_ATTACHMENT_UNUSED)
+   continue;
+
+   int idx = subpass->color_attachments[i].attachment;
+   struct radv_color_buffer_info *cb = 
>attachments[idx].cb;
+
+   unsigned format = G_028C70_FORMAT(cb->cb_color_info);
+   unsigned swap = G_028C70_COMP_SWAP(cb->cb_color_info);
+   uint32_t spi_format = (pipeline->graphics.col_format >> (i * 
4)) & 0xf;
+   uint32_t colormask = (pipeline->graphics.cb_target_mask >> (i * 
4)) & 0xf;
+
+   bool has_alpha, has_rgb;
+
+   /* Set if RGB and A are present. */
+   has_alpha = !G_028C74_FORCE_DST_ALPHA_1(cb->cb_color_attrib);
+
+   if (format == V_028C70_COLOR_8 ||
+   format == V_028C70_COLOR_16 ||
+   format == V_028C70_COLOR_32)
+   has_rgb = !has_alpha;
+   else
+   has_rgb = true;
+
+   /* Check the colormask and export format. */
+   if (!(colormask & 0x7))
+   has_rgb = false;
+   if (!(colormask & 0x8))
+   has_alpha = false;
+
+   if (spi_format == V_028714_SPI_SHADER_ZERO) {
+   has_rgb = false;
+   has_alpha = false;
+   }
+
+   /* Disable value checking for disabled channels. */
+   if (!has_rgb)
+   sx_blend_opt_control |= 
S_02875C_MRT0_COLOR_OPT_DISABLE(1) << (i * 4);
+   if (!has_alpha)
+   sx_blend_opt_control |= 
S_02875C_MRT0_ALPHA_OPT_DISABLE(1) << (i * 4);
+
+   /* Enable down-conversion for 32bpp and smaller formats. */
+   switch (format) {
+   case V_028C70_COLOR_8:
+   case V_028C70_COLOR_8_8:
+   case V_028C70_COLOR_8_8_8_8:
+   /* For 1 and 2-channel formats, use the superset 
thereof. */
+   if (spi_format == V_028714_SPI_SHADER_FP16_ABGR ||
+   spi_format == V_028714_SPI_SHADER_UINT16_ABGR ||
+   spi_format == V_028714_SPI_SHADER_SINT16_ABGR) {
+   sx_ps_downconvert |= 
V_028754_SX_RT_EXPORT_8_8_8_8 << (i * 4);
+   sx_blend_opt_epsilon |= V_028758_8BIT_FORMAT << 
(i * 4);
+   }
+   break;
+
+   case V_028C70_COLOR_5_6_5:
+   if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
+   sx_ps_downconvert |= 
V_028754_SX_RT_EXPORT_5_6_5 << (i * 4);
+   sx_blend_opt_epsilon |= V_028758_6BIT_FORMAT << 
(i * 4);
+   }
+   break;
+
+   case V_028C70_COLOR_1_5_5_5:
+   if (spi_format == V_028714_SPI_SHADER_FP16_ABGR) {
+   sx_ps_downconvert |=

Mesa (master): nir: Check if u_vector_init() succeeds

2018-04-10 Thread Topi Pohjolainen

Module: Mesa
Branch: master
Commit: 5d895a1f374854a068104f07f79a24fc79110aea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d895a1f374854a068104f07f79a24fc79110aea

Author: Topi Pohjolainen 
Date:   Thu Apr  5 10:21:01 2018 +0300

nir: Check if u_vector_init() succeeds

However, it only fails when running out of memory. Now, if we
are about to check that, we should be consistent and check
the allocation of the worklist as well.

CID: 1433512
Fixes: edb18564c7 nir: Initial implementation of a nir_instr_worklist
Reviewed-by: Thomas Helland 
Signed-off-by: Topi Pohjolainen 

---

 src/compiler/nir/nir_worklist.h | 11 +--
 1 file changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/compiler/nir/nir_worklist.h b/src/compiler/nir/nir_worklist.h
index e376908766..3fb391fcef 100644
--- a/src/compiler/nir/nir_worklist.h
+++ b/src/compiler/nir/nir_worklist.h
@@ -105,8 +105,15 @@ typedef struct {
 static inline nir_instr_worklist *
 nir_instr_worklist_create() {
nir_instr_worklist *wl = malloc(sizeof(nir_instr_worklist));
-   u_vector_init(>instr_vec, sizeof(struct nir_instr *),
- sizeof(struct nir_instr *) * 8);
+   if (!wl)
+  return NULL;
+
+   if (!u_vector_init(>instr_vec, sizeof(struct nir_instr *),
+  sizeof(struct nir_instr *) * 8)) {
+  free(wl);
+  return NULL;
+   }
+
return wl;
 }
 

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Mesa (master): mesa: Assert base format before truncating to unsigned short

2018-04-10 Thread Topi Pohjolainen

Module: Mesa
Branch: master
Commit: 98d38747543277cf931499a6b66626ac644b1865
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=98d38747543277cf931499a6b66626ac644b1865

Author: Topi Pohjolainen 
Date:   Fri Apr  6 10:41:26 2018 +0300

mesa: Assert base format before truncating to unsigned short

CID: 1433709
Fixes: ca721b3d8: mesa: use GLenum16 in a few more places
Reviewed-by: Marek Olšák 
Reviewed-by: Brian Paul 

Signed-off-by: Topi Pohjolainen 

---

 src/mesa/main/teximage.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 8f5351085c..f560512fb4 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -845,6 +845,7 @@ _mesa_init_teximage_fields_ms(struct gl_context *ctx,
 mesa_format format,
 GLuint numSamples, GLboolean fixedSampleLocations)
 {
+   const GLint base_format =_mesa_base_tex_format(ctx, internalFormat);
GLenum target;
assert(img);
assert(width >= 0);
@@ -852,8 +853,8 @@ _mesa_init_teximage_fields_ms(struct gl_context *ctx,
assert(depth >= 0);
 
target = img->TexObject->Target;
-   img->_BaseFormat = _mesa_base_tex_format( ctx, internalFormat );
-   assert(img->_BaseFormat != -1);
+   assert(base_format != -1);
+   img->_BaseFormat = (GLenum16)base_format;
img->InternalFormat = internalFormat;
img->Border = border;
img->Width = width;

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Mesa (master): intel/dev: Assert the number of slices is not zero

2018-04-10 Thread Topi Pohjolainen

Module: Mesa
Branch: master
Commit: 26f48fe01092e2fb05daaa5090ac69f8a86a2cfd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=26f48fe01092e2fb05daaa5090ac69f8a86a2cfd

Author: Topi Pohjolainen 
Date:   Thu Apr  5 10:38:46 2018 +0300

intel/dev: Assert the number of slices is not zero

Fixes: c1900f5b intel: devinfo: add helper functions to fill...
CID: 1433511
Reviewed-by: Lionel Landwerlin 
Signed-off-by: Topi Pohjolainen 

---

 src/intel/dev/gen_device_info.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index f7cb94f179..dfeab6e606 100644
--- a/src/intel/dev/gen_device_info.c
+++ b/src/intel/dev/gen_device_info.c
@@ -1047,7 +1047,7 @@ gen_device_info_update_from_topology(struct 
gen_device_info *devinfo,
/* We expect the total number of EUs to be uniformly distributed throughout
 * the subslices.
 */
-   assert((n_eus % n_subslices) == 0);
+   assert(n_subslices && (n_eus % n_subslices) == 0);
devinfo->num_eu_per_subslice = n_eus / n_subslices;
 }
 

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Mesa (master): i965: Remove brw_bo_alloc_tiled_2d from intel_detect_swizzling.

2018-04-10 Thread Kenneth Graunke

Module: Mesa
Branch: master
Commit: 8960903c90e65c4d824e4ec247e5135d6909caa1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8960903c90e65c4d824e4ec247e5135d6909caa1

Author: Kenneth Graunke 
Date:   Mon Apr  9 22:45:43 2018 -0700

i965: Remove brw_bo_alloc_tiled_2d from intel_detect_swizzling.

I'd like to drop this pre-isl function.  This drops one of the two uses.

Reviewed-by: Iago Toral Quiroga 

---

 src/mesa/drivers/dri/i965/intel_screen.c | 14 --
 1 file changed, 4 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 29cb7ad57d..7f3c82fab8 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1828,24 +1828,18 @@ intel_init_bufmgr(struct intel_screen *screen)
 static bool
 intel_detect_swizzling(struct intel_screen *screen)
 {
-   struct brw_bo *buffer;
-   unsigned flags = 0;
-   uint32_t aligned_pitch;
uint32_t tiling = I915_TILING_X;
uint32_t swizzle_mode = 0;
-
-   buffer = brw_bo_alloc_tiled_2d(screen->bufmgr, "swizzle test",
-  64, 64, 4, tiling, _pitch, flags);
+   struct brw_bo *buffer =
+  brw_bo_alloc_tiled(screen->bufmgr, "swizzle test", 32768,
+ tiling, 512, 0);
if (buffer == NULL)
   return false;
 
brw_bo_get_tiling(buffer, , _mode);
brw_bo_unreference(buffer);
 
-   if (swizzle_mode == I915_BIT_6_SWIZZLE_NONE)
-  return false;
-   else
-  return true;
+   return swizzle_mode != I915_BIT_6_SWIZZLE_NONE;
 }
 
 static int

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Mesa (master): mesa: fix glsl version mismatch in compat profile

2018-04-10 Thread Timothy Arceri

Module: Mesa
Branch: master
Commit: a05faf80c380a03347604e79136627267ff9f893
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a05faf80c380a03347604e79136627267ff9f893

Author: Timothy Arceri 
Date:   Tue Apr 10 21:40:11 2018 +1000

mesa: fix glsl version mismatch in compat profile

Drivers that only support compat 3.0 were reporting GLSL 1.40
support. This fixes issues with the menu of Dawn of War II.

Fixes: a0c8b49284ef "mesa: enable OpenGL 3.1 with ARB_compatibility"

Reviewed-by: Marek Olšák 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105807

---

 src/mesa/main/version.c | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/mesa/main/version.c b/src/mesa/main/version.c
index 0a4e7630da..84babd69e2 100644
--- a/src/mesa/main/version.c
+++ b/src/mesa/main/version.c
@@ -620,8 +620,11 @@ _mesa_compute_version(struct gl_context *ctx)
/* Make sure that the GLSL version lines up with the GL version. In some
 * cases it can be too high, e.g. if an extension is missing.
 */
-   if (_mesa_is_desktop_gl(ctx) && ctx->Version >= 31) {
+   if (_mesa_is_desktop_gl(ctx)) {
   switch (ctx->Version) {
+  case 30:
+ ctx->Const.GLSLVersion = 130;
+ break;
   case 31:
  ctx->Const.GLSLVersion = 140;
  break;
@@ -629,7 +632,8 @@ _mesa_compute_version(struct gl_context *ctx)
  ctx->Const.GLSLVersion = 150;
  break;
   default:
- ctx->Const.GLSLVersion = ctx->Version * 10;
+ if (ctx->Version >= 33)
+ctx->Const.GLSLVersion = ctx->Version * 10;
  break;
   }
}

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Mesa (master): radv: add shader BOs to the list at pipeline bind time

2018-04-10 Thread Samuel Pitoiset

Module: Mesa
Branch: master
Commit: 9f6a28eb27ca059cbadfa5e277bfe4509a426615
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f6a28eb27ca059cbadfa5e277bfe4509a426615

Author: Samuel Pitoiset 
Date:   Tue Apr 10 14:09:04 2018 +0200

radv: add shader BOs to the list at pipeline bind time

Otherwise, the shader BOs are not added to the list on SI because
prefetching isn't supported. Calling radv_cs_add_buffer() in the
prefetch codepath was a bad idea.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105952
Fixes: 4ad7595f35 ("radv: rename radv_emit_prefetch() to radv_emit_prefetch_L2")
Signed-off-by: Samuel Pitoiset 
Tested-by: Turo Lamminen 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/amd/vulkan/radv_cmd_buffer.c | 18 +++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 4e89969016..3b1d6aedc8 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -625,8 +625,6 @@ static void
 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer,
  struct radv_shader_variant *shader)
 {
-   struct radeon_winsys *ws = cmd_buffer->device->ws;
-   struct radeon_winsys_cs *cs = cmd_buffer->cs;
uint64_t va;
 
if (!shader)
@@ -634,7 +632,6 @@ radv_emit_shader_prefetch(struct radv_cmd_buffer 
*cmd_buffer,
 
va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
 
-   radv_cs_add_buffer(ws, cs, shader->bo, 8);
si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);
 }
 
@@ -702,6 +699,18 @@ radv_emit_graphics_pipeline(struct radv_cmd_buffer 
*cmd_buffer)
 
radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);
 
+   for (unsigned i = 0; i < MESA_SHADER_COMPUTE; i++) {
+   if (!pipeline->shaders[i])
+   continue;
+
+   radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
+  pipeline->shaders[i]->bo, 8);
+   }
+
+   if (radv_pipeline_has_gs(pipeline))
+   radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
+  pipeline->gs_copy_shader->bo, 8);
+
if (unlikely(cmd_buffer->device->trace_bo))
radv_save_pipeline(cmd_buffer, pipeline, RING_GFX);
 
@@ -2280,6 +2289,9 @@ radv_emit_compute_pipeline(struct radv_cmd_buffer 
*cmd_buffer)
  MAX2(cmd_buffer->compute_scratch_size_needed,
   pipeline->max_waves * 
pipeline->scratch_bytes_per_wave);
 
+   radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,
+  pipeline->shaders[MESA_SHADER_COMPUTE]->bo, 8);
+
if (unlikely(cmd_buffer->device->trace_bo))
radv_save_pipeline(cmd_buffer, pipeline, RING_COMPUTE);
 }

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Mesa (master): radv: fix picking the method for resolve subpass

2018-04-10 Thread Samuel Pitoiset

Module: Mesa
Branch: master
Commit: 0babc8e5d665e54783c926b89183ab9a596aa04c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0babc8e5d665e54783c926b89183ab9a596aa04c

Author: Samuel Pitoiset 
Date:   Tue Apr 10 16:00:56 2018 +0200

radv: fix picking the method for resolve subpass

The source and destination image parameters were swapped.

No CTS changes on Polaris10, but I suspect this might
fix something.

Fixes: 2a04f5481df ("radv/meta: select resolve paths")
Signed-off-by: Samuel Pitoiset 
Reviewed-by: Bas Nieuwenhuizen 

---

 src/amd/vulkan/radv_meta_resolve.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_meta_resolve.c 
b/src/amd/vulkan/radv_meta_resolve.c
index bee398378c..e932976df2 100644
--- a/src/amd/vulkan/radv_meta_resolve.c
+++ b/src/amd/vulkan/radv_meta_resolve.c
@@ -621,7 +621,7 @@ radv_cmd_buffer_resolve_subpass(struct radv_cmd_buffer 
*cmd_buffer)
struct radv_image *dst_img = 
cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment->image;
struct radv_image *src_img = 
cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment->image;
 
-   radv_pick_resolve_method_images(dst_img, src_img, 
dest_att.layout, cmd_buffer, _method);
+   radv_pick_resolve_method_images(src_img, dst_img, 
dest_att.layout, cmd_buffer, _method);
if (resolve_method == RESOLVE_FRAGMENT) {
break;
}

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Mesa (master): ac/surface/gfx9: request desired micro tile mode explicitly

2018-04-10 Thread Marek Olšák

Module: Mesa
Branch: master
Commit: b64b7125586ce48232658cd860f549a6139b6ddd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b64b7125586ce48232658cd860f549a6139b6ddd

Author: Marek Olšák 
Date:   Mon Apr  2 12:54:52 2018 -0400

ac/surface/gfx9: request desired micro tile mode explicitly

Tested-by: Dieter Nützel 

---

 src/amd/common/ac_surface.c | 20 
 1 file changed, 16 insertions(+), 4 deletions(-)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 1e1641daee..b294cd8525 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -814,7 +814,8 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
 static int
 gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
ADDR2_COMPUTE_SURFACE_INFO_INPUT *in,
-   bool is_fmask, AddrSwizzleMode *swizzle_mode)
+   bool is_fmask, unsigned flags,
+   AddrSwizzleMode *swizzle_mode)
 {
ADDR_E_RETURNCODE ret;
ADDR2_GET_PREFERRED_SURF_SETTING_INPUT sin = {0};
@@ -839,6 +840,13 @@ gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
sin.numSamples = in->numSamples;
sin.numFrags = in->numFrags;
 
+   if (flags & RADEON_SURF_SCANOUT)
+   sin.preferredSwSet.sw_D = 1;
+   else if (in->flags.depth || in->flags.stencil || is_fmask)
+   sin.preferredSwSet.sw_Z = 1;
+   else
+   sin.preferredSwSet.sw_S = 1;
+
if (is_fmask) {
sin.flags.color = 0;
sin.flags.fmask = 1;
@@ -1036,7 +1044,9 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
fin.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_INPUT);
fout.size = sizeof(ADDR2_COMPUTE_FMASK_INFO_OUTPUT);
 
-   ret = gfx9_get_preferred_swizzle_mode(addrlib, in, 
true, );
+   ret = gfx9_get_preferred_swizzle_mode(addrlib, in,
+ true, surf->flags,
+ );
if (ret != ADDR_OK)
return ret;
 
@@ -1232,7 +1242,8 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
break;
}
 
-   r = gfx9_get_preferred_swizzle_mode(addrlib, , 
false,
+   r = gfx9_get_preferred_swizzle_mode(addrlib, ,
+   false, surf->flags,

);
if (r)
return r;
@@ -1268,7 +1279,8 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
AddrSurfInfoIn.format = ADDR_FMT_8;
 
if (!AddrSurfInfoIn.flags.depth) {
-   r = gfx9_get_preferred_swizzle_mode(addrlib, 
, false,
+   r = gfx9_get_preferred_swizzle_mode(addrlib, 
,
+   false, surf->flags,

);
if (r)
return r;

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Mesa (master): ac/surface: don't set the display flag for obviously unsupported cases (v2)

2018-04-10 Thread Marek Olšák

Module: Mesa
Branch: master
Commit: e29facff315ea63b8643766a45b3e56bf1dd8866
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e29facff315ea63b8643766a45b3e56bf1dd8866

Author: Marek Olšák 
Date:   Mon Apr  2 12:51:14 2018 -0400

ac/surface: don't set the display flag for obviously unsupported cases (v2)

This enables the tile swizzle for some cases of the displayable micro mode,
and it also fixes an addrlib assertion failure on Vega.

Reviewed-by: Michel Dänzer 

---

 src/amd/common/ac_surface.c| 34 +++---
 src/amd/common/ac_surface.h|  1 +
 src/amd/vulkan/radv_image.c|  1 +
 src/gallium/winsys/amdgpu/drm/amdgpu_surface.c |  1 +
 4 files changed, 33 insertions(+), 4 deletions(-)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index b294cd8525..1b4d72e31b 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -415,6 +415,31 @@ static unsigned cik_get_macro_tile_index(struct 
radeon_surf *surf)
return index;
 }
 
+static bool get_display_flag(const struct ac_surf_config *config,
+const struct radeon_surf *surf)
+{
+   unsigned num_channels = config->info.num_channels;
+   unsigned bpe = surf->bpe;
+
+   if (surf->flags & RADEON_SURF_SCANOUT &&
+   !(surf->flags & RADEON_SURF_FMASK) &&
+   config->info.samples <= 1 &&
+   surf->blk_w <= 2 && surf->blk_h == 1) {
+   /* subsampled */
+   if (surf->blk_w == 2 && surf->blk_h == 1)
+   return true;
+
+   if  (/* RGBA8 or RGBA16F */
+(bpe >= 4 && bpe <= 8 && num_channels == 4) ||
+/* R5G6B5 or R5G5B5A1 */
+(bpe == 2 && num_channels >= 3) ||
+/* C8 palette */
+(bpe == 1 && num_channels == 1))
+   return true;
+   }
+   return false;
+}
+
 /**
  * This must be called after the first level is computed.
  *
@@ -449,7 +474,7 @@ static int gfx6_surface_settings(ADDR_HANDLE addrlib,
config->info.surf_index &&
surf->u.legacy.level[0].mode == RADEON_SURF_MODE_2D &&
!(surf->flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_SHAREABLE)) 
&&
-   (config->info.samples > 1 || !(surf->flags & RADEON_SURF_SCANOUT))) 
{
+   !get_display_flag(config, surf)) {
ADDR_COMPUTE_BASE_SWIZZLE_INPUT AddrBaseSwizzleIn = {0};
ADDR_COMPUTE_BASE_SWIZZLE_OUTPUT AddrBaseSwizzleOut = {0};
 
@@ -568,7 +593,7 @@ static int gfx6_compute_surface(ADDR_HANDLE addrlib,
AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
AddrSurfInfoIn.flags.cube = config->is_cube;
AddrSurfInfoIn.flags.fmask = (surf->flags & RADEON_SURF_FMASK) != 0;
-   AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
+   AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
AddrSurfInfoIn.flags.pow2Pad = config->info.levels > 1;
AddrSurfInfoIn.flags.tcCompatible = (surf->flags & 
RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
 
@@ -848,6 +873,7 @@ gfx9_get_preferred_swizzle_mode(ADDR_HANDLE addrlib,
sin.preferredSwSet.sw_S = 1;
 
if (is_fmask) {
+   sin.flags.display = 0;
sin.flags.color = 0;
sin.flags.fmask = 1;
}
@@ -943,7 +969,7 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
in->swizzleMode >= ADDR_SW_64KB_Z_T &&
!out.mipChainInTail &&
!(surf->flags & RADEON_SURF_SHAREABLE) &&
-   (in->numSamples > 1 || !(surf->flags & 
RADEON_SURF_SCANOUT))) {
+   !in->flags.display) {
ADDR2_COMPUTE_PIPEBANKXOR_INPUT xin = {0};
ADDR2_COMPUTE_PIPEBANKXOR_OUTPUT xout = {0};
 
@@ -1196,7 +1222,7 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
 
AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
-   AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
+   AddrSurfInfoIn.flags.display = get_display_flag(config, surf);
/* flags.texture currently refers to TC-compatible HTILE */
AddrSurfInfoIn.flags.texture = AddrSurfInfoIn.flags.color ||
   surf->flags & 
RADEON_SURF_TC_COMPATIBLE_HTILE;
diff --git a/src/amd/common/ac_surface.h b/src/amd/common/ac_surface.h
index 71f320af8e..37df859e6d 100644
--- a/src/amd/common/ac_surface.h
+++ b/src/amd/common/ac_surface.h
@@ -219,6 +219,7 @@ struct ac_surf_info {
uint32_t depth;
uint8_t samples;
uint8_t levels;
+   uint8_t num_channels; /* heuristic for displayability */

Mesa (master): radeonsi: add shader binary padding for UMR

2018-04-10 Thread Marek Olšák

Module: Mesa
Branch: master
Commit: 19ce5048eedeac6584ae51f79658656ae53f0e05
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=19ce5048eedeac6584ae51f79658656ae53f0e05

Author: Marek Olšák 
Date:   Thu Apr  5 14:48:37 2018 -0400

radeonsi: add shader binary padding for UMR

---

 src/gallium/drivers/radeonsi/si_shader.c | 18 +++---
 1 file changed, 15 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index c18915488e..8c62d53e2a 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -5309,6 +5309,10 @@ void si_shader_apply_scratch_relocs(struct si_shader 
*shader,
}
 }
 
+/* For the UMR disassembler. */
+#define DEBUGGER_END_OF_CODE_MARKER0xbf9f /* invalid instruction */
+#define DEBUGGER_NUM_MARKERS   5
+
 static unsigned si_get_shader_binary_size(const struct si_shader *shader)
 {
unsigned size = shader->binary.code_size;
@@ -5321,7 +5325,7 @@ static unsigned si_get_shader_binary_size(const struct 
si_shader *shader)
size += shader->prolog2->binary.code_size;
if (shader->epilog)
size += shader->epilog->binary.code_size;
-   return size;
+   return size + DEBUGGER_NUM_MARKERS * 4;
 }
 
 int si_shader_binary_upload(struct si_screen *sscreen, struct si_shader 
*shader)
@@ -5380,10 +5384,18 @@ int si_shader_binary_upload(struct si_screen *sscreen, 
struct si_shader *shader)
memcpy(ptr, mainb->code, mainb->code_size);
ptr += mainb->code_size;
 
-   if (epilog)
+   if (epilog) {
memcpy(ptr, epilog->code, epilog->code_size);
-   else if (mainb->rodata_size > 0)
+   ptr += epilog->code_size;
+   } else if (mainb->rodata_size > 0) {
memcpy(ptr, mainb->rodata, mainb->rodata_size);
+   ptr += mainb->rodata_size;
+   }
+
+   /* Add end-of-code markers for the UMR disassembler. */
+   uint32_t *ptr32 = (uint32_t*)ptr;
+   for (unsigned i = 0; i < DEBUGGER_NUM_MARKERS; i++)
+   ptr32[i] = DEBUGGER_END_OF_CODE_MARKER;
 
sscreen->ws->buffer_unmap(shader->bo->buf);
return 0;

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Mesa (master): glsl: remove unreachable assert()

2018-04-10 Thread Emil Velikov

Module: Mesa
Branch: master
Commit: 8eceac9de7d3cd4fddabbe61d512acfed9812169
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8eceac9de7d3cd4fddabbe61d512acfed9812169

Author: Emil Velikov 
Date:   Wed Mar 28 18:21:59 2018 +0100

glsl: remove unreachable assert()

Earlier commit enforced that we'll bail out if the number of terminators
is different than 2. With that in mind, the assert() will never trigger.

Fixes: 56b867395de ("glsl: fix infinite loop caused by bug in loop
unrolling pass")
Reviewed-by: Timothy Arceri 
Signed-off-by: Emil Velikov 

---

 src/compiler/glsl/loop_unroll.cpp | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/compiler/glsl/loop_unroll.cpp 
b/src/compiler/glsl/loop_unroll.cpp
index f6efe6475a..874f418568 100644
--- a/src/compiler/glsl/loop_unroll.cpp
+++ b/src/compiler/glsl/loop_unroll.cpp
@@ -528,8 +528,6 @@ loop_unroll_visitor::visit_leave(ir_loop *ir)
unsigned term_count = 0;
bool first_term_then_continue = false;
foreach_in_list(loop_terminator, t, >terminators) {
-  assert(term_count < 2);
-
   ir_if *ir_if = t->ir->as_if();
   assert(ir_if != NULL);
 

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Mesa (master): docs/release-calendar: update to include 18.1 and 18.2

2018-04-10 Thread Emil Velikov

Module: Mesa
Branch: master
Commit: 5dd02123a05b9cb5ade38d412609df1062843209
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5dd02123a05b9cb5ade38d412609df1062843209

Author: Emil Velikov 
Date:   Mon Apr  9 17:45:52 2018 +0100

docs/release-calendar: update to include 18.1 and 18.2

Dylan has kindly stepped up to help with 18.1.0, while I've taken the
liberty to nominate Andres for 18.2.0 ;-)

As always, people are welcome to swap/adjust where needed.

v2: Add Juan for 18.0.x (Juan)

Cc: Andres Gomez 
Reviewed-by: Juan A. Suarez 
Acked-by: Dylan Baker  (v1)
Signed-off-by: Emil Velikov 

---

 docs/release-calendar.html | 88 +++---
 1 file changed, 84 insertions(+), 4 deletions(-)

diff --git a/docs/release-calendar.html b/docs/release-calendar.html
index 8f588ab46c..b363c822ea 100644
--- a/docs/release-calendar.html
+++ b/docs/release-calendar.html
@@ -43,27 +43,107 @@ if you'd like to nominate a patch in the next stable 
release.
 2018-04-06
 17.3.9
 Juan A. Suarez Romero
-Final planned release for the 17.3 series
+Last planned 17.3.x release
 
 
-18.0
+18.0
 2018-04-06
 18.0.1
-Andres Gomez
+Juan A. Suarez Romero
 
 
 
 2018-04-20
 18.0.2
-Andres Gomez
+Juan A. Suarez Romero
 
 
 
 2018-05-04
 18.0.3
+Juan A. Suarez Romero
+
+
+
+2018-05-18
+18.0.4
+Juan A. Suarez Romero
+Last planned 18.0.x release
+
+
+18.1
+2018-04-20
+18.1.0rc1
+Dylan Baker
+
+
+
+2018-04-27
+18.1.0rc2
+Dylan Baker
+
+
+
+2018-05-04
+18.1.0rc3
+Dylan Baker
+
+
+
+2018-05-11
+18.1.0rc4
+Dylan Baker
+Last planned RC/Final release
+
+
+TBD
+18.1.1
+Emil Velikov
+
+
+
+TBD
+18.1.2
+Emil Velikov
+
+
+
+TBD
+18.1.3
+Emil Velikov
+
+
+
+TBD
+18.1.4
+Emil Velikov
+Last planned RC/Final release
+
+
+18.2
+2018-07-20
+18.2.0rc1
 Andres Gomez
 
 
+
+2018-07-27
+18.2.0rc2
+Andres Gomez
+
+
+
+2018-08-03
+18.2.0rc3
+Andres Gomez
+
+
+
+2018-08-10
+18.2.0rc4
+Andres Gomez
+Last planned RC/Final release
+
 
 
 

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Mesa (master): spirv: autotools: add vtn_gather_types_c.py in distribution tarball

2018-04-10 Thread Juan Antonio Suárez Romero

Module: Mesa
Branch: master
Commit: 0d0ef8ae335bfe746bd5802eb9521986349db4b4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d0ef8ae335bfe746bd5802eb9521986349db4b4

Author: Juan A. Suarez Romero 
Date:   Mon Apr  9 13:50:46 2018 +0200

spirv: autotools: add vtn_gather_types_c.py in distribution tarball

Fixes: 042ee4bea26 "(spirv: Move SPIR-V building to Makefile.spirv.am and
spirv/meson.build")

Reviewed-by: Emil Velikov 

---

 src/compiler/Makefile.spirv.am | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/compiler/Makefile.spirv.am b/src/compiler/Makefile.spirv.am
index a9f90c26e7..2ac97f30ac 100644
--- a/src/compiler/Makefile.spirv.am
+++ b/src/compiler/Makefile.spirv.am
@@ -55,4 +55,5 @@ CLEANFILES += \
 
 EXTRA_DIST += \
spirv/spirv_info_c.py   \
-   spirv/spirv.core.grammar.json
+   spirv/spirv.core.grammar.json   \
+   spirv/vtn_gather_types_c.py

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Mesa (master): radeonsi: autotools: add si_build_pm4.h in dist tarball

2018-04-10 Thread Juan Antonio Suárez Romero

Module: Mesa
Branch: master
Commit: 15ed75783490e49fe636d58c3d2294a9a4f3b420
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=15ed75783490e49fe636d58c3d2294a9a4f3b420

Author: Juan A. Suarez Romero 
Date:   Mon Apr  9 14:07:34 2018 +0200

radeonsi: autotools: add si_build_pm4.h in dist tarball

Fixes: 5777488406c ("radeonsi: move r600_cs.h contents into si_pipe.h,
si_build_pm4.h")

Reviewed-by: Marek Olšák 
Reviewed-by: Emil Velikov 

---

 src/gallium/drivers/radeonsi/Makefile.sources | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/gallium/drivers/radeonsi/Makefile.sources 
b/src/gallium/drivers/radeonsi/Makefile.sources
index 6117005cbd..b20a5497f5 100644
--- a/src/gallium/drivers/radeonsi/Makefile.sources
+++ b/src/gallium/drivers/radeonsi/Makefile.sources
@@ -7,6 +7,7 @@ C_SOURCES := \
driinfo_radeonsi.h \
si_blit.c \
si_buffer.c \
+   si_build_pm4.h \
si_clear.c \
si_compute.c \
si_compute.h \

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Mesa (master): ac/nir: Use an array instead of hashtable for SSA defs.

2018-04-10 Thread Bas Nieuwenhuizen

Module: Mesa
Branch: master
Commit: 4381be4648b9ebb15b0a06885489998d5daac482
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4381be4648b9ebb15b0a06885489998d5daac482

Author: Bas Nieuwenhuizen 
Date:   Tue Apr 10 09:31:24 2018 +0200

ac/nir: Use an array instead of hashtable for SSA defs.

Saves about 2% of compile time for F1 2017, as well as reduce code
size of an optimized libvulkan_radeon.so by about 1 KiB.

This still keeps the hashtable, as we also stored blocks in there.

Reviewed-by: Samuel Pitoiset 

---

 src/amd/common/ac_nir_to_llvm.c | 22 +-
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 053c19808f..7c2bd5c0cc 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -38,6 +38,8 @@ struct ac_nir_context {
 
gl_shader_stage stage;
 
+   LLVMValueRef *ssa_defs;
+
struct hash_table *defs;
struct hash_table *phis;
struct hash_table *vars;
@@ -87,8 +89,7 @@ static LLVMTypeRef get_def_type(struct ac_nir_context *ctx,
 static LLVMValueRef get_src(struct ac_nir_context *nir, nir_src src)
 {
assert(src.is_ssa);
-   struct hash_entry *entry = _mesa_hash_table_search(nir->defs, src.ssa);
-   return (LLVMValueRef)entry->data;
+   return nir->ssa_defs[src.ssa->index];
 }
 
 static LLVMValueRef
@@ -1028,8 +1029,7 @@ static void visit_alu(struct ac_nir_context *ctx, const 
nir_alu_instr *instr)
if (result) {
assert(instr->dest.dest.is_ssa);
result = ac_to_integer(>ac, result);
-   _mesa_hash_table_insert(ctx->defs, >dest.dest.ssa,
-   result);
+   ctx->ssa_defs[instr->dest.dest.ssa.index] = result;
}
 }
 
@@ -1062,7 +1062,7 @@ static void visit_load_const(struct ac_nir_context *ctx,
} else
value = values[0];
 
-   _mesa_hash_table_insert(ctx->defs, >def, value);
+   ctx->ssa_defs[instr->def.index] = value;
 }
 
 static LLVMValueRef
@@ -3095,7 +3095,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
break;
}
if (result) {
-   _mesa_hash_table_insert(ctx->defs, >dest.ssa, result);
+   ctx->ssa_defs[instr->dest.ssa.index] = result;
}
 }
 
@@ -3596,7 +3596,7 @@ write_result:
if (result) {
assert(instr->dest.is_ssa);
result = ac_to_integer(>ac, result);
-   _mesa_hash_table_insert(ctx->defs, >dest.ssa, result);
+   ctx->ssa_defs[instr->dest.ssa.index] = result;
}
 }
 
@@ -3606,7 +3606,7 @@ static void visit_phi(struct ac_nir_context *ctx, 
nir_phi_instr *instr)
LLVMTypeRef type = get_def_type(ctx, >dest.ssa);
LLVMValueRef result = LLVMBuildPhi(ctx->ac.builder, type, "");
 
-   _mesa_hash_table_insert(ctx->defs, >dest.ssa, result);
+   ctx->ssa_defs[instr->dest.ssa.index] = result;
_mesa_hash_table_insert(ctx->phis, instr, result);
 }
 
@@ -3644,7 +3644,7 @@ static void visit_ssa_undef(struct ac_nir_context *ctx,
else {
undef = LLVMGetUndef(LLVMVectorType(type, num_components));
}
-   _mesa_hash_table_insert(ctx->defs, >def, undef);
+   ctx->ssa_defs[instr->def.index] = undef;
 }
 
 static void visit_jump(struct ac_llvm_context *ctx,
@@ -3927,6 +3927,9 @@ void ac_nir_translate(struct ac_llvm_context *ac, struct 
ac_shader_abi *abi,
 
func = (struct nir_function *)exec_list_get_head(>functions);
 
+   nir_index_ssa_defs(func->impl);
+   ctx.ssa_defs = calloc(func->impl->ssa_alloc, sizeof(LLVMValueRef));
+
setup_locals(, func);
 
if (nir->info.stage == MESA_SHADER_COMPUTE)
@@ -3940,6 +3943,7 @@ void ac_nir_translate(struct ac_llvm_context *ac, struct 
ac_shader_abi *abi,
  ctx.abi->outputs);
 
free(ctx.locals);
+   free(ctx.ssa_defs);
ralloc_free(ctx.defs);
ralloc_free(ctx.phis);
ralloc_free(ctx.vars);

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Mesa (master): ac/nir: Use an array instead of hashtable for SSA defs.

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