Mesa (master): st/nir: make st_nir_opts() available externally
Module: Mesa
Branch: master
Commit: 0b3e9564bdda575c3956f338454f4f632041e151
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b3e9564bdda575c3956f338454f4f632041e151
Author: Timothy Arceri
Date: Wed May 9 13:25:46 2018 +1000
st/nir: make st_nir_opts() available externally
The following patch will make use of this for asm style programs.
Reviewed-by: Eric Anholt
---
src/mesa/state_tracker/st_glsl_to_nir.cpp | 2 +-
src/mesa/state_tracker/st_nir.h | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 3b261cf1b2..de906e60c3 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -314,7 +314,7 @@ st_nir_assign_uniform_locations(struct gl_context *ctx,
*size = max;
}
-static void
+void
st_nir_opts(nir_shader *nir)
{
bool progress;
diff --git a/src/mesa/state_tracker/st_nir.h b/src/mesa/state_tracker/st_nir.h
index 1c2e32a5e6..15f1ce93e5 100644
--- a/src/mesa/state_tracker/st_nir.h
+++ b/src/mesa/state_tracker/st_nir.h
@@ -42,6 +42,8 @@ void st_finalize_nir(struct st_context *st, struct gl_program
*prog,
struct gl_shader_program *shader_program,
struct nir_shader *nir);
+void st_nir_opts(struct nir_shader *nir);
+
bool
st_link_nir(struct gl_context *ctx,
struct gl_shader_program *shader_program);
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Mesa (master): st/nir: use NIR for asm programs
Module: Mesa
Branch: master
Commit: 5c33e8c7729edd5e16020ebb8703be96523e04f2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c33e8c7729edd5e16020ebb8703be96523e04f2
Author: Timothy Arceri
Date: Wed May 9 13:28:05 2018 +1000
st/nir: use NIR for asm programs
Reviewed-by: Eric Anholt
---
src/mesa/state_tracker/st_program.c | 65 +
1 file changed, 58 insertions(+), 7 deletions(-)
diff --git a/src/mesa/state_tracker/st_program.c
b/src/mesa/state_tracker/st_program.c
index f256e2e862..a52c9f8256 100644
--- a/src/mesa/state_tracker/st_program.c
+++ b/src/mesa/state_tracker/st_program.c
@@ -37,6 +37,7 @@
#include "main/mtypes.h"
#include "program/prog_parameter.h"
#include "program/prog_print.h"
+#include "program/prog_to_nir.h"
#include "program/programopt.h"
#include "compiler/nir/nir.h"
@@ -378,6 +379,28 @@ st_release_cp_variants(struct st_context *st, struct
st_compute_program *stcp)
}
/**
+ * Translate ARB (asm) program to NIR
+ */
+static nir_shader *
+st_translate_prog_to_nir(struct st_context *st, struct gl_program *prog,
+ gl_shader_stage stage)
+{
+ const struct gl_shader_compiler_options *options =
+ &st->ctx->Const.ShaderCompilerOptions[stage];
+
+ /* Translate to NIR */
+ nir_shader *nir = prog_to_nir(prog, options->NirOptions);
+ NIR_PASS_V(nir, nir_lower_regs_to_ssa); /* turn registers into SSA */
+ nir_validate_shader(nir);
+
+ /* Optimise NIR */
+ st_nir_opts(nir);
+ nir_validate_shader(nir);
+
+ return nir;
+}
+
+/**
* Translate a vertex program.
*/
bool
@@ -458,15 +481,28 @@ st_translate_vertex_program(struct st_context *st,
/* No samplers are allowed in ARB_vp. */
}
- if (stvp->shader_program) {
- struct gl_program *prog = stvp->shader_program->last_vert_prog;
- if (prog) {
- st_translate_stream_output_info2(prog->sh.LinkedTransformFeedback,
- stvp->result_to_output,
- &stvp->tgsi.stream_output);
+ enum pipe_shader_ir preferred_ir = (enum pipe_shader_ir)
+ st->pipe->screen->get_shader_param(st->pipe->screen, PIPE_SHADER_VERTEX,
+ PIPE_SHADER_CAP_PREFERRED_IR);
+
+ if (preferred_ir == PIPE_SHADER_IR_NIR) {
+ if (stvp->shader_program) {
+ struct gl_program *prog = stvp->shader_program->last_vert_prog;
+ if (prog) {
+st_translate_stream_output_info2(prog->sh.LinkedTransformFeedback,
+ stvp->result_to_output,
+ &stvp->tgsi.stream_output);
+ }
+
+ st_store_ir_in_disk_cache(st, &stvp->Base, true);
+ } else {
+ nir_shader *nir = st_translate_prog_to_nir(st, &stvp->Base,
+MESA_SHADER_VERTEX);
+
+ stvp->tgsi.type = PIPE_SHADER_IR_NIR;
+ stvp->tgsi.ir.nir = nir;
}
- st_store_ir_in_disk_cache(st, &stvp->Base, true);
return true;
}
@@ -706,6 +742,21 @@ st_translate_fragment_program(struct st_context *st,
}
}
+ enum pipe_shader_ir preferred_ir = (enum pipe_shader_ir)
+ st->pipe->screen->get_shader_param(st->pipe->screen,
+ PIPE_SHADER_FRAGMENT,
+ PIPE_SHADER_CAP_PREFERRED_IR);
+
+ if (preferred_ir == PIPE_SHADER_IR_NIR) {
+ nir_shader *nir = st_translate_prog_to_nir(st, &stfp->Base,
+ MESA_SHADER_FRAGMENT);
+
+ stfp->tgsi.type = PIPE_SHADER_IR_NIR;
+ stfp->tgsi.ir.nir = nir;
+
+ return true;
+ }
+
/*
* Convert Mesa program inputs to TGSI input register semantics.
*/
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Mesa: tag mesa-18.1.0-rc4: mesa-18.1.0-rc4
Module: Mesa Branch: refs/tags/mesa-18.1.0-rc4 Tag:a428d00619069fd307efdfe557c6cb649cd87c99 URL: http://cgit.freedesktop.org/mesa/mesa/tag/?id=a428d00619069fd307efdfe557c6cb649cd87c99 Tagger: Dylan Baker Date: Fri May 11 16:29:28 2018 -0700 mesa-18.1.0-rc4 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeon/vce: add firmware support for ver 53 and up
Module: Mesa
Branch: master
Commit: 0907d3ab9c61ee1fc841aaf22fb4a5ab38633a0c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0907d3ab9c61ee1fc841aaf22fb4a5ab38633a0c
Author: Boyuan Zhang
Date: Tue May 8 14:35:06 2018 -0400
radeon/vce: add firmware support for ver 53 and up
All vce firmwares with major version greater than or equal to 53 are supported
Signed-off-by: Boyuan Zhang
Reviewed-by: Leo Liu
---
src/gallium/drivers/radeon/radeon_vce.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_vce.c
b/src/gallium/drivers/radeon/radeon_vce.c
index 22168b50e2..6d1b1ff787 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -506,7 +506,7 @@ struct pipe_video_codec *si_vce_create_encoder(struct
pipe_context *context,
break;
default:
- if ((sscreen->info.vce_fw_version & (0xff << 24)) == FW_53) {
+ if ((sscreen->info.vce_fw_version & (0xff << 24)) >= FW_53) {
si_vce_52_init(enc);
si_get_pic_param = si_vce_52_get_param;
} else
@@ -542,7 +542,7 @@ bool si_vce_is_fw_version_supported(struct si_screen
*sscreen)
case FW_52_8_3:
return true;
default:
- if ((sscreen->info.vce_fw_version & (0xff << 24)) == FW_53)
+ if ((sscreen->info.vce_fw_version & (0xff << 24)) >= FW_53)
return true;
else
return false;
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Mesa (master): etnaviv: remove pipe_fence_handle::ctx
Module: Mesa
Branch: master
Commit: a7c81a7f676618723de547b71d57eb3781147ba2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7c81a7f676618723de547b71d57eb3781147ba2
Author: Rob Clark
Date: Tue May 8 21:00:18 2018 -0400
etnaviv: remove pipe_fence_handle::ctx
A fence can outlive the ctx it was created from (see glmark2).. etnaviv
doesn't actually need fence->ctx so lets remove it before someone makes
the mistake of assuming it is a valid pointer.
Signed-off-by: Rob Clark
Reviewed-by: Christian Gmeiner
---
src/gallium/drivers/etnaviv/etnaviv_fence.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/gallium/drivers/etnaviv/etnaviv_fence.c
b/src/gallium/drivers/etnaviv/etnaviv_fence.c
index 22a964ad28..cf3e67766b 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_fence.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_fence.c
@@ -36,7 +36,6 @@
struct pipe_fence_handle {
struct pipe_reference reference;
- struct etna_context *ctx;
struct etna_screen *screen;
int fence_fd;
uint32_t timestamp;
@@ -111,7 +110,6 @@ etna_fence_create(struct pipe_context *pctx, int fence_fd)
pipe_reference_init(&fence->reference, 1);
- fence->ctx = ctx;
fence->screen = ctx->screen;
fence->timestamp = etna_cmd_stream_timestamp(ctx->stream);
fence->fence_fd = fence_fd;
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Mesa (master): swr/rast: Prepend the console output with a newline
Module: Mesa
Branch: master
Commit: 8cb55dae2e796445635303f03a0e1e6c01a767d5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8cb55dae2e796445635303f03a0e1e6c01a767d5
Author: George Kyriazis
Date: Mon Apr 30 17:45:55 2018 -0500
swr/rast: Prepend the console output with a newline
It can get jumbled with output from other threads.
Reviewed-by: Bruce Cherniak
---
.../swr/rasterizer/codegen/templates/gen_ar_eventhandlerfile.hpp| 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
a/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_ar_eventhandlerfile.hpp
b/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_ar_eventhandlerfile.hpp
index ceded82b73..79612f3120 100644
---
a/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_ar_eventhandlerfile.hpp
+++
b/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_ar_eventhandlerfile.hpp
@@ -59,7 +59,7 @@ namespace ArchRast
outDir << KNOB_DEBUG_OUTPUT_DIR << pBaseName << "_" << pid <<
std::ends;
mOutputDir = outDir.str();
if (CreateDirectory(mOutputDir.c_str(), NULL)) {
-std::cout << "ArchRast Dir: " << mOutputDir << std::endl
<< std::endl << std::flush;
+std::cout << std::endl << "ArchRast Dir: " << mOutputDir
<< std::endl << std::endl << std::flush;
}
// There could be multiple threads creating thread pools. We
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Mesa (master): swr/rast: Add ConcatLists()
Module: Mesa Branch: master Commit: db25fcfcdebe96d65f62692d4f0729dcee6ee2e0 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=db25fcfcdebe96d65f62692d4f0729dcee6ee2e0 Author: George Kyriazis Date: Fri Apr 27 18:05:00 2018 -0500 swr/rast: Add ConcatLists() for concatenating lists Reviewed-by: Bruce Cherniak --- src/gallium/drivers/swr/rasterizer/codegen/gen_common.py | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/gallium/drivers/swr/rasterizer/codegen/gen_common.py b/src/gallium/drivers/swr/rasterizer/codegen/gen_common.py index 44a0cc88e3..60b749d3ab 100644 --- a/src/gallium/drivers/swr/rasterizer/codegen/gen_common.py +++ b/src/gallium/drivers/swr/rasterizer/codegen/gen_common.py @@ -32,6 +32,12 @@ from mako.template import Template from mako.exceptions import RichTraceback #== +def ConcatLists(list_of_lists): +output = [] +for l in list_of_lists: output += l +return output + +#== def MakeTmpDir(suffix=''): ''' Create temporary directory for use in codegen scripts. ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): swr/rast: Change formatting
Module: Mesa
Branch: master
Commit: b3b0f0e0ec98d1da42554764adc17402535fa0b7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3b0f0e0ec98d1da42554764adc17402535fa0b7
Author: George Kyriazis
Date: Wed Apr 25 22:20:01 2018 -0500
swr/rast: Change formatting
Reviewed-by: Bruce Cherniak
---
src/gallium/drivers/swr/rasterizer/core/api.cpp | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/swr/rasterizer/core/api.cpp
b/src/gallium/drivers/swr/rasterizer/core/api.cpp
index a2ee85d12b..3458793fd8 100644
--- a/src/gallium/drivers/swr/rasterizer/core/api.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/api.cpp
@@ -475,7 +475,12 @@ void SetupDefaultState(SWR_CONTEXT *pContext)
pState->depthBoundsState.depthBoundsTestMaxValue = 1.0f;
}
-void SwrSync(HANDLE hContext, PFN_CALLBACK_FUNC pfnFunc, uint64_t userData,
uint64_t userData2, uint64_t userData3)
+void SWR_API SwrSync(
+HANDLE hContext,
+PFN_CALLBACK_FUNC pfnFunc,
+uint64_t userData,
+uint64_t userData2,
+uint64_t userData3)
{
SWR_ASSERT(pfnFunc != nullptr);
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Mesa (master): swr/rast: Use binner topology to assemble backend attributes
Module: Mesa
Branch: master
Commit: 70f0a28b83d9977e106f80cfd033e0796bc43f2f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=70f0a28b83d9977e106f80cfd033e0796bc43f2f
Author: George Kyriazis
Date: Thu Apr 26 16:12:24 2018 -0500
swr/rast: Use binner topology to assemble backend attributes
Previously was using the draw topology, which may change if GS or Tess
are active. Only affected attributes marked with constant interpolation,
which limited the impact.
Reviewed-by: Bruce Cherniak
---
src/gallium/drivers/swr/rasterizer/core/binner.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/swr/rasterizer/core/binner.cpp
b/src/gallium/drivers/swr/rasterizer/core/binner.cpp
index 9f8dc887aa..7b9c20ef80 100644
--- a/src/gallium/drivers/swr/rasterizer/core/binner.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/binner.cpp
@@ -81,7 +81,7 @@ INLINE void ProcessAttributes(
// Conservative Rasterization requires degenerate tris to have constant
attribute interpolation
uint32_t constantInterpMask = IsDegenerate::value ? 0x :
backendState.constantInterpolationMask;
const uint32_t provokingVertex =
pDC->pState->state.frontendState.topologyProvokingVertex;
-const PRIMITIVE_TOPOLOGY topo = pDC->pState->state.topology;
+const PRIMITIVE_TOPOLOGY topo = pa.binTopology;
static const float constTable[3][4] = {
{ 0.0f, 0.0f, 0.0f, 0.0f },
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Mesa (master): swr/rast: Add Builder::GetVectorType()
Module: Mesa
Branch: master
Commit: 8238c791dcd244c5d242b0e61cbc744ed64e5e23
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8238c791dcd244c5d242b0e61cbc744ed64e5e23
Author: George Kyriazis
Date: Tue May 1 16:33:19 2018 -0500
swr/rast: Add Builder::GetVectorType()
Reviewed-by: Bruce Cherniak
---
.../drivers/swr/rasterizer/jitter/builder.cpp | 44 ++
.../drivers/swr/rasterizer/jitter/builder.h| 1 +
2 files changed, 45 insertions(+)
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder.cpp
b/src/gallium/drivers/swr/rasterizer/jitter/builder.cpp
index 32487353f8..e1c5d80c80 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/builder.cpp
+++ b/src/gallium/drivers/swr/rasterizer/jitter/builder.cpp
@@ -170,4 +170,48 @@ namespace SwrJit
return (pGenIntrin->getMetadata("is_evaluate") != nullptr);
}
+//
+/// @brief Packetizes the type. Assumes SOA conversion.
+Type* Builder::GetVectorType(Type* pType)
+{
+if (pType->isVectorTy())
+{
+return pType;
+}
+
+// [N x float] should packetize to [N x <8 x float>]
+if (pType->isArrayTy())
+{
+uint32_t arraySize = pType->getArrayNumElements();
+Type* pArrayType = pType->getArrayElementType();
+Type* pVecArrayType = GetVectorType(pArrayType);
+Type* pVecType = ArrayType::get(pVecArrayType, arraySize);
+return pVecType;
+}
+
+// {float,int} should packetize to {<8 x float>, <8 x int>}
+if (pType->isAggregateType())
+{
+uint32_t numElems = pType->getStructNumElements();
+SmallVector vecTypes;
+for (uint32_t i = 0; i < numElems; ++i)
+{
+Type* pElemType = pType->getStructElementType(i);
+Type* pVecElemType = GetVectorType(pElemType);
+vecTypes.push_back(pVecElemType);
+}
+Type* pVecType = StructType::get(JM()->mContext, vecTypes);
+return pVecType;
+}
+
+// [N x float]* should packetize to [N x <8 x float>]*
+if (pType->isPointerTy() &&
pType->getPointerElementType()->isArrayTy())
+{
+return
PointerType::get(GetVectorType(pType->getPointerElementType()),
pType->getPointerAddressSpace());
+}
+
+// should packetize to <8 x >
+Type* vecType = VectorType::get(pType, JM()->mVWidth);
+return vecType;
+}
}
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder.h
b/src/gallium/drivers/swr/rasterizer/jitter/builder.h
index 82c5f8cde2..6ca128d38f 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/builder.h
+++ b/src/gallium/drivers/swr/rasterizer/jitter/builder.h
@@ -123,6 +123,7 @@ namespace SwrJit
bool IsTempAlloca(Value* inst);
bool SetTexelMaskEvaluate(Instruction* inst);
bool IsTexelMaskEvaluate(Instruction* inst);
+Type* GetVectorType(Type* pType);
#include "gen_builder.hpp"
#include "gen_builder_meta.hpp"
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Mesa (master): swr/rast: Add constant initializer for uint64_t
Module: Mesa
Branch: master
Commit: dcaca3c7b34f4b9c150860cde19c8f21d13bf51f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dcaca3c7b34f4b9c150860cde19c8f21d13bf51f
Author: George Kyriazis
Date: Thu Apr 26 19:29:40 2018 -0500
swr/rast: Add constant initializer for uint64_t
Reviewed-by: Bruce Cherniak
---
src/gallium/drivers/swr/rasterizer/jitter/builder_misc.cpp | 5 +
src/gallium/drivers/swr/rasterizer/jitter/builder_misc.h | 1 +
2 files changed, 6 insertions(+)
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder_misc.cpp
b/src/gallium/drivers/swr/rasterizer/jitter/builder_misc.cpp
index 619a67beba..231fa94d00 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/builder_misc.cpp
+++ b/src/gallium/drivers/swr/rasterizer/jitter/builder_misc.cpp
@@ -182,6 +182,11 @@ namespace SwrJit
return ConstantInt::get(IRB()->getInt32Ty(), i);
}
+Constant *Builder::C(uint64_t i)
+{
+return ConstantInt::get(IRB()->getInt64Ty(), i);
+}
+
Constant *Builder::C(float i)
{
return ConstantFP::get(IRB()->getFloatTy(), i);
diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder_misc.h
b/src/gallium/drivers/swr/rasterizer/jitter/builder_misc.h
index a51aad05a0..d7732ef8c2 100644
--- a/src/gallium/drivers/swr/rasterizer/jitter/builder_misc.h
+++ b/src/gallium/drivers/swr/rasterizer/jitter/builder_misc.h
@@ -34,6 +34,7 @@ Constant *C(char i);
Constant *C(uint8_t i);
Constant *C(int i);
Constant *C(int64_t i);
+Constant *C(uint64_t i);
Constant *C(uint16_t i);
Constant *C(uint32_t i);
Constant *C(float i);
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Mesa (master): swr/rast: Thread locked tiles improvement
Module: Mesa
Branch: master
Commit: 4e52cb51b56eaae7153394ed712f49ce0ba63bcc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e52cb51b56eaae7153394ed712f49ce0ba63bcc
Author: George Kyriazis
Date: Tue May 1 19:33:38 2018 -0500
swr/rast: Thread locked tiles improvement
- Change tilemgr TILE_ID encoding to use Morton-order (Z-order).
- Change locked tiles set to bitset. Makes clear, set, get much faster.
Reviewed-by: Bruce Cherniak
---
src/gallium/drivers/swr/rasterizer/core/api.cpp| 11 ++-
src/gallium/drivers/swr/rasterizer/core/context.h | 2 +-
.../drivers/swr/rasterizer/core/threads.cpp| 5 +-
src/gallium/drivers/swr/rasterizer/core/threads.h | 2 +-
.../drivers/swr/rasterizer/core/tilemgr.cpp| 31 +++---
src/gallium/drivers/swr/rasterizer/core/tilemgr.h | 20 ++--
src/gallium/drivers/swr/rasterizer/core/tileset.h | 105 +
7 files changed, 152 insertions(+), 24 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/core/api.cpp
b/src/gallium/drivers/swr/rasterizer/core/api.cpp
index 3458793fd8..47f3633d54 100644
--- a/src/gallium/drivers/swr/rasterizer/core/api.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/api.cpp
@@ -42,6 +42,7 @@
#include "core/tilemgr.h"
#include "core/clip.h"
#include "core/utils.h"
+#include "core/tileset.h"
#include "common/os.h"
@@ -139,6 +140,11 @@ HANDLE SwrCreateContext(
BindApiThread(pContext, 0);
}
+if (pContext->threadInfo.SINGLE_THREADED)
+{
+pContext->pSingleThreadLockedTiles = new TileSet();
+}
+
pContext->ppScratch = new uint8_t*[pContext->NumWorkerThreads];
pContext->pStats = (SWR_STATS*)AlignedMalloc(sizeof(SWR_STATS) *
pContext->NumWorkerThreads, 64);
@@ -245,7 +251,7 @@ void QueueWork(SWR_CONTEXT *pContext)
{
uint32_t curDraw[2] = { pContext->pCurDrawContext->drawId,
pContext->pCurDrawContext->drawId };
WorkOnFifoFE(pContext, 0, curDraw[0]);
-WorkOnFifoBE(pContext, 0, curDraw[1],
pContext->singleThreadLockedTiles, 0, 0);
+WorkOnFifoBE(pContext, 0, curDraw[1],
*pContext->pSingleThreadLockedTiles, 0, 0);
}
else
{
@@ -427,7 +433,8 @@ void SwrDestroyContext(HANDLE hContext)
delete[] pContext->ppScratch;
AlignedFree(pContext->pStats);
-delete(pContext->pHotTileMgr);
+delete pContext->pHotTileMgr;
+delete pContext->pSingleThreadLockedTiles;
pContext->~SWR_CONTEXT();
AlignedFree(GetContext(hContext));
diff --git a/src/gallium/drivers/swr/rasterizer/core/context.h
b/src/gallium/drivers/swr/rasterizer/core/context.h
index af8f4b8db4..2cd61e4abb 100644
--- a/src/gallium/drivers/swr/rasterizer/core/context.h
+++ b/src/gallium/drivers/swr/rasterizer/core/context.h
@@ -516,7 +516,7 @@ struct SWR_CONTEXT
uint32_t lastFrameChecked;
uint64_t lastDrawChecked;
-TileSet singleThreadLockedTiles;
+TileSet* pSingleThreadLockedTiles;
// ArchRast thread contexts.
HANDLE* pArContext;
diff --git a/src/gallium/drivers/swr/rasterizer/core/threads.cpp
b/src/gallium/drivers/swr/rasterizer/core/threads.cpp
index 9e16246c3f..f77ae22a80 100644
--- a/src/gallium/drivers/swr/rasterizer/core/threads.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/threads.cpp
@@ -49,6 +49,7 @@
#include "rasterizer.h"
#include "rdtsc_core.h"
#include "tilemgr.h"
+#include "tileset.h"
@@ -587,7 +588,7 @@ bool WorkOnFifoBE(
}
// can only work on this draw if it's not in use by other threads
-if (lockedTiles.find(tileID) != lockedTiles.end())
+if (lockedTiles.get(tileID))
{
continue;
}
@@ -645,7 +646,7 @@ bool WorkOnFifoBE(
else
{
// This tile is already locked. So let's add it to our locked
tiles set. This way we don't try locking this one again.
-lockedTiles.insert(tileID);
+lockedTiles.set(tileID);
}
}
}
diff --git a/src/gallium/drivers/swr/rasterizer/core/threads.h
b/src/gallium/drivers/swr/rasterizer/core/threads.h
index cb918ddb60..0489a3cc6c 100644
--- a/src/gallium/drivers/swr/rasterizer/core/threads.h
+++ b/src/gallium/drivers/swr/rasterizer/core/threads.h
@@ -62,7 +62,7 @@ struct THREAD_POOL
THREAD_DATA *pApiThreadData;
};
-typedef std::unordered_set TileSet;
+struct TileSet;
void CreateThreadPool(SWR_CONTEXT *pContext, THREAD_POOL *pPool);
void StartThreadPool(SWR_CONTEXT* pContext, THREAD_POOL* pPool);
diff --git a/src/gallium/drivers/swr/rasterizer/core/tilemgr.cpp
b/src/gallium/drivers/swr/rasterizer/core/tilemgr.cpp
index 28fa787711..1bdef4bd7d 100644
--- a/src/gallium/drivers/swr/rasterizer/core/tilemgr.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/tilemgr.cpp
@@ -33,8 +33,6 @@
#include "core/multisample.h"
#include "rdtsc_core.h"
-#define TILE_ID(x,y) ((x << 16 | y))
-
MacroTileMgr
Mesa (18.1): winsys/amdgpu: Destroy dev_hash table when the last winsys is removed.
Module: Mesa
Branch: 18.1
Commit: 36c24a608e81307e7abbc60f2e397bd1fe514fb4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=36c24a608e81307e7abbc60f2e397bd1fe514fb4
Author: Jan Vesely
Date: Thu May 10 18:29:13 2018 -0400
winsys/amdgpu: Destroy dev_hash table when the last winsys is removed.
Fixes memory leak on module unload.
CC:
Signed-off-by: Jan Vesely
Reviewed-by: Marek Olšák
(cherry picked from commit 58272c1ad771802a6f15a482ae552649e9085042)
---
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index f4bbd3e732..84d8ca6fcf 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -220,8 +220,13 @@ static bool amdgpu_winsys_unref(struct radeon_winsys *rws)
simple_mtx_lock(&dev_tab_mutex);
destroy = pipe_reference(&ws->reference, NULL);
- if (destroy && dev_tab)
+ if (destroy && dev_tab) {
util_hash_table_remove(dev_tab, ws->dev);
+ if (util_hash_table_count(dev_tab) == 0) {
+ util_hash_table_destroy(dev_tab);
+ dev_tab = NULL;
+ }
+ }
simple_mtx_unlock(&dev_tab_mutex);
return destroy;
___
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Mesa (18.1): radeonsi/gfx9: work around a GPU hang due to broken indirect indexing in LLVM
Module: Mesa Branch: 18.1 Commit: 1def4eaa5c29a7b25d626a37d55f1541273cf336 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1def4eaa5c29a7b25d626a37d55f1541273cf336 Author: Marek Olšák Date: Tue May 1 20:16:19 2018 -0400 radeonsi/gfx9: work around a GPU hang due to broken indirect indexing in LLVM Fixes: 6d19120da85 "radeonsi/gfx9: workaround for INTERP with indirect indexing" Cc: 18.1 Reviewed-by: Nicolai Hähnle (cherry picked from commit 597b9e881083533b987dbcbb8f679ca1eefff974) --- src/gallium/drivers/radeonsi/si_get.c | 9 + 1 file changed, 9 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_get.c b/src/gallium/drivers/radeonsi/si_get.c index 04ab0f46bb..6bfbc4d0c4 100644 --- a/src/gallium/drivers/radeonsi/si_get.c +++ b/src/gallium/drivers/radeonsi/si_get.c @@ -484,6 +484,15 @@ static int si_get_shader_param(struct pipe_screen* pscreen, !sscreen->llvm_has_working_vgpr_indexing) return 0; + /* Doing indirect indexing on GFX9 with LLVM 6.0 hangs. +* This means we don't support INTERP instructions with +* indirect indexing on inputs. +*/ + if (shader == PIPE_SHADER_FRAGMENT && + !sscreen->llvm_has_working_vgpr_indexing && + HAVE_LLVM < 0x0700) + return 0; + /* TCS and TES load inputs directly from LDS or offchip * memory, so indirect indexing is always supported. * PS has to support indirect indexing, because we can't ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (18.1): mesa: revert GL_[SECONDARY_]COLOR_ARRAY_SIZE glGet type to TYPE_INT
Module: Mesa
Branch: 18.1
Commit: 421aedcc5932d2dc23fb18b721d1bbb2180c02d2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=421aedcc5932d2dc23fb18b721d1bbb2180c02d2
Author: Brian Paul
Date: Thu May 10 09:24:20 2018 -0600
mesa: revert GL_[SECONDARY_]COLOR_ARRAY_SIZE glGet type to TYPE_INT
Since size can be 3, 4 or GL_BGRA we need to keep these glGet types
as TYPE_INT, not TYPE_UBYTE.
Fixes: d07466fe18522 ("mesa: fix glGetInteger/Float/etc queries for
vertex arrays attribs")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106462
cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Mathias Fröhlich
(cherry picked from commit e4211b36bba4acde3e56ce1e22b12759e820a241)
---
src/mesa/main/get_hash_params.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/get_hash_params.py b/src/mesa/main/get_hash_params.py
index 62245693e7..4af12d4309 100644
--- a/src/mesa/main/get_hash_params.py
+++ b/src/mesa/main/get_hash_params.py
@@ -219,7 +219,7 @@ descriptor=[
[ "NORMAL_ARRAY_TYPE", "ARRAY_ENUM16(VertexAttrib[VERT_ATTRIB_NORMAL].Type),
NO_EXTRA" ],
[ "NORMAL_ARRAY_STRIDE",
"ARRAY_SHORT(VertexAttrib[VERT_ATTRIB_NORMAL].Stride), NO_EXTRA" ],
[ "COLOR_ARRAY", "ARRAY_BOOL(VertexAttrib[VERT_ATTRIB_COLOR0].Enabled),
NO_EXTRA" ],
- [ "COLOR_ARRAY_SIZE", "LOC_CUSTOM, TYPE_UBYTE, 0, NO_EXTRA" ],
+ [ "COLOR_ARRAY_SIZE", "LOC_CUSTOM, TYPE_INT, 0, NO_EXTRA" ],
[ "COLOR_ARRAY_TYPE", "ARRAY_ENUM16(VertexAttrib[VERT_ATTRIB_COLOR0].Type),
NO_EXTRA" ],
[ "COLOR_ARRAY_STRIDE",
"ARRAY_SHORT(VertexAttrib[VERT_ATTRIB_COLOR0].Stride), NO_EXTRA" ],
[ "TEXTURE_COORD_ARRAY", "LOC_CUSTOM, TYPE_BOOLEAN, offsetof(struct
gl_array_attributes, Enabled), NO_EXTRA" ],
@@ -812,7 +812,7 @@ descriptor=[
[ "SECONDARY_COLOR_ARRAY",
"ARRAY_BOOL(VertexAttrib[VERT_ATTRIB_COLOR1].Enabled), NO_EXTRA" ],
[ "SECONDARY_COLOR_ARRAY_TYPE",
"ARRAY_ENUM16(VertexAttrib[VERT_ATTRIB_COLOR1].Type), NO_EXTRA" ],
[ "SECONDARY_COLOR_ARRAY_STRIDE",
"ARRAY_SHORT(VertexAttrib[VERT_ATTRIB_COLOR1].Stride), NO_EXTRA" ],
- [ "SECONDARY_COLOR_ARRAY_SIZE", "LOC_CUSTOM, TYPE_UBYTE, 0, NO_EXTRA" ],
+ [ "SECONDARY_COLOR_ARRAY_SIZE", "LOC_CUSTOM, TYPE_INT, 0, NO_EXTRA" ],
# GL_EXT_fog_coord
[ "CURRENT_FOG_COORDINATE",
"CONTEXT_FLOAT(Current.Attrib[VERT_ATTRIB_FOG][0]), extra_flush_current" ],
___
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Mesa (18.1): mesa: fix glGetInteger/Float/etc queries for vertex arrays attribs
Module: Mesa
Branch: 18.1
Commit: 5391c4f5fd53e0b757bb9d951c8f716fb9d12f57
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5391c4f5fd53e0b757bb9d951c8f716fb9d12f57
Author: Brian Paul
Date: Wed May 9 19:46:32 2018 -0600
mesa: fix glGetInteger/Float/etc queries for vertex arrays attribs
The vertex array Size and Stride attributes are now ubyte and short,
respectively. The glGet code needed to be updated to handle those
types, but wasn't.
Fixes the new piglit test gl-1.5-get-array-attribs test.
v2: fix inadvertant whitespace change, change COLOR_ARRAY_SIZE to UBYTE,
misc fixes suggested by Justin
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106450
Fixes: d5f42f96e16 ("mesa: shrink size of gl_array_attributes (v2)")
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Mathias Fröhlich
Reviewed-by: Jordan Justen
(cherry picked from commit d07466fe18522cde1acadfc597583f80b69c15b7)
---
src/mesa/main/get.c | 71
src/mesa/main/get_hash_params.py | 26 +++
2 files changed, 84 insertions(+), 13 deletions(-)
diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index 90ab7ca60f..9a16d079e2 100644
--- a/src/mesa/main/get.c
+++ b/src/mesa/main/get.c
@@ -105,6 +105,8 @@ enum value_type {
TYPE_ENUM,
TYPE_ENUM_2,
TYPE_BOOLEAN,
+ TYPE_UBYTE,
+ TYPE_SHORT,
TYPE_BIT_0,
TYPE_BIT_1,
TYPE_BIT_2,
@@ -188,6 +190,8 @@ union value {
GLint value_int_4[4];
GLint64 value_int64;
GLenum value_enum;
+ GLubyte value_ubyte;
+ GLshort value_short;
/* Sigh, see GL_COMPRESSED_TEXTURE_FORMATS_ARB handling */
struct {
@@ -235,10 +239,13 @@ union value {
#define CONTEXT_MATRIX(field) CONTEXT_FIELD(field, TYPE_MATRIX)
#define CONTEXT_MATRIX_T(field) CONTEXT_FIELD(field, TYPE_MATRIX_T)
+/* Vertex array fields */
#define ARRAY_INT(field) ARRAY_FIELD(field, TYPE_INT)
#define ARRAY_ENUM(field) ARRAY_FIELD(field, TYPE_ENUM)
#define ARRAY_ENUM16(field) ARRAY_FIELD(field, TYPE_ENUM16)
#define ARRAY_BOOL(field) ARRAY_FIELD(field, TYPE_BOOLEAN)
+#define ARRAY_UBYTE(field) ARRAY_FIELD(field, TYPE_UBYTE)
+#define ARRAY_SHORT(field) ARRAY_FIELD(field, TYPE_SHORT)
#define EXT(f) \
offsetof(struct gl_extensions, f)
@@ -1517,6 +1524,10 @@ get_value_size(enum value_type type, const union value
*v)
return sizeof(GLenum) * 2;
case TYPE_BOOLEAN:
return sizeof(GLboolean);
+ case TYPE_UBYTE:
+ return sizeof(GLubyte);
+ case TYPE_SHORT:
+ return sizeof(GLshort);
case TYPE_BIT_0:
case TYPE_BIT_1:
case TYPE_BIT_2:
@@ -1628,6 +1639,14 @@ _mesa_GetBooleanv(GLenum pname, GLboolean *params)
params[0] = ((GLboolean*) p)[0];
break;
+ case TYPE_UBYTE:
+ params[0] = INT_TO_BOOLEAN(((GLubyte *) p)[0]);
+ break;
+
+ case TYPE_SHORT:
+ params[0] = INT_TO_BOOLEAN(((GLshort *) p)[0]);
+ break;
+
case TYPE_MATRIX:
m = *(GLmatrix **) p;
for (i = 0; i < 16; i++)
@@ -1735,6 +1754,14 @@ _mesa_GetFloatv(GLenum pname, GLfloat *params)
params[0] = BOOLEAN_TO_FLOAT(*(GLboolean*) p);
break;
+ case TYPE_UBYTE:
+ params[0] = (GLfloat) ((GLubyte *) p)[0];
+ break;
+
+ case TYPE_SHORT:
+ params[0] = (GLfloat) ((GLshort *) p)[0];
+ break;
+
case TYPE_MATRIX:
m = *(GLmatrix **) p;
for (i = 0; i < 16; i++)
@@ -1842,6 +1869,14 @@ _mesa_GetIntegerv(GLenum pname, GLint *params)
params[0] = BOOLEAN_TO_INT(*(GLboolean*) p);
break;
+ case TYPE_UBYTE:
+ params[0] = ((GLubyte *) p)[0];
+ break;
+
+ case TYPE_SHORT:
+ params[0] = ((GLshort *) p)[0];
+ break;
+
case TYPE_MATRIX:
m = *(GLmatrix **) p;
for (i = 0; i < 16; i++)
@@ -2062,6 +2097,14 @@ _mesa_GetDoublev(GLenum pname, GLdouble *params)
params[0] = *(GLboolean*) p;
break;
+ case TYPE_UBYTE:
+ params[0] = ((GLubyte *) p)[0];
+ break;
+
+ case TYPE_SHORT:
+ params[0] = ((GLshort *) p)[0];
+ break;
+
case TYPE_MATRIX:
m = *(GLmatrix **) p;
for (i = 0; i < 16; i++)
@@ -2141,6 +2184,8 @@ _mesa_GetUnsignedBytevEXT(GLenum pname, GLubyte *data)
case TYPE_ENUM:
case TYPE_ENUM_2:
case TYPE_BOOLEAN:
+ case TYPE_UBYTE:
+ case TYPE_SHORT:
case TYPE_FLOAT:
case TYPE_FLOATN:
case TYPE_FLOAT_2:
@@ -2790,6 +2835,14 @@ _mesa_GetFloati_v(GLenum pname, GLuint index, GLfloat
*params)
params[0] = BOOLEAN_TO_FLOAT(v.value_bool);
break;
+ case TYPE_UBYTE:
+ params[0] = (GLfloat) v.value_ubyte;
+ break;
+
+ case TYPE_SHORT:
+ params[0] = (GLfloat) v.value_short;
+ break;
+
case TYPE_MATRIX:
m = *(GLmatrix **) &v;
for (i = 0; i < 16; i++)
@@ -2873,6 +2926,14 @@ _mesa_GetDoublei_v(GLenum pname, GLuint index, GLdouble
*params)
params[0] = (GLdouble) BOOLEAN_TO_FLOAT(v.value_bool);
break;
+ case TYPE_UBYT
Mesa (18.1): Bump version to rc4
Module: Mesa Branch: 18.1 Commit: 630559e05443b1df6fedb7576c2291af99c3dec5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=630559e05443b1df6fedb7576c2291af99c3dec5 Author: Dylan Baker Date: Fri May 11 08:34:16 2018 -0700 Bump version to rc4 --- VERSION | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/VERSION b/VERSION index 5b3a4a1f0b..628d7e49e3 100644 --- a/VERSION +++ b/VERSION @@ -1 +1 @@ -18.1.0-rc3 +18.1.0-rc4 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (18.1): 21 new commits
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ce9f53f5d9685b94baf35be5faed96fcecd18abd
Author: Dylan Baker
Date: Fri May 11 08:34:16 2018 -0700
Bump version to rc4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e4c54e10315e312cd1a8c05175e67b99e4167e37
Author: Jason Ekstrand
Date: Wed May 9 15:06:13 2018 -0700
i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL
From the bspec docs for "Indirect State Pointers Disable":
"At the completion of the post-sync operation associated with this
pipe control packet, the indirect state pointers in the hardware are
considered invalid"
So the ISP disable is a post-sync type of operation which means that it
should be combined with a CS stall. Without this, the simulator throws
an error.
Fixes: 766d801ca "anv: emit pixel scoreboard stall before ISP disable"
Fixes: f536097f6 "i965: require pixel scoreboard stall prior to ISP disable"
Reviewed-by: Lionel Landwerlin
(cherry picked from commit a8a740f272a808a2694524b43fc33d2f0c0e3709)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b9b1175aaec05544fe0ac02d486d6a9286e3188
Author: Matt Turner
Date: Wed May 9 16:36:58 2018 -0700
gallium/tests: Fix assignment of EXTRA_DIST
Fixes: 6754c2e83d79 ("autotools: Include new meson files")
(cherry picked from commit 0f959215c340150cb6075f5c2d3ccfc5d109558f)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7da026cb98204f9a74a3f2521cd620c6e056921f
Author: Lionel Landwerlin
Date: Tue May 8 17:25:55 2018 +0100
anv: emit pixel scoreboard stall before ISP disable
We want to make sure that all indirect state data has been loaded into
the EUs before disable the pointers.
Signed-off-by: Lionel Landwerlin
Reviewed-by: Rafael Antognolli
Fixes: 78c125af3904c ("anv/gen10: Ignore push constant packets during
context restore.")
(cherry picked from commit 766d801ca32118a722fb2e58a48ee9a96897d3b7)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c140183d411b17951a2a570674b9adab222d10a
Author: Lionel Landwerlin
Date: Tue May 1 12:32:45 2018 +0100
i965: require pixel scoreboard stall prior to ISP disable
Invalidating the indirect state pointers might affect a previously
scheduled & still running 3DPRIMITIVE (causing page fault). So stall
on pixel scoreboard before that.
v2: Fix compile issue :(
v3: Stall on pixel scoreboard
v4: Drop the post sync operation (Lionel)
Signed-off-by: Lionel Landwerlin
Reviewed-by: Rafael Antognolli
Fixes: ca19ee33d7d39 ("i965/gen10: Ignore push constant packets during
context restore.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106243
(cherry picked from commit f536097f67521180dafd270b28ac9a852af9c141)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e3106b460eaeb3744d289d0d949891a7912ff816
Author: Lionel Landwerlin
Date: Wed May 9 16:40:37 2018 +0100
i965: silence unused variable
Signed-off-by: Lionel Landwerlin
Fixes: 2dc29e095f9da ("i965: Don't leak blorp on Gen4-5.")
Reviewed-by: Caio Marcelo de Oliveira Filho
(cherry picked from commit 3853f1c6f4b97edde22c767a80c137da6e39904a)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5519bb3c659165c487603fa67bff90d62b606a5c
Author: Jan Vesely
Date: Tue May 8 01:39:04 2018 -0400
winsys/radeon: Destroy fd_hash table when the last winsys is removed.
Fixes memory leak on module unload.
v2: Use util_hash_table helper function
CC:
Reviewed-by: Marek Olšák
Signed-off-by: Jan Vesely
(cherry picked from commit 45dfa6f4e77fbb21f312eb6101db6c25acd4d483)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5fc5b1dab831b8846fb09db7cad6f83f00c0
Author: Jan Vesely
Date: Wed May 9 15:06:33 2018 -0400
gallium/auxiliary: Add helper function to count the number of entries in
hash table
CC:
Reviewed-by: Marek Olšák
Signed-off-by: Jan Vesely
(cherry picked from commit d146768d139f887105464f0db5600dd046452a8f)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e90f0d711c6429d34aa60fef4c878c0badce1ea3
Author: Dave Airlie
Date: Wed May 9 23:17:09 2018 +0100
r600: fix constant buffer bounds.
If you have an indirect access to a constant buffer on r600/eg
use a vertex fetch in the shader. However apps have expected
behaviour on those out of bounds accessess (even if illegal).
If the constants were being uploaded as part of a larger
upload buffer, we'd set the range of allowed access to a lot
larger than required so apps would get values back from
other parts of the upload buffer instead of the expected out
of bounds access.
This fixes rendering bugs in Trine and Witcher 1, thanks
to iive for nagging me effectively until I figured it out :
Mesa (master): meson: Fix build for egl platform_x11 with dri3
Module: Mesa
Branch: master
Commit: 659910eda01de0ddbd168a0879f548b7950aef00
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=659910eda01de0ddbd168a0879f548b7950aef00
Author: Ville Syrjälä
Date: Mon May 7 19:20:23 2018 +0300
meson: Fix build for egl platform_x11 with dri3
platform_x11 with dri3 needs inc_loader.
In file included from ../src/egl/drivers/dri2/platform_x11_dri3.c:35:0:
../src/egl/drivers/dri2/egl_dri2.h:41:32: fatal error: loader_dri3_helper.h: No
such file or directory
In file included from ../src/egl/drivers/dri2/platform_x11.c:46:0:
../src/egl/drivers/dri2/egl_dri2.h:41:32: fatal error: loader_dri3_helper.h: No
such file or directory
In file included from ../src/egl/drivers/dri2/egl_dri2.c:61:0:
../src/egl/drivers/dri2/egl_dri2.h:41:32: fatal error: loader_dri3_helper.h: No
such file or directory
Cc: Dylan Baker
Reviewed-by: Eric Engestrom
Signed-off-by: Ville Syrjälä
---
src/egl/meson.build | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/egl/meson.build b/src/egl/meson.build
index 6537e4bdee..9050d763a6 100644
--- a/src/egl/meson.build
+++ b/src/egl/meson.build
@@ -102,6 +102,7 @@ if with_platform_x11
if with_dri3
files_egl += files('drivers/dri2/platform_x11_dri3.c')
link_for_egl += libloader_dri3_helper
+incs_for_egl += inc_loader
endif
deps_for_egl += [dep_x11_xcb, dep_xcb_dri2, dep_xcb_xfixes]
endif
___
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Mesa (master): radv: minor cleanups in radv_fill_shader_variant()
Module: Mesa
Branch: master
Commit: 3a410f0afcfe8c26290782141a08ff962956ef3a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a410f0afcfe8c26290782141a08ff962956ef3a
Author: Samuel Pitoiset
Date: Fri May 11 09:46:46 2018 +0200
radv: minor cleanups in radv_fill_shader_variant()
Signed-off-by: Samuel Pitoiset
Reviewed-by: Timothy Arceri
---
src/amd/vulkan/radv_shader.c | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 27b3fbed16..07634870d4 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -371,6 +371,7 @@ radv_fill_shader_variant(struct radv_device *device,
gl_shader_stage stage)
{
bool scratch_enabled = variant->config.scratch_bytes_per_wave > 0;
+ struct radv_shader_info *info = &variant->info.info;
unsigned vgpr_comp_cnt = 0;
if (scratch_enabled && !device->llvm_supports_spill)
@@ -378,9 +379,9 @@ radv_fill_shader_variant(struct radv_device *device,
variant->code_size = binary->code_size;
variant->rsrc2 = S_00B12C_USER_SGPR(variant->info.num_user_sgprs) |
- S_00B12C_SCRATCH_EN(scratch_enabled);
+S_00B12C_SCRATCH_EN(scratch_enabled);
- variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
+ variant->rsrc1 = S_00B848_VGPRS((variant->config.num_vgprs - 1) / 4) |
S_00B848_SGPRS((variant->config.num_sgprs - 1) / 8) |
S_00B848_DX10_CLAMP(1) |
S_00B848_FLOAT_MODE(variant->config.float_mode);
@@ -391,10 +392,11 @@ radv_fill_shader_variant(struct radv_device *device,
variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
break;
case MESA_SHADER_TESS_CTRL:
- if (device->physical_device->rad_info.chip_class >= GFX9)
+ if (device->physical_device->rad_info.chip_class >= GFX9) {
vgpr_comp_cnt = variant->info.vs.vgpr_comp_cnt;
- else
+ } else {
variant->rsrc2 |= S_00B12C_OC_LDS_EN(1);
+ }
break;
case MESA_SHADER_VERTEX:
case MESA_SHADER_GEOMETRY:
@@ -402,8 +404,7 @@ radv_fill_shader_variant(struct radv_device *device,
break;
case MESA_SHADER_FRAGMENT:
break;
- case MESA_SHADER_COMPUTE: {
- struct radv_shader_info *info = &variant->info.info;
+ case MESA_SHADER_COMPUTE:
variant->rsrc2 |=
S_00B84C_TGID_X_EN(info->cs.uses_block_id[0]) |
S_00B84C_TGID_Y_EN(info->cs.uses_block_id[1]) |
@@ -413,7 +414,6 @@ radv_fill_shader_variant(struct radv_device *device,
S_00B84C_TG_SIZE_EN(info->cs.uses_local_invocation_idx)
|
S_00B84C_LDS_SIZE(variant->config.lds_size);
break;
- }
default:
unreachable("unsupported shader type");
break;
@@ -421,7 +421,6 @@ radv_fill_shader_variant(struct radv_device *device,
if (device->physical_device->rad_info.chip_class >= GFX9 &&
stage == MESA_SHADER_GEOMETRY) {
- struct radv_shader_info *info = &variant->info.info;
unsigned es_type = variant->info.gs.es_type;
unsigned gs_vgpr_comp_cnt, es_vgpr_comp_cnt;
@@ -436,23 +435,25 @@ radv_fill_shader_variant(struct radv_device *device,
/* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
* VGPR[0:4] are always loaded.
*/
- if (info->uses_invocation_id)
+ if (info->uses_invocation_id) {
gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
- else if (info->uses_prim_id)
+ } else if (info->uses_prim_id) {
gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
- else if (variant->info.gs.vertices_in >= 3)
+ } else if (variant->info.gs.vertices_in >= 3) {
gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
- else
+ } else {
gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
+ }
variant->rsrc1 |= S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
variant->rsrc2 |= S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
S_00B22C_OC_LDS_EN(es_type ==
MESA_SHADER_TESS_EVAL);
} else if (device->physical_device->rad_info.chip_class >= GFX9 &&
- stage == MESA_SHADER_TESS_CTRL)
+ stage == MESA_SHADER_TESS_CTRL) {
variant->rsrc1 |= S_00B428_LS_VGPR_COMP_CNT(vgpr_comp_cnt);
- else
+ } else {
variant->rsrc1 |= S_00
Mesa (master): radv: move ac_build_if_state on top of radv_nir_to_llvm.c
Module: Mesa
Branch: master
Commit: efc10949cc9259da25dafd4965ba5e58cd99a181
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=efc10949cc9259da25dafd4965ba5e58cd99a181
Author: Samuel Pitoiset
Date: Fri May 11 09:37:11 2018 +0200
radv: move ac_build_if_state on top of radv_nir_to_llvm.c
These helpers will be needed for future work.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Timothy Arceri
---
src/amd/vulkan/radv_nir_to_llvm.c | 183 +++---
1 file changed, 92 insertions(+), 91 deletions(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index e2d241e495..f98940f0d8 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -124,6 +124,98 @@ radv_shader_context_from_abi(struct ac_shader_abi *abi)
return container_of(abi, ctx, abi);
}
+struct ac_build_if_state
+{
+ struct radv_shader_context *ctx;
+ LLVMValueRef condition;
+ LLVMBasicBlockRef entry_block;
+ LLVMBasicBlockRef true_block;
+ LLVMBasicBlockRef false_block;
+ LLVMBasicBlockRef merge_block;
+};
+
+static LLVMBasicBlockRef
+ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
+{
+ LLVMBasicBlockRef current_block;
+ LLVMBasicBlockRef next_block;
+ LLVMBasicBlockRef new_block;
+
+ /* get current basic block */
+ current_block = LLVMGetInsertBlock(ctx->ac.builder);
+
+ /* chqeck if there's another block after this one */
+ next_block = LLVMGetNextBasicBlock(current_block);
+ if (next_block) {
+ /* insert the new block before the next block */
+ new_block = LLVMInsertBasicBlockInContext(ctx->context,
next_block, name);
+ }
+ else {
+ /* append new block after current block */
+ LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
+ new_block = LLVMAppendBasicBlockInContext(ctx->context,
function, name);
+ }
+ return new_block;
+}
+
+static void
+ac_nir_build_if(struct ac_build_if_state *ifthen,
+ struct radv_shader_context *ctx,
+ LLVMValueRef condition)
+{
+ LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
+
+ memset(ifthen, 0, sizeof *ifthen);
+ ifthen->ctx = ctx;
+ ifthen->condition = condition;
+ ifthen->entry_block = block;
+
+ /* create endif/merge basic block for the phi functions */
+ ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
+
+ /* create/insert true_block before merge_block */
+ ifthen->true_block =
+ LLVMInsertBasicBlockInContext(ctx->context,
+ ifthen->merge_block,
+ "if-true-block");
+
+ /* successive code goes into the true block */
+ LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
+}
+
+/**
+ * End a conditional.
+ */
+static void
+ac_nir_build_endif(struct ac_build_if_state *ifthen)
+{
+ LLVMBuilderRef builder = ifthen->ctx->ac.builder;
+
+ /* Insert branch to the merge block from current block */
+ LLVMBuildBr(builder, ifthen->merge_block);
+
+ /*
+* Now patch in the various branch instructions.
+*/
+
+ /* Insert the conditional branch instruction at the end of entry_block
*/
+ LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
+ if (ifthen->false_block) {
+ /* we have an else clause */
+ LLVMBuildCondBr(builder, ifthen->condition,
+ ifthen->true_block, ifthen->false_block);
+ }
+ else {
+ /* no else clause */
+ LLVMBuildCondBr(builder, ifthen->condition,
+ ifthen->true_block, ifthen->merge_block);
+ }
+
+ /* Resume building code at end of the ifthen->merge_block */
+ LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
+}
+
+
static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
{
switch (ctx->stage) {
@@ -2502,97 +2594,6 @@ handle_ls_outputs_post(struct radv_shader_context *ctx)
}
}
-struct ac_build_if_state
-{
- struct radv_shader_context *ctx;
- LLVMValueRef condition;
- LLVMBasicBlockRef entry_block;
- LLVMBasicBlockRef true_block;
- LLVMBasicBlockRef false_block;
- LLVMBasicBlockRef merge_block;
-};
-
-static LLVMBasicBlockRef
-ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
-{
- LLVMBasicBlockRef current_block;
- LLVMBasicBlockRef next_block;
- LLVMBasicBlockRef new_block;
-
- /* get current basic block */
- current_block = LLVMGetInsertBlock(ctx->ac.builder);
-
- /* check if there's another block after this one */
- next_block = LLVMGetNextBasicBlock(current_block);
- if (next_block) {
