Mesa (master): virgl: enable vertex streams when glsl level is high enough.
Module: Mesa Branch: master Commit: 9585e702065d9c2db57ab32f53a42d1ceafdb4a3 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9585e702065d9c2db57ab32f53a42d1ceafdb4a3 Author: Dave Airlie Date: Mon Dec 21 16:59:58 2015 +1000 virgl: enable vertex streams when glsl level is high enough. This enabled the vertex streams out when the host supports GL4.0. --- src/gallium/drivers/virgl/virgl_encode.c | 2 +- src/gallium/drivers/virgl/virgl_screen.c | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/virgl/virgl_encode.c b/src/gallium/drivers/virgl/virgl_encode.c index a6f6d13f85..f3cbd1ca4b 100644 --- a/src/gallium/drivers/virgl/virgl_encode.c +++ b/src/gallium/drivers/virgl/virgl_encode.c @@ -232,7 +232,7 @@ static void virgl_emit_shader_streamout(struct virgl_context *ctx, VIRGL_OBJ_SHADER_SO_OUTPUT_BUFFER(so_info->output[i].output_buffer) | VIRGL_OBJ_SHADER_SO_OUTPUT_DST_OFFSET(so_info->output[i].dst_offset); virgl_encoder_write_dword(ctx->cbuf, tmp); - virgl_encoder_write_dword(ctx->cbuf, 0); + virgl_encoder_write_dword(ctx->cbuf, so_info->output[i].stream); } } } diff --git a/src/gallium/drivers/virgl/virgl_screen.c b/src/gallium/drivers/virgl/virgl_screen.c index ab35b1fe2c..1ca9e85de7 100644 --- a/src/gallium/drivers/virgl/virgl_screen.c +++ b/src/gallium/drivers/virgl/virgl_screen.c @@ -198,12 +198,13 @@ virgl_get_param(struct pipe_screen *screen, enum pipe_cap param) return vscreen->caps.caps.v1.bset.has_sample_shading; case PIPE_CAP_CULL_DISTANCE: return vscreen->caps.caps.v1.bset.has_cull; + case PIPE_CAP_MAX_VERTEX_STREAMS: + return vscreen->caps.caps.v1.glsl_level >= 400 ? 4 : 1; case PIPE_CAP_TEXTURE_GATHER_SM5: case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT: case PIPE_CAP_FAKE_SW_MSAA: case PIPE_CAP_TEXTURE_GATHER_OFFSETS: case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION: - case PIPE_CAP_MAX_VERTEX_STREAMS: case PIPE_CAP_MULTI_DRAW_INDIRECT: case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS: case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): opencl: autotools: Fix linking order for OpenCL target
Module: Mesa Branch: master Commit: b691d9192c436aba5a76577b7d772a791283a2e2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b691d9192c436aba5a76577b7d772a791283a2e2 Author: Kai Wasserbäch Date: Tue May 1 14:14:46 2018 +0200 opencl: autotools: Fix linking order for OpenCL target Otherwise the build fails with an undefined reference to clang::FrontendTimesIsEnabled. Bugzilla: https://bugs.freedesktop.org/106209 Cc: Jan Vesely Cc: mesa-sta...@lists.freedesktop.org Signed-off-by: Kai Wasserbäch Acked-by: Jan Vesely Tested-by: Aaron Watry Tested-by: Dieter Nützel --- src/gallium/targets/opencl/Makefile.am | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/gallium/targets/opencl/Makefile.am b/src/gallium/targets/opencl/Makefile.am index de68a93ad5..f0e1de7797 100644 --- a/src/gallium/targets/opencl/Makefile.am +++ b/src/gallium/targets/opencl/Makefile.am @@ -23,11 +23,10 @@ lib@OPENCL_LIBNAME@_la_LIBADD = \ $(LIBELF_LIBS) \ $(DLOPEN_LIBS) \ -lclangCodeGen \ - -lclangFrontendTool \ -lclangFrontend \ + -lclangFrontendTool \ -lclangDriver \ -lclangSerialization \ - -lclangCodeGen \ -lclangParse \ -lclangSema \ -lclangAnalysis \ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: run the shader info pass before emitting the GS copy shader
Module: Mesa Branch: master Commit: ea43d935ab765575994557d1f923b570d4bd9085 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ea43d935ab765575994557d1f923b570d4bd9085 Author: Samuel Pitoiset Date: Mon May 14 16:04:34 2018 +0200 radv: run the shader info pass before emitting the GS copy shader For further optimizations. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_nir_to_llvm.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index 47c52dc437..2162ca58e0 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -3549,6 +3549,8 @@ radv_compile_gs_copy_shader(LLVMTargetMachineRef tm, ctx.ac.builder = ac_create_builder(ctx.context, float_mode); ctx.stage = MESA_SHADER_VERTEX; + radv_nir_shader_info_pass(geom_shader, options, &shader_info->info); + create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX); ctx.gs_max_out_vertices = geom_shader->info.gs.vertices_out; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: scan the geometry shader output usage mask
Module: Mesa
Branch: master
Commit: 560bd9eb67fb24b05816c3afb9a47794eddb61aa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=560bd9eb67fb24b05816c3afb9a47794eddb61aa
Author: Samuel Pitoiset
Date: Mon May 14 16:04:35 2018 +0200
radv: scan the geometry shader output usage mask
For reducing the number of parameters that are exported by
the GS copy shader.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_shader.h | 3 +++
src/amd/vulkan/radv_shader_info.c | 6 ++
2 files changed, 9 insertions(+)
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index b711cba80c..679fa44279 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -159,6 +159,9 @@ struct radv_shader_info {
} vs;
struct {
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
+ } gs;
+ struct {
+ uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
} tes;
struct {
bool force_persample;
diff --git a/src/amd/vulkan/radv_shader_info.c
b/src/amd/vulkan/radv_shader_info.c
index a436bd7534..b45b4c0c95 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -134,6 +134,12 @@ gather_intrinsic_store_var_info(const nir_shader *nir,
instr->const_index[0] << comp;
}
break;
+ case MESA_SHADER_GEOMETRY:
+ for (unsigned i = 0; i < attrib_count; i++) {
+ info->gs.output_usage_mask[idx + i +
const_offset] |=
+ instr->const_index[0] << comp;
+ }
+ break;
case MESA_SHADER_TESS_EVAL:
for (unsigned i = 0; i < attrib_count; i++) {
info->tes.output_usage_mask[idx + i +
const_offset] |=
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Mesa (master): radv: reduce the number of parameters export by the GS copy shader
Module: Mesa
Branch: master
Commit: 97b179570c092632589dba1bd0ed49ec3b4d5cd5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=97b179570c092632589dba1bd0ed49ec3b4d5cd5
Author: Samuel Pitoiset
Date: Mon May 14 16:04:36 2018 +0200
radv: reduce the number of parameters export by the GS copy shader
By using the geometry shader output usage mask.
This improves all Vulkan demos that use a geometry shader
(ie. geometryshader, deferredshadows, viewportarray).
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_nir_to_llvm.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index 2162ca58e0..b4af0f2941 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -2493,10 +2493,9 @@ handle_vs_outputs_post(struct radv_shader_context *ctx,
output_usage_mask =
ctx->shader_info->info.tes.output_usage_mask[i];
} else {
- /* Enable all channels for the GS copy shader because
-* we don't know the output usage mask currently.
-*/
- output_usage_mask = 0xf;
+ assert(ctx->is_gs_copy_shader);
+ output_usage_mask =
+ ctx->shader_info->info.gs.output_usage_mask[i];
}
radv_export_param(ctx, param_count, values, output_usage_mask);
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Mesa (master): radv: check that layout isn't NULL in radv_nir_shader_info_pass()
Module: Mesa Branch: master Commit: 7cbc6f2621f6d91b7bb201b9539ebff0f903828a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7cbc6f2621f6d91b7bb201b9539ebff0f903828a Author: Samuel Pitoiset Date: Mon May 14 16:04:33 2018 +0200 radv: check that layout isn't NULL in radv_nir_shader_info_pass() An upcoming patch will run the shader info pass on the geometry shader just before emitting the GS copy shader. Signed-off-by: Samuel Pitoiset Reviewed-by: Bas Nieuwenhuizen --- src/amd/vulkan/radv_shader_info.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_shader_info.c b/src/amd/vulkan/radv_shader_info.c index aa06efc9dc..a436bd7534 100644 --- a/src/amd/vulkan/radv_shader_info.c +++ b/src/amd/vulkan/radv_shader_info.c @@ -424,7 +424,7 @@ radv_nir_shader_info_pass(const struct nir_shader *nir, struct nir_function *func = (struct nir_function *)exec_list_get_head_const(&nir->functions); - if (options->layout->dynamic_offset_count) + if (options->layout && options->layout->dynamic_offset_count) info->loads_push_constants = true; nir_foreach_variable(variable, &nir->inputs) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): intel/blorp: Use linear formats for CCS_E clear colors in copies
Module: Mesa Branch: master Commit: 18f8200a994440faa9fb9e80e99e8140ea912993 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=18f8200a994440faa9fb9e80e99e8140ea912993 Author: Jason Ekstrand Date: Fri May 11 15:02:13 2018 -0700 intel/blorp: Use linear formats for CCS_E clear colors in copies It's clear that the original code meant to do this and there is even a 10-line comment explaining why. Originally, we had a simple function for packing the clear colors which was unaware of sRGB. However, in a6b66a7b26ae1, when we started using ISL to do the packing, the wrong format was used. Fixes: a6b66a7b26 "intel/blorp: Use ISL instead of bitcast_color..." Reviewed-by: Topi Pohjolainen --- src/intel/blorp/blorp_blit.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c index e825862d71..26bf4426c0 100644 --- a/src/intel/blorp/blorp_blit.c +++ b/src/intel/blorp/blorp_blit.c @@ -2562,7 +2562,7 @@ blorp_copy(struct blorp_batch *batch, params.src.view.format)); uint32_t packed[4]; isl_color_value_pack(¶ms.src.clear_color, - params.src.surf.format, packed); + linear_src_format, packed); isl_color_value_unpack(¶ms.src.clear_color, params.src.view.format, packed); } @@ -2576,7 +2576,7 @@ blorp_copy(struct blorp_batch *batch, params.dst.view.format)); uint32_t packed[4]; isl_color_value_pack(¶ms.dst.clear_color, - params.dst.surf.format, packed); + linear_dst_format, packed); isl_color_value_unpack(¶ms.dst.clear_color, params.dst.view.format, packed); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: Add support for IMG_DATA_FORMAT_32_32_32.
Module: Mesa
Branch: master
Commit: e361970ed73d0f0a11d93a718dbfe2bf4f38b56d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e361970ed73d0f0a11d93a718dbfe2bf4f38b56d
Author: Bas Nieuwenhuizen
Date: Tue May 1 04:03:34 2018 +0200
radv: Add support for IMG_DATA_FORMAT_32_32_32.
Basic sampling support for linear tiling.
No CTS regressions, but it seems the blitting coverage is not very
extensive.
https://bugs.freedesktop.org/show_bug.cgi?id=106331
Reviewed-by: Samuel Pitoiset
---
src/amd/common/ac_surface.c | 4
src/amd/vulkan/radv_formats.c | 10 ++
src/amd/vulkan/radv_meta_copy.c | 1 +
3 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 12240c93d6..9e742dc8a4 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -1320,6 +1320,10 @@ static int gfx9_compute_surface(ADDR_HANDLE addrlib,
assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
AddrSurfInfoIn.format = ADDR_FMT_32_32;
break;
+ case 12:
+ assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
+ AddrSurfInfoIn.format = ADDR_FMT_32_32_32;
+ break;
case 16:
assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
AddrSurfInfoIn.format = ADDR_FMT_32_32_32_32;
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index 1bafe09e77..f8438f43b8 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -321,10 +321,8 @@ uint32_t radv_translate_tex_dataformat(VkFormat format,
return V_008F14_IMG_DATA_FORMAT_32;
case 2:
return V_008F14_IMG_DATA_FORMAT_32_32;
-#if 0 /* Not supported for render targets */
case 3:
return V_008F14_IMG_DATA_FORMAT_32_32_32;
-#endif
case 4:
return V_008F14_IMG_DATA_FORMAT_32_32_32_32;
}
@@ -638,13 +636,17 @@ radv_physical_device_get_format_properties(struct
radv_physical_device *physical
tiled |=
VK_FORMAT_FEATURE_COLOR_ATTACHMENT_BLEND_BIT;
}
}
- if (tiled &&
util_is_power_of_two_or_zero(vk_format_get_blocksize(format)) && !scaled) {
+ if (tiled && !scaled) {
tiled |= VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR |
VK_FORMAT_FEATURE_TRANSFER_DST_BIT_KHR;
}
+
+ /* Tiled formatting does not support NPOT pixel sizes */
+ if
(!util_is_power_of_two_or_zero(vk_format_get_blocksize(format)))
+ tiled = 0;
}
- if (linear &&
util_is_power_of_two_or_zero(vk_format_get_blocksize(format)) && !scaled) {
+ if (linear && !scaled) {
linear |= VK_FORMAT_FEATURE_TRANSFER_SRC_BIT_KHR |
VK_FORMAT_FEATURE_TRANSFER_DST_BIT_KHR;
}
diff --git a/src/amd/vulkan/radv_meta_copy.c b/src/amd/vulkan/radv_meta_copy.c
index 2055289a9b..1f18886d2c 100644
--- a/src/amd/vulkan/radv_meta_copy.c
+++ b/src/amd/vulkan/radv_meta_copy.c
@@ -72,6 +72,7 @@ vk_format_for_size(int bs)
case 2: return VK_FORMAT_R8G8_UINT;
case 4: return VK_FORMAT_R8G8B8A8_UINT;
case 8: return VK_FORMAT_R16G16B16A16_UINT;
+ case 12: return VK_FORMAT_R32G32B32_UINT;
case 16: return VK_FORMAT_R32G32B32A32_UINT;
default:
unreachable("Invalid format block size");
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Mesa (master): radv: Fix up 2_10_10_10 alpha sign.
Module: Mesa
Branch: master
Commit: 3d4d388e3929d7948b62d90867357aecbfba5aeb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d4d388e3929d7948b62d90867357aecbfba5aeb
Author: Bas Nieuwenhuizen
Date: Sat May 12 23:50:04 2018 +0200
radv: Fix up 2_10_10_10 alpha sign.
Pre-Vega HW always interprets the alpha for this format as unsigned,
so we have to implement a fixup to do the sign correctly for signed
formats.
v2: Improve indexing mess.
CC: 18.0 18.1
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106480
Reviewed-by: Samuel Pitoiset
---
src/amd/vulkan/radv_nir_to_llvm.c | 68 +--
src/amd/vulkan/radv_pipeline.c| 30 +++--
src/amd/vulkan/radv_private.h | 1 +
src/amd/vulkan/radv_shader.h | 12 +++
4 files changed, 98 insertions(+), 13 deletions(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index f98940f0d8..47c52dc437 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -1865,6 +1865,47 @@ static LLVMValueRef radv_get_sampler_desc(struct
ac_shader_abi *abi,
return ac_build_load_to_sgpr(&ctx->ac, list, index);
}
+/* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
+ * so we may need to fix it up. */
+static LLVMValueRef
+adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
+ unsigned adjustment,
+ LLVMValueRef alpha)
+{
+ if (adjustment == RADV_ALPHA_ADJUST_NONE)
+ return alpha;
+
+ LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
+
+ if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
+ alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32,
"");
+ else
+ alpha = ac_to_integer(&ctx->ac, alpha);
+
+ /* For the integer-like cases, do a natural sign extension.
+*
+* For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
+* and happen to contain 0, 1, 2, 3 as the two LSBs of the
+* exponent.
+*/
+ alpha = LLVMBuildShl(ctx->ac.builder, alpha,
+adjustment == RADV_ALPHA_ADJUST_SNORM ?
+LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
+ alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
+
+ /* Convert back to the right type. */
+ if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
+ LLVMValueRef clamp;
+ LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
+ alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32,
"");
+ clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha,
neg_one, "");
+ alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha,
"");
+ } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
+ alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32,
"");
+ }
+
+ return alpha;
+}
static void
handle_vs_input_decl(struct radv_shader_context *ctx,
@@ -1875,18 +1916,19 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
LLVMValueRef t_list;
LLVMValueRef input;
LLVMValueRef buffer_index;
- int index = variable->data.location - VERT_ATTRIB_GENERIC0;
- int idx = variable->data.location;
unsigned attrib_count = glsl_count_attribute_slots(variable->type,
true);
uint8_t input_usage_mask =
ctx->shader_info->info.vs.input_usage_mask[variable->data.location];
unsigned num_channels = util_last_bit(input_usage_mask);
- variable->data.driver_location = idx * 4;
+ variable->data.driver_location = variable->data.location * 4;
+
+ for (unsigned i = 0; i < attrib_count; ++i) {
+ LLVMValueRef output[4];
+ unsigned attrib_index = variable->data.location + i -
VERT_ATTRIB_GENERIC0;
- for (unsigned i = 0; i < attrib_count; ++i, ++idx) {
- if (ctx->options->key.vs.instance_rate_inputs & (1u << (index +
i))) {
- uint32_t divisor =
ctx->options->key.vs.instance_rate_divisors[index + i];
+ if (ctx->options->key.vs.instance_rate_inputs & (1u <<
attrib_index)) {
+ uint32_t divisor =
ctx->options->key.vs.instance_rate_divisors[attrib_index];
if (divisor) {
buffer_index = LLVMBuildAdd(ctx->ac.builder,
ctx->abi.instance_id,
@@ -1910,7 +1952,7 @@ handle_vs_input_decl(struct radv_shader_context *ctx,
} else
buffer_index = LLVMBuildAdd(ctx->ac.builder,
ctx->abi.vertex_id,
ctx->abi.base_vertex, "");
- t_offset = LLVMConstInt(ctx->ac.i32, index + i, false);
+ t_offset = LLVMConstInt(ctx->ac.i32, attrib_index, false);
t_list = ac_build_load_to_sgpr(&ctx->ac,
Mesa (master): radv: Disable texel buffers with A2 SNORM/SSCALED/SINT for pre-vega.
Module: Mesa
Branch: master
Commit: f944a59996287de85d4c6d9b7b000d25f41b1d79
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f944a59996287de85d4c6d9b7b000d25f41b1d79
Author: Bas Nieuwenhuizen
Date: Sat May 12 23:56:56 2018 +0200
radv: Disable texel buffers with A2 SNORM/SSCALED/SINT for pre-vega.
The hardware always interprets the alpha as unsigned and fixing it
in the shader is going to add unacceptable overheads.
CC: 18.0 18.1
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106480
Reviewed-by: Samuel Pitoiset
---
src/amd/vulkan/radv_formats.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index f8438f43b8..1ac07b41a6 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -657,6 +657,25 @@ radv_physical_device_get_format_properties(struct
radv_physical_device *physical
tiled |= VK_FORMAT_FEATURE_STORAGE_IMAGE_ATOMIC_BIT;
}
+ switch(format) {
+ case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
+ case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
+ case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
+ case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
+ case VK_FORMAT_A2R10G10B10_SINT_PACK32:
+ case VK_FORMAT_A2B10G10R10_SINT_PACK32:
+ if (physical_device->rad_info.chip_class <= VI &&
+ physical_device->rad_info.family != CHIP_STONEY) {
+ buffer &= ~(VK_FORMAT_FEATURE_UNIFORM_TEXEL_BUFFER_BIT |
+ VK_FORMAT_FEATURE_STORAGE_TEXEL_BUFFER_BIT);
+ linear = 0;
+ tiled = 0;
+ }
+ break;
+ default:
+ break;
+ }
+
out_properties->linearTilingFeatures = linear;
out_properties->optimalTilingFeatures = tiled;
out_properties->bufferFeatures = buffer;
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Mesa (master): radv: Fix multiview queries.
Module: Mesa
Branch: master
Commit: 62f50df7b79c273a0eb9bf769eded76933bddc3a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=62f50df7b79c273a0eb9bf769eded76933bddc3a
Author: Bas Nieuwenhuizen
Date: Sun May 13 22:01:44 2018 +0200
radv: Fix multiview queries.
This moves the extra queries to after the main query ended, instead
of doing it after the begin and hence doing nesting.
We also emit only (view count - 1) extra queries, as the main query
is already there for the first view.
This fixes the CTS occasionally getting stuck in
dEQP-VK.multiview.queries* waiting on results.
Fixes: 32b4f3c38dc "radv/query: handle multiview queries properly. (v3)"
CC: 18.1
Reviewed-by: Dave Airlie
Reviewed-by: Samuel Pitoiset
---
src/amd/vulkan/radv_query.c | 39 ---
1 file changed, 20 insertions(+), 19 deletions(-)
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index 2b2e80f4e5..3749e2f43d 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -1204,25 +1204,6 @@ void radv_CmdBeginQuery(
va += pool->stride * query;
emit_begin_query(cmd_buffer, va, pool->type, flags);
-
- /*
-* For multiview we have to emit a query for each bit in the mask,
-* however the first query we emit will get the totals for all the
-* operations, so we don't want to get a real value in the other
-* queries. This emits a fake begin/end sequence so the waiting
-* code gets a completed query value and doesn't hang, but the
-* query returns 0.
-*/
- if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
- uint64_t avail_va = va + pool->availability_offset + 4 * query;
-
- for (unsigned i = 0; i <
util_bitcount(cmd_buffer->state.subpass->view_mask); i++) {
- va += pool->stride;
- avail_va += 4;
- emit_begin_query(cmd_buffer, va, pool->type, flags);
- emit_end_query(cmd_buffer, va, avail_va, pool->type);
- }
- }
}
@@ -1241,6 +1222,26 @@ void radv_CmdEndQuery(
* currently be active, which means the BO is already in the list.
*/
emit_end_query(cmd_buffer, va, avail_va, pool->type);
+
+ /*
+* For multiview we have to emit a query for each bit in the mask,
+* however the first query we emit will get the totals for all the
+* operations, so we don't want to get a real value in the other
+* queries. This emits a fake begin/end sequence so the waiting
+* code gets a completed query value and doesn't hang, but the
+* query returns 0.
+*/
+ if (cmd_buffer->state.subpass && cmd_buffer->state.subpass->view_mask) {
+ uint64_t avail_va = va + pool->availability_offset + 4 * query;
+
+
+ for (unsigned i = 1; i <
util_bitcount(cmd_buffer->state.subpass->view_mask); i++) {
+ va += pool->stride;
+ avail_va += 4;
+ emit_begin_query(cmd_buffer, va, pool->type, 0);
+ emit_end_query(cmd_buffer, va, avail_va, pool->type);
+ }
+ }
}
void radv_CmdWriteTimestamp(
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Mesa (master): radv: Translate logic ops.
Module: Mesa Branch: master Commit: dd102405dea022f6c27bc42176f50f3bb2761ae6 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd102405dea022f6c27bc42176f50f3bb2761ae6 Author: Bas Nieuwenhuizen Date: Mon May 14 03:01:21 2018 +0200 radv: Translate logic ops. radeonsi could pass them through but the enum changed between Gallium and Vulkan, so we have to translate. In progress I made the register defines a bit more readable. CC: 18.0 18.1 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100430 Reviewed-by: Samuel Pitoiset --- src/amd/common/sid.h | 44 +++-- src/amd/vulkan/radv_pipeline.c | 45 -- 2 files changed, 59 insertions(+), 30 deletions(-) diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h index 3588d39d62..e922b38ae3 100644 --- a/src/amd/common/sid.h +++ b/src/amd/common/sid.h @@ -6892,34 +6892,22 @@ #define S_028808_ROP3(x) (((unsigned)(x) & 0xFF) << 16) #define G_028808_ROP3(x)(((x) >> 16) & 0xFF) #define C_028808_ROP3 0xFF00 -#define V_028808_X_0X00 0x00 -#define V_028808_X_0X05 0x05 -#define V_028808_X_0X0A 0x0A -#define V_028808_X_0X0F 0x0F -#define V_028808_X_0X11 0x11 -#define V_028808_X_0X22 0x22 -#define V_028808_X_0X33 0x33 -#define V_028808_X_0X44 0x44 -#define V_028808_X_0X50 0x50 -#define V_028808_X_0X55 0x55 -#define V_028808_X_0X5A 0x5A -#define V_028808_X_0X5F 0x5F -#define V_028808_X_0X66 0x66 -#define V_028808_X_0X77 0x77 -#define V_028808_X_0X88 0x88 -#define V_028808_X_0X99 0x99 -#define V_028808_X_0XA0 0xA0 -#define V_028808_X_0XA5 0xA5 -#define V_028808_X_0XAA 0xAA -#define V_028808_X_0XAF 0xAF -#define V_028808_X_0XBB 0xBB -#define V_028808_X_0XCC 0xCC -#define V_028808_X_0XDD 0xDD -#define V_028808_X_0XEE 0xEE -#define V_028808_X_0XF0 0xF0 -#define V_028808_X_0XF5 0xF5 -#define V_028808_X_0XFA 0xFA -#define V_028808_X_0XFF 0xFF +#define V_028808_ROP3_CLEAR 0x00 +#define V_028808_ROP3_NOR 0x11 +#define V_028808_ROP3_AND_INVERTED 0x22 +#define V_028808_ROP3_COPY_INVERTED 0x33 +#define V_028808_ROP3_AND_REVERSE 0x44 +#define V_028808_ROP3_INVERT0x55 +#define V_028808_ROP3_XOR 0x66 +#define V_028808_ROP3_NAND 0x77 +#define V_028808_ROP3_AND 0x88 +#define V_028808_ROP3_EQUIVALENT0x99 +#define V_028808_ROP3_NO_OP 0xaa +#define V_028808_ROP3_OR_INVERTED 0xbb +#define V_028808_ROP3_COPY 0xcc +#define V_028808_ROP3_OR_REVERSE0xdd +#define V_028808_ROP3_OR0xee +#define V_028808_ROP3_SET 0xff #define R_02880C_DB_SHADER_CONTROL 0x02880C #define S_02880C_Z_EXPORT_ENABLE(x) (((unsigned)(x) & 0x1) << 0) #define G_02880C_Z_EXPORT_ENABLE(x) (((x) >> 0) & 0x1) diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c index 3d242e05bf..7a577dae41 100644 --- a/src/amd/vulkan/radv_pipeline.c +++ b/src/amd/vulkan/radv_pipeline.c @@ -181,6 +181,47 @@ radv_pipeline_scratch_init(struct radv_devi
Mesa (master): meson: remove dependency antipattern
Module: Mesa Branch: master Commit: f0cdc39b134dfc38f84b0f6dc1eaad86d28d4170 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0cdc39b134dfc38f84b0f6dc1eaad86d28d4170 Author: Eric Engestrom Date: Tue May 8 16:40:24 2018 +0100 meson: remove dependency antipattern `dep_valgrind != []` now (0.45) produces a warning that is quite explicit: WARNING: Trying to compare values of different types (DependencyHolder, list) using !=. The result of this is undefined and will become a hard error in a future Meson release. `dep_valgrind = []` used to be the recommended way to deal with non-existant dependency, but these don't work with `.found()`, so now the recommended way is to declare a impossible dependency, which null_dep does for us in Mesa. In short, we don't need and shouldn't check for `!= []` anywhere anymore. Reviewed-by: Dylan Baker Signed-off-by: Eric Engestrom --- src/compiler/glsl/glcpp/meson.build | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/glsl/glcpp/meson.build b/src/compiler/glsl/glcpp/meson.build index e6a3dc8675..09d44ddd68 100644 --- a/src/compiler/glsl/glcpp/meson.build +++ b/src/compiler/glsl/glcpp/meson.build @@ -57,7 +57,7 @@ glcpp = executable( if with_tests modes = ['unix', 'windows', 'oldmac', 'bizarro'] - if dep_valgrind != [] and dep_valgrind.found() + if dep_valgrind.found() modes += ['valgrind'] endif ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: allow to dump the GS copy shader with RADV_DEBUG="shaders"
Module: Mesa
Branch: master
Commit: 8ade3e46845ed51b17bc0ff129f3e1eeea589a36
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ade3e46845ed51b17bc0ff129f3e1eeea589a36
Author: Samuel Pitoiset
Date: Fri May 11 16:36:02 2018 +0200
radv: allow to dump the GS copy shader with RADV_DEBUG="shaders"
Signed-off-by: Samuel Pitoiset
Reviewed-by: Timothy Arceri
---
src/amd/vulkan/radv_pipeline.c | 2 +-
src/amd/vulkan/radv_shader.c | 2 +-
src/amd/vulkan/radv_shader.h | 9 ++---
3 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index d443f8271e..e6ac0721dc 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1984,7 +1984,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
radv_link_shaders(pipeline, nir);
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
- if (modules[i] && radv_can_dump_shader(device, modules[i]))
+ if (modules[i] && radv_can_dump_shader(device, modules[i],
false))
nir_print_shader(nir[i], stderr);
}
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index fde6309c97..dfe63d60d4 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -484,7 +484,7 @@ shader_variant_create(struct radv_device *device,
options->family = chip_family;
options->chip_class = device->physical_device->rad_info.chip_class;
- options->dump_shader = radv_can_dump_shader(device, module);
+ options->dump_shader = radv_can_dump_shader(device, module,
gs_copy_shader);
options->dump_preoptir = options->dump_shader &&
device->instance->debug_flags &
RADV_DEBUG_PREOPTIR;
options->record_llvm_ir = device->keep_shader_info;
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index 182b69849c..12878307ec 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -329,11 +329,14 @@ radv_shader_dump_stats(struct radv_device *device,
static inline bool
radv_can_dump_shader(struct radv_device *device,
-struct radv_shader_module *module)
+struct radv_shader_module *module,
+bool is_gs_copy_shader)
{
+ if (!(device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS))
+ return false;
+
/* Only dump non-meta shaders, useful for debugging purposes. */
- return device->instance->debug_flags & RADV_DEBUG_DUMP_SHADERS &&
- module && !module->nir;
+ return (module && !module->nir) || is_gs_copy_shader;
}
static inline bool
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Mesa (master): radv: move {load,store}_var intrinsics scanning in different functions
Module: Mesa
Branch: master
Commit: 553418af1ecbaed04e24197caaf1febd575fec41
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=553418af1ecbaed04e24197caaf1febd575fec41
Author: Samuel Pitoiset
Date: Thu May 10 17:15:41 2018 +0200
radv: move {load,store}_var intrinsics scanning in different functions
These are going to be crazy and we are probably going to add
more scan stuff in the future. Also use switch cases instead.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Timothy Arceri
---
src/amd/vulkan/radv_shader_info.c | 127 --
1 file changed, 80 insertions(+), 47 deletions(-)
diff --git a/src/amd/vulkan/radv_shader_info.c
b/src/amd/vulkan/radv_shader_info.c
index 1fb350faed..aa06efc9dc 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -88,6 +88,83 @@ static void get_deref_offset(nir_deref_var *deref, unsigned
*const_out)
}
static void
+gather_intrinsic_load_var_info(const nir_shader *nir,
+ const nir_intrinsic_instr *instr,
+ struct radv_shader_info *info)
+{
+ switch (nir->info.stage) {
+ case MESA_SHADER_VERTEX: {
+ nir_deref_var *dvar = instr->variables[0];
+ nir_variable *var = dvar->var;
+
+ if (var->data.mode == nir_var_shader_in) {
+ unsigned idx = var->data.location;
+ uint8_t mask =
nir_ssa_def_components_read(&instr->dest.ssa);
+
+ info->vs.input_usage_mask[idx] |=
+ mask << var->data.location_frac;
+ }
+ break;
+ }
+ default:
+ break;
+ }
+}
+
+static void
+gather_intrinsic_store_var_info(const nir_shader *nir,
+ const nir_intrinsic_instr *instr,
+ struct radv_shader_info *info)
+{
+ nir_deref_var *dvar = instr->variables[0];
+ nir_variable *var = dvar->var;
+
+ if (var->data.mode == nir_var_shader_out) {
+ unsigned attrib_count = glsl_count_attribute_slots(var->type,
false);
+ unsigned idx = var->data.location;
+ unsigned comp = var->data.location_frac;
+ unsigned const_offset = 0;
+
+ get_deref_offset(dvar, &const_offset);
+
+ switch (nir->info.stage) {
+ case MESA_SHADER_VERTEX:
+ for (unsigned i = 0; i < attrib_count; i++) {
+ info->vs.output_usage_mask[idx + i +
const_offset] |=
+ instr->const_index[0] << comp;
+ }
+ break;
+ case MESA_SHADER_TESS_EVAL:
+ for (unsigned i = 0; i < attrib_count; i++) {
+ info->tes.output_usage_mask[idx + i +
const_offset] |=
+ instr->const_index[0] << comp;
+ }
+ break;
+ case MESA_SHADER_TESS_CTRL: {
+ unsigned param = shader_io_get_unique_index(idx);
+ const struct glsl_type *type = var->type;
+
+ if (!var->data.patch)
+ type = glsl_get_array_element(var->type);
+
+ unsigned slots =
+ var->data.compact ?
DIV_ROUND_UP(glsl_get_length(type), 4)
+ :
glsl_count_attribute_slots(type, false);
+
+ if (idx == VARYING_SLOT_CLIP_DIST0)
+ slots = (nir->info.clip_distance_array_size +
+nir->info.cull_distance_array_size >
4) ? 2 : 1;
+
+ mark_tess_output(info, var->data.patch, param, slots);
+ break;
+ }
+ default:
+ break;
+ }
+ }
+}
+
+static void
gather_intrinsic_info(const nir_shader *nir, const nir_intrinsic_instr *instr,
struct radv_shader_info *info)
{
@@ -197,55 +274,11 @@ gather_intrinsic_info(const nir_shader *nir, const
nir_intrinsic_instr *instr,
info->ps.writes_memory = true;
break;
case nir_intrinsic_load_var:
- if (nir->info.stage == MESA_SHADER_VERTEX) {
- nir_deref_var *dvar = instr->variables[0];
- nir_variable *var = dvar->var;
-
- if (var->data.mode == nir_var_shader_in) {
- unsigned idx = var->data.location;
- uint8_t mask =
-
nir_ssa_def_components_read(&instr->dest.ssa) << var->data.location_frac;
- info->vs.input_usage_mask[idx] |= mask;
-
Mesa (master): radv: remove useless check in radv_create_shaders()
Module: Mesa
Branch: master
Commit: ece398277cf1de5ac4debfd9855909fd1bafb239
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ece398277cf1de5ac4debfd9855909fd1bafb239
Author: Samuel Pitoiset
Date: Fri May 11 16:36:52 2018 +0200
radv: remove useless check in radv_create_shaders()
radv_can_dump_shader() already handles if module is NULL.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Timothy Arceri
---
src/amd/vulkan/radv_pipeline.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index e6ac0721dc..3d242e05bf 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1984,7 +1984,7 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
radv_link_shaders(pipeline, nir);
for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
- if (modules[i] && radv_can_dump_shader(device, modules[i],
false))
+ if (radv_can_dump_shader(device, modules[i], false))
nir_print_shader(nir[i], stderr);
}
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