Mesa (master): pan/midgard: Use shared psiz clamp pass
Module: Mesa
Branch: master
Commit: 20237166b60a9fe525c906a3efd1046d2853c40a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=20237166b60a9fe525c906a3efd1046d2853c40a
Author: Alyssa Rosenzweig
Date: Mon Aug 26 12:14:11 2019 -0700
pan/midgard: Use shared psiz clamp pass
We already had a perfectly cromulent pass for this, but one landed in
common NIR code so let's switch and lighten our tree.
Signed-off-by: Alyssa Rosenzweig
---
src/gallium/drivers/panfrost/meson.build | 1 -
src/gallium/drivers/panfrost/nir/nir_clamp_psiz.c | 75 ---
src/panfrost/midgard/compiler.h | 5 --
src/panfrost/midgard/midgard_compile.c| 2 +-
4 files changed, 1 insertion(+), 82 deletions(-)
diff --git a/src/gallium/drivers/panfrost/meson.build
b/src/gallium/drivers/panfrost/meson.build
index 8d4facec982..c188274236b 100644
--- a/src/gallium/drivers/panfrost/meson.build
+++ b/src/gallium/drivers/panfrost/meson.build
@@ -29,7 +29,6 @@ files_panfrost = files(
'nir/nir_undef_to_zero.c',
'nir/nir_lower_blend.c',
'nir/nir_lower_framebuffer.c',
- 'nir/nir_clamp_psiz.c',
'pan_context.c',
'pan_afbc.c',
diff --git a/src/gallium/drivers/panfrost/nir/nir_clamp_psiz.c
b/src/gallium/drivers/panfrost/nir/nir_clamp_psiz.c
deleted file mode 100644
index 249a400a19e..000
--- a/src/gallium/drivers/panfrost/nir/nir_clamp_psiz.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (C) 2019 Collabora, Ltd.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-/**
- * @file
- *
- * Clamps writes to VARYING_SLOT_PSIZ to a given limit.
- */
-
-#include "compiler/nir/nir.h"
-#include "compiler/nir/nir_builder.h"
-
-void
-nir_clamp_psiz(nir_shader *shader, float min_size, float max_size);
-
-void
-nir_clamp_psiz(nir_shader *shader, float min_size, float max_size)
-{
- nir_foreach_function(func, shader) {
- nir_foreach_block(block, func->impl) {
- nir_foreach_instr_safe(instr, block) {
-if (instr->type != nir_instr_type_intrinsic)
- continue;
-
-nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
-if (intr->intrinsic != nir_intrinsic_store_deref)
- continue;
-
-nir_variable *var = nir_intrinsic_get_var(intr, 0);
-if (var->data.location != VARYING_SLOT_PSIZ)
- continue;
-
-nir_builder b;
-nir_builder_init(&b, func->impl);
-b.cursor = nir_before_instr(instr);
-
-nir_ssa_def *in_size = nir_ssa_for_src(&b, intr->src[1],
- intr->num_components);
-
-nir_ssa_def *clamped =
- nir_fmin(&b,
-nir_fmax(&b, in_size, nir_imm_float(&b, min_size)),
-nir_imm_float(&b, max_size));
-
-nir_instr_rewrite_src(instr, &intr->src[1],
- nir_src_for_ssa(clamped));
-
- }
- }
-
- nir_metadata_preserve(func->impl, nir_metadata_block_index |
-nir_metadata_dominance);
- }
-}
-
diff --git a/src/panfrost/midgard/compiler.h b/src/panfrost/midgard/compiler.h
index 97795b25cb9..b202a92aeea 100644
--- a/src/panfrost/midgard/compiler.h
+++ b/src/panfrost/midgard/compiler.h
@@ -635,14 +635,9 @@ void emit_binary_bundle(
struct util_dynarray *emission,
int next_tag);
-/* NIR stuff. TODO: Move? Share? Something? */
-
bool
nir_undef_to_zero(nir_shader *shader);
-void
-nir_clamp_psiz(nir_shader *shader, float min_size, float max_size);
-
/* Optimizations */
bool midgard_opt_copy_prop(compiler_context *ctx, midgard_block *block);
diff --git a/src/panfrost/midgard/midgard_compile.c
b/src/panfrost/midgard/midgard_compile.c
index eec3e8d56ed..79f33e8006e 100644
--- a/src/panfrost/midgard/midgard_compile.c
+++ b/src/panfrost/midgard/midgard_compile.c
@@ -2525,7 +2
Mesa (master): 28 new commits
URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b225f1892a677d9b735782c9d6aac4ee5d33c56 Author: Alyssa Rosenzweig Date: Fri Aug 30 13:49:33 2019 -0700 pan/midgard: Remove mir_opt_post_move_eliminate This optimization depended on RA running before scheduling. It therefore no longer applies and is now unused. Signed-off-by: Alyssa Rosenzweig URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d699a17475b5d123e6a22778e8ac6e005774ce92 Author: Alyssa Rosenzweig Date: Fri Aug 30 12:56:55 2019 -0700 pan/midgard: Schedule before RA This is a tradeoff. Scheduling before RA means we don't do RA on what-will-become pipeline registers. Importantly, it means the scheduler is able to reorder instructions, as registers have not been decided yet. Unfortunately, it also complicates register spilling, since the spills themselves won't get bundled optimally and we can only spill twice per ALU bundle (only one spill per bundle allowed here). It also prevents us from eliminating dead moves introduced by register allocation, as they are not dead before RA. The shader-db regressions are from poor spilling choices introduced by the new bundling requirements. These could be solved by the combination of a post-scheduler (to combine adjacent spills into bundles) with a VLIW-aware spill cost calculation. Nevertheless, the change is small enough that I feel it's worth it to eat a tiny shader-db regression for the sake of flexibility. Signed-off-by: Alyssa Rosenzweig URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e06d90c4510eb3a8c42b0e0d1a3ebfd19830069 Author: Alyssa Rosenzweig Date: Fri Aug 30 11:06:33 2019 -0700 pan/midgard: Handle fragment writeout in RA Rather than using a pile of hacks and awkward constructs in MIR to ensure the writeout parameter gets written into r0, let's add a dedicated shadow register class for writeout (interfering with work register r0) so we can express the writeout condition succintly and directly. Signed-off-by: Alyssa Rosenzweig URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=116b17d2d191892aeccf8fd5044a20f5a2d0c64f Author: Alyssa Rosenzweig Date: Fri Aug 30 14:35:01 2019 -0700 pan/midgard: Do not propagate swizzles into writeout There's no slot for it; you'll end up writing into the void and clobbering stuff. Don't. do it. Signed-off-by: Alyssa Rosenzweig URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb3cc20f42feb4a79c35ca717d4bda2430223d78 Author: Alyssa Rosenzweig Date: Fri Aug 30 11:04:52 2019 -0700 pan/midgard: Fix misc. RA issues When running the register allocator after scheduling, the MIR looks a little different, so we need to extend the RA to handle a few of these extra cases correctly. Signed-off-by: Alyssa Rosenzweig URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5ba016d3ab1abb9f97e7864fbe5ab96e3877ee7 Author: Alyssa Rosenzweig Date: Fri Aug 30 11:03:44 2019 -0700 pan/midgard: Print MIR by the bundle After scheduling, we still have valid MIR, but we have additional bundling annotations which we would like to keep debug, so print these. Signed-off-by: Alyssa Rosenzweig URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f42cebdd8424d3e0896bd0ddc214b2996bd07a73 Author: Alyssa Rosenzweig Date: Fri Aug 30 11:02:52 2019 -0700 pan/midgard: Print branches in MIR Rather than a vague "br.??" line, annotate the branch with its target type (useful for disambiguating discards) and whether it was inverted. Signed-off-by: Alyssa Rosenzweig URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=59f2cfcbc7d9da9b9e7c45ccc58c5cdaecbe92e8 Author: Alyssa Rosenzweig Date: Fri Aug 30 11:01:57 2019 -0700 pan/midgard: Remove texture_index This is deadcode. Signed-off-by: Alyssa Rosenzweig URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=76529836ecf53c977762283cf944a5c123c2b6db Author: Alyssa Rosenzweig Date: Fri Aug 30 11:01:15 2019 -0700 pan/midgard: Cleanup fragment writeout branch I'm not sure if this is strictly necessary but it makes debugging easier and minimizes the diff with the experimental scheduler. Signed-off-by: Alyssa Rosenzweig URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc2ba8efe96f2b44a6dc3d1e0b06c3a1ee9b8f50 Author: Alyssa Rosenzweig Date: Fri Aug 30 10:53:13 2019 -0700 pan/midgard: Add scheduling barriers Scheduling occurs on a per-block basis, strongly assuming that a given block contains at most a single branch. This does not always map to the source NIR control flow, particularly when discard intrinsics are involved. The solution is to allow scheduling barriers, which will terminate a block early in code generation a
Mesa (master): Revert "glx: Unset the direct_support bit for GLX_EXT_import_context"
Module: Mesa
Branch: master
Commit: da5ebe30105f70e3520ce3ae145793b72569
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=da5ebe30105f70e3520ce3ae145793b72569
Author: Adam Jackson
Date: Thu Aug 29 12:15:22 2019 -0400
Revert "glx: Unset the direct_support bit for GLX_EXT_import_context"
The GLX extension strings are independent of any context, so abusing the
direct_support bit to control this extension's visibility is wrong.
This reverts commit 079d0717fc896bc8086b037d0ed22642274986c7.
Reported-by: Michel Dänzer
Reviewed-by: Michel Dänzer
---
src/glx/glxextensions.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/glx/glxextensions.c b/src/glx/glxextensions.c
index a6fcc5f744b..f6a7a31a219 100644
--- a/src/glx/glxextensions.c
+++ b/src/glx/glxextensions.c
@@ -146,7 +146,7 @@ static const struct extension_info known_glx_extensions[] =
{
{ GLX(EXT_create_context_es_profile), VER(0,0), Y, N, N, N },
{ GLX(EXT_fbconfig_packed_float), VER(0,0), Y, Y, N, N },
{ GLX(EXT_framebuffer_sRGB),VER(0,0), Y, Y, N, N },
- { GLX(EXT_import_context), VER(0,0), Y, N, N, N },
+ { GLX(EXT_import_context), VER(0,0), Y, Y, N, N },
{ GLX(EXT_texture_from_pixmap), VER(0,0), Y, N, N, N },
{ GLX(EXT_visual_info), VER(0,0), Y, Y, N, N },
{ GLX(EXT_visual_rating), VER(0,0), Y, Y, N, N },
___
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Mesa (master): panfrost: Add transient BOs to job batches
Module: Mesa Branch: master Commit: 9087cf70153ebc412982dc38db3829adf27ebb39 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9087cf70153ebc412982dc38db3829adf27ebb39 Author: Boris Brezillon Date: Fri Aug 30 15:38:56 2019 +0200 panfrost: Add transient BOs to job batches Memory allocated through panfrost_allocate_transient() is likely to come from the transient pool. Let's add the BO backing the allocated memory region to the job batch so the kernel can retain this BO while jobs are executed. In practice that has never been a problem because the transient pool is never shrinked, and even if it was, we still control the lifetime of the job, so there's no reason for this BO to be freed before the GPU is done executing the batch. But it still make sense to add the BO for debugging purpose. Signed-off-by: Boris Brezillon Reviewed-by: Alyssa Rosenzweig --- src/gallium/drivers/panfrost/pan_allocate.c | 2 ++ src/gallium/drivers/panfrost/pan_drm.c | 1 - 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/panfrost/pan_allocate.c b/src/gallium/drivers/panfrost/pan_allocate.c index fb8b18fe718..78318ee1784 100644 --- a/src/gallium/drivers/panfrost/pan_allocate.c +++ b/src/gallium/drivers/panfrost/pan_allocate.c @@ -111,6 +111,8 @@ panfrost_allocate_transient(struct panfrost_context *ctx, size_t sz) bo = panfrost_create_slab(screen, &index); } +panfrost_job_add_bo(batch, bo); + /* Remember we created this */ util_dynarray_append(&batch->transient_indices, unsigned, index); diff --git a/src/gallium/drivers/panfrost/pan_drm.c b/src/gallium/drivers/panfrost/pan_drm.c index fc2e9255fac..4e692824809 100644 --- a/src/gallium/drivers/panfrost/pan_drm.c +++ b/src/gallium/drivers/panfrost/pan_drm.c @@ -298,7 +298,6 @@ panfrost_drm_submit_vs_fs_job(struct panfrost_context *ctx, bool has_draws) struct panfrost_job *job = panfrost_get_job_for_fbo(ctx); -/* TODO: Add here the transient pools */ panfrost_job_add_bo(job, ctx->scratchpad.bo); panfrost_job_add_bo(job, ctx->tiler_heap.bo); panfrost_job_add_bo(job, job->polygon_list); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): panfrost: Jobs must be per context, not per screen
Module: Mesa
Branch: master
Commit: 6b0dc3d53011b384798bcdb5d5e804d7482a3247
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b0dc3d53011b384798bcdb5d5e804d7482a3247
Author: Rohan Garg
Date: Fri Aug 30 18:00:12 2019 +0200
panfrost: Jobs must be per context, not per screen
Jobs _must_ only be shared across the same context, having
the last_job tracked in a screen causes use-after-free issues
and memory corruptions.
Signed-off-by: Rohan Garg
Reviewed-by: Boris Brezillon
Reviewed-by: Alyssa Rosenzweig
Signed-off-by: Boris Brezillon
---
src/gallium/drivers/panfrost/pan_context.c | 10 +-
src/gallium/drivers/panfrost/pan_context.h | 6 ++
src/gallium/drivers/panfrost/pan_drm.c | 6 +++---
src/gallium/drivers/panfrost/pan_screen.c | 3 ---
src/gallium/drivers/panfrost/pan_screen.h | 6 --
5 files changed, 14 insertions(+), 17 deletions(-)
diff --git a/src/gallium/drivers/panfrost/pan_context.c
b/src/gallium/drivers/panfrost/pan_context.c
index fa9c92af9f6..94ee9b5bdb2 100644
--- a/src/gallium/drivers/panfrost/pan_context.c
+++ b/src/gallium/drivers/panfrost/pan_context.c
@@ -1329,9 +1329,6 @@ panfrost_submit_frame(struct panfrost_context *ctx, bool
flush_immediate,
struct pipe_fence_handle **fence,
struct panfrost_job *job)
{
-struct pipe_context *gallium = (struct pipe_context *) ctx;
-struct panfrost_screen *screen = pan_screen(gallium->screen);
-
panfrost_job_submit(ctx, job);
/* If visual, we can stall a frame */
@@ -1339,8 +1336,8 @@ panfrost_submit_frame(struct panfrost_context *ctx, bool
flush_immediate,
if (!flush_immediate)
panfrost_drm_force_flush_fragment(ctx, fence);
-screen->last_fragment_flushed = false;
-screen->last_job = job;
+ctx->last_fragment_flushed = false;
+ctx->last_job = job;
/* If readback, flush now (hurts the pipelined performance) */
if (flush_immediate)
@@ -2856,6 +2853,9 @@ panfrost_create_context(struct pipe_screen *screen, void
*priv, unsigned flags)
assert(ctx->blitter);
assert(ctx->blitter_wallpaper);
+ctx->last_fragment_flushed = true;
+ctx->last_job = NULL;
+
/* Prepare for render! */
panfrost_job_init(ctx);
diff --git a/src/gallium/drivers/panfrost/pan_context.h
b/src/gallium/drivers/panfrost/pan_context.h
index 4c1580b3393..9f96e983a86 100644
--- a/src/gallium/drivers/panfrost/pan_context.h
+++ b/src/gallium/drivers/panfrost/pan_context.h
@@ -203,6 +203,12 @@ struct panfrost_context {
bool is_t6xx;
uint32_t out_sync;
+
+/* While we're busy building up the job for frame N, the GPU is
+ * still busy executing frame N-1. So hold a reference to
+ * yesterjob */
+int last_fragment_flushed;
+struct panfrost_job *last_job;
};
/* Corresponds to the CSO */
diff --git a/src/gallium/drivers/panfrost/pan_drm.c
b/src/gallium/drivers/panfrost/pan_drm.c
index 8e05fc936b2..fc2e9255fac 100644
--- a/src/gallium/drivers/panfrost/pan_drm.c
+++ b/src/gallium/drivers/panfrost/pan_drm.c
@@ -349,12 +349,12 @@ panfrost_drm_force_flush_fragment(struct panfrost_context
*ctx,
struct pipe_context *gallium = (struct pipe_context *) ctx;
struct panfrost_screen *screen = pan_screen(gallium->screen);
-if (!screen->last_fragment_flushed) {
+if (!ctx->last_fragment_flushed) {
drmSyncobjWait(screen->fd, &ctx->out_sync, 1, INT64_MAX, 0,
NULL);
-screen->last_fragment_flushed = true;
+ctx->last_fragment_flushed = true;
/* The job finished up, so we're safe to clean it up now */
-panfrost_free_job(ctx, screen->last_job);
+panfrost_free_job(ctx, ctx->last_job);
}
if (fence) {
diff --git a/src/gallium/drivers/panfrost/pan_screen.c
b/src/gallium/drivers/panfrost/pan_screen.c
index 36c91a1572e..5c288f52bbd 100644
--- a/src/gallium/drivers/panfrost/pan_screen.c
+++ b/src/gallium/drivers/panfrost/pan_screen.c
@@ -665,9 +665,6 @@ panfrost_create_screen(int fd, struct renderonly *ro)
screen->base.fence_finish = panfrost_fence_finish;
screen->base.set_damage_region = panfrost_resource_set_damage_region;
-screen->last_fragment_flushed = true;
-screen->last_job = NULL;
-
panfrost_resource_screen_init(screen);
return &screen->base;
diff --git a/src/gallium/drivers/panfrost/pan_screen.h
b/src/gallium/drivers/panfrost/pan_screen.h
index 02e8a96fabe..0a8da3362fb 100644
--- a/src/gallium/drivers/panfrost/pan_screen.h
+++ b/src/gallium/drivers/panfrost/pan_screen.h
@@ -118,12 +118,6 @@ struct panfrost_screen {
* Each bucket is a linked list of free panfrost_bo objects. */
struct list_head bo_cache[NR_BO_CACHE_BUCKETS];
-
-/* While we're busy building up th
Mesa (master): panfrost: protect access to shared bo cache and transient pool
Module: Mesa
Branch: master
Commit: b2ff2dfc2a8797260d7b87a5cc6188d891f713ff
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b2ff2dfc2a8797260d7b87a5cc6188d891f713ff
Author: Rohan Garg
Date: Fri Aug 30 18:00:13 2019 +0200
panfrost: protect access to shared bo cache and transient pool
Both the BO cache and the transient pool are shared across
context's. Protect access to these with mutexes.
Signed-off-by: Rohan Garg
Reviewed-by: Boris Brezillon
Reviewed-by: Alyssa Rosenzweig
Signed-off-by: Boris Brezillon
---
src/gallium/drivers/panfrost/pan_allocate.c | 2 ++
src/gallium/drivers/panfrost/pan_bo_cache.c | 16 +++-
src/gallium/drivers/panfrost/pan_job.c | 2 ++
src/gallium/drivers/panfrost/pan_screen.c | 4
src/gallium/drivers/panfrost/pan_screen.h | 4
5 files changed, 23 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/panfrost/pan_allocate.c
b/src/gallium/drivers/panfrost/pan_allocate.c
index f549c864c70..fb8b18fe718 100644
--- a/src/gallium/drivers/panfrost/pan_allocate.c
+++ b/src/gallium/drivers/panfrost/pan_allocate.c
@@ -74,6 +74,7 @@ panfrost_allocate_transient(struct panfrost_context *ctx,
size_t sz)
unsigned offset = 0;
bool update_offset = false;
+pthread_mutex_lock(&screen->transient_lock);
bool has_current = batch->transient_indices.size;
bool fits_in_current = (batch->transient_offset + sz) <
TRANSIENT_SLAB_SIZE;
@@ -131,6 +132,7 @@ panfrost_allocate_transient(struct panfrost_context *ctx,
size_t sz)
if (update_offset)
batch->transient_offset = offset + sz;
+pthread_mutex_unlock(&screen->transient_lock);
return ret;
diff --git a/src/gallium/drivers/panfrost/pan_bo_cache.c
b/src/gallium/drivers/panfrost/pan_bo_cache.c
index 9dd6b694b72..f2f49437a89 100644
--- a/src/gallium/drivers/panfrost/pan_bo_cache.c
+++ b/src/gallium/drivers/panfrost/pan_bo_cache.c
@@ -24,6 +24,7 @@
* Alyssa Rosenzweig
*/
#include
+#include
#include "drm-uapi/panfrost_drm.h"
#include "pan_screen.h"
@@ -84,7 +85,9 @@ panfrost_bo_cache_fetch(
struct panfrost_screen *screen,
size_t size, uint32_t flags)
{
+pthread_mutex_lock(&screen->bo_cache_lock);
struct list_head *bucket = pan_bucket(screen, size);
+struct panfrost_bo *bo = NULL;
/* Iterate the bucket looking for something suitable */
list_for_each_entry_safe(struct panfrost_bo, entry, bucket, link) {
@@ -106,12 +109,13 @@ panfrost_bo_cache_fetch(
continue;
}
/* Let's go! */
-return entry;
+bo = entry;
+break;
}
}
+pthread_mutex_unlock(&screen->bo_cache_lock);
-/* We didn't find anything */
-return NULL;
+return bo;
}
/* Tries to add a BO to the cache. Returns if it was
@@ -122,6 +126,7 @@ panfrost_bo_cache_put(
struct panfrost_screen *screen,
struct panfrost_bo *bo)
{
+pthread_mutex_lock(&screen->bo_cache_lock);
struct list_head *bucket = pan_bucket(screen, bo->size);
struct drm_panfrost_madvise madv;
@@ -133,6 +138,7 @@ panfrost_bo_cache_put(
/* Add us to the bucket */
list_addtail(&bo->link, bucket);
+pthread_mutex_unlock(&screen->bo_cache_lock);
return true;
}
@@ -147,6 +153,7 @@ void
panfrost_bo_cache_evict_all(
struct panfrost_screen *screen)
{
+pthread_mutex_lock(&screen->bo_cache_lock);
for (unsigned i = 0; i < ARRAY_SIZE(screen->bo_cache); ++i) {
struct list_head *bucket = &screen->bo_cache[i];
@@ -155,7 +162,6 @@ panfrost_bo_cache_evict_all(
panfrost_drm_release_bo(screen, entry, false);
}
}
-
-return;
+pthread_mutex_unlock(&screen->bo_cache_lock);
}
diff --git a/src/gallium/drivers/panfrost/pan_job.c
b/src/gallium/drivers/panfrost/pan_job.c
index f5bbd04b913..f7ff57c4331 100644
--- a/src/gallium/drivers/panfrost/pan_job.c
+++ b/src/gallium/drivers/panfrost/pan_job.c
@@ -67,10 +67,12 @@ panfrost_free_job(struct panfrost_context *ctx, struct
panfrost_job *job)
/* Free up the transient BOs we're sitting on */
struct panfrost_screen *screen = pan_screen(ctx->base.screen);
+pthread_mutex_lock(&screen->transient_lock);
util_dynarray_foreach(&job->transient_indices, unsigned, index) {
/* Mark it free */
BITSET_SET(screen->free_transient, *index);
}
+pthread_mutex_unlock(&screen->transient_lock);
/* Unreference the polygon list */
panfrost_bo_unreference(ctx->base.screen, job->polygon_list);
diff --git a/src/gallium/drivers/panfrost/pan_screen.c
b/src/galliu
Mesa (master): st/mesa: Allow zero as [level|layer]_override
Module: Mesa
Branch: master
Commit: bd98470a4692860004c1e9282808a638758c6f04
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd98470a4692860004c1e9282808a638758c6f04
Author: Lepton Wu
Date: Fri Aug 30 17:30:53 2019 +
st/mesa: Allow zero as [level|layer]_override
This fix two dEQP tests for virgl:
dEQP-EGL.functional.image.create.gles2_cubemap_positive_x_rgba_texture
dEQP-EGL.functional.image.render_multiple_contexts.gles2_cubemap_positive_x_rgba8_texture
Signed-off-by: Lepton Wu
Reviewed-by: Marek Olšák
---
src/mesa/state_tracker/st_cb_texture.c | 7 +--
src/mesa/state_tracker/st_sampler_view.c | 14 +++---
src/mesa/state_tracker/st_texture.h | 8
src/mesa/state_tracker/st_vdpau.c| 8
4 files changed, 20 insertions(+), 17 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_texture.c
b/src/mesa/state_tracker/st_cb_texture.c
index 1ace61863ff..3f1c73fe66d 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -157,6 +157,9 @@ st_NewTextureObject(struct gl_context * ctx, GLuint name,
GLenum target)
if (!obj)
return NULL;
+ obj->level_override = -1;
+ obj->layer_override = -1;
+
/* Pre-allocate a sampler views container to save a branch in the
* fast path.
*/
@@ -754,8 +757,8 @@ prep_teximage(struct gl_context *ctx, struct
gl_texture_image *texImage,
assert(!st_texture_image(texImage)->pt);
_mesa_clear_texture_object(ctx, texObj, texImage);
- stObj->layer_override = 0;
- stObj->level_override = 0;
+ stObj->layer_override = -1;
+ stObj->level_override = -1;
pipe_resource_reference(&stObj->pt, NULL);
/* oops, need to init this image again */
diff --git a/src/mesa/state_tracker/st_sampler_view.c
b/src/mesa/state_tracker/st_sampler_view.c
index 2fa08815085..664295dd852 100644
--- a/src/mesa/state_tracker/st_sampler_view.c
+++ b/src/mesa/state_tracker/st_sampler_view.c
@@ -527,13 +527,13 @@ st_create_texture_sampler_view_from_stobj(struct
st_context *st,
templ.format = format;
- if (stObj->level_override) {
+ if (stObj->level_override >= 0) {
templ.u.tex.first_level = templ.u.tex.last_level = stObj->level_override;
} else {
templ.u.tex.first_level = stObj->base.MinLevel + stObj->base.BaseLevel;
templ.u.tex.last_level = last_level(stObj);
}
- if (stObj->layer_override) {
+ if (stObj->layer_override >= 0) {
templ.u.tex.first_layer = templ.u.tex.last_layer = stObj->layer_override;
} else {
templ.u.tex.first_layer = stObj->base.MinLayer;
@@ -578,12 +578,12 @@ st_get_texture_sampler_view_from_stobj(struct st_context
*st,
assert(!check_sampler_swizzle(st, stObj, view, glsl130_or_later));
assert(get_sampler_view_format(st, stObj, srgb_skip_decode) ==
view->format);
assert(gl_target_to_pipe(stObj->base.Target) == view->target);
- assert(stObj->level_override ||
+ assert(stObj->level_override >= 0 ||
stObj->base.MinLevel + stObj->base.BaseLevel ==
view->u.tex.first_level);
- assert(stObj->level_override || last_level(stObj) ==
view->u.tex.last_level);
- assert(stObj->layer_override || stObj->base.MinLayer ==
view->u.tex.first_layer);
- assert(stObj->layer_override || last_layer(stObj) ==
view->u.tex.last_layer);
- assert(!stObj->layer_override ||
+ assert(stObj->level_override >= 0 || last_level(stObj) ==
view->u.tex.last_level);
+ assert(stObj->layer_override >= 0 || stObj->base.MinLayer ==
view->u.tex.first_layer);
+ assert(stObj->layer_override >= 0 || last_layer(stObj) ==
view->u.tex.last_layer);
+ assert(stObj->layer_override < 0 ||
(stObj->layer_override == view->u.tex.first_layer &&
stObj->layer_override == view->u.tex.last_layer));
return view;
diff --git a/src/mesa/state_tracker/st_texture.h
b/src/mesa/state_tracker/st_texture.h
index c5fc30cec5d..1fc36631c2e 100644
--- a/src/mesa/state_tracker/st_texture.h
+++ b/src/mesa/state_tracker/st_texture.h
@@ -164,15 +164,15 @@ struct st_texture_object
*/
enum pipe_format surface_format;
- /* When non-zero, samplers should use this level instead of the level
+ /* When non-negative, samplers should use this level instead of the level
* range specified by the GL state.
*
* This is used for EGL images, which may correspond to a single level out
* of an imported pipe_resources with multiple mip levels.
*/
- uint level_override;
+ int level_override;
- /* When non-zero, samplers should use this layer instead of the one
+ /* When non-negative, samplers should use this layer instead of the one
* specified by the GL state.
*
* This is used for EGL images and VDPAU interop, where imported
@@ -180,7 +180,7 @@ struct st_texture_object
* with different fields in the case of VDPAU) even though the GL state
* descr
Mesa (19.1): 21 new commits
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=52aea45dbcacdc5fc974432e62b548d19f06e9bf
Author: Pierre-Eric Pelloux-Prayer
Date: Wed Aug 28 10:56:52 2019 +0200
glsl: replace 'x + (-x)' with constant 0
This fixes a hang in shadertoy for radeonsi where a buffer was initialized
with:
value -= value
with value being undefined.
In this case LLVM replace the operation with an assignment to NaN.
Cc: 19.1 19.2
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111241
Reviewed-by: Marek Olšák
(cherry picked from commit 47cc660d9c19572e5ef2dce7c8ae1766a2ac9885)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=938adab8ea75dd473440efa8e7e8719982065eb1
Author: Ian Romanick
Date: Mon Aug 26 13:33:06 2019 -0700
intel/compiler: Request bitfield_reverse lowering on pre-Gen7 hardware
See the previous commit for the explanation of the Fixes tag.
Hurts 21 shaders in shader-db. All of the hurt shaders are in Unreal
Engine 4 tech demos.
Reviewed-by: Matt Turner
Fixes: 7afa26d4e39 ("nir: Add lowering for nir_op_bitfield_reverse.")
(cherry picked from commit b418269d7dd576a7c9afd728bf8a883b4da98b30)
Signed-off-by: Juan A. Suarez Romero
[Juan A. Suarez: resolve trivial conflicts]
Conflicts:
src/intel/compiler/brw_compiler.c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=759afcacd9eee8de364bd328ff8b4ba8214a17e9
Author: Ian Romanick
Date: Mon Aug 26 13:28:09 2019 -0700
nir/algrbraic: Don't optimize open-coded bitfield reverse when lowering is
enabled
This caused a problem on Sandybridge where an open-coded
bitfieldReverse() function could be optimized to a
nir_op_bitfield_reverse that would generate an unsupported BFREV
instruction in the backend. This was encountered in some Unreal4 tech
demos in shader-db. The bug was not previously noticed because we don't
actually try to run those demos on Sandybridge.
The fixes tag is a bit a lie. The actual bug was introduced about
26,000 commits earlier in 371c4b3c48f ("nir: Recognize open-coded
bitfield_reverse."). Without the NIR lowering pass, the flag needed to
avoid the optimization does not exist. Hopefully nobody will care to
fix this on an earlier Mesa release.
Reviewed-by: Matt Turner
Fixes: 7afa26d4e39 ("nir: Add lowering for nir_op_bitfield_reverse.")
(cherry picked from commit d3fd1c761aab01e06665180ab86c9528c0b285b2)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=48a671e2696f161090efd8eb3337f04d8af9aa3f
Author: Kenneth Graunke
Date: Mon Aug 26 15:21:40 2019 -0700
intel/compiler: Fix src0/desc setter ordering
src0 vstride and type overlap with bits of the extended descriptor.
brw_set_desc() also sets the extended descriptor to 0. So by setting
the descriptor, then setting src0, we were accidentally setting a bunch
of extended descriptor bits unintentionally.
When using this infrastructure for framebuffer writes (in a future
patch), this ended up setting the extended descriptor bit 20, which is
"Null Render Target" on Icelake, causing nothing to be written to the
framebuffer.
Reviewed-by: Jason Ekstrand
(cherry picked from commit c8c9c4868429f98e77f782637568e9eed2dd33f9)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6138702dec5852740911adc159ba342923baf874
Author: Kenneth Graunke
Date: Fri Aug 23 11:10:30 2019 -0700
mesa: Fix _mesa_float_to_unorm() on 32-bit systems.
This fixes the following CTS test on 32-bit systems:
GTF-GL46.gtf30.GL3Tests.packed_depth_stencil.packed_depth_stencil_init
It does glGetTexImage of a 16-bit SNORM image, requesting 32-bit UNORM
data. In get_tex_rgba_uncompressed, we round trip through float to
handle image transfer ops for clamping. _mesa_format_convert does:
_mesa_float_to_unorm(0.571428597f, 32)
which translated to:
_mesa_lroundevenf(0.571428597f * 0xu)
which produced different results on 64-bit and 32-bit systems:
64-bit: result = 0x92492500
32-bit: result = 0x8000
This is because the size of "long" varies between the two systems, and
0x92492500 is too large to fit in a signed 32-bit integer. To fix this,
we switch to the new _mesa_i64roundevenf function which always does the
64-bit operation.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104395
Fixes: 594fc0f8595 ("mesa: Replace F_TO_I() with _mesa_lroundevenf().")
Reviewed-by: Marek Olšák
Reviewed-by: Matt Turner
(cherry picked from commit e18cd5452aa4434fb22105eb939843381771b91c)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=68bd0c7b9df48657e76dfb3b02c4b0f928a9f803
Author: Kenneth Graunke
Date: Fri Aug 23 11:08:48 2019 -0700
util: Add a _mesa_i64roundevenf() h
Mesa (master): freedreno/a3xx: fix texture tiling parameters
Module: Mesa
Branch: master
Commit: ed1954ced38be473b64cefd5dc31e372601dfdc1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed1954ced38be473b64cefd5dc31e372601dfdc1
Author: Khaled Emara
Date: Sun Aug 25 23:39:02 2019 +0200
freedreno/a3xx: fix texture tiling parameters
* Fix 2D/2DArray/3D tiling parameters:
There is a bottom threshold for width and height.
* Renable tiling for Cubemap, after setting the right parameters.
Reviewed-by: Rob Clark
---
src/gallium/drivers/freedreno/a3xx/fd3_resource.c | 31 +++
1 file changed, 21 insertions(+), 10 deletions(-)
diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_resource.c
b/src/gallium/drivers/freedreno/a3xx/fd3_resource.c
index 5bde52c62be..4f8e195f199 100644
--- a/src/gallium/drivers/freedreno/a3xx/fd3_resource.c
+++ b/src/gallium/drivers/freedreno/a3xx/fd3_resource.c
@@ -41,16 +41,30 @@ setup_slices(struct fd_resource *rsc, uint32_t alignment,
enum pipe_format forma
uint32_t blocks;
if (rsc->tile_mode) {
- width = util_next_power_of_two(width);
- height = util_next_power_of_two(height);
- uint32_t tpitch = width * rsc->cpp;
- slice->pitch = (tpitch > 32) ? tpitch : 32;
+ if (prsc->target != PIPE_TEXTURE_CUBE) {
+ if (level == 0) {
+ width = util_next_power_of_two(width);
+ height = util_next_power_of_two(height);
+ }
+ width = MAX2(width, 8);
+ height = MAX2(height, 4);
+ // Multiplying by 4 is the result of the 4x4
tiling pattern.
+ slice->pitch = width * 4;
+ blocks = util_format_get_nblocks(format, width,
height);
+ } else {
+ uint32_t twidth, theight;
+ twidth = align(width, 8);
+ theight = align(height, 4);
+ // Multiplying by 4 is the result of the 4x4
tiling pattern.
+ slice->pitch = twidth * 4;
+ blocks = util_format_get_nblocks(format,
twidth, theight);
+ }
} else {
slice->pitch = width = align(width, pitchalign);
+ blocks = util_format_get_nblocks(format, slice->pitch,
height);
}
slice->offset = size;
- blocks = util_format_get_nblocks(format, slice->pitch, height);
/* 1d array and 2d array textures must all have the same layer
size
* for each miplevel on a3xx. 3d textures can have different
layer
* sizes for high levels, but the hw auto-sizer is buggy (or at
least
@@ -96,16 +110,13 @@ fd3_setup_slices(struct fd_resource *rsc)
}
static bool
-ok_format(enum pipe_format pfmt, const struct pipe_resource * tmpl)
+ok_format(enum pipe_format pfmt)
{
enum a3xx_color_fmt fmt = fd3_pipe2color(pfmt);
if (fmt == ~0)
return false;
- if (tmpl->target == PIPE_TEXTURE_CUBE)
- return false;
-
switch (pfmt) {
case PIPE_FORMAT_R8_UINT:
case PIPE_FORMAT_R8_SINT:
@@ -121,7 +132,7 @@ ok_format(enum pipe_format pfmt, const struct pipe_resource
* tmpl)
unsigned
fd3_tile_mode(const struct pipe_resource *tmpl)
{
- if (ok_format(tmpl->format, tmpl))
+ if (ok_format(tmpl->format))
return TILE_4X4;
return LINEAR;
}
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): freedreno/a3xx: fix sysmem <-> gmem tiles transfer
Module: Mesa Branch: master Commit: 6926f56d5bd02de66d1e928d79ffb8082eeb0211 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6926f56d5bd02de66d1e928d79ffb8082eeb0211 Author: Khaled Emara Date: Sun Aug 25 23:49:10 2019 +0200 freedreno/a3xx: fix sysmem <-> gmem tiles transfer Tiling mode was missing from fd3_emit_gmem_restore_tex(). emit_gmem2mem_surf() used LINEAR exclusiveley. Reviewed-by: Rob Clark --- src/gallium/drivers/freedreno/a3xx/fd3_emit.c | 3 ++- src/gallium/drivers/freedreno/a3xx/fd3_gmem.c | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c index a966934fe99..43de2273144 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_emit.c +++ b/src/gallium/drivers/freedreno/a3xx/fd3_emit.c @@ -315,7 +315,8 @@ fd3_emit_gmem_restore_tex(struct fd_ringbuffer *ring, debug_assert(psurf[i]->u.tex.first_layer == psurf[i]->u.tex.last_layer); - OUT_RING(ring, A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) | + OUT_RING(ring, A3XX_TEX_CONST_0_TILE_MODE(rsc->tile_mode) | +A3XX_TEX_CONST_0_FMT(fd3_pipe2tex(format)) | A3XX_TEX_CONST_0_TYPE(A3XX_TEX_2D) | fd3_tex_swiz(format, PIPE_SWIZZLE_X, PIPE_SWIZZLE_Y, PIPE_SWIZZLE_Z, PIPE_SWIZZLE_W)); diff --git a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c index 8bb8b681a28..33658f7dc8d 100644 --- a/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c +++ b/src/gallium/drivers/freedreno/a3xx/fd3_gmem.c @@ -346,7 +346,7 @@ emit_gmem2mem_surf(struct fd_batch *batch, OUT_RELOCW(ring, rsc->bo, offset, 0, -1);/* RB_COPY_DEST_BASE */ OUT_RING(ring, A3XX_RB_COPY_DEST_PITCH_PITCH(slice->pitch * rsc->cpp)); - OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(LINEAR) | + OUT_RING(ring, A3XX_RB_COPY_DEST_INFO_TILE(rsc->tile_mode) | A3XX_RB_COPY_DEST_INFO_FORMAT(fd3_pipe2color(format)) | A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(0xf) | A3XX_RB_COPY_DEST_INFO_ENDIAN(ENDIAN_NONE) | ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): gitlab-ci: Use new needs: keyword
Module: Mesa Branch: master Commit: 8de25ecd6b493c67f96d1f123535311964ba302e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8de25ecd6b493c67f96d1f123535311964ba302e Author: Michel Dänzer Date: Tue Aug 27 11:57:13 2019 +0200 gitlab-ci: Use new needs: keyword This way, the test jobs can start running before all build+test jobs have finished, once the meson-main job has. Idea suggested by Daniel Stone on IRC. See https://docs.gitlab.com/ce/ci/directed_acyclic_graph/ and https://docs.gitlab.com/ce/ci/yaml/README.html#needs for details. v2: * Improve commit log (Daniel Stone, Eric Engestrom) Reviewed-by: Eric Engestrom Reviewed-by: Eric Anholt --- .gitlab-ci.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index fd80edb37d7..6a5dde86ed3 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -353,6 +353,7 @@ test-llvmpipe-gles2: extends: .deqp-test dependencies: - meson-main + needs: [meson-main] test-softpipe-gles2: parallel: 4 @@ -365,6 +366,7 @@ test-softpipe-gles2: extends: .deqp-test dependencies: - meson-main + needs: [meson-main] # The GLES2 CTS run takes about 8 minutes of CPU time, while GLES3 is # 25 minutes. Until we can get its runtime down, just do a partial @@ -381,3 +383,4 @@ test-softpipe-gles3-limited: extends: .deqp-test dependencies: - meson-main + needs: [meson-main] ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): gitlab-ci: Move up meson-main job definition
Module: Mesa Branch: master Commit: 42f8d5a531c4996dfacda2f88f14f55fa9677e02 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=42f8d5a531c4996dfacda2f88f14f55fa9677e02 Author: Michel Dänzer Date: Wed Aug 28 12:01:02 2019 +0200 gitlab-ci: Move up meson-main job definition In order to increase the chance of it running early. Reviewed-by: Eric Engestrom Reviewed-by: Eric Anholt --- .gitlab-ci.yml | 58 +- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 8977b86341e..fd80edb37d7 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -111,6 +111,35 @@ debian: - scons $SCONS_TARGET - eval $SCONS_CHECK_COMMAND +meson-main: + extends: .meson-build + variables: +UNWIND: "true" +DRI_LOADERS: > + -D glx=dri + -D gbm=true + -D egl=true + -D platforms=x11,wayland,drm,surfaceless +DRI_DRIVERS: "i915,i965,r100,r200,nouveau" +GALLIUM_ST: > + -D dri3=true + -D gallium-extra-hud=true + -D gallium-vdpau=true + -D gallium-xvmc=true + -D gallium-omx=bellagio + -D gallium-va=true + -D gallium-xa=true + -D gallium-nine=true + -D gallium-opencl=disabled +GALLIUM_DRIVERS: "iris,nouveau,kmsro,r300,r600,freedreno,swrast,svga,v3d,vc4,virgl,etnaviv,panfrost,lima" +LLVM_VERSION: "7" +EXTRA_OPTION: > + -D osmesa=gallium + -D tools=all +MESON_SHADERDB: "true" +BUILDTYPE: "debugoptimized" + <<: *ci-deqp-artifacts + # NOTE: Building SWR is 2x (yes two) times slower than all the other # gallium drivers combined. # Start this early so that it doesn't limit the total run time. @@ -164,35 +193,6 @@ scons-win64: SCONS_TARGET: platform=windows machine=x86_64 SCONS_CHECK_COMMAND: "true" -meson-main: - extends: .meson-build - variables: -UNWIND: "true" -DRI_LOADERS: > - -D glx=dri - -D gbm=true - -D egl=true - -D platforms=x11,wayland,drm,surfaceless -DRI_DRIVERS: "i915,i965,r100,r200,nouveau" -GALLIUM_ST: > - -D dri3=true - -D gallium-extra-hud=true - -D gallium-vdpau=true - -D gallium-xvmc=true - -D gallium-omx=bellagio - -D gallium-va=true - -D gallium-xa=true - -D gallium-nine=true - -D gallium-opencl=disabled -GALLIUM_DRIVERS: "iris,nouveau,kmsro,r300,r600,freedreno,swrast,svga,v3d,vc4,virgl,etnaviv,panfrost,lima" -LLVM_VERSION: "7" -EXTRA_OPTION: > - -D osmesa=gallium - -D tools=all -MESON_SHADERDB: "true" -BUILDTYPE: "debugoptimized" - <<: *ci-deqp-artifacts - meson-clover: extends: .meson-build variables: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): broadcom/v3d: Allow importing linear BOs with arbitrary offset/stride.
Module: Mesa
Branch: master
Commit: 873b092e9110a0605293db7bc1c5bcb749cf9a28
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=873b092e9110a0605293db7bc1c5bcb749cf9a28
Author: Dave Stevenson
Date: Wed May 22 17:12:56 2019 +0100
broadcom/v3d: Allow importing linear BOs with arbitrary offset/stride.
Equivalent of 0c1dd9dee "broadcom/vc4: Allow importing linear BOs with
arbitrary offset/stride." for v3d.
Allows YUV buffers with a single buffer and plane offsets to be
passed in.
Signed-off-by: Dave Stevenson
Reviewed-by: Eric Anholt
---
src/gallium/drivers/v3d/v3d_resource.c | 31 +++
1 file changed, 23 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/v3d/v3d_resource.c
b/src/gallium/drivers/v3d/v3d_resource.c
index 064709dff12..c2590fac1e5 100644
--- a/src/gallium/drivers/v3d/v3d_resource.c
+++ b/src/gallium/drivers/v3d/v3d_resource.c
@@ -842,13 +842,6 @@ v3d_resource_from_handle(struct pipe_screen *pscreen,
goto fail;
}
-if (whandle->offset != 0) {
-fprintf(stderr,
-"Attempt to import unsupported winsys offset %u\n",
-whandle->offset);
-goto fail;
-}
-
switch (whandle->type) {
case WINSYS_HANDLE_TYPE_SHARED:
rsc->bo = v3d_bo_open_name(screen, whandle->handle);
@@ -871,6 +864,26 @@ v3d_resource_from_handle(struct pipe_screen *pscreen,
v3d_setup_slices(rsc, whandle->stride, true);
v3d_debug_resource_layout(rsc, "import");
+if (whandle->offset != 0) {
+if (rsc->tiled) {
+fprintf(stderr,
+"Attempt to import unsupported winsys offset
%u\n",
+whandle->offset);
+goto fail;
+}
+rsc->slices[0].offset += whandle->offset;
+
+if (rsc->slices[0].offset + rsc->slices[0].size >
+rsc->bo->size) {
+fprintf(stderr, "Attempt to import "
+"with overflowing offset (%d + %d > %d)\n",
+whandle->offset,
+rsc->slices[0].size,
+rsc->bo->size);
+ goto fail;
+ }
+}
+
if (screen->ro) {
/* Make sure that renderonly has a handle to our buffer in the
* display's fd, so that a later renderonly_get_handle()
@@ -886,7 +899,7 @@ v3d_resource_from_handle(struct pipe_screen *pscreen,
}
}
-if (whandle->stride != slice->stride) {
+if (rsc->tiled && whandle->stride != slice->stride) {
static bool warned = false;
if (!warned) {
warned = true;
@@ -899,6 +912,8 @@ v3d_resource_from_handle(struct pipe_screen *pscreen,
slice->stride);
}
goto fail;
+} else if (!rsc->tiled) {
+slice->stride = whandle->stride;
}
return prsc;
___
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Mesa (master): swr/rasterizer: Fix GS attributes processing
Module: Mesa
Branch: master
Commit: 2263e6a8955b2fc5706879978d5c7db7de850266
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2263e6a8955b2fc5706879978d5c7db7de850266
Author: Jan Zielinski
Date: Fri Aug 2 11:59:03 2019 +0200
swr/rasterizer: Fix GS attributes processing
Input to GS is just a set of attributes, so remove explicit setup of
'position' which is meaningless for GS input processing.
Reviewed-by: Alok Hota
---
src/gallium/drivers/swr/rasterizer/core/frontend.cpp | 16
src/gallium/drivers/swr/rasterizer/core/state.h | 11 +++
src/gallium/drivers/swr/swr_shader.cpp | 7 +++
3 files changed, 10 insertions(+), 24 deletions(-)
diff --git a/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
b/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
index 1aa98f49fd7..13e92e8640a 100644
--- a/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
+++ b/src/gallium/drivers/swr/rasterizer/core/frontend.cpp
@@ -851,29 +851,21 @@ static void GeometryShaderStage(DRAW_CONTEXT* pDC,
gsContext.inputVertStride = pState->inputVertStride;
for (uint32_t slot = 0; slot < pState->numInputAttribs; ++slot)
{
-uint32_t srcAttribSlot = pState->srcVertexAttribOffset + slot;
-uint32_t attribSlot= pState->vertexAttribOffset + slot;
-pa.Assemble(srcAttribSlot, attrib);
+uint32_t attribOffset = slot + pState->vertexAttribOffset;
+pa.Assemble(attribOffset, attrib);
for (uint32_t i = 0; i < numVertsPerPrim; ++i)
{
-gsContext.pVerts[attribSlot + pState->inputVertStride * i] =
attrib[i];
+gsContext.pVerts[attribOffset + pState->inputVertStride * i] =
attrib[i];
}
}
-// assemble position
-pa.Assemble(VERTEX_POSITION_SLOT, attrib);
-for (uint32_t i = 0; i < numVertsPerPrim; ++i)
-{
-gsContext.pVerts[VERTEX_POSITION_SLOT + pState->inputVertStride * i] =
attrib[i];
-}
-
// record valid prims from the frontend to avoid over binning the newly
generated
// prims from the GS
#if USE_SIMD16_FRONTEND
uint32_t numInputPrims = numPrims_simd8;
#else
-uint32_t numInputPrims = pa.NumPrims();
+uint32_t numInputPrims = pa.NumPrims();
#endif
for (uint32_t instance = 0; instance < pState->instanceCount; ++instance)
diff --git a/src/gallium/drivers/swr/rasterizer/core/state.h
b/src/gallium/drivers/swr/rasterizer/core/state.h
index 66144bbef75..66a23bd9b08 100644
--- a/src/gallium/drivers/swr/rasterizer/core/state.h
+++ b/src/gallium/drivers/swr/rasterizer/core/state.h
@@ -747,13 +747,11 @@ struct SWR_GS_STATE
// Total amount of memory to allocate for one instance of the shader
output in bytes
uint32_t allocationSize;
-// Offset to the start of the attributes of the input vertices, in
simdvector units, as read by
-// the GS
+// Offset to start reading data per input vertex in simdvector units. This
can be used to
+// skip over any vertex data output from the previous stage that is unused
in the GS, removing
+// unnecessary vertex processing.
uint32_t vertexAttribOffset;
-// Offset to the attributes as stored by the preceding shader stage.
-uint32_t srcVertexAttribOffset;
-
// Size of the control data section which contains cut or streamID data,
in simdscalar units.
// Should be sized to handle the maximum number of verts output by the GS.
Can be 0 if there are
// no cuts or streamID bits.
@@ -772,10 +770,7 @@ struct SWR_GS_STATE
// shader is expected to store the final vertex count in the first dword
of the gs output
// stream.
uint32_t staticVertexCount;
-
-uint32_t pad;
};
-static_assert(sizeof(SWR_GS_STATE) == 64, "Adjust padding to keep size (or
remove this assert)");
//
/// SWR_TS_OUTPUT_TOPOLOGY - Defines data output by the tessellator / DS
diff --git a/src/gallium/drivers/swr/swr_shader.cpp
b/src/gallium/drivers/swr/swr_shader.cpp
index cbffaef0b12..9b27652d8bc 100644
--- a/src/gallium/drivers/swr/swr_shader.cpp
+++ b/src/gallium/drivers/swr/swr_shader.cpp
@@ -555,7 +555,7 @@ BuilderSWR::CompileGS(struct swr_context *ctx,
swr_jit_gs_key &key)
pGS->gsEnable = true;
- pGS->numInputAttribs = info->num_inputs;
+ pGS->numInputAttribs = (VERTEX_ATTRIB_START_SLOT - VERTEX_POSITION_SLOT) +
info->num_inputs;
pGS->outputTopology =
swr_convert_prim_topology(info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM]);
pGS->maxNumVerts = info->properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
@@ -565,8 +565,7 @@ BuilderSWR::CompileGS(struct swr_context *ctx,
swr_jit_gs_key &key)
pGS->isSingleStream = true;
pGS->singleStreamID = 0;
- pGS->vertexAttribOffset = VERTEX_ATTRIB_START_SLOT; // TODO: optimize
- pGS->srcVertexAttribOffset = VERTEX_ATTRIB_START_SLOT; // TODO: optimize
+ pGS->vertexAttribOffset =
Mesa (staging/19.1): glsl: replace 'x + (-x)' with constant 0
Module: Mesa
Branch: staging/19.1
Commit: 52aea45dbcacdc5fc974432e62b548d19f06e9bf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=52aea45dbcacdc5fc974432e62b548d19f06e9bf
Author: Pierre-Eric Pelloux-Prayer
Date: Wed Aug 28 10:56:52 2019 +0200
glsl: replace 'x + (-x)' with constant 0
This fixes a hang in shadertoy for radeonsi where a buffer was initialized with:
value -= value
with value being undefined.
In this case LLVM replace the operation with an assignment to NaN.
Cc: 19.1 19.2
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111241
Reviewed-by: Marek Olšák
(cherry picked from commit 47cc660d9c19572e5ef2dce7c8ae1766a2ac9885)
---
src/compiler/glsl/opt_algebraic.cpp | 12
1 file changed, 12 insertions(+)
diff --git a/src/compiler/glsl/opt_algebraic.cpp
b/src/compiler/glsl/opt_algebraic.cpp
index ff4be269578..3147d25aea8 100644
--- a/src/compiler/glsl/opt_algebraic.cpp
+++ b/src/compiler/glsl/opt_algebraic.cpp
@@ -507,6 +507,18 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir)
if (is_vec_zero(op_const[1]))
return ir->operands[0];
+ /* Replace (x + (-x)) with constant 0 */
+ for (int i = 0; i < 2; i++) {
+ if (op_expr[i]) {
+if (op_expr[i]->operation == ir_unop_neg) {
+ ir_rvalue *other = ir->operands[(i + 1) % 2];
+ if (other && op_expr[i]->operands[0]->equals(other)) {
+ return ir_constant::zero(ir, ir->type);
+ }
+}
+ }
+ }
+
/* Reassociate addition of constants so that we can do constant
* folding.
*/
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Mesa (master): radv: remove useless ac_llvm_util.h include from the WSI code
Module: Mesa Branch: master Commit: dc27a54c847a2473fa7b1aaebec8b389e450a88c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc27a54c847a2473fa7b1aaebec8b389e450a88c Author: Samuel Pitoiset Date: Thu Aug 29 11:46:46 2019 +0200 radv: remove useless ac_llvm_util.h include from the WSI code Signed-off-by: Samuel Pitoiset Reviewed-by: Dave Airlie --- src/amd/vulkan/radv_wsi_display.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/amd/vulkan/radv_wsi_display.c b/src/amd/vulkan/radv_wsi_display.c index 2d5167d5f5f..101da601ee5 100644 --- a/src/amd/vulkan/radv_wsi_display.c +++ b/src/amd/vulkan/radv_wsi_display.c @@ -34,7 +34,6 @@ #include #include #include "winsys/amdgpu/radv_amdgpu_winsys_public.h" -#include "ac_llvm_util.h" #include "vk_format.h" #include "sid.h" #include "util/debug.h" ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: remove some unused fields from radv_shader_context
Module: Mesa
Branch: master
Commit: 9aaca9012369843cf15bd773d37c15d0bb322261
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9aaca9012369843cf15bd773d37c15d0bb322261
Author: Samuel Pitoiset
Date: Wed Aug 28 16:46:15 2019 +0200
radv: remove some unused fields from radv_shader_context
Signed-off-by: Samuel Pitoiset
Reviewed-by: Dave Airlie
---
src/amd/vulkan/radv_nir_to_llvm.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index 9378bab1a04..c409a02e4d1 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -95,9 +95,7 @@ struct radv_shader_context {
gl_shader_stage stage;
LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
- uint64_t float16_shaded_mask;
- uint64_t input_mask;
uint64_t output_mask;
bool is_gs_copy_shader;
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Mesa (master): radv: remove unused shader_info parameter in ac_compile_llvm_module()
Module: Mesa Branch: master Commit: 6cb455c418b207e5829be44ec118dd2b253a1a07 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6cb455c418b207e5829be44ec118dd2b253a1a07 Author: Samuel Pitoiset Date: Fri Jul 26 14:48:23 2019 +0200 radv: remove unused shader_info parameter in ac_compile_llvm_module() Signed-off-by: Samuel Pitoiset Reviewed-by: Dave Airlie --- src/amd/vulkan/radv_nir_to_llvm.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/amd/vulkan/radv_nir_to_llvm.c b/src/amd/vulkan/radv_nir_to_llvm.c index c409a02e4d1..8a9960ddca2 100644 --- a/src/amd/vulkan/radv_nir_to_llvm.c +++ b/src/amd/vulkan/radv_nir_to_llvm.c @@ -4559,7 +4559,6 @@ static unsigned radv_llvm_compile(LLVMModuleRef M, static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm, LLVMModuleRef llvm_module, struct radv_shader_binary **rbinary, - struct radv_shader_variant_info *shader_info, gl_shader_stage stage, const char *name, const struct radv_nir_compiler_options *options) @@ -4662,7 +4661,7 @@ radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm, llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, shader_info, options); - ac_compile_llvm_module(ac_llvm, llvm_module, rbinary, shader_info, + ac_compile_llvm_module(ac_llvm, llvm_module, rbinary, nir[nir_count - 1]->info.stage, radv_get_shader_name(shader_info, nir[nir_count - 1]->info.stage), @@ -4816,7 +4815,7 @@ radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm, ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options); - ac_compile_llvm_module(ac_llvm, ctx.ac.module, rbinary, shader_info, + ac_compile_llvm_module(ac_llvm, ctx.ac.module, rbinary, MESA_SHADER_VERTEX, "GS Copy Shader", options); (*rbinary)->is_gs_copy_shader = true; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radv: move setting can_discard to ac_fill_shader_info()
Module: Mesa
Branch: master
Commit: 7b1655ccf3471a7c961612197b7227fd0e4abb35
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b1655ccf3471a7c961612197b7227fd0e4abb35
Author: Samuel Pitoiset
Date: Wed Aug 28 16:52:30 2019 +0200
radv: move setting can_discard to ac_fill_shader_info()
Signed-off-by: Samuel Pitoiset
Reviewed-by: Dave Airlie
---
src/amd/vulkan/radv_nir_to_llvm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index b4ee28f4d37..1c1633a51e7 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -4298,7 +4298,6 @@ LLVMModuleRef ac_translate_nir_to_llvm(struct
ac_llvm_compiler *ac_llvm,
} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
ctx.abi.load_base_vertex = radv_load_base_vertex;
} else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
- shader_info->fs.can_discard =
shaders[i]->info.fs.uses_discard;
ctx.abi.load_sample_position = load_sample_position;
ctx.abi.load_sample_mask_in = load_sample_mask_in;
ctx.abi.emit_kill = radv_emit_kill;
@@ -4521,6 +4520,7 @@ ac_fill_shader_info(struct radv_shader_variant_info
*shader_info, struct nir_sha
shader_info->cs.block_size[i] =
nir->info.cs.local_size[i];
break;
case MESA_SHADER_FRAGMENT:
+ shader_info->fs.can_discard = nir->info.fs.uses_discard;
shader_info->fs.early_fragment_test =
nir->info.fs.early_fragment_tests;
shader_info->fs.post_depth_coverage =
nir->info.fs.post_depth_coverage;
break;
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Mesa (master): radv: keep a pointer to a NIR shader into radv_shader_context
Module: Mesa
Branch: master
Commit: 6b96c94b5a8ef29a9cb710f59f4b5b7a5aeb47b1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b96c94b5a8ef29a9cb710f59f4b5b7a5aeb47b1
Author: Samuel Pitoiset
Date: Wed Aug 28 17:08:29 2019 +0200
radv: keep a pointer to a NIR shader into radv_shader_context
This avoids multiple copies for nothing and it's more elegant.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Dave Airlie
---
src/amd/vulkan/radv_nir_to_llvm.c | 60 ---
1 file changed, 24 insertions(+), 36 deletions(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index 1c1633a51e7..047a77d6c96 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -49,6 +49,7 @@ struct radv_shader_context {
struct ac_llvm_context ac;
const struct radv_nir_compiler_options *options;
struct radv_shader_variant_info *shader_info;
+ const struct nir_shader *shader;
struct ac_shader_abi abi;
unsigned max_workgroup_size;
@@ -104,14 +105,7 @@ struct radv_shader_context {
LLVMValueRef gs_generated_prims[4];
LLVMValueRef gs_ngg_emit;
LLVMValueRef gs_ngg_scratch;
- unsigned gs_max_out_vertices;
- unsigned gs_output_prim;
- unsigned tes_primitive_mode;
-
- uint32_t tcs_patch_outputs_read;
- uint64_t tcs_outputs_read;
- uint32_t tcs_vertices_per_patch;
uint32_t tcs_num_inputs;
uint32_t tcs_num_patches;
uint32_t max_gsvs_emit_size;
@@ -159,13 +153,13 @@ static unsigned
get_tcs_num_patches(struct radv_shader_context *ctx)
{
unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
- unsigned num_tcs_output_cp = ctx->tcs_vertices_per_patch;
+ unsigned num_tcs_output_cp = ctx->shader->info.tess.tcs_vertices_out;
uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
uint32_t input_patch_size = ctx->options->key.tcs.input_vertices *
input_vertex_size;
uint32_t num_tcs_outputs =
util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
uint32_t num_tcs_patch_outputs =
util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
uint32_t output_vertex_size = num_tcs_outputs * 16;
- uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch *
output_vertex_size;
+ uint32_t pervertex_output_patch_size =
ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
uint32_t output_patch_size = pervertex_output_patch_size +
num_tcs_patch_outputs * 16;
unsigned num_patches;
unsigned hardware_lds_size;
@@ -217,7 +211,7 @@ calculate_tess_lds_size(struct radv_shader_context *ctx)
unsigned num_patches;
unsigned lds_size;
- num_tcs_output_cp = ctx->tcs_vertices_per_patch;
+ num_tcs_output_cp = ctx->shader->info.tess.tcs_vertices_out;
num_tcs_outputs =
util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
num_tcs_patch_outputs =
util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
@@ -273,7 +267,7 @@ get_tcs_out_patch_stride(struct radv_shader_context *ctx)
uint32_t num_tcs_outputs =
util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
uint32_t num_tcs_patch_outputs =
util_last_bit64(ctx->shader_info->info.tcs.patch_outputs_written);
uint32_t output_vertex_size = num_tcs_outputs * 16;
- uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch *
output_vertex_size;
+ uint32_t pervertex_output_patch_size =
ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
uint32_t output_patch_size = pervertex_output_patch_size +
num_tcs_patch_outputs * 16;
output_patch_size /= 4;
return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
@@ -312,7 +306,7 @@ get_tcs_out_patch0_patch_data_offset(struct
radv_shader_context *ctx)
uint32_t num_tcs_outputs =
util_last_bit64(ctx->shader_info->info.tcs.outputs_written);
uint32_t output_vertex_size = num_tcs_outputs * 16;
- uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch *
output_vertex_size;
+ uint32_t pervertex_output_patch_size =
ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
unsigned num_patches = ctx->tcs_num_patches;
output_patch0_offset *= num_patches;
@@ -1333,7 +1327,7 @@ static LLVMValueRef get_non_vertex_index_offset(struct
radv_shader_context *ctx)
num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
uint32_t output_vertex_size = num_tcs_outputs * 16;
- uint32_t pervertex_output_patch_size = ctx->tcs_vertices_per_patch *
output_vertex_size;
+ uint32_t pervertex_output_patch_size =
ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size *
num_patches, false);
}
@@ -1343,7 +1337,
Mesa (master): radv: remove radv_init_llvm_target() helper
Module: Mesa
Branch: master
Commit: cc3d36b5ddd7202c6b65111f58fce0e53690570f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc3d36b5ddd7202c6b65111f58fce0e53690570f
Author: Samuel Pitoiset
Date: Thu Aug 29 11:49:03 2019 +0200
radv: remove radv_init_llvm_target() helper
RADV no longer uses specific LLVM options compared to the common code.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Dave Airlie
---
src/amd/vulkan/radv_shader.c | 34 +-
1 file changed, 1 insertion(+), 33 deletions(-)
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 82858bc906a..e907c04863a 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -859,38 +859,6 @@ static void radv_postprocess_config(const struct
radv_physical_device *pdevice,
}
}
-static void radv_init_llvm_target()
-{
- LLVMInitializeAMDGPUTargetInfo();
- LLVMInitializeAMDGPUTarget();
- LLVMInitializeAMDGPUTargetMC();
- LLVMInitializeAMDGPUAsmPrinter();
-
- /* For inline assembly. */
- LLVMInitializeAMDGPUAsmParser();
-
- /* Workaround for bug in llvm 4.0 that causes image intrinsics
-* to disappear.
-* https://reviews.llvm.org/D26348
-*
-* Workaround for bug in llvm that causes the GPU to hang in presence
-* of nested loops because there is an exec mask issue. The proper
-* solution is to fix LLVM but this might require a bunch of work.
-* https://bugs.llvm.org/show_bug.cgi?id=37744
-*
-* "mesa" is the prefix for error messages.
-*/
- const char *argv[2] = { "mesa", "-simplifycfg-sink-common=false" };
- LLVMParseCommandLineOptions(2, argv, NULL);
-}
-
-static once_flag radv_init_llvm_target_once_flag = ONCE_FLAG_INIT;
-
-static void radv_init_llvm_once(void)
-{
- call_once(&radv_init_llvm_target_once_flag, radv_init_llvm_target);
-}
-
struct radv_shader_variant *
radv_shader_variant_create(struct radv_device *device,
const struct radv_shader_binary *binary,
@@ -1103,7 +1071,7 @@ shader_variant_compile(struct radv_device *device,
tm_options |= AC_TM_NO_LOAD_STORE_OPT;
thread_compiler = !(device->instance->debug_flags &
RADV_DEBUG_NOTHREADLLVM);
- radv_init_llvm_once();
+ ac_init_llvm_once();
radv_init_llvm_compiler(&ac_llvm,
thread_compiler,
chip_family, tm_options,
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Mesa (master): radv: replace ac_nir_build_if by ac_build_ifcc
Module: Mesa
Branch: master
Commit: 081561de16e077ab613accf8b8f8f5d5df81ea42
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=081561de16e077ab613accf8b8f8f5d5df81ea42
Author: Samuel Pitoiset
Date: Thu Aug 29 13:32:10 2019 +0200
radv: replace ac_nir_build_if by ac_build_ifcc
Signed-off-by: Samuel Pitoiset
Reviewed-by: Dave Airlie
---
src/amd/vulkan/radv_nir_to_llvm.c | 120 +-
1 file changed, 13 insertions(+), 107 deletions(-)
diff --git a/src/amd/vulkan/radv_nir_to_llvm.c
b/src/amd/vulkan/radv_nir_to_llvm.c
index 8a9960ddca2..b4ee28f4d37 100644
--- a/src/amd/vulkan/radv_nir_to_llvm.c
+++ b/src/amd/vulkan/radv_nir_to_llvm.c
@@ -142,98 +142,6 @@ radv_shader_context_from_abi(struct ac_shader_abi *abi)
return container_of(abi, ctx, abi);
}
-struct ac_build_if_state
-{
- struct radv_shader_context *ctx;
- LLVMValueRef condition;
- LLVMBasicBlockRef entry_block;
- LLVMBasicBlockRef true_block;
- LLVMBasicBlockRef false_block;
- LLVMBasicBlockRef merge_block;
-};
-
-static LLVMBasicBlockRef
-ac_build_insert_new_block(struct radv_shader_context *ctx, const char *name)
-{
- LLVMBasicBlockRef current_block;
- LLVMBasicBlockRef next_block;
- LLVMBasicBlockRef new_block;
-
- /* get current basic block */
- current_block = LLVMGetInsertBlock(ctx->ac.builder);
-
- /* chqeck if there's another block after this one */
- next_block = LLVMGetNextBasicBlock(current_block);
- if (next_block) {
- /* insert the new block before the next block */
- new_block = LLVMInsertBasicBlockInContext(ctx->context,
next_block, name);
- }
- else {
- /* append new block after current block */
- LLVMValueRef function = LLVMGetBasicBlockParent(current_block);
- new_block = LLVMAppendBasicBlockInContext(ctx->context,
function, name);
- }
- return new_block;
-}
-
-static void
-ac_nir_build_if(struct ac_build_if_state *ifthen,
- struct radv_shader_context *ctx,
- LLVMValueRef condition)
-{
- LLVMBasicBlockRef block = LLVMGetInsertBlock(ctx->ac.builder);
-
- memset(ifthen, 0, sizeof *ifthen);
- ifthen->ctx = ctx;
- ifthen->condition = condition;
- ifthen->entry_block = block;
-
- /* create endif/merge basic block for the phi functions */
- ifthen->merge_block = ac_build_insert_new_block(ctx, "endif-block");
-
- /* create/insert true_block before merge_block */
- ifthen->true_block =
- LLVMInsertBasicBlockInContext(ctx->context,
- ifthen->merge_block,
- "if-true-block");
-
- /* successive code goes into the true block */
- LLVMPositionBuilderAtEnd(ctx->ac.builder, ifthen->true_block);
-}
-
-/**
- * End a conditional.
- */
-static void
-ac_nir_build_endif(struct ac_build_if_state *ifthen)
-{
- LLVMBuilderRef builder = ifthen->ctx->ac.builder;
-
- /* Insert branch to the merge block from current block */
- LLVMBuildBr(builder, ifthen->merge_block);
-
- /*
-* Now patch in the various branch instructions.
-*/
-
- /* Insert the conditional branch instruction at the end of entry_block
*/
- LLVMPositionBuilderAtEnd(builder, ifthen->entry_block);
- if (ifthen->false_block) {
- /* we have an else clause */
- LLVMBuildCondBr(builder, ifthen->condition,
- ifthen->true_block, ifthen->false_block);
- }
- else {
- /* no else clause */
- LLVMBuildCondBr(builder, ifthen->condition,
- ifthen->true_block, ifthen->merge_block);
- }
-
- /* Resume building code at end of the ifthen->merge_block */
- LLVMPositionBuilderAtEnd(builder, ifthen->merge_block);
-}
-
-
static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
{
switch (ctx->stage) {
@@ -2637,7 +2545,6 @@ radv_emit_stream_output(struct radv_shader_context *ctx,
static void
radv_emit_streamout(struct radv_shader_context *ctx, unsigned stream)
{
- struct ac_build_if_state if_ctx;
int i;
/* Get bits [22:16], i.e. (so_param >> 16) & 127; */
@@ -2657,7 +2564,7 @@ radv_emit_streamout(struct radv_shader_context *ctx,
unsigned stream)
* out-of-bounds buffer access. The hw tells us via the SGPR
* (so_vtx_count) which threads are allowed to emit streamout data.
*/
- ac_nir_build_if(&if_ctx, ctx, can_emit);
+ ac_build_ifcc(&ctx->ac, can_emit, 6501);
{
/* The buffer offset is computed as follows:
* ByteOffset = streamout_offset[buffer_id]*4 +
@@ -2719,7 +2626,7 @@ radv_emit_streamout(struct radv_shader_context *ctx,
unsigned stream)
Mesa (master): radv: move lowering PS inputs/outputs at the right place
Module: Mesa
Branch: master
Commit: 8d44f838443d8d403ed20f1414916bf59f660901
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d44f838443d8d403ed20f1414916bf59f660901
Author: Samuel Pitoiset
Date: Thu Aug 29 11:16:44 2019 +0200
radv: move lowering PS inputs/outputs at the right place
At shaders creation, just after NIR linking.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Dave Airlie
---
src/amd/vulkan/radv_pipeline.c | 3 +++
src/amd/vulkan/radv_shader.c | 7 ++-
src/amd/vulkan/radv_shader.h | 3 +++
3 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 52f8cd048c3..0897b2d153e 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2578,6 +2578,9 @@ void radv_create_shaders(struct radv_pipeline *pipeline,
nir_print_shader(nir[i], stderr);
}
+ if (nir[MESA_SHADER_FRAGMENT])
+ radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
+
radv_fill_shader_keys(device, keys, key, nir);
if (nir[MESA_SHADER_FRAGMENT]) {
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index a3e9b45a752..82858bc906a 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -520,8 +520,8 @@ lower_view_index(nir_shader *nir)
return progress;
}
-static void
-lower_fs_io(nir_shader *nir)
+void
+radv_lower_fs_io(nir_shader *nir)
{
NIR_PASS_V(nir, lower_view_index);
nir_assign_io_var_locations(&nir->inputs, &nir->num_inputs,
@@ -1072,9 +1072,6 @@ shader_variant_compile(struct radv_device *device,
struct radv_shader_variant_info variant_info = {0};
bool thread_compiler;
- if (shaders[0]->info.stage == MESA_SHADER_FRAGMENT)
- lower_fs_io(shaders[0]);
-
options->family = chip_family;
options->chip_class = device->physical_device->rad_info.chip_class;
options->dump_shader = radv_can_dump_shader(device, module,
gs_copy_shader);
diff --git a/src/amd/vulkan/radv_shader.h b/src/amd/vulkan/radv_shader.h
index b8770b8c999..67c45a0f0bd 100644
--- a/src/amd/vulkan/radv_shader.h
+++ b/src/amd/vulkan/radv_shader.h
@@ -449,4 +449,7 @@ radv_can_dump_shader_stats(struct radv_device *device,
unsigned
shader_io_get_unique_index(gl_varying_slot slot);
+void
+radv_lower_fs_io(nir_shader *nir);
+
#endif
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Mesa (master): radv: gather info about PS inputs in the shader info pass
Module: Mesa
Branch: master
Commit: 151d6990ec7164c7e3678bb6032032d49b117c85
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=151d6990ec7164c7e3678bb6032032d49b117c85
Author: Samuel Pitoiset
Date: Thu Aug 29 11:12:25 2019 +0200
radv: gather info about PS inputs in the shader info pass
It's the right place to do that.
Signed-off-by: Samuel Pitoiset
Reviewed-by: Dave Airlie
---
src/amd/vulkan/radv_pipeline.c| 10 +++---
src/amd/vulkan/radv_shader.c | 68 ++-
src/amd/vulkan/radv_shader.h | 8 ++---
src/amd/vulkan/radv_shader_info.c | 41 +++
4 files changed, 53 insertions(+), 74 deletions(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 3e448db1fd5..52f8cd048c3 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -4023,11 +4023,11 @@ radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs,
}
}
- for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.fs.input_mask;
++i) {
+ for (unsigned i = 0; i < 32 && (1u << i) <=
ps->info.info.ps.input_mask; ++i) {
unsigned vs_offset;
bool flat_shade;
bool float16;
- if (!(ps->info.fs.input_mask & (1u << i)))
+ if (!(ps->info.info.ps.input_mask & (1u << i)))
continue;
vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 +
i];
@@ -4037,8 +4037,8 @@ radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs,
continue;
}
- flat_shade = !!(ps->info.fs.flat_shaded_mask & (1u <<
ps_offset));
- float16 = !!(ps->info.fs.float16_shaded_mask & (1u <<
ps_offset));
+ flat_shade = !!(ps->info.info.ps.flat_shaded_mask & (1u <<
ps_offset));
+ float16 = !!(ps->info.info.ps.float16_shaded_mask & (1u <<
ps_offset));
ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset,
flat_shade, float16);
++ps_offset;
@@ -4113,7 +4113,7 @@ radv_pipeline_generate_fragment_shader(struct
radeon_cmdbuf *ctx_cs,
ps->config.spi_ps_input_addr);
radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
- S_0286D8_NUM_INTERP(ps->info.fs.num_interp) |
+ S_0286D8_NUM_INTERP(ps->info.info.ps.num_interp)
|
S_0286D8_PS_W32_EN(ps->info.info.wave_size ==
32));
radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL,
pipeline->graphics.spi_baryc_cntl);
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 5166ecc15ab..a3e9b45a752 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -453,53 +453,6 @@ radv_shader_compile_to_nir(struct radv_device *device,
return nir;
}
-static void mark_16bit_fs_input(struct radv_shader_variant_info *shader_info,
-const struct glsl_type *type,
-int location)
-{
- if (glsl_type_is_scalar(type) || glsl_type_is_vector(type) ||
glsl_type_is_matrix(type)) {
- unsigned attrib_count = glsl_count_attribute_slots(type, false);
- if (glsl_type_is_16bit(type)) {
- shader_info->fs.float16_shaded_mask |= ((1ull <<
attrib_count) - 1) << location;
- }
- } else if (glsl_type_is_array(type)) {
- unsigned stride =
glsl_count_attribute_slots(glsl_get_array_element(type), false);
- for (unsigned i = 0; i < glsl_get_length(type); ++i) {
- mark_16bit_fs_input(shader_info,
glsl_get_array_element(type), location + i * stride);
- }
- } else {
- assert(glsl_type_is_struct_or_ifc(type));
- for (unsigned i = 0; i < glsl_get_length(type); i++) {
- mark_16bit_fs_input(shader_info,
glsl_get_struct_field(type, i), location);
- location +=
glsl_count_attribute_slots(glsl_get_struct_field(type, i), false);
- }
- }
-}
-
-static void
-handle_fs_input_decl(struct radv_shader_variant_info *shader_info,
-struct nir_variable *variable)
-{
- unsigned attrib_count = glsl_count_attribute_slots(variable->type,
false);
-
- if (variable->data.compact) {
- unsigned component_count = variable->data.location_frac +
- glsl_get_length(variable->type);
- attrib_count = (component_count + 3) / 4;
- } else {
- mark_16bit_fs_input(shader_info, variable->type,
- variable->data.driver_location);
- }
-
- uint64_t mask = ((1ull << attrib_count) - 1);
-
- if (variable->data.interpolation == INTERP_MODE_FL
