Mesa (master): ac/llvm: fix invalid use of unreachable in ac_build_atomic_rmw()

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 8227b08c08182fe7b75e2ec3b8b7531cfebaef59
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8227b08c08182fe7b75e2ec3b8b7531cfebaef59

Author: Samuel Pitoiset 
Date:   Wed Sep 30 13:33:58 2020 +0200

ac/llvm: fix invalid use of unreachable in ac_build_atomic_rmw()

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Bas Nieuwenhuizen 
Part-of: 

---

 src/amd/llvm/ac_llvm_helper.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/llvm/ac_llvm_helper.cpp b/src/amd/llvm/ac_llvm_helper.cpp
index f9b70e3f38c..5f04813704f 100644
--- a/src/amd/llvm/ac_llvm_helper.cpp
+++ b/src/amd/llvm/ac_llvm_helper.cpp
@@ -310,7 +310,7 @@ LLVMValueRef ac_build_atomic_rmw(struct ac_llvm_context 
*ctx, LLVMAtomicRMWBinOp
   binop = llvm::AtomicRMWInst::UMin;
   break;
default:
-  unreachable(!"invalid LLVMAtomicRMWBinOp");
+  unreachable("invalid LLVMAtomicRMWBinOp");
   break;
}
unsigned SSID = 
llvm::unwrap(ctx->context)->getOrInsertSyncScopeID(sync_scope);

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Mesa (master): ac/nir: fix nir_intrinsic_shared_atomic_fadd

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: b00a023f1e16a280730650952134ce9b72382987
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b00a023f1e16a280730650952134ce9b72382987

Author: Samuel Pitoiset 
Date:   Wed Sep 30 13:52:19 2020 +0200

ac/nir: fix nir_intrinsic_shared_atomic_fadd

This was completely broken.

Fixes dEQP-VK.glsl.atomic_operations.add_float32_compute_shared.

Signed-off-by: Samuel Pitoiset 
Reviewed-by: Bas Nieuwenhuizen 
Part-of: 

---

 src/amd/llvm/ac_llvm_helper.cpp | 5 +
 src/amd/llvm/ac_nir_to_llvm.c   | 9 +
 2 files changed, 14 insertions(+)

diff --git a/src/amd/llvm/ac_llvm_helper.cpp b/src/amd/llvm/ac_llvm_helper.cpp
index 5f04813704f..ebeafaea553 100644
--- a/src/amd/llvm/ac_llvm_helper.cpp
+++ b/src/amd/llvm/ac_llvm_helper.cpp
@@ -309,6 +309,11 @@ LLVMValueRef ac_build_atomic_rmw(struct ac_llvm_context 
*ctx, LLVMAtomicRMWBinOp
case LLVMAtomicRMWBinOpUMin:
   binop = llvm::AtomicRMWInst::UMin;
   break;
+#if LLVM_VERSION_MAJOR >= 10
+   case LLVMAtomicRMWBinOpFAdd:
+  binop = llvm::AtomicRMWInst::FAdd;
+  break;
+#endif
default:
   unreachable("invalid LLVMAtomicRMWBinOp");
   break;
diff --git a/src/amd/llvm/ac_nir_to_llvm.c b/src/amd/llvm/ac_nir_to_llvm.c
index 1beea68e876..a3543c4ae06 100644
--- a/src/amd/llvm/ac_nir_to_llvm.c
+++ b/src/amd/llvm/ac_nir_to_llvm.c
@@ -3364,11 +3364,20 @@ static LLVMValueRef visit_var_atomic(struct 
ac_nir_context *ctx, const nir_intri
   if (instr->intrinsic == nir_intrinsic_shared_atomic_fadd ||
   instr->intrinsic == nir_intrinsic_deref_atomic_fadd) {
  val = ac_to_float(&ctx->ac, src);
+
+ LLVMTypeRef ptr_type =
+LLVMPointerType(LLVMTypeOf(val), 
LLVMGetPointerAddressSpace(LLVMTypeOf(ptr)));
+ ptr = LLVMBuildBitCast(ctx->ac.builder, ptr, ptr_type, "");
   } else {
  val = ac_to_integer(&ctx->ac, src);
   }
 
   result = ac_build_atomic_rmw(&ctx->ac, op, ptr, val, sync_scope);
+
+  if (instr->intrinsic == nir_intrinsic_shared_atomic_fadd ||
+  instr->intrinsic == nir_intrinsic_deref_atomic_fadd) {
+ result = ac_to_integer(&ctx->ac, result);
+  }
}
 
if (ctx->ac.postponed_kill)

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Mesa (master): radv: fix gathering writes_memory for global store/atomic operations

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 892e74d2f7c6e443f57c03508ddb5647142588dd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=892e74d2f7c6e443f57c03508ddb5647142588dd

Author: Samuel Pitoiset 
Date:   Wed Sep 30 13:19:32 2020 +0200

radv: fix gathering writes_memory for global store/atomic operations

Because global operations are lowered before the shader info pass now
we have to adjust the gathering code.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3578
Fixes: 1588644543d ("radv: lower deref operations for global memory for both 
backends")
Signed-off-by: Samuel Pitoiset 
Reviewed-by: Bas Nieuwenhuizen 
Part-of: 

---

 src/amd/vulkan/radv_shader_info.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/src/amd/vulkan/radv_shader_info.c 
b/src/amd/vulkan/radv_shader_info.c
index 63a1f19e771..ed2da050dda 100644
--- a/src/amd/vulkan/radv_shader_info.c
+++ b/src/amd/vulkan/radv_shader_info.c
@@ -332,6 +332,17 @@ gather_intrinsic_info(const nir_shader *nir, const 
nir_intrinsic_instr *instr,
case nir_intrinsic_ssbo_atomic_xor:
case nir_intrinsic_ssbo_atomic_exchange:
case nir_intrinsic_ssbo_atomic_comp_swap:
+   case nir_intrinsic_store_global:
+   case nir_intrinsic_global_atomic_add:
+   case nir_intrinsic_global_atomic_imin:
+   case nir_intrinsic_global_atomic_umin:
+   case nir_intrinsic_global_atomic_imax:
+   case nir_intrinsic_global_atomic_umax:
+   case nir_intrinsic_global_atomic_and:
+   case nir_intrinsic_global_atomic_or:
+   case nir_intrinsic_global_atomic_xor:
+   case nir_intrinsic_global_atomic_exchange:
+   case nir_intrinsic_global_atomic_comp_swap:
set_writes_memory(nir, info);
break;
case nir_intrinsic_load_deref:

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Mesa (master): lavapipe: rename vallium to lavapipe

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: e94fd4cc65899bccceb4642363bc4376c6831580
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e94fd4cc65899bccceb4642363bc4376c6831580

Author: Dave Airlie 
Date:   Wed Sep 30 05:29:04 2020 +1000

lavapipe: rename vallium to lavapipe

Just a cooler name, and a lot easier to search for. thanks Marek

Acked-by: Marek Olšák 
Part-of: 

---

 .../val_cmd_buffer.c => lavapipe/lvp_cmd_buffer.c} | 584 +--
 .../{vallium/val_conv.h => lavapipe/lvp_conv.h}|   0
 .../lvp_descriptor_set.c}  | 164 +++---
 .../val_device.c => lavapipe/lvp_device.c} | 450 +++
 .../lvp_entrypoints_gen.py}| 102 ++--
 .../val_execute.c => lavapipe/lvp_execute.c}   | 374 ++--
 .../lvp_extensions.py} |  12 +-
 .../val_formats.c => lavapipe/lvp_formats.c}   |  36 +-
 .../{vallium/val_image.c => lavapipe/lvp_image.c}  |  76 +--
 .../lvp_lower_input_attachments.c} |   4 +-
 .../lvp_lower_vulkan_resource.c}   |  20 +-
 .../lvp_lower_vulkan_resource.h}   |  14 +-
 .../{vallium/val_pass.c => lavapipe/lvp_pass.c}|  66 +--
 .../val_pipeline.c => lavapipe/lvp_pipeline.c} | 106 ++--
 .../lvp_pipeline_cache.c}  |  24 +-
 .../val_private.h => lavapipe/lvp_private.h}   | 640 ++---
 .../{vallium/val_query.c => lavapipe/lvp_query.c}  |  24 +-
 .../{vallium/val_util.c => lavapipe/lvp_util.c}|   8 +-
 .../{vallium/val_wsi.c => lavapipe/lvp_wsi.c}  |  80 +--
 .../{vallium/val_wsi.h => lavapipe/lvp_wsi.h}  |  44 +-
 .../lvp_wsi_wayland.c} |  10 +-
 .../val_wsi_x11.c => lavapipe/lvp_wsi_x11.c}   |  18 +-
 src/gallium/frontends/lavapipe/meson.build |  66 +++
 src/gallium/frontends/vallium/meson.build  |  66 ---
 src/gallium/meson.build|   4 +-
 .../{vallium/val_icd.py => lavapipe/lvp_icd.py}|   4 +-
 .../targets/{vallium => lavapipe}/meson.build  |  16 +-
 src/gallium/targets/{vallium => lavapipe}/target.c |   0
 28 files changed, 1506 insertions(+), 1506 deletions(-)

Diff:   
http://cgit.freedesktop.org/mesa/mesa/diff/?id=e94fd4cc65899bccceb4642363bc4376c6831580
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Mesa (master): radeonsi: Fix dead lock with aux_context_lock in si_screen_clear_buffer.

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 5e8791a0bf00384cbd7e3a7231bddbc48bd550a8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e8791a0bf00384cbd7e3a7231bddbc48bd550a8

Author: Olsak, Marek 
Date:   Wed Sep 30 12:19:05 2020 -0400

radeonsi: Fix dead lock with aux_context_lock in si_screen_clear_buffer.

After disable SDMA on Arcturus(gfx9), dead lock with aux_context_lock is
detected since si_screen_clear_buffer is called recursively before
release lock.

The call trace is:
si_clear_render_target->si_compute_clear_render_target->
si_launch_grid_internal->si_launch_grid->si_emit_cache_flush->
si_prim_discard_signal_next_compute_ib_start->u_suballocator_alloc->
si_resource_create->si_buffer_create->si_alloc_resource->
si_screen_clear_buffer->simple_mtx_lock->
si_sdma_clear_buffer->si_pipe_clear_buffer->
si_clear_buffer->si_compute_do_clear_or_copy->
si_launch_grid_internal->si_launch_grid->si_emit_cache_flush->
si_prim_discard_signal_next_compute_ib_start->u_suballocator_alloc->
si_resource_create->si_buffer_create->si_alloc_resource->
si_screen_clear_buffer->simple_mtx_lock

Fixes: 07a49bf5976 "radeonsi: disable SDMA on gfx9"
Signed-off-by: James Zhu 
Reviewed-by: Marek Olšák 
Part-of: 

---

 src/gallium/drivers/radeonsi/si_pipe.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index a8e67c32855..ab476013873 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -601,6 +601,8 @@ static struct pipe_context *si_create_context(struct 
pipe_screen *screen, unsign
   si_initialize_prim_discard_tunables(sscreen, is_aux_context,
   
&sctx->prim_discard_vertex_count_threshold,
   &sctx->index_ring_size_per_ib);
+   } else {
+  sctx->prim_discard_vertex_count_threshold = UINT_MAX;
}
 
/* Initialize SDMA functions. */

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Mesa (staging/20.1): nir/cf: Better handle intra-block splits

[GitLab Mirror]

Module: Mesa
Branch: staging/20.1
Commit: 0eef738b1fc604bc5d7b679c7afb55e1fff6e58d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0eef738b1fc604bc5d7b679c7afb55e1fff6e58d

Author: Jason Ekstrand 
Date:   Thu Sep 24 23:50:24 2020 -0500

nir/cf: Better handle intra-block splits

In the case where end was a instruction-based cursor, we would mix up
our blocks and end up with block_begin pointing after the second split.
This causes a segfault as the cf_node list walk at the end of the
function never terminates properly.  There's also a possibility of
mix-up if begin is an instruction-based cursor which was found by
inspection.

Fixes: fc7f2d2364a9 "nir/cf: add new control modification API's"
Reviewed-by: Connor Abbott 
Acked-by: Matt Turner 
Part-of: 
(cherry picked from commit 7dbb1f7462433940951ce6c3fa22f6368aeafd50)

---

 .pick_status.json   |  2 +-
 src/compiler/nir/nir_control_flow.c | 31 ---
 2 files changed, 25 insertions(+), 8 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index dbce07a661c..952114c5011 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -238,7 +238,7 @@
 "description": "nir/cf: Better handle intra-block splits",
 "nominated": true,
 "nomination_type": 1,
-"resolution": 0,
+"resolution": 1,
 "master_sha": null,
 "because_sha": "fc7f2d2364a98d4ec8fb8627b03c6f84b353998c"
 },
diff --git a/src/compiler/nir/nir_control_flow.c 
b/src/compiler/nir/nir_control_flow.c
index 252aaf335ad..e89851859be 100644
--- a/src/compiler/nir/nir_control_flow.c
+++ b/src/compiler/nir/nir_control_flow.c
@@ -666,16 +666,33 @@ nir_cf_extract(nir_cf_list *extracted, nir_cursor begin, 
nir_cursor end)
   return;
}
 
-   /* In the case where begin points to an instruction in some basic block and
-* end points to the end of the same basic block, we rely on the fact that
-* splitting on an instruction moves earlier instructions into a new basic
-* block. If the later instructions were moved instead, then the end cursor
-* would be pointing to the same place that begin used to point to, which
-* is obviously not what we want.
-*/
split_block_cursor(begin, &block_before, &block_begin);
+
+   /* Splitting a block twice with two cursors created before either split is
+* tricky and there are a couple of places it can go wrong if both cursors
+* point to the same block.  One is if the second cursor is an block-based
+* cursor and, thanks to the split above, it ends up pointing to the wrong
+* block.  If it's a before_block cursor and it's in the same block as
+* begin, then begin must also be a before_block cursor and it should be
+* caught by the nir_cursors_equal check above and we won't get here.  If
+* it's an after_block cursor, we need to re-adjust to ensure that it
+* points to the second one of the split blocks, regardless of which it is.
+*/
+   if (end.option == nir_cursor_after_block && end.block == block_before)
+  end.block = block_begin;
+
split_block_cursor(end, &block_end, &block_after);
 
+   /* The second place this can all go wrong is that it could be that the
+* second split places the original block after the new block in which case
+* the block_begin pointer that we saved off above is pointing to the block
+* at the end rather than the block in the middle like it's supposed to be.
+* In this case, we have to re-adjust begin_block to point to the middle
+* one.
+*/
+   if (block_begin == block_after)
+  block_begin = block_end;
+
extracted->impl = nir_cf_node_get_function(&block_begin->cf_node);
exec_list_make_empty(&extracted->list);
 

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Mesa (staging/20.1): .pick_status.json: Update to 90e42f87ac56f1a3466151afd998cd8a4cd2f071

[GitLab Mirror]

Module: Mesa
Branch: staging/20.1
Commit: d0973b18bda13fba17cb3a93b0734414d7a1a75a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d0973b18bda13fba17cb3a93b0734414d7a1a75a

Author: Eric Engestrom 
Date:   Wed Sep 30 22:29:54 2020 +0200

.pick_status.json: Update to 90e42f87ac56f1a3466151afd998cd8a4cd2f071

---

 .pick_status.json | 936 ++
 1 file changed, 936 insertions(+)

diff --git a/.pick_status.json b/.pick_status.json
index 1fce3727bb4..dbce07a661c 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1,4 +1,940 @@
 [
+{
+"sha": "90e42f87ac56f1a3466151afd998cd8a4cd2f071",
+"description": "add one last 20.1 release to coincide with expected 
20.2.1",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "fe16e40974851488c3f94bfede3db6fe57593202",
+"description": "docs: update calendar and link releases notes for 
20.1.9",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "00d87db89b52b9fb85eaf7c6a88451e2bea7339b",
+"description": "docs: add release notes for 20.1.9",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "49ec863e8303170fd2a871689f9d9366215dca7e",
+"description": "freedreno/ir3: Enable the i/o vectorizer on UBOs.",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "e3f465580511153daca9ec9085375bd518ed5b24",
+"description": "nir: Make nir_lower_ubo_vec4() handle non-vec4-aligned 
loads.",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "618556a8cbdf86c31eb359c043cc9c629dc6fc0b",
+"description": "nir: Drop the high_offset argument to the 
load_store_vectorizer filter.",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "5f757bb95c20cdebed578b851e9f204b8aa6c014",
+"description": "nir: Make the load_store_vectorizer provide align_mul 
+ align_offset.",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "9c5a793dc72bf6977643b0fc8bf8b1579639d7d7",
+"description": "nir/gl_nir_lower_buffers: Set up align_mul/offset on 
UBOs.",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "ffbfc1ec0eb9190e8e7fa099631917e2987db325",
+"description": "nir/nir_lower_uniforms_to_ubo: Set better alignments 
on our new instructions.",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "c88c89ff3ea05cc168d1514fab1b71de2a357bb2",
+"description": "nir: Print the alignment information on casts.",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "6c1c5714409c1e49f941289396cc5112da95dad9",
+"description": "nir: Document a bit about how align_mul/offset work.",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "bd60e31c837b9c8ed48f6b4db0b93b14ab46135e",
+"description": "freedreno/ir3: Make sure we run the opt loop after 
lowering UBOs to vec4.",
+"nominated": false,
+"nomination_type": 1,
+"resolution": 4,
+"master_sha": null,
+"because_sha": "2b2524099379b96a6dbeab037a25cbf5d71da7df"
+},
+{
+"sha": "8dc8922af257e454f4460bbc5993df5647968146",
+"description": "turnip: implement legacy API functions separately",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "25ebd7f90f83c4a78b68386b248983f624c3678e",
+"description": "Revert \"nir/lower_goto_if: Add a route::outside 
set\"",
+"nominated": false,
+"nomination_type": 2,
+"resolution": 4,
+"master_sha": null,
+"because_sha": "d57573dcd4aa2160f3153df466b01f377484a3fa"
+},
+{
+

Mesa (master): add one last 20.1 release to coincide with expected 20.2.1

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 90e42f87ac56f1a3466151afd998cd8a4cd2f071
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=90e42f87ac56f1a3466151afd998cd8a4cd2f071

Author: Eric Engestrom 
Date:   Wed Sep 30 21:57:19 2020 +0200

add one last 20.1 release to coincide with expected 20.2.1

Part-of: 

---

 docs/release-calendar.rst | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/docs/release-calendar.rst b/docs/release-calendar.rst
index 74e40273bd0..48f60d20361 100644
--- a/docs/release-calendar.rst
+++ b/docs/release-calendar.rst
@@ -30,5 +30,7 @@ Calendar
 
++---++-+-+
 | Branch | Expected date | Release| Release manager | Notes
   |
 
++===++=+=+
+| 20.1   | 2020-10-14| 20.1.10| Eric Engestrom  | Last planned release 
of the 20.1 series |
+++---++-+-+
 | 20.2   | 2020-09-16| 20.2.0-rc5 | Dylan Baker | or 20.2.0 final  
   |
 
++---++-+-+

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Mesa (master): docs: update calendar and link releases notes for 20.1.9

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: fe16e40974851488c3f94bfede3db6fe57593202
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fe16e40974851488c3f94bfede3db6fe57593202

Author: Eric Engestrom 
Date:   Wed Sep 30 21:20:29 2020 +0200

docs: update calendar and link releases notes for 20.1.9

Part-of: 

---

 docs/release-calendar.rst | 2 --
 docs/relnotes.rst | 2 ++
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/release-calendar.rst b/docs/release-calendar.rst
index f6cfb650b5c..74e40273bd0 100644
--- a/docs/release-calendar.rst
+++ b/docs/release-calendar.rst
@@ -30,7 +30,5 @@ Calendar
 
++---++-+-+
 | Branch | Expected date | Release| Release manager | Notes
   |
 
++===++=+=+
-| 20.1   | 2020-09-30| 20.1.9 | Eric Engestrom  | Last planned release 
of the 20.1 series |
-++---++-+-+
 | 20.2   | 2020-09-16| 20.2.0-rc5 | Dylan Baker | or 20.2.0 final  
   |
 
++---++-+-+
diff --git a/docs/relnotes.rst b/docs/relnotes.rst
index 5e2ddd12766..422f6d9996c 100644
--- a/docs/relnotes.rst
+++ b/docs/relnotes.rst
@@ -3,6 +3,7 @@ Release Notes
 
 The release notes summarize what's new or changed in each Mesa release.
 
+-  :doc:`20.1.9 release notes `
 -  :doc:`20.1.8 release notes `
 -  :doc:`20.1.7 release notes `
 -  :doc:`20.1.6 release notes `
@@ -314,6 +315,7 @@ file ` and the following release notes.
:maxdepth: 1
:hidden:
 
+   relnotes/20.1.9
relnotes/20.1.8
relnotes/20.1.7
relnotes/20.1.6

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Mesa (master): docs: add release notes for 20.1.9

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 00d87db89b52b9fb85eaf7c6a88451e2bea7339b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=00d87db89b52b9fb85eaf7c6a88451e2bea7339b

Author: Eric Engestrom 
Date:   Wed Sep 30 20:08:22 2020 +0200

docs: add release notes for 20.1.9

Part-of: 

---

 docs/relnotes/20.1.9.rst | 132 +++
 1 file changed, 132 insertions(+)

diff --git a/docs/relnotes/20.1.9.rst b/docs/relnotes/20.1.9.rst
new file mode 100644
index 000..53c096e4f51
--- /dev/null
+++ b/docs/relnotes/20.1.9.rst
@@ -0,0 +1,132 @@
+Mesa 20.1.9 Release Notes / 2020-09-30
+==
+
+Mesa 20.1.9 is a bug fix release which fixes bugs found since the 20.1.8 
release.
+
+Mesa 20.1.9 implements the OpenGL 4.6 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.6. OpenGL
+4.6 is **only** available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+
+Mesa 20.1.9 implements the Vulkan 1.2 API, but the version reported by
+the apiVersion property of the VkPhysicalDeviceProperties struct
+depends on the particular driver being used.
+
+SHA256 checksum
+---
+
+::
+
+b251ca0769b722058986640d48f8457c596142cfbee1a83cba91b83391427382  
mesa-20.1.9.tar.xz
+
+
+New features
+
+
+- None
+
+
+Bug fixes
+-
+
+- Horizon Zero Dawn graphics corruption with with radv
+- Running Amber test leads to VK_DEVICE_LOST
+- \[spirv-fuzz\] Shader generates a wrong image
+- anv: dEQP-VK.robustness.robustness2.\* failures on gen12
+- \[RADV\] Problems reading primitive ID in fragment shader after tessellation
+- Substance Painter 6.1.3 black glitches on Radeon RX570
+- vkCmdCopyImage broadcasts subsample 0 of MSAA src into all subsamples of dst 
on RADV
+
+
+Changes
+---
+
+Bas Nieuwenhuizen (3):
+
+- amd/common: Cache intra-tile addresses for retile map.
+- ac/surface: Fix depth import on GFX6-GFX8.
+- st/mesa: Deal with empty textures/buffers in semaphore wait/signal.
+
+Christian Gmeiner (1):
+
+- etnaviv: simplify linear stride implementation
+
+Connor Abbott (1):
+
+- nir/lower_io_arrays: Fix xfb_offset bug
+
+Danylo Piliaiev (4):
+
+- nir/lower_io: Eliminate oob writes and return zero for oob reads
+- nir/large_constants: Eliminate out-of-bounds writes to large constants
+- nir/lower_samplers: Clamp out-of-bounds access to array of samplers
+- intel/fs: Disable sample mask predication for scratch stores
+
+Dylan Baker (1):
+
+- meson/anv: Use variable that checks for --build-id
+
+Eric Engestrom (9):
+
+- docs/relnotes: add sha256 sums to 20.1.8
+- .pick_status.json: Update to d74fe47101995d2659b1e59495d2f77b9dc14f3d
+- .pick_status.json: Update to c669db0b503c10faf2d1c67c9340d7222b4f946e
+- .pick_status.json: Update to a3543adc2628461818cfa691a7f547af7bc6f0fb
+- .pick_status.json: Mark 802d3611dcec8102ef75fe2461340c2997af931e as 
denominated
+- .pick_status.json: Mark e98c7a66347a05fc166c377ab1abb77955aff775 as 
denominated
+- .pick_status.json: Mark 6b1a56b908e702c06f55c63b19b695a47f607456 as 
denominated
+- .pick_status.json: Mark 89401e58672e1251b954662f0f776a6e9bce6df8 as 
denominated
+- .pick_status.json: Update to efaea653b5766427701817ab06c319902a148ee9
+
+Erik Faye-Lund (2):
+
+- mesa: handle GL_FRONT after translating to it
+- st/mesa: use roundf instead of floorf for lod-bias rounding
+
+Jason Ekstrand (2):
+
+- intel/fs/swsb: SCHEDULING_FENCE only emits SYNC_NOP
+- nir/liveness: Consider if uses in nir_ssa_defs_interfere
+
+Jesse Natalie (1):
+
+- glsl_type: Add packed to structure type comparison for hash map
+
+Karol Herbst (1):
+
+- spirv: extract switch parsing into its own function
+
+Lionel Landwerlin (1):
+
+- intel/compiler: fixup Gen12 workaround for array sizes
+
+Marek Olšák (1):
+
+- radeonsi: fix indirect dispatches with variable block sizes
+
+Nanley Chery (1):
+
+- blorp: Ensure aligned HIZ_CCS_WT partial clears
+
+Pierre-Eric Pelloux-Prayer (3):
+
+- mesa: fix glUniform\* when a struct contains a bindless sampler
+- gallium/vl: do not call transfer_unmap if transfer is NULL
+- gallium/vl: add chroma_format arg to vl_video_buffer functions
+
+Pierre-Loup A. Griffais (2):
+
+- radv: fix null descriptor for dynamic buffers
+- radv: fix vertex buffer null descriptors
+
+Rhys Perry (2):
+
+- radv: initialize with expanded cmask if the destination layout needs it
+- radv,aco: fix reading primitive ID in FS after TES
+
+Samuel Pitoiset (2):
+
+- radv: fix transform feedback crashes if pCounterBufferOffsets is NULL
+- spirv: fix emitting switch cases that directly jump to the merge block

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Mesa (master): nir: Drop the high_offset argument to the load_store_vectorizer filter.

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 618556a8cbdf86c31eb359c043cc9c629dc6fc0b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=618556a8cbdf86c31eb359c043cc9c629dc6fc0b

Author: Eric Anholt 
Date:   Tue Sep  8 11:12:56 2020 -0700

nir: Drop the high_offset argument to the load_store_vectorizer filter.

Nothing uses it, and it's not clear to me what it provides over
alignment/num_components/bit_size.

Reviewed-by: Rob Clark 
Part-of: 

---

 src/amd/compiler/aco_instruction_selection_setup.cpp   | 2 +-
 src/compiler/nir/nir.h | 2 +-
 src/compiler/nir/nir_opt_load_store_vectorize.c| 2 +-
 src/compiler/nir/tests/load_store_vectorizer_tests.cpp | 4 ++--
 src/intel/compiler/brw_nir.c   | 2 +-
 5 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp 
b/src/amd/compiler/aco_instruction_selection_setup.cpp
index e4b837c561c..367524c5e38 100644
--- a/src/amd/compiler/aco_instruction_selection_setup.cpp
+++ b/src/amd/compiler/aco_instruction_selection_setup.cpp
@@ -385,7 +385,7 @@ type_size(const struct glsl_type *type, bool bindless)
 bool
 mem_vectorize_callback(unsigned align_mul, unsigned align_offset,
unsigned bit_size,
-   unsigned num_components, unsigned high_offset,
+   unsigned num_components,
nir_intrinsic_instr *low, nir_intrinsic_instr *high)
 {
if (num_components > 4)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 80d89b7f3f2..5ac625904b9 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -4854,7 +4854,7 @@ bool nir_opt_conditional_discard(nir_shader *shader);
 typedef bool (*nir_should_vectorize_mem_func)(unsigned align_mul,
   unsigned align_offset,
   unsigned bit_size,
-  unsigned num_components, 
unsigned high_offset,
+  unsigned num_components,
   nir_intrinsic_instr *low, 
nir_intrinsic_instr *high);
 
 bool nir_opt_load_store_vectorize(nir_shader *shader, nir_variable_mode modes,
diff --git a/src/compiler/nir/nir_opt_load_store_vectorize.c 
b/src/compiler/nir/nir_opt_load_store_vectorize.c
index 6ae69031820..51405fa1bc3 100644
--- a/src/compiler/nir/nir_opt_load_store_vectorize.c
+++ b/src/compiler/nir/nir_opt_load_store_vectorize.c
@@ -670,7 +670,7 @@ new_bitsize_acceptable(struct vectorize_ctx *ctx, unsigned 
new_bit_size,
if (!ctx->callback(low->align_mul,
   low->align_offset,
   new_bit_size, new_num_components,
-  high_offset, low->intrin, high->intrin))
+  low->intrin, high->intrin))
   return false;
 
if (low->is_store) {
diff --git a/src/compiler/nir/tests/load_store_vectorizer_tests.cpp 
b/src/compiler/nir/tests/load_store_vectorizer_tests.cpp
index dd9d4015836..0f49d30e01a 100644
--- a/src/compiler/nir/tests/load_store_vectorizer_tests.cpp
+++ b/src/compiler/nir/tests/load_store_vectorizer_tests.cpp
@@ -72,7 +72,7 @@ protected:
 
static bool mem_vectorize_callback(unsigned align_mul, unsigned 
align_offset,
   unsigned bit_size,
-  unsigned num_components, unsigned 
high_offset,
+  unsigned num_components,
   nir_intrinsic_instr *low, 
nir_intrinsic_instr *high);
static void shared_type_info(const struct glsl_type *type, unsigned *size, 
unsigned *align);
 
@@ -365,7 +365,7 @@ bool nir_load_store_vectorize_test::test_alu_def(
 
 bool nir_load_store_vectorize_test::mem_vectorize_callback(
unsigned align_mul, unsigned align_offset, unsigned bit_size,
-   unsigned num_components, unsigned high_offset,
+   unsigned num_components,
nir_intrinsic_instr *low, nir_intrinsic_instr *high)
 {
return bit_size / 8;
diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c
index c1af534295f..0de36e67984 100644
--- a/src/intel/compiler/brw_nir.c
+++ b/src/intel/compiler/brw_nir.c
@@ -857,7 +857,7 @@ brw_nir_link_shaders(const struct brw_compiler *compiler,
 static bool
 brw_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset,
  unsigned bit_size,
- unsigned num_components, unsigned high_offset,
+ unsigned num_components,
  nir_intrinsic_instr *low,
  nir_intrinsic_instr *high)
 {

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Mesa (master): nir: Print the alignment information on casts.

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: c88c89ff3ea05cc168d1514fab1b71de2a357bb2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c88c89ff3ea05cc168d1514fab1b71de2a357bb2

Author: Eric Anholt 
Date:   Tue Sep  8 12:50:34 2020 -0700

nir: Print the alignment information on casts.

I wanted it for debugging GL alignment.

Reviewed-by: Rob Clark 
Part-of: 

---

 src/compiler/nir/nir_print.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c
index c84c70ac9b7..8d86bf87bca 100644
--- a/src/compiler/nir/nir_print.c
+++ b/src/compiler/nir/nir_print.c
@@ -736,7 +736,9 @@ print_deref_instr(nir_deref_instr *instr, print_state 
*state)
}
 
if (instr->deref_type == nir_deref_type_cast) {
-  fprintf(fp, " /* ptr_stride=%u */", instr->cast.ptr_stride);
+  fprintf(fp, " /* ptr_stride=%u, align_mul=%u, align_offset=%u */",
+  instr->cast.ptr_stride,
+  instr->cast.align_mul, instr->cast.align_offset);
}
 }
 

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Mesa (master): freedreno/ir3: Enable the i/o vectorizer on UBOs.

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 49ec863e8303170fd2a871689f9d9366215dca7e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=49ec863e8303170fd2a871689f9d9366215dca7e

Author: Eric Anholt 
Date:   Thu Aug 20 13:29:58 2020 -0700

freedreno/ir3: Enable the i/o vectorizer on UBOs.

This will merge loads of UBO components together into vec4 loads.  At the
same time, it improves the alignment information on our loads, fixing the
regression from the vec3 loads fix.

shader-db results:
total instructions in shared programs: 12829370 -> 8755851 (-31.75%)
total cat6 in shared programs: 145840 -> 97027 (-33.47%)

Overall results from before the vec3 fix:
total instructions in shared programs: 8019997 -> 8755851 (9.18%)
total cat6 in shared programs: 87683 -> 97027 (10.66%)

Part-of: 

---

 src/freedreno/ir3/ir3_nir.c | 33 +
 1 file changed, 33 insertions(+)

diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c
index 64daa685705..2628746a302 100644
--- a/src/freedreno/ir3/ir3_nir.c
+++ b/src/freedreno/ir3/ir3_nir.c
@@ -145,6 +145,36 @@ ir3_get_compiler_options(struct ir3_compiler *compiler)
return &options;
 }
 
+static bool
+ir3_nir_should_vectorize_mem(unsigned align_mul, unsigned align_offset,
+   unsigned bit_size,
+   unsigned num_components,
+   nir_intrinsic_instr *low,
+   nir_intrinsic_instr *high)
+{
+   assert(bit_size >= 8);
+   if (bit_size != 32)
+   return false;
+   unsigned byte_size = bit_size / 8;
+
+   int size = num_components * byte_size;
+
+   /* Don't care about alignment past vec4. */
+   assert(util_is_power_of_two_nonzero(align_mul));
+   align_mul = MIN2(align_mul, 16);
+   align_offset &= 15;
+
+   /* Our offset alignment should aways be at least 4 bytes */
+   if (align_mul < 4)
+   return false;
+
+   unsigned worst_start_offset = 16 - align_mul + align_offset;
+   if (worst_start_offset + size > 16)
+   return false;
+
+   return true;
+}
+
 #define OPT(nir, pass, ...) ({ \
bool this_progress = false; \
NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__);  \
@@ -188,6 +218,9 @@ ir3_optimize_loop(nir_shader *s)
progress |= OPT(s, nir_lower_pack);
progress |= OPT(s, nir_opt_constant_folding);
 
+   progress |= OPT(s, nir_opt_load_store_vectorize, 
nir_var_mem_ubo,
+   ir3_nir_should_vectorize_mem, 0);
+
if (lower_flrp != 0) {
if (OPT(s, nir_lower_flrp,
lower_flrp,

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Mesa (master): nir: Document a bit about how align_mul/offset work.

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 6c1c5714409c1e49f941289396cc5112da95dad9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6c1c5714409c1e49f941289396cc5112da95dad9

Author: Eric Anholt 
Date:   Tue Sep  8 13:07:56 2020 -0700

nir: Document a bit about how align_mul/offset work.

Introduces a #define for the maximum valid align_mul that's used in the
load_store_vectorizer tests (currently, though it will be used more soon).

Reviewed-by: Rob Clark 
Part-of: 

---

 src/compiler/nir/nir.h | 15 +--
 src/compiler/nir/tests/load_store_vectorizer_tests.cpp |  2 +-
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 1ac0ba45cee..80400dc7996 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1718,10 +1718,14 @@ typedef enum {
 * Alignment for offsets and addresses
 *
 * These two parameters, specify an alignment in terms of a multiplier and
-* an offset.  The offset or address parameter X of the intrinsic is
-* guaranteed to satisfy the following:
+* an offset.  The multiplier is always a power of two.  The offset or
+* address parameter X of the intrinsic is guaranteed to satisfy the
+* following:
 *
 *(X - align_offset) % align_mul == 0
+*
+* For constant offset values, align_mul will be NIR_ALIGN_MUL_MAX and the
+* align_offset will be modulo that.
 */
NIR_INTRINSIC_ALIGN_MUL,
NIR_INTRINSIC_ALIGN_OFFSET,
@@ -1778,6 +1782,13 @@ typedef enum {
 
 } nir_intrinsic_index_flag;
 
+/**
+ * Maximum valid value for a nir align_mul value (in intrinsics or derefs).
+ *
+ * Offsets can be signed, so this is the largest power of two in int32_t.
+ */
+#define NIR_ALIGN_MUL_MAX 0x4000
+
 typedef struct {
unsigned location:7; /* gl_vert_attrib, gl_varying_slot, or gl_frag_result 
*/
unsigned num_slots:6;  /* max 32, may be pessimistic with const indexing */
diff --git a/src/compiler/nir/tests/load_store_vectorizer_tests.cpp 
b/src/compiler/nir/tests/load_store_vectorizer_tests.cpp
index 75880c3805f..708cbefbabd 100644
--- a/src/compiler/nir/tests/load_store_vectorizer_tests.cpp
+++ b/src/compiler/nir/tests/load_store_vectorizer_tests.cpp
@@ -1875,6 +1875,6 @@ TEST_F(nir_load_store_vectorize_test, 
ubo_alignment_const_100)
   create_indirect_load(nir_var_mem_ubo, 0, nir_imm_int(b, 100), 0x1);
 
EXPECT_TRUE(run_vectorizer(nir_var_mem_ubo));
-   EXPECT_EQ(nir_intrinsic_align_mul(load), 0x4000);
+   EXPECT_EQ(nir_intrinsic_align_mul(load), NIR_ALIGN_MUL_MAX);
EXPECT_EQ(nir_intrinsic_align_offset(load), 100);
 }

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Mesa (master): freedreno/ir3: Make sure we run the opt loop after lowering UBOs to vec4.

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: bd60e31c837b9c8ed48f6b4db0b93b14ab46135e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd60e31c837b9c8ed48f6b4db0b93b14ab46135e

Author: Eric Anholt 
Date:   Mon Sep 14 13:13:47 2020 -0700

freedreno/ir3: Make sure we run the opt loop after lowering UBOs to vec4.

The lowering pass may introduce vector bcsels that we need to scalarize
back out.  It's unusual to have UBOs and not get any lowered to push
constants, so the flag was usually set anyway.

Fixes: 2b2524099379 ("freedreno/ir3: Replace our custom vec4 UBO intrinsic
with the shared lowering.")

Part-of: 

---

 src/freedreno/ir3/ir3_nir.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c
index 9b406166007..64daa685705 100644
--- a/src/freedreno/ir3/ir3_nir.c
+++ b/src/freedreno/ir3/ir3_nir.c
@@ -471,7 +471,7 @@ ir3_nir_lower_variant(struct ir3_shader_variant *so, 
nir_shader *s)
 * be left as load_ubo
 */
if (so->shader->compiler->gpu_id >= 600)
-   OPT_V(s, nir_lower_ubo_vec4);
+   progress |= OPT(s, nir_lower_ubo_vec4);
 
OPT_V(s, ir3_nir_lower_io_offsets, so->shader->compiler->gpu_id);
 

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Mesa (master): nir/nir_lower_uniforms_to_ubo: Set better alignments on our new instructions.

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: ffbfc1ec0eb9190e8e7fa099631917e2987db325
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ffbfc1ec0eb9190e8e7fa099631917e2987db325

Author: Eric Anholt 
Date:   Wed Sep  9 10:21:49 2020 -0700

nir/nir_lower_uniforms_to_ubo: Set better alignments on our new instructions.

The change on freedreno is in the noise.

Reviewed-by: Rob Clark 
Part-of: 

---

 src/compiler/nir/nir_lower_uniforms_to_ubo.c | 19 ++-
 1 file changed, 18 insertions(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir_lower_uniforms_to_ubo.c 
b/src/compiler/nir/nir_lower_uniforms_to_ubo.c
index 4d1a5a7fbb5..47e92fa9508 100644
--- a/src/compiler/nir/nir_lower_uniforms_to_ubo.c
+++ b/src/compiler/nir/nir_lower_uniforms_to_ubo.c
@@ -69,7 +69,24 @@ lower_instr(nir_intrinsic_instr *instr, nir_builder *b, int 
multiplier)
   load->src[0] = nir_src_for_ssa(ubo_idx);
   load->src[1] = nir_src_for_ssa(ubo_offset);
   assert(instr->dest.ssa.bit_size >= 8);
-  nir_intrinsic_set_align(load, instr->dest.ssa.bit_size / 8, 0);
+
+  /* If it's const, set the alignment to our known constant offset.  If
+   * not, set it to a pessimistic value based on the multiplier (or the
+   * scalar size, for qword loads).
+   *
+   * We could potentially set up stricter alignments for indirects by
+   * knowing what features are enabled in the APIs (see comment in
+   * nir_lower_ubo_vec4.c)
+   */
+  if (nir_src_is_const(instr->src[0])) {
+ nir_intrinsic_set_align(load, NIR_ALIGN_MUL_MAX,
+ (nir_src_as_uint(instr->src[0]) +
+  nir_intrinsic_base(instr) * multiplier) %
+ NIR_ALIGN_MUL_MAX);
+  } else {
+ nir_intrinsic_set_align(load, MAX2(multiplier,
+instr->dest.ssa.bit_size / 8), 0);
+  }
   nir_ssa_dest_init(&load->instr, &load->dest,
 load->num_components, instr->dest.ssa.bit_size,
 instr->dest.ssa.name);

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Mesa (master): nir/gl_nir_lower_buffers: Set up align_mul/offset on UBOs.

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 9c5a793dc72bf6977643b0fc8bf8b1579639d7d7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9c5a793dc72bf6977643b0fc8bf8b1579639d7d7

Author: Eric Anholt 
Date:   Tue Sep  8 12:44:30 2020 -0700

nir/gl_nir_lower_buffers: Set up align_mul/offset on UBOs.

nir_lower_to_explicit_io will give us good alignments if we have the
cast's alignment information known, and it's trivial: Just the offset of
the UBO variable that is at the base of the deref.  Otherwise, explicit io
assumes the load is aligned just to the size of a scalar value in it.

The change in freedreno is in the noise.

Reviewed-by: Rob Clark 
Part-of: 

---

 src/compiler/glsl/gl_nir_lower_buffers.c | 13 +++--
 1 file changed, 11 insertions(+), 2 deletions(-)

diff --git a/src/compiler/glsl/gl_nir_lower_buffers.c 
b/src/compiler/glsl/gl_nir_lower_buffers.c
index b83df08a867..d78473ddbf9 100644
--- a/src/compiler/glsl/gl_nir_lower_buffers.c
+++ b/src/compiler/glsl/gl_nir_lower_buffers.c
@@ -182,6 +182,7 @@ lower_buffer_interface_derefs_impl(nir_function_impl *impl,
 
 b.cursor = nir_before_instr(&deref->instr);
 
+unsigned offset = 0;
 nir_ssa_def *ptr;
 if (deref->deref_type == nir_deref_type_var &&
 !glsl_type_is_interface(glsl_without_array(deref->var->type))) 
{
@@ -189,7 +190,7 @@ lower_buffer_interface_derefs_impl(nir_function_impl *impl,
 * containing one.  We need the block index and its offset
 * inside that block
 */
-   unsigned index, offset;
+   unsigned index;
get_block_index_offset(deref->var, shader_program,
   b.shader->info.stage,
   &index, &offset);
@@ -201,7 +202,7 @@ lower_buffer_interface_derefs_impl(nir_function_impl *impl,
 */
nir_ssa_def *index = get_block_array_index(&b, deref,
   shader_program);
-   ptr = nir_vec2(&b, index, nir_imm_int(&b, 0));
+   ptr = nir_vec2(&b, index, nir_imm_int(&b, offset));
 } else {
/* This will get handled by nir_lower_explicit_io(). */
break;
@@ -209,6 +210,14 @@ lower_buffer_interface_derefs_impl(nir_function_impl *impl,
 
 nir_deref_instr *cast = nir_build_deref_cast(&b, ptr, deref->mode,
  deref->type, 0);
+/* Set the alignment on the cast so that we get good alignment out
+ * of nir_lower_explicit_io.  Our offset to the start of the UBO
+ * variable is always a constant, so we can use the maximum
+ * align_mul.
+ */
+cast->cast.align_mul = NIR_ALIGN_MUL_MAX;
+cast->cast.align_offset = offset % NIR_ALIGN_MUL_MAX;
+
 nir_ssa_def_rewrite_uses(&deref->dest.ssa,
  nir_src_for_ssa(&cast->dest.ssa));
 nir_deref_instr_remove_if_unused(deref);

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Mesa (master): nir: Make nir_lower_ubo_vec4() handle non-vec4-aligned loads.

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: e3f465580511153daca9ec9085375bd518ed5b24
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e3f465580511153daca9ec9085375bd518ed5b24

Author: Eric Anholt 
Date:   Tue Sep  8 11:55:58 2020 -0700

nir: Make nir_lower_ubo_vec4() handle non-vec4-aligned loads.

It turns out I had missed a case in my enumeration of why everything
currently was vec4-aligned.

Fixes a simple testcase of loading from a vec3[2] array in freedreno with
IR3_SHADER_DEBUG=nouboopt.

Initial shader-db results look devastating:

total instructions in shared programs: 8019997 -> 12829370 (59.97%)
total cat6 in shared programs: 87683 -> 145840 (66.33%)

Hopefully this will recover once we introduce the i/o vectorizer, but that
was blocked on getting the vec3 case fixed.

Reviewed-by: Rob Clark 
Part-of: 

---

 src/compiler/nir/nir_lower_ubo_vec4.c | 127 +-
 1 file changed, 80 insertions(+), 47 deletions(-)

diff --git a/src/compiler/nir/nir_lower_ubo_vec4.c 
b/src/compiler/nir/nir_lower_ubo_vec4.c
index 2f739ffd63a..85e780df132 100644
--- a/src/compiler/nir/nir_lower_ubo_vec4.c
+++ b/src/compiler/nir/nir_lower_ubo_vec4.c
@@ -26,8 +26,10 @@
  * hardware to have, and it gives NIR a chance to optimize the addressing math
  * and CSE the loads.
  *
- * We assume that the UBO loads do not cross a vec4 boundary.  This is true
- * for:
+ * This pass handles lowering for loads that straddle a vec4 alignment
+ * boundary.  We try to minimize the extra loads we generate for that case,
+ * and are ensured non-straddling loads with:
+ *
  * - std140 (GLSL 1.40, GLSL ES)
  * - Vulkan "Extended Layout" (the baseline for UBOs)
  *
@@ -36,6 +38,10 @@
  * - GLSL 4.30's new packed mode (enabled by PIPE_CAP_LOAD_CONSTBUF) where
  *   vec3 arrays are packed tightly.
  *
+ * - PackedDriverUniformStorage in GL (enabled by PIPE_CAP_PACKED_UNIFORMS)
+ *   combined with nir_lower_uniforms_to_ubo, where values in the default
+ *   uniform block are packed tightly.
+ *
  * - Vulkan's scalarBlockLayout optional feature:
  *
  *   "A member is defined to improperly straddle if either of the following are
@@ -66,6 +72,22 @@ nir_lower_ubo_vec4_filter(const nir_instr *instr, const void 
*data)
return nir_instr_as_intrinsic(instr)->intrinsic == nir_intrinsic_load_ubo;
 }
 
+static nir_intrinsic_instr *
+nir_load_ubo_vec4(nir_builder *b, nir_ssa_def *block, nir_ssa_def *offset,
+  unsigned bit_size, unsigned num_components)
+{
+   nir_intrinsic_instr *load =
+  nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_ubo_vec4);
+   load->src[0] = nir_src_for_ssa(block);
+   load->src[1] = nir_src_for_ssa(offset);
+
+   nir_ssa_dest_init(&load->instr, &load->dest, num_components, bit_size, 
NULL);
+   load->num_components = num_components;
+   nir_builder_instr_insert(b, &load->instr);
+
+   return load;
+}
+
 static nir_ssa_def *
 nir_lower_ubo_vec4_lower(nir_builder *b, nir_instr *instr, void *data)
 {
@@ -74,11 +96,7 @@ nir_lower_ubo_vec4_lower(nir_builder *b, nir_instr *instr, 
void *data)
nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
 
nir_ssa_def *byte_offset = nir_ssa_for_src(b, intr->src[1], 1);
-
-   nir_intrinsic_instr *load =
-  nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_ubo_vec4);
-   nir_src_copy(&load->src[0], &intr->src[0], &load->instr);
-   load->src[1] = nir_src_for_ssa(nir_ushr_imm(b, byte_offset, 4));
+   nir_ssa_def *vec4_offset = nir_ushr_imm(b, byte_offset, 4);
 
unsigned align_mul = nir_intrinsic_align_mul(intr);
unsigned align_offset = nir_intrinsic_align_offset(intr);
@@ -93,24 +111,16 @@ nir_lower_ubo_vec4_lower(nir_builder *b, nir_instr *instr, 
void *data)
align_offset &= 15;
assert(align_offset % chan_size_bytes == 0);
 
-   /* We assume that loads don't cross vec4 boundaries, just that we need
-* to extract from within the vec4 when we don't have a good alignment.
-*/
-   if (intr->num_components == chans_per_vec4) {
-  align_mul = 16;
-  align_offset = 0;
-   }
-
unsigned num_components = intr->num_components;
-   bool aligned_mul = align_mul % 16 == 0;
+   bool aligned_mul = (align_mul == 16 &&
+   align_offset +  chan_size_bytes * num_components <= 16);
if (!aligned_mul)
   num_components = chans_per_vec4;
 
-   nir_ssa_dest_init(&load->instr, &load->dest,
- num_components, intr->dest.ssa.bit_size,
- intr->dest.ssa.name);
-   load->num_components = num_components;
-   nir_builder_instr_insert(b, &load->instr);
+   nir_intrinsic_instr *load = nir_load_ubo_vec4(b, intr->src[0].ssa,
+ vec4_offset,
+ intr->dest.ssa.bit_size,
+ num_components);
 
nir_ssa_def *result = &load->dest.ssa;
 
@@ -120,39 +

Mesa (master): nir: Make the load_store_vectorizer provide align_mul + align_offset.

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 5f757bb95c20cdebed578b851e9f204b8aa6c014
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f757bb95c20cdebed578b851e9f204b8aa6c014

Author: Eric Anholt 
Date:   Tue Sep  8 10:58:49 2020 -0700

nir: Make the load_store_vectorizer provide align_mul + align_offset.

It was passing an encoding of the two that wasn't good for ensuring "Don't
combine loads that would make us straddle a vec4 boundary" for
nir_lower_ubo_vec4.

Reviewed-by: Rob Clark 
Part-of: 

---

 src/amd/compiler/aco_instruction_selection_setup.cpp   |  9 -
 src/compiler/nir/nir.h |  4 +++-
 src/compiler/nir/nir_opt_load_store_vectorize.c|  5 +++--
 src/compiler/nir/tests/load_store_vectorizer_tests.cpp |  6 --
 src/intel/compiler/brw_nir.c   | 10 +-
 5 files changed, 27 insertions(+), 7 deletions(-)

diff --git a/src/amd/compiler/aco_instruction_selection_setup.cpp 
b/src/amd/compiler/aco_instruction_selection_setup.cpp
index 4bae3d2d396..e4b837c561c 100644
--- a/src/amd/compiler/aco_instruction_selection_setup.cpp
+++ b/src/amd/compiler/aco_instruction_selection_setup.cpp
@@ -383,7 +383,8 @@ type_size(const struct glsl_type *type, bool bindless)
 }
 
 bool
-mem_vectorize_callback(unsigned align, unsigned bit_size,
+mem_vectorize_callback(unsigned align_mul, unsigned align_offset,
+   unsigned bit_size,
unsigned num_components, unsigned high_offset,
nir_intrinsic_instr *low, nir_intrinsic_instr *high)
 {
@@ -394,6 +395,12 @@ mem_vectorize_callback(unsigned align, unsigned bit_size,
if (bit_size * num_components > 128)
   return false;
 
+   uint32_t align;
+   if (align_offset)
+  align = 1 << (ffs(align_offset) - 1);
+   else
+  align = align_mul;
+
switch (low->intrinsic) {
case nir_intrinsic_load_global:
case nir_intrinsic_store_global:
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 80400dc7996..80d89b7f3f2 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -4851,7 +4851,9 @@ bool nir_opt_vectorize(nir_shader *shader, 
nir_opt_vectorize_cb filter,
 
 bool nir_opt_conditional_discard(nir_shader *shader);
 
-typedef bool (*nir_should_vectorize_mem_func)(unsigned align, unsigned 
bit_size,
+typedef bool (*nir_should_vectorize_mem_func)(unsigned align_mul,
+  unsigned align_offset,
+  unsigned bit_size,
   unsigned num_components, 
unsigned high_offset,
   nir_intrinsic_instr *low, 
nir_intrinsic_instr *high);
 
diff --git a/src/compiler/nir/nir_opt_load_store_vectorize.c 
b/src/compiler/nir/nir_opt_load_store_vectorize.c
index 35a650736f9..6ae69031820 100644
--- a/src/compiler/nir/nir_opt_load_store_vectorize.c
+++ b/src/compiler/nir/nir_opt_load_store_vectorize.c
@@ -667,8 +667,9 @@ new_bitsize_acceptable(struct vectorize_ctx *ctx, unsigned 
new_bit_size,
if (new_bit_size / common_bit_size > NIR_MAX_VEC_COMPONENTS)
   return false;
 
-   uint32_t align = low->align_offset ? 1 << (ffs(low->align_offset) - 1) : 
low->align_mul;
-   if (!ctx->callback(align, new_bit_size, new_num_components,
+   if (!ctx->callback(low->align_mul,
+  low->align_offset,
+  new_bit_size, new_num_components,
   high_offset, low->intrin, high->intrin))
   return false;
 
diff --git a/src/compiler/nir/tests/load_store_vectorizer_tests.cpp 
b/src/compiler/nir/tests/load_store_vectorizer_tests.cpp
index 708cbefbabd..dd9d4015836 100644
--- a/src/compiler/nir/tests/load_store_vectorizer_tests.cpp
+++ b/src/compiler/nir/tests/load_store_vectorizer_tests.cpp
@@ -70,7 +70,8 @@ protected:
bool test_alu(nir_instr *instr, nir_op op);
bool test_alu_def(nir_instr *instr, unsigned index, nir_ssa_def *def, 
unsigned swizzle=0);
 
-   static bool mem_vectorize_callback(unsigned align, unsigned bit_size,
+   static bool mem_vectorize_callback(unsigned align_mul, unsigned 
align_offset,
+  unsigned bit_size,
   unsigned num_components, unsigned 
high_offset,
   nir_intrinsic_instr *low, 
nir_intrinsic_instr *high);
static void shared_type_info(const struct glsl_type *type, unsigned *size, 
unsigned *align);
@@ -363,7 +364,8 @@ bool nir_load_store_vectorize_test::test_alu_def(
 }
 
 bool nir_load_store_vectorize_test::mem_vectorize_callback(
-   unsigned align, unsigned bit_size, unsigned num_components, unsigned 
high_offset,
+   unsigned align_mul, unsigned align_offset, unsigned bit_size,
+   unsigned num_components, unsigned high_offset,
nir_intrinsic_instr *low, nir_intrinsic_instr *high)
 {
   

Mesa (20.1): 39 new commits

[GitLab Mirror]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1329a289045dec333d713bb53cf6ea726adbe813
Author: Eric Engestrom 
Date:   Wed Sep 30 21:24:06 2020 +0200

docs/relnotes: add sha256 sums to 20.1.9

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a443eb1adf1240341241331e55f9959669f57a0
Author: Eric Engestrom 
Date:   Wed Sep 30 20:37:42 2020 +0200

VERSION: bump to release 20.1.9

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bc6fd91e68a0c05716b66161fd5936a55c5f569b
Author: Eric Engestrom 
Date:   Wed Sep 30 20:33:53 2020 +0200

docs: add release notes for 20.1.9

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e1f6000b540c3d48cb573653db6e1bf4e0003050
Author: Connor Abbott 
Date:   Fri Aug 21 15:51:47 2020 +0200

nir/lower_io_arrays: Fix xfb_offset bug

I noticed this once I started gathering xfb_info after
nir_lower_io_arrays_to_elements_no_indirect.

Fixes: b2bbd978d0b ("nir: fix lowering arrays to elements for XFB outputs")
Reviewed-by: Caio Marcelo de Oliveira Filho 
Part-of: 
(cherry picked from commit 5a88db682e08b5e58b40653872569f5b5d7d)

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=30b256c21e08d6193da534b4b700cdfeb47a506f
Author: Erik Faye-Lund 
Date:   Mon Sep 28 16:11:38 2020 +0200

st/mesa: use roundf instead of floorf for lod-bias rounding

There's no good reason not to use a symmetric rounding mode here. This
fixes the following GL CTS case for me:

GTF-GL33.gtf21.GL3Tests.texture_lod_bias.texture_lod_bias_all

Fixes: 132b69c4edb ("st/mesa: round lod_bias to a multiple of 1/256")
Reviewed-by: Marek Olšák 
Part-of: 
(cherry picked from commit 7685c37bf47104497d70c4580abb9e050ea8100f)

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=71b3582ec157e7855d20cebf20014e1afe54ece6
Author: Pierre-Eric Pelloux-Prayer 
Date:   Tue Sep 22 14:32:13 2020 +0200

gallium/vl: add chroma_format arg to vl_video_buffer functions

vl_mpeg12_decoder needs to override the chroma_format value to get the
correct size calculated (chroma_format is used by 
vl_video_buffer_adjust_size).

I'm not sure why it's needed, but this is needed to get correct mpeg decode.

Fixes: 24f2b0a8560 ("gallium/video: remove pipe_video_buffer.chroma_format")
Acked-by: Leo Liu 
Part-of: 
(cherry picked from commit 2584d48b2cf13ea50b4e6177f32bacf0c7027e79)

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fc21ef6b66efc322f77e1fefc0120ac2213ebe95
Author: Pierre-Eric Pelloux-Prayer 
Date:   Tue Sep 22 14:31:32 2020 +0200

gallium/vl: do not call transfer_unmap if transfer is NULL

CC: mesa-stable
Acked-by: Leo Liu 
Part-of: 
(cherry picked from commit b121b1b8b8f6df790dd8150a8b5e8021dc9e56bb)

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d74c2e743d00a0bb58cc5ef33a6320d45e546c12
Author: Eric Engestrom 
Date:   Tue Sep 29 22:11:28 2020 +0200

.pick_status.json: Update to efaea653b5766427701817ab06c319902a148ee9

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0dbec6b96410c9e46b7b7d89fcf049044bddd21f
Author: Eric Engestrom 
Date:   Mon Sep 28 23:03:31 2020 +0200

.pick_status.json: Mark 89401e58672e1251b954662f0f776a6e9bce6df8 as 
denominated

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=db4a29d078fcfacb434d9c12027da9ec684d64d4
Author: Samuel Pitoiset 
Date:   Thu Sep 3 22:02:01 2020 +0200

spirv: fix emitting switch cases that directly jump to the merge block

As shown in the valid SPIR-V below, if one switch case statement
directly jumps to the merge block, it has no branches at all and
we have to reset the fall variable. Otherwise, it creates an
unintentional fallthrough.

   OpSelectionMerge %97 None
   OpSwitch %96 %97 1 %99 2 %100
%100 = OpLabel
%102 = OpAccessChain %_ptr_StorageBuffer_v4float %86 %uint_0 %uint_37
%103 = OpLoad %v4float %102
%104 = OpBitcast %v4uint %103
%105 = OpCompositeExtract %uint %104 0
%106 = OpShiftLeftLogical %uint %105 %uint_1
   OpBranch %97
 %99 = OpLabel
   OpBranch %97
 %97 = OpLabel
%107 = OpPhi %uint %uint_4 %75 %uint_5 %99 %106 %100

This fixes serious corruption in Horizon Zero Dawn.

v2: Changed the code to skip the entire if-block instead of resetting
the fallthrough variable.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3460
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset 
Signed-off-by: Bas Nieuwenhuizen 
Reviewed-by: Daniel Schürmann 
Part-of: 
(cherry p

Mesa (staging/20.1): docs/relnotes: add sha256 sums to 20.1.9

[GitLab Mirror]

Module: Mesa
Branch: staging/20.1
Commit: 1329a289045dec333d713bb53cf6ea726adbe813
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1329a289045dec333d713bb53cf6ea726adbe813

Author: Eric Engestrom 
Date:   Wed Sep 30 21:24:06 2020 +0200

docs/relnotes: add sha256 sums to 20.1.9

---

 docs/relnotes/20.1.9.html | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/relnotes/20.1.9.html b/docs/relnotes/20.1.9.html
index 39d9a2067fd..498b018242c 100644
--- a/docs/relnotes/20.1.9.html
+++ b/docs/relnotes/20.1.9.html
@@ -36,7 +36,7 @@ depends on the particular driver being used.
 
 SHA256 checksum
 
-TBD.
+b251ca0769b722058986640d48f8457c596142cfbee1a83cba91b83391427382  
mesa-20.1.9.tar.xz
 
 
 

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Mesa: tag mesa-20.1.9: mesa-20.1.9

[GitLab Mirror]

Module: Mesa
Branch: refs/tags/mesa-20.1.9
Tag:f18aa423d7e99d9f947aa68c1c8a8d64dfcd2dd8
URL:
http://cgit.freedesktop.org/mesa/mesa/tag/?id=f18aa423d7e99d9f947aa68c1c8a8d64dfcd2dd8

Tagger: Eric Engestrom 
Date:   Wed Sep 30 20:52:19 2020 +0200

mesa-20.1.9
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Mesa (staging/20.1): VERSION: bump to release 20.1.9

[GitLab Mirror]

Module: Mesa
Branch: staging/20.1
Commit: 0a443eb1adf1240341241331e55f9959669f57a0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a443eb1adf1240341241331e55f9959669f57a0

Author: Eric Engestrom 
Date:   Wed Sep 30 20:37:42 2020 +0200

VERSION: bump to release 20.1.9

---

 VERSION | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/VERSION b/VERSION
index 54d13e7d1b8..07ea1529b50 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-20.1.8
+20.1.9

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Mesa (staging/20.1): docs: add release notes for 20.1.9

[GitLab Mirror]

Module: Mesa
Branch: staging/20.1
Commit: bc6fd91e68a0c05716b66161fd5936a55c5f569b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bc6fd91e68a0c05716b66161fd5936a55c5f569b

Author: Eric Engestrom 
Date:   Wed Sep 30 20:33:53 2020 +0200

docs: add release notes for 20.1.9

---

 docs/relnotes/20.1.9.html | 140 ++
 1 file changed, 140 insertions(+)

diff --git a/docs/relnotes/20.1.9.html b/docs/relnotes/20.1.9.html
new file mode 100644
index 000..39d9a2067fd
--- /dev/null
+++ b/docs/relnotes/20.1.9.html
@@ -0,0 +1,140 @@
+
+http://www.w3.org/TR/html4/loose.dtd";>
+
+
+
+Mesa Release Notes
+
+
+
+
+
+The Mesa 3D Graphics Library
+
+
+
+
+
+Mesa 20.1.9 Release Notes / 2020-09-30
+
+
+Mesa 20.1.9 is a bug fix release which fixes bugs found since the 20.1.8 
release.
+
+
+Mesa 20.1.9 implements the OpenGL 4.6 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.6. OpenGL
+4.6 is only available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+
+
+Mesa 20.1.9 implements the Vulkan 1.2 API, but the version reported by
+the apiVersion property of the VkPhysicalDeviceProperties struct
+depends on the particular driver being used.
+
+
+SHA256 checksum
+
+TBD.
+
+
+
+New features
+
+
+None
+
+
+Bug fixes
+
+
+Horizon Zero Dawn graphics corruption with with radv
+Running Amber test leads to VK_DEVICE_LOST
+[spirv-fuzz] Shader generates a wrong image
+anv: dEQP-VK.robustness.robustness2.* failures on gen12
+[RADV] Problems reading primitive ID in fragment shader after 
tessellation
+Substance Painter 6.1.3 black glitches on Radeon RX570
+vkCmdCopyImage broadcasts subsample 0 of MSAA src into all subsamples 
of dst on RADV
+
+
+Changes
+
+
+Bas Nieuwenhuizen (3):
+  amd/common: Cache intra-tile addresses for retile map.
+  ac/surface: Fix depth import on GFX6-GFX8.
+  st/mesa: Deal with empty textures/buffers in semaphore 
wait/signal.
+
+Christian Gmeiner (1):
+  etnaviv: simplify linear stride implementation
+
+Connor Abbott (1):
+  nir/lower_io_arrays: Fix xfb_offset bug
+
+Danylo Piliaiev (4):
+  nir/lower_io: Eliminate oob writes and return zero for oob 
reads
+  nir/large_constants: Eliminate out-of-bounds writes to large 
constants
+  nir/lower_samplers: Clamp out-of-bounds access to array of 
samplers
+  intel/fs: Disable sample mask predication for scratch stores
+
+Dylan Baker (1):
+  meson/anv: Use variable that checks for --build-id
+
+Eric Engestrom (9):
+  docs/relnotes: add sha256 sums to 20.1.8
+  .pick_status.json: Update to 
d74fe47101995d2659b1e59495d2f77b9dc14f3d
+  .pick_status.json: Update to 
c669db0b503c10faf2d1c67c9340d7222b4f946e
+  .pick_status.json: Update to 
a3543adc2628461818cfa691a7f547af7bc6f0fb
+  .pick_status.json: Mark 802d3611dcec8102ef75fe2461340c2997af931e 
as denominated
+  .pick_status.json: Mark e98c7a66347a05fc166c377ab1abb77955aff775 
as denominated
+  .pick_status.json: Mark 6b1a56b908e702c06f55c63b19b695a47f607456 
as denominated
+  .pick_status.json: Mark 89401e58672e1251b954662f0f776a6e9bce6df8 
as denominated
+  .pick_status.json: Update to 
efaea653b5766427701817ab06c319902a148ee9
+
+Erik Faye-Lund (2):
+  mesa: handle GL_FRONT after translating to it
+  st/mesa: use roundf instead of floorf for lod-bias rounding
+
+Jason Ekstrand (2):
+  intel/fs/swsb: SCHEDULING_FENCE only emits SYNC_NOP
+  nir/liveness: Consider if uses in nir_ssa_defs_interfere
+
+Jesse Natalie (1):
+  glsl_type: Add packed to structure type comparison for hash 
map
+
+Karol Herbst (1):
+  spirv: extract switch parsing into its own function
+
+Lionel Landwerlin (1):
+  intel/compiler: fixup Gen12 workaround for array sizes
+
+Marek Olšák (1):
+  radeonsi: fix indirect dispatches with variable block sizes
+
+Nanley Chery (1):
+  blorp: Ensure aligned HIZ_CCS_WT partial clears
+
+Pierre-Eric Pelloux-Prayer (3):
+  mesa: fix glUniform* when a struct contains a bindless 
sampler
+  gallium/vl: do not call transfer_unmap if transfer is NULL
+  gallium/vl: add chroma_format arg to vl_video_buffer 
functions
+
+Pierre-Loup A. Griffais (2):
+  radv: fix null descriptor for dynamic buffers
+  radv: fix vertex buffer null descriptors
+
+Rhys Perry (2):
+  radv: initialize with expanded cmask if the destination layout 
needs it
+  radv,aco: fix reading primitive ID in FS after

Mesa (master): turnip: implement legacy API functions separately

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 8dc8922af257e454f4460bbc5993df5647968146
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8dc8922af257e454f4460bbc5993df5647968146

Author: Jonathan Marek 
Date:   Tue Sep 29 12:04:17 2020 -0400

turnip: implement legacy API functions separately

Move legacy API functions to a separate file, and implement them by calling
the new API functions, like tu_CreateRenderPass was already doing.

Signed-off-by: Jonathan Marek 
Part-of: 

---

 src/freedreno/vulkan/meson.build |   1 +
 src/freedreno/vulkan/tu_cmd_buffer.c |  37 +---
 src/freedreno/vulkan/tu_device.c | 167 +++-
 src/freedreno/vulkan/tu_formats.c|  52 -
 src/freedreno/vulkan/tu_legacy.c | 375 +++
 src/freedreno/vulkan/tu_pass.c   | 145 --
 6 files changed, 414 insertions(+), 363 deletions(-)

diff --git a/src/freedreno/vulkan/meson.build b/src/freedreno/vulkan/meson.build
index f50375c7a58..2dbcfd85c06 100644
--- a/src/freedreno/vulkan/meson.build
+++ b/src/freedreno/vulkan/meson.build
@@ -49,6 +49,7 @@ libtu_files = files(
   'tu_descriptor_set.h',
   'tu_formats.c',
   'tu_image.c',
+  'tu_legacy.c',
   'tu_nir_lower_multiview.c',
   'tu_pass.c',
   'tu_pipeline.c',
diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c 
b/src/freedreno/vulkan/tu_cmd_buffer.c
index 3d312315b1f..9142c8c20d5 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -2881,9 +2881,9 @@ tu_subpass_barrier(struct tu_cmd_buffer *cmd_buffer,
 }
 
 void
-tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
-  const VkRenderPassBeginInfo *pRenderPassBegin,
-  VkSubpassContents contents)
+tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer,
+   const VkRenderPassBeginInfo *pRenderPassBegin,
+   const VkSubpassBeginInfo *pSubpassBeginInfo)
 {
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
TU_FROM_HANDLE(tu_render_pass, pass, pRenderPassBegin->renderPass);
@@ -2918,16 +2918,9 @@ tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer,
 }
 
 void
-tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer,
-   const VkRenderPassBeginInfo *pRenderPassBeginInfo,
-   const VkSubpassBeginInfoKHR *pSubpassBeginInfo)
-{
-   tu_CmdBeginRenderPass(commandBuffer, pRenderPassBeginInfo,
- pSubpassBeginInfo->contents);
-}
-
-void
-tu_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents)
+tu_CmdNextSubpass2(VkCommandBuffer commandBuffer,
+   const VkSubpassBeginInfo *pSubpassBeginInfo,
+   const VkSubpassEndInfo *pSubpassEndInfo)
 {
TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
const struct tu_render_pass *pass = cmd->state.pass;
@@ -2980,14 +2973,6 @@ tu_CmdNextSubpass(VkCommandBuffer commandBuffer, 
VkSubpassContents contents)
tu_set_input_attachments(cmd, cmd->state.subpass);
 }
 
-void
-tu_CmdNextSubpass2(VkCommandBuffer commandBuffer,
-   const VkSubpassBeginInfoKHR *pSubpassBeginInfo,
-   const VkSubpassEndInfoKHR *pSubpassEndInfo)
-{
-   tu_CmdNextSubpass(commandBuffer, pSubpassBeginInfo->contents);
-}
-
 static void
 tu6_emit_user_consts(struct tu_cs *cs, const struct tu_pipeline *pipeline,
  struct tu_descriptor_state *descriptors_state,
@@ -3839,7 +3824,8 @@ tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
 }
 
 void
-tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
+tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer,
+ const VkSubpassEndInfoKHR *pSubpassEndInfo)
 {
TU_FROM_HANDLE(tu_cmd_buffer, cmd_buffer, commandBuffer);
 
@@ -3869,13 +3855,6 @@ tu_CmdEndRenderPass(VkCommandBuffer commandBuffer)
cmd_buffer->state.has_subpass_predication = false;
 }
 
-void
-tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer,
- const VkSubpassEndInfoKHR *pSubpassEndInfo)
-{
-   tu_CmdEndRenderPass(commandBuffer);
-}
-
 struct tu_barrier_info
 {
uint32_t eventCount;
diff --git a/src/freedreno/vulkan/tu_device.c b/src/freedreno/vulkan/tu_device.c
index 8b4f15766e4..c06fdec6a42 100644
--- a/src/freedreno/vulkan/tu_device.c
+++ b/src/freedreno/vulkan/tu_device.c
@@ -367,12 +367,10 @@ tu_EnumeratePhysicalDeviceGroups(
 }
 
 void
-tu_GetPhysicalDeviceFeatures(VkPhysicalDevice physicalDevice,
- VkPhysicalDeviceFeatures *pFeatures)
+tu_GetPhysicalDeviceFeatures2(VkPhysicalDevice physicalDevice,
+  VkPhysicalDeviceFeatures2 *pFeatures)
 {
-   memset(pFeatures, 0, sizeof(*pFeatures));
-
-   *pFeatures = (VkPhysicalDeviceFeatures) {
+   pFeatures->features = (VkPhysicalDeviceFeatures) {
   .robustBufferAccess = true,
   .fullDrawIndexUint32 = true,
   .imageCubeArray = true,
@@ -419,12 +417,7 @@ tu_GetPh

Mesa (staging/20.2): radv,radeonsi: Disable compression on interop depth images

[GitLab Mirror]

Module: Mesa
Branch: staging/20.2
Commit: b971b42b149b9cfa33622c2250a1c5bda728ce42
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b971b42b149b9cfa33622c2250a1c5bda728ce42

Author: Bas Nieuwenhuizen 
Date:   Fri Aug 14 00:58:06 2020 +0200

radv,radeonsi: Disable compression on interop depth images

If we want to use HTILE correctly we need to communicate extra stuff
like clear colors. (Unlike DCC there is no HTILE FCE)

CC: mesa-stable
Reviewed-by: Marek Olšák 
(cherry picked from commit d78df70c2a85fd846d40b71b9e213122347bea1b)

Part-of: 

---

 .pick_status.json | 2 +-
 src/amd/vulkan/radv_image.c   | 1 +
 src/gallium/drivers/radeonsi/si_texture.c | 3 ++-
 3 files changed, 4 insertions(+), 2 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 4d8b5ce3666..60ef7e5a3a8 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -4243,7 +4243,7 @@
 "description": "radv,radeonsi: Disable compression on interop depth 
images",
 "nominated": true,
 "nomination_type": 0,
-"resolution": 0,
+"resolution": 3,
 "master_sha": null,
 "because_sha": null
 },
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 2bd152b964c..e2204c4add0 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -261,6 +261,7 @@ static inline bool
 radv_use_htile_for_image(const struct radv_image *image)
 {
return image->info.levels == 1 &&
+  !image->shareable &&
   image->info.width * image->info.height >= 8 * 8;
 }
 
diff --git a/src/gallium/drivers/radeonsi/si_texture.c 
b/src/gallium/drivers/radeonsi/si_texture.c
index 01439114241..ad8196ba40d 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -237,7 +237,8 @@ static int si_init_surface(struct si_screen *sscreen, 
struct radeon_surf *surfac
if (!is_flushed_depth && is_depth) {
   flags |= RADEON_SURF_ZBUFFER;
 
-  if (sscreen->debug_flags & DBG(NO_HYPERZ)) {
+  if ((sscreen->debug_flags & DBG(NO_HYPERZ)) ||
+  (ptex->bind & PIPE_BIND_SHARED) || is_imported) {
  flags |= RADEON_SURF_NO_HTILE;
   } else if (tc_compatible_htile &&
  (sscreen->info.chip_class >= GFX9 || array_mode == 
RADEON_SURF_MODE_2D)) {

___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/mesa-commit

Mesa (master): Revert "nir/lower_goto_if: Add a route::outside set"

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 25ebd7f90f83c4a78b68386b248983f624c3678e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=25ebd7f90f83c4a78b68386b248983f624c3678e

Author: Jason Ekstrand 
Date:   Thu Sep 24 09:12:38 2020 -0500

Revert "nir/lower_goto_if: Add a route::outside set"

This reverts commit d57573dcd4aa2160f3153df466b01f377484a3fa.  The
actual bug was an issue with prev_frontiers which has been properly
fixed in the previous commit.

Reviewed-by: Karol Herbst 
Part-of: 

---

 src/compiler/nir/nir_lower_goto_ifs.c | 35 ++-
 1 file changed, 6 insertions(+), 29 deletions(-)

diff --git a/src/compiler/nir/nir_lower_goto_ifs.c 
b/src/compiler/nir/nir_lower_goto_ifs.c
index f5532e0e356..0e6902e9ded 100644
--- a/src/compiler/nir/nir_lower_goto_ifs.c
+++ b/src/compiler/nir/nir_lower_goto_ifs.c
@@ -50,7 +50,6 @@ struct path_fork {
 };
 
 struct routes {
-   struct set *outside;
struct path regular;
struct path brk;
struct path cont;
@@ -69,9 +68,6 @@ struct strct_lvl {
/** Reach set from inside_outside if irreducable */
struct set *reach;
 
-   /** Outside set from inside_outside if irreducable */
-   struct set *outside;
-
/** True if a skip region starts with this level */
bool skip_start;
 
@@ -295,18 +291,14 @@ fork_reachable(struct path_fork *fork)
 static void
 loop_routing_start(struct routes *routing, nir_builder *b,
struct path loop_path, struct set *reach,
-   struct set *outside, void *mem_ctx)
+   void *mem_ctx)
 {
if (NIR_LOWER_GOTO_IFS_DEBUG) {
   printf("loop_routing_start:\n");
   printf("reach =   ");
   print_block_set(reach);
-  printf("outside = ");
-  print_block_set(outside);
   printf("loop_path.reachable = ");
   print_block_set(loop_path.reachable);
-  printf("routing->outside =");
-  print_block_set(routing->outside);
   printf("routing->regular.reachable =  ");
   print_block_set(routing->regular.reachable);
   printf("routing->brk.reachable =  ");
@@ -334,12 +326,6 @@ loop_routing_start(struct routes *routing, nir_builder *b,
   continue_needed = true;
}
 
-   if (outside && outside->entries) {
-  routing->outside = _mesa_set_clone(routing->outside, routing);
-  set_foreach(outside, entry)
- _mesa_set_add_pre_hashed(routing->outside, entry->hash, entry->key);
-   }
-
routing->brk = routing_backup->regular;
routing->cont = loop_path;
routing->regular = loop_path;
@@ -632,7 +618,6 @@ handle_irreducible(struct set *remaining, struct strct_lvl 
*curr_level,
   inside_outside((nir_block *) entry->key, loop_heads, remaining,
  curr_level->reach, brk_reachable, mem_ctx);
}
-   curr_level->outside = remaining;
_mesa_set_destroy(loop_heads, NULL);
 }
 
@@ -672,21 +657,16 @@ handle_irreducible(struct set *remaining, struct 
strct_lvl *curr_level,
  *   zeroth level
  */
 static void
-organize_levels(struct list_head *levels, struct set *children,
+organize_levels(struct list_head *levels, struct set *remaining,
 struct set *reach, struct routes *routing,
 nir_function_impl *impl, bool is_domminated, void *mem_ctx)
 {
if (NIR_LOWER_GOTO_IFS_DEBUG) {
   printf("organize_levels:\n");
-  printf("children = ");
-  print_block_set(children);
   printf("reach = ");
   print_block_set(reach);
}
 
-   /* Duplicate remaining because we're going to destroy it */
-   struct set *remaining = _mesa_set_clone(children, mem_ctx);
-
/* blocks that can be reached by the remaining blocks */
struct set *remaining_frontier = _mesa_pointer_set_create(mem_ctx);
 
@@ -855,10 +835,8 @@ plant_levels(struct list_head *levels, struct routes 
*routing,
   }
   struct path in_path = routing->regular;
   routing->regular = level->out_path;
-  if (level->irreducible) {
- loop_routing_start(routing, b, in_path, level->reach,
-level->outside, mem_ctx);
-  }
+  if (level->irreducible)
+ loop_routing_start(routing, b, in_path, level->reach, mem_ctx);
   select_blocks(routing, b, in_path, mem_ctx);
   if (level->irreducible)
  loop_routing_end(routing, b);
@@ -877,7 +855,7 @@ nir_structurize(struct routes *routing, nir_builder *b, 
nir_block *block,
 {
struct set *remaining = _mesa_pointer_set_create(mem_ctx);
for (int i = 0; i < block->num_dom_children; i++) {
-  if (!_mesa_set_search(routing->outside, block->dom_children[i]))
+  if (!_mesa_set_search(routing->brk.reachable, block->dom_children[i]))
  _mesa_set_add(remaining, block->dom_children[i]);
}
 
@@ -905,7 +883,7 @@ nir_structurize(struct routes *routing, nir_builder

Mesa (master): nir/validate: Improve the validation of blocks

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 6f134a622b186df8a8b3b25d98cee70c78d1992a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f134a622b186df8a8b3b25d98cee70c78d1992a

Author: Jason Ekstrand 
Date:   Tue Sep 15 11:28:43 2020 -0500

nir/validate: Improve the validation of blocks

This commit adds a number of new validation checks:

 1. We now check that every block pointer in the IR points to a block
that actually exists in a block list that's reachable from the
nir_function_impl.

 2. We assert that nir_function_impl::body is non-empty

 3. We assert that the start block has no predecessors.  This is
important because we tend to put run-once code there.

 4. We now validate some stuff on the end block.

Reviewed-by: Karol Herbst 
Part-of: 

---

 src/compiler/nir/nir_validate.c | 100 
 1 file changed, 80 insertions(+), 20 deletions(-)

diff --git a/src/compiler/nir/nir_validate.c b/src/compiler/nir/nir_validate.c
index 0be74297858..57f7e365158 100644
--- a/src/compiler/nir/nir_validate.c
+++ b/src/compiler/nir/nir_validate.c
@@ -81,6 +81,9 @@ typedef struct {
/* the current function implementation being validated */
nir_function_impl *impl;
 
+   /* Set of all blocks in the list */
+   struct set *blocks;
+
/* Set of seen SSA sources */
struct set *ssa_srcs;
 
@@ -932,8 +935,63 @@ validate_phi_srcs(nir_block *block, nir_block *succ, 
validate_state *state)
}
 }
 
+static void
+collect_blocks(struct exec_list *cf_list, validate_state *state)
+{
+   exec_list_validate(cf_list);
+   foreach_list_typed(nir_cf_node, node, node, cf_list) {
+  switch (node->type) {
+  case nir_cf_node_block:
+ _mesa_set_add(state->blocks, nir_cf_node_as_block(node));
+ break;
+
+  case nir_cf_node_if:
+ collect_blocks(&nir_cf_node_as_if(node)->then_list, state);
+ collect_blocks(&nir_cf_node_as_if(node)->else_list, state);
+ break;
+
+  case nir_cf_node_loop:
+ collect_blocks(&nir_cf_node_as_loop(node)->body, state);
+ break;
+
+  default:
+ unreachable("Invalid CF node type");
+  }
+   }
+}
+
 static void validate_cf_node(nir_cf_node *node, validate_state *state);
 
+static void
+validate_block_predecessors(nir_block *block, validate_state *state)
+{
+   for (unsigned i = 0; i < 2; i++) {
+  if (block->successors[i] == NULL)
+ continue;
+
+  /* The block has to exist in the nir_function_impl */
+  validate_assert(state, _mesa_set_search(state->blocks,
+  block->successors[i]));
+
+  /* And we have to be in our successor's predecessors set */
+  validate_assert(state,
+ _mesa_set_search(block->successors[i]->predecessors, block));
+
+  validate_phi_srcs(block, block->successors[i], state);
+   }
+
+   /* The start block cannot have any predecessors */
+   if (block == nir_start_block(state->impl))
+  validate_assert(state, block->predecessors->entries == 0);
+
+   set_foreach(block->predecessors, entry) {
+  const nir_block *pred = entry->key;
+  validate_assert(state, _mesa_set_search(state->blocks, pred));
+  validate_assert(state, pred->successors[0] == block ||
+ pred->successors[1] == block);
+   }
+}
+
 static void
 validate_block(nir_block *block, validate_state *state)
 {
@@ -953,22 +1011,7 @@ validate_block(nir_block *block, validate_state *state)
 
validate_assert(state, block->successors[0] != NULL);
validate_assert(state, block->successors[0] != block->successors[1]);
-
-   for (unsigned i = 0; i < 2; i++) {
-  if (block->successors[i] != NULL) {
- struct set_entry *entry =
-_mesa_set_search(block->successors[i]->predecessors, block);
- validate_assert(state, entry);
-
- validate_phi_srcs(block, block->successors[i], state);
-  }
-   }
-
-   set_foreach(block->predecessors, entry) {
-  const nir_block *pred = entry->key;
-  validate_assert(state, pred->successors[0] == block ||
- pred->successors[1] == block);
-   }
+   validate_block_predecessors(block, state);
 
if (!state->impl->structured) {
   validate_assert(state, nir_block_ends_in_jump(block));
@@ -1021,6 +1064,20 @@ validate_block(nir_block *block, validate_state *state)
}
 }
 
+
+static void
+validate_end_block(nir_block *block, validate_state *state)
+{
+   validate_assert(state, block->cf_node.parent == &state->impl->cf_node);
+
+   exec_list_validate(&block->instr_list);
+   validate_assert(state, exec_list_is_empty(&block->instr_list));
+
+   validate_assert(state, block->successors[0] == NULL);
+   validate_assert(state, block->successors[1] == NULL);
+   validate_block_predecessors(block, state);
+}
+
 static void
 validate_if(nir_if *if_stmt, validate_state *state)
 {
@@ -1044,12 +1101,10 @@ validate_if(nir_if *if_

Mesa (master): nir/lower_goto_ifs: Use rzalloc

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: dc010cb74e1a60645cfd088f51c88a13cf5687ba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc010cb74e1a60645cfd088f51c88a13cf5687ba

Author: Jason Ekstrand 
Date:   Wed Sep 23 21:54:05 2020 -0500

nir/lower_goto_ifs: Use rzalloc

In particular, SSA forks weren't always getting properly initialized
which was causing asserts to fail.

Reviewed-by: Karol Herbst 
Part-of: 

---

 src/compiler/nir/nir_lower_goto_ifs.c | 12 ++--
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/src/compiler/nir/nir_lower_goto_ifs.c 
b/src/compiler/nir/nir_lower_goto_ifs.c
index 7f62f59212f..e12683f30b3 100644
--- a/src/compiler/nir/nir_lower_goto_ifs.c
+++ b/src/compiler/nir/nir_lower_goto_ifs.c
@@ -312,7 +312,7 @@ loop_routing_start(struct routes *routing, nir_builder *b,
   printf("\n");
}
 
-   struct routes *routing_backup = ralloc(mem_ctx, struct routes);
+   struct routes *routing_backup = rzalloc(mem_ctx, struct routes);
*routing_backup = *routing;
bool break_needed = false;
bool continue_needed = false;
@@ -342,7 +342,7 @@ loop_routing_start(struct routes *routing, nir_builder *b,
routing->loop_backup = routing_backup;
 
if (break_needed) {
-  struct path_fork *fork = ralloc(mem_ctx, struct path_fork);
+  struct path_fork *fork = rzalloc(mem_ctx, struct path_fork);
   fork->is_var = true;
   fork->path_var = nir_local_variable_create(b->impl, glsl_bool_type(),
  "path_break");
@@ -352,7 +352,7 @@ loop_routing_start(struct routes *routing, nir_builder *b,
   routing->brk.reachable = fork_reachable(fork);
}
if (continue_needed) {
-  struct path_fork *fork = ralloc(mem_ctx, struct path_fork);
+  struct path_fork *fork = rzalloc(mem_ctx, struct path_fork);
   fork->is_var = true;
   fork->path_var = nir_local_variable_create(b->impl, glsl_bool_type(),
  "path_continue");
@@ -522,7 +522,7 @@ select_fork_recur(struct nir_block **blocks, unsigned 
start, unsigned end,
if (start == end - 1)
   return NULL;
 
-   struct path_fork *fork = ralloc(mem_ctx, struct path_fork);
+   struct path_fork *fork = rzalloc(mem_ctx, struct path_fork);
fork->is_var = need_var;
if (need_var)
   fork->path_var = nir_local_variable_create(impl, glsl_bool_type(),
@@ -801,7 +801,7 @@ organize_levels(struct list_head *levels, struct set 
*children,
   routing->regular.fork = select_fork(routing->regular.reachable, impl,
   need_var, mem_ctx);
   if (level->skip_start) {
- struct path_fork *fork = ralloc(mem_ctx, struct path_fork);
+ struct path_fork *fork = rzalloc(mem_ctx, struct path_fork);
  fork->is_var = need_var;
  if (need_var)
 fork->path_var = nir_local_variable_create(impl, glsl_bool_type(),
@@ -984,7 +984,7 @@ nir_lower_goto_ifs_impl(nir_function_impl *impl)
   exec_node_data(nir_cf_node, exec_list_get_head(&cf_list.list), node);
nir_block *start_block = nir_cf_node_as_block(start_node);
 
-   struct routes *routing = ralloc(mem_ctx, struct routes);
+   struct routes *routing = rzalloc(mem_ctx, struct routes);
*routing = (struct routes) {
   .outside = empty_set,
   .regular.reachable = end_set,

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Mesa (master): nir/lower_goto_ifs: Add asserts for SSA forks

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 7749983658ec32ead48f0557d5661df91ca3a60c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7749983658ec32ead48f0557d5661df91ca3a60c

Author: Jason Ekstrand 
Date:   Wed Sep 23 16:52:18 2020 -0500

nir/lower_goto_ifs: Add asserts for SSA forks

Reviewed-by: Karol Herbst 
Part-of: 

---

 src/compiler/nir/nir_lower_goto_ifs.c | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/compiler/nir/nir_lower_goto_ifs.c 
b/src/compiler/nir/nir_lower_goto_ifs.c
index e12683f30b3..9b842a95136 100644
--- a/src/compiler/nir/nir_lower_goto_ifs.c
+++ b/src/compiler/nir/nir_lower_goto_ifs.c
@@ -170,10 +170,12 @@ set_path_vars_cond(nir_builder *b, struct path_fork 
*fork, nir_src condition,
   for (i = 0; i < 2; i++) {
  if (_mesa_set_search(fork->paths[i].reachable, then_block)) {
 if (_mesa_set_search(fork->paths[i].reachable, else_block)) {
-   if (fork->is_var)
+   if (fork->is_var) {
   nir_store_var(b, fork->path_var, nir_imm_bool(b, i), 1);
-   else
+   } else {
+  assert(fork->path_ssa == NULL);
   fork->path_ssa = nir_imm_bool(b, i);
+   }
fork = fork->paths[i].fork;
break;
 }
@@ -184,10 +186,12 @@ set_path_vars_cond(nir_builder *b, struct path_fork 
*fork, nir_src condition,
assert(ssa_def->num_components == 1);
if (!i)
   ssa_def = nir_inot(b, ssa_def);
-   if (fork->is_var)
+   if (fork->is_var) {
   nir_store_var(b, fork->path_var, ssa_def, 1);
-   else
+   } else {
+  assert(fork->path_ssa == NULL);
   fork->path_ssa = ssa_def;
+   }
set_path_vars(b, fork->paths[i].fork, then_block);
set_path_vars(b, fork->paths[!i].fork, else_block);
return;

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Mesa (master): nir/lower_goto_ifs: Always include level dom_frontiers in prev_frontier

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 57c9fc3cbaf59320d397df840d3004a58335aa04
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=57c9fc3cbaf59320d397df840d3004a58335aa04

Author: Jason Ekstrand 
Date:   Wed Sep 23 15:54:08 2020 -0500

nir/lower_goto_ifs: Always include level dom_frontiers in prev_frontier

When we come in from some other level or from the parent, we need to
ensure that the reach set is in prev_frontier but we also need to
consider the dominance frontier of our level.  Otherwise, we may end up
leaving out possible blocks when computing the reach of a level.

Acked-by: Karol Herbst 
Part-of: 

---

 src/compiler/nir/nir_lower_goto_ifs.c | 32 
 1 file changed, 12 insertions(+), 20 deletions(-)

diff --git a/src/compiler/nir/nir_lower_goto_ifs.c 
b/src/compiler/nir/nir_lower_goto_ifs.c
index 9b842a95136..f5532e0e356 100644
--- a/src/compiler/nir/nir_lower_goto_ifs.c
+++ b/src/compiler/nir/nir_lower_goto_ifs.c
@@ -738,28 +738,20 @@ organize_levels(struct list_head *levels, struct set 
*children,
 
   struct set *prev_frontier = NULL;
   if (!prev_level) {
- prev_frontier = reach;
+ prev_frontier = _mesa_set_clone(reach, curr_level);
   } else if (prev_level->irreducible) {
- prev_frontier = prev_level->reach;
-  } else {
- set_foreach(curr_level->blocks, blocks_entry) {
-nir_block *level_block = (nir_block *) blocks_entry->key;
-if (curr_level->blocks->entries == 1) {
-   /* If we only have one block, there's no union operation and we
-* can just use the one from the one block.
-*/
-   prev_frontier = level_block->dom_frontier;
-   break;
-}
+ prev_frontier = _mesa_set_clone(prev_level->reach, curr_level);
+  }
 
-if (prev_frontier == NULL) {
-   prev_frontier =
-  _mesa_set_clone(level_block->dom_frontier, prev_level);
-} else {
-   set_foreach(level_block->dom_frontier, entry)
-  _mesa_set_add_pre_hashed(prev_frontier, entry->hash,
-   entry->key);
-}
+  set_foreach(curr_level->blocks, blocks_entry) {
+ nir_block *level_block = (nir_block *) blocks_entry->key;
+ if (prev_frontier == NULL) {
+prev_frontier =
+   _mesa_set_clone(level_block->dom_frontier, curr_level);
+ } else {
+set_foreach(level_block->dom_frontier, entry)
+   _mesa_set_add_pre_hashed(prev_frontier, entry->hash,
+entry->key);
  }
   }
 

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Mesa (master): nir/lower_goto_ifs: Don't destroy SSA form in the process

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: b6a4172f1045783576c1bd2f97d4d8d9e031294d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b6a4172f1045783576c1bd2f97d4d8d9e031294d

Author: Jason Ekstrand 
Date:   Wed Sep 16 12:49:15 2020 -0500

nir/lower_goto_ifs: Don't destroy SSA form in the process

There are two issues here:

 1. If there are any phi nodes, we'll make complete hash of them.  This
isn't likely actually a problem because spirv_to_nir doesn't
generate any actual phi nodes today.  However, if we start doing any
other passes before this, we may have a problem.

 2. Even without phi nodes, we may still break SSA form.  This can
happen if we ever have to stick a block inside a conditional to
satisfy weird CFG constraints.  Doing so can cause it to no longer
look like it dominates some of its uses even though, at runtime,
it's guaranteed to be run first.

Reviewed-by: Karol Herbst 
Part-of: 

---

 src/compiler/nir/nir_lower_goto_ifs.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/src/compiler/nir/nir_lower_goto_ifs.c 
b/src/compiler/nir/nir_lower_goto_ifs.c
index 44eaf729ec5..7f62f59212f 100644
--- a/src/compiler/nir/nir_lower_goto_ifs.c
+++ b/src/compiler/nir/nir_lower_goto_ifs.c
@@ -957,6 +957,12 @@ nir_lower_goto_ifs_impl(nir_function_impl *impl)
 
nir_metadata_require(impl, nir_metadata_dominance);
 
+   /* We're going to re-arrange blocks like crazy.  This is much easier to do
+* if we don't have any phi nodes to fix up.
+*/
+   nir_foreach_block_unstructured(block, impl)
+  nir_lower_phis_to_regs_block(block);
+
nir_cf_list cf_list;
nir_cf_extract(&cf_list, nir_before_cf_list(&impl->body),
 nir_after_cf_list(&impl->body));
@@ -997,6 +1003,9 @@ nir_lower_goto_ifs_impl(nir_function_impl *impl)
 
nir_metadata_preserve(impl, nir_metadata_none);
 
+   nir_repair_ssa_impl(impl);
+   nir_lower_regs_to_ssa_impl(impl);
+
return true;
 }
 

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Mesa (master): spirv: Only run repair_ssa if structured

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: fa3c38ceb36eaa681f2ab0be7b07aefbeefc617d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa3c38ceb36eaa681f2ab0be7b07aefbeefc617d

Author: Jason Ekstrand 
Date:   Thu Sep 17 09:11:19 2020 -0500

spirv: Only run repair_ssa if structured

We shouldn't need it if we're unstructured and the pass assumes
structure so attempting to run it will assert-fail.

Reviewed-by: Karol Herbst 
Part-of: 

---

 src/compiler/spirv/vtn_cfg.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/compiler/spirv/vtn_cfg.c b/src/compiler/spirv/vtn_cfg.c
index fa7ab5eda28..4914fc645ce 100644
--- a/src/compiler/spirv/vtn_cfg.c
+++ b/src/compiler/spirv/vtn_cfg.c
@@ -1368,7 +1368,7 @@ vtn_function_emit(struct vtn_builder *b, struct 
vtn_function *func,
 * but instructions in the continue may use SSA defs in the loop body.
 * Therefore, we need to repair SSA to insert the needed phi nodes.
 */
-   if (b->has_loop_continue || b->has_kill)
+   if (b->func->impl->structured && (b->has_loop_continue || b->has_kill))
   nir_repair_ssa_impl(func->impl);
 
func->emitted = true;

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Mesa (master): nir/dominance: Use _mesa_set_clear instead ofhand-rolling it

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 719c68016a2ebb098473f2f338372b545f7cd0ac
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=719c68016a2ebb098473f2f338372b545f7cd0ac

Author: Jason Ekstrand 
Date:   Wed Sep 16 14:37:28 2020 -0500

nir/dominance: Use _mesa_set_clear instead ofhand-rolling it

Reviewed-by: Karol Herbst 
Part-of: 

---

 src/compiler/nir/nir_dominance.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/compiler/nir/nir_dominance.c b/src/compiler/nir/nir_dominance.c
index 0f4cd5a0cfe..4ea46f8f6f7 100644
--- a/src/compiler/nir/nir_dominance.c
+++ b/src/compiler/nir/nir_dominance.c
@@ -46,9 +46,7 @@ init_block(nir_block *block, nir_function_impl *impl)
block->dom_pre_index = UINT32_MAX;
block->dom_post_index = 0;
 
-   set_foreach(block->dom_frontier, entry) {
-  _mesa_set_remove(block->dom_frontier, entry);
-   }
+   _mesa_set_clear(block->dom_frontier, NULL);
 
return true;
 }

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Mesa (master): util: implement f16c - fast half<->float conversions

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 87900afe5bbe90c5f3ad0921b28ae1c889029ada
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=87900afe5bbe90c5f3ad0921b28ae1c889029ada

Author: Marek Olšák 
Date:   Fri Sep 18 05:21:09 2020 -0400

util: implement f16c - fast half<->float conversions

This also happens to fix bptc-float-modes on llvmpipe.

Acked-by: Pierre-Eric Pelloux-Prayer 
Part-of: 

---

 .gitlab-ci/piglit/quick_gl.txt   |  5 ++--
 meson.build  | 13 ++
 src/gallium/tests/unit/u_half_test.c | 25 +++-
 src/util/half_float.c|  8 +++
 src/util/half_float.h| 46 
 src/util/softfloat.c |  2 +-
 src/util/softfloat.h |  2 +-
 7 files changed, 82 insertions(+), 19 deletions(-)

diff --git a/.gitlab-ci/piglit/quick_gl.txt b/.gitlab-ci/piglit/quick_gl.txt
index a24ae0d3647..104d2f6cd01 100644
--- a/.gitlab-ci/piglit/quick_gl.txt
+++ b/.gitlab-ci/piglit/quick_gl.txt
@@ -738,7 +738,6 @@ spec/arb_sparse_buffer/commit: skip
 spec/arb_sparse_buffer/minmax: skip
 
spec/arb_tessellation_shader/arb_tessellation_shader-immediate-mode-draw-patches:
 skip
 spec/arb_texture_buffer_object/negative-unsupported: skip
-spec/arb_texture_compression_bptc/bptc-float-modes: fail
 spec/arb_texture_cube_map/copyteximage cube samples=16: skip
 spec/arb_texture_cube_map/copyteximage cube samples=2: skip
 spec/arb_texture_cube_map/copyteximage cube samples=32: skip
@@ -1656,8 +1655,8 @@ wgl/wgl-sanity: skip
 summary:
name:  results
  
-   pass:23074
-   fail:  198
+   pass:23075
+   fail:  197
   crash:0
skip: 1433
 timeout:0
diff --git a/meson.build b/meson.build
index 76f72a9df7c..b855710e787 100644
--- a/meson.build
+++ b/meson.build
@@ -,6 +,19 @@ else
   sse41_args = []
 endif
 
+if cc.has_argument('-mf16c') and cpp.has_argument('-mf16c')
+  pre_args += '-DUSE_F16C'
+  c_args += '-mf16c'
+  cpp_args += '-mf16c'
+
+  # GCC on x86 (not x86_64) with -msse* assumes a 16 byte aligned stack, but
+  # that's not guaranteed (not sure if this also applies to -mf16c)
+  if host_machine.cpu_family() == 'x86'
+c_args += '-mstackrealign'
+cpp_args += '-mstackrealign'
+  endif
+endif
+
 # Check for GCC style atomics
 dep_atomic = null_dep
 
diff --git a/src/gallium/tests/unit/u_half_test.c 
b/src/gallium/tests/unit/u_half_test.c
index 48a9a2d539c..fb4ce6ec9f2 100644
--- a/src/gallium/tests/unit/u_half_test.c
+++ b/src/gallium/tests/unit/u_half_test.c
@@ -4,9 +4,10 @@
 
 #include "util/u_math.h"
 #include "util/u_half.h"
+#include "util/u_cpu_detect.h"
 
-int
-main(int argc, char **argv)
+static void
+test(void)
 {
unsigned i;
unsigned roundtrip_fails = 0;
@@ -28,9 +29,21 @@ main(int argc, char **argv)
 
if(roundtrip_fails) {
   printf("Failure! %u/65536 half floats failed a conversion to float and 
back.\n", roundtrip_fails);
-  return 1;
-   } else {
-  printf("Success!\n");
-  return 0;
+  exit(1);
}
 }
+
+int
+main(int argc, char **argv)
+{
+   assert(!util_cpu_caps.has_f16c);
+   test();
+
+   /* Test f16c. */
+   util_cpu_detect();
+   if (util_cpu_caps.has_f16c)
+  test();
+
+   printf("Success!\n");
+   return 0;
+}
diff --git a/src/util/half_float.c b/src/util/half_float.c
index aae690a56a6..61b512f48ed 100644
--- a/src/util/half_float.c
+++ b/src/util/half_float.c
@@ -54,7 +54,7 @@ typedef union { float f; int32_t i; uint32_t u; } fi_type;
  * result in the same value as if the expression were executed on the GPU.
  */
 uint16_t
-_mesa_float_to_half(float val)
+_mesa_float_to_half_slow(float val)
 {
const fi_type fi = {val};
const int flt_m = fi.i & 0x7f;
@@ -129,9 +129,9 @@ _mesa_float_to_half(float val)
 }
 
 uint16_t
-_mesa_float_to_float16_rtz(float val)
+_mesa_float_to_float16_rtz_slow(float val)
 {
-return _mesa_float_to_half_rtz(val);
+return _mesa_float_to_half_rtz_slow(val);
 }
 
 /**
@@ -140,7 +140,7 @@ _mesa_float_to_float16_rtz(float val)
  * http://www.opengl.org/discussion_boards/ubb/Forum3/HTML/008786.html
  */
 float
-_mesa_half_to_float(uint16_t val)
+_mesa_half_to_float_slow(uint16_t val)
 {
return util_half_to_float(val);
 }
diff --git a/src/util/half_float.h b/src/util/half_float.h
index c9fad9a9400..6f9a405613b 100644
--- a/src/util/half_float.h
+++ b/src/util/half_float.h
@@ -28,6 +28,14 @@
 
 #include 
 #include 
+#include 
+#include "util/u_cpu_detect.h"
+
+#ifdef USE_F16C
+#include 
+#define F16C_NEAREST 0
+#define F16C_TRUNCATE 3
+#endif
 
 #ifdef __cplusplus
 extern "C" {
@@ -36,18 +44,48 @@ extern "C" {
 #define FP16_ONE ((uint16_t) 0x3c00)
 #define FP16_ZERO((uint16_t) 0)
 
-uint16_t _mesa_float_to_half(float val);
-float _mesa_half_to_float(uint16_t val);
+uint16_t _mesa_float_to_half_slow(float val);

Mesa (master): util: remove util_float_to_half and util_half_to_float wrappers

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 2b6a17234376817e75d1f81edf5bd1b28eefb374
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b6a17234376817e75d1f81edf5bd1b28eefb374

Author: Marek Olšák 
Date:   Fri Sep 18 05:53:56 2020 -0400

util: remove util_float_to_half and util_half_to_float wrappers

Acked-by: Pierre-Eric Pelloux-Prayer 
Part-of: 

---

 src/freedreno/registers/gen_header.py  |  2 +-
 src/freedreno/rnn/headergen2.c |  2 +-
 src/freedreno/vulkan/tu_clear_blit.c   |  2 +-
 src/gallium/auxiliary/gallivm/lp_bld_const.c   |  4 +--
 src/gallium/auxiliary/gallivm/lp_bld_conv.c|  4 +--
 src/gallium/auxiliary/tgsi/tgsi_exec.c |  8 ++---
 .../auxiliary/translate/translate_generic.c|  2 +-
 src/gallium/auxiliary/util/u_half.h| 12 ---
 src/gallium/drivers/etnaviv/etnaviv_blend.c|  8 ++---
 src/gallium/drivers/etnaviv/etnaviv_disasm.c   |  2 +-
 src/gallium/drivers/etnaviv/etnaviv_zsa.c  |  2 +-
 src/gallium/drivers/freedreno/a5xx/fd5_emit.c  |  4 +--
 src/gallium/drivers/freedreno/a6xx/fd6_emit.c  |  4 +--
 src/gallium/drivers/freedreno/freedreno_texture.c  |  2 +-
 src/gallium/drivers/lima/ir/pp/codegen.c   |  2 +-
 src/gallium/drivers/lima/ir/pp/disasm.c|  2 +-
 src/gallium/drivers/lima/lima_draw.c   |  2 +-
 .../drivers/nouveau/nv30/nv30_state_validate.c |  8 ++---
 src/gallium/drivers/r300/r300_state.c  | 10 +++---
 src/gallium/drivers/v3d/v3dx_emit.c|  6 ++--
 src/gallium/drivers/v3d/v3dx_state.c   | 10 +++---
 src/gallium/frontends/nine/vertexshader9.h |  4 +--
 src/gallium/tests/unit/translate_test.c|  2 +-
 src/gallium/tests/unit/u_half_test.c   |  4 +--
 src/mesa/vbo/vbo_attrib_tmp.h  | 42 +++---
 src/util/format/u_format_pack.py   |  2 +-
 26 files changed, 70 insertions(+), 82 deletions(-)

diff --git a/src/freedreno/registers/gen_header.py 
b/src/freedreno/registers/gen_header.py
index 9657dff014c..480911a280b 100644
--- a/src/freedreno/registers/gen_header.py
+++ b/src/freedreno/registers/gen_header.py
@@ -78,7 +78,7 @@ class Field(object):
val = "fui(%s)" % var_name
elif self.type == "float" and self.high - self.low == 15:
type = "float"
-   val = "util_float_to_half(%s)" % var_name
+   val = "_mesa_float_to_half(%s)" % var_name
elif self.type in [ "address", "waddress" ]:
type = "uint64_t"
val = var_name
diff --git a/src/freedreno/rnn/headergen2.c b/src/freedreno/rnn/headergen2.c
index d5a3eb7562e..478dde3e6c2 100644
--- a/src/freedreno/rnn/headergen2.c
+++ b/src/freedreno/rnn/headergen2.c
@@ -201,7 +201,7 @@ static void printtypeinfo (struct rnntypeinfo *ti, struct 
rnnbitfield *bf,
if (width == 32)
fprintf(dst, "fui(val)");
else if (width == 16)
-   fprintf(dst, "util_float_to_half(val)");
+   fprintf(dst, "_mesa_float_to_half(val)");
else
assert(!"invalid float size");
} else {
diff --git a/src/freedreno/vulkan/tu_clear_blit.c 
b/src/freedreno/vulkan/tu_clear_blit.c
index a645831ed4c..96e48751105 100644
--- a/src/freedreno/vulkan/tu_clear_blit.c
+++ b/src/freedreno/vulkan/tu_clear_blit.c
@@ -122,7 +122,7 @@ r2d_clear_value(struct tu_cs *cs, VkFormat format, const 
VkClearValue *val)
 else
clear_value[i] = tu_pack_float32_for_unorm(linear, 8);
  } else if (ifmt == R2D_FLOAT16) {
-clear_value[i] = util_float_to_half(val->color.float32[i]);
+clear_value[i] = _mesa_float_to_half(val->color.float32[i]);
  } else {
 assert(ifmt == R2D_FLOAT32 || ifmt == R2D_INT32 ||
ifmt == R2D_INT16 || ifmt == R2D_INT8);
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_const.c 
b/src/gallium/auxiliary/gallivm/lp_bld_const.c
index 58fdcc94437..63a6599284f 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_const.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_const.c
@@ -257,7 +257,7 @@ lp_build_one(struct gallivm_state *gallivm, struct lp_type 
type)
elem_type = lp_build_elem_type(gallivm, type);
 
if(type.floating && type.width == 16)
-  elems[0] = LLVMConstInt(elem_type, util_float_to_half(1.0f), 0);
+  elems[0] = LLVMConstInt(elem_type, _mesa_float_to_half(1.0f), 0);
else if(type.floating)
   elems[0] = LLVMConstReal(elem_type, 1.0);
else if(type.fixed)
@@ -304,7 +304,7 @@ lp_build_const_elem(struct gallivm_state *gallivm,
LLVMValueRef elem;
 
if(type.floating &

Mesa (master): gallium/util: remove empty file u_half.h

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 4fb2eddfdf9adafde2e6f94de23202ee44123d59
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4fb2eddfdf9adafde2e6f94de23202ee44123d59

Author: Marek Olšák 
Date:   Sat Sep 19 14:11:02 2020 -0400

gallium/util: remove empty file u_half.h

Acked-by: Pierre-Eric Pelloux-Prayer 
Part-of: 

---

 src/amd/vulkan/radv_formats.c  |  2 +-
 src/freedreno/fdl/fd5_layout_test.c|  3 +-
 src/freedreno/perfcntrs/fd2_perfcntr.c |  3 +-
 src/freedreno/perfcntrs/fd5_perfcntr.c |  3 +-
 src/freedreno/perfcntrs/fd6_perfcntr.c |  3 +-
 src/freedreno/perfcntrs/freedreno_perfcntr.h   |  2 ++
 src/freedreno/vulkan/tu_clear_blit.c   |  2 +-
 src/gallium/auxiliary/Makefile.sources |  1 -
 src/gallium/auxiliary/gallivm/lp_bld_const.c   |  2 +-
 src/gallium/auxiliary/gallivm/lp_bld_conv.c|  2 +-
 src/gallium/auxiliary/meson.build  |  1 -
 src/gallium/auxiliary/tgsi/tgsi_exec.c |  2 +-
 .../auxiliary/translate/translate_generic.c|  2 +-
 src/gallium/auxiliary/util/u_half.h| 36 --
 src/gallium/drivers/etnaviv/etnaviv_blend.c|  2 +-
 src/gallium/drivers/etnaviv/etnaviv_compiler_nir.c |  2 +-
 src/gallium/drivers/etnaviv/etnaviv_disasm.c   |  2 +-
 src/gallium/drivers/etnaviv/etnaviv_zsa.c  |  2 +-
 src/gallium/drivers/freedreno/freedreno_util.h |  2 +-
 src/gallium/drivers/lima/ir/pp/codegen.c   |  2 +-
 src/gallium/drivers/lima/ir/pp/disasm.c|  2 +-
 src/gallium/drivers/lima/lima_draw.c   |  2 +-
 .../drivers/nouveau/nv30/nv30_state_validate.c |  2 +-
 src/gallium/drivers/r300/r300_blit.c   |  2 +-
 src/gallium/drivers/r300/r300_state.c  |  2 +-
 src/gallium/drivers/v3d/v3dx_emit.c|  2 +-
 src/gallium/drivers/v3d/v3dx_state.c   |  2 +-
 src/gallium/frontends/nine/vertexshader9.h |  2 +-
 src/gallium/tests/unit/translate_test.c|  2 +-
 src/gallium/tests/unit/u_half_test.c   |  2 +-
 src/mesa/vbo/vbo_attrib_tmp.h  |  2 +-
 src/util/format/u_format_pack.py   |  2 +-
 src/util/half_float.c  |  2 +-
 src/util/tests/format/u_format_test.c  |  3 +-
 34 files changed, 37 insertions(+), 68 deletions(-)

diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index a839e2db43d..bf76b6b2551 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -29,7 +29,7 @@
 
 #include "vk_util.h"
 
-#include "util/u_half.h"
+#include "util/half_float.h"
 #include "util/format_srgb.h"
 #include "util/format_r11g11b10f.h"
 #include "util/format_rgb9e5.h"
diff --git a/src/freedreno/fdl/fd5_layout_test.c 
b/src/freedreno/fdl/fd5_layout_test.c
index 71ed259e1fc..e8496996d3b 100644
--- a/src/freedreno/fdl/fd5_layout_test.c
+++ b/src/freedreno/fdl/fd5_layout_test.c
@@ -24,7 +24,8 @@
 #include "freedreno_layout.h"
 #include "fd_layout_test.h"
 #include "adreno_common.xml.h"
-#include "util/u_half.h"
+#include "util/half_float.h"
+#include "util/u_math.h"
 #include "a5xx.xml.h"
 
 #include 
diff --git a/src/freedreno/perfcntrs/fd2_perfcntr.c 
b/src/freedreno/perfcntrs/fd2_perfcntr.c
index eac2de0214b..a0f1ef8b3c0 100644
--- a/src/freedreno/perfcntrs/fd2_perfcntr.c
+++ b/src/freedreno/perfcntrs/fd2_perfcntr.c
@@ -25,7 +25,8 @@
  *Rob Clark 
  */
 
-#include "util/u_half.h"
+#include "util/half_float.h"
+#include "util/u_math.h"
 #include "adreno_common.xml.h"
 #include "adreno_pm4.xml.h"
 #include "a2xx.xml.h"
diff --git a/src/freedreno/perfcntrs/fd5_perfcntr.c 
b/src/freedreno/perfcntrs/fd5_perfcntr.c
index 2d0579ca363..0d8d2ae47b5 100644
--- a/src/freedreno/perfcntrs/fd5_perfcntr.c
+++ b/src/freedreno/perfcntrs/fd5_perfcntr.c
@@ -27,7 +27,8 @@
 #ifndef FD5_PERFCNTR_H_
 #define FD5_PERFCNTR_H_
 
-#include "util/u_half.h"
+#include "util/half_float.h"
+#include "util/u_math.h"
 #include "adreno_common.xml.h"
 #include "a5xx.xml.h"
 
diff --git a/src/freedreno/perfcntrs/fd6_perfcntr.c 
b/src/freedreno/perfcntrs/fd6_perfcntr.c
index 02e55f8babd..f50a72e3bac 100644
--- a/src/freedreno/perfcntrs/fd6_perfcntr.c
+++ b/src/freedreno/perfcntrs/fd6_perfcntr.c
@@ -27,7 +27,8 @@
 #ifndef FD6_PERFCNTR_H_
 #define FD6_PERFCNTR_H_
 
-#include "util/u_half.h"
+#include "util/half_float.h"
+#include "util/u_math.h"
 #include "adreno_common.xml.h"
 #include "adreno_pm4.xml.h"
 #include "a6xx.xml.h"
diff --git a/src/freedreno/perfcntrs/freedreno_perfcntr.h 
b/src/freedreno/perfcntrs/freedreno_perfcntr.h
index 867048afc1c..250ea92fc37 100644
--- a/src/freedreno/perfcntrs/freedreno_perfcntr.h
+++ b/src/freedreno/perfcntrs/freedreno_perfcntr.h
@@ -27,6 +27,8 @@
 #ifndef FREEDRENO_PERFCNTR_H_
 #define FREEDRENO_PERFCNTR_H_
 
+#include "util/m

Mesa (master): gallium/util: remove redundant util_float_to_half_rtz

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 7a1deb16f8af4e0ae4ed64511cbfcc606087f0ee
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a1deb16f8af4e0ae4ed64511cbfcc606087f0ee

Author: Marek Olšák 
Date:   Fri Sep 18 06:00:06 2020 -0400

gallium/util: remove redundant util_float_to_half_rtz

Acked-by: Pierre-Eric Pelloux-Prayer 
Part-of: 

---

 src/amd/vulkan/radv_formats.c   |  2 +-
 src/gallium/auxiliary/util/u_half.h | 73 -
 src/util/format/u_format_pack.py|  2 +-
 src/util/format/u_format_tests.c|  3 ++
 4 files changed, 5 insertions(+), 75 deletions(-)

diff --git a/src/amd/vulkan/radv_formats.c b/src/amd/vulkan/radv_formats.c
index ed9e30f101a..a839e2db43d 100644
--- a/src/amd/vulkan/radv_formats.c
+++ b/src/amd/vulkan/radv_formats.c
@@ -1079,7 +1079,7 @@ bool radv_format_pack_clear_color(VkFormat format,
if (channel->size == 32) {
memcpy(&v, &value->float32[c], 4);
} else if(channel->size == 16) {
-   v = util_float_to_half_rtz(value->float32[c]);
+   v = 
_mesa_float_to_float16_rtz(value->float32[c]);
} else {
fprintf(stderr, "failed to fast clear for 
unhandled float size in format %d\n", format);
return false;
diff --git a/src/gallium/auxiliary/util/u_half.h 
b/src/gallium/auxiliary/util/u_half.h
index 5146897e867..bb1a048b2c2 100644
--- a/src/gallium/auxiliary/util/u_half.h
+++ b/src/gallium/auxiliary/util/u_half.h
@@ -32,78 +32,5 @@
 #include "util/u_math.h"
 #include "util/half_float.h"
 
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*
- * References for float <-> half conversions
- *
- *  http://fgiesen.wordpress.com/2012/03/28/half-to-float-done-quic/
- *  https://gist.github.com/2156668
- *  https://gist.github.com/2144712
- */
-
-static inline uint16_t
-util_float_to_half_rtz(float f)
-{
-   uint32_t sign_mask  = 0x8000;
-   uint32_t round_mask = ~0xfff;
-   uint32_t f32inf = 0xff << 23;
-   uint32_t f16inf = 0x1f << 23;
-   uint32_t sign;
-   union fi magic;
-   union fi f32;
-   uint16_t f16;
-
-   magic.ui = 0xf << 23;
-
-   f32.f = f;
-
-   /* Sign */
-   sign = f32.ui & sign_mask;
-   f32.ui ^= sign;
-
-   if (f32.ui == f32inf) {
-  /* Inf */
-  f16 = 0x7c00;
-   } else if (f32.ui > f32inf) {
-  /* NaN */
-  f16 = 0x7e00;
-   } else {
-  /* Number */
-  f32.ui &= round_mask;
-  f32.f  *= magic.f;
-  f32.ui -= round_mask;
-  /*
-   * XXX: The magic mul relies on denorms being available, otherwise
-   * all f16 denorms get flushed to zero - hence when this is used
-   * for tgsi_exec in softpipe we won't get f16 denorms.
-   */
-  /*
-   * Clamp to max finite value if overflowed.
-   * OpenGL has completely undefined rounding behavior for float to
-   * half-float conversions, and this matches what is mandated for float
-   * to fp11/fp10, which recommend round-to-nearest-finite too.
-   * (d3d10 is deeply unhappy about flushing such values to infinity, and
-   * while it also mandates round-to-zero it doesn't care nearly as much
-   * about that.)
-   */
-  if (f32.ui > f16inf)
- f32.ui = f16inf - 1;
-
-  f16 = f32.ui >> 13;
-   }
-
-   /* Sign */
-   f16 |= sign >> 16;
-
-   return f16;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
 #endif /* U_HALF_H */
 
diff --git a/src/util/format/u_format_pack.py b/src/util/format/u_format_pack.py
index 4da64dfc0c7..9cdd122d4fe 100644
--- a/src/util/format/u_format_pack.py
+++ b/src/util/format/u_format_pack.py
@@ -436,7 +436,7 @@ def conversion_expr(src_channel,
 src_size = 32
 
 if dst_channel.size == 16:
-value = 'util_float_to_half_rtz(%s)' % value
+value = '_mesa_float_to_float16_rtz(%s)' % value
 elif dst_channel.size == 64 and src_size < 64:
 value = '(double)%s' % value
 
diff --git a/src/util/format/u_format_tests.c b/src/util/format/u_format_tests.c
index 0c34a822b99..0cc4de86d88 100644
--- a/src/util/format/u_format_tests.c
+++ b/src/util/format/u_format_tests.c
@@ -914,8 +914,11 @@ util_format_test_cases[] =
{PIPE_FORMAT_R16_FLOAT, PACKED_1x16(0x), PACKED_1x16(0x03FF), 
UNPACKED_1x1( 6.09756E-5, 0.0, 0.0, 1.0)},
 #endif
 
+   /* This fails with _mesa_float_to_float16_rtz, but passes with 
_mesa_float_to_float16_rtne. */
+#if 0
/* Minimum positive denormal */
{PIPE_FORMAT_R16_FLOAT, PACKED_1x16(0x), PACKED_1x16(0x0001), 
UNPACKED_1x1( 5.96046E-8, 0.0, 0.0, 1.0)},
+#endif
 
/* Min representable value */
{PIPE_FORMAT_R16_FLOAT, PACKED_1x16(0x), PACKED_1x16(0xfbff), 
UNPACKED_1x1(   -65504.0, 0.0, 0.0, 1.0)},

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Mesa (master): util: move util_half_to_float code into _mesa_half_to_float_slow

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 5af81393e419eaf086e4de2a1d149af78cd1f54d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5af81393e419eaf086e4de2a1d149af78cd1f54d

Author: Marek Olšák 
Date:   Fri Sep 18 05:48:05 2020 -0400

util: move util_half_to_float code into _mesa_half_to_float_slow

Acked-by: Pierre-Eric Pelloux-Prayer 
Part-of: 

---

 src/gallium/auxiliary/util/u_half.h | 24 +---
 src/util/half_float.c   | 24 +++-
 2 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_half.h 
b/src/gallium/auxiliary/util/u_half.h
index bbcc843c310..04c59302765 100644
--- a/src/gallium/auxiliary/util/u_half.h
+++ b/src/gallium/auxiliary/util/u_half.h
@@ -110,29 +110,7 @@ util_float_to_half_rtz(float f)
 static inline float
 util_half_to_float(uint16_t f16)
 {
-   union fi infnan;
-   union fi magic;
-   union fi f32;
-
-   infnan.ui = 0x8f << 23;
-   infnan.f = 65536.0f;
-   magic.ui  = 0xef << 23;
-
-   /* Exponent / Mantissa */
-   f32.ui = (f16 & 0x7fff) << 13;
-
-   /* Adjust */
-   f32.f *= magic.f;
-   /* XXX: The magic mul relies on denorms being available */
-
-   /* Inf / NaN */
-   if (f32.f >= infnan.f)
-  f32.ui |= 0xff << 23;
-
-   /* Sign */
-   f32.ui |= (uint32_t)(f16 & 0x8000) << 16;
-
-   return f32.f;
+   return _mesa_half_to_float(f16);
 }
 
 #ifdef __cplusplus
diff --git a/src/util/half_float.c b/src/util/half_float.c
index 61b512f48ed..0d1e6a9551e 100644
--- a/src/util/half_float.c
+++ b/src/util/half_float.c
@@ -142,7 +142,29 @@ _mesa_float_to_float16_rtz_slow(float val)
 float
 _mesa_half_to_float_slow(uint16_t val)
 {
-   return util_half_to_float(val);
+   union fi infnan;
+   union fi magic;
+   union fi f32;
+
+   infnan.ui = 0x8f << 23;
+   infnan.f = 65536.0f;
+   magic.ui  = 0xef << 23;
+
+   /* Exponent / Mantissa */
+   f32.ui = (val & 0x7fff) << 13;
+
+   /* Adjust */
+   f32.f *= magic.f;
+   /* XXX: The magic mul relies on denorms being available */
+
+   /* Inf / NaN */
+   if (f32.f >= infnan.f)
+  f32.ui |= 0xff << 23;
+
+   /* Sign */
+   f32.ui |= (uint32_t)(val & 0x8000) << 16;
+
+   return f32.f;
 }
 
 /**

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Mesa (staging/20.2): VERSION: bump for 20.2.0 release

[GitLab Mirror]

Module: Mesa
Branch: staging/20.2
Commit: 663d464366675bf6d44c5d4d00e04cbdfa3f6057
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=663d464366675bf6d44c5d4d00e04cbdfa3f6057

Author: Dylan Baker 
Date:   Mon Sep 28 15:50:54 2020 -0700

VERSION: bump for 20.2.0 release

---

 VERSION | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/VERSION b/VERSION
index 5f8e39e1b00..86d4688d091 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-20.2.0-rc4
+20.2.0

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Mesa (staging/20.2): radeonsi: fix indirect dispatches with variable block sizes

[GitLab Mirror]

Module: Mesa
Branch: staging/20.2
Commit: 401e03925d0bdcd761e6bbfa0a2825de59c08a8d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=401e03925d0bdcd761e6bbfa0a2825de59c08a8d

Author: Marek Olšák 
Date:   Thu Sep 17 19:45:14 2020 -0400

radeonsi: fix indirect dispatches with variable block sizes

The block size input was uninitialized.

Fixes: 77c81164bc1c "radeonsi: support ARB_compute_variable_group_size"

Acked-by: Pierre-Eric Pelloux-Prayer 
Part-of: 
(cherry picked from commit 8be46d6558e04f5dc9b8bebd31a36b1f3d593aa6)

---

 .pick_status.json |  2 +-
 src/gallium/drivers/radeonsi/si_compute.c | 21 ++---
 2 files changed, 11 insertions(+), 12 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 52518971660..78ec2b91f4c 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1444,7 +1444,7 @@
 "description": "radeonsi: fix indirect dispatches with variable block 
sizes",
 "nominated": true,
 "nomination_type": 1,
-"resolution": 0,
+"resolution": 1,
 "master_sha": null,
 "because_sha": "77c81164bc1cd9ec98b32c40753f590791450434"
 },
diff --git a/src/gallium/drivers/radeonsi/si_compute.c 
b/src/gallium/drivers/radeonsi/si_compute.c
index 4f8618cf775..6d97ed5ec88 100644
--- a/src/gallium/drivers/radeonsi/si_compute.c
+++ b/src/gallium/drivers/radeonsi/si_compute.c
@@ -703,27 +703,26 @@ static void si_setup_nir_user_data(struct si_context 
*sctx, const struct pipe_gr
  12 * sel->info.uses_grid_size;
unsigned cs_user_data_reg = block_size_reg + 12 * 
program->reads_variable_block_size;
 
-   if (info->indirect) {
-  if (sel->info.uses_grid_size) {
+   if (sel->info.uses_grid_size) {
+  if (info->indirect) {
  for (unsigned i = 0; i < 3; ++i) {
 si_cp_copy_data(sctx, sctx->gfx_cs, COPY_DATA_REG, NULL, 
(grid_size_reg >> 2) + i,
 COPY_DATA_SRC_MEM, si_resource(info->indirect),
 info->indirect_offset + 4 * i);
  }
-  }
-   } else {
-  if (sel->info.uses_grid_size) {
+  } else {
  radeon_set_sh_reg_seq(cs, grid_size_reg, 3);
  radeon_emit(cs, info->grid[0]);
  radeon_emit(cs, info->grid[1]);
  radeon_emit(cs, info->grid[2]);
   }
-  if (program->reads_variable_block_size) {
- radeon_set_sh_reg_seq(cs, block_size_reg, 3);
- radeon_emit(cs, info->block[0]);
- radeon_emit(cs, info->block[1]);
- radeon_emit(cs, info->block[2]);
-  }
+   }
+
+   if (program->reads_variable_block_size) {
+  radeon_set_sh_reg_seq(cs, block_size_reg, 3);
+  radeon_emit(cs, info->block[0]);
+  radeon_emit(cs, info->block[1]);
+  radeon_emit(cs, info->block[2]);
}
 
if (program->num_cs_user_data_dwords) {

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Mesa (staging/20.2): gallium/vl: do not call transfer_unmap if transfer is NULL

[GitLab Mirror]

Module: Mesa
Branch: staging/20.2
Commit: e84d418bd1501a956dd9920619b2af709a31e551
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e84d418bd1501a956dd9920619b2af709a31e551

Author: Pierre-Eric Pelloux-Prayer 
Date:   Tue Sep 22 14:31:32 2020 +0200

gallium/vl: do not call transfer_unmap if transfer is NULL

CC: mesa-stable
Acked-by: Leo Liu 
Part-of: 
(cherry picked from commit b121b1b8b8f6df790dd8150a8b5e8021dc9e56bb)

---

 .pick_status.json| 2 +-
 src/gallium/auxiliary/vl/vl_mpeg12_decoder.c | 3 ++-
 src/gallium/auxiliary/vl/vl_vertex_buffers.c | 6 --
 3 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 478fbbd2eaf..5416e6da36d 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -733,7 +733,7 @@
 "description": "gallium/vl: do not call transfer_unmap if transfer is 
NULL",
 "nominated": true,
 "nomination_type": 0,
-"resolution": 0,
+"resolution": 1,
 "master_sha": null,
 "because_sha": null
 },
diff --git a/src/gallium/auxiliary/vl/vl_mpeg12_decoder.c 
b/src/gallium/auxiliary/vl/vl_mpeg12_decoder.c
index 8a04158145a..c522498c3e7 100644
--- a/src/gallium/auxiliary/vl/vl_mpeg12_decoder.c
+++ b/src/gallium/auxiliary/vl/vl_mpeg12_decoder.c
@@ -769,7 +769,8 @@ vl_mpeg12_end_frame(struct pipe_video_codec *decoder,
 
vl_vb_unmap(&buf->vertex_stream, dec->context);
 
-   dec->context->transfer_unmap(dec->context, buf->tex_transfer);
+   if (buf->tex_transfer)
+  dec->context->transfer_unmap(dec->context, buf->tex_transfer);
 
vb[0] = dec->quads;
vb[1] = dec->pos;
diff --git a/src/gallium/auxiliary/vl/vl_vertex_buffers.c 
b/src/gallium/auxiliary/vl/vl_vertex_buffers.c
index 7e6fdfaaf56..90f69c3c2b6 100644
--- a/src/gallium/auxiliary/vl/vl_vertex_buffers.c
+++ b/src/gallium/auxiliary/vl/vl_vertex_buffers.c
@@ -352,11 +352,13 @@ vl_vb_unmap(struct vl_vertex_buffer *buffer, struct 
pipe_context *pipe)
assert(buffer && pipe);
 
for (i = 0; i < VL_NUM_COMPONENTS; ++i) {
-  pipe_buffer_unmap(pipe, buffer->ycbcr[i].transfer);
+  if (buffer->ycbcr[i].transfer)
+ pipe_buffer_unmap(pipe, buffer->ycbcr[i].transfer);
}
 
for (i = 0; i < VL_MAX_REF_FRAMES; ++i) {
-  pipe_buffer_unmap(pipe, buffer->mv[i].transfer);
+  if (buffer->mv[i].transfer)
+ pipe_buffer_unmap(pipe, buffer->mv[i].transfer);
}
 }
 

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Mesa (staging/20.2): st/mesa: use roundf instead of floorf for lod-bias rounding

[GitLab Mirror]

Module: Mesa
Branch: staging/20.2
Commit: 09c31b46d39bf05e10b791dd0793091ab1366327
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=09c31b46d39bf05e10b791dd0793091ab1366327

Author: Erik Faye-Lund 
Date:   Mon Sep 28 16:11:38 2020 +0200

st/mesa: use roundf instead of floorf for lod-bias rounding

There's no good reason not to use a symmetric rounding mode here. This
fixes the following GL CTS case for me:

GTF-GL33.gtf21.GL3Tests.texture_lod_bias.texture_lod_bias_all

Fixes: 132b69c4edb ("st/mesa: round lod_bias to a multiple of 1/256")
Reviewed-by: Marek Olšák 
Part-of: 
(cherry picked from commit 7685c37bf47104497d70c4580abb9e050ea8100f)

---

 .pick_status.json| 2 +-
 src/mesa/state_tracker/st_atom_sampler.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index d68fbf92e85..a1d3640953d 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -220,7 +220,7 @@
 "description": "st/mesa: use roundf instead of floorf for lod-bias 
rounding",
 "nominated": true,
 "nomination_type": 1,
-"resolution": 0,
+"resolution": 1,
 "master_sha": null,
 "because_sha": "132b69c4edb824c70c98f8937c63e49b04f3adff"
 },
diff --git a/src/mesa/state_tracker/st_atom_sampler.c 
b/src/mesa/state_tracker/st_atom_sampler.c
index 7ae981b71b4..3efbdc2c827 100644
--- a/src/mesa/state_tracker/st_atom_sampler.c
+++ b/src/mesa/state_tracker/st_atom_sampler.c
@@ -132,7 +132,7 @@ st_convert_sampler(const struct st_context *st,
 * levels.
 */
sampler->lod_bias = CLAMP(sampler->lod_bias, -16, 16);
-   sampler->lod_bias = floorf(sampler->lod_bias * 256) / 256;
+   sampler->lod_bias = roundf(sampler->lod_bias * 256) / 256;
 
sampler->min_lod = MAX2(msamp->MinLod, 0.0f);
sampler->max_lod = msamp->MaxLod;

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Mesa (staging/20.2): nir/lower_io_arrays: Fix xfb_offset bug

[GitLab Mirror]

Module: Mesa
Branch: staging/20.2
Commit: 79263cda925e4de5a5eb7dde9459a0d630037e26
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=79263cda925e4de5a5eb7dde9459a0d630037e26

Author: Connor Abbott 
Date:   Fri Aug 21 15:51:47 2020 +0200

nir/lower_io_arrays: Fix xfb_offset bug

I noticed this once I started gathering xfb_info after
nir_lower_io_arrays_to_elements_no_indirect.

Fixes: b2bbd978d0b ("nir: fix lowering arrays to elements for XFB outputs")
Reviewed-by: Caio Marcelo de Oliveira Filho 
Part-of: 
(cherry picked from commit 5a88db682e08b5e58b40653872569f5b5d7d)

---

 .pick_status.json  | 2 +-
 src/compiler/nir/nir_lower_io_arrays_to_elements.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index a1d3640953d..d893e0a590c 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -121,7 +121,7 @@
 "description": "nir/lower_io_arrays: Fix xfb_offset bug",
 "nominated": true,
 "nomination_type": 1,
-"resolution": 0,
+"resolution": 1,
 "master_sha": null,
 "because_sha": "b2bbd978d0b1c85919c6f3b5f631b3c6cbaaaf8a"
 },
diff --git a/src/compiler/nir/nir_lower_io_arrays_to_elements.c 
b/src/compiler/nir/nir_lower_io_arrays_to_elements.c
index e49abefc0d4..376326575b0 100644
--- a/src/compiler/nir/nir_lower_io_arrays_to_elements.c
+++ b/src/compiler/nir/nir_lower_io_arrays_to_elements.c
@@ -61,7 +61,7 @@ get_io_offset(nir_builder *b, nir_deref_instr *deref, 
nir_variable *var,
  unsigned size = glsl_count_attribute_slots((*p)->type, false);
  offset += size * index;
 
- xfb_offset += index * glsl_get_component_slots((*p)->type) * 4;
+ *xfb_offset += index * glsl_get_component_slots((*p)->type) * 4;
 
  unsigned num_elements = glsl_type_is_array((*p)->type) ?
 glsl_get_aoa_size((*p)->type) : 1;

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Mesa (staging/20.2): etnaviv: simplify linear stride implementation

[GitLab Mirror]

Module: Mesa
Branch: staging/20.2
Commit: fbbd66dcad05cec8548b9d77edc2e2eab09bc675
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fbbd66dcad05cec8548b9d77edc2e2eab09bc675

Author: Christian Gmeiner 
Date:   Sat Jan  4 07:13:47 2020 +0100

etnaviv: simplify linear stride implementation

As documented in the galcore kernel driver "only LOD0 is valid
for this register". This makes sense, as NTE's LINEAR_STRIDE is
only capable to store one linear stride value per sampler.
This fixes linear textures in sampler slot != 0.

Fixes: 34458c1cf6c ("etnaviv: add linear sampling support")
CC: 
Signed-off-by: Christian Gmeiner 
Reviewed-by: Michael Tretter 
Part-of: 
(cherry picked from commit a7e3cc7a0eafc1076a2f7775f754e74584fc3537)

---

 .pick_status.json   |  2 +-
 src/gallium/drivers/etnaviv/etnaviv_texture_state.c | 20 +---
 2 files changed, 10 insertions(+), 12 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index c3ae3fdc138..52518971660 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1453,7 +1453,7 @@
 "description": "etnaviv: simplify linear stride implementation",
 "nominated": true,
 "nomination_type": 1,
-"resolution": 0,
+"resolution": 1,
 "master_sha": null,
 "because_sha": "34458c1cf6caf1718e111096143e74aabc7985a7"
 },
diff --git a/src/gallium/drivers/etnaviv/etnaviv_texture_state.c 
b/src/gallium/drivers/etnaviv/etnaviv_texture_state.c
index 4c11b114ac0..8684275ebd9 100644
--- a/src/gallium/drivers/etnaviv/etnaviv_texture_state.c
+++ b/src/gallium/drivers/etnaviv/etnaviv_texture_state.c
@@ -68,7 +68,7 @@ struct etna_sampler_view {
uint32_t TE_SAMPLER_SIZE;
uint32_t TE_SAMPLER_LOG_SIZE;
uint32_t TE_SAMPLER_ASTC0;
-   uint32_t TE_SAMPLER_LINEAR_STRIDE[VIVS_TE_SAMPLER_LINEAR_STRIDE__LEN];
+   uint32_t TE_SAMPLER_LINEAR_STRIDE;  /* only LOD0 */
struct etna_reloc TE_SAMPLER_LOD_ADDR[VIVS_TE_SAMPLER_LOD_ADDR__LEN];
unsigned min_lod, max_lod; /* 5.5 fixp */
 
@@ -211,12 +211,11 @@ etna_create_sampler_view_state(struct pipe_context *pctx, 
struct pipe_resource *
if (res->layout == ETNA_LAYOUT_LINEAR && 
!util_format_is_compressed(so->format)) {
   sv->TE_SAMPLER_CONFIG0 |= 
VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(TEXTURE_ADDRESSING_MODE_LINEAR);
 
-  for (int lod = 0; lod <= res->base.last_level; ++lod)
- sv->TE_SAMPLER_LINEAR_STRIDE[lod] = res->levels[lod].stride;
-
+  assert(res->base.last_level == 0);
+  sv->TE_SAMPLER_LINEAR_STRIDE = res->levels[0].stride;
} else {
   sv->TE_SAMPLER_CONFIG0 |= 
VIVS_TE_SAMPLER_CONFIG0_ADDRESSING_MODE(TEXTURE_ADDRESSING_MODE_TILED);
-  memset(&sv->TE_SAMPLER_LINEAR_STRIDE, 0, 
sizeof(sv->TE_SAMPLER_LINEAR_STRIDE));
+  sv->TE_SAMPLER_LINEAR_STRIDE = 0;
}
 
sv->TE_SAMPLER_CONFIG1 |= COND(ext, 
VIVS_TE_SAMPLER_CONFIG1_FORMAT_EXT(format)) |
@@ -406,12 +405,11 @@ etna_emit_texture_state(struct etna_context *ctx)
   }
}
if (unlikely(dirty & (ETNA_DIRTY_SAMPLER_VIEWS))) {
-  for (int y = 0; y < VIVS_TE_SAMPLER_LINEAR_STRIDE__LEN; ++y) {
- for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
-if ((1 << x) & active_samplers) {
-   struct etna_sampler_view *sv = 
etna_sampler_view(ctx->sampler_view[x]);
-   /*02C00*/ EMIT_STATE(TE_SAMPLER_LINEAR_STRIDE(x, y), 
sv->TE_SAMPLER_LINEAR_STRIDE[y]);
-}
+  /* only LOD0 is valid for this register */
+  for (int x = 0; x < VIVS_TE_SAMPLER__LEN; ++x) {
+ if ((1 << x) & active_samplers) {
+struct etna_sampler_view *sv = 
etna_sampler_view(ctx->sampler_view[x]);
+/*02C00*/ EMIT_STATE(TE_SAMPLER_LINEAR_STRIDE(0, x), 
sv->TE_SAMPLER_LINEAR_STRIDE);
  }
   }
}

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Mesa (staging/20.2): .pick_status.json: Update to 291cfb1e41513008a5be08be95399373a7de206d

[GitLab Mirror]

Module: Mesa
Branch: staging/20.2
Commit: d82aa3bf603c37082c1b2291e81a8aad0a62a1e1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d82aa3bf603c37082c1b2291e81a8aad0a62a1e1

Author: Dylan Baker 
Date:   Tue Sep 29 08:54:46 2020 -0700

.pick_status.json: Update to 291cfb1e41513008a5be08be95399373a7de206d

---

 .pick_status.json | 1593 +
 1 file changed, 1593 insertions(+)

Diff:   
http://cgit.freedesktop.org/mesa/mesa/diff/?id=d82aa3bf603c37082c1b2291e81a8aad0a62a1e1
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Mesa (staging/20.2): docs: Add sh256 sums for 20.2.0

[GitLab Mirror]

Module: Mesa
Branch: staging/20.2
Commit: 4f8488b857c0d17d64e136af306a010e43681eaf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f8488b857c0d17d64e136af306a010e43681eaf

Author: Dylan Baker 
Date:   Mon Sep 28 16:28:46 2020 -0700

docs: Add sh256 sums for 20.2.0

---

 docs/relnotes/20.2.0.rst   |  2 +-
 docs/relnotes/new_features.txt | 29 -
 2 files changed, 1 insertion(+), 30 deletions(-)

diff --git a/docs/relnotes/20.2.0.rst b/docs/relnotes/20.2.0.rst
index 5eeb128711b..3b210ab58da 100644
--- a/docs/relnotes/20.2.0.rst
+++ b/docs/relnotes/20.2.0.rst
@@ -21,7 +21,7 @@ SHA256 checksum
 
 ::
 
-TBD.
+63f0359575d558ef98dd78adffc0df4c66b76964ebf603b778b7004964191d30  
mesa-20.2.0.tar.xz
 
 
 New features
diff --git a/docs/relnotes/new_features.txt b/docs/relnotes/new_features.txt
deleted file mode 100644
index 2fc8b39f72f..000
--- a/docs/relnotes/new_features.txt
+++ /dev/null
@@ -1,29 +0,0 @@
-GL_ARB_compute_variable_group_size on Iris.
-GL_ARB_gpu_shader5 on llvmpipe
-GL_ARB_post_depth_coverage on llvmpipe
-GL 4.3 on llvmpipe
-GLES 3.2 on llvmpipe
-GL_EXT_shader_group_vote on GLES3.
-GL_EXT_texture_shadow_lod on llvmpipe
-VK_AMD_texture_gather_bias_lod on RADV.
-VK_AMD_gpu_shader_half_float on RADV/ACO.
-VK_AMD_gpu_shader_int16 on RADV/ACO.
-VK_EXT_extended_dynamic_state on ANV and RADV.
-VK_EXT_image_robustness on RADV.
-VK_EXT_private_data on ANV and RADV.
-VK_EXT_custom_border_color on ANV and RADV.
-VK_EXT_pipeline_creation_cache_control on ANV and RADV.
-VK_EXT_shader_demote_to_helper_invocation on RADV/LLVM.
-VK_EXT_subgroup_size_control on RADV/ACO.
-VK_GOOGLE_user_type on ANV and RADV.
-VK_KHR_shader_subgroup_extended_types on RADV/ACO.
-GL_ARB_gl_spirv on nvc0/nir.
-GL_ARB_spirv_extensions on nvc0/nir.
-RADV now uses ACO per default as backend
-RADV_DEBUG=llvm option to enable LLVM backend for RADV
-VK_EXT_image_robustness for ANV
-VK_EXT_shader_atomic_float on ANV
-VK_EXT__formats on ANV and RADV.
-VK_KHR_memory_model on RADV.
-GL 4.5 on llvmpipe
-EGL_KHR_swap_buffers_with_damage on X11 (DRI3)

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Mesa (staging/20.2): nir/cf: Better handle intra-block splits

[GitLab Mirror]

Module: Mesa
Branch: staging/20.2
Commit: a48475971769b320bf4d4ab02677346baa040219
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a48475971769b320bf4d4ab02677346baa040219

Author: Jason Ekstrand 
Date:   Thu Sep 24 23:50:24 2020 -0500

nir/cf: Better handle intra-block splits

In the case where end was a instruction-based cursor, we would mix up
our blocks and end up with block_begin pointing after the second split.
This causes a segfault as the cf_node list walk at the end of the
function never terminates properly.  There's also a possibility of
mix-up if begin is an instruction-based cursor which was found by
inspection.

Fixes: fc7f2d2364a9 "nir/cf: add new control modification API's"
Reviewed-by: Connor Abbott 
Acked-by: Matt Turner 
Part-of: 
(cherry picked from commit 7dbb1f7462433940951ce6c3fa22f6368aeafd50)

---

 .pick_status.json   |  2 +-
 src/compiler/nir/nir_control_flow.c | 31 ---
 2 files changed, 25 insertions(+), 8 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index c8d4d56da55..4d8b5ce3666 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -4,7 +4,7 @@
 "description": "nir/cf: Better handle intra-block splits",
 "nominated": true,
 "nomination_type": 1,
-"resolution": 0,
+"resolution": 1,
 "master_sha": null,
 "because_sha": "fc7f2d2364a98d4ec8fb8627b03c6f84b353998c"
 },
diff --git a/src/compiler/nir/nir_control_flow.c 
b/src/compiler/nir/nir_control_flow.c
index c52d091e848..213d926a389 100644
--- a/src/compiler/nir/nir_control_flow.c
+++ b/src/compiler/nir/nir_control_flow.c
@@ -673,16 +673,33 @@ nir_cf_extract(nir_cf_list *extracted, nir_cursor begin, 
nir_cursor end)
   return;
}
 
-   /* In the case where begin points to an instruction in some basic block and
-* end points to the end of the same basic block, we rely on the fact that
-* splitting on an instruction moves earlier instructions into a new basic
-* block. If the later instructions were moved instead, then the end cursor
-* would be pointing to the same place that begin used to point to, which
-* is obviously not what we want.
-*/
split_block_cursor(begin, &block_before, &block_begin);
+
+   /* Splitting a block twice with two cursors created before either split is
+* tricky and there are a couple of places it can go wrong if both cursors
+* point to the same block.  One is if the second cursor is an block-based
+* cursor and, thanks to the split above, it ends up pointing to the wrong
+* block.  If it's a before_block cursor and it's in the same block as
+* begin, then begin must also be a before_block cursor and it should be
+* caught by the nir_cursors_equal check above and we won't get here.  If
+* it's an after_block cursor, we need to re-adjust to ensure that it
+* points to the second one of the split blocks, regardless of which it is.
+*/
+   if (end.option == nir_cursor_after_block && end.block == block_before)
+  end.block = block_begin;
+
split_block_cursor(end, &block_end, &block_after);
 
+   /* The second place this can all go wrong is that it could be that the
+* second split places the original block after the new block in which case
+* the block_begin pointer that we saved off above is pointing to the block
+* at the end rather than the block in the middle like it's supposed to be.
+* In this case, we have to re-adjust begin_block to point to the middle
+* one.
+*/
+   if (block_begin == block_after)
+  block_begin = block_end;
+
extracted->impl = nir_cf_node_get_function(&block_begin->cf_node);
exec_list_make_empty(&extracted->list);
 

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Mesa (staging/20.2): nir/liveness: Consider if uses in nir_ssa_defs_interfere

[GitLab Mirror]

Module: Mesa
Branch: staging/20.2
Commit: da7f4b5ada922f62e46d4bd9cc07222a228643ff
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=da7f4b5ada922f62e46d4bd9cc07222a228643ff

Author: Jason Ekstrand 
Date:   Tue Sep 22 16:56:42 2020 -0500

nir/liveness: Consider if uses in nir_ssa_defs_interfere

Fixes: f86902e75d9 "nir: Add an SSA-based liveness analysis pass"
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3428
Reviewed-by: Eric Anholt 
Reviewed-by: Yevhenii Kharchenko 
Reviewed-by: Connor Abbott 
Part-of: 
(cherry picked from commit 0206fb39418786e069088c513bf392d564d3d0f9)

---

 .pick_status.json   | 2 +-
 src/compiler/nir/nir_liveness.c | 9 +
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/.pick_status.json b/.pick_status.json
index 78ec2b91f4c..24361ca41d6 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1273,7 +1273,7 @@
 "description": "nir/liveness: Consider if uses in 
nir_ssa_defs_interfere",
 "nominated": true,
 "nomination_type": 1,
-"resolution": 0,
+"resolution": 1,
 "master_sha": null,
 "because_sha": "f86902e75d989b781be36ced5dc98dfc0cd34b7b"
 },
diff --git a/src/compiler/nir/nir_liveness.c b/src/compiler/nir/nir_liveness.c
index 16dbeb4a223..c3c181b3263 100644
--- a/src/compiler/nir/nir_liveness.c
+++ b/src/compiler/nir/nir_liveness.c
@@ -250,6 +250,15 @@ search_for_use_after_instr(nir_instr *start, nir_ssa_def 
*def)
  return true;
   node = node->next;
}
+
+   /* If uses are considered to be in the block immediately preceding the if
+* so we need to also check the following if condition, if any.
+*/
+   nir_if *following_if = nir_block_get_following_if(start->block);
+   if (following_if && following_if->condition.is_ssa &&
+   following_if->condition.ssa == def)
+  return true;
+
return false;
 }
 

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Mesa (staging/20.2): gallium/vl: add chroma_format arg to vl_video_buffer functions

[GitLab Mirror]

Module: Mesa
Branch: staging/20.2
Commit: e2f99a7ab73ba9b0e2a5c3db7d8323c70a4e3e75
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2f99a7ab73ba9b0e2a5c3db7d8323c70a4e3e75

Author: Pierre-Eric Pelloux-Prayer 
Date:   Tue Sep 22 14:32:13 2020 +0200

gallium/vl: add chroma_format arg to vl_video_buffer functions

vl_mpeg12_decoder needs to override the chroma_format value to get the
correct size calculated (chroma_format is used by vl_video_buffer_adjust_size).

I'm not sure why it's needed, but this is needed to get correct mpeg decode.

Fixes: 24f2b0a8560 ("gallium/video: remove pipe_video_buffer.chroma_format")
Acked-by: Leo Liu 
Part-of: 
(cherry picked from commit 2584d48b2cf13ea50b4e6177f32bacf0c7027e79)

---

 .pick_status.json|  2 +-
 src/gallium/auxiliary/vl/vl_mpeg12_decoder.c | 13 +++--
 src/gallium/auxiliary/vl/vl_stubs.c  |  3 ++-
 src/gallium/auxiliary/vl/vl_video_buffer.c   | 20 +---
 src/gallium/auxiliary/vl/vl_video_buffer.h   |  6 --
 src/gallium/drivers/r600/r600_uvd.c  | 11 ---
 6 files changed, 35 insertions(+), 20 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 5416e6da36d..c8d4d56da55 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -724,7 +724,7 @@
 "description": "gallium/vl: add chroma_format arg to vl_video_buffer 
functions",
 "nominated": true,
 "nomination_type": 1,
-"resolution": 0,
+"resolution": 1,
 "master_sha": null,
 "because_sha": "24f2b0a8560f34745854bf8263fa7c2d0f95f2bc"
 },
diff --git a/src/gallium/auxiliary/vl/vl_mpeg12_decoder.c 
b/src/gallium/auxiliary/vl/vl_mpeg12_decoder.c
index c522498c3e7..d64f2cba143 100644
--- a/src/gallium/auxiliary/vl/vl_mpeg12_decoder.c
+++ b/src/gallium/auxiliary/vl/vl_mpeg12_decoder.c
@@ -983,28 +983,28 @@ init_idct(struct vl_mpeg12_decoder *dec, const struct 
format_config* format_conf
   nr_of_idct_render_targets = 1;
 
formats[0] = formats[1] = formats[2] = format_config->idct_source_format;
-   assert(pipe_format_to_chroma_format(formats[0]) == dec->base.chroma_format);
memset(&templat, 0, sizeof(templat));
templat.width = dec->base.width / 4;
templat.height = dec->base.height;
dec->idct_source = vl_video_buffer_create_ex
(
   dec->context, &templat,
-  formats, 1, 1, PIPE_USAGE_DEFAULT
+  formats, 1, 1, PIPE_USAGE_DEFAULT,
+  PIPE_VIDEO_CHROMA_FORMAT_420
);
 
if (!dec->idct_source)
   goto error_idct_source;
 
formats[0] = formats[1] = formats[2] = format_config->mc_source_format;
-   assert(pipe_format_to_chroma_format(formats[0]) == dec->base.chroma_format);
memset(&templat, 0, sizeof(templat));
templat.width = dec->base.width / nr_of_idct_render_targets;
templat.height = dec->base.height / 4;
dec->mc_source = vl_video_buffer_create_ex
(
   dec->context, &templat,
-  formats, nr_of_idct_render_targets, 1, PIPE_USAGE_DEFAULT
+  formats, nr_of_idct_render_targets, 1, PIPE_USAGE_DEFAULT,
+  PIPE_VIDEO_CHROMA_FORMAT_420
);
 
if (!dec->mc_source)
@@ -1055,9 +1055,10 @@ init_mc_source_widthout_idct(struct vl_mpeg12_decoder 
*dec, const struct format_
dec->mc_source = vl_video_buffer_create_ex
(
   dec->context, &templat,
-  formats, 1, 1, PIPE_USAGE_DEFAULT
+  formats, 1, 1, PIPE_USAGE_DEFAULT,
+  PIPE_VIDEO_CHROMA_FORMAT_420
);
-  
+
return dec->mc_source != NULL;
 }
 
diff --git a/src/gallium/auxiliary/vl/vl_stubs.c 
b/src/gallium/auxiliary/vl/vl_stubs.c
index befd2468f49..02568ac2843 100644
--- a/src/gallium/auxiliary/vl/vl_stubs.c
+++ b/src/gallium/auxiliary/vl/vl_stubs.c
@@ -85,7 +85,8 @@ vl_video_buffer_template(struct pipe_resource *templ,
  const struct pipe_video_buffer *tmpl,
  enum pipe_format resource_format,
  unsigned depth, unsigned array_size,
- unsigned usage, unsigned plane)
+ unsigned usage, unsigned plane,
+ enum pipe_video_chroma_format chroma_format)
 {
assert(0);
 }
diff --git a/src/gallium/auxiliary/vl/vl_video_buffer.c 
b/src/gallium/auxiliary/vl/vl_video_buffer.c
index f4fac6ca0bc..54cc0c52909 100644
--- a/src/gallium/auxiliary/vl/vl_video_buffer.c
+++ b/src/gallium/auxiliary/vl/vl_video_buffer.c
@@ -169,7 +169,8 @@ vl_video_buffer_template(struct pipe_resource *templ,
  const struct pipe_video_buffer *tmpl,
  enum pipe_format resource_format,
  unsigned depth, unsigned array_size,
- unsigned usage, unsigned plane)
+ unsigned usage, unsigned plane,
+ enum pipe_video_chroma_format chroma_format)
 {
unsigned height = tmpl->height;
 
@@ -188,7 +1

Mesa (staging/20.2): gallium/dri2: Move image->texture assignment after image NULL check.

[GitLab Mirror]

Module: Mesa
Branch: staging/20.2
Commit: 28cff4722da78a41f4b972acd9c437b546713c91
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=28cff4722da78a41f4b972acd9c437b546713c91

Author: Vinson Lee 
Date:   Mon Sep 21 18:20:25 2020 -0700

gallium/dri2: Move image->texture assignment after image NULL check.

Fix defect reported by Coverity Scan.

Dereference before null check (REVERSE_INULL)
check_after_deref: Null-checking image suggests that it may be
null, but it has already been dereferenced on all paths leading to
the check.

Fixes: ad609bf55a87 ("frontend/dri: Implement mapping individual planes.")
Signed-off-by: Vinson Lee 
Reviewed-by: Tapani Pälli 
Part-of: 
(cherry picked from commit 03e7b75c22c0b3b55820be982ff9d98d704f3260)

---

 .pick_status.json| 2 +-
 src/gallium/frontends/dri/dri2.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index cc51ee37c1b..478fbbd2eaf 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -2335,7 +2335,7 @@
 "description": "gallium/dri2: Move image->texture assignment after 
image NULL check.",
 "nominated": true,
 "nomination_type": 1,
-"resolution": 0,
+"resolution": 1,
 "master_sha": null,
 "because_sha": "ad609bf55a87200ab11ad7cf31420dcfd8dfc141"
 },
diff --git a/src/gallium/frontends/dri/dri2.c b/src/gallium/frontends/dri/dri2.c
index da2a28725e8..8eff860015d 100644
--- a/src/gallium/frontends/dri/dri2.c
+++ b/src/gallium/frontends/dri/dri2.c
@@ -1533,7 +1533,6 @@ dri2_map_image(__DRIcontext *context, __DRIimage *image,
struct dri_context *ctx = dri_context(context);
struct pipe_context *pipe = ctx->st->pipe;
enum pipe_transfer_usage pipe_access = 0;
-   struct pipe_resource *resource = image->texture;
struct pipe_transfer *trans;
void *map;
 
@@ -1544,6 +1543,7 @@ dri2_map_image(__DRIcontext *context, __DRIimage *image,
if (plane >= dri2_get_mapping_by_format(image->dri_format)->nplanes)
   return NULL;
 
+   struct pipe_resource *resource = image->texture;
while (plane--)
   resource = resource->next;
 

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Mesa (staging/20.2): .pick_status.json: Update to 7dbb1f7462433940951ce6c3fa22f6368aeafd50

[GitLab Mirror]

Module: Mesa
Branch: staging/20.2
Commit: a0238684de1d47faba5532c3c92b604af22a3b3d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0238684de1d47faba5532c3c92b604af22a3b3d

Author: Dylan Baker 
Date:   Wed Sep 30 09:26:48 2020 -0700

.pick_status.json: Update to 7dbb1f7462433940951ce6c3fa22f6368aeafd50

---

 .pick_status.json | 792 ++
 1 file changed, 792 insertions(+)

diff --git a/.pick_status.json b/.pick_status.json
index d893e0a590c..cc51ee37c1b 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1,4 +1,796 @@
 [
+{
+"sha": "7dbb1f7462433940951ce6c3fa22f6368aeafd50",
+"description": "nir/cf: Better handle intra-block splits",
+"nominated": true,
+"nomination_type": 1,
+"resolution": 0,
+"master_sha": null,
+"because_sha": "fc7f2d2364a98d4ec8fb8627b03c6f84b353998c"
+},
+{
+"sha": "5e2e882270cfb174513bcc9a1e717077a8f39130",
+"description": "nir: Disallow goto and goto_if in clone and 
[de]serialize",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "9a48ed84ecd166d57fb8018401eb5491d8f80bb1",
+"description": "nir/copy_propagate: Copy-prop into jump conditions",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "7f0cd6f1539ff4a98d1d084116834073f20c515d",
+"description": "nir/opt_if: Use early returns in opt_if_merge()",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "656e428ff4e027d134027df73a0fe13e587011a8",
+"description": "nir/opt_if: Remove open-coded 
nir_ssa_def_rewrite_uses()",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "c6f871b62e21343263a7a4c1fd945269e87fd7ee",
+"description": "nir/lower_returns: Use nir control flow insertion 
helpers",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "f103bded0b5b7f1860a1d0be92d19bb248d29fd4",
+"description": "ttn: Use nir control flow insertion helpers",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "f504eb683d8596326015d18b6fcdfccc8a4ad32e",
+"description": "radv: Use nir control flow insertion helpers",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "b2ede6280c0a6030efb0bf2005b018dbacfbf4f1",
+"description": "intel/nir: Use nir control flow helpers",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "55e2b3424decf9f0240bb6fe0fd521e775d28d66",
+"description": "radeonsi: Fix imports with displayable DCC.",
+"nominated": false,
+"nomination_type": 1,
+"resolution": 4,
+"master_sha": null,
+"because_sha": "c6c1fa9a2638800155b31701190af7baccb0c18f"
+},
+{
+"sha": "636f770233543c00c319895201498c57eece6774",
+"description": "bin/gen_release_notes.py: escape special rST 
characters",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "ae7975ecd43d769a31debb6190586bd2437a6f63",
+"description": "docs: cpu -> CPU",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "5fe6124661db8e89c437ef1cd4e947c1275c046a",
+"description": "docs: Sandybridge -> Sandy Bridge",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "302fc31847354550cfaba4141cb64b0df3b66e9c",
+"description": "docs: vmware -> VMWare",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": null,
+"because_sha": null
+},
+{
+"sha": "37bb6ddcc25a67327e8759901930bccb5b495c67",
+"description": "docs: ubuntu -> Ubuntu",
+"nominated": false,
+"nomination_type": null,
+"resolution": 4,
+"master_sha": n

Mesa (staging/20.2): docs: add release notes for 20.2.0

[GitLab Mirror]

Module: Mesa
Branch: staging/20.2
Commit: 0ab255b82dafaa2a4126a084dda76db3d46d1fc8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ab255b82dafaa2a4126a084dda76db3d46d1fc8

Author: Dylan Baker 
Date:   Mon Sep 28 16:27:44 2020 -0700

docs: add release notes for 20.2.0

---

 docs/relnotes/20.2.0.rst | 4752 ++
 1 file changed, 4752 insertions(+)

Diff:   
http://cgit.freedesktop.org/mesa/mesa/diff/?id=0ab255b82dafaa2a4126a084dda76db3d46d1fc8
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Mesa (staging/20.2): meson/anv: Use variable that checks for --build-id

[GitLab Mirror]

Module: Mesa
Branch: staging/20.2
Commit: 0c9b64f9f4bfba79f1a56fbf6b902caac197d766
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c9b64f9f4bfba79f1a56fbf6b902caac197d766

Author: Dylan Baker 
Date:   Tue Sep 22 09:02:46 2020 -0700

meson/anv: Use variable that checks for --build-id

fixes: d1992255bb29054fa51763376d125183a9f602f3
   ("meson: Add build Intel "anv" vulkan driver")

Acked-by: Jason Ekstrand 
Part-of: 
(cherry picked from commit 465460943a2bf049e83a602d70f921775245dbca)

---

 .pick_status.json| 2 +-
 src/intel/vulkan/meson.build | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 2662029a33b..d68fbf92e85 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1048,7 +1048,7 @@
 "description": "meson/anv: Use variable that checks for --build-id",
 "nominated": true,
 "nomination_type": 1,
-"resolution": 0,
+"resolution": 1,
 "master_sha": null,
 "because_sha": "d1992255bb29054fa51763376d125183a9f602f3"
 },
diff --git a/src/intel/vulkan/meson.build b/src/intel/vulkan/meson.build
index 2d37fa0eb5e..844d08b4fd1 100644
--- a/src/intel/vulkan/meson.build
+++ b/src/intel/vulkan/meson.build
@@ -204,7 +204,7 @@ libvulkan_intel = shared_library(
   ],
   c_args : anv_flags,
   gnu_symbol_visibility : 'hidden',
-  link_args : ['-Wl,--build-id=sha1', ld_args_bsymbolic, ld_args_gc_sections],
+  link_args : [ld_args_build_id, ld_args_bsymbolic, ld_args_gc_sections],
   install : true,
 )
 

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Mesa (staging/20.2): blorp: Ensure aligned HIZ_CCS_WT partial clears

[GitLab Mirror]

Module: Mesa
Branch: staging/20.2
Commit: e2ee71614f20201eab2f18a64e2bee3630a81c99
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2ee71614f20201eab2f18a64e2bee3630a81c99

Author: Nanley Chery 
Date:   Thu Sep 24 10:01:11 2020 -0700

blorp: Ensure aligned HIZ_CCS_WT partial clears

Fixes: 5425fcf2cb3 ("intel/blorp: Satisfy HIZ_CCS fast-clear alignments")
Reported-by: Sagar Ghuge 
Tested-by: Ivan Briano 
Reviewed-by: Jason Ekstrand 
Part-of: 
(cherry picked from commit 7f3e881c6cd179a9a541a673f0fc67ef63e50cea)

---

 .pick_status.json | 2 +-
 src/intel/blorp/blorp_clear.c | 9 +
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 24361ca41d6..2662029a33b 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -1246,7 +1246,7 @@
 "description": "blorp: Ensure aligned HIZ_CCS_WT partial clears",
 "nominated": true,
 "nomination_type": 1,
-"resolution": 0,
+"resolution": 1,
 "master_sha": null,
 "because_sha": "5425fcf2cb39dc9df56593d4460b56688506c0cc"
 },
diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c
index 7c7796d0b12..202d3839f73 100644
--- a/src/intel/blorp/blorp_clear.c
+++ b/src/intel/blorp/blorp_clear.c
@@ -834,11 +834,12 @@ blorp_can_hiz_clear_depth(const struct gen_device_info 
*devinfo,
   const bool unaligned = (slice_x0 + x0) % 16 || (slice_y0 + y0) % 8 ||
  (max_x1_y1 ? haligned_x1 % 16 || valigned_y1 % 8 :
   x1 % 16 || y1 % 8);
-  const bool alignment_used = surf->levels > 1 ||
-  surf->logical_level0_px.depth > 1 ||
-  surf->logical_level0_px.array_len > 1;
+  const bool partial_clear = x0 > 0 || y0 > 0 || !max_x1_y1;
+  const bool multislice_surf = surf->levels > 1 ||
+   surf->logical_level0_px.depth > 1 ||
+   surf->logical_level0_px.array_len > 1;
 
-  if (unaligned && alignment_used)
+  if (unaligned && (partial_clear || multislice_surf))
  return false;
}
 

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Mesa (master): nir/lower_returns: Use nir control flow insertion helpers

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: c6f871b62e21343263a7a4c1fd945269e87fd7ee
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c6f871b62e21343263a7a4c1fd945269e87fd7ee

Author: Connor Abbott 
Date:   Wed Apr 10 11:34:57 2019 +0200

nir/lower_returns: Use nir control flow insertion helpers

Reviewed-by: Jason Ekstrand 
Reviewed-by: Matt Turner 
Part-of: 

---

 src/compiler/nir/nir_lower_returns.c | 10 --
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/src/compiler/nir/nir_lower_returns.c 
b/src/compiler/nir/nir_lower_returns.c
index 56c7656aeaf..ae933e662cd 100644
--- a/src/compiler/nir/nir_lower_returns.c
+++ b/src/compiler/nir/nir_lower_returns.c
@@ -55,17 +55,13 @@ predicate_following(nir_cf_node *node, struct 
lower_returns_state *state)
 
assert(state->return_flag);
 
-   nir_if *if_stmt = nir_if_create(b->shader);
-   if_stmt->condition = nir_src_for_ssa(nir_load_var(b, state->return_flag));
-   nir_cf_node_insert(b->cursor, &if_stmt->cf_node);
+   nir_if *if_stmt = nir_push_if(b, nir_load_var(b, state->return_flag));
 
if (state->loop) {
   /* If we're inside of a loop, then all we need to do is insert a
* conditional break.
*/
-  nir_jump_instr *brk =
- nir_jump_instr_create(state->builder.shader, nir_jump_break);
-  nir_instr_insert(nir_before_cf_list(&if_stmt->then_list), &brk->instr);
+  nir_jump(b, nir_jump_break);
} else {
   /* Otherwise, we need to actually move everything into the else case
* of the if statement.
@@ -76,6 +72,8 @@ predicate_following(nir_cf_node *node, struct 
lower_returns_state *state)
   assert(!exec_list_is_empty(&list.list));
   nir_cf_reinsert(&list, nir_before_cf_list(&if_stmt->else_list));
}
+
+   nir_pop_if(b, NULL);
 }
 
 static bool

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Mesa (master): nir/opt_if: Remove open-coded nir_ssa_def_rewrite_uses()

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 656e428ff4e027d134027df73a0fe13e587011a8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=656e428ff4e027d134027df73a0fe13e587011a8

Author: Connor Abbott 
Date:   Tue Apr 16 19:31:45 2019 +0200

nir/opt_if: Remove open-coded nir_ssa_def_rewrite_uses()

So that we don't have to change these two places later.

Reviewed-by: Jason Ekstrand 
Reviewed-by: Matt Turner 
Part-of: 

---

 src/compiler/nir/nir_opt_if.c | 20 ++--
 1 file changed, 2 insertions(+), 18 deletions(-)

diff --git a/src/compiler/nir/nir_opt_if.c b/src/compiler/nir/nir_opt_if.c
index e4083a465cb..d507ceef275 100644
--- a/src/compiler/nir/nir_opt_if.c
+++ b/src/compiler/nir/nir_opt_if.c
@@ -493,16 +493,8 @@ opt_split_alu_of_phi(nir_builder *b, nir_loop *loop)
  /* Modify all readers of the original ALU instruction to read the
   * result of the phi.
   */
- nir_foreach_use_safe(use_src, &alu->dest.dest.ssa) {
-nir_instr_rewrite_src(use_src->parent_instr,
-  use_src,
+ nir_ssa_def_rewrite_uses(&alu->dest.dest.ssa,
   nir_src_for_ssa(&phi->dest.ssa));
- }
-
- nir_foreach_if_use_safe(use_src, &alu->dest.dest.ssa) {
-nir_if_rewrite_condition(use_src->parent_if,
- nir_src_for_ssa(&phi->dest.ssa));
- }
 
  /* Since the original ALU instruction no longer has any readers, just
   * remove it.
@@ -713,16 +705,8 @@ opt_simplify_bcsel_of_phi(nir_builder *b, nir_loop *loop)
   /* Modify all readers of the bcsel instruction to read the result of
* the phi.
*/
-  nir_foreach_use_safe(use_src, &bcsel->dest.dest.ssa) {
- nir_instr_rewrite_src(use_src->parent_instr,
-   use_src,
+  nir_ssa_def_rewrite_uses(&bcsel->dest.dest.ssa,
nir_src_for_ssa(&phi->dest.ssa));
-  }
-
-  nir_foreach_if_use_safe(use_src, &bcsel->dest.dest.ssa) {
- nir_if_rewrite_condition(use_src->parent_if,
-  nir_src_for_ssa(&phi->dest.ssa));
-  }
 
   /* Since the original bcsel instruction no longer has any readers,
* just remove it.

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Mesa (master): ttn: Use nir control flow insertion helpers

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: f103bded0b5b7f1860a1d0be92d19bb248d29fd4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f103bded0b5b7f1860a1d0be92d19bb248d29fd4

Author: Connor Abbott 
Date:   Tue Apr  9 22:31:50 2019 +0200

ttn: Use nir control flow insertion helpers

As a side effect, we can delete the whole control flow stack thing.

v2 (Jason Ekstrand):
 - Drop the ttn_if helper and just inline it in the two uses

Reviewed-by: Jason Ekstrand 
Reviewed-by: Eric Anholt 
Reviewed-by: Matt Turner 
Part-of: 

---

 src/gallium/auxiliary/nir/tgsi_to_nir.c | 123 +++-
 1 file changed, 8 insertions(+), 115 deletions(-)

diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c 
b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index 8f07b4babe8..4f9705fc95b 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -85,27 +85,6 @@ struct ttn_compile {
nir_variable *input_var_position;
nir_variable *input_var_point;
 
-   /**
-* Stack of nir_cursors where instructions should be pushed as we pop
-* back out of the control flow stack.
-*
-* For each IF/ELSE/ENDIF block, if_stack[if_stack_pos] has where the else
-* instructions should be placed, and if_stack[if_stack_pos - 1] has where
-* the next instructions outside of the if/then/else block go.
-*/
-   nir_cursor *if_stack;
-   unsigned if_stack_pos;
-
-   /**
-* Stack of nir_cursors where instructions should be pushed as we pop
-* back out of the control flow stack.
-*
-* loop_stack[loop_stack_pos - 1] contains the cf_node_list for the outside
-* of the loop.
-*/
-   nir_cursor *loop_stack;
-   unsigned loop_stack_pos;
-
/* How many TGSI_FILE_IMMEDIATE vec4s have been parsed so far. */
unsigned next_imm;
 
@@ -1160,85 +1139,6 @@ ttn_kill_if(nir_builder *b, nir_op op, nir_alu_dest 
dest, nir_ssa_def **src)
b->shader->info.fs.uses_discard = true;
 }
 
-static void
-ttn_if(struct ttn_compile *c, nir_ssa_def *src, bool is_uint)
-{
-   nir_builder *b = &c->build;
-   nir_ssa_def *src_x = ttn_channel(b, src, X);
-
-   nir_if *if_stmt = nir_if_create(b->shader);
-   if (is_uint) {
-  /* equivalent to TGSI UIF, src is interpreted as integer */
-  if_stmt->condition = nir_src_for_ssa(nir_ine(b, src_x, nir_imm_int(b, 
0)));
-   } else {
-  /* equivalent to TGSI IF, src is interpreted as float */
-  if_stmt->condition = nir_src_for_ssa(nir_fneu(b, src_x, nir_imm_float(b, 
0.0)));
-   }
-   nir_builder_cf_insert(b, &if_stmt->cf_node);
-
-   c->if_stack[c->if_stack_pos] = nir_after_cf_node(&if_stmt->cf_node);
-   c->if_stack_pos++;
-
-   b->cursor = nir_after_cf_list(&if_stmt->then_list);
-
-   c->if_stack[c->if_stack_pos] = nir_after_cf_list(&if_stmt->else_list);
-   c->if_stack_pos++;
-}
-
-static void
-ttn_else(struct ttn_compile *c)
-{
-   nir_builder *b = &c->build;
-
-   b->cursor = c->if_stack[c->if_stack_pos - 1];
-}
-
-static void
-ttn_endif(struct ttn_compile *c)
-{
-   nir_builder *b = &c->build;
-
-   c->if_stack_pos -= 2;
-   b->cursor = c->if_stack[c->if_stack_pos];
-}
-
-static void
-ttn_bgnloop(struct ttn_compile *c)
-{
-   nir_builder *b = &c->build;
-
-   nir_loop *loop = nir_loop_create(b->shader);
-   nir_builder_cf_insert(b, &loop->cf_node);
-
-   c->loop_stack[c->loop_stack_pos] = nir_after_cf_node(&loop->cf_node);
-   c->loop_stack_pos++;
-
-   b->cursor = nir_after_cf_list(&loop->body);
-}
-
-static void
-ttn_cont(nir_builder *b)
-{
-   nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_continue);
-   nir_builder_instr_insert(b, &instr->instr);
-}
-
-static void
-ttn_brk(nir_builder *b)
-{
-   nir_jump_instr *instr = nir_jump_instr_create(b->shader, nir_jump_break);
-   nir_builder_instr_insert(b, &instr->instr);
-}
-
-static void
-ttn_endloop(struct ttn_compile *c)
-{
-   nir_builder *b = &c->build;
-
-   c->loop_stack_pos--;
-   b->cursor = c->loop_stack[c->loop_stack_pos];
-}
-
 static void
 get_texture_info(unsigned texture,
  enum glsl_sampler_dim *dim,
@@ -,35 +2122,35 @@ ttn_emit_instruction(struct ttn_compile *c)
   break;
 
case TGSI_OPCODE_IF:
-  ttn_if(c, src[0], false);
+  nir_push_if(b, nir_fneu(b, src[0], nir_imm_float(b, 0.0)));
   break;
 
case TGSI_OPCODE_UIF:
-  ttn_if(c, src[0], true);
+  nir_push_if(b, nir_ine(b, src[0], nir_imm_int(b, 0)));
   break;
 
case TGSI_OPCODE_ELSE:
-  ttn_else(c);
+  nir_push_else(&c->build, NULL);
   break;
 
case TGSI_OPCODE_ENDIF:
-  ttn_endif(c);
+  nir_pop_if(&c->build, NULL);
   break;
 
case TGSI_OPCODE_BGNLOOP:
-  ttn_bgnloop(c);
+  nir_push_loop(&c->build);
   break;
 
case TGSI_OPCODE_BRK:
-  ttn_brk(b);
+  nir_jump(b, nir_jump_break);
   break;
 
case TGSI_OPCODE_CONT:
-  ttn_cont(b);
+  nir_jump(b, nir_jump_continue);
   b

Mesa (master): nir/opt_if: Use early returns in opt_if_merge()

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 7f0cd6f1539ff4a98d1d084116834073f20c515d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f0cd6f1539ff4a98d1d084116834073f20c515d

Author: Connor Abbott 
Date:   Tue Apr 16 19:39:11 2019 +0200

nir/opt_if: Use early returns in opt_if_merge()

We would've had to add yet another level of indentation, or duplicated
finding the if conditions in the next commit. Refactor this function to
use early returns like our other optimizations, so that this isn't an
issue.

Reviewed-by: Jason Ekstrand 
Reviewed-by: Matt Turner 
Part-of: 

---

 src/compiler/nir/nir_opt_if.c | 119 +-
 1 file changed, 59 insertions(+), 60 deletions(-)

diff --git a/src/compiler/nir/nir_opt_if.c b/src/compiler/nir/nir_opt_if.c
index d507ceef275..4283d445912 100644
--- a/src/compiler/nir/nir_opt_if.c
+++ b/src/compiler/nir/nir_opt_if.c
@@ -1230,77 +1230,76 @@ opt_if_merge(nir_if *nif)
bool progress = false;
 
nir_block *next_blk = nir_cf_node_cf_tree_next(&nif->cf_node);
-   if (next_blk && nif->condition.is_ssa) {
-  nir_if *next_if = nir_block_get_following_if(next_blk);
-  if (next_if && next_if->condition.is_ssa) {
-
- /* Here we merge two consecutive ifs that have the same
-  * condition e.g:
-  *
-  *   if ssa_12 {
-  *  ...
-  *   } else {
-  *  ...
-  *   }
-  *   if ssa_12 {
-  *  ...
-  *   } else {
-  *  ...
-  *   }
-  *
-  * Note: This only merges if-statements when the block between them
-  * is empty. The reason we don't try to merge ifs that just have phis
-  * between them is because this can results in increased register
-  * pressure. For example when merging if ladders created by indirect
-  * indexing.
-  */
- if (nif->condition.ssa == next_if->condition.ssa &&
- exec_list_is_empty(&next_blk->instr_list)) {
+   if (!next_blk || !nif->condition.is_ssa)
+  return false;
 
-/* This optimization isn't made to work in this case and
- * opt_if_evaluate_condition_use will optimize it later.
- */
-if (nir_block_ends_in_jump(nir_if_last_then_block(nif)) ||
-nir_block_ends_in_jump(nir_if_last_else_block(nif)))
-   return false;
+   nir_if *next_if = nir_block_get_following_if(next_blk);
+   if (!next_if || !next_if->condition.is_ssa)
+  return false;
 
-simple_merge_if(nif, next_if, true, true);
-simple_merge_if(nif, next_if, false, false);
+   /* Here we merge two consecutive ifs that have the same condition e.g:
+*
+*   if ssa_12 {
+*  ...
+*   } else {
+*  ...
+*   }
+*   if ssa_12 {
+*  ...
+*   } else {
+*  ...
+*   }
+*
+* Note: This only merges if-statements when the block between them is
+* empty. The reason we don't try to merge ifs that just have phis between
+* them is because this can result in increased register pressure. For
+* example when merging if ladders created by indirect indexing.
+*/
+   if (nif->condition.ssa == next_if->condition.ssa &&
+   exec_list_is_empty(&next_blk->instr_list)) {
 
-nir_block *new_then_block = nir_if_last_then_block(nif);
-nir_block *new_else_block = nir_if_last_else_block(nif);
+  /* This optimization isn't made to work in this case and
+   * opt_if_evaluate_condition_use will optimize it later.
+   */
+  if (nir_block_ends_in_jump(nir_if_last_then_block(nif)) ||
+  nir_block_ends_in_jump(nir_if_last_else_block(nif)))
+ return false;
 
-nir_block *old_then_block = nir_if_last_then_block(next_if);
-nir_block *old_else_block = nir_if_last_else_block(next_if);
+  simple_merge_if(nif, next_if, true, true);
+  simple_merge_if(nif, next_if, false, false);
 
-/* Rewrite the predecessor block for any phis following the second
- * if-statement.
- */
-rewrite_phi_predecessor_blocks(next_if, old_then_block,
-   old_else_block,
-   new_then_block,
-   new_else_block);
+  nir_block *new_then_block = nir_if_last_then_block(nif);
+  nir_block *new_else_block = nir_if_last_else_block(nif);
 
-/* Move phis after merged if to avoid them being deleted when we
- * remove the merged if-statement.
- */
-nir_block *after_next_if_block =
-   nir_cf_node_as_block(nir_cf_node_next(&next_if->cf_node));
+  nir_block *old_then_block = nir_if_last_then_block(next_if);
+  nir_block *old_else_block = nir_if_last_else_block(next_if);
 
-  

Mesa (master): radv: Use nir control flow insertion helpers

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: f504eb683d8596326015d18b6fcdfccc8a4ad32e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f504eb683d8596326015d18b6fcdfccc8a4ad32e

Author: Connor Abbott 
Date:   Tue Apr  9 22:31:06 2019 +0200

radv: Use nir control flow insertion helpers

v2 (Jason Ekstrand):
 - Rebased and tweaked a few cases
 - Use the helpers in build_timestamp_query_shader

Reviewed-by: Matt Turner 
Part-of: 

---

 src/amd/vulkan/radv_meta.c  |  16 ++--
 src/amd/vulkan/radv_query.c | 186 ++--
 2 files changed, 63 insertions(+), 139 deletions(-)

diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index a8e1f7aeb20..589895f5bcb 100644
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -584,7 +584,7 @@ void radv_meta_build_resolve_shader_core(nir_builder *b,
 {
/* do a txf_ms on each sample */
nir_ssa_def *tmp;
-   nir_if *outer_if = NULL;
+   bool inserted_if = false;
 
nir_ssa_def *input_img_deref = &nir_build_deref_var(b, 
input_img)->dest.ssa;
 
@@ -622,11 +622,7 @@ void radv_meta_build_resolve_shader_core(nir_builder *b,
nir_builder_instr_insert(b, &tex_all_same->instr);
 
nir_ssa_def *all_same = nir_ieq(b, &tex_all_same->dest.ssa, 
nir_imm_int(b, 0));
-   nir_if *if_stmt = nir_if_create(b->shader);
-   if_stmt->condition = nir_src_for_ssa(all_same);
-   nir_cf_node_insert(b->cursor, &if_stmt->cf_node);
-
-   b->cursor = nir_after_cf_list(&if_stmt->then_list);
+   nir_push_if(b, all_same);
for (int i = 1; i < samples; i++) {
nir_tex_instr *tex_add = 
nir_tex_instr_create(b->shader, 3);
tex_add->sampler_dim = GLSL_SAMPLER_DIM_MS;
@@ -649,13 +645,13 @@ void radv_meta_build_resolve_shader_core(nir_builder *b,
 
tmp = nir_fdiv(b, tmp, nir_imm_float(b, samples));
nir_store_var(b, color, tmp, 0xf);
-   b->cursor = nir_after_cf_list(&if_stmt->else_list);
-   outer_if = if_stmt;
+   nir_push_else(b, NULL);
+   inserted_if = true;
}
nir_store_var(b, color, &tex->dest.ssa, 0xf);
 
-   if (outer_if)
-   b->cursor = nir_after_cf_node(&outer_if->cf_node);
+   if (inserted_if)
+   nir_pop_if(b, NULL);
 }
 
 nir_ssa_def *
diff --git a/src/amd/vulkan/radv_query.c b/src/amd/vulkan/radv_query.c
index f7d6633d412..10c7022857b 100644
--- a/src/amd/vulkan/radv_query.c
+++ b/src/amd/vulkan/radv_query.c
@@ -57,16 +57,10 @@ static void radv_break_on_count(nir_builder *b, 
nir_variable *var, nir_ssa_def *
 {
nir_ssa_def *counter = nir_load_var(b, var);
 
-   nir_if *if_stmt = nir_if_create(b->shader);
-   if_stmt->condition = nir_src_for_ssa(nir_uge(b, counter, count));
-   nir_cf_node_insert(b->cursor, &if_stmt->cf_node);
+   nir_push_if(b, nir_uge(b, counter, count));
+   nir_jump(b, nir_jump_break);
+   nir_pop_if(b, NULL);
 
-   b->cursor = nir_after_cf_list(&if_stmt->then_list);
-
-   nir_jump_instr *instr = nir_jump_instr_create(b->shader, 
nir_jump_break);
-   nir_builder_instr_insert(b, &instr->instr);
-
-   b->cursor = nir_after_cf_node(&if_stmt->cf_node);
counter = nir_iadd(b, counter, nir_imm_int(b, 1));
nir_store_var(b, var, counter, 0x1);
 }
@@ -88,18 +82,9 @@ static void
 radv_store_availability(nir_builder *b, nir_ssa_def *flags, nir_ssa_def 
*dst_buf,
 nir_ssa_def *offset, nir_ssa_def *value32)
 {
-   nir_ssa_def *result_is_64bit = nir_test_flag(b, flags, 
VK_QUERY_RESULT_64_BIT);
-   nir_if *availability_if = nir_if_create(b->shader);
-   availability_if->condition = nir_src_for_ssa(nir_test_flag(b, flags, 
VK_QUERY_RESULT_WITH_AVAILABILITY_BIT));
-   nir_cf_node_insert(b->cursor, &availability_if->cf_node);
-
-   b->cursor = nir_after_cf_list(&availability_if->then_list);
+   nir_push_if(b, nir_test_flag(b, flags, 
VK_QUERY_RESULT_WITH_AVAILABILITY_BIT));
 
-   nir_if *store_64bit_if = nir_if_create(b->shader);
-   store_64bit_if->condition = nir_src_for_ssa(result_is_64bit);
-   nir_cf_node_insert(b->cursor, &store_64bit_if->cf_node);
-
-   b->cursor = nir_after_cf_list(&store_64bit_if->then_list);
+   nir_push_if(b, nir_test_flag(b, flags, VK_QUERY_RESULT_64_BIT));
 
nir_intrinsic_instr *store = nir_intrinsic_instr_create(b->shader, 
nir_intrinsic_store_ssbo);
store->src[0] = nir_src_for_ssa(nir_vec2(b, value32, nir_imm_int(b, 
0)));
@@ -110,7 +95,7 @@ radv_store_availability(nir_builder *b, nir_ssa_def *flags, 
nir_ssa_def *dst_buf
store->num_components = 2;
nir_builder_instr_insert(b, &store->instr);
 
-   b->cursor = nir_after_cf_list(&store_64bit_if->else_list);
+   nir_p

Mesa (master): nir: Disallow goto and goto_if in clone and [de]serialize

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 5e2e882270cfb174513bcc9a1e717077a8f39130
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e2e882270cfb174513bcc9a1e717077a8f39130

Author: Jason Ekstrand 
Date:   Thu Sep 24 18:55:09 2020 -0500

nir: Disallow goto and goto_if in clone and [de]serialize

Reviewed-by: Matt Turner 
Part-of: 

---

 src/compiler/nir/nir_clone.c | 3 +++
 src/compiler/nir/nir_serialize.c | 7 +++
 2 files changed, 10 insertions(+)

diff --git a/src/compiler/nir/nir_clone.c b/src/compiler/nir/nir_clone.c
index d090a7cf160..5caf3fc3939 100644
--- a/src/compiler/nir/nir_clone.c
+++ b/src/compiler/nir/nir_clone.c
@@ -472,6 +472,9 @@ clone_phi(clone_state *state, const nir_phi_instr *phi, 
nir_block *nblk)
 static nir_jump_instr *
 clone_jump(clone_state *state, const nir_jump_instr *jmp)
 {
+   /* These aren't handled because they require special block linking */
+   assert(jmp->type != nir_jump_goto && jmp->type != nir_jump_goto_if);
+
nir_jump_instr *njmp = nir_jump_instr_create(state->ns, jmp->type);
 
return njmp;
diff --git a/src/compiler/nir/nir_serialize.c b/src/compiler/nir/nir_serialize.c
index 64319886cd9..baa6953f33e 100644
--- a/src/compiler/nir/nir_serialize.c
+++ b/src/compiler/nir/nir_serialize.c
@@ -1636,6 +1636,9 @@ read_fixup_phis(read_ctx *ctx)
 static void
 write_jump(write_ctx *ctx, const nir_jump_instr *jmp)
 {
+   /* These aren't handled because they require special block linking */
+   assert(jmp->type != nir_jump_goto && jmp->type != nir_jump_goto_if);
+
assert(jmp->type < 4);
 
union packed_instr header;
@@ -1650,6 +1653,10 @@ write_jump(write_ctx *ctx, const nir_jump_instr *jmp)
 static nir_jump_instr *
 read_jump(read_ctx *ctx, union packed_instr header)
 {
+   /* These aren't handled because they require special block linking */
+   assert(header.jump.type != nir_jump_goto &&
+  header.jump.type != nir_jump_goto_if);
+
nir_jump_instr *jmp = nir_jump_instr_create(ctx->nir, header.jump.type);
return jmp;
 }

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Mesa (master): nir/copy_propagate: Copy-prop into jump conditions

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 9a48ed84ecd166d57fb8018401eb5491d8f80bb1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a48ed84ecd166d57fb8018401eb5491d8f80bb1

Author: Jason Ekstrand 
Date:   Thu Sep 24 18:21:58 2020 -0500

nir/copy_propagate: Copy-prop into jump conditions

Reviewed-by: Eric Anholt 
Reviewed-by: Matt Turner 
Part-of: 

---

 src/compiler/nir/nir_opt_copy_propagate.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/src/compiler/nir/nir_opt_copy_propagate.c 
b/src/compiler/nir/nir_opt_copy_propagate.c
index e67bcf3c2ef..be9bce3ef2e 100644
--- a/src/compiler/nir/nir_opt_copy_propagate.c
+++ b/src/compiler/nir/nir_opt_copy_propagate.c
@@ -230,6 +230,16 @@ copy_prop_instr(nir_instr *instr)
   return progress;
}
 
+   case nir_instr_type_jump: {
+  nir_jump_instr *jump = nir_instr_as_jump(instr);
+  if (jump->type == nir_jump_goto_if) {
+ while (copy_prop_src(&jump->condition, instr, NULL, 1))
+progress = true;
+  }
+
+  return progress;
+   }
+
case nir_instr_type_phi: {
   nir_phi_instr *phi = nir_instr_as_phi(instr);
   assert(phi->dest.is_ssa);

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Mesa (master): intel/nir: Use nir control flow helpers

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: b2ede6280c0a6030efb0bf2005b018dbacfbf4f1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b2ede6280c0a6030efb0bf2005b018dbacfbf4f1

Author: Connor Abbott 
Date:   Tue Apr  9 22:16:26 2019 +0200

intel/nir: Use nir control flow helpers

Reviewed-by: Jason Ekstrand 
Reviewed-by: Matt Turner 
Part-of: 

---

 src/intel/blorp/blorp_blit.c | 21 +
 src/intel/compiler/brw_nir_tcs_workarounds.c |  9 +++--
 2 files changed, 12 insertions(+), 18 deletions(-)

diff --git a/src/intel/blorp/blorp_blit.c b/src/intel/blorp/blorp_blit.c
index 3aac0abf274..e783277bbb1 100644
--- a/src/intel/blorp/blorp_blit.c
+++ b/src/intel/blorp/blorp_blit.c
@@ -564,9 +564,6 @@ blorp_nir_combine_samples(nir_builder *b, struct 
brw_blorp_blit_vars *v,
   nir_alu_type dst_type,
   enum blorp_filter filter)
 {
-   /* If non-null, this is the outer-most if statement */
-   nir_if *outer_if = NULL;
-
nir_variable *color =
   nir_local_variable_create(b->impl, glsl_vec4_type(), "color");
 
@@ -603,6 +600,10 @@ blorp_nir_combine_samples(nir_builder *b, struct 
brw_blorp_blit_vars *v,
   unreachable("Invalid filter");
}
 
+   /* If true, we inserted an if statement that we need to pop at at the end.
+*/
+   bool inserted_if = false;
+
/* We add together samples using a binary tree structure, e.g. for 4x MSAA:
 *
 *   result = ((sample[0] + sample[1]) + (sample[2] + sample[3])) / 4
@@ -674,15 +675,11 @@ blorp_nir_combine_samples(nir_builder *b, struct 
brw_blorp_blit_vars *v,
  nir_ssa_def *mcs_clear =
 blorp_nir_mcs_is_clear_color(b, mcs, tex_samples);
 
- nir_if *if_stmt = nir_if_create(b->shader);
- if_stmt->condition = nir_src_for_ssa(nir_ior(b, mcs_zero, mcs_clear));
- nir_cf_node_insert(b->cursor, &if_stmt->cf_node);
-
- b->cursor = nir_after_cf_list(&if_stmt->then_list);
+ nir_push_if(b, nir_ior(b, mcs_zero, mcs_clear));
  nir_store_var(b, color, texture_data[0], 0xf);
 
- b->cursor = nir_after_cf_list(&if_stmt->else_list);
- outer_if = if_stmt;
+ nir_push_else(b, NULL);
+ inserted_if = true;
   }
 
   for (int j = 0; j < count_trailing_one_bits(i); j++) {
@@ -708,8 +705,8 @@ blorp_nir_combine_samples(nir_builder *b, struct 
brw_blorp_blit_vars *v,
 
nir_store_var(b, color, texture_data[0], 0xf);
 
-   if (outer_if)
-  b->cursor = nir_after_cf_node(&outer_if->cf_node);
+   if (inserted_if)
+  nir_pop_if(b, NULL);
 
return nir_load_var(b, color);
 }
diff --git a/src/intel/compiler/brw_nir_tcs_workarounds.c 
b/src/intel/compiler/brw_nir_tcs_workarounds.c
index 174cf6eec88..ac2a90b4cc1 100644
--- a/src/intel/compiler/brw_nir_tcs_workarounds.c
+++ b/src/intel/compiler/brw_nir_tcs_workarounds.c
@@ -100,12 +100,7 @@ emit_quads_workaround(nir_builder *b, nir_block *block)
nir_ior(b, nir_bany(b, nir_flt(b, nir_imm_float(b, 1.0f), outer)),
   nir_bany(b, nir_flt(b, nir_imm_float(b, 1.0f), inner)));
 
-   nir_if *if_stmt = nir_if_create(b->shader);
-   if_stmt->condition = nir_src_for_ssa(any_greater_than_1);
-   nir_builder_cf_insert(b, &if_stmt->cf_node);
-
-   /* Fill out the new then-block */
-   b->cursor = nir_after_cf_list(&if_stmt->then_list);
+   nir_push_if(b, any_greater_than_1);
 
inner = nir_bcsel(b, nir_fge(b, nir_imm_float(b, 1.0f), inner),
 nir_imm_float(b, 2.0f), inner);
@@ -118,6 +113,8 @@ emit_quads_workaround(nir_builder *b, nir_block *block)
store->src[0] = nir_src_for_ssa(inner);
store->src[1] = nir_src_for_ssa(nir_imm_int(b, 0));
nir_builder_instr_insert(b, &store->instr);
+
+   nir_pop_if(b, NULL);
 }
 
 void

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Mesa (master): nir/cf: Better handle intra-block splits

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 7dbb1f7462433940951ce6c3fa22f6368aeafd50
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7dbb1f7462433940951ce6c3fa22f6368aeafd50

Author: Jason Ekstrand 
Date:   Thu Sep 24 23:50:24 2020 -0500

nir/cf: Better handle intra-block splits

In the case where end was a instruction-based cursor, we would mix up
our blocks and end up with block_begin pointing after the second split.
This causes a segfault as the cf_node list walk at the end of the
function never terminates properly.  There's also a possibility of
mix-up if begin is an instruction-based cursor which was found by
inspection.

Fixes: fc7f2d2364a9 "nir/cf: add new control modification API's"
Reviewed-by: Connor Abbott 
Acked-by: Matt Turner 
Part-of: 

---

 src/compiler/nir/nir_control_flow.c | 31 ---
 1 file changed, 24 insertions(+), 7 deletions(-)

diff --git a/src/compiler/nir/nir_control_flow.c 
b/src/compiler/nir/nir_control_flow.c
index 71a98065072..75146cc1cf3 100644
--- a/src/compiler/nir/nir_control_flow.c
+++ b/src/compiler/nir/nir_control_flow.c
@@ -683,16 +683,33 @@ nir_cf_extract(nir_cf_list *extracted, nir_cursor begin, 
nir_cursor end)
   return;
}
 
-   /* In the case where begin points to an instruction in some basic block and
-* end points to the end of the same basic block, we rely on the fact that
-* splitting on an instruction moves earlier instructions into a new basic
-* block. If the later instructions were moved instead, then the end cursor
-* would be pointing to the same place that begin used to point to, which
-* is obviously not what we want.
-*/
split_block_cursor(begin, &block_before, &block_begin);
+
+   /* Splitting a block twice with two cursors created before either split is
+* tricky and there are a couple of places it can go wrong if both cursors
+* point to the same block.  One is if the second cursor is an block-based
+* cursor and, thanks to the split above, it ends up pointing to the wrong
+* block.  If it's a before_block cursor and it's in the same block as
+* begin, then begin must also be a before_block cursor and it should be
+* caught by the nir_cursors_equal check above and we won't get here.  If
+* it's an after_block cursor, we need to re-adjust to ensure that it
+* points to the second one of the split blocks, regardless of which it is.
+*/
+   if (end.option == nir_cursor_after_block && end.block == block_before)
+  end.block = block_begin;
+
split_block_cursor(end, &block_end, &block_after);
 
+   /* The second place this can all go wrong is that it could be that the
+* second split places the original block after the new block in which case
+* the block_begin pointer that we saved off above is pointing to the block
+* at the end rather than the block in the middle like it's supposed to be.
+* In this case, we have to re-adjust begin_block to point to the middle
+* one.
+*/
+   if (block_begin == block_after)
+  block_begin = block_end;
+
extracted->impl = nir_cf_node_get_function(&block_begin->cf_node);
exec_list_make_empty(&extracted->list);
 

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Mesa (master): radeonsi: Fix imports with displayable DCC.

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 55e2b3424decf9f0240bb6fe0fd521e775d28d66
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=55e2b3424decf9f0240bb6fe0fd521e775d28d66

Author: Bas Nieuwenhuizen 
Date:   Tue Sep 29 18:41:31 2020 +0200

radeonsi: Fix imports with displayable DCC.

Otherwise we reset the displayable DCC on import.

Fixes: c6c1fa9a263 "radeonsi: Put retile map in separate buffers."
Acked-by: Pierre-Eric Pelloux-Prayer 
Reviewed-by: Marek Olšák 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3577
Part-of: 

---

 src/gallium/drivers/radeonsi/si_texture.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_texture.c 
b/src/gallium/drivers/radeonsi/si_texture.c
index 68d8e2c1f4e..93e52e75c8d 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -1152,10 +1152,12 @@ static struct si_texture 
*si_texture_create_object(struct pipe_screen *screen,
 
/* Initialize displayable DCC that requires the retile blit. */
if (tex->surface.display_dcc_offset) {
-  /* Uninitialized DCC can hang the display hw.
-   * Clear to white to indicate that. */
-  si_screen_clear_buffer(sscreen, &tex->buffer.b.b, 
tex->surface.display_dcc_offset,
- tex->surface.u.gfx9.display_dcc_size, 
DCC_CLEAR_COLOR_);
+  if (!(surface->flags & RADEON_SURF_IMPORTED)) {
+ /* Uninitialized DCC can hang the display hw.
+  * Clear to white to indicate that. */
+ si_screen_clear_buffer(sscreen, &tex->buffer.b.b, 
tex->surface.display_dcc_offset,
+tex->surface.u.gfx9.display_dcc_size, 
DCC_CLEAR_COLOR_);
+  }
 
   /* Upload the DCC retile map.
* Use a staging buffer for the upload, because

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Mesa (staging/20.1): st/mesa: use roundf instead of floorf for lod-bias rounding

[GitLab Mirror]

Module: Mesa
Branch: staging/20.1
Commit: 30b256c21e08d6193da534b4b700cdfeb47a506f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=30b256c21e08d6193da534b4b700cdfeb47a506f

Author: Erik Faye-Lund 
Date:   Mon Sep 28 16:11:38 2020 +0200

st/mesa: use roundf instead of floorf for lod-bias rounding

There's no good reason not to use a symmetric rounding mode here. This
fixes the following GL CTS case for me:

GTF-GL33.gtf21.GL3Tests.texture_lod_bias.texture_lod_bias_all

Fixes: 132b69c4edb ("st/mesa: round lod_bias to a multiple of 1/256")
Reviewed-by: Marek Olšák 
Part-of: 
(cherry picked from commit 7685c37bf47104497d70c4580abb9e050ea8100f)

---

 .pick_status.json| 2 +-
 src/mesa/state_tracker/st_atom_sampler.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index a734fabb12d..57d4ab82da8 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -310,7 +310,7 @@
 "description": "st/mesa: use roundf instead of floorf for lod-bias 
rounding",
 "nominated": true,
 "nomination_type": 1,
-"resolution": 0,
+"resolution": 1,
 "master_sha": null,
 "because_sha": "132b69c4edb824c70c98f8937c63e49b04f3adff"
 },
diff --git a/src/mesa/state_tracker/st_atom_sampler.c 
b/src/mesa/state_tracker/st_atom_sampler.c
index 7ae981b71b4..3efbdc2c827 100644
--- a/src/mesa/state_tracker/st_atom_sampler.c
+++ b/src/mesa/state_tracker/st_atom_sampler.c
@@ -132,7 +132,7 @@ st_convert_sampler(const struct st_context *st,
 * levels.
 */
sampler->lod_bias = CLAMP(sampler->lod_bias, -16, 16);
-   sampler->lod_bias = floorf(sampler->lod_bias * 256) / 256;
+   sampler->lod_bias = roundf(sampler->lod_bias * 256) / 256;
 
sampler->min_lod = MAX2(msamp->MinLod, 0.0f);
sampler->max_lod = msamp->MaxLod;

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Mesa (staging/20.1): nir/lower_io_arrays: Fix xfb_offset bug

[GitLab Mirror]

Module: Mesa
Branch: staging/20.1
Commit: e1f6000b540c3d48cb573653db6e1bf4e0003050
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e1f6000b540c3d48cb573653db6e1bf4e0003050

Author: Connor Abbott 
Date:   Fri Aug 21 15:51:47 2020 +0200

nir/lower_io_arrays: Fix xfb_offset bug

I noticed this once I started gathering xfb_info after
nir_lower_io_arrays_to_elements_no_indirect.

Fixes: b2bbd978d0b ("nir: fix lowering arrays to elements for XFB outputs")
Reviewed-by: Caio Marcelo de Oliveira Filho 
Part-of: 
(cherry picked from commit 5a88db682e08b5e58b40653872569f5b5d7d)

---

 .pick_status.json  | 2 +-
 src/compiler/nir/nir_lower_io_arrays_to_elements.c | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/.pick_status.json b/.pick_status.json
index 57d4ab82da8..1fce3727bb4 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -211,7 +211,7 @@
 "description": "nir/lower_io_arrays: Fix xfb_offset bug",
 "nominated": true,
 "nomination_type": 1,
-"resolution": 0,
+"resolution": 1,
 "master_sha": null,
 "because_sha": "b2bbd978d0b1c85919c6f3b5f631b3c6cbaaaf8a"
 },
diff --git a/src/compiler/nir/nir_lower_io_arrays_to_elements.c 
b/src/compiler/nir/nir_lower_io_arrays_to_elements.c
index e49abefc0d4..376326575b0 100644
--- a/src/compiler/nir/nir_lower_io_arrays_to_elements.c
+++ b/src/compiler/nir/nir_lower_io_arrays_to_elements.c
@@ -61,7 +61,7 @@ get_io_offset(nir_builder *b, nir_deref_instr *deref, 
nir_variable *var,
  unsigned size = glsl_count_attribute_slots((*p)->type, false);
  offset += size * index;
 
- xfb_offset += index * glsl_get_component_slots((*p)->type) * 4;
+ *xfb_offset += index * glsl_get_component_slots((*p)->type) * 4;
 
  unsigned num_elements = glsl_type_is_array((*p)->type) ?
 glsl_get_aoa_size((*p)->type) : 1;

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Mesa (master): bin/gen_release_notes.py: escape special rST characters

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 636f770233543c00c319895201498c57eece6774
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=636f770233543c00c319895201498c57eece6774

Author: Eric Engestrom 
Date:   Fri Sep 25 21:19:10 2020 +0200

bin/gen_release_notes.py: escape special rST characters

Signed-off-by: Eric Engestrom 
Reviewed-by: Dylan Baker 
Part-of: 

---

 bin/gen_release_notes.py | 22 ++
 1 file changed, 18 insertions(+), 4 deletions(-)

diff --git a/bin/gen_release_notes.py b/bin/gen_release_notes.py
index 716f807b317..880161181a8 100755
--- a/bin/gen_release_notes.py
+++ b/bin/gen_release_notes.py
@@ -25,6 +25,7 @@ import asyncio
 import datetime
 import os
 import pathlib
+import re
 import subprocess
 import sys
 import textwrap
@@ -74,7 +75,7 @@ TEMPLATE = Template(textwrap.dedent("""\
 
 
 %for f in features:
-- ${f}
+- ${rst_escape(f)}
 %endfor
 
 
@@ -82,7 +83,7 @@ TEMPLATE = Template(textwrap.dedent("""\
 -
 
 %for b in bugs:
-- ${b}
+- ${rst_escape(b)}
 %endfor
 
 
@@ -91,15 +92,27 @@ TEMPLATE = Template(textwrap.dedent("""\
 %for c, author_line in changes:
   %if author_line:
 
-${c}
+${rst_escape(c)}
 
   %else:
-- ${c}
+- ${rst_escape(c)}
   %endif
 %endfor
 """))
 
 
+def rst_escape(unsafe_str: str) -> str:
+"Escape rST special chars when they follow or preceed a whitespace"
+special = re.escape(r'`<>*_#[]|')
+unsafe_str = re.sub(r'(^|\s)([' + special + r'])',
+r'\1\\\2',
+unsafe_str)
+unsafe_str = re.sub(r'([' + special + r'])(\s|$)',
+r'\\\1\2',
+unsafe_str)
+return unsafe_str
+
+
 async def gather_commits(version: str) -> str:
 p = await asyncio.create_subprocess_exec(
 'git', 'log', '--oneline', f'mesa-{version}..', '--grep', r'Closes: 
\(https\|#\).*',
@@ -249,6 +262,7 @@ async def main() -> None:
 header_underline=header_underline,
 previous_version=previous_version,
 vk_version=CURRENT_VK_VERSION,
+rst_escape=rst_escape,
 ))
 except:
 print(exceptions.text_error_template().render())

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Mesa (master): 31 new commits

[GitLab Mirror]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ae7975ecd43d769a31debb6190586bd2437a6f63
Author: Erik Faye-Lund 
Date:   Tue Sep 29 19:15:32 2020 +0200

docs: cpu -> CPU

Reviewed-by: Eric Engestrom 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5fe6124661db8e89c437ef1cd4e947c1275c046a
Author: Erik Faye-Lund 
Date:   Tue Sep 29 19:09:35 2020 +0200

docs: Sandybridge -> Sandy Bridge

Reviewed-by: Eric Engestrom 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=302fc31847354550cfaba4141cb64b0df3b66e9c
Author: Erik Faye-Lund 
Date:   Tue Sep 29 19:07:15 2020 +0200

docs: vmware -> VMWare

Reviewed-by: Eric Engestrom 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=37bb6ddcc25a67327e8759901930bccb5b495c67
Author: Erik Faye-Lund 
Date:   Tue Sep 29 19:03:28 2020 +0200

docs: ubuntu -> Ubuntu

Reviewed-by: Eric Engestrom 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c90662dfbac62157e3673c7d91bf4e2d6c69049
Author: Erik Faye-Lund 
Date:   Tue Sep 29 19:01:13 2020 +0200

docs: scons -> SCons

Reviewed-by: Eric Engestrom 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f4f441465acd324f8eb4744b0a34aed5f2d17fa
Author: Erik Faye-Lund 
Date:   Tue Sep 29 18:58:22 2020 +0200

docs: quote "git log"

Reviewed-by: Eric Engestrom 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=50e26e5376e542b6c6483bcfd689ffd5ffd20369
Author: Erik Faye-Lund 
Date:   Tue Sep 29 18:57:33 2020 +0200

docs: git -> Git

Reviewed-by: Eric Engestrom 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=24e8e53bac37de19e1377fac76e98e680eb415bb
Author: Erik Faye-Lund 
Date:   Tue Sep 29 18:49:33 2020 +0200

docs: android -> Android

Reviewed-by: Eric Engestrom 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca613a5a7ef07ff95ffd02c241488fe7f006595d
Author: Erik Faye-Lund 
Date:   Tue Sep 29 18:48:24 2020 +0200

docs: drm -> DRM

Reviewed-by: Eric Engestrom 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f59b19ad04931570c6e9be722943368b8b06a42
Author: Erik Faye-Lund 
Date:   Tue Sep 29 18:47:22 2020 +0200

docs: wayland -> Wayland

Reviewed-by: Eric Engestrom 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d2090e79d0dc56448ac15f6900104c24be1d259
Author: Erik Faye-Lund 
Date:   Tue Sep 29 18:46:58 2020 +0200

docs: x11 -> X11

Reviewed-by: Eric Engestrom 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0db015294ea3ada56dc2cec7ba80d495a6040e27
Author: Erik Faye-Lund 
Date:   Tue Sep 29 18:44:21 2020 +0200

docs: cmake -> CMake

Reviewed-by: Eric Engestrom 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b8b0e5ece02c3f8c40f565688263c3bb7007ee52
Author: Erik Faye-Lund 
Date:   Tue Sep 29 18:41:52 2020 +0200

docs: gpu -> GPU

Reviewed-by: Eric Engestrom 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=12d925dc8d608b80e9078201cefc04ff54d38661
Author: Erik Faye-Lund 
Date:   Tue Sep 29 18:38:30 2020 +0200

docs: visual studio -> Visual Studio

Reviewed-by: Eric Engestrom 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e9d87eacc568366753606b47843c9b7ca8341b0
Author: Erik Faye-Lund 
Date:   Tue Sep 29 18:37:11 2020 +0200

docs: windows -> Windows

Reviewed-by: Eric Engestrom 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0df19e3c6bf74c3b2427740ff62e709c132350ed
Author: Erik Faye-Lund 
Date:   Tue Sep 29 18:34:46 2020 +0200

docs: linux -> Linux

Reviewed-by: Eric Engestrom 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=557ee09c2eab7032180952ff82c8f833637

Mesa (master): vallium: Stop using lower_ubo_ssbo_access_to_offsets

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 1cadbe514138e898d4b0cd3f3d5ba35c20fac87b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1cadbe514138e898d4b0cd3f3d5ba35c20fac87b

Author: Jason Ekstrand 
Date:   Mon Sep 21 17:34:23 2020 -0500

vallium: Stop using lower_ubo_ssbo_access_to_offsets

This legacy path needs to die.  Drivers shouldn't be using it anymore.
While we're here, we also implement the resource_reindex intrinsic which
doesn't come up in most direct-access cases but can depending on how the
OpAccessChains are structured.  It comes up all the time in the variable
pointers world.

Reviewed-by: Dave Airlie 
Part-of: 

---

 .../frontends/vallium/val_lower_vulkan_resource.c  | 61 --
 src/gallium/frontends/vallium/val_pipeline.c   |  5 +-
 2 files changed, 61 insertions(+), 5 deletions(-)

diff --git a/src/gallium/frontends/vallium/val_lower_vulkan_resource.c 
b/src/gallium/frontends/vallium/val_lower_vulkan_resource.c
index 801fd64d9f9..131aa9ce7ff 100644
--- a/src/gallium/frontends/vallium/val_lower_vulkan_resource.c
+++ b/src/gallium/frontends/vallium/val_lower_vulkan_resource.c
@@ -31,8 +31,15 @@ lower_vulkan_resource_index(const nir_instr *instr, const 
void *data_cb)
 {
if (instr->type == nir_instr_type_intrinsic) {
   nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
-  if (intrin->intrinsic == nir_intrinsic_vulkan_resource_index)
+  switch (intrin->intrinsic) {
+  case nir_intrinsic_vulkan_resource_index:
+  case nir_intrinsic_vulkan_resource_reindex:
+  case nir_intrinsic_load_vulkan_descriptor:
+  case nir_intrinsic_get_ssbo_size:
  return true;
+  default:
+ return false;
+  }
}
if (instr->type == nir_instr_type_tex) {
   return true;
@@ -62,11 +69,35 @@ static nir_ssa_def *lower_vri_intrin_vri(struct nir_builder 
*b,
  value += binding->stage[b->shader->info.stage].const_buffer_index + 1;
else
  value += binding->stage[b->shader->info.stage].shader_buffer_index;
+
+   /* The SSA size for indices is the same as for pointers.  We use
+* nir_addr_format_32bit_index_offset so we need a vec2.  We don't need all
+* that data so just stuff a 0 in the second component.
+*/
if (nir_src_is_const(intrin->src[0])) {
   value += nir_src_comp_as_int(intrin->src[0], 0);
-  return nir_imm_int(b, value);
+  return nir_imm_ivec2(b, value, 0);
} else
-  return nir_iadd_imm(b, intrin->src[0].ssa, value);
+  return nir_vec2(b, nir_iadd_imm(b, intrin->src[0].ssa, value),
+ nir_imm_int(b, 0));
+}
+
+static nir_ssa_def *lower_vri_intrin_vrri(struct nir_builder *b,
+  nir_instr *instr, void *data_cb)
+{
+   nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
+   nir_ssa_def *old_index = nir_ssa_for_src(b, intrin->src[0], 1);
+   nir_ssa_def *delta = nir_ssa_for_src(b, intrin->src[1], 1);
+   return nir_vec2(b, nir_iadd(b, old_index, delta),
+  nir_imm_int(b, 0));
+}
+
+static nir_ssa_def *lower_vri_intrin_lvd(struct nir_builder *b,
+ nir_instr *instr, void *data_cb)
+{
+   nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
+   nir_ssa_def *index = nir_ssa_for_src(b, intrin->src[0], 1);
+   return nir_vec2(b, index, nir_imm_int(b, 0));
 }
 
 static int lower_vri_instr_tex_deref(nir_tex_instr *tex,
@@ -131,8 +162,30 @@ static nir_ssa_def *lower_vri_instr(struct nir_builder *b,
 {
if (instr->type == nir_instr_type_intrinsic) {
   nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
-  if (intrin->intrinsic == nir_intrinsic_vulkan_resource_index)
+  switch (intrin->intrinsic) {
+  case nir_intrinsic_vulkan_resource_index:
  return lower_vri_intrin_vri(b, instr, data_cb);
+
+  case nir_intrinsic_vulkan_resource_reindex:
+ return lower_vri_intrin_vrri(b, instr, data_cb);
+
+  case nir_intrinsic_load_vulkan_descriptor:
+ return lower_vri_intrin_lvd(b, instr, data_cb);
+
+  case nir_intrinsic_get_ssbo_size: {
+ /* The result of the load_vulkan_descriptor is a vec2(index, offset)
+  * but we only want the index in get_ssbo_size.
+  */
+ b->cursor = nir_before_instr(&intrin->instr);
+ nir_ssa_def *index = nir_ssa_for_src(b, intrin->src[0], 1);
+ nir_instr_rewrite_src(&intrin->instr, &intrin->src[0],
+   nir_src_for_ssa(index));
+ return NULL;
+  }
+
+  default:
+ return NULL;
+  }
}
if (instr->type == nir_instr_type_tex)
   lower_vri_instr_tex(b, nir_instr_as_tex(instr), data_cb);
diff --git a/src/gallium/frontends/vallium/val_pipeline.c 
b/src/gallium/frontends/vallium/val_pipeline.c
index d884ed541fe..dc0465dd895 100644
--- a/src/gallium/frontends/vallium/val_pipeline.c
+++ b/src/gall

Mesa (master): spirv: Delete the legacy offset/index UBO/SSBO lowering

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 92a594b15402364097a62b5724c3da33327e17fd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=92a594b15402364097a62b5724c3da33327e17fd

Author: Jason Ekstrand 
Date:   Sat May 30 00:50:56 2020 -0500

spirv: Delete the legacy offset/index UBO/SSBO lowering

Reviewed-by: Dave Airlie 
Part-of: 

---

 src/compiler/spirv/nir_spirv.h  |   3 -
 src/compiler/spirv/spirv_to_nir.c   |  83 ---
 src/compiler/spirv/vtn_private.h|  10 -
 src/compiler/spirv/vtn_variables.c  | 655 +++-
 src/freedreno/vulkan/tu_shader.c|   1 -
 src/gallium/drivers/freedreno/ir3/ir3_cmdline.c |   1 -
 6 files changed, 70 insertions(+), 683 deletions(-)

diff --git a/src/compiler/spirv/nir_spirv.h b/src/compiler/spirv/nir_spirv.h
index b4d8b98b9ca..f4a5921a6d2 100644
--- a/src/compiler/spirv/nir_spirv.h
+++ b/src/compiler/spirv/nir_spirv.h
@@ -56,9 +56,6 @@ enum nir_spirv_execution_environment {
 struct spirv_to_nir_options {
enum nir_spirv_execution_environment environment;
 
-   /* Whether or not to lower all UBO/SSBO access to offsets up-front. */
-   bool lower_ubo_ssbo_access_to_offsets;
-
/* Whether to make FragCoord to a system value, the same as
 * GLSLFragCoordIsSysVal in GLSL.
 */
diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 09c7a804b9e..1ee5f90842c 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -3301,34 +3301,6 @@ vtn_handle_image(struct vtn_builder *b, SpvOp opcode,
   vtn_emit_memory_barrier(b, scope, after_semantics);
 }
 
-static nir_intrinsic_op
-get_ssbo_nir_atomic_op(struct vtn_builder *b, SpvOp opcode)
-{
-   switch (opcode) {
-   case SpvOpAtomicLoad: return nir_intrinsic_load_ssbo;
-   case SpvOpAtomicStore:return nir_intrinsic_store_ssbo;
-#define OP(S, N) case SpvOp##S: return nir_intrinsic_ssbo_##N;
-   OP(AtomicExchange,atomic_exchange)
-   OP(AtomicCompareExchange, atomic_comp_swap)
-   OP(AtomicCompareExchangeWeak, atomic_comp_swap)
-   OP(AtomicIIncrement,  atomic_add)
-   OP(AtomicIDecrement,  atomic_add)
-   OP(AtomicIAdd,atomic_add)
-   OP(AtomicISub,atomic_add)
-   OP(AtomicSMin,atomic_imin)
-   OP(AtomicUMin,atomic_umin)
-   OP(AtomicSMax,atomic_imax)
-   OP(AtomicUMax,atomic_umax)
-   OP(AtomicAnd, atomic_and)
-   OP(AtomicOr,  atomic_or)
-   OP(AtomicXor, atomic_xor)
-   OP(AtomicFAddEXT, atomic_fadd)
-#undef OP
-   default:
-  vtn_fail_with_opcode("Invalid SSBO atomic", opcode);
-   }
-}
-
 static nir_intrinsic_op
 get_uniform_nir_atomic_op(struct vtn_builder *b, SpvOp opcode)
 {
@@ -3473,61 +3445,6 @@ vtn_handle_atomics(struct vtn_builder *b, SpvOp opcode,
  unreachable("Invalid SPIR-V atomic");
 
   }
-   } else if (vtn_pointer_uses_ssa_offset(b, ptr)) {
-  nir_ssa_def *offset, *index;
-  offset = vtn_pointer_to_offset(b, ptr, &index);
-
-  assert(ptr->mode == vtn_variable_mode_ssbo);
-
-  nir_intrinsic_op op  = get_ssbo_nir_atomic_op(b, opcode);
-  atomic = nir_intrinsic_instr_create(b->nb.shader, op);
-
-  nir_intrinsic_set_access(atomic, access | ACCESS_COHERENT);
-
-  int src = 0;
-  switch (opcode) {
-  case SpvOpAtomicLoad:
- atomic->num_components = glsl_get_vector_elements(ptr->type->type);
- nir_intrinsic_set_align(atomic, 4, 0);
- if (ptr->mode == vtn_variable_mode_ssbo)
-atomic->src[src++] = nir_src_for_ssa(index);
- atomic->src[src++] = nir_src_for_ssa(offset);
- break;
-
-  case SpvOpAtomicStore:
- atomic->num_components = glsl_get_vector_elements(ptr->type->type);
- nir_intrinsic_set_write_mask(atomic, (1 << atomic->num_components) - 
1);
- nir_intrinsic_set_align(atomic, 4, 0);
- atomic->src[src++] = nir_src_for_ssa(vtn_get_nir_ssa(b, w[4]));
- if (ptr->mode == vtn_variable_mode_ssbo)
-atomic->src[src++] = nir_src_for_ssa(index);
- atomic->src[src++] = nir_src_for_ssa(offset);
- break;
-
-  case SpvOpAtomicExchange:
-  case SpvOpAtomicCompareExchange:
-  case SpvOpAtomicCompareExchangeWeak:
-  case SpvOpAtomicIIncrement:
-  case SpvOpAtomicIDecrement:
-  case SpvOpAtomicIAdd:
-  case SpvOpAtomicISub:
-  case SpvOpAtomicSMin:
-  case SpvOpAtomicUMin:
-  case SpvOpAtomicSMax:
-  case SpvOpAtomicUMax:
-  case SpvOpAtomicAnd:
-  case SpvOpAtomicOr:
-  case SpvOpAtomicXor:
-  case SpvOpAtomicFAddEXT:
- if (ptr->mode == vtn_variable_mode_ssbo)
-atomic->src[src++] = nir_src_for_ssa(index);
- atomic->src[src++] = nir_src_for_ssa(offset);

Mesa (master): nir: Allow creating variables with nir_var_mem_push_const.

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 7a2b4ce22e40471b45c5506f970bedac678243fe
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a2b4ce22e40471b45c5506f970bedac678243fe

Author: Jason Ekstrand 
Date:   Wed May 27 16:51:04 2020 -0500

nir: Allow creating variables with nir_var_mem_push_const.

Reviewed-by: Caio Marcelo de Oliveira Filho 
Part-of: 

---

 src/compiler/nir/nir.c  | 5 +
 src/compiler/nir/nir_print.c| 2 ++
 src/compiler/nir/nir_validate.c | 4 +++-
 3 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/src/compiler/nir/nir.c b/src/compiler/nir/nir.c
index 99d11871b9a..a57ca421e0a 100644
--- a/src/compiler/nir/nir.c
+++ b/src/compiler/nir/nir.c
@@ -115,6 +115,7 @@ nir_shader_add_variable(nir_shader *shader, nir_variable 
*var)
case nir_var_mem_ssbo:
case nir_var_mem_shared:
case nir_var_system_value:
+   case nir_var_mem_push_const:
case nir_var_mem_constant:
   break;
 
@@ -122,10 +123,6 @@ nir_shader_add_variable(nir_shader *shader, nir_variable 
*var)
   assert(!"nir_shader_add_variable cannot be used for global memory");
   return;
 
-   case nir_var_mem_push_const:
-  assert(!"nir_var_push_constant is not supposed to be used for 
variables");
-  return;
-
default:
   assert(!"invalid mode");
   return;
diff --git a/src/compiler/nir/nir_print.c b/src/compiler/nir/nir_print.c
index fa1b7044160..c84c70ac9b7 100644
--- a/src/compiler/nir/nir_print.c
+++ b/src/compiler/nir/nir_print.c
@@ -465,6 +465,8 @@ get_variable_mode_str(nir_variable_mode mode, bool 
want_local_global_mode)
   return "shared";
case nir_var_mem_global:
   return "global";
+   case nir_var_mem_push_const:
+  return "push_const";
case nir_var_mem_constant:
   return "constant";
case nir_var_shader_temp:
diff --git a/src/compiler/nir/nir_validate.c b/src/compiler/nir/nir_validate.c
index 90576b0a08f..0be74297858 100644
--- a/src/compiler/nir/nir_validate.c
+++ b/src/compiler/nir/nir_validate.c
@@ -457,7 +457,8 @@ validate_deref_instr(nir_deref_instr *instr, validate_state 
*state)
  if (instr->mode == nir_var_mem_ubo ||
  instr->mode == nir_var_mem_ssbo ||
  instr->mode == nir_var_mem_shared ||
- instr->mode == nir_var_mem_global) {
+ instr->mode == nir_var_mem_global ||
+ instr->mode == nir_var_mem_push_const) {
 /* Shared variables and UBO/SSBOs have a bit more relaxed rules
  * because we need to be able to handle array derefs on vectors.
  * Fortunately, nir_lower_io handles these just fine.
@@ -1410,6 +1411,7 @@ nir_validate_shader(nir_shader *shader, const char *when)
   nir_var_system_value |
   nir_var_mem_ssbo |
   nir_var_mem_shared |
+  nir_var_mem_push_const |
   nir_var_mem_constant;
 
exec_list_validate(&shader->variables);

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Mesa (master): anv,radv,tu,val: Call nir_lower_io for push constants

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: d3fa7451a6651ea78bd4d1ec2f63e052e7608531
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d3fa7451a6651ea78bd4d1ec2f63e052e7608531

Author: Jason Ekstrand 
Date:   Wed May 27 17:09:33 2020 -0500

anv,radv,tu,val: Call nir_lower_io for push constants

Reviewed-by: Caio Marcelo de Oliveira Filho 
Part-of: 

---

 src/amd/vulkan/radv_shader.c | 3 +++
 src/freedreno/vulkan/tu_shader.c | 3 +++
 src/gallium/frontends/vallium/val_pipeline.c | 3 +++
 src/intel/vulkan/anv_pipeline.c  | 2 ++
 4 files changed, 11 insertions(+)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index e2f8d56bfbe..88a50414334 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -653,6 +653,9 @@ radv_shader_compile_to_nir(struct radv_device *device,
 */
nir_lower_var_copies(nir);
 
+   NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_push_const,
+  nir_address_format_32bit_offset);
+
NIR_PASS_V(nir, nir_lower_explicit_io,
   nir_var_mem_ubo | nir_var_mem_ssbo,
   nir_address_format_32bit_index_offset);
diff --git a/src/freedreno/vulkan/tu_shader.c b/src/freedreno/vulkan/tu_shader.c
index 9d4fe21470d..218a206777f 100644
--- a/src/freedreno/vulkan/tu_shader.c
+++ b/src/freedreno/vulkan/tu_shader.c
@@ -765,6 +765,9 @@ tu_shader_create(struct tu_device *dev,
  &shader->multi_pos_output, dev);
}
 
+   NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_push_const,
+  nir_address_format_32bit_offset);
+
NIR_PASS_V(nir, nir_lower_explicit_io,
   nir_var_mem_ubo | nir_var_mem_ssbo,
   nir_address_format_vec2_index_32bit_offset);
diff --git a/src/gallium/frontends/vallium/val_pipeline.c 
b/src/gallium/frontends/vallium/val_pipeline.c
index a1d83902c56..d884ed541fe 100644
--- a/src/gallium/frontends/vallium/val_pipeline.c
+++ b/src/gallium/frontends/vallium/val_pipeline.c
@@ -573,6 +573,9 @@ val_shader_compile_to_ir(struct val_pipeline *pipeline,
NIR_PASS_V(nir, nir_split_var_copies);
NIR_PASS_V(nir, nir_lower_global_vars_to_local);
 
+   NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_push_const,
+  nir_address_format_32bit_offset);
+
if (nir->info.stage == MESA_SHADER_COMPUTE) {
   NIR_PASS_V(nir, nir_lower_vars_to_explicit_types, nir_var_mem_shared, 
shared_var_info);
   NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_shared, 
nir_address_format_32bit_offset);
diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c
index a16137786bb..36da2cc8b6e 100644
--- a/src/intel/vulkan/anv_pipeline.c
+++ b/src/intel/vulkan/anv_pipeline.c
@@ -765,6 +765,8 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
 
NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_global,
   nir_address_format_64bit_global);
+   NIR_PASS_V(nir, nir_lower_explicit_io, nir_var_mem_push_const,
+  nir_address_format_32bit_offset);
 
/* Apply the actual pipeline layout to UBOs, SSBOs, and textures */
anv_nir_apply_pipeline_layout(pdevice,

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Mesa (master): spirv: Use derefs for push constants

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 657d49a9ba17bea52689c8ad53a3752a647cdc53
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=657d49a9ba17bea52689c8ad53a3752a647cdc53

Author: Jason Ekstrand 
Date:   Wed May 27 17:23:45 2020 -0500

spirv: Use derefs for push constants

Reviewed-by: Caio Marcelo de Oliveira Filho 
Part-of: 

---

 src/compiler/spirv/spirv_to_nir.c  |  1 +
 src/compiler/spirv/vtn_variables.c | 73 +-
 2 files changed, 10 insertions(+), 64 deletions(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index e19fd027483..09c7a804b9e 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -844,6 +844,7 @@ vtn_type_needs_explicit_layout(struct vtn_builder *b, enum 
vtn_variable_mode mod
case vtn_variable_mode_ssbo:
case vtn_variable_mode_phys_ssbo:
case vtn_variable_mode_ubo:
+   case vtn_variable_mode_push_constant:
   return true;
 
default:
diff --git a/src/compiler/spirv/vtn_variables.c 
b/src/compiler/spirv/vtn_variables.c
index 4a73fc8dbe7..7ac60317cf2 100644
--- a/src/compiler/spirv/vtn_variables.c
+++ b/src/compiler/spirv/vtn_variables.c
@@ -179,10 +179,9 @@ bool
 vtn_mode_uses_ssa_offset(struct vtn_builder *b,
  enum vtn_variable_mode mode)
 {
-   return ((mode == vtn_variable_mode_ubo ||
-mode == vtn_variable_mode_ssbo) &&
-   b->options->lower_ubo_ssbo_access_to_offsets) ||
-  mode == vtn_variable_mode_push_constant;
+   return (mode == vtn_variable_mode_ubo ||
+   mode == vtn_variable_mode_ssbo) &&
+  b->options->lower_ubo_ssbo_access_to_offsets;
 }
 
 static bool
@@ -203,8 +202,7 @@ vtn_pointer_is_external_block(struct vtn_builder *b,
 {
return ptr->mode == vtn_variable_mode_ssbo ||
   ptr->mode == vtn_variable_mode_ubo ||
-  ptr->mode == vtn_variable_mode_phys_ssbo ||
-  ptr->mode == vtn_variable_mode_push_constant;
+  ptr->mode == vtn_variable_mode_phys_ssbo;
 }
 
 static nir_ssa_def *
@@ -773,60 +771,6 @@ vtn_pointer_to_offset(struct vtn_builder *b, struct 
vtn_pointer *ptr,
return ptr->offset;
 }
 
-/* Tries to compute the size of an interface block based on the strides and
- * offsets that are provided to us in the SPIR-V source.
- */
-static unsigned
-vtn_type_block_size(struct vtn_builder *b, struct vtn_type *type)
-{
-   enum glsl_base_type base_type = glsl_get_base_type(type->type);
-   switch (base_type) {
-   case GLSL_TYPE_UINT:
-   case GLSL_TYPE_INT:
-   case GLSL_TYPE_UINT16:
-   case GLSL_TYPE_INT16:
-   case GLSL_TYPE_UINT8:
-   case GLSL_TYPE_INT8:
-   case GLSL_TYPE_UINT64:
-   case GLSL_TYPE_INT64:
-   case GLSL_TYPE_FLOAT:
-   case GLSL_TYPE_FLOAT16:
-   case GLSL_TYPE_BOOL:
-   case GLSL_TYPE_DOUBLE: {
-  unsigned cols = type->row_major ? glsl_get_vector_elements(type->type) :
-glsl_get_matrix_columns(type->type);
-  if (cols > 1) {
- vtn_assert(type->stride > 0);
- return type->stride * cols;
-  } else {
- unsigned type_size = glsl_get_bit_size(type->type) / 8;
- return glsl_get_vector_elements(type->type) * type_size;
-  }
-   }
-
-   case GLSL_TYPE_STRUCT:
-   case GLSL_TYPE_INTERFACE: {
-  unsigned size = 0;
-  unsigned num_fields = glsl_get_length(type->type);
-  for (unsigned f = 0; f < num_fields; f++) {
- unsigned field_end = type->offsets[f] +
-  vtn_type_block_size(b, type->members[f]);
- size = MAX2(size, field_end);
-  }
-  return size;
-   }
-
-   case GLSL_TYPE_ARRAY:
-  vtn_assert(type->stride > 0);
-  vtn_assert(glsl_get_length(type->type) > 0);
-  return type->stride * glsl_get_length(type->type);
-
-   default:
-  vtn_fail("Invalid block type");
-  return 0;
-   }
-}
-
 static void
 _vtn_load_store_tail(struct vtn_builder *b, nir_intrinsic_op op, bool load,
  nir_ssa_def *index, nir_ssa_def *offset,
@@ -1876,7 +1820,7 @@ vtn_storage_class_to_mode(struct vtn_builder *b,
   break;
case SpvStorageClassPushConstant:
   mode = vtn_variable_mode_push_constant;
-  nir_mode = nir_var_uniform;
+  nir_mode = nir_var_mem_push_const;
   break;
case SpvStorageClassInput:
   mode = vtn_variable_mode_input;
@@ -2203,7 +2147,8 @@ vtn_create_variable(struct vtn_builder *b, struct 
vtn_value *val,
   }
   break;
case vtn_variable_mode_push_constant:
-  b->shader->num_uniforms = vtn_type_block_size(b, type);
+  b->shader->num_uniforms =
+ glsl_get_explicit_size(without_array->type, false);
   break;
 
case vtn_variable_mode_image:
@@ -2249,6 +2194,7 @@ vtn_create_variable(struct vtn_builder *b, struct 
vtn_value *val,
 
case vtn_variable_mode_ubo:
case vtn_variable_mode_ssbo:
+   case vtn_variable_mo

Mesa (master): nir/lower_io: Add support for push constants

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: ac7537f155b65801fa41773c8024c335c006c8bb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac7537f155b65801fa41773c8024c335c006c8bb

Author: Jason Ekstrand 
Date:   Wed May 27 17:08:28 2020 -0500

nir/lower_io: Add support for push constants

Reviewed-by: Caio Marcelo de Oliveira Filho 
Part-of: 

---

 src/compiler/nir/nir.h  |  9 -
 src/compiler/nir/nir_lower_io.c | 16 ++--
 2 files changed, 22 insertions(+), 3 deletions(-)

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 2f9409c857d..1ac0ba45cee 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -1897,7 +1897,7 @@ nir_intrinsic_set_##name(nir_intrinsic_instr *instr, type 
val)\
instr->const_index[info->index_map[NIR_INTRINSIC_##flag] - 1] = val;   \
 } \
 static inline bool\
-nir_intrinsic_has_##name(nir_intrinsic_instr *instr)  \
+nir_intrinsic_has_##name(const nir_intrinsic_instr *instr)\
 { \
const nir_intrinsic_info *info = &nir_intrinsic_infos[instr->intrinsic];   \
return info->index_map[NIR_INTRINSIC_##flag] > 0;  \
@@ -1959,6 +1959,13 @@ nir_intrinsic_align(const nir_intrinsic_instr *intrin)
return align_offset ? 1 << (ffs(align_offset) - 1) : align_mul;
 }
 
+static inline bool
+nir_intrinsic_has_align(const nir_intrinsic_instr *intrin)
+{
+   return nir_intrinsic_has_align_mul(intrin) &&
+  nir_intrinsic_has_align_offset(intrin);
+}
+
 static inline void
 nir_intrinsic_set_io_semantics(nir_intrinsic_instr *intrin,
nir_io_semantics semantics)
diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c
index 9fb49c1b466..c4284022752 100644
--- a/src/compiler/nir/nir_lower_io.c
+++ b/src/compiler/nir/nir_lower_io.c
@@ -849,7 +849,7 @@ build_addr_for_var(nir_builder *b, nir_variable *var,
 {
assert(var->data.mode & (nir_var_uniform | nir_var_mem_shared |
 nir_var_shader_temp | nir_var_function_temp |
-nir_var_mem_constant));
+nir_var_mem_push_const | nir_var_mem_constant));
 
const unsigned num_comps = nir_address_format_num_components(addr_format);
const unsigned bit_size = nir_address_format_bit_size(addr_format);
@@ -1134,6 +1134,10 @@ build_explicit_io_load(nir_builder *b, 
nir_intrinsic_instr *intrin,
  op = nir_intrinsic_load_global;
   }
   break;
+   case nir_var_mem_push_const:
+  assert(addr_format == nir_address_format_32bit_offset);
+  op = nir_intrinsic_load_push_constant;
+  break;
case nir_var_mem_constant:
   if (addr_format_is_offset(addr_format)) {
  op = nir_intrinsic_load_constant;
@@ -1164,6 +1168,13 @@ build_explicit_io_load(nir_builder *b, 
nir_intrinsic_instr *intrin,
if (op == nir_intrinsic_load_constant) {
   nir_intrinsic_set_base(load, 0);
   nir_intrinsic_set_range(load, b->shader->constant_data_size);
+   } else if (mode == nir_var_mem_push_const) {
+  /* Push constants are required to be able to be chased back to the
+   * variable so we can provide a base/range.
+   */
+  nir_variable *var = nir_deref_instr_get_variable(deref);
+  nir_intrinsic_set_base(load, 0);
+  nir_intrinsic_set_range(load, glsl_get_explicit_size(var->type, false));
}
 
unsigned bit_size = intrin->dest.ssa.bit_size;
@@ -1172,7 +1183,8 @@ build_explicit_io_load(nir_builder *b, 
nir_intrinsic_instr *intrin,
   bit_size = 32;
}
 
-   nir_intrinsic_set_align(load, align_mul, align_offset);
+   if (nir_intrinsic_has_align(load))
+  nir_intrinsic_set_align(load, align_mul, align_offset);
 
if (nir_intrinsic_has_range_base(load)) {
   unsigned base, range;

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Mesa (master): gallivm/nir: handle non-32-bit mul high

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 760ba65733d7915a61eaaebd073ce7c06cafec2e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=760ba65733d7915a61eaaebd073ce7c06cafec2e

Author: Dave Airlie 
Date:   Tue Sep 29 17:10:07 2020 +1000

gallivm/nir: handle non-32-bit mul high

Reviewed-by: Roland Scheidegger 
Part-of: 

---

 src/gallium/auxiliary/gallivm/lp_bld_nir.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_nir.c 
b/src/gallium/auxiliary/gallivm/lp_bld_nir.c
index 93879969fd0..612a4ff754e 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_nir.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_nir.c
@@ -699,7 +699,7 @@ static LLVMValueRef do_alu_action(struct 
lp_build_nir_context *bld_base,
   break;
case nir_op_imul_high: {
   LLVMValueRef hi_bits;
-  lp_build_mul_32_lohi(&bld_base->int_bld, src[0], src[1], &hi_bits);
+  lp_build_mul_32_lohi(get_int_bld(bld_base, false, src_bit_size[0]), 
src[0], src[1], &hi_bits);
   result = hi_bits;
   break;
}
@@ -818,7 +818,7 @@ static LLVMValueRef do_alu_action(struct 
lp_build_nir_context *bld_base,
   break;
case nir_op_umul_high: {
   LLVMValueRef hi_bits;
-  lp_build_mul_32_lohi(&bld_base->uint_bld, src[0], src[1], &hi_bits);
+  lp_build_mul_32_lohi(get_int_bld(bld_base, true, src_bit_size[0]), 
src[0], src[1], &hi_bits);
   result = hi_bits;
   break;
}

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Mesa (master): gallivm: fix 64-bit CL intrinsics.

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 28911360507312dd6176c1c53d147846a9849e1a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=28911360507312dd6176c1c53d147846a9849e1a

Author: Dave Airlie 
Date:   Tue Sep 29 16:27:58 2020 +1000

gallivm: fix 64-bit CL intrinsics.

This fixes a bunch of bad casts in piglit tests

Reviewed-by: Roland Scheidegger 
Part-of: 

---

 src/gallium/auxiliary/gallivm/lp_bld_nir_soa.c | 25 +++--
 1 file changed, 19 insertions(+), 6 deletions(-)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_nir_soa.c 
b/src/gallium/auxiliary/gallivm/lp_bld_nir_soa.c
index 54a286c1662..2b10baba5ae 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_nir_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_nir_soa.c
@@ -1431,6 +1431,7 @@ static void emit_sysval_intrin(struct 
lp_build_nir_context *bld_base,
 {
struct lp_build_nir_soa_context *bld = (struct lp_build_nir_soa_context 
*)bld_base;
struct gallivm_state *gallivm = bld_base->base.gallivm;
+   struct lp_build_context *bld_broad = get_int_bld(bld_base, true, 
instr->dest.ssa.bit_size);
switch (instr->intrinsic) {
case nir_intrinsic_load_instance_id:
   result[0] = lp_build_broadcast_scalar(&bld_base->uint_bld, 
bld->system_values.instance_id);
@@ -1447,18 +1448,30 @@ static void emit_sysval_intrin(struct 
lp_build_nir_context *bld_base,
case nir_intrinsic_load_primitive_id:
   result[0] = bld->system_values.prim_id;
   break;
-   case nir_intrinsic_load_work_group_id:
-  for (unsigned i = 0; i < 3; i++)
- result[i] = lp_build_broadcast_scalar(&bld_base->uint_bld, 
LLVMBuildExtractElement(gallivm->builder, bld->system_values.block_id, 
lp_build_const_int32(gallivm, i), ""));
+   case nir_intrinsic_load_work_group_id: {
+  LLVMValueRef tmp[3];
+  for (unsigned i = 0; i < 3; i++) {
+ tmp[i] = LLVMBuildExtractElement(gallivm->builder, 
bld->system_values.block_id, lp_build_const_int32(gallivm, i), "");
+ if (instr->dest.ssa.bit_size == 64)
+tmp[i] = LLVMBuildZExt(gallivm->builder, tmp[i], 
bld_base->uint64_bld.elem_type, "");
+ result[i] = lp_build_broadcast_scalar(bld_broad, tmp[i]);
+  }
   break;
+   }
case nir_intrinsic_load_local_invocation_id:
   for (unsigned i = 0; i < 3; i++)
  result[i] = LLVMBuildExtractValue(gallivm->builder, 
bld->system_values.thread_id, i, "");
   break;
-   case nir_intrinsic_load_num_work_groups:
-  for (unsigned i = 0; i < 3; i++)
- result[i] = lp_build_broadcast_scalar(&bld_base->uint_bld, 
LLVMBuildExtractElement(gallivm->builder, bld->system_values.grid_size, 
lp_build_const_int32(gallivm, i), ""));
+   case nir_intrinsic_load_num_work_groups: {
+  LLVMValueRef tmp[3];
+  for (unsigned i = 0; i < 3; i++) {
+ tmp[i] = LLVMBuildExtractElement(gallivm->builder, 
bld->system_values.grid_size, lp_build_const_int32(gallivm, i), "");
+ if (instr->dest.ssa.bit_size == 64)
+tmp[i] = LLVMBuildZExt(gallivm->builder, tmp[i], 
bld_base->uint64_bld.elem_type, "");
+ result[i] = lp_build_broadcast_scalar(bld_broad, tmp[i]);
+  }
   break;
+   }
case nir_intrinsic_load_invocation_id:
   if (bld_base->shader->info.stage == MESA_SHADER_TESS_CTRL)
  result[0] = bld->system_values.invocation_id;

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Mesa (master): llvmpipe: use an alternate env var to enable clover.

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: b0504ed682f7df16ec108016b09ad6ede1c290a4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0504ed682f7df16ec108016b09ad6ede1c290a4

Author: Dave Airlie 
Date:   Tue Sep 29 08:35:20 2020 +1000

llvmpipe: use an alternate env var to enable clover.

This can be used outside debug contexts.

Reviewed-by: Roland Scheidegger 
Part-of: 

---

 src/gallium/drivers/llvmpipe/lp_debug.h  | 3 +--
 src/gallium/drivers/llvmpipe/lp_screen.c | 4 ++--
 src/gallium/drivers/llvmpipe/lp_screen.h | 1 +
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/llvmpipe/lp_debug.h 
b/src/gallium/drivers/llvmpipe/lp_debug.h
index 41047fbc754..d76b9be7544 100644
--- a/src/gallium/drivers/llvmpipe/lp_debug.h
+++ b/src/gallium/drivers/llvmpipe/lp_debug.h
@@ -46,8 +46,7 @@
 #define DEBUG_FS0x8000
 #define DEBUG_CS0x1
 #define DEBUG_TGSI_IR   0x2
-#define DEBUG_CL0x4
-#define DEBUG_CACHE_STATS   0x8
+#define DEBUG_CACHE_STATS   0x4
 
 /* Performance flags.  These are active even on release builds.
  */
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c 
b/src/gallium/drivers/llvmpipe/lp_screen.c
index 218d80e5c48..848a48f54e0 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.c
+++ b/src/gallium/drivers/llvmpipe/lp_screen.c
@@ -74,7 +74,6 @@ static const struct debug_named_value lp_debug_flags[] = {
{ "fs", DEBUG_FS, NULL },
{ "cs", DEBUG_CS, NULL },
{ "tgsi_ir", DEBUG_TGSI_IR, NULL },
-   { "cl", DEBUG_CL, NULL },
{ "cache_stats", DEBUG_CACHE_STATS, NULL },
DEBUG_NAMED_VALUE_END
 };
@@ -357,7 +356,7 @@ llvmpipe_get_shader_param(struct pipe_screen *screen,
switch(shader)
{
case PIPE_SHADER_COMPUTE:
-  if ((LP_DEBUG & DEBUG_CL) && param == PIPE_SHADER_CAP_SUPPORTED_IRS)
+  if ((lscreen->allow_cl) && param == PIPE_SHADER_CAP_SUPPORTED_IRS)
  return (1 << PIPE_SHADER_IR_TGSI) | (1 << PIPE_SHADER_IR_NIR) | (1 << 
PIPE_SHADER_IR_NIR_SERIALIZED);
   /* fallthrough */
case PIPE_SHADER_FRAGMENT:
@@ -914,6 +913,7 @@ llvmpipe_create_screen(struct sw_winsys *winsys)
screen->base.get_disk_shader_cache = lp_get_disk_shader_cache;
llvmpipe_init_screen_resource_funcs(&screen->base);
 
+   screen->allow_cl = !!getenv("LP_CL");
screen->use_tgsi = (LP_DEBUG & DEBUG_TGSI_IR);
screen->num_threads = util_cpu_caps.nr_cpus > 1 ? util_cpu_caps.nr_cpus : 0;
 #ifdef EMBEDDED_DEVICE
diff --git a/src/gallium/drivers/llvmpipe/lp_screen.h 
b/src/gallium/drivers/llvmpipe/lp_screen.h
index 6b3798e4d7a..a790c199cd9 100644
--- a/src/gallium/drivers/llvmpipe/lp_screen.h
+++ b/src/gallium/drivers/llvmpipe/lp_screen.h
@@ -62,6 +62,7 @@ struct llvmpipe_screen
mtx_t cs_mutex;
 
bool use_tgsi;
+   bool allow_cl;
 
struct disk_cache *disk_shader_cache;
unsigned num_disk_shader_cache_hits;

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Mesa (master): gallivm/nir: fix up non 32-bit load stores

[GitLab Mirror]

Module: Mesa
Branch: master
Commit: 5d4502c085521ba149048c958f56ee4a62b8484c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d4502c085521ba149048c958f56ee4a62b8484c

Author: Dave Airlie 
Date:   Tue Sep 29 17:16:01 2020 +1000

gallivm/nir: fix up non 32-bit load stores

This fixes a bunch of opencl tests.

Reviewed-by: Roland Scheidegger 
Part-of: 

---

 src/gallium/auxiliary/gallivm/lp_bld_nir_soa.c | 65 +++---
 1 file changed, 39 insertions(+), 26 deletions(-)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_nir_soa.c 
b/src/gallium/auxiliary/gallivm/lp_bld_nir_soa.c
index 2b10baba5ae..652b160db2d 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_nir_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_nir_soa.c
@@ -35,6 +35,22 @@
 #include "lp_bld_coro.h"
 #include "lp_bld_printf.h"
 #include "util/u_math.h"
+
+static int bit_size_to_shift_size(int bit_size)
+{
+   switch (bit_size) {
+   case 64:
+  return 3;
+   default:
+   case 32:
+  return 2;
+   case 16:
+  return 1;
+   case 8:
+  return 0;
+   }
+}
+
 /*
  * combine the execution mask if there is one with the current mask.
  */
@@ -709,14 +725,8 @@ static void emit_load_kernel_arg(struct 
lp_build_nir_context *bld_base,
LLVMBuilderRef builder = gallivm->builder;
struct lp_build_context *bld_broad = get_int_bld(bld_base, true, bit_size);
LLVMValueRef kernel_args_ptr = bld->kernel_args_ptr;
-   unsigned size_shift = 0;
+   unsigned size_shift = bit_size_to_shift_size(bit_size);
struct lp_build_context *bld_offset = get_int_bld(bld_base, true, 
offset_bit_size);
-   if (bit_size == 16)
-  size_shift = 1;
-   else if (bit_size == 32)
-  size_shift = 2;
-   else if (bit_size == 64)
-  size_shift = 3;
if (size_shift)
   offset = lp_build_shr(bld_offset, offset, 
lp_build_const_int_vec(gallivm, bld_offset->type, size_shift));
 
@@ -945,11 +955,7 @@ static void emit_load_ubo(struct lp_build_nir_context 
*bld_base,
struct lp_build_context *uint_bld = &bld_base->uint_bld;
struct lp_build_context *bld_broad = bit_size == 64 ? &bld_base->dbl_bld : 
&bld_base->base;
LLVMValueRef consts_ptr = lp_build_array_get(gallivm, bld->consts_ptr, 
index);
-   unsigned size_shift = 0;
-   if (bit_size == 32)
-  size_shift = 2;
-   else if (bit_size == 64)
-  size_shift = 3;
+   unsigned size_shift = bit_size_to_shift_size(bit_size);
if (size_shift)
   offset = lp_build_shr(uint_bld, offset, lp_build_const_int_vec(gallivm, 
uint_bld->type, size_shift));
if (bit_size == 64) {
@@ -993,19 +999,22 @@ static void emit_load_mem(struct lp_build_nir_context 
*bld_base,
LLVMBuilderRef builder = bld->bld_base.base.gallivm->builder;
LLVMValueRef ssbo_ptr = NULL;
struct lp_build_context *uint_bld = &bld_base->uint_bld;
-   struct lp_build_context *uint64_bld = &bld_base->uint64_bld;
LLVMValueRef ssbo_limit = NULL;
+   struct lp_build_context *load_bld;
+   uint32_t shift_val = bit_size_to_shift_size(bit_size);
+
+   load_bld = get_int_bld(bld_base, true, bit_size);
 
if (index) {
   LLVMValueRef ssbo_size_ptr = lp_build_array_get(gallivm, 
bld->ssbo_sizes_ptr, LLVMBuildExtractElement(builder, index, 
lp_build_const_int32(gallivm, 0), ""));
-  ssbo_limit = LLVMBuildAShr(gallivm->builder, ssbo_size_ptr, 
lp_build_const_int32(gallivm, bit_size == 64 ? 3 : 2), "");
+  ssbo_limit = LLVMBuildAShr(gallivm->builder, ssbo_size_ptr, 
lp_build_const_int32(gallivm, shift_val), "");
   ssbo_limit = lp_build_broadcast_scalar(uint_bld, ssbo_limit);
 
   ssbo_ptr = lp_build_array_get(gallivm, bld->ssbo_ptr, 
LLVMBuildExtractElement(builder, index, lp_build_const_int32(gallivm, 0), ""));
} else
   ssbo_ptr = bld->shared_ptr;
 
-   offset = LLVMBuildAShr(gallivm->builder, offset, 
lp_build_const_int_vec(gallivm, uint_bld->type, bit_size == 64 ? 3 : 2), "");
+   offset = LLVMBuildAShr(gallivm->builder, offset, 
lp_build_const_int_vec(gallivm, uint_bld->type, shift_val), "");
for (unsigned c = 0; c < nc; c++) {
   LLVMValueRef loop_index = lp_build_add(uint_bld, offset, 
lp_build_const_int_vec(gallivm, uint_bld->type, c));
   LLVMValueRef exec_mask = mask_vec(bld_base);
@@ -1015,7 +1024,7 @@ static void emit_load_mem(struct lp_build_nir_context 
*bld_base,
  exec_mask = LLVMBuildAnd(builder, exec_mask, ssbo_oob_cmp, "");
   }
 
-  LLVMValueRef result = lp_build_alloca(gallivm, bit_size == 64 ? 
uint64_bld->vec_type : uint_bld->vec_type, "");
+  LLVMValueRef result = lp_build_alloca(gallivm, load_bld->vec_type, "");
   struct lp_build_loop_state loop_state;
   lp_build_loop_begin(&loop_state, gallivm, lp_build_const_int32(gallivm, 
0));
 
@@ -1030,8 +1039,8 @@ static void emit_load_mem(struct lp_build_nir_context 
*bld_base,
 
   lp_build_if(&ifthen, gallivm, cond);
   LLVMValueRef scalar;
-  if (bit_size == 64) {
- LLVMV