Mesa (master): radeonsi: add new polaris12 pci id
Module: Mesa Branch: master Commit: 5c603b902bb6cd186e0d1b8f19d7496545bca667 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5c603b902bb6cd186e0d1b8f19d7496545bca667 Author: Alex Deucher Date: Fri Jun 16 12:12:21 2017 -0400 radeonsi: add new polaris12 pci id Reviewed-by: Marek Olšák Signed-off-by: Alex Deucher Cc: 17.0 17.1 --- include/pci_ids/radeonsi_pci_ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index 50f638f582..9453c1c391 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -213,6 +213,7 @@ CHIPSET(0x6985, POLARIS12_, POLARIS12) CHIPSET(0x6986, POLARIS12_, POLARIS12) CHIPSET(0x6987, POLARIS12_, POLARIS12) CHIPSET(0x6995, POLARIS12_, POLARIS12) +CHIPSET(0x6997, POLARIS12_, POLARIS12) CHIPSET(0x699F, POLARIS12_, POLARIS12) CHIPSET(0x6860, VEGA10_, VEGA10) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add new vega10 pci ids
Module: Mesa Branch: master Commit: 2f0450c627e5158d49aa1320eed9a5f6cb184838 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f0450c627e5158d49aa1320eed9a5f6cb184838 Author: Alex Deucher Date: Wed May 10 11:40:01 2017 -0400 radeonsi: add new vega10 pci ids Reviewed-by: Nicolai Hähnle Cc: 17.1 Signed-off-by: Alex Deucher --- include/pci_ids/radeonsi_pci_ids.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index 1058682c8e..a20a936ef3 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -219,6 +219,8 @@ CHIPSET(0x6860, VEGA10_, VEGA10) CHIPSET(0x6861, VEGA10_, VEGA10) CHIPSET(0x6862, VEGA10_, VEGA10) CHIPSET(0x6863, VEGA10_, VEGA10) +CHIPSET(0x6864, VEGA10_, VEGA10) CHIPSET(0x6867, VEGA10_, VEGA10) +CHIPSET(0x6868, VEGA10_, VEGA10) CHIPSET(0x687F, VEGA10_, VEGA10) CHIPSET(0x686C, VEGA10_, VEGA10) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add new polaris10 pci id
Module: Mesa Branch: master Commit: d921af62f5761b331039eee1497861b5826ecf82 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d921af62f5761b331039eee1497861b5826ecf82 Author: Alex Deucher Date: Wed Apr 5 09:40:53 2017 -0400 radeonsi: add new polaris10 pci id Reviewed-by: Christian König Cc: 13.0 17.0 Signed-off-by: Alex Deucher --- include/pci_ids/radeonsi_pci_ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index f4139ea754..1058682c8e 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -202,6 +202,7 @@ CHIPSET(0x67C9, POLARIS10_, POLARIS10) CHIPSET(0x67CA, POLARIS10_, POLARIS10) CHIPSET(0x67CC, POLARIS10_, POLARIS10) CHIPSET(0x67CF, POLARIS10_, POLARIS10) +CHIPSET(0x67D0, POLARIS10_, POLARIS10) CHIPSET(0x67DF, POLARIS10_, POLARIS10) CHIPSET(0x98E4, STONEY_, STONEY) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add new polaris12 pci id
Module: Mesa Branch: master Commit: c2a97fb7ae991fa52adfd1dabbebbe1803261863 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c2a97fb7ae991fa52adfd1dabbebbe1803261863 Author: Alex Deucher Date: Fri Mar 17 11:13:09 2017 -0400 radeonsi: add new polaris12 pci id Reviewed-by: Marek Olšák Cc: 17.0 Signed-off-by: Alex Deucher --- include/pci_ids/radeonsi_pci_ids.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index fca47b0e15..b14291d638 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -211,4 +211,5 @@ CHIPSET(0x6981, POLARIS12_, POLARIS12) CHIPSET(0x6985, POLARIS12_, POLARIS12) CHIPSET(0x6986, POLARIS12_, POLARIS12) CHIPSET(0x6987, POLARIS12_, POLARIS12) +CHIPSET(0x6995, POLARIS12_, POLARIS12) CHIPSET(0x699F, POLARIS12_, POLARIS12) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add Polaris12 PCI ID
Module: Mesa Branch: master Commit: 13ae47234a6c61448b1c4bcaaf2dc4269906c7cd URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=13ae47234a6c61448b1c4bcaaf2dc4269906c7cd Author: Junwei Zhang Date: Thu Aug 4 13:08:40 2016 +0800 radeonsi: add Polaris12 PCI ID Reviewed-by: Marek Olšák Signed-off-by: Junwei Zhang Reviewed-by: Nicolai Hähnle --- include/pci_ids/radeonsi_pci_ids.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index 20c1583..fca47b0 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -205,3 +205,10 @@ CHIPSET(0x67CF, POLARIS10_, POLARIS10) CHIPSET(0x67DF, POLARIS10_, POLARIS10) CHIPSET(0x98E4, STONEY_, STONEY) + +CHIPSET(0x6980, POLARIS12_, POLARIS12) +CHIPSET(0x6981, POLARIS12_, POLARIS12) +CHIPSET(0x6985, POLARIS12_, POLARIS12) +CHIPSET(0x6986, POLARIS12_, POLARIS12) +CHIPSET(0x6987, POLARIS12_, POLARIS12) +CHIPSET(0x699F, POLARIS12_, POLARIS12) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add Polaris12 support (v3)
Module: Mesa
Branch: master
Commit: 018ead42d7d58517976e37f80f5de4a677cd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=018ead42d7d58517976e37f80f5de4a677cd
Author: Junwei Zhang
Date: Mon Dec 19 13:51:25 2016 -0500
radeonsi: add Polaris12 support (v3)
v2: use gfxip names for llvm 4.0+
v3: use tonga for llvm <= 3.8, drop gfxip name,
we can just change that we change the other asics.
Reviewed-by: Marek Olšák
Signed-off-by: Junwei Zhang
Reviewed-by: Nicolai Hähnle
Acked-by: Christian König
---
src/amd/addrlib/r800/ciaddrlib.cpp| 3 ++-
src/amd/addrlib/r800/ciaddrlib.h | 1 +
src/amd/common/amd_family.h | 1 +
src/amd/common/amdgpu_id.h| 4
src/gallium/drivers/radeon/r600_pipe_common.c | 3 +++
src/gallium/drivers/radeon/radeon_vce.c | 3 ++-
src/gallium/drivers/radeonsi/si_pipe.c| 1 +
src/gallium/drivers/radeonsi/si_state.c | 1 +
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 4
9 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/src/amd/addrlib/r800/ciaddrlib.cpp
b/src/amd/addrlib/r800/ciaddrlib.cpp
index 7c5d29a..c726c4d 100644
--- a/src/amd/addrlib/r800/ciaddrlib.cpp
+++ b/src/amd/addrlib/r800/ciaddrlib.cpp
@@ -353,6 +353,7 @@ AddrChipFamily CIAddrLib::HwlConvertChipFamily(
m_settings.isFiji= ASICREV_IS_FIJI_P(uChipRevision);
m_settings.isPolaris10 =
ASICREV_IS_POLARIS10_P(uChipRevision);
m_settings.isPolaris11 =
ASICREV_IS_POLARIS11_M(uChipRevision);
+m_settings.isPolaris12 =
ASICREV_IS_POLARIS12_V(uChipRevision);
break;
case FAMILY_CZ:
m_settings.isCarrizo = 1;
@@ -417,7 +418,7 @@ BOOL_32 CIAddrLib::HwlInitGlobalParams(
{
m_pipes = 16;
}
-else if (m_settings.isPolaris11)
+else if (m_settings.isPolaris11 || m_settings.isPolaris12)
{
m_pipes = 4;
}
diff --git a/src/amd/addrlib/r800/ciaddrlib.h b/src/amd/addrlib/r800/ciaddrlib.h
index de995fa..2c9a4cc 100644
--- a/src/amd/addrlib/r800/ciaddrlib.h
+++ b/src/amd/addrlib/r800/ciaddrlib.h
@@ -62,6 +62,7 @@ struct CIChipSettings
UINT_32 isFiji: 1;
UINT_32 isPolaris10 : 1;
UINT_32 isPolaris11 : 1;
+UINT_32 isPolaris12 : 1;
// VI fusion (Carrizo)
UINT_32 isCarrizo : 1;
};
diff --git a/src/amd/common/amd_family.h b/src/amd/common/amd_family.h
index 6a713ad..b09bbb8 100644
--- a/src/amd/common/amd_family.h
+++ b/src/amd/common/amd_family.h
@@ -91,6 +91,7 @@ enum radeon_family {
CHIP_STONEY,
CHIP_POLARIS10,
CHIP_POLARIS11,
+CHIP_POLARIS12,
CHIP_LAST,
};
diff --git a/src/amd/common/amdgpu_id.h b/src/amd/common/amdgpu_id.h
index f91df55..1683a5a 100644
--- a/src/amd/common/amdgpu_id.h
+++ b/src/amd/common/amdgpu_id.h
@@ -142,6 +142,8 @@ enum {
VI_POLARIS11_M_A0 = 90,
+ VI_POLARIS12_V_A0 = 100,
+
VI_UNKNOWN= 0xFF
};
@@ -156,6 +158,8 @@ enum {
((eChipRev >= VI_POLARIS10_P_A0) && (eChipRev < VI_POLARIS11_M_A0))
#define ASICREV_IS_POLARIS11_M(eChipRev) \
(eChipRev >= VI_POLARIS11_M_A0)
+#define ASICREV_IS_POLARIS12_V(eChipRev)\
+ (eChipRev >= VI_POLARIS12_V_A0)
/* CZ specific rev IDs */
enum {
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 0b5c6dc..e0b914c 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -755,6 +755,7 @@ static const char* r600_get_chip_name(struct
r600_common_screen *rscreen)
case CHIP_FIJI: return "AMD FIJI";
case CHIP_POLARIS10: return "AMD POLARIS10";
case CHIP_POLARIS11: return "AMD POLARIS11";
+ case CHIP_POLARIS12: return "AMD POLARIS12";
case CHIP_STONEY: return "AMD STONEY";
default: return "AMD unknown";
}
@@ -889,9 +890,11 @@ const char *r600_get_llvm_processor_name(enum
radeon_family family)
#if HAVE_LLVM <= 0x0308
case CHIP_POLARIS10: return "tonga";
case CHIP_POLARIS11: return "tonga";
+ case CHIP_POLARIS12: return "tonga";
#else
case CHIP_POLARIS10: return "polaris10";
case CHIP_POLARIS11: return "polaris11";
+ case CHIP_POLARIS12: return "polaris11";
#endif
default: return "";
}
diff --git a/src/gallium/drivers/radeon/radeon_vce.c
b/src/gallium/drivers/radeon/radeon_vce.c
index aad2ec1..dcd56ea 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -413,7 +413,8 @@ struct pipe_video_codec *rvce_create_encoder(struct
pipe_context *context,
enc->use_vui = true;
if (rscreen->info.family >= CHIP_TONGA &&
rscreen->info.family != CHIP_STONEY &&
- rscreen->info.family != CHIP_POLARIS11)
+ rscreen->info.f
Mesa (master): radeonsi: fix the raster config setup for 1 RB iceland chips
Module: Mesa Branch: master Commit: bd85e4a041c13c0c8a6a9abc7d15d1ceede42cea URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd85e4a041c13c0c8a6a9abc7d15d1ceede42cea Author: Alex Deucher Date: Mon May 23 15:53:56 2016 -0400 radeonsi: fix the raster config setup for 1 RB iceland chips I didn't realize there were 1 and 2 RB variants when this code was originally added. Reviewed-by: Marek Olšák Signed-off-by: Alex Deucher Cc: 11.1 11.2 12.0 --- src/gallium/drivers/radeonsi/si_state.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 5bf87a8..58cbac4 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3712,7 +3712,10 @@ static void si_init_config(struct si_context *sctx) raster_config_1 = 0x002a; break; case CHIP_ICELAND: - raster_config = 0x0002; + if (num_rb == 1) + raster_config = 0x; + else + raster_config = 0x0002; raster_config_1 = 0x; break; case CHIP_CARRIZO: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add new polaris11 pci ids
Module: Mesa Branch: master Commit: 86f51d7958ab56e358da942ae46a04e305c78436 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=86f51d7958ab56e358da942ae46a04e305c78436 Author: Alex Deucher Date: Tue May 17 17:10:50 2016 -0400 radeonsi: add new polaris11 pci ids Reviewed-by: Nicolai Hähnle Signed-off-by: Alex Deucher --- include/pci_ids/radeonsi_pci_ids.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index 94e4fac..20c1583 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -184,9 +184,12 @@ CHIPSET(0x7300, FIJI_, FIJI) CHIPSET(0x67E0, POLARIS11_, POLARIS11) CHIPSET(0x67E1, POLARIS11_, POLARIS11) +CHIPSET(0x67E3, POLARIS11_, POLARIS11) +CHIPSET(0x67E7, POLARIS11_, POLARIS11) CHIPSET(0x67E8, POLARIS11_, POLARIS11) CHIPSET(0x67E9, POLARIS11_, POLARIS11) CHIPSET(0x67EB, POLARIS11_, POLARIS11) +CHIPSET(0x67EF, POLARIS11_, POLARIS11) CHIPSET(0x67FF, POLARIS11_, POLARIS11) CHIPSET(0x67C0, POLARIS10_, POLARIS10) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add new polaris10 pci ids
Module: Mesa Branch: master Commit: 768320b4979b2f8edff8039e5414f139013adb1d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=768320b4979b2f8edff8039e5414f139013adb1d Author: Alex Deucher Date: Tue May 17 17:06:26 2016 -0400 radeonsi: add new polaris10 pci ids Reviewed-by: Nicolai Hähnle Signed-off-by: Alex Deucher --- include/pci_ids/radeonsi_pci_ids.h | 9 + 1 file changed, 9 insertions(+) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index 4df8e9d..94e4fac 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -190,6 +190,15 @@ CHIPSET(0x67EB, POLARIS11_, POLARIS11) CHIPSET(0x67FF, POLARIS11_, POLARIS11) CHIPSET(0x67C0, POLARIS10_, POLARIS10) +CHIPSET(0x67C1, POLARIS10_, POLARIS10) +CHIPSET(0x67C2, POLARIS10_, POLARIS10) +CHIPSET(0x67C4, POLARIS10_, POLARIS10) +CHIPSET(0x67C7, POLARIS10_, POLARIS10) +CHIPSET(0x67C8, POLARIS10_, POLARIS10) +CHIPSET(0x67C9, POLARIS10_, POLARIS10) +CHIPSET(0x67CA, POLARIS10_, POLARIS10) +CHIPSET(0x67CC, POLARIS10_, POLARIS10) +CHIPSET(0x67CF, POLARIS10_, POLARIS10) CHIPSET(0x67DF, POLARIS10_, POLARIS10) CHIPSET(0x98E4, STONEY_, STONEY) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add support for Polaris (v2)
Module: Mesa
Branch: master
Commit: 42e442d888ce2d3dcb95350d17c298791f5d76cc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=42e442d888ce2d3dcb95350d17c298791f5d76cc
Author: Sonny Jiang
Date: Wed Nov 4 16:13:07 2015 -0500
radeonsi: add support for Polaris (v2)
v2: Polaris chips should be defined after Stoney
Signed-off-by: Sonny Jiang (v1)
Reviewed-by: Michel Dänzer (v1)
Signed-off-by: Leo Liu (v2 diff)
Reviewed-by: Alex Deucher (v2 diff)
---
src/gallium/drivers/radeon/r600_pipe_common.c | 9 +
src/gallium/drivers/radeon/radeon_winsys.h| 2 ++
src/gallium/drivers/radeonsi/si_pipe.c| 2 ++
src/gallium/drivers/radeonsi/si_state.c | 8
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 8
5 files changed, 29 insertions(+)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index eed9d83..720fc06 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -467,6 +467,8 @@ static const char* r600_get_chip_name(struct
r600_common_screen *rscreen)
case CHIP_ICELAND: return "AMD ICELAND";
case CHIP_CARRIZO: return "AMD CARRIZO";
case CHIP_FIJI: return "AMD FIJI";
+ case CHIP_POLARIS10: return "AMD POLARIS10";
+ case CHIP_POLARIS11: return "AMD POLARIS11";
case CHIP_STONEY: return "AMD STONEY";
default: return "AMD unknown";
}
@@ -598,6 +600,13 @@ const char *r600_get_llvm_processor_name(enum
radeon_family family)
case CHIP_FIJI: return "fiji";
case CHIP_STONEY: return "stoney";
#endif
+#if HAVE_LLVM <= 0x0308
+ case CHIP_POLARIS10: return "tonga";
+ case CHIP_POLARIS11: return "tonga";
+#else
+ case CHIP_POLARIS10: return "polaris10";
+ case CHIP_POLARIS11: return "polaris11";
+#endif
default: return "";
}
}
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index d35e963..baecca7 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -124,6 +124,8 @@ enum radeon_family {
CHIP_CARRIZO,
CHIP_FIJI,
CHIP_STONEY,
+CHIP_POLARIS10,
+CHIP_POLARIS11,
CHIP_LAST,
};
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index dd1103e..ed84dc2 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -598,6 +598,8 @@ static bool si_init_gs_info(struct si_screen *sscreen)
case CHIP_HAWAII:
case CHIP_TONGA:
case CHIP_FIJI:
+ case CHIP_POLARIS10:
+ case CHIP_POLARIS11:
sscreen->gs_table_depth = 32;
return true;
default:
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 1245f56..a2b0da9 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3946,6 +3946,14 @@ static void si_init_config(struct si_context *sctx)
raster_config_1 = 0x002e;
}
break;
+ case CHIP_POLARIS10:
+ raster_config = 0x1612;
+ raster_config_1 = 0x002a;
+ break;
+ case CHIP_POLARIS11:
+ raster_config = 0x1612;
+ raster_config_1 = 0x;
+ break;
case CHIP_TONGA:
raster_config = 0x1612;
raster_config_1 = 0x002a;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index 938b9c2..87d9a6a 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -237,6 +237,14 @@ static boolean do_winsys_init(struct amdgpu_winsys *ws,
int fd)
ws->family = FAMILY_VI;
ws->rev_id = VI_FIJI_P_A0;
break;
+ case CHIP_POLARIS10:
+ ws->family = FAMILY_VI;
+ ws->rev_id = VI_POLARIS10_P_A0;
+ break;
+ case CHIP_POLARIS11:
+ ws->family = FAMILY_VI;
+ ws->rev_id = VI_POLARIS11_M_A0;
+ break;
default:
fprintf(stderr, "amdgpu: Unknown family.\n");
goto fail;
___
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Mesa (master): radeonsi: add Polaris PCI IDs
Module: Mesa Branch: master Commit: f00c840578a70e479ffb99f6b64c73dc420179fa URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f00c840578a70e479ffb99f6b64c73dc420179fa Author: Sonny Jiang Date: Wed Nov 4 11:01:33 2015 -0500 radeonsi: add Polaris PCI IDs Signed-off-by: Sonny Jiang Reviewed-by: Alex Deucher (Polaris10) Reviewed-by: Michel Dänzer (Polaris11) --- include/pci_ids/radeonsi_pci_ids.h | 10 ++ 1 file changed, 10 insertions(+) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index bcf15a1..4df8e9d 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -182,4 +182,14 @@ CHIPSET(0x9877, CARRIZO_, CARRIZO) CHIPSET(0x7300, FIJI_, FIJI) +CHIPSET(0x67E0, POLARIS11_, POLARIS11) +CHIPSET(0x67E1, POLARIS11_, POLARIS11) +CHIPSET(0x67E8, POLARIS11_, POLARIS11) +CHIPSET(0x67E9, POLARIS11_, POLARIS11) +CHIPSET(0x67EB, POLARIS11_, POLARIS11) +CHIPSET(0x67FF, POLARIS11_, POLARIS11) + +CHIPSET(0x67C0, POLARIS10_, POLARIS10) +CHIPSET(0x67DF, POLARIS10_, POLARIS10) + CHIPSET(0x98E4, STONEY_, STONEY) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeon/vce: add Polaris11 VCE firmware support
Module: Mesa Branch: master Commit: 0c5477465f08502fd81783ce17c449330537eb00 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c5477465f08502fd81783ce17c449330537eb00 Author: Sonny Jiang Date: Tue Dec 15 15:16:29 2015 -0500 radeon/vce: add Polaris11 VCE firmware support Signed-off-by: Sonny Jiang --- src/gallium/drivers/radeon/radeon_vce.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/gallium/drivers/radeon/radeon_vce.c b/src/gallium/drivers/radeon/radeon_vce.c index 2ab74e9..6584393 100644 --- a/src/gallium/drivers/radeon/radeon_vce.c +++ b/src/gallium/drivers/radeon/radeon_vce.c @@ -50,6 +50,7 @@ #define FW_50_10_2 ((50 << 24) | (10 << 16) | (2 << 8)) #define FW_50_17_3 ((50 << 24) | (17 << 16) | (3 << 8)) #define FW_52_0_3 ((52 << 24) | (0 << 16) | (3 << 8)) +#define FW_52_4_3 ((52 << 24) | (4 << 16) | (3 << 8)) /** * flush commands to the hardware @@ -482,6 +483,7 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context, break; case FW_52_0_3: + case FW_52_4_3: radeon_vce_52_init(enc); break; @@ -514,6 +516,7 @@ bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen) case FW_50_10_2: case FW_50_17_3: case FW_52_0_3: + case FW_52_4_3: return true; default: return false; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeon/vce: disable two pipe mode for Polaris11
Module: Mesa Branch: master Commit: f87ed903fb6fd1bdb0cfa7a4dd5b9d00a9f38e31 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f87ed903fb6fd1bdb0cfa7a4dd5b9d00a9f38e31 Author: Sonny Jiang Date: Tue Dec 15 15:33:40 2015 -0500 radeon/vce: disable two pipe mode for Polaris11 Signed-off-by: Sonny Jiang Reviewed-by: Leo Liu --- src/gallium/drivers/radeon/radeon_vce.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeon/radeon_vce.c b/src/gallium/drivers/radeon/radeon_vce.c index 6584393..99b82ca 100644 --- a/src/gallium/drivers/radeon/radeon_vce.c +++ b/src/gallium/drivers/radeon/radeon_vce.c @@ -409,7 +409,8 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context, rscreen->info.drm_major == 3) enc->use_vui = true; if (rscreen->info.family >= CHIP_TONGA && - rscreen->info.family != CHIP_STONEY) + rscreen->info.family != CHIP_STONEY && + rscreen->info.family != CHIP_POLARIS11) enc->dual_pipe = true; /* TODO enable B frame with dual instance */ if ((rscreen->info.family >= CHIP_TONGA) && ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): winsys/amdgpu: addrlib - add Polaris support (v2)
Module: Mesa
Branch: master
Commit: f5e24b19e883281452952ecce3e811cda1f7946c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5e24b19e883281452952ecce3e811cda1f7946c
Author: Sonny Jiang
Date: Tue Nov 3 11:46:38 2015 -0500
winsys/amdgpu: addrlib - add Polaris support (v2)
v2: fix indentation as noted by Michel
Signed-off-by: Sonny Jiang
Reviewed-by: Alex Deucher
Reviewed-by: Michel Dänzer
---
src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp | 8 +++-
src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h | 2 ++
src/gallium/winsys/amdgpu/drm/amdgpu_id.h| 10 +-
3 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp
b/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp
index 5702162..7c5d29a 100644
--- a/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp
+++ b/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.cpp
@@ -351,6 +351,8 @@ AddrChipFamily CIAddrLib::HwlConvertChipFamily(
m_settings.isIceland = ASICREV_IS_ICELAND_M(uChipRevision);
m_settings.isTonga = ASICREV_IS_TONGA_P(uChipRevision);
m_settings.isFiji= ASICREV_IS_FIJI_P(uChipRevision);
+m_settings.isPolaris10 =
ASICREV_IS_POLARIS10_P(uChipRevision);
+m_settings.isPolaris11 =
ASICREV_IS_POLARIS11_M(uChipRevision);
break;
case FAMILY_CZ:
m_settings.isCarrizo = 1;
@@ -403,7 +405,7 @@ BOOL_32 CIAddrLib::HwlInitGlobalParams(
// @todo: VI
// Move this to VI code path once created
-if (m_settings.isTonga)
+if (m_settings.isTonga || m_settings.isPolaris10)
{
m_pipes = 8;
}
@@ -415,6 +417,10 @@ BOOL_32 CIAddrLib::HwlInitGlobalParams(
{
m_pipes = 16;
}
+else if (m_settings.isPolaris11)
+{
+m_pipes = 4;
+}
if (valid)
{
diff --git a/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h
b/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h
index 4cbe970..de995fa 100644
--- a/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h
+++ b/src/gallium/winsys/amdgpu/drm/addrlib/r800/ciaddrlib.h
@@ -60,6 +60,8 @@ struct CIChipSettings
UINT_32 isIceland : 1;
UINT_32 isTonga : 1;
UINT_32 isFiji: 1;
+UINT_32 isPolaris10 : 1;
+UINT_32 isPolaris11 : 1;
// VI fusion (Carrizo)
UINT_32 isCarrizo : 1;
};
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_id.h
b/src/gallium/winsys/amdgpu/drm/amdgpu_id.h
index 90fe0cd..40b835c 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_id.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_id.h
@@ -138,6 +138,10 @@ enum {
VI_FIJI_P_A0 = 60,
+ VI_POLARIS10_P_A0 = 80,
+
+ VI_POLARIS11_M_A0 = 90,
+
VI_UNKNOWN= 0xFF
};
@@ -147,7 +151,11 @@ enum {
#define ASICREV_IS_TONGA_P(eChipRev) \
((eChipRev >= VI_TONGA_P_A0) && (eChipRev < VI_FIJI_P_A0))
#define ASICREV_IS_FIJI_P(eChipRev)\
- (eChipRev >= VI_FIJI_P_A0)
+ ((eChipRev >= VI_FIJI_P_A0) && (eChipRev < VI_POLARIS10_P_A0))
+#define ASICREV_IS_POLARIS10_P(eChipRev)\
+ ((eChipRev >= VI_POLARIS10_P_A0) && (eChipRev < VI_POLARIS11_M_A0))
+#define ASICREV_IS_POLARIS11_M(eChipRev) \
+ (eChipRev >= VI_POLARIS11_M_A0)
/* CZ specific rev IDs */
enum {
___
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Mesa (master): radeon/uvd: uv pitch separation for stoney
Module: Mesa
Branch: master
Commit: f55f134a033a61d67c2a71bbe57f85eb3484eec1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f55f134a033a61d67c2a71bbe57f85eb3484eec1
Author: Boyuan Zhang
Date: Thu Nov 12 18:01:16 2015 -0500
radeon/uvd: uv pitch separation for stoney
v2: set the behaviour default for future ASICs.
Signed-off-by: Boyuan Zhang
Reviewed-by: Leo Liu
Cc: mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/radeon/radeon_uvd.c |2 ++
src/gallium/drivers/radeon/radeon_uvd.h |5 -
2 files changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeon/radeon_uvd.c
b/src/gallium/drivers/radeon/radeon_uvd.c
index 0c643e5..6ea07be 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.c
+++ b/src/gallium/drivers/radeon/radeon_uvd.c
@@ -958,6 +958,8 @@ static void ruvd_end_frame(struct pipe_video_codec *decoder,
dec->msg->body.decode.db_pitch = dec->base.width;
dt = dec->set_dtb(dec->msg, (struct vl_video_buffer *)target);
+ if (((struct r600_common_screen*)dec->screen)->family >= CHIP_STONEY)
+ dec->msg->body.decode.dt_wa_chroma_top_offset =
dec->msg->body.decode.dt_pitch / 2;
switch (u_reduce_video_profile(picture->profile)) {
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
diff --git a/src/gallium/drivers/radeon/radeon_uvd.h
b/src/gallium/drivers/radeon/radeon_uvd.h
index 9cc0a69..88013bd 100644
--- a/src/gallium/drivers/radeon/radeon_uvd.h
+++ b/src/gallium/drivers/radeon/radeon_uvd.h
@@ -394,7 +394,10 @@ struct ruvd_msg {
uint32_tdt_chroma_top_offset;
uint32_tdt_chroma_bottom_offset;
uint32_tdt_surf_tile_config;
- uint32_tdt_reserved[3];
+ uint32_tdt_uv_surf_tile_config;
+ // re-use dt_wa_chroma_top_offset as dt_ext_info for UV
pitch in stoney
+ uint32_tdt_wa_chroma_top_offset;
+ uint32_tdt_wa_chroma_bottom_offset;
uint32_treserved[16];
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Mesa (master): radeonsi: enable optimal raster config setting for fiji (v2 )
Module: Mesa
Branch: master
Commit: 00f554abba8c0f3b65af94365c15109c3b858486
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=00f554abba8c0f3b65af94365c15109c3b858486
Author: Alex Deucher
Date: Fri Nov 13 13:00:30 2015 -0500
radeonsi: enable optimal raster config setting for fiji (v2)
Requires proper kernel tiling configuration so check the tiling
config registers.
v2: send the right version of the patch
Reviewed-by: Marek Olšák
Signed-off-by: Alex Deucher
Cc: mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/radeonsi/si_state.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index f0f87da..209b940 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3283,6 +3283,7 @@ si_write_harvested_raster_configs(struct si_context *sctx,
static void si_init_config(struct si_context *sctx)
{
+ struct si_screen *sscreen = sctx->screen;
unsigned num_rb = MIN2(sctx->screen->b.info.r600_num_backends, 16);
unsigned rb_mask = sctx->screen->b.info.si_backend_enabled_mask;
unsigned raster_config, raster_config_1;
@@ -3353,9 +3354,14 @@ static void si_init_config(struct si_context *sctx)
raster_config_1 = 0x002e;
break;
case CHIP_FIJI:
- /* Fiji should be same as Hawaii, but that causes corruption in
some cases */
- raster_config = 0x1612; /* 0x3a00161a */
- raster_config_1 = 0x002a; /* 0x002e */
+ if (sscreen->b.info.cik_macrotile_mode_array[0] == 0x00e8) {
+ /* old kernels with old tiling config */
+ raster_config = 0x1612;
+ raster_config_1 = 0x002a;
+ } else {
+ raster_config = 0x3a00161a;
+ raster_config_1 = 0x002e;
+ }
break;
case CHIP_TONGA:
raster_config = 0x1612;
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Mesa (master): radeonsi: use proper GRBM_GFX_INDEX offset for CI+
Module: Mesa Branch: master Commit: 5b37d8b50cfc9a390f8320557a332a3c75b91953 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5b37d8b50cfc9a390f8320557a332a3c75b91953 Author: Alex Deucher Date: Fri Nov 13 16:21:09 2015 -0500 radeonsi: use proper GRBM_GFX_INDEX offset for CI+ The offset is different on CI and newer. Reviewed-by: Marek Olšák Signed-off-by: Alex Deucher --- src/gallium/drivers/radeonsi/si_state.c | 16 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 93847d5..f0f87da 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3256,21 +3256,29 @@ si_write_harvested_raster_configs(struct si_context *sctx, } } - /* GRBM_GFX_INDEX is privileged on VI */ - if (sctx->b.chip_class <= CIK) + /* GRBM_GFX_INDEX has a different offset on SI and CI+ */ + if (sctx->b.chip_class < CIK) si_pm4_set_reg(pm4, GRBM_GFX_INDEX, SE_INDEX(se) | SH_BROADCAST_WRITES | INSTANCE_BROADCAST_WRITES); + else + si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX, + S_030800_SE_INDEX(se) | S_030800_SH_BROADCAST_WRITES(1) | + S_030800_INSTANCE_BROADCAST_WRITES(1)); si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, raster_config_se); if (sctx->b.chip_class >= CIK) si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, raster_config_1); } - /* GRBM_GFX_INDEX is privileged on VI */ - if (sctx->b.chip_class <= CIK) + /* GRBM_GFX_INDEX has a different offset on SI and CI+ */ + if (sctx->b.chip_class < CIK) si_pm4_set_reg(pm4, GRBM_GFX_INDEX, SE_BROADCAST_WRITES | SH_BROADCAST_WRITES | INSTANCE_BROADCAST_WRITES); + else + si_pm4_set_reg(pm4, R_030800_GRBM_GFX_INDEX, + S_030800_SE_BROADCAST_WRITES(1) | S_030800_SH_BROADCAST_WRITES(1) | + S_030800_INSTANCE_BROADCAST_WRITES(1)); } static void si_init_config(struct si_context *sctx) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add Stoney to si_init_gs_info()
Module: Mesa Branch: master Commit: 830e57b82d21fd324059b7a7074b047ad41d0aa4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=830e57b82d21fd324059b7a7074b047ad41d0aa4 Author: Alex Deucher Date: Fri Oct 23 18:31:57 2015 -0400 radeonsi: add Stoney to si_init_gs_info() This patch was originally written before stoney support was merged. Add stoney. Reviewed-by: Marek Olšák Signed-off-by: Alex Deucher --- src/gallium/drivers/radeonsi/si_pipe.c |1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index e653799..047bbf4 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -586,6 +586,7 @@ static bool si_init_gs_info(struct si_screen *sscreen) case CHIP_MULLINS: case CHIP_ICELAND: case CHIP_CARRIZO: + case CHIP_STONEY: sscreen->gs_table_depth = 16; return true; case CHIP_TAHITI: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add support for Stoney asics (v3)
Module: Mesa
Branch: master
Commit: bf0d0ce0d57dce5df8195942d2eda6389d341fea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf0d0ce0d57dce5df8195942d2eda6389d341fea
Author: Samuel Li
Date: Fri Aug 21 15:35:46 2015 -0400
radeonsi: add support for Stoney asics (v3)
v2 (agd): rebase on mesa master, split pci ids to
separate commit
v3 (agd): use carrizo for llvm processor name for
llvm 3.7 and older
Reviewed-by: Marek Olšák
Signed-off-by: Samuel Li
Cc: mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/radeon/r600_pipe_common.c |6 ++
src/gallium/drivers/radeon/radeon_winsys.h|1 +
src/gallium/drivers/radeonsi/si_state.c |1 +
src/gallium/winsys/amdgpu/drm/amdgpu_id.h |8 ++--
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c |6 +-
5 files changed, 19 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 7ac94ca..4ce0c6a 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -416,6 +416,7 @@ static const char* r600_get_chip_name(struct
r600_common_screen *rscreen)
case CHIP_ICELAND: return "AMD ICELAND";
case CHIP_CARRIZO: return "AMD CARRIZO";
case CHIP_FIJI: return "AMD FIJI";
+ case CHIP_STONEY: return "AMD STONEY";
default: return "AMD unknown";
}
}
@@ -540,6 +541,11 @@ const char *r600_get_llvm_processor_name(enum
radeon_family family)
case CHIP_ICELAND: return "iceland";
case CHIP_CARRIZO: return "carrizo";
case CHIP_FIJI: return "fiji";
+#if HAVE_LLVM <= 0x0307
+ case CHIP_STONEY: return "carrizo";
+#else
+ case CHIP_STONEY: return "stoney";
+#endif
default: return "";
}
}
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index b91e1ad..5f13c1e 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -137,6 +137,7 @@ enum radeon_family {
CHIP_ICELAND,
CHIP_CARRIZO,
CHIP_FIJI,
+CHIP_STONEY,
CHIP_LAST,
};
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 243bdc6..a71ff49 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3336,6 +3336,7 @@ static void si_init_config(struct si_context *sctx)
break;
case CHIP_KABINI:
case CHIP_MULLINS:
+ case CHIP_STONEY:
raster_config = 0x;
raster_config_1 = 0x;
break;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_id.h
b/src/gallium/winsys/amdgpu/drm/amdgpu_id.h
index 8882c41..90fe0cd 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_id.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_id.h
@@ -151,11 +151,15 @@ enum {
/* CZ specific rev IDs */
enum {
- CZ_CARRIZO_A0 = 0x01,
+ CARRIZO_A0 = 0x01,
+STONEY_A0= 0x61,
CZ_UNKNOWN = 0xFF
};
#define ASICREV_IS_CARRIZO(eChipRev) \
- (eChipRev >= CARRIZO_A0)
+ ((eChipRev >= CARRIZO_A0) && (eChipRev < STONEY_A0))
+
+#define ASICREV_IS_STONEY(eChipRev) \
+ ((eChipRev >= STONEY_A0) && (eChipRev < CZ_UNKNOWN))
#endif /* AMDGPU_ID_H */
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
index c877249..32cd9d9 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
@@ -226,7 +226,11 @@ static boolean do_winsys_init(struct amdgpu_winsys *ws)
break;
case CHIP_CARRIZO:
ws->family = FAMILY_CZ;
- ws->rev_id = CZ_CARRIZO_A0;
+ ws->rev_id = CARRIZO_A0;
+ break;
+ case CHIP_STONEY:
+ ws->family = FAMILY_CZ;
+ ws->rev_id = STONEY_A0;
break;
case CHIP_FIJI:
ws->family = FAMILY_VI;
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Mesa (master): radeonsi: add Stoney pci ids
Module: Mesa Branch: master Commit: 98546bfd038bc07a8cc7fed259c5022486bba473 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=98546bfd038bc07a8cc7fed259c5022486bba473 Author: Samuel Li Date: Thu Oct 22 12:06:43 2015 -0400 radeonsi: add Stoney pci ids Reviewed-by: Marek Olšák Reviewed-by: Michel Dänzer Signed-off-by: Samuel Li Cc: mesa-sta...@lists.freedesktop.org --- include/pci_ids/radeonsi_pci_ids.h |2 ++ 1 file changed, 2 insertions(+) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index 52eada1..bcf15a1 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -181,3 +181,5 @@ CHIPSET(0x9876, CARRIZO_, CARRIZO) CHIPSET(0x9877, CARRIZO_, CARRIZO) CHIPSET(0x7300, FIJI_, FIJI) + +CHIPSET(0x98E4, STONEY_, STONEY) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeon/uvd: don't expose HEVC on old UVD hw (v3)
Module: Mesa
Branch: master
Commit: 7b636581253fe858ac883e3d3eec21173ac069d4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b636581253fe858ac883e3d3eec21173ac069d4
Author: Alex Deucher
Date: Thu Oct 22 12:24:42 2015 -0400
radeon/uvd: don't expose HEVC on old UVD hw (v3)
The section for UVD 2 and older was not updated
when HEVC support was added. Reported by Kano
on irc.
v2: integrate the UVD2 and older checks into the
main switch statement.
v3: handle encode checking as well. Encode is
already checked in the top case statement, so
drop encode checks in the lower case statement.
Reviewed-by: Christian König
Signed-off-by: Alex Deucher
Cc: mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/radeon/radeon_video.c | 50 +++--
1 file changed, 18 insertions(+), 32 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_video.c
b/src/gallium/drivers/radeon/radeon_video.c
index 3a1834b..32bfc32 100644
--- a/src/gallium/drivers/radeon/radeon_video.c
+++ b/src/gallium/drivers/radeon/radeon_video.c
@@ -205,11 +205,12 @@ int rvid_get_video_param(struct pipe_screen *screen,
enum pipe_video_cap param)
{
struct r600_common_screen *rscreen = (struct r600_common_screen
*)screen;
+ enum pipe_video_format codec = u_reduce_video_profile(profile);
if (entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
switch (param) {
case PIPE_VIDEO_CAP_SUPPORTED:
- return u_reduce_video_profile(profile) ==
PIPE_VIDEO_FORMAT_MPEG4_AVC &&
+ return codec == PIPE_VIDEO_FORMAT_MPEG4_AVC &&
rvce_is_fw_version_supported(rscreen);
case PIPE_VIDEO_CAP_NPOT_TEXTURES:
return 1;
@@ -232,38 +233,19 @@ int rvid_get_video_param(struct pipe_screen *screen,
}
}
- /* UVD 2.x limits */
- if (rscreen->family < CHIP_PALM) {
- enum pipe_video_format codec = u_reduce_video_profile(profile);
- switch (param) {
- case PIPE_VIDEO_CAP_SUPPORTED:
- /* no support for MPEG4 */
- return codec != PIPE_VIDEO_FORMAT_MPEG4 &&
- /* FIXME: VC-1 simple/main profile is broken */
- profile != PIPE_VIDEO_PROFILE_VC1_SIMPLE &&
- profile != PIPE_VIDEO_PROFILE_VC1_MAIN;
- case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
- case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
- /* MPEG2 only with shaders and no support for
- interlacing on R6xx style UVD */
- return codec != PIPE_VIDEO_FORMAT_MPEG12 &&
- rscreen->family > CHIP_RV770;
- default:
- break;
- }
- }
-
switch (param) {
case PIPE_VIDEO_CAP_SUPPORTED:
- switch (u_reduce_video_profile(profile)) {
+ switch (codec) {
case PIPE_VIDEO_FORMAT_MPEG12:
case PIPE_VIDEO_FORMAT_MPEG4:
case PIPE_VIDEO_FORMAT_MPEG4_AVC:
- return entrypoint != PIPE_VIDEO_ENTRYPOINT_ENCODE;
+ if (rscreen->family < CHIP_PALM)
+ /* no support for MPEG4 */
+ return codec != PIPE_VIDEO_FORMAT_MPEG4;
+ return true;
case PIPE_VIDEO_FORMAT_VC1:
/* FIXME: VC-1 simple/main profile is broken */
- return profile == PIPE_VIDEO_PROFILE_VC1_ADVANCED &&
- entrypoint != PIPE_VIDEO_ENTRYPOINT_ENCODE;
+ return profile == PIPE_VIDEO_PROFILE_VC1_ADVANCED;
case PIPE_VIDEO_FORMAT_HEVC:
/* Carrizo only supports HEVC Main */
return rscreen->family >= CHIP_CARRIZO &&
@@ -280,13 +262,17 @@ int rvid_get_video_param(struct pipe_screen *screen,
case PIPE_VIDEO_CAP_PREFERED_FORMAT:
return PIPE_FORMAT_NV12;
case PIPE_VIDEO_CAP_PREFERS_INTERLACED:
- if (u_reduce_video_profile(profile) == PIPE_VIDEO_FORMAT_HEVC)
- return false; //The hardware doesn't support interlaced
HEVC.
- return true;
case PIPE_VIDEO_CAP_SUPPORTS_INTERLACED:
- if (u_reduce_video_profile(profile) == PIPE_VIDEO_FORMAT_HEVC)
- return false; //The hardware doesn't support interlaced
HEVC.
- return true;
+ if (rscreen->family < CHIP_PALM) {
+ /* MPEG2 only with shaders and no support for
+
Mesa (master): radeonsi: add new OLAND pci id
Module: Mesa Branch: master Commit: 87cea61b9e2681e5365e989c7fa7a0298e4005fa URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=87cea61b9e2681e5365e989c7fa7a0298e4005fa Author: Alex Deucher Date: Mon Aug 10 15:35:21 2015 -0400 radeonsi: add new OLAND pci id Reviewed-by: Edward O'Callaghan Reviewed-by: Michel Dänzer Signed-off-by: Alex Deucher Cc: mesa-sta...@lists.freedesktop.org --- include/pci_ids/radeonsi_pci_ids.h |1 + 1 file changed, 1 insertion(+) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index cd5da99..f451b7d 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -63,6 +63,7 @@ CHIPSET(0x6608, OLAND_6608, OLAND) CHIPSET(0x6610, OLAND_6610, OLAND) CHIPSET(0x6611, OLAND_6611, OLAND) CHIPSET(0x6613, OLAND_6613, OLAND) +CHIPSET(0x6617, OLAND_6617, OLAND) CHIPSET(0x6620, OLAND_6620, OLAND) CHIPSET(0x6621, OLAND_6621, OLAND) CHIPSET(0x6623, OLAND_6623, OLAND) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (amdgpu): radeonsi: properly handler raster_config setup on CZ
Module: Mesa Branch: amdgpu Commit: a0f1d85f9984b5da83595b5f73ca2ab2f1917c8d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0f1d85f9984b5da83595b5f73ca2ab2f1917c8d Author: Alex Deucher Date: Wed Jun 10 11:43:24 2015 -0400 radeonsi: properly handler raster_config setup on CZ Need to take into account the number of RBs. Reviewed-by: Marek Olšák Signed-off-by: Alex Deucher --- src/gallium/drivers/radeonsi/si_state.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index b3e77ec..f3c90e2 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3093,10 +3093,10 @@ void si_init_config(struct si_context *sctx) si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x002a); break; case CHIP_ICELAND: - case CHIP_CARRIZO: si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0002); si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x); break; + case CHIP_CARRIZO: case CHIP_KAVERI: if (num_rb > 1) si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0002); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (amdgpu): radeonsi: properly set the raster_config for KV
Module: Mesa
Branch: amdgpu
Commit: 0d60a4fb3a41817346a18f56acecdff566effed5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d60a4fb3a41817346a18f56acecdff566effed5
Author: Alex Deucher
Date: Wed Jun 10 11:39:30 2015 -0400
radeonsi: properly set the raster_config for KV
This enables the second RB on asics that support it which
should boost performance.
Reviewed-by: Marek Olšák
Signed-off-by: Alex Deucher
Cc: mesa-sta...@lists.freedesktop.org
---
src/gallium/drivers/radeonsi/si_state.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index b35fbd5..b3e77ec 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3040,6 +3040,7 @@ si_write_harvested_raster_configs(struct si_context *sctx,
void si_init_config(struct si_context *sctx)
{
+ unsigned num_rb = sctx->screen->b.info.r600_num_backends;
struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
if (pm4 == NULL)
@@ -3097,14 +3098,17 @@ void si_init_config(struct si_context *sctx)
si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
0x);
break;
case CHIP_KAVERI:
- /* XXX todo */
+ if (num_rb > 1)
+ si_pm4_set_reg(pm4,
R_028350_PA_SC_RASTER_CONFIG, 0x0002);
+ else
+ si_pm4_set_reg(pm4,
R_028350_PA_SC_RASTER_CONFIG, 0x);
+ si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
0x);
+ break;
case CHIP_KABINI:
- /* XXX todo */
case CHIP_MULLINS:
- /* XXX todo */
default:
- si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0);
- si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0);
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
0x);
+ si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
0x);
break;
}
} else {
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Mesa (amdgpu): radeon/vce: move CPB handling function into common code
Module: Mesa
Branch: amdgpu
Commit: 2f2a2a87a6f4f7951ba01ac7cd3c5d15d9881e8b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f2a2a87a6f4f7951ba01ac7cd3c5d15d9881e8b
Author: Christian König
Date: Thu Mar 26 09:52:37 2015 +0100
radeon/vce: move CPB handling function into common code
They are not firmware version dependent.
Signed-off-by: Christian König
---
src/gallium/drivers/radeon/radeon_vce.c| 38
src/gallium/drivers/radeon/radeon_vce.h|7 +
src/gallium/drivers/radeon/radeon_vce_40_2_2.c | 32 ++--
3 files changed, 48 insertions(+), 29 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_vce.c
b/src/gallium/drivers/radeon/radeon_vce.c
index 6bd9b31..740134d 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -183,6 +183,44 @@ static unsigned get_cpb_num(struct rvce_encoder *enc)
}
/**
+ * Get the slot for the currently encoded frame
+ */
+struct rvce_cpb_slot *current_slot(struct rvce_encoder *enc)
+{
+ return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.prev, list);
+}
+
+/**
+ * Get the slot for L0
+ */
+struct rvce_cpb_slot *l0_slot(struct rvce_encoder *enc)
+{
+ return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next, list);
+}
+
+/**
+ * Get the slot for L1
+ */
+struct rvce_cpb_slot *l1_slot(struct rvce_encoder *enc)
+{
+ return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next->next,
list);
+}
+
+/**
+ * Calculate the offsets into the CPB
+ */
+void rvce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
+ unsigned *luma_offset, unsigned *chroma_offset)
+{
+ unsigned pitch = align(enc->luma->level[0].pitch_bytes, 128);
+ unsigned vpitch = align(enc->luma->npix_y, 16);
+ unsigned fsize = pitch * (vpitch + vpitch / 2);
+
+ *luma_offset = slot->index * fsize;
+ *chroma_offset = *luma_offset + pitch * vpitch;
+}
+
+/**
* destroy this video encoder
*/
static void rvce_destroy(struct pipe_video_codec *encoder)
diff --git a/src/gallium/drivers/radeon/radeon_vce.h
b/src/gallium/drivers/radeon/radeon_vce.h
index 4d07204..77a56d5 100644
--- a/src/gallium/drivers/radeon/radeon_vce.h
+++ b/src/gallium/drivers/radeon/radeon_vce.h
@@ -108,6 +108,13 @@ struct rvce_encoder {
booluse_2p;
};
+/* CPB handling functions */
+struct rvce_cpb_slot *current_slot(struct rvce_encoder *enc);
+struct rvce_cpb_slot *l0_slot(struct rvce_encoder *enc);
+struct rvce_cpb_slot *l1_slot(struct rvce_encoder *enc);
+void rvce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
+ unsigned *luma_offset, unsigned *chroma_offset);
+
struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
const struct pipe_video_codec
*templat,
struct radeon_winsys* ws,
diff --git a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
index 970d572..234b2eb 100644
--- a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
+++ b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
@@ -48,32 +48,6 @@
static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
-static struct rvce_cpb_slot *current_slot(struct rvce_encoder *enc)
-{
- return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.prev, list);
-}
-
-static struct rvce_cpb_slot *l0_slot(struct rvce_encoder *enc)
-{
- return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next, list);
-}
-
-static struct rvce_cpb_slot *l1_slot(struct rvce_encoder *enc)
-{
- return LIST_ENTRY(struct rvce_cpb_slot, enc->cpb_slots.next->next,
list);
-}
-
-static void frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
-unsigned *luma_offset, unsigned *chroma_offset)
-{
- unsigned pitch = align(enc->luma->level[0].pitch_bytes, 128);
- unsigned vpitch = align(enc->luma->npix_y, 16);
- unsigned fsize = pitch * (vpitch + vpitch / 2);
-
- *luma_offset = slot->index * fsize;
- *chroma_offset = *luma_offset + pitch * vpitch;
-}
-
static void session(struct rvce_encoder *enc)
{
RVCE_BEGIN(0x0001); // session cmd
@@ -392,7 +366,7 @@ static void encode(struct rvce_encoder *enc)
if(enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P ||
enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B) {
struct rvce_cpb_slot *l0 = l0_slot(enc);
- frame_offset(enc, l0, &luma_offset, &chroma_offset);
+ rvce_frame_offset(enc, l0, &luma_offset, &chroma_offset);
RVCE_CS(l0->picture_type); // encPicType
RVCE_CS(l0->frame_num); // frameNumber
RVCE_CS(l0->pic_order_cnt); // pictureOrderCount
@@ -418,7 +392,7 @@ static void encode(struct rvce_encoder *enc)
Mesa (amdgpu): winsys/amdgpu: don't use VRAM with APUs that don' t have much of it
Module: Mesa
Branch: amdgpu
Commit: 2b2d18c64303df46b4df74336aba2b7e58d522a0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b2d18c64303df46b4df74336aba2b7e58d522a0
Author: Marek Olšák
Date: Fri Jun 5 15:57:03 2015 +0200
winsys/amdgpu: don't use VRAM with APUs that don't have much of it
Reviewed-by: Alex Deucher
Reviewed-by: Michel Dänzer
---
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 10 ++
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c |6 +-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 02e0c07..5b09b16 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -484,6 +484,16 @@ amdgpu_bo_create(struct radeon_winsys *rws,
struct pb_manager *provider;
struct pb_buffer *buffer;
+ /* Don't use VRAM if the GPU doesn't have much. This is only the initial
+* domain. The kernel is free to move the buffer if it wants to.
+*
+* 64MB means no VRAM by todays standards.
+*/
+ if (domain & RADEON_DOMAIN_VRAM && ws->info.vram_size <= 64*1024*1024) {
+ domain = RADEON_DOMAIN_GTT;
+ flags = RADEON_FLAG_GTT_WC;
+ }
+
memset(&desc, 0, sizeof(desc));
desc.base.alignment = alignment;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 6e15f83..8aafc45 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -424,10 +424,14 @@ static unsigned amdgpu_cs_add_reloc(struct
radeon_winsys_cs *rcs,
enum radeon_bo_domain domains,
enum radeon_bo_priority priority)
{
+ /* Don't use the "domains" parameter. Amdgpu doesn't support changing
+* the buffer placement during command submission.
+*/
struct amdgpu_cs *cs = amdgpu_cs(rcs);
struct amdgpu_winsys_bo *bo = (struct amdgpu_winsys_bo*)buf;
enum radeon_bo_domain added_domains;
- unsigned index = amdgpu_add_reloc(cs, bo, usage, domains, priority,
&added_domains);
+ unsigned index = amdgpu_add_reloc(cs, bo, usage, bo->initial_domain,
+ priority, &added_domains);
if (added_domains & RADEON_DOMAIN_GTT)
cs->csc->used_gart += bo->base.size;
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Mesa (amdgpu): radeon/vce: clean up radeon_vce_40.2.2.c
Module: Mesa
Branch: amdgpu
Commit: 12e084b30a2d13dcd615405a5c2e5a6cd68886ac
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=12e084b30a2d13dcd615405a5c2e5a6cd68886ac
Author: Leo Liu
Date: Fri May 29 13:33:20 2015 -0400
radeon/vce: clean up radeon_vce_40.2.2.c
Change this file back to original release and only for v40.2.2
Signed-off-by: Leo Liu
Reviewed-by: Christian König
---
src/gallium/drivers/radeon/radeon_vce.c|5
src/gallium/drivers/radeon/radeon_vce.h|1 -
src/gallium/drivers/radeon/radeon_vce_40_2_2.c | 30 ++--
3 files changed, 2 insertions(+), 34 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_vce.c
b/src/gallium/drivers/radeon/radeon_vce.c
index 964fa47..ce61639 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -401,8 +401,6 @@ struct pipe_video_codec *rvce_create_encoder(struct
pipe_context *context,
enc->use_vm = true;
if ((rscreen->info.drm_major > 2) || (rscreen->info.drm_minor >= 42))
enc->use_vui = true;
- if (rscreen->info.family >= CHIP_TONGA)
- enc->use_2p = true;
enc->base = *templ;
enc->base.context = context;
@@ -442,9 +440,6 @@ struct pipe_video_codec *rvce_create_encoder(struct
pipe_context *context,
cpb_size = cpb_size * align(tmp_surf->npix_y, 16);
cpb_size = cpb_size * 3 / 2;
cpb_size = cpb_size * enc->cpb_num;
- if (enc->use_2p)
- cpb_size += RVCE_MAX_AUX_BUFFER_NUM *
- RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE;
tmp_buf->destroy(tmp_buf);
if (!rvid_create_buffer(enc->screen, &enc->cpb, cpb_size,
PIPE_USAGE_DEFAULT)) {
RVID_ERR("Can't create CPB buffer.\n");
diff --git a/src/gallium/drivers/radeon/radeon_vce.h
b/src/gallium/drivers/radeon/radeon_vce.h
index 890930c..64f2872 100644
--- a/src/gallium/drivers/radeon/radeon_vce.h
+++ b/src/gallium/drivers/radeon/radeon_vce.h
@@ -105,7 +105,6 @@ struct rvce_encoder {
booluse_vm;
unsignedfw_ver;
booluse_vui;
- booluse_2p;
};
/* CPB handling functions */
diff --git a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
index 234b2eb..71b5e89 100644
--- a/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
+++ b/src/gallium/drivers/radeon/radeon_vce_40_2_2.c
@@ -44,8 +44,6 @@
#include "radeon_video.h"
#include "radeon_vce.h"
-#define FW_40_2_2 ((40 << 24) | (2 << 16) | (2 << 8))
-
static const unsigned profiles[7] = { 66, 77, 88, 100, 110, 122, 244 };
static void session(struct rvce_encoder *enc)
@@ -121,10 +119,6 @@ static void rate_control(struct rvce_encoder *enc)
RVCE_CS(0x); // encBPicsDeltaQP
RVCE_CS(0x); // encReferenceBPicsDeltaQP
RVCE_CS(0x); // encRateControlReInitDisable
- if (enc->fw_ver > FW_40_2_2) {
- RVCE_CS(0x); // encLCVBRInitQPFlag
- RVCE_CS(0x); // encLCVBRSATDBasedNonlinearBitBudgetFlag
- }
RVCE_END();
}
@@ -293,28 +287,8 @@ static void encode(struct rvce_encoder *enc)
RVCE_CS(enc->bs_size); // videoBitstreamRingSize
RVCE_END();
- if (enc->use_2p) {
- unsigned aux_offset = enc->cpb.res->buf->size -
- RVCE_MAX_AUX_BUFFER_NUM *
RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE;
- RVCE_BEGIN(0x0502); // auxiliary buffer
- for (i = 0; i < 4; ++i) {
- RVCE_CS(aux_offset);
- aux_offset += RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE;
- }
- for (i = 0; i < 4; ++i)
- RVCE_CS(0x);
- for (i = 0; i < 4; ++i)
- RVCE_CS(RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE);
- for (i = 0; i < 4; ++i)
- RVCE_CS(0x);
- RVCE_END();
- }
-
RVCE_BEGIN(0x0301); // encode
- if ((enc->fw_ver > FW_40_2_2) && (!enc->pic.frame_num))
- RVCE_CS(0x0011); // insertHeaders
- else
- RVCE_CS(0x); // insertHeaders
+ RVCE_CS(0x); // insertHeaders
RVCE_CS(0x); // pictureStructure
RVCE_CS(enc->bs_size); // allowedMaxBitstreamSize
RVCE_CS(0x); // forceRefreshMap
@@ -328,7 +302,7 @@ static void encode(struct rvce_encoder *enc)
RVCE_CS(align(enc->luma->npix_y, 16)); // encInputFrameYPitch
RVCE_CS(enc->luma->level[0].pitch_bytes); // encInputPicLumaPitch
RVCE_CS(enc->chroma->level[0].pitch_bytes); // encInputPicChromaPitch
- RVCE_CS(0x); //
encInputPic(Addr|Array)Mode,encDisable(TwoPipeMode|MBOffloading)
+ RVCE_CS(0x); // encInputPic(Add
Mesa (amdgpu): radeon/vce: add new firmware support for VI and CI
Module: Mesa
Branch: amdgpu
Commit: 619d37b9194f68916c5f720533645e2861452107
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=619d37b9194f68916c5f720533645e2861452107
Author: Leo Liu
Date: Fri May 29 13:43:00 2015 -0400
radeon/vce: add new firmware support for VI and CI
Signed-off-by: Leo Liu
Reviewed-by: Christian König
---
src/gallium/drivers/radeon/radeon_vce.c |8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeon/radeon_vce.c
b/src/gallium/drivers/radeon/radeon_vce.c
index ce61639..f360e82 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -47,6 +47,8 @@
#define FW_40_2_2 ((40 << 24) | (2 << 16) | (2 << 8))
#define FW_50_0_1 ((50 << 24) | (0 << 16) | (1 << 8))
#define FW_50_1_2 ((50 << 24) | (1 << 16) | (2 << 8))
+#define FW_50_10_2 ((50 << 24) | (10 << 16) | (2 << 8))
+#define FW_50_17_3 ((50 << 24) | (17 << 16) | (3 << 8))
/**
* flush commands to the hardware
@@ -459,6 +461,8 @@ struct pipe_video_codec *rvce_create_encoder(struct
pipe_context *context,
case FW_50_0_1:
case FW_50_1_2:
+ case FW_50_10_2:
+ case FW_50_17_3:
radeon_vce_50_init(enc);
break;
@@ -486,7 +490,9 @@ bool rvce_is_fw_version_supported(struct r600_common_screen
*rscreen)
{
return rscreen->info.vce_fw_version == FW_40_2_2 ||
rscreen->info.vce_fw_version == FW_50_0_1 ||
- rscreen->info.vce_fw_version == FW_50_1_2;
+ rscreen->info.vce_fw_version == FW_50_1_2 ||
+ rscreen->info.vce_fw_version == FW_50_10_2 ||
+ rscreen->info.vce_fw_version == FW_50_17_3;
}
/**
___
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Mesa (amdgpu): radeon/vce: add dual pipe support for VI
Module: Mesa
Branch: amdgpu
Commit: 2f7eef72c7d9a7a7402228b9846c2a4ffdfdcd94
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f7eef72c7d9a7a7402228b9846c2a4ffdfdcd94
Author: Leo Liu
Date: Fri May 29 13:37:43 2015 -0400
radeon/vce: add dual pipe support for VI
Dual pipe requires additional auxiliary buffers for MB row encode,
This also makes dual pipe support available on each of dual instances.
Signed-off-by: Leo Liu
Reviewed-by: Christian König
---
src/gallium/drivers/radeon/radeon_vce.c|5 +
src/gallium/drivers/radeon/radeon_vce.h|1 +
src/gallium/drivers/radeon/radeon_vce_50.c | 18 +-
3 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeon/radeon_vce.c
b/src/gallium/drivers/radeon/radeon_vce.c
index f360e82..5065a50 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -403,6 +403,8 @@ struct pipe_video_codec *rvce_create_encoder(struct
pipe_context *context,
enc->use_vm = true;
if ((rscreen->info.drm_major > 2) || (rscreen->info.drm_minor >= 42))
enc->use_vui = true;
+ if (rscreen->info.family >= CHIP_TONGA)
+ enc->dual_pipe = true;
enc->base = *templ;
enc->base.context = context;
@@ -442,6 +444,9 @@ struct pipe_video_codec *rvce_create_encoder(struct
pipe_context *context,
cpb_size = cpb_size * align(tmp_surf->npix_y, 16);
cpb_size = cpb_size * 3 / 2;
cpb_size = cpb_size * enc->cpb_num;
+ if (enc->dual_pipe)
+ cpb_size += RVCE_MAX_AUX_BUFFER_NUM *
+ RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
tmp_buf->destroy(tmp_buf);
if (!rvid_create_buffer(enc->screen, &enc->cpb, cpb_size,
PIPE_USAGE_DEFAULT)) {
RVID_ERR("Can't create CPB buffer.\n");
diff --git a/src/gallium/drivers/radeon/radeon_vce.h
b/src/gallium/drivers/radeon/radeon_vce.h
index 64f2872..a588194 100644
--- a/src/gallium/drivers/radeon/radeon_vce.h
+++ b/src/gallium/drivers/radeon/radeon_vce.h
@@ -105,6 +105,7 @@ struct rvce_encoder {
booluse_vm;
unsignedfw_ver;
booluse_vui;
+ booldual_pipe;
};
/* CPB handling functions */
diff --git a/src/gallium/drivers/radeon/radeon_vce_50.c
b/src/gallium/drivers/radeon/radeon_vce_50.c
index d7fdd12..019927e 100644
--- a/src/gallium/drivers/radeon/radeon_vce_50.c
+++ b/src/gallium/drivers/radeon/radeon_vce_50.c
@@ -104,6 +104,19 @@ static void encode(struct rvce_encoder *enc)
RVCE_CS(enc->bs_size); // videoBitstreamRingSize
RVCE_END();
+ if (enc->dual_pipe) {
+ unsigned aux_offset = enc->cpb.res->buf->size -
+ RVCE_MAX_AUX_BUFFER_NUM *
RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE * 2;
+ RVCE_BEGIN(0x0502); // auxiliary buffer
+ for (i = 0; i < 8; ++i) {
+ RVCE_CS(aux_offset);
+ aux_offset += RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE;
+ }
+ for (i = 0; i < 8; ++i)
+ RVCE_CS(RVCE_MAX_BITSTREAM_OUTPUT_ROW_SIZE);
+ RVCE_END();
+ }
+
RVCE_BEGIN(0x0301); // encode
RVCE_CS(enc->pic.frame_num ? 0x0 : 0x11); // insertHeaders
RVCE_CS(0x); // pictureStructure
@@ -119,7 +132,10 @@ static void encode(struct rvce_encoder *enc)
RVCE_CS(align(enc->luma->npix_y, 16)); // encInputFrameYPitch
RVCE_CS(enc->luma->level[0].pitch_bytes); // encInputPicLumaPitch
RVCE_CS(enc->chroma->level[0].pitch_bytes); // encInputPicChromaPitch
- RVCE_CS(0x0001); //
encInputPic(Addr|Array)Mode,encDisable(TwoPipeMode|MBOffloading)
+ if (enc->dual_pipe)
+ RVCE_CS(0x); //
encInputPic(Addr|Array)Mode,encDisable(TwoPipeMode|MBOffloading)
+ else
+ RVCE_CS(0x0001); //
encInputPic(Addr|Array)Mode,encDisable(TwoPipeMode|MBOffloading)
RVCE_CS(0x); // encInputPicTileConfig
RVCE_CS(enc->pic.picture_type); // encPicType
RVCE_CS(enc->pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR); //
encIdrFlag
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Mesa (amdgpu): radeon/vce: adapt new firmware interface changes
Module: Mesa
Branch: amdgpu
Commit: a5aa23dc83409542fdb500e378239a7ade66b6ee
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5aa23dc83409542fdb500e378239a7ade66b6ee
Author: Christian König
Date: Thu Mar 26 10:00:09 2015 +0100
radeon/vce: adapt new firmware interface changes
v2: make this also compatible with original released firmware
v3 (chk): switch to original idea of separate files for fw versions
Signed-off-by: Leo Liu
Signed-off-by: Christian König
Reviewed-by: Alex Deucher (v2)
Conflicts:
src/gallium/drivers/radeon/radeon_vce.c
v4: (leo) resolve the conflicts
---
src/gallium/drivers/radeon/Makefile.sources |1 +
src/gallium/drivers/radeon/radeon_vce.c | 22 ++-
src/gallium/drivers/radeon/radeon_vce.h |3 +
src/gallium/drivers/radeon/radeon_vce_50.c | 226 +++
4 files changed, 250 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/Makefile.sources
b/src/gallium/drivers/radeon/Makefile.sources
index c655fe5..f63790c 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -12,6 +12,7 @@ C_SOURCES := \
radeon_uvd.c \
radeon_uvd.h \
radeon_vce_40_2_2.c \
+ radeon_vce_50.c \
radeon_vce.c \
radeon_vce.h \
radeon_video.c \
diff --git a/src/gallium/drivers/radeon/radeon_vce.c
b/src/gallium/drivers/radeon/radeon_vce.c
index 740134d..964fa47 100644
--- a/src/gallium/drivers/radeon/radeon_vce.c
+++ b/src/gallium/drivers/radeon/radeon_vce.c
@@ -44,6 +44,10 @@
#include "radeon_video.h"
#include "radeon_vce.h"
+#define FW_40_2_2 ((40 << 24) | (2 << 16) | (2 << 8))
+#define FW_50_0_1 ((50 << 24) | (0 << 16) | (1 << 8))
+#define FW_50_1_2 ((50 << 24) | (1 << 16) | (2 << 8))
+
/**
* flush commands to the hardware
*/
@@ -453,7 +457,19 @@ struct pipe_video_codec *rvce_create_encoder(struct
pipe_context *context,
reset_cpb(enc);
- radeon_vce_40_2_2_init(enc);
+ switch (rscreen->info.vce_fw_version) {
+ case FW_40_2_2:
+ radeon_vce_40_2_2_init(enc);
+ break;
+
+ case FW_50_0_1:
+ case FW_50_1_2:
+ radeon_vce_50_init(enc);
+ break;
+
+ default:
+ goto error;
+ }
return &enc->base;
@@ -473,7 +489,9 @@ error:
*/
bool rvce_is_fw_version_supported(struct r600_common_screen *rscreen)
{
- return rscreen->info.vce_fw_version >= ((40 << 24) | (2 << 16) | (2 <<
8));
+ return rscreen->info.vce_fw_version == FW_40_2_2 ||
+ rscreen->info.vce_fw_version == FW_50_0_1 ||
+ rscreen->info.vce_fw_version == FW_50_1_2;
}
/**
diff --git a/src/gallium/drivers/radeon/radeon_vce.h
b/src/gallium/drivers/radeon/radeon_vce.h
index 77a56d5..890930c 100644
--- a/src/gallium/drivers/radeon/radeon_vce.h
+++ b/src/gallium/drivers/radeon/radeon_vce.h
@@ -129,4 +129,7 @@ void rvce_add_buffer(struct rvce_encoder *enc, struct
radeon_winsys_cs_handle *b
/* init vce fw 40.2.2 specific callbacks */
void radeon_vce_40_2_2_init(struct rvce_encoder *enc);
+/* init vce fw 50 specific callbacks */
+void radeon_vce_50_init(struct rvce_encoder *enc);
+
#endif
diff --git a/src/gallium/drivers/radeon/radeon_vce_50.c
b/src/gallium/drivers/radeon/radeon_vce_50.c
new file mode 100644
index 000..d7fdd12
--- /dev/null
+++ b/src/gallium/drivers/radeon/radeon_vce_50.c
@@ -0,0 +1,226 @@
+/**
+ *
+ * Copyright 2013 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
+ * IN NO EVENT SHALL THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR
+ * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
+ * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
+ * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+
Mesa (amdgpu): winsys/amdgpu: don't use KMS handles as reloc hash keys
Module: Mesa
Branch: amdgpu
Commit: 8380f7fcb9057a6f99160a3f4bcf3fec7b3ab773
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8380f7fcb9057a6f99160a3f4bcf3fec7b3ab773
Author: Marek Olšák
Date: Thu Jun 4 12:50:55 2015 +0200
winsys/amdgpu: don't use KMS handles as reloc hash keys
Reviewed-by: Christian König
---
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 21 +++--
src/gallium/winsys/amdgpu/drm/amdgpu_bo.h |2 +-
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c |4 ++--
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h |1 +
4 files changed, 7 insertions(+), 21 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index b274536..02e0c07 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -292,12 +292,7 @@ static struct pb_buffer *amdgpu_bomgr_create_bo(struct
pb_manager *_mgr,
bo->bo = result.buf_handle;
bo->va = result.virtual_mc_base_address;
bo->initial_domain = rdesc->initial_domain;
-
- if (amdgpu_bo_export(bo->bo, amdgpu_bo_handle_type_kms, &bo->handle)) {
- amdgpu_bo_free(bo->bo);
- FREE(bo);
- return NULL;
- }
+ bo->unique_id = __sync_fetch_and_add(&rws->next_bo_unique_id, 1);
if (rdesc->initial_domain & RADEON_DOMAIN_VRAM)
rws->allocated_vram += align(size, 4096);
@@ -573,12 +568,7 @@ static struct pb_buffer *amdgpu_bo_from_handle(struct
radeon_winsys *rws,
bo->rws = ws;
bo->va = result.virtual_mc_base_address;
bo->initial_domain = initial;
-
- if (amdgpu_bo_export(bo->bo, amdgpu_bo_handle_type_kms, &bo->handle)) {
- amdgpu_bo_free(bo->bo);
- FREE(bo);
- return NULL;
- }
+ bo->unique_id = __sync_fetch_and_add(&ws->next_bo_unique_id, 1);
if (stride)
*stride = whandle->stride;
@@ -648,12 +638,7 @@ static struct pb_buffer *amdgpu_bo_from_ptr(struct
radeon_winsys *rws,
bo->user_ptr = pointer;
bo->va = result.virtual_mc_base_address;
bo->initial_domain = RADEON_DOMAIN_GTT;
-
-if (amdgpu_bo_export(bo->bo, amdgpu_bo_handle_type_kms, &bo->handle)) {
- amdgpu_bo_free(bo->bo);
- FREE(bo);
- return NULL;
-}
+bo->unique_id = __sync_fetch_and_add(&ws->next_bo_unique_id, 1);
ws->allocated_gtt += align(bo->base.size, 4096);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
index 77c0520..6b03afd 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
@@ -50,7 +50,7 @@ struct amdgpu_winsys_bo {
void *user_ptr; /* from buffer_from_ptr */
amdgpu_bo_handle bo;
- uint32_t handle;
+ uint32_t unique_id;
uint64_t va;
enum radeon_bo_domain initial_domain;
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 1fda66f..6e15f83 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -335,7 +335,7 @@ amdgpu_cs_create(struct radeon_winsys_ctx *rwctx,
int amdgpu_get_reloc(struct amdgpu_cs_context *csc, struct amdgpu_winsys_bo
*bo)
{
- unsigned hash = bo->handle & (Elements(csc->buffer_indices_hashlist)-1);
+ unsigned hash = bo->unique_id & (Elements(csc->buffer_indices_hashlist)-1);
int i = csc->buffer_indices_hashlist[hash];
/* not found or found */
@@ -370,7 +370,7 @@ static unsigned amdgpu_add_reloc(struct amdgpu_cs *cs,
{
struct amdgpu_cs_context *csc = cs->csc;
struct amdgpu_cs_buffer *reloc;
- unsigned hash = bo->handle & (Elements(csc->buffer_indices_hashlist)-1);
+ unsigned hash = bo->unique_id & (Elements(csc->buffer_indices_hashlist)-1);
int i = -1;
priority = MIN2(priority, 15);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
index cc475d0..195fb15 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
@@ -47,6 +47,7 @@ struct amdgpu_winsys {
amdgpu_device_handle dev;
int num_cs; /* The number of command streams created. */
+ uint32_t next_bo_unique_id;
uint64_t allocated_vram;
uint64_t allocated_gtt;
uint64_t buffer_wait_time; /* time spent in buffer_wait in ns */
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Mesa (amdgpu): winsys/amdgpu: allocate IBs like normal buffers
Module: Mesa
Branch: amdgpu
Commit: 3e6c7a2892fc05a8e1e368878f35d7968d630742
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3e6c7a2892fc05a8e1e368878f35d7968d630742
Author: Marek Olšák
Date: Fri May 29 12:58:17 2015 +0200
winsys/amdgpu: allocate IBs like normal buffers
There is a big IB buffer whose size is 256KB and normal IBs are allocated
from it. Each driver command stream (CS) has its own big IB buffer.
The maximum size of allocated IBs from the big buffer is 64KB.
(so there's a minimum of 4 IBs per buffer)
However, the size is determined when flushing, so if the used size is only
1KB, the next IB will start after the 1KB.
After the big IB buffer is all used, another one is allocated or reused.
The reusing is done by the buffer allocator itself.
Reviewed-by: Christian König
---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 54 +++--
src/gallium/winsys/amdgpu/drm/amdgpu_cs.h |9 +
2 files changed, 52 insertions(+), 11 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 7064474..05720ef 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -179,17 +179,44 @@ amdgpu_ctx_query_reset_status(struct radeon_winsys_ctx
*rwctx)
static bool amdgpu_get_new_ib(struct amdgpu_cs *cs)
{
struct amdgpu_cs_context *cur_cs = cs->csc;
- struct amdgpu_cs_ib_alloc_result ib;
- int r;
-
- r = amdgpu_cs_alloc_ib(cs->ctx->ctx, amdgpu_cs_ib_size_64K, &ib);
- if (r)
- return false;
+ unsigned max_ib_size = RADEON_MAX_CMDBUF_DWORDS * 4;
- cs->base.buf = ib.cpu;
cs->base.cdw = 0;
+ cs->base.buf = NULL;
+
+ /* Allocate a new buffer for IBs if the current buffer is all used. */
+ if (!cs->big_ib_buffer ||
+ cs->used_ib_space + max_ib_size > cs->big_ib_buffer->size) {
+ struct radeon_winsys *ws = &cs->ctx->ws->base;
+ struct radeon_winsys_cs_handle *winsys_bo;
+
+ pb_reference(&cs->big_ib_buffer, NULL);
+ cs->big_ib_winsys_buffer = NULL;
+ cs->ib_mapped = NULL;
+ cs->used_ib_space = 0;
+
+ cs->big_ib_buffer = ws->buffer_create(ws, 256 * 1024, 4096, true,
+RADEON_DOMAIN_GTT,
+RADEON_FLAG_CPU_ACCESS);
+ if (!cs->big_ib_buffer)
+ return false;
+
+ winsys_bo = ws->buffer_get_cs_handle(cs->big_ib_buffer);
+
+ cs->ib_mapped = ws->buffer_map(winsys_bo, NULL, PIPE_TRANSFER_WRITE);
+ if (!cs->ib_mapped) {
+ pb_reference(&cs->big_ib_buffer, NULL);
+ return false;
+ }
+
+ cs->big_ib_winsys_buffer = (struct amdgpu_winsys_bo*)winsys_bo;
+ }
- cur_cs->ib.ib_handle = ib.handle;
+ pb_reference(&cur_cs->ib_buffer, cs->big_ib_buffer);
+ cur_cs->ib_winsys_buffer = cs->big_ib_winsys_buffer;
+ cur_cs->ib.bo_handle = cs->big_ib_winsys_buffer->bo;
+ cur_cs->ib.offset_dw = cs->used_ib_space / 4;
+ cs->base.buf = (uint32_t*)(cs->ib_mapped + cs->used_ib_space);
return true;
}
@@ -250,6 +277,7 @@ static void amdgpu_cs_context_cleanup(struct
amdgpu_cs_context *csc)
static void amdgpu_destroy_cs_context(struct amdgpu_cs_context *csc)
{
amdgpu_cs_context_cleanup(csc);
+ pb_reference(&csc->ib_buffer, NULL);
FREE(csc->flags);
FREE(csc->buffers);
FREE(csc->handles);
@@ -451,15 +479,17 @@ void amdgpu_cs_emit_ioctl_oneshot(struct amdgpu_cs *cs,
struct amdgpu_cs_context
for (i = 0; i < csc->num_buffers; i++) {
amdgpu_fence_reference(&csc->buffers[i].bo->fence, csc->fence);
}
+ amdgpu_fence_reference(&csc->ib_winsys_buffer->fence, csc->fence);
}
/* Cleanup. */
- if (cs->cst->request.resources)
- amdgpu_bo_list_destroy(cs->cst->request.resources);
+ if (csc->request.resources)
+ amdgpu_bo_list_destroy(csc->request.resources);
for (i = 0; i < csc->num_buffers; i++) {
p_atomic_dec(&csc->buffers[i].bo->num_active_ioctls);
}
+ p_atomic_dec(&csc->ib_winsys_buffer->num_active_ioctls);
amdgpu_cs_context_cleanup(csc);
}
@@ -545,11 +575,13 @@ static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
}
cs->cst->ib.size = cs->base.cdw;
+ cs->used_ib_space += cs->base.cdw * 4;
for (i = 0; i < num_buffers; i++) {
/* Update the number of active asynchronous CS ioctls for the buffer.
*/
p_atomic_inc(&cs->cst->buffers[i].bo->num_active_ioctls);
}
+ p_atomic_inc(&cs->cst->ib_winsys_buffer->num_active_ioctls);
switch (cs->base.ring_type) {
case RING_DMA:
@@ -608,9 +640,9 @@ static void amdgpu_cs_destroy(struct radeon_winsys_cs *rcs)
amdgpu_cs_context_cleanup(&cs->csc1);
amdgpu_cs_context_cleanup(&cs->csc2);
p_atomic_dec(&cs->ctx->ws->num_cs);
- amdgpu_cs_free_ib(cs->csc->ib.ib_handle);
amdgpu_destroy_cs_context(&cs->csc1);
amdgpu_destroy_cs_context(&cs->csc2);
+ pb_reference(&c
Mesa (amdgpu): winsys/amdgpu: add IBs to the buffer list, adapt to interface changes
Module: Mesa
Branch: amdgpu
Commit: df90f08389f4be5c273fce9bc32cb43c9b4d42a4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=df90f08389f4be5c273fce9bc32cb43c9b4d42a4
Author: Marek Olšák
Date: Tue Jun 2 13:21:18 2015 +0200
winsys/amdgpu: add IBs to the buffer list, adapt to interface changes
Reviewed-by: Christian König
---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c |9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 05720ef..1fda66f 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -214,8 +214,7 @@ static bool amdgpu_get_new_ib(struct amdgpu_cs *cs)
pb_reference(&cur_cs->ib_buffer, cs->big_ib_buffer);
cur_cs->ib_winsys_buffer = cs->big_ib_winsys_buffer;
- cur_cs->ib.bo_handle = cs->big_ib_winsys_buffer->bo;
- cur_cs->ib.offset_dw = cs->used_ib_space / 4;
+ cur_cs->ib.ib_mc_address = cs->big_ib_winsys_buffer->va + cs->used_ib_space;
cs->base.buf = (uint32_t*)(cs->ib_mapped + cs->used_ib_space);
return true;
}
@@ -479,7 +478,6 @@ void amdgpu_cs_emit_ioctl_oneshot(struct amdgpu_cs *cs,
struct amdgpu_cs_context
for (i = 0; i < csc->num_buffers; i++) {
amdgpu_fence_reference(&csc->buffers[i].bo->fence, csc->fence);
}
- amdgpu_fence_reference(&csc->ib_winsys_buffer->fence, csc->fence);
}
/* Cleanup. */
@@ -489,7 +487,6 @@ void amdgpu_cs_emit_ioctl_oneshot(struct amdgpu_cs *cs,
struct amdgpu_cs_context
for (i = 0; i < csc->num_buffers; i++) {
p_atomic_dec(&csc->buffers[i].bo->num_active_ioctls);
}
- p_atomic_dec(&csc->ib_winsys_buffer->num_active_ioctls);
amdgpu_cs_context_cleanup(csc);
}
@@ -553,6 +550,9 @@ static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
fprintf(stderr, "amdgpu: command stream overflowed\n");
}
+ amdgpu_cs_add_reloc(rcs, (void*)cs->csc->ib_winsys_buffer,
+ RADEON_USAGE_READ, 0, RADEON_PRIO_MIN);
+
amdgpu_cs_sync_flush(rcs);
/* Swap command streams. */
@@ -581,7 +581,6 @@ static void amdgpu_cs_flush(struct radeon_winsys_cs *rcs,
/* Update the number of active asynchronous CS ioctls for the buffer.
*/
p_atomic_inc(&cs->cst->buffers[i].bo->num_active_ioctls);
}
- p_atomic_inc(&cs->cst->ib_winsys_buffer->num_active_ioctls);
switch (cs->base.ring_type) {
case RING_DMA:
___
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Mesa (amdgpu): Revert "winsys/amdgpu: use amdgpu_bo_wait_for_idle"
Module: Mesa
Branch: amdgpu
Commit: 6b7f81f654fa627157a91e1bc5b59f7b63726d3d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b7f81f654fa627157a91e1bc5b59f7b63726d3d
Author: Leo Liu
Date: Fri May 22 09:20:49 2015 -0400
Revert "winsys/amdgpu: use amdgpu_bo_wait_for_idle"
This reverts commit 3691c11ace4a0e7b2307dbf047048d363803d387.
This cause HW transcode performance drop 30%, revert it for now.
Acked-by: Marek Olšák
---
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 14 +++---
src/gallium/winsys/amdgpu/drm/amdgpu_bo.h |2 ++
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c |4
3 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 06858d3..b274536 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -76,29 +76,28 @@ static struct amdgpu_winsys_bo *get_amdgpu_winsys_bo(struct
pb_buffer *_buf)
static void amdgpu_bo_wait(struct pb_buffer *_buf, enum radeon_bo_usage usage)
{
struct amdgpu_winsys_bo *bo = get_amdgpu_winsys_bo(_buf);
- bool busy;
+ struct radeon_winsys *ws = &bo->rws->base;
while (p_atomic_read(&bo->num_active_ioctls)) {
sched_yield();
}
- amdgpu_bo_wait_for_idle(bo->bo, AMDGPU_TIMEOUT_INFINITE, &busy);
+ if (bo->fence) {
+ ws->fence_wait(ws, bo->fence, PIPE_TIMEOUT_INFINITE);
+ }
}
static boolean amdgpu_bo_is_busy(struct pb_buffer *_buf,
enum radeon_bo_usage usage)
{
struct amdgpu_winsys_bo *bo = get_amdgpu_winsys_bo(_buf);
- bool busy;
+ struct radeon_winsys *ws = &bo->rws->base;
if (p_atomic_read(&bo->num_active_ioctls)) {
return TRUE;
}
- if (amdgpu_bo_wait_for_idle(bo->bo, 0, &busy))
- return false;
-
- return busy;
+ return bo->fence && !ws->fence_wait(ws, bo->fence, 0);
}
static enum radeon_bo_domain amdgpu_bo_get_initial_domain(
@@ -112,6 +111,7 @@ static void amdgpu_bo_destroy(struct pb_buffer *_buf)
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
amdgpu_bo_free(bo->bo);
+ amdgpu_fence_reference(&bo->fence, NULL);
if (bo->initial_domain & RADEON_DOMAIN_VRAM)
bo->rws->allocated_vram -= align(bo->base.size, 4096);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
index f708731..77c0520 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
@@ -60,6 +60,8 @@ struct amdgpu_winsys_bo {
/* how many command streams, which are being emitted in a separate
* thread, is this bo referenced in? */
int num_active_ioctls;
+
+ struct pipe_fence_handle *fence; /* for buffer_wait & buffer_is_busy */
};
struct pb_manager *amdgpu_bomgr_create(struct amdgpu_winsys *rws);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
index 7b32ae3..7064474 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
@@ -447,6 +447,10 @@ void amdgpu_cs_emit_ioctl_oneshot(struct amdgpu_cs *cs,
struct amdgpu_cs_context
} else {
/* Success. */
amdgpu_fence_submitted(csc->fence, fence);
+
+ for (i = 0; i < csc->num_buffers; i++) {
+ amdgpu_fence_reference(&csc->buffers[i].bo->fence, csc->fence);
+ }
}
/* Cleanup. */
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Mesa (amdgpu): winsys/amdgpu: set PIPE_CONFIG and NUM_BANKS in tiling_flags
Module: Mesa
Branch: amdgpu
Commit: 3f9ce0edc821eae6f35829691ddf1bc02529abfc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f9ce0edc821eae6f35829691ddf1bc02529abfc
Author: Marek Olšák
Date: Fri May 15 11:54:31 2015 +0200
winsys/amdgpu: set PIPE_CONFIG and NUM_BANKS in tiling_flags
Reviewed-by: Alex Deucher
Acked-by: Christian König
---
src/gallium/drivers/r300/r300_state.c |2 +-
src/gallium/drivers/r300/r300_texture.c|2 +-
src/gallium/drivers/radeon/r600_texture.c |3 ++-
src/gallium/drivers/radeon/radeon_winsys.h |5 -
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c |5 -
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c |2 ++
src/gallium/winsys/radeon/drm/radeon_drm_bo.c |3 ++-
7 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/r300/r300_state.c
b/src/gallium/drivers/r300/r300_state.c
index e886df8..d99d5ae 100644
--- a/src/gallium/drivers/r300/r300_state.c
+++ b/src/gallium/drivers/r300/r300_state.c
@@ -844,7 +844,7 @@ static void r300_tex_set_tiling_flags(struct r300_context
*r300,
tex->tex.macrotile[level]) {
r300->rws->buffer_set_tiling(tex->buf, r300->cs,
tex->tex.microtile, tex->tex.macrotile[level],
-0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0,
tex->tex.stride_in_bytes[0], false);
tex->surface_level = level;
diff --git a/src/gallium/drivers/r300/r300_texture.c
b/src/gallium/drivers/r300/r300_texture.c
index 6c01c0d..5e4d50d 100644
--- a/src/gallium/drivers/r300/r300_texture.c
+++ b/src/gallium/drivers/r300/r300_texture.c
@@ -1063,7 +1063,7 @@ r300_texture_create_object(struct r300_screen *rscreen,
rws->buffer_set_tiling(tex->buf, NULL,
tex->tex.microtile, tex->tex.macrotile[0],
-0, 0, 0, 0, 0,
+0, 0, 0, 0, 0, 0, 0,
tex->tex.stride_in_bytes[0], false);
return tex;
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index 1b64507..62705db 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -243,10 +243,11 @@ static boolean r600_texture_get_handle(struct
pipe_screen* screen,
RADEON_LAYOUT_TILED :
RADEON_LAYOUT_LINEAR,
surface->level[0].mode >=
RADEON_SURF_MODE_2D ?
RADEON_LAYOUT_TILED :
RADEON_LAYOUT_LINEAR,
+ surface->pipe_config,
surface->bankw, surface->bankh,
surface->tile_split,
surface->stencil_tile_split,
- surface->mtilea,
+ surface->mtilea, surface->num_banks,
surface->level[0].pitch_bytes,
(surface->flags & RADEON_SURF_SCANOUT)
!= 0);
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index a0645ef..6efdc11 100644
--- a/src/gallium/drivers/radeon/radeon_winsys.h
+++ b/src/gallium/drivers/radeon/radeon_winsys.h
@@ -323,6 +323,8 @@ struct radeon_surf {
struct radeon_surf_levelstencil_level[RADEON_SURF_MAX_LEVEL];
uint32_ttiling_index[RADEON_SURF_MAX_LEVEL];
uint32_tstencil_tiling_index[RADEON_SURF_MAX_LEVEL];
+uint32_tpipe_config;
+uint32_tnum_banks;
};
struct radeon_winsys {
@@ -456,10 +458,11 @@ struct radeon_winsys {
struct radeon_winsys_cs *rcs,
enum radeon_bo_layout microtile,
enum radeon_bo_layout macrotile,
+ unsigned pipe_config,
unsigned bankw, unsigned bankh,
unsigned tile_split,
unsigned stencil_tile_split,
- unsigned mtilea,
+ unsigned mtilea, unsigned num_banks,
unsigned stride,
bool scanout);
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 0c0362f..06858d3 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -422,10 +422,11 @@ static void amdgpu_bo_set_tiling(struct pb_buffer *_buf,
struct radeon_winsys_cs *rcs,
enum radeon_bo_layout microtiled,
enum radeon_bo_layout macrotiled,
+
Mesa (amdgpu): winsys/amdgpu: use the new tiling flags
Module: Mesa
Branch: amdgpu
Commit: b7258d5db9052c275f52b58161285dc497f04374
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7258d5db9052c275f52b58161285dc497f04374
Author: Marek Olšák
Date: Fri May 15 00:36:54 2015 +0200
winsys/amdgpu: use the new tiling flags
Reviewed-by: Alex Deucher
Acked-by: Christian König
---
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 64 -
1 file changed, 26 insertions(+), 38 deletions(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 8065f46..0c0362f 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -402,23 +402,20 @@ static void amdgpu_bo_get_tiling(struct pb_buffer *_buf,
*microtiled = RADEON_LAYOUT_LINEAR;
*macrotiled = RADEON_LAYOUT_LINEAR;
- if (tiling_flags & AMDGPU_TILING_MICRO)
- *microtiled = RADEON_LAYOUT_TILED;
- else if (tiling_flags & AMDGPU_TILING_MICRO_SQUARE)
- *microtiled = RADEON_LAYOUT_SQUARETILED;
- if (tiling_flags & AMDGPU_TILING_MACRO)
+ if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 4) /* 2D_TILED_THIN1 */
*macrotiled = RADEON_LAYOUT_TILED;
- if (bankw && tile_split && stencil_tile_split && mtilea && tile_split) {
- *bankw = (tiling_flags >> AMDGPU_TILING_EG_BANKW_SHIFT) &
AMDGPU_TILING_EG_BANKW_MASK;
- *bankh = (tiling_flags >> AMDGPU_TILING_EG_BANKH_SHIFT) &
AMDGPU_TILING_EG_BANKH_MASK;
- *tile_split = (tiling_flags >> AMDGPU_TILING_EG_TILE_SPLIT_SHIFT) &
AMDGPU_TILING_EG_TILE_SPLIT_MASK;
- *stencil_tile_split = (tiling_flags >>
AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) &
AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_MASK;
- *mtilea = (tiling_flags >> AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT) &
AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK;
- *tile_split = eg_tile_split(*tile_split);
+ else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == 2) /*
1D_TILED_THIN1 */
+ *microtiled = RADEON_LAYOUT_TILED;
+
+ if (bankw && tile_split && mtilea && tile_split) {
+ *bankw = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
+ *bankh = 1 << AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
+ *tile_split = eg_tile_split(AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT));
+ *mtilea = 1 << AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
}
if (scanout)
- *scanout = !(tiling_flags & AMDGPU_TILING_R600_NO_SCANOUT);
+ *scanout = AMDGPU_TILING_GET(tiling_flags, MICRO_TILE_MODE) == 0; /*
DISPLAY */
}
static void amdgpu_bo_set_tiling(struct pb_buffer *_buf,
@@ -437,7 +434,6 @@ static void amdgpu_bo_set_tiling(struct pb_buffer *_buf,
struct amdgpu_bo_metadata metadata = {0};
uint32_t tiling_flags = 0;
-
/* Tiling determines how DRM treats the buffer data.
* We must flush CS when changing it if the buffer is referenced. */
if (cs && amdgpu_bo_is_referenced_by_cs(cs, bo)) {
@@ -448,31 +444,23 @@ static void amdgpu_bo_set_tiling(struct pb_buffer *_buf,
sched_yield();
}
- if (microtiled == RADEON_LAYOUT_TILED)
- tiling_flags |= AMDGPU_TILING_MICRO;
- else if (microtiled == RADEON_LAYOUT_SQUARETILED)
- tiling_flags |= AMDGPU_TILING_MICRO_SQUARE;
-
if (macrotiled == RADEON_LAYOUT_TILED)
- tiling_flags |= AMDGPU_TILING_MACRO;
-
- tiling_flags |= (bankw & AMDGPU_TILING_EG_BANKW_MASK) <<
- AMDGPU_TILING_EG_BANKW_SHIFT;
- tiling_flags |= (bankh & AMDGPU_TILING_EG_BANKH_MASK) <<
- AMDGPU_TILING_EG_BANKH_SHIFT;
- if (tile_split) {
- tiling_flags |= (eg_tile_split_rev(tile_split) &
- AMDGPU_TILING_EG_TILE_SPLIT_MASK) <<
- AMDGPU_TILING_EG_TILE_SPLIT_SHIFT;
- }
- tiling_flags |= (stencil_tile_split &
-AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_MASK) <<
- AMDGPU_TILING_EG_STENCIL_TILE_SPLIT_SHIFT;
- tiling_flags |= (mtilea & AMDGPU_TILING_EG_MACRO_TILE_ASPECT_MASK) <<
- AMDGPU_TILING_EG_MACRO_TILE_ASPECT_SHIFT;
-
- if (!scanout)
- tiling_flags |= AMDGPU_TILING_R600_NO_SCANOUT;
+ tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 4); /* 2D_TILED_THIN1 */
+ else if (microtiled == RADEON_LAYOUT_TILED)
+ tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 2); /* 1D_TILED_THIN1 */
+ else
+ tiling_flags |= AMDGPU_TILING_SET(ARRAY_MODE, 1); /* LINEAR_ALIGNED */
+
+ tiling_flags |= AMDGPU_TILING_SET(BANK_WIDTH, util_logbase2(bankw));
+ tiling_flags |= AMDGPU_TILING_SET(BANK_HEIGHT, util_logbase2(bankh));
+ if (tile_split)
+ tiling_flags |= AMDGPU_TILING_SET(TILE_SPLIT,
eg_tile_split_rev(tile_split));
+ tiling_flags |= AMDGPU_TILING_SET(MACRO_TILE_ASPECT, util_logbase2(mtilea));
+
+
Mesa (amdgpu): radeonsi: add some additional tonga pci ids
Module: Mesa Branch: amdgpu Commit: f27f1813b18f2a76febaaab81bf15f499578ea8d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f27f1813b18f2a76febaaab81bf15f499578ea8d Author: Alex Deucher Date: Tue May 12 13:15:44 2015 -0400 radeonsi: add some additional tonga pci ids Reviewed-by: Marek Olšák Signed-off-by: Alex Deucher --- include/pci_ids/radeonsi_pci_ids.h |2 ++ 1 file changed, 2 insertions(+) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index ca81f76..3589198 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -165,8 +165,10 @@ CHIPSET(0x6907, ICELAND_, ICELAND) CHIPSET(0x6920, TONGA_, TONGA) CHIPSET(0x6921, TONGA_, TONGA) CHIPSET(0x6928, TONGA_, TONGA) +CHIPSET(0x6929, TONGA_, TONGA) CHIPSET(0x692B, TONGA_, TONGA) CHIPSET(0x692F, TONGA_, TONGA) +CHIPSET(0x6930, TONGA_, TONGA) CHIPSET(0x6938, TONGA_, TONGA) CHIPSET(0x6939, TONGA_, TONGA) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add new bonaire pci id
Module: Mesa Branch: master Commit: 71ba30f7788167c04d0968d286a387fce16afcce URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=71ba30f7788167c04d0968d286a387fce16afcce Author: Alex Deucher Date: Tue May 12 13:13:05 2015 -0400 radeonsi: add new bonaire pci id Reviewed-by: Marek Olšák Signed-off-by: Alex Deucher Cc: mesa-sta...@lists.freedesktop.org --- include/pci_ids/radeonsi_pci_ids.h |1 + 1 file changed, 1 insertion(+) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index 571e863..cd5da99 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -85,6 +85,7 @@ CHIPSET(0x6651, BONAIRE_6651, BONAIRE) CHIPSET(0x6658, BONAIRE_6658, BONAIRE) CHIPSET(0x665C, BONAIRE_665C, BONAIRE) CHIPSET(0x665D, BONAIRE_665D, BONAIRE) +CHIPSET(0x665F, BONAIRE_665F, BONAIRE) CHIPSET(0x9830, KABINI_9830, KABINI) CHIPSET(0x9831, KABINI_9831, KABINI) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (amdgpu): winsys/amdgpu: switch to new GTT_USWC definition
Module: Mesa
Branch: amdgpu
Commit: 6d06d4b70eee188c48a7e9bb194c426e5b4e0b4b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6d06d4b70eee188c48a7e9bb194c426e5b4e0b4b
Author: Jammy Zhou
Date: Thu May 7 09:49:38 2015 +0800
winsys/amdgpu: switch to new GTT_USWC definition
Signed-off-by: Jammy Zhou
Reviewed-by: Alex Deucher
---
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index 6c79c67..7aa1b02 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -263,7 +263,7 @@ static struct pb_buffer *amdgpu_bomgr_create_bo(struct
pb_manager *_mgr,
if (rdesc->initial_domain & RADEON_DOMAIN_GTT) {
request.preferred_heap |= AMDGPU_GEM_DOMAIN_GTT;
if (rdesc->flags & RADEON_FLAG_GTT_WC)
- request.flags |= AMDGPU_GEM_CREATE_CPU_GTT_WC;
+ request.flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
}
r = amdgpu_bo_alloc(rws->dev, &request, &result);
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Mesa (master): radeon/uvd: remove comment about RV770
Module: Mesa Branch: master Commit: 6b48c18b034cad91eac6ee2823e34053125a74c9 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b48c18b034cad91eac6ee2823e34053125a74c9 Author: Alex Deucher Date: Tue Aug 26 23:08:07 2014 -0400 radeon/uvd: remove comment about RV770 It doesn't seem to support field based decode after testing. Signed-off-by: Alex Deucher Reviewed-by: Christian König --- src/gallium/drivers/radeon/radeon_video.c |1 - 1 file changed, 1 deletion(-) diff --git a/src/gallium/drivers/radeon/radeon_video.c b/src/gallium/drivers/radeon/radeon_video.c index 6dcee45..2e683c4 100644 --- a/src/gallium/drivers/radeon/radeon_video.c +++ b/src/gallium/drivers/radeon/radeon_video.c @@ -254,7 +254,6 @@ int rvid_get_video_param(struct pipe_screen *screen, /* MPEG2 only with shaders and no support for interlacing on R6xx style UVD */ return codec != PIPE_VIDEO_FORMAT_MPEG12 && - /* TODO: RV770 might actually work */ rscreen->family > CHIP_RV770; default: break; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add new CIK pci ids
Module: Mesa Branch: master Commit: f50b6b489534f8f362953cbe08d37233f1eab669 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f50b6b489534f8f362953cbe08d37233f1eab669 Author: Alex Deucher Date: Thu Aug 21 11:13:17 2014 -0400 radeonsi: add new CIK pci ids Signed-off-by: Alex Deucher Cc: mesa-sta...@lists.freedesktop.org --- include/pci_ids/radeonsi_pci_ids.h |3 +++ 1 file changed, 3 insertions(+) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index 5099c74..6412f08 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -73,6 +73,8 @@ CHIPSET(0x666F, HAINAN_666F, HAINAN) CHIPSET(0x6640, BONAIRE_6640, BONAIRE) CHIPSET(0x6641, BONAIRE_6641, BONAIRE) +CHIPSET(0x6646, BONAIRE_6646, BONAIRE) +CHIPSET(0x6647, BONAIRE_6647, BONAIRE) CHIPSET(0x6649, BONAIRE_6649, BONAIRE) CHIPSET(0x6650, BONAIRE_6650, BONAIRE) CHIPSET(0x6651, BONAIRE_6651, BONAIRE) @@ -132,6 +134,7 @@ CHIPSET(0x1313, KAVERI_1313, KAVERI) CHIPSET(0x1315, KAVERI_1315, KAVERI) CHIPSET(0x1316, KAVERI_1316, KAVERI) CHIPSET(0x1317, KAVERI_1317, KAVERI) +CHIPSET(0x1318, KAVERI_1318, KAVERI) CHIPSET(0x131B, KAVERI_131B, KAVERI) CHIPSET(0x131C, KAVERI_131C, KAVERI) CHIPSET(0x131D, KAVERI_131D, KAVERI) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add new SI pci ids
Module: Mesa Branch: master Commit: 153df688349dd6e55fa4c280ed6c8abd02c5f890 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=153df688349dd6e55fa4c280ed6c8abd02c5f890 Author: Alex Deucher Date: Thu Aug 21 11:16:15 2014 -0400 radeonsi: add new SI pci ids Signed-off-by: Alex Deucher Cc: mesa-sta...@lists.freedesktop.org --- include/pci_ids/radeonsi_pci_ids.h |4 1 file changed, 4 insertions(+) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index 6412f08..571e863 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -38,6 +38,7 @@ CHIPSET(0x6828, VERDE_6828, VERDE) CHIPSET(0x6829, VERDE_6829, VERDE) CHIPSET(0x682A, VERDE_682A, VERDE) CHIPSET(0x682B, VERDE_682B, VERDE) +CHIPSET(0x682C, VERDE_682C, VERDE) CHIPSET(0x682D, VERDE_682D, VERDE) CHIPSET(0x682F, VERDE_682F, VERDE) CHIPSET(0x6830, VERDE_6830, VERDE) @@ -54,8 +55,11 @@ CHIPSET(0x6600, OLAND_6600, OLAND) CHIPSET(0x6601, OLAND_6601, OLAND) CHIPSET(0x6602, OLAND_6602, OLAND) CHIPSET(0x6603, OLAND_6603, OLAND) +CHIPSET(0x6604, OLAND_6604, OLAND) +CHIPSET(0x6605, OLAND_6605, OLAND) CHIPSET(0x6606, OLAND_6606, OLAND) CHIPSET(0x6607, OLAND_6607, OLAND) +CHIPSET(0x6608, OLAND_6608, OLAND) CHIPSET(0x6610, OLAND_6610, OLAND) CHIPSET(0x6611, OLAND_6611, OLAND) CHIPSET(0x6613, OLAND_6613, OLAND) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): winsys/radeon: fix nop packet padding for hawaii
Module: Mesa
Branch: master
Commit: 36771dc60fc3934b326eeff4aa6d3a4d438222eb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=36771dc60fc3934b326eeff4aa6d3a4d438222eb
Author: Andreas Boll
Date: Mon Aug 4 12:48:50 2014 +0200
winsys/radeon: fix nop packet padding for hawaii
The initial firmware for hawaii does not support type3 nop packet.
Detect the new hawaii firmware with query RADEON_INFO_ACCEL_WORKING2.
If the returned value is 3, then the new firmware is used.
This patch uses type2 for the old firmware and type3 for the new firmware.
It fixes the cases when the old firmware is used and the user wants to
manually enable acceleration.
The two possible scenarios are:
- the kernel has no support for the new firmware.
- the kernel has support for the new firmware but only the old firmware
is available.
Additionaly this patch disables GPU acceleration on hawaii if the kernel
returns a value < 2. In this case the kernel hasn't the required fixes
for proper acceleration.
v2:
- Fix indentation
- Use private struct radeon_drm_winsys instead of public struct radeon_info
- Rename r600_accel_working2 to accel_working2
v3:
- Use type2 nop packet for returned value < 3
v4:
- Fail to initialize winsys for returned value < 2
Cc: mesa-sta...@lists.freedesktop.org
Cc: Alex Deucher
Cc: Jérôme Glisse
Cc: Marek Olšák
Cc: Michel Dänzer
Signed-off-by: Andreas Boll
Signed-off-by: Alex Deucher
---
src/gallium/winsys/radeon/drm/radeon_drm_cs.c |6 +-
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 10 ++
src/gallium/winsys/radeon/drm/radeon_drm_winsys.h |1 +
3 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index a06ecb2..dd109af 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -446,8 +446,12 @@ static void radeon_drm_cs_flush(struct radeon_winsys_cs
*rcs,
case RING_GFX:
/* pad DMA ring to 8 DWs to meet CP fetch alignment requirements
* r6xx, requires at least 4 dw alignment to avoid a hw bug.
+ * hawaii with old firmware needs type2 nop packet.
+ * accel_working2 with value 2 indicates the new firmware.
*/
-if (cs->ws->info.chip_class <= SI) {
+if (cs->ws->info.chip_class <= SI ||
+(cs->ws->info.family == CHIP_HAWAII &&
+ cs->ws->accel_working2 < 3)) {
while (rcs->cdw & 7)
OUT_CS(&cs->base, 0x8000); /* type2 nop packet */
} else {
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 21567bb..820cc90 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -415,6 +415,16 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
radeon_get_drm_value(ws->fd, RADEON_INFO_MAX_SH_PER_SE, NULL,
&ws->info.max_sh_per_se);
+radeon_get_drm_value(ws->fd, RADEON_INFO_ACCEL_WORKING2, NULL,
+ &ws->accel_working2);
+if (ws->info.family == CHIP_HAWAII && ws->accel_working2 < 2) {
+fprintf(stderr, "radeon: GPU acceleration for Hawaii disabled, "
+"returned accel_working2 value %u is smaller than 2. "
+"Please install a newer kernel.\n",
+ws->accel_working2);
+return FALSE;
+}
+
if (radeon_get_drm_value(ws->fd, RADEON_INFO_SI_TILE_MODE_ARRAY, NULL,
ws->info.si_tile_mode_array)) {
ws->info.si_tile_mode_array_valid = TRUE;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
index ea6f7f0..aebc391 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.h
@@ -55,6 +55,7 @@ struct radeon_drm_winsys {
enum radeon_generation gen;
struct radeon_info info;
uint32_t va_start;
+uint32_t accel_working2;
struct pb_manager *kman;
struct pb_manager *cman_vram;
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Mesa (master): radeonsi: add support for Mullins asics.
Module: Mesa
Branch: master
Commit: aad669b1e90491f7c3951016456e8a2660d91a85
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aad669b1e90491f7c3951016456e8a2660d91a85
Author: Samuel Li
Date: Thu May 1 13:27:58 2014 -0400
radeonsi: add support for Mullins asics.
v2: name defaults to kabini for older llvm
v3: fix llvm version check
Signed-off-by: Samuel Li
Signed-off-by: Alex Deucher
Signed-off-by: Leo Liu
Reviewed-by: Marek Olšák
Reviewed-by: Tom Stellard
---
src/gallium/drivers/radeon/r600_pipe_common.c |7 +++
src/gallium/drivers/radeonsi/si_state.c |2 ++
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c |1 +
src/gallium/winsys/radeon/drm/radeon_winsys.h |1 +
4 files changed, 11 insertions(+)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 957186a..70c4d1a 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -293,6 +293,7 @@ static const char* r600_get_name(struct pipe_screen*
pscreen)
case CHIP_KAVERI: return "AMD KAVERI";
case CHIP_KABINI: return "AMD KABINI";
case CHIP_HAWAII: return "AMD HAWAII";
+ case CHIP_MULLINS: return "AMD MULLINS";
default: return "AMD unknown";
}
}
@@ -410,6 +411,12 @@ const char *r600_get_llvm_processor_name(enum
radeon_family family)
case CHIP_KABINI: return "kabini";
case CHIP_KAVERI: return "kaveri";
case CHIP_HAWAII: return "hawaii";
+ case CHIP_MULLINS:
+#if HAVE_LLVM >= 0x0305
+ return "mullins";
+#else
+ return "kabini";
+#endif
default: return "";
#endif
}
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 80f54e2..6d5408b 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -3101,6 +3101,8 @@ void si_init_config(struct si_context *sctx)
/* XXX todo */
case CHIP_KABINI:
/* XXX todo */
+ case CHIP_MULLINS:
+ /* XXX todo */
default:
si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
0x);
si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
0x);
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 7618316..e54e79e 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -276,6 +276,7 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
case CHIP_KAVERI:
case CHIP_KABINI:
case CHIP_HAWAII:
+case CHIP_MULLINS:
ws->info.chip_class = CIK;
break;
}
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h
b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index 1cb17bb..2d13550 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -130,6 +130,7 @@ enum radeon_family {
CHIP_KAVERI,
CHIP_KABINI,
CHIP_HAWAII,
+CHIP_MULLINS,
CHIP_LAST,
};
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Mesa (master): configure: bump up libdrm_radeon requirement to 2.4.54
Module: Mesa Branch: master Commit: b26175b6c386215c9f9cecef6e2db3502f1e9c56 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b26175b6c386215c9f9cecef6e2db3502f1e9c56 Author: Alex Deucher Date: Fri May 2 17:28:04 2014 -0400 configure: bump up libdrm_radeon requirement to 2.4.54 Required for Mullins. Signed-off-by: Alex Deucher --- configure.ac |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/configure.ac b/configure.ac index 7251a5b..e77ed77 100644 --- a/configure.ac +++ b/configure.ac @@ -28,7 +28,7 @@ AC_SUBST([OSMESA_VERSION]) dnl Versions for external dependencies LIBDRM_REQUIRED=2.4.38 -LIBDRM_RADEON_REQUIRED=2.4.53 +LIBDRM_RADEON_REQUIRED=2.4.54 LIBDRM_INTEL_REQUIRED=2.4.52 LIBDRM_NVVIEUX_REQUIRED=2.4.33 LIBDRM_NOUVEAU_REQUIRED="2.4.33 libdrm >= 2.4.41" ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add Mullins pci ids.
Module: Mesa Branch: master Commit: 7f8f6790e4ccf455427e7a2977d90a411fd6cc37 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f8f6790e4ccf455427e7a2977d90a411fd6cc37 Author: Samuel Li Date: Tue Nov 12 15:49:55 2013 -0500 radeonsi: add Mullins pci ids. Signed-off-by: Samuel Li Signed-off-by: Alex Deucher Reviewed-by: Marek Olšák --- include/pci_ids/radeonsi_pci_ids.h | 17 + 1 file changed, 17 insertions(+) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index 7b42d5e..5099c74 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -97,6 +97,23 @@ CHIPSET(0x983D, KABINI_983D, KABINI) CHIPSET(0x983E, KABINI_983E, KABINI) CHIPSET(0x983F, KABINI_983F, KABINI) +CHIPSET(0x9850, MULLINS_9850, MULLINS) +CHIPSET(0x9851, MULLINS_9851, MULLINS) +CHIPSET(0x9852, MULLINS_9852, MULLINS) +CHIPSET(0x9853, MULLINS_9853, MULLINS) +CHIPSET(0x9854, MULLINS_9854, MULLINS) +CHIPSET(0x9855, MULLINS_9855, MULLINS) +CHIPSET(0x9856, MULLINS_9856, MULLINS) +CHIPSET(0x9857, MULLINS_9857, MULLINS) +CHIPSET(0x9858, MULLINS_9858, MULLINS) +CHIPSET(0x9859, MULLINS_9859, MULLINS) +CHIPSET(0x985A, MULLINS_985A, MULLINS) +CHIPSET(0x985B, MULLINS_985B, MULLINS) +CHIPSET(0x985C, MULLINS_985C, MULLINS) +CHIPSET(0x985D, MULLINS_985D, MULLINS) +CHIPSET(0x985E, MULLINS_985E, MULLINS) +CHIPSET(0x985F, MULLINS_985F, MULLINS) + CHIPSET(0x1304, KAVERI_1304, KAVERI) CHIPSET(0x1305, KAVERI_1305, KAVERI) CHIPSET(0x1306, KAVERI_1306, KAVERI) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: fix num banks selection on SI for dma setup (v2)
Module: Mesa
Branch: master
Commit: 7489f3eedafbdad905158196873c8b3f5ccb546f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7489f3eedafbdad905158196873c8b3f5ccb546f
Author: Alex Deucher
Date: Fri Apr 18 13:03:37 2014 -0400
radeonsi: fix num banks selection on SI for dma setup (v2)
The number of banks varies based on the tile mode index
just like CIK.
Bug:
https://bugs.freedesktop.org/show_bug.cgi?id=77533
v2: fix ordering for nbanks calculation for consistency
Signed-off-by: Alex Deucher
---
src/gallium/drivers/radeonsi/si_dma.c | 18 ++
src/gallium/drivers/radeonsi/si_state.c | 24
src/gallium/drivers/radeonsi/si_state.h |1 +
3 files changed, 19 insertions(+), 24 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_dma.c
b/src/gallium/drivers/radeonsi/si_dma.c
index afe8a3a..97ea08b 100644
--- a/src/gallium/drivers/radeonsi/si_dma.c
+++ b/src/gallium/drivers/radeonsi/si_dma.c
@@ -45,21 +45,6 @@ static unsigned si_array_mode(unsigned mode)
}
}
-static uint32_t si_num_banks(uint32_t nbanks)
-{
- switch (nbanks) {
- case 2:
- return V_009910_ADDR_SURF_2_BANK;
- case 4:
- return V_009910_ADDR_SURF_4_BANK;
- case 8:
- default:
- return V_009910_ADDR_SURF_8_BANK;
- case 16:
- return V_009910_ADDR_SURF_16_BANK;
- }
-}
-
static uint32_t si_micro_tile_mode(struct si_screen *sscreen, unsigned
tile_mode)
{
if (sscreen->b.info.si_tile_mode_array_valid) {
@@ -161,7 +146,6 @@ static void si_dma_copy_tile(struct si_context *ctx,
sub_cmd = SI_DMA_COPY_TILED;
lbpp = util_logbase2(bpp);
pitch_tile_max = ((pitch / bpp) / 8) - 1;
- nbanks = si_num_banks(ctx->screen->b.tiling_info.num_banks);
if (dst_mode == RADEON_SURF_MODE_LINEAR) {
/* T2L */
@@ -185,6 +169,7 @@ static void si_dma_copy_tile(struct si_context *ctx,
bank_h = cik_bank_wh(rsrc->surface.bankh);
bank_w = cik_bank_wh(rsrc->surface.bankw);
mt_aspect = cik_macro_tile_aspect(rsrc->surface.mtilea);
+ nbanks = cik_num_banks(sscreen, rsrc->surface.bpe,
rsrc->surface.tile_split);
tile_split = cik_tile_split(rsrc->surface.tile_split);
tile_mode_index = si_tile_mode_index(rsrc, src_level,
util_format_has_stencil(util_format_description(src->format)));
@@ -212,6 +197,7 @@ static void si_dma_copy_tile(struct si_context *ctx,
bank_h = cik_bank_wh(rdst->surface.bankh);
bank_w = cik_bank_wh(rdst->surface.bankw);
mt_aspect = cik_macro_tile_aspect(rdst->surface.mtilea);
+ nbanks = cik_num_banks(sscreen, rdst->surface.bpe,
rdst->surface.tile_split);
tile_split = cik_tile_split(rdst->surface.tile_split);
tile_mode_index = si_tile_mode_index(rdst, dst_level,
util_format_has_stencil(util_format_description(dst->format)));
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index ab9c4cc..211a615 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -47,23 +47,31 @@ static void si_init_atom(struct r600_atom *atom, struct
r600_atom **list_elem,
*list_elem = atom;
}
-static uint32_t cik_num_banks(struct si_screen *sscreen, unsigned bpe,
unsigned tile_split)
+uint32_t cik_num_banks(struct si_screen *sscreen, unsigned bpe, unsigned
tile_split)
{
- if (sscreen->b.info.cik_macrotile_mode_array_valid) {
- unsigned index, tileb;
+ unsigned index, tileb;
- tileb = 8 * 8 * bpe;
- tileb = MIN2(tile_split, tileb);
+ tileb = 8 * 8 * bpe;
+ tileb = MIN2(tile_split, tileb);
- for (index = 0; tileb > 64; index++) {
- tileb >>= 1;
- }
+ for (index = 0; tileb > 64; index++) {
+ tileb >>= 1;
+ }
+ if ((sscreen->b.chip_class == CIK) &&
+ sscreen->b.info.cik_macrotile_mode_array_valid) {
assert(index < 16);
return (sscreen->b.info.cik_macrotile_mode_array[index] >> 6) &
0x3;
}
+ if ((sscreen->b.chip_class == SI) &&
+ sscreen->b.info.si_tile_mode_array_valid) {
+ assert(index < 16);
+
+ return (sscreen->b.info.si_tile_mode_array[index] >> 20) & 0x3;
+ }
+
/* The old way. */
switch (sscreen->b.tiling_info.num_banks) {
case 2:
diff --git a/src/gallium/drivers/radeonsi/si_state.h
b/src/gallium/drivers/radeonsi/si_state.h
index c080600..
Mesa (master): radeon/uvd: fix typo in documentation
Module: Mesa Branch: master Commit: 5f23a2d9c2df7e7b860246be37b495e7fbea76ca URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f23a2d9c2df7e7b860246be37b495e7fbea76ca Author: Dieter Nützel Date: Tue Mar 4 17:49:01 2014 -0500 radeon/uvd: fix typo in documentation s/grap/grab/ Signed-off-by: Alex Deucher --- src/gallium/drivers/radeon/radeon_uvd.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeon/radeon_uvd.c b/src/gallium/drivers/radeon/radeon_uvd.c index 3075905..8ca8dc3 100644 --- a/src/gallium/drivers/radeon/radeon_uvd.c +++ b/src/gallium/drivers/radeon/radeon_uvd.c @@ -137,7 +137,7 @@ static void send_msg_buf(struct ruvd_decoder *dec) if (!dec->msg || !dec->fb) return; - /* grap the current message buffer */ + /* grab the current message buffer */ buf = &dec->msg_fb_buffers[dec->cur_buffer]; /* unmap the buffer */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeon: reverse DBG_NO_HYPERZ logic
Module: Mesa
Branch: master
Commit: 01e637114914453451becc0dc8afe60faff48d84
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=01e637114914453451becc0dc8afe60faff48d84
Author: Alex Deucher
Date: Wed Feb 12 12:00:17 2014 -0500
radeon: reverse DBG_NO_HYPERZ logic
Change the flag to DBG_HYPERZ and reverse the logic
so setting the flag enabled the feature. This disables
hyperz on r600g and radeonsi by default. It can be
enabled by setting the env var. There are just too
many issues with certain apps so leave it disabled for
now until we sort out the issues with the problematic
apps.
Bugs:
https://bugs.freedesktop.org/show_bug.cgi?id=58660
https://bugs.freedesktop.org/show_bug.cgi?id=64471
https://bugs.freedesktop.org/show_bug.cgi?id=66352
https://bugs.freedesktop.org/show_bug.cgi?id=68799
https://bugs.freedesktop.org/show_bug.cgi?id=72685
https://bugs.freedesktop.org/show_bug.cgi?id=73088
https://bugs.freedesktop.org/show_bug.cgi?id=74428
https://bugs.freedesktop.org/show_bug.cgi?id=74803
https://bugs.freedesktop.org/show_bug.cgi?id=74863
https://bugs.freedesktop.org/show_bug.cgi?id=74892
https://bugzilla.kernel.org/show_bug.cgi?id=70411
Signed-off-by: Alex Deucher
Cc: "10.1" "10.0"
Acked-by: Marek Olšák
---
src/gallium/drivers/r600/r600_pipe.c |4 ++--
src/gallium/drivers/radeon/r600_pipe_common.c |2 +-
src/gallium/drivers/radeon/r600_pipe_common.h |2 +-
src/gallium/drivers/radeon/r600_texture.c |2 +-
4 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index 796f0f5..8ea192a 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -584,8 +584,8 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys
*ws)
rscreen->b.debug_flags |= DBG_COMPUTE;
if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE))
rscreen->b.debug_flags |= DBG_FS | DBG_VS | DBG_GS | DBG_PS |
DBG_CS;
- if (!debug_get_bool_option("R600_HYPERZ", TRUE))
- rscreen->b.debug_flags |= DBG_NO_HYPERZ;
+ if (debug_get_bool_option("R600_HYPERZ", FALSE))
+ rscreen->b.debug_flags |= DBG_HYPERZ;
if (!debug_get_bool_option("R600_LLVM", TRUE))
rscreen->b.debug_flags |= DBG_NO_LLVM;
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 7af8124..dbca157 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -137,7 +137,7 @@ static const struct debug_named_value
common_debug_options[] = {
{ "ps", DBG_PS, "Print pixel shaders" },
{ "cs", DBG_CS, "Print compute shaders" },
- { "nohyperz", DBG_NO_HYPERZ, "Disable Hyper-Z" },
+ { "hyperz", DBG_HYPERZ, "Enable Hyper-Z" },
/* GL uses the word INVALIDATE, gallium uses the word DISCARD */
{ "noinvalrange", DBG_NO_DISCARD_RANGE, "Disable handling of
INVALIDATE_RANGE map flags" },
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 7193a0f..2fbc6a3 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -83,7 +83,7 @@
#define DBG_PS (1 << 11)
#define DBG_CS (1 << 12)
/* features */
-#define DBG_NO_HYPERZ (1 << 13)
+#define DBG_HYPERZ (1 << 13)
#define DBG_NO_DISCARD_RANGE (1 << 14)
/* The maximum allowed bit is 15. */
diff --git a/src/gallium/drivers/radeon/r600_texture.c
b/src/gallium/drivers/radeon/r600_texture.c
index 356e0af..2cfab51 100644
--- a/src/gallium/drivers/radeon/r600_texture.c
+++ b/src/gallium/drivers/radeon/r600_texture.c
@@ -596,7 +596,7 @@ r600_texture_create_object(struct pipe_screen *screen,
if (rtex->is_depth) {
if (!(base->flags & (R600_RESOURCE_FLAG_TRANSFER |
R600_RESOURCE_FLAG_FLUSHED_DEPTH)) &&
- !(rscreen->debug_flags & DBG_NO_HYPERZ)) {
+ (rscreen->debug_flags & DBG_HYPERZ)) {
r600_texture_allocate_htile(rscreen, rtex);
}
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Mesa (master): r600g: fix SUMO2 pci id
Module: Mesa Branch: master Commit: e2d53fac1c5b18f5c9e95d39d4e2be4703b0b363 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2d53fac1c5b18f5c9e95d39d4e2be4703b0b363 Author: Alex Deucher Date: Tue Dec 24 15:22:31 2013 -0500 r600g: fix SUMO2 pci id 0x9649 is sumo2, not sumo. Signed-off-by: Alex Deucher CC: "9.2" "10.0" --- include/pci_ids/r600_pci_ids.h |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/pci_ids/r600_pci_ids.h b/include/pci_ids/r600_pci_ids.h index 5036a83..533c9f3 100644 --- a/include/pci_ids/r600_pci_ids.h +++ b/include/pci_ids/r600_pci_ids.h @@ -208,7 +208,7 @@ CHIPSET(0x9644, SUMO2_9644, SUMO2) CHIPSET(0x9645, SUMO2_9645, SUMO2) CHIPSET(0x9647, SUMO_9647, SUMO) CHIPSET(0x9648, SUMO_9648, SUMO) -CHIPSET(0x9649, SUMO_9649, SUMO) +CHIPSET(0x9649, SUMO2_9649, SUMO2) CHIPSET(0x964a, SUMO_964A, SUMO) CHIPSET(0x964b, SUMO_964B, SUMO) CHIPSET(0x964c, SUMO_964C, SUMO) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add support for Hawaii asics (v2)
Module: Mesa Branch: master Commit: f5778f152b250cb233f4bee021baae916e504afe URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5778f152b250cb233f4bee021baae916e504afe Author: Alex Deucher Date: Tue Sep 24 12:12:29 2013 -0400 radeonsi: add support for Hawaii asics (v2) Update additional register fields. Reviewed-by: Michel Dänzer Signed-off-by: Alex Deucher --- src/gallium/drivers/radeonsi/radeonsi_pipe.c |2 ++ src/gallium/drivers/radeonsi/si_state.c |4 src/gallium/drivers/radeonsi/sid.h|9 + src/gallium/winsys/radeon/drm/radeon_drm_winsys.c |1 + src/gallium/winsys/radeon/drm/radeon_winsys.h |1 + 5 files changed, 17 insertions(+), 0 deletions(-) diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c b/src/gallium/drivers/radeonsi/radeonsi_pipe.c index b79a58e..1f92791 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c +++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c @@ -258,6 +258,7 @@ const char *r600_get_llvm_processor_name(enum radeon_family family) case CHIP_BONAIRE: return "bonaire"; case CHIP_KABINI: return "kabini"; case CHIP_KAVERI: return "kaveri"; + case CHIP_HAWAII: return "hawaii"; default: return ""; #endif } @@ -274,6 +275,7 @@ static const char *r600_get_family_name(enum radeon_family family) case CHIP_BONAIRE: return "AMD BONAIRE"; case CHIP_KAVERI: return "AMD KAVERI"; case CHIP_KABINI: return "AMD KABINI"; + case CHIP_HAWAII: return "AMD HAWAII"; default: return "AMD unknown"; } } diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 72368d8..2742836 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -3136,6 +3136,10 @@ void si_init_config(struct r600_context *rctx) si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x1612); si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x); break; + case CHIP_HAWAII: + si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x3a00161a); + si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1, 0x002e); + break; case CHIP_KAVERI: /* XXX todo */ case CHIP_KABINI: diff --git a/src/gallium/drivers/radeonsi/sid.h b/src/gallium/drivers/radeonsi/sid.h index 021f4eb..aab39fc 100644 --- a/src/gallium/drivers/radeonsi/sid.h +++ b/src/gallium/drivers/radeonsi/sid.h @@ -5403,6 +5403,8 @@ #define V_02803C_X_ADDR_SURF_P8_32X32_16X16 0x0C #define V_02803C_X_ADDR_SURF_P8_32X32_16X32 0x0D #define V_02803C_X_ADDR_SURF_P8_32X64_32X32 0x0E +#define V_02803C_X_ADDR_SURF_P16_32X32_8X16 0x10 +#define V_02803C_X_ADDR_SURF_P16_32X32_16X160x11 #define S_02803C_BANK_WIDTH(x) (((x) & 0x03) << 13) #define G_02803C_BANK_WIDTH(x) (((x) >> 13) & 0x03) #define C_02803C_BANK_WIDTH 0x9FFF @@ -5731,6 +5733,13 @@ #define V_028350_RASTER_CONFIG_PKR_YSEL_1 0x01 #define V_028350_RASTER_CONFIG_PKR_YSEL_2 0x02 #define V_028350_RASTER_CONFIG_PKR_YSEL_3 0x03 +#define S_028350_PKR_XSEL2(x) (((x) & 0x03) << 14) +#define G_028350_PKR_XSEL2(x) (((x) >> 14) & 0x03) +#define C_028350_PKR_XSEL2 0x3FFF +#define V_028350_RASTER_CONFIG_PKR_XSEL2_0 0x00 +#define V_028350_RASTER_CONFIG_PKR_XSEL2_1 0x01 +#define V_028350_RASTER_CONFIG_PKR_XSEL2_2 0x02 +#define V_028350_RASTER_CONFIG_PKR_XSEL2_3 0x03 #define S_028350_SC_MAP(x) (((x) & 0x03) << 16) #define G_028350_SC_MAP(x) (((x) >> 16) & 0x03) #define C_028350_SC_MAP 0xFFFC diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c index 8a8f180..1860810 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c @@ -330,6 +330,7 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws) case CHIP_BONAIRE: case CHIP_KAVERI:
Mesa (master): radeonsi: add Hawaii pci ids
Module: Mesa Branch: master Commit: 469b42ee21d6bc530200c76cb0e73b0b461ab6e8 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=469b42ee21d6bc530200c76cb0e73b0b461ab6e8 Author: Alex Deucher Date: Tue Sep 24 12:13:42 2013 -0400 radeonsi: add Hawaii pci ids Reviewed-by: Michel Dänzer Signed-off-by: Alex Deucher --- include/pci_ids/radeonsi_pci_ids.h | 13 + 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index 0fdd1ad..7b42d5e 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -118,3 +118,16 @@ CHIPSET(0x1317, KAVERI_1317, KAVERI) CHIPSET(0x131B, KAVERI_131B, KAVERI) CHIPSET(0x131C, KAVERI_131C, KAVERI) CHIPSET(0x131D, KAVERI_131D, KAVERI) + +CHIPSET(0x67A0, HAWAII_67A0, HAWAII) +CHIPSET(0x67A1, HAWAII_67A1, HAWAII) +CHIPSET(0x67A2, HAWAII_67A2, HAWAII) +CHIPSET(0x67A8, HAWAII_67A8, HAWAII) +CHIPSET(0x67A9, HAWAII_67A9, HAWAII) +CHIPSET(0x67AA, HAWAII_67AA, HAWAII) +CHIPSET(0x67B0, HAWAII_67B0, HAWAII) +CHIPSET(0x67B1, HAWAII_67B1, HAWAII) +CHIPSET(0x67B8, HAWAII_67B8, HAWAII) +CHIPSET(0x67B9, HAWAII_67B9, HAWAII) +CHIPSET(0x67BA, HAWAII_67BA, HAWAII) +CHIPSET(0x67BE, HAWAII_67BE, HAWAII) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): st/xorg: Include u_surface.h for u_copy_rect
Module: Mesa Branch: master Commit: d2eb281fb2322fd4b73d558e07883ed2f85edf25 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2eb281fb2322fd4b73d558e07883ed2f85edf25 Author: Alex Deucher Date: Tue Oct 1 11:15:26 2013 -0400 st/xorg: Include u_surface.h for u_copy_rect Fixes build errors. Signed-off-by: Alex Deucher Reviewed-by: Brian Paul --- src/gallium/state_trackers/xorg/xorg_crtc.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/gallium/state_trackers/xorg/xorg_crtc.c b/src/gallium/state_trackers/xorg/xorg_crtc.c index 3cbffb5..0ab41b4 100644 --- a/src/gallium/state_trackers/xorg/xorg_crtc.c +++ b/src/gallium/state_trackers/xorg/xorg_crtc.c @@ -53,6 +53,7 @@ #include "state_tracker/drm_driver.h" #include "util/u_inlines.h" #include "util/u_rect.h" +#include "util/u_surface.h" #ifdef HAVE_LIBKMS #include "libkms/libkms.h" ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: remove DMA padding
Module: Mesa
Branch: master
Commit: 9bc47dbe5062fe1f462f62bf3a2dda7b2f3ddea3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9bc47dbe5062fe1f462f62bf3a2dda7b2f3ddea3
Author: Alex Deucher
Date: Fri Sep 6 19:10:27 2013 -0400
r600g: remove DMA padding
This is now handled in the winsys.
Reviewed-by: Marek Olšák
Signed-off-by: Alex Deucher
---
src/gallium/drivers/r600/r600_pipe.c |9 -
1 files changed, 0 insertions(+), 9 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index b4b8c88..aa5cadf 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -217,20 +217,11 @@ static void r600_flush_dma_ring(void *ctx, unsigned flags)
{
struct r600_context *rctx = (struct r600_context *)ctx;
struct radeon_winsys_cs *cs = rctx->b.rings.dma.cs;
- unsigned padding_dw, i;
if (!cs->cdw) {
return;
}
- /* Pad the DMA CS to a multiple of 8 dwords. */
- padding_dw = 8 - cs->cdw % 8;
- if (padding_dw < 8) {
- for (i = 0; i < padding_dw; i++) {
- cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0,
0);
- }
- }
-
rctx->b.rings.dma.flushing = true;
rctx->b.ws->cs_flush(cs, flags, 0);
rctx->b.rings.dma.flushing = false;
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Mesa (master): radeon/winsys: pad IBs to a multiple of 8 DWs
Module: Mesa
Branch: master
Commit: a81beee37e0dd7b75422448420e8e8b0b4b76c1e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a81beee37e0dd7b75422448420e8e8b0b4b76c1e
Author: Alex Deucher
Date: Fri Sep 6 16:43:34 2013 -0400
radeon/winsys: pad IBs to a multiple of 8 DWs
This aligns the gfx, compute, and dma IBs to 8 DW boundries.
This aligns the the IB to the fetch size of the CP for optimal
performance. Additionally, r6xx hardware requires at least 4
DW alignment to avoid a hw bug. This also aligns the DMA
IBs to 8 DW which is required for the DMA engine. This
alignment is already handled in the gallium driver, but that
patch can be removed now that it's done in the winsys.
Reviewed-by: Marek Olšák
Signed-off-by: Alex Deucher
CC: "9.2"
CC: "9.1"
---
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 30 +
1 files changed, 30 insertions(+), 0 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index ea0c99d..38a9209 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -466,6 +466,36 @@ static void radeon_drm_cs_flush(struct radeon_winsys_cs
*rcs, unsigned flags, ui
struct radeon_drm_cs *cs = radeon_drm_cs(rcs);
struct radeon_cs_context *tmp;
+switch (cs->base.ring_type) {
+case RING_DMA:
+ /* pad DMA ring to 8 DWs */
+ if (cs->ws->info.chip_class <= SI) {
+ while (rcs->cdw & 7)
+ OUT_CS(&cs->base, 0xf000); /* NOP packet */
+ } else {
+ while (rcs->cdw & 7)
+ OUT_CS(&cs->base, 0x); /* NOP packet */
+ }
+ break;
+case RING_GFX:
+ /* pad DMA ring to 8 DWs to meet CP fetch alignment requirements
+* r6xx, requires at least 4 dw alignment to avoid a hw bug.
+*/
+if (flags & RADEON_FLUSH_COMPUTE) {
+ if (cs->ws->info.chip_class <= SI) {
+ while (rcs->cdw & 7)
+ OUT_CS(&cs->base, 0x8000); /* type2 nop
packet */
+ } else {
+ while (rcs->cdw & 7)
+ OUT_CS(&cs->base, 0x1000); /* type3 nop
packet */
+ }
+ } else {
+ while (rcs->cdw & 7)
+ OUT_CS(&cs->base, 0x8000); /* type2 nop packet
*/
+ }
+ break;
+}
+
if (rcs->cdw > RADEON_MAX_CMDBUF_DWORDS) {
fprintf(stderr, "radeon: command stream overflowed\n");
}
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Mesa (master): radeonsi: add berlin pci ids
Module: Mesa Branch: master Commit: 18805b16c8a86ad9de4b5bb9afdce576f528f745 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=18805b16c8a86ad9de4b5bb9afdce576f528f745 Author: Alex Deucher Date: Thu Jan 24 19:46:50 2013 -0500 radeonsi: add berlin pci ids Signed-off-by: Alex Deucher --- include/pci_ids/radeonsi_pci_ids.h | 22 ++ 1 files changed, 22 insertions(+), 0 deletions(-) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index 2156728..0fdd1ad 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -96,3 +96,25 @@ CHIPSET(0x983C, KABINI_983C, KABINI) CHIPSET(0x983D, KABINI_983D, KABINI) CHIPSET(0x983E, KABINI_983E, KABINI) CHIPSET(0x983F, KABINI_983F, KABINI) + +CHIPSET(0x1304, KAVERI_1304, KAVERI) +CHIPSET(0x1305, KAVERI_1305, KAVERI) +CHIPSET(0x1306, KAVERI_1306, KAVERI) +CHIPSET(0x1307, KAVERI_1307, KAVERI) +CHIPSET(0x1309, KAVERI_1309, KAVERI) +CHIPSET(0x130A, KAVERI_130A, KAVERI) +CHIPSET(0x130B, KAVERI_130B, KAVERI) +CHIPSET(0x130C, KAVERI_130C, KAVERI) +CHIPSET(0x130D, KAVERI_130D, KAVERI) +CHIPSET(0x130E, KAVERI_130E, KAVERI) +CHIPSET(0x130F, KAVERI_130F, KAVERI) +CHIPSET(0x1310, KAVERI_1310, KAVERI) +CHIPSET(0x1311, KAVERI_1311, KAVERI) +CHIPSET(0x1312, KAVERI_1312, KAVERI) +CHIPSET(0x1313, KAVERI_1313, KAVERI) +CHIPSET(0x1315, KAVERI_1315, KAVERI) +CHIPSET(0x1316, KAVERI_1316, KAVERI) +CHIPSET(0x1317, KAVERI_1317, KAVERI) +CHIPSET(0x131B, KAVERI_131B, KAVERI) +CHIPSET(0x131C, KAVERI_131C, KAVERI) +CHIPSET(0x131D, KAVERI_131D, KAVERI) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: disable GPUVM by default
Module: Mesa
Branch: master
Commit: c88783047e2a0faa39d6f3ac6fbd3f26a480d5d3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c88783047e2a0faa39d6f3ac6fbd3f26a480d5d3
Author: Alex Deucher
Date: Thu Aug 8 21:11:22 2013 -0400
r600g: disable GPUVM by default
Cayman and trinity systems still seem to suffer from
stability problems with GPUVM. This also fixes compute
on these asics. It can still be enabled for testing
by setting env var RADEON_VA=true.
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=65958
Signed-off-by: Alex Deucher
CC: "9.2"
CC: "9.1"
Reviewed-by: Christian König
---
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 033e78f..69c42a0 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -404,7 +404,7 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
&ws->info.r600_ib_vm_max_size))
ws->info.r600_virtual_address = FALSE;
}
- if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", TRUE))
+ if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", FALSE))
ws->info.r600_virtual_address = FALSE;
}
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Mesa (master): r600g: don't use the CB/DB CP COHER logic on r6xx
Module: Mesa
Branch: master
Commit: e0a7565832b567a2ffc65b08d21500ba5d914415
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e0a7565832b567a2ffc65b08d21500ba5d914415
Author: Alex Deucher
Date: Fri Jul 12 09:31:28 2013 -0400
r600g: don't use the CB/DB CP COHER logic on r6xx
There are hw bugs. Flush and inv event is sufficient.
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=66837
Signed-off-by: Alex Deucher
---
src/gallium/drivers/r600/r600_hw_context.c | 12 ++--
1 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_hw_context.c
b/src/gallium/drivers/r600/r600_hw_context.c
index 652329b..7bb4825 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -246,13 +246,21 @@ void r600_flush_emit(struct r600_context *rctx)
cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
}
- if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB) {
+ /* Don't use the DB CP COHER logic on r6xx.
+* There are hw bugs.
+*/
+ if (rctx->chip_class >= R700 &&
+ (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_DB)) {
cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
S_0085F0_DB_DEST_BASE_ENA(1) |
S_0085F0_SMX_ACTION_ENA(1);
}
- if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB) {
+ /* Don't use the CB CP COHER logic on r6xx.
+* There are hw bugs.
+*/
+ if (rctx->chip_class >= R700 &&
+ (rctx->flags & R600_CONTEXT_FLUSH_AND_INV_CB)) {
cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
S_0085F0_CB0_DEST_BASE_ENA(1) |
S_0085F0_CB1_DEST_BASE_ENA(1) |
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Mesa (master): radeon: bump libdrm_radeon requirement for CIK support
Module: Mesa Branch: master Commit: 77300bacaf991c4f052999466cf7a5e48704114b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=77300bacaf991c4f052999466cf7a5e48704114b Author: Alex Deucher Date: Thu Jul 11 18:51:32 2013 -0400 radeon: bump libdrm_radeon requirement for CIK support Signed-off-by: Alex Deucher --- configure.ac |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/configure.ac b/configure.ac index 3a0cd77..2265e85 100644 --- a/configure.ac +++ b/configure.ac @@ -31,7 +31,7 @@ AC_SUBST([OSMESA_VERSION]) dnl Versions for external dependencies LIBDRM_REQUIRED=2.4.24 -LIBDRM_RADEON_REQUIRED=2.4.45 +LIBDRM_RADEON_REQUIRED=2.4.46 LIBDRM_INTEL_REQUIRED=2.4.38 LIBDRM_NVVIEUX_REQUIRED=2.4.33 LIBDRM_NOUVEAU_REQUIRED="2.4.33 libdrm >= 2.4.41" ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: x/ y coordinates must be divided by block dim in dma blit
Module: Mesa
Branch: master
Commit: 9974593dfbf87e95a4c396772b82c302d663d1f8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9974593dfbf87e95a4c396772b82c302d663d1f8
Author: Christoph Bumiller
Date: Fri Jul 5 20:55:36 2013 +0200
r600g: x/y coordinates must be divided by block dim in dma blit
Note: this is a candidate for the 9.1 branch.
Reviewed-by: Marek Olšák
Signed-off-by: Alex Deucher
---
src/gallium/drivers/r600/evergreen_state.c | 10 --
src/gallium/drivers/r600/r600_state.c | 10 --
2 files changed, 16 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 4166b18..980e75a 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3733,6 +3733,7 @@ boolean evergreen_dma_blit(struct pipe_context *ctx,
struct r600_texture *rdst = (struct r600_texture*)dst;
unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
unsigned src_w, dst_w;
+ unsigned src_x, src_y;
if (rctx->rings.dma.cs == NULL) {
return FALSE;
@@ -3741,6 +3742,11 @@ boolean evergreen_dma_blit(struct pipe_context *ctx,
return FALSE;
}
+ src_x = util_format_get_nblocksx(src->format, src_box->x);
+ dst_x = util_format_get_nblocksx(src->format, dst_x);
+ src_y = util_format_get_nblocksy(src->format, src_box->y);
+ dst_y = util_format_get_nblocksy(src->format, dst_y);
+
bpp = rdst->surface.bpe;
dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
src_pitch = rsrc->surface.level[src_level].pitch_bytes;
@@ -3785,7 +3791,7 @@ boolean evergreen_dma_blit(struct pipe_context *ctx,
*/
src_offset= rsrc->surface.level[src_level].offset;
src_offset += rsrc->surface.level[src_level].slice_size *
src_box->z;
- src_offset += src_box->y * src_pitch + src_box->x * bpp;
+ src_offset += src_y * src_pitch + src_x * bpp;
dst_offset = rdst->surface.level[dst_level].offset;
dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
dst_offset += dst_y * dst_pitch + dst_x * bpp;
@@ -3793,7 +3799,7 @@ boolean evergreen_dma_blit(struct pipe_context *ctx,
src_box->height * src_pitch);
} else {
evergreen_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y,
dst_z,
- src, src_level, src_box->x, src_box->y,
src_box->z,
+ src, src_level, src_x, src_y,
src_box->z,
copy_height, dst_pitch, bpp);
}
return TRUE;
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 759f71f..4590fdd 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -3132,6 +3132,7 @@ boolean r600_dma_blit(struct pipe_context *ctx,
struct r600_texture *rdst = (struct r600_texture*)dst;
unsigned dst_pitch, src_pitch, bpp, dst_mode, src_mode, copy_height;
unsigned src_w, dst_w;
+ unsigned src_x, src_y;
if (rctx->rings.dma.cs == NULL) {
return FALSE;
@@ -3140,6 +3141,11 @@ boolean r600_dma_blit(struct pipe_context *ctx,
return FALSE;
}
+ src_x = util_format_get_nblocksx(src->format, src_box->x);
+ dst_x = util_format_get_nblocksx(src->format, dst_x);
+ src_y = util_format_get_nblocksy(src->format, src_box->y);
+ dst_y = util_format_get_nblocksy(src->format, dst_y);
+
bpp = rdst->surface.bpe;
dst_pitch = rdst->surface.level[dst_level].pitch_bytes;
src_pitch = rsrc->surface.level[src_level].pitch_bytes;
@@ -3172,7 +3178,7 @@ boolean r600_dma_blit(struct pipe_context *ctx,
*/
src_offset= rsrc->surface.level[src_level].offset;
src_offset += rsrc->surface.level[src_level].slice_size *
src_box->z;
- src_offset += src_box->y * src_pitch + src_box->x * bpp;
+ src_offset += src_y * src_pitch + src_x * bpp;
dst_offset = rdst->surface.level[dst_level].offset;
dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
dst_offset += dst_y * dst_pitch + dst_x * bpp;
@@ -3184,7 +3190,7 @@ boolean r600_dma_blit(struct pipe_context *ctx,
r600_dma_copy(rctx, dst, src, dst_offset, src_offset, size);
} else {
return r600_dma_copy_tile(rctx, dst, dst_level, dst_x, dst_y,
dst_z,
- src, src_level, src_box->x, src_box->y,
src_box->z,
+
Mesa (master): radeonsi: add llvm processor names for CIK
Module: Mesa Branch: master Commit: 1357624abc19dfc7b2086b2fd6729826ec229a65 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1357624abc19dfc7b2086b2fd6729826ec229a65 Author: Alex Deucher Date: Fri Jun 7 14:08:25 2013 -0400 radeonsi: add llvm processor names for CIK Requires updated llvm. Signed-off-by: Alex Deucher --- src/gallium/drivers/radeonsi/radeonsi_pipe.c |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c b/src/gallium/drivers/radeonsi/radeonsi_pipe.c index 9aa8863..f5e6b1b 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c +++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c @@ -299,6 +299,9 @@ const char *r600_get_llvm_processor_name(enum radeon_family family) case CHIP_VERDE: return "verde"; case CHIP_OLAND: return "oland"; case CHIP_HAINAN: return "hainan"; + case CHIP_BONAIRE: return "bonaire"; + case CHIP_KABINI: return "kabini"; + case CHIP_KAVERI: return "kaveri"; default: return ""; } } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: disable 2D tiling on CIK for now
Module: Mesa
Branch: master
Commit: d669992e3543ccdc9a9f8c9d8b375f292b4a9315
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d669992e3543ccdc9a9f8c9d8b375f292b4a9315
Author: Alex Deucher
Date: Fri May 3 17:12:04 2013 -0400
radeonsi: disable 2D tiling on CIK for now
Causes GPU hangs.
Signed-off-by: Alex Deucher
---
src/gallium/drivers/radeonsi/r600_texture.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/r600_texture.c
b/src/gallium/drivers/radeonsi/r600_texture.c
index 8992f9a..282d4f2 100644
--- a/src/gallium/drivers/radeonsi/r600_texture.c
+++ b/src/gallium/drivers/radeonsi/r600_texture.c
@@ -532,7 +532,10 @@ struct pipe_resource *si_texture_create(struct pipe_screen
*screen,
if (util_format_is_compressed(templ->format)) {
array_mode = V_009910_ARRAY_1D_TILED_THIN1;
} else {
- array_mode = V_009910_ARRAY_2D_TILED_THIN1;
+ if (rscreen->chip_class >= CIK)
+ array_mode = V_009910_ARRAY_1D_TILED_THIN1; /*
XXX fix me */
+ else
+ array_mode = V_009910_ARRAY_2D_TILED_THIN1;
}
}
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Mesa (master): radeonsi: update surface sync packet emit for CIK
Module: Mesa
Branch: master
Commit: 72c10be3a76e0e63a6e33da148fd755a1e3f34c1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=72c10be3a76e0e63a6e33da148fd755a1e3f34c1
Author: Alex Deucher
Date: Mon Oct 1 16:37:54 2012 -0400
radeonsi: update surface sync packet emit for CIK
Signed-off-by: Alex Deucher
---
src/gallium/drivers/radeonsi/si_commands.c | 23 +--
1 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_commands.c
b/src/gallium/drivers/radeonsi/si_commands.c
index 8dcf5d3..bf95924 100644
--- a/src/gallium/drivers/radeonsi/si_commands.c
+++ b/src/gallium/drivers/radeonsi/si_commands.c
@@ -60,10 +60,21 @@ void si_cmd_draw_index_auto(struct si_pm4_state *pm4,
uint32_t count,
void si_cmd_surface_sync(struct si_pm4_state *pm4, uint32_t cp_coher_cntl)
{
- si_pm4_cmd_begin(pm4, PKT3_SURFACE_SYNC);
- si_pm4_cmd_add(pm4, cp_coher_cntl); /* CP_COHER_CNTL */
- si_pm4_cmd_add(pm4, 0x);/* CP_COHER_SIZE */
- si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE */
- si_pm4_cmd_add(pm4, 0x000A);/* POLL_INTERVAL */
- si_pm4_cmd_end(pm4, false);
+ if (pm4->chip_class >= CIK) {
+ si_pm4_cmd_begin(pm4, PKT3_ACQUIRE_MEM);
+ si_pm4_cmd_add(pm4, cp_coher_cntl); /* CP_COHER_CNTL */
+ si_pm4_cmd_add(pm4, 0x);/* CP_COHER_SIZE */
+ si_pm4_cmd_add(pm4, 0xff); /* CP_COHER_SIZE_HI */
+ si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE */
+ si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE_HI */
+ si_pm4_cmd_add(pm4, 0x000A);/* POLL_INTERVAL */
+ si_pm4_cmd_end(pm4, false);
+ } else {
+ si_pm4_cmd_begin(pm4, PKT3_SURFACE_SYNC);
+ si_pm4_cmd_add(pm4, cp_coher_cntl); /* CP_COHER_CNTL */
+ si_pm4_cmd_add(pm4, 0x);/* CP_COHER_SIZE */
+ si_pm4_cmd_add(pm4, 0); /* CP_COHER_BASE */
+ si_pm4_cmd_add(pm4, 0x000A);/* POLL_INTERVAL */
+ si_pm4_cmd_end(pm4, false);
+ }
}
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Mesa (master): radeonsi: emit PA_SC_RASTER_CONFIG[_1] on cik
Module: Mesa
Branch: master
Commit: 234d81e6b26457a94aae37633c1adc89498bdb4e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=234d81e6b26457a94aae37633c1adc89498bdb4e
Author: Alex Deucher
Date: Fri Jun 7 14:07:10 2013 -0400
radeonsi: emit PA_SC_RASTER_CONFIG[_1] on cik
Use the golden values for each asic.
Todo: update Kabini and Kaveri.
Signed-off-by: Alex Deucher
---
src/gallium/drivers/radeonsi/si_state.c | 51 --
1 files changed, 34 insertions(+), 17 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 4ef73ec..58e5a56 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2937,23 +2937,40 @@ void si_init_config(struct r600_context *rctx)
si_pm4_set_reg(pm4, R_02882C_PA_SU_PRIM_FILTER_CNTL, 0);
- switch (rctx->screen->family) {
- case CHIP_TAHITI:
- case CHIP_PITCAIRN:
- si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x2a00126a);
- break;
- case CHIP_VERDE:
- si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x124a);
- break;
- case CHIP_OLAND:
- si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0082);
- break;
- case CHIP_HAINAN:
- si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x);
- break;
- default:
- si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x);
- break;
+ if (rctx->chip_class >= CIK) {
+ switch (rctx->screen->family) {
+ case CHIP_BONAIRE:
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
0x1612);
+ si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
0x);
+ break;
+ case CHIP_KAVERI:
+ /* XXX todo */
+ case CHIP_KABINI:
+ /* XXX todo */
+ default:
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
0x);
+ si_pm4_set_reg(pm4, R_028354_PA_SC_RASTER_CONFIG_1,
0x);
+ break;
+ }
+ } else {
+ switch (rctx->screen->family) {
+ case CHIP_TAHITI:
+ case CHIP_PITCAIRN:
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
0x2a00126a);
+ break;
+ case CHIP_VERDE:
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
0x124a);
+ break;
+ case CHIP_OLAND:
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
0x0082);
+ break;
+ case CHIP_HAINAN:
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
0x);
+ break;
+ default:
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG,
0x);
+ break;
+ }
}
si_pm4_set_state(rctx, init, pm4);
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Mesa (master): radeonsi: properly handle DB tiling setup on CIK
Module: Mesa
Branch: master
Commit: 3a47f1945ffda1d931790845daa38d370b1833bc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3a47f1945ffda1d931790845daa38d370b1833bc
Author: Alex Deucher
Date: Thu May 2 12:28:38 2013 -0400
radeonsi: properly handle DB tiling setup on CIK
On CIK, DB switches back to using per-surface tiling
parameters rather than the tile index used on SI.
Signed-off-by: Alex Deucher
---
src/gallium/drivers/radeonsi/si_state.c | 162 +--
1 files changed, 155 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 7df38e9..a0abf13 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -38,6 +38,114 @@
#include "si_state.h"
#include "sid.h"
+static uint32_t cik_num_banks(uint32_t nbanks)
+{
+ switch (nbanks) {
+ case 2:
+ return V_02803C_ADDR_SURF_2_BANK;
+ case 4:
+ return V_02803C_ADDR_SURF_4_BANK;
+ case 8:
+ default:
+ return V_02803C_ADDR_SURF_8_BANK;
+ case 16:
+ return V_02803C_ADDR_SURF_16_BANK;
+ }
+}
+
+
+static unsigned cik_tile_split(unsigned tile_split)
+{
+ switch (tile_split) {
+ case 64:
+ tile_split = V_028040_ADDR_SURF_TILE_SPLIT_64B;
+ break;
+ case 128:
+ tile_split = V_028040_ADDR_SURF_TILE_SPLIT_128B;
+ break;
+ case 256:
+ tile_split = V_028040_ADDR_SURF_TILE_SPLIT_256B;
+ break;
+ case 512:
+ tile_split = V_028040_ADDR_SURF_TILE_SPLIT_512B;
+ break;
+ default:
+ case 1024:
+ tile_split = V_028040_ADDR_SURF_TILE_SPLIT_1KB;
+ break;
+ case 2048:
+ tile_split = V_028040_ADDR_SURF_TILE_SPLIT_2KB;
+ break;
+ case 4096:
+ tile_split = V_028040_ADDR_SURF_TILE_SPLIT_4KB;
+ break;
+ }
+ return tile_split;
+}
+
+static unsigned cik_macro_tile_aspect(unsigned macro_tile_aspect)
+{
+ switch (macro_tile_aspect) {
+ default:
+ case 1:
+ macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_1;
+ break;
+ case 2:
+ macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_2;
+ break;
+ case 4:
+ macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_4;
+ break;
+ case 8:
+ macro_tile_aspect = V_02803C_ADDR_SURF_MACRO_ASPECT_8;
+ break;
+ }
+ return macro_tile_aspect;
+}
+
+static unsigned cik_bank_wh(unsigned bankwh)
+{
+ switch (bankwh) {
+ default:
+ case 1:
+ bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_1;
+ break;
+ case 2:
+ bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_2;
+ break;
+ case 4:
+ bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_4;
+ break;
+ case 8:
+ bankwh = V_02803C_ADDR_SURF_BANK_WIDTH_8;
+ break;
+ }
+ return bankwh;
+}
+
+static unsigned cik_db_pipe_config(unsigned tile_pipes,
+ unsigned num_rbs)
+{
+ unsigned pipe_config;
+
+ switch (tile_pipes) {
+ case 8:
+ pipe_config = V_02803C_X_ADDR_SURF_P8_32X32_16X16;
+ break;
+ case 4:
+ default:
+ if (num_rbs == 4)
+ pipe_config = V_02803C_X_ADDR_SURF_P4_16X16;
+ else
+ pipe_config = V_02803C_X_ADDR_SURF_P4_8X16;
+ break;
+ case 2:
+ pipe_config = V_02803C_ADDR_SURF_P2;
+ break;
+ }
+ return pipe_config;
+}
+
/*
* inferred framebuffer and blender state
*/
@@ -1752,10 +1860,12 @@ static void si_cb(struct r600_context *rctx, struct
si_pm4_state *pm4,
static void si_db(struct r600_context *rctx, struct si_pm4_state *pm4,
const struct pipe_framebuffer_state *state)
{
+ struct r600_screen *rscreen = rctx->screen;
struct r600_resource_texture *rtex;
struct r600_surface *surf;
- unsigned level, pitch, slice, format, tile_mode_index;
- uint32_t z_info, s_info;
+ unsigned level, pitch, slice, format, tile_mode_index, array_mode;
+ unsigned macro_aspect, tile_split, stile_split, bankh, bankw, nbanks,
pipe_config;
+ uint32_t z_info, s_info, db_depth_info;
uint64_t z_offs, s_offs;
if (state->zsbuf == NULL) {
@@ -1788,22 +1898,60 @@ static void si_db(struct r600_context *rctx, struct
si_pm4_state *pm4,
slice = slice - 1;
}
+ db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
+
z_info = S_028040_FORMAT(format);
Mesa (master): radeonsi: PA_CL_ENHANCE is privileged on CIK
Module: Mesa Branch: master Commit: 9d8ad222c69d70201d6b62eda454e08333e836ad URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d8ad222c69d70201d6b62eda454e08333e836ad Author: Alex Deucher Date: Thu Nov 15 23:05:59 2012 -0500 radeonsi: PA_CL_ENHANCE is privileged on CIK Needs to be and is set by the kernel. Signed-off-by: Alex Deucher --- src/gallium/drivers/radeonsi/si_state.c |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index db113aa..4ef73ec 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2925,8 +2925,9 @@ void si_init_config(struct r600_context *rctx) S_028AA8_PRIMGROUP_SIZE(63)); si_pm4_set_reg(pm4, R_028AB4_VGT_REUSE_OFF, 0x); si_pm4_set_reg(pm4, R_028AB8_VGT_VTX_CNT_EN, 0x0); - si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) | - S_008A14_CLIP_VTX_REORDER_ENA(1)); + if (rctx->chip_class < CIK) + si_pm4_set_reg(pm4, R_008A14_PA_CL_ENHANCE, S_008A14_NUM_CLIP_SEQ(3) | + S_008A14_CLIP_VTX_REORDER_ENA(1)); si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, 0); si_pm4_set_reg(pm4, R_028BD4_PA_SC_CENTROID_PRIORITY_0, 0x76543210); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add kabini pci ids
Module: Mesa Branch: master Commit: c309e64db8795ce0786f4b631dbc9488d0583893 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c309e64db8795ce0786f4b631dbc9488d0583893 Author: Alex Deucher Date: Thu Jan 24 19:46:05 2013 -0500 radeonsi: add kabini pci ids Signed-off-by: Alex Deucher --- include/pci_ids/radeonsi_pci_ids.h | 17 + 1 files changed, 17 insertions(+), 0 deletions(-) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index a1fcf53..2156728 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -79,3 +79,20 @@ CHIPSET(0x6651, BONAIRE_6651, BONAIRE) CHIPSET(0x6658, BONAIRE_6658, BONAIRE) CHIPSET(0x665C, BONAIRE_665C, BONAIRE) CHIPSET(0x665D, BONAIRE_665D, BONAIRE) + +CHIPSET(0x9830, KABINI_9830, KABINI) +CHIPSET(0x9831, KABINI_9831, KABINI) +CHIPSET(0x9832, KABINI_9832, KABINI) +CHIPSET(0x9833, KABINI_9833, KABINI) +CHIPSET(0x9834, KABINI_9834, KABINI) +CHIPSET(0x9835, KABINI_9835, KABINI) +CHIPSET(0x9836, KABINI_9836, KABINI) +CHIPSET(0x9837, KABINI_9837, KABINI) +CHIPSET(0x9838, KABINI_9838, KABINI) +CHIPSET(0x9839, KABINI_9839, KABINI) +CHIPSET(0x983A, KABINI_983A, KABINI) +CHIPSET(0x983B, KABINI_983B, KABINI) +CHIPSET(0x983C, KABINI_983C, KABINI) +CHIPSET(0x983D, KABINI_983D, KABINI) +CHIPSET(0x983E, KABINI_983E, KABINI) +CHIPSET(0x983F, KABINI_983F, KABINI) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add bonaire pci ids
Module: Mesa Branch: master Commit: b6b13466917af78e36d58a36b1c8afa08ff95f5c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b6b13466917af78e36d58a36b1c8afa08ff95f5c Author: Alex Deucher Date: Fri Jun 7 14:09:20 2013 -0400 radeonsi: add bonaire pci ids Signed-off-by: Alex Deucher --- include/pci_ids/radeonsi_pci_ids.h |9 + 1 files changed, 9 insertions(+), 0 deletions(-) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index f823a2e..a1fcf53 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -70,3 +70,12 @@ CHIPSET(0x6664, HAINAN_6664, HAINAN) CHIPSET(0x6665, HAINAN_6665, HAINAN) CHIPSET(0x6667, HAINAN_6667, HAINAN) CHIPSET(0x666F, HAINAN_666F, HAINAN) + +CHIPSET(0x6640, BONAIRE_6640, BONAIRE) +CHIPSET(0x6641, BONAIRE_6641, BONAIRE) +CHIPSET(0x6649, BONAIRE_6649, BONAIRE) +CHIPSET(0x6650, BONAIRE_6650, BONAIRE) +CHIPSET(0x6651, BONAIRE_6651, BONAIRE) +CHIPSET(0x6658, BONAIRE_6658, BONAIRE) +CHIPSET(0x665C, BONAIRE_665C, BONAIRE) +CHIPSET(0x665D, BONAIRE_665D, BONAIRE) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: emit TA_BC_BASE_ADDR_HI for border color on CIK
Module: Mesa Branch: master Commit: 59e4fe0b7506432bb81cbe524a7e930a25d03c4e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=59e4fe0b7506432bb81cbe524a7e930a25d03c4e Author: Alex Deucher Date: Thu Nov 8 19:00:59 2012 -0500 radeonsi: emit TA_BC_BASE_ADDR_HI for border color on CIK Signed-off-by: Alex Deucher --- src/gallium/drivers/radeonsi/si_state.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index 0dc74bc..7df38e9 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2472,6 +2472,8 @@ static struct si_pm4_state *si_bind_sampler(struct r600_context *rctx, unsigned (void*)rctx->border_color_table); si_pm4_set_reg(pm4, R_028080_TA_BC_BASE_ADDR, va_offset >> 8); + if (rctx->chip_class >= CIK) + si_pm4_set_reg(pm4, R_028084_TA_BC_BASE_ADDR_HI, va_offset >> 40); rctx->ws->buffer_unmap(rctx->border_color_table->cs_buf); si_pm4_add_bo(pm4, rctx->border_color_table, RADEON_USAGE_READ); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: store chip class in the pm4 struct
Module: Mesa
Branch: master
Commit: f2a9bd80840d5c570689ea1f4ccb648000fc9b88
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f2a9bd80840d5c570689ea1f4ccb648000fc9b88
Author: Alex Deucher
Date: Fri Jun 7 14:04:58 2013 -0400
radeonsi: store chip class in the pm4 struct
Will be used for asic specific pm4 behavior.
Signed-off-by: Alex Deucher
---
src/gallium/drivers/radeonsi/r600_hw_context.c |6 +++-
src/gallium/drivers/radeonsi/radeonsi_pm4.c| 12 +
src/gallium/drivers/radeonsi/radeonsi_pm4.h|4 +++
src/gallium/drivers/radeonsi/si_state.c| 32 +++
src/gallium/drivers/radeonsi/si_state_draw.c | 27 +++-
5 files changed, 62 insertions(+), 19 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/r600_hw_context.c
b/src/gallium/drivers/radeonsi/r600_hw_context.c
index f3f07a3..25c972b 100644
--- a/src/gallium/drivers/radeonsi/r600_hw_context.c
+++ b/src/gallium/drivers/radeonsi/r600_hw_context.c
@@ -161,7 +161,11 @@ static void r600_flush_framebuffer(struct r600_context
*ctx)
if (!(ctx->flags & R600_CONTEXT_DST_CACHES_DIRTY))
return;
- pm4 = CALLOC_STRUCT(si_pm4_state);
+ pm4 = si_pm4_alloc_state(ctx);
+
+ if (pm4 == NULL)
+ return;
+
si_cmd_surface_sync(pm4, S_0085F0_CB0_DEST_BASE_ENA(1) |
S_0085F0_CB1_DEST_BASE_ENA(1) |
S_0085F0_CB2_DEST_BASE_ENA(1) |
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pm4.c
b/src/gallium/drivers/radeonsi/radeonsi_pm4.c
index daac562..bbc62d3 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pm4.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_pm4.c
@@ -173,6 +173,18 @@ void si_pm4_free_state(struct r600_context *rctx,
FREE(state);
}
+struct si_pm4_state * si_pm4_alloc_state(struct r600_context *rctx)
+{
+ struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+
+if (pm4 == NULL)
+return NULL;
+
+ pm4->chip_class = rctx->chip_class;
+
+ return pm4;
+}
+
uint32_t si_pm4_sync_flags(struct r600_context *rctx)
{
uint32_t cp_coher_cntl = 0;
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pm4.h
b/src/gallium/drivers/radeonsi/radeonsi_pm4.h
index 9e7d636..68aa36a 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pm4.h
+++ b/src/gallium/drivers/radeonsi/radeonsi_pm4.h
@@ -35,9 +35,12 @@
// forward defines
struct r600_context;
+enum chip_class;
struct si_pm4_state
{
+ /* family specific handling */
+ enum chip_class chip_class;
/* PKT3_SET_*_REG handling */
unsignedlast_opcode;
unsignedlast_reg;
@@ -83,6 +86,7 @@ void si_pm4_inval_zsbuf_cache(struct si_pm4_state *state);
void si_pm4_free_state(struct r600_context *rctx,
struct si_pm4_state *state,
unsigned idx);
+struct si_pm4_state * si_pm4_alloc_state(struct r600_context *rctx);
uint32_t si_pm4_sync_flags(struct r600_context *rctx);
unsigned si_pm4_dirty_dw(struct r600_context *rctx);
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index a0abf13..db113aa 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -158,7 +158,7 @@ static void si_update_fb_blend_state(struct r600_context
*rctx)
if (blend == NULL)
return;
- pm4 = CALLOC_STRUCT(si_pm4_state);
+ pm4 = si_pm4_alloc_state(rctx);
if (pm4 == NULL)
return;
@@ -321,7 +321,7 @@ static void si_set_blend_color(struct pipe_context *ctx,
const struct pipe_blend_color *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
if (pm4 == NULL)
return;
@@ -342,7 +342,7 @@ static void si_set_clip_state(struct pipe_context *ctx,
const struct pipe_clip_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
struct pipe_constant_buffer cb;
if (pm4 == NULL)
@@ -375,7 +375,7 @@ static void si_set_scissor_states(struct pipe_context *ctx,
const struct pipe_scissor_state *state)
{
struct r600_context *rctx = (struct r600_context *)ctx;
- struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
+ struct si_pm4_state *pm4 = si_pm4_alloc_state(rctx);
uint32_t tl, br;
if (pm4 == NULL)
@@ -457,7 +457,11 @@ static void si_update_fb_rs_state(struct r600_context
*rctx)
return;
}
- pm4 = CALLOC_STRUCT(si_pm4_state);
+ pm4 = si_pm4_all
Mesa (master): radeonsi: rename SI chip class from TAHITI to SI
Module: Mesa
Branch: master
Commit: 5b3f1ea933a7ab6aa09ecdd1529b2baac558804e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5b3f1ea933a7ab6aa09ecdd1529b2baac558804e
Author: Alex Deucher
Date: Fri Jun 7 13:58:34 2013 -0400
radeonsi: rename SI chip class from TAHITI to SI
Covers the entire family.
Signed-off-by: Alex Deucher
---
src/gallium/drivers/radeonsi/radeonsi_pipe.c |4 ++--
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c |2 +-
src/gallium/winsys/radeon/drm/radeon_winsys.h |2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
index 3f4cd78..775fa97 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
@@ -232,7 +232,7 @@ static struct pipe_context *r600_create_context(struct
pipe_screen *screen, void
}
switch (rctx->chip_class) {
- case TAHITI:
+ case SI:
si_init_state_functions(rctx);
LIST_INITHEAD(&rctx->active_query_list);
rctx->cs = rctx->ws->cs_create(rctx->ws, RING_GFX, NULL);
@@ -795,7 +795,7 @@ struct pipe_screen *radeonsi_screen_create(struct
radeon_winsys *ws)
/* setup class */
if (rscreen->family >= CHIP_TAHITI) {
- rscreen->chip_class = TAHITI;
+ rscreen->chip_class = SI;
} else {
fprintf(stderr, "r600: Unsupported family %d\n",
rscreen->family);
FREE(rscreen);
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index ee4dfa1..0eec984 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -322,7 +322,7 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
case CHIP_VERDE:
case CHIP_OLAND:
case CHIP_HAINAN:
-ws->info.chip_class = TAHITI;
+ws->info.chip_class = SI;
break;
}
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h
b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index d0f16e1..8dba64e 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -137,7 +137,7 @@ enum chip_class {
R700,
EVERGREEN,
CAYMAN,
-TAHITI,
+SI,
};
enum ring_type {
___
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Mesa (master): radeonsi: emit additional shader pgm rsrc registers for CIK
Module: Mesa
Branch: master
Commit: 8c903f5df940729f16c2d4e90eafa4a9aa4cd02b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c903f5df940729f16c2d4e90eafa4a9aa4cd02b
Author: Alex Deucher
Date: Fri Sep 28 18:31:16 2012 -0400
radeonsi: emit additional shader pgm rsrc registers for CIK
Signed-off-by: Alex Deucher
---
src/gallium/drivers/radeonsi/si_state_draw.c | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 234f661..d828659 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -103,6 +103,13 @@ static void si_pipe_shader_vs(struct pipe_context *ctx,
struct si_pipe_shader *s
si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
S_00B12C_USER_SGPR(num_user_sgprs));
+ if (rctx->chip_class >= CIK) {
+ si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
+ S_00B118_CU_EN(0x));
+ si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
+ S_00B11C_LIMIT(0));
+ }
+
si_pm4_bind_state(rctx, vs, shader->pm4);
}
@@ -233,6 +240,10 @@ static void si_pipe_shader_ps(struct pipe_context *ctx,
struct si_pipe_shader *s
S_00B028_SGPRS((num_sgprs - 1) / 8));
si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
S_00B02C_USER_SGPR(num_user_sgprs));
+ if (rctx->chip_class >= CIK) {
+ si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
+ S_00B01C_CU_EN(0x));
+ }
si_pm4_set_reg(pm4, R_02880C_DB_SHADER_CONTROL, db_shader_control);
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Mesa (master): radeonsi: fix VGT_PRIMITIVE_TYPE emit for CIK
Module: Mesa Branch: master Commit: b363a45c545e161e986bd438b6be2bdabe56d446 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b363a45c545e161e986bd438b6be2bdabe56d446 Author: Alex Deucher Date: Fri Sep 28 17:35:26 2012 -0400 radeonsi: fix VGT_PRIMITIVE_TYPE emit for CIK Signed-off-by: Alex Deucher --- src/gallium/drivers/radeonsi/si_state_draw.c |5 - 1 files changed, 4 insertions(+), 1 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index 09c741f..234f661 100644 --- a/src/gallium/drivers/radeonsi/si_state_draw.c +++ b/src/gallium/drivers/radeonsi/si_state_draw.c @@ -285,7 +285,10 @@ static bool si_update_draw_info_state(struct r600_context *rctx, return false; } - si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim); + if (rctx->chip_class >= CIK) + si_pm4_set_reg(pm4, R_030908_VGT_PRIMITIVE_TYPE, prim); + else + si_pm4_set_reg(pm4, R_008958_VGT_PRIMITIVE_TYPE, prim); si_pm4_set_reg(pm4, R_028400_VGT_MAX_VTX_INDX, ~0); si_pm4_set_reg(pm4, R_028404_VGT_MIN_VTX_INDX, 0); si_pm4_set_reg(pm4, R_028408_VGT_INDX_OFFSET, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: initial support for CIK chips
Module: Mesa
Branch: master
Commit: f29f206c93743d421c428383afaa2944f680d9c5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f29f206c93743d421c428383afaa2944f680d9c5
Author: Alex Deucher
Date: Fri Jun 7 14:00:11 2013 -0400
radeonsi: initial support for CIK chips
Add the infrastructure to differentiate them.
Just treat them like SI for now.
Signed-off-by: Alex Deucher
---
src/gallium/drivers/radeonsi/radeonsi_pipe.c | 14 +-
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c |5 +
src/gallium/winsys/radeon/drm/radeon_winsys.h |4
3 files changed, 22 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
index 775fa97..9aa8863 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
@@ -239,6 +239,13 @@ static struct pipe_context *r600_create_context(struct
pipe_screen *screen, void
rctx->max_db = 8;
si_init_config(rctx);
break;
+ case CIK:
+ si_init_state_functions(rctx);
+ LIST_INITHEAD(&rctx->active_query_list);
+ rctx->cs = rctx->ws->cs_create(rctx->ws, RING_GFX, NULL);
+ rctx->max_db = 8;
+ si_init_config(rctx);
+ break;
default:
R600_ERR("Unsupported chip class %d.\n", rctx->chip_class);
r600_destroy_context(&rctx->context);
@@ -304,6 +311,9 @@ static const char *r600_get_family_name(enum radeon_family
family)
case CHIP_VERDE: return "AMD CAPE VERDE";
case CHIP_OLAND: return "AMD OLAND";
case CHIP_HAINAN: return "AMD HAINAN";
+ case CHIP_BONAIRE: return "AMD BONAIRE";
+ case CHIP_KAVERI: return "AMD KAVERI";
+ case CHIP_KABINI: return "AMD KABINI";
default: return "AMD unknown";
}
}
@@ -794,7 +804,9 @@ struct pipe_screen *radeonsi_screen_create(struct
radeon_winsys *ws)
}
/* setup class */
- if (rscreen->family >= CHIP_TAHITI) {
+ if (rscreen->family >= CHIP_BONAIRE) {
+ rscreen->chip_class = CIK;
+ } else if (rscreen->family >= CHIP_TAHITI) {
rscreen->chip_class = SI;
} else {
fprintf(stderr, "r600: Unsupported family %d\n",
rscreen->family);
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 0eec984..033e78f 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -324,6 +324,11 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
case CHIP_HAINAN:
ws->info.chip_class = SI;
break;
+case CHIP_BONAIRE:
+case CHIP_KAVERI:
+case CHIP_KABINI:
+ws->info.chip_class = CIK;
+break;
}
/* Check for dma */
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h
b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index 8dba64e..a619d70 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -125,6 +125,9 @@ enum radeon_family {
CHIP_VERDE,
CHIP_OLAND,
CHIP_HAINAN,
+CHIP_BONAIRE,
+CHIP_KAVERI,
+CHIP_KABINI,
CHIP_LAST,
};
@@ -138,6 +141,7 @@ enum chip_class {
EVERGREEN,
CAYMAN,
SI,
+CIK,
};
enum ring_type {
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Mesa (master): radeonsi: register updates for CIK
Module: Mesa Branch: master Commit: ecb679a8d305e2973bff386331f192ceae33cf67 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=ecb679a8d305e2973bff386331f192ceae33cf67 Author: Alex Deucher Date: Thu Nov 15 11:07:07 2012 -0500 radeonsi: register updates for CIK Signed-off-by: Alex Deucher --- src/gallium/drivers/radeonsi/sid.h | 996 +--- 1 files changed, 931 insertions(+), 65 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=ecb679a8d305e2973bff386331f192ceae33cf67 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: initial PM4 changes for CIK
Module: Mesa
Branch: master
Commit: deb23582436245dc7b2b3f67ab5d3f7c5bceb112
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=deb23582436245dc7b2b3f67ab5d3f7c5bceb112
Author: Alex Deucher
Date: Thu Nov 8 18:59:46 2012 -0500
radeonsi: initial PM4 changes for CIK
note which packets are removed and add new ones.
Signed-off-by: Alex Deucher
---
src/gallium/drivers/radeonsi/radeonsi_pm4.c |4
src/gallium/drivers/radeonsi/sid.h | 19 +++
2 files changed, 15 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pm4.c
b/src/gallium/drivers/radeonsi/radeonsi_pm4.c
index f70b9f8..daac562 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pm4.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_pm4.c
@@ -70,6 +70,10 @@ void si_pm4_set_reg(struct si_pm4_state *state, unsigned
reg, uint32_t val)
opcode = PKT3_SET_CONTEXT_REG;
reg -= SI_CONTEXT_REG_OFFSET;
+ } else if (reg >= CIK_UCONFIG_REG_OFFSET && reg < CIK_UCONFIG_REG_END) {
+ opcode = PKT3_SET_UCONFIG_REG;
+ reg -= CIK_UCONFIG_REG_OFFSET;
+
} else {
R600_ERR("Invalid register offset %08x!\n", reg);
return;
diff --git a/src/gallium/drivers/radeonsi/sid.h
b/src/gallium/drivers/radeonsi/sid.h
index ca161df..ccdcc96 100644
--- a/src/gallium/drivers/radeonsi/sid.h
+++ b/src/gallium/drivers/radeonsi/sid.h
@@ -31,6 +31,8 @@
#define SI_SH_REG_END0xC000
#define SI_CONTEXT_REG_OFFSET0x00028000
#define SI_CONTEXT_REG_END 0x00029000
+#define CIK_UCONFIG_REG_OFFSET 0x0003
+#define CIK_UCONFIG_REG_END 0x00031000
#define EVENT_TYPE_CACHE_FLUSH 0x6
#define EVENT_TYPE_PS_PARTIAL_FLUSH0x10
@@ -70,16 +72,15 @@
#define PKT3_NOP 0x10
#define PKT3_DISPATCH_DIRECT 0x15
#define PKT3_DISPATCH_INDIRECT 0x16
+#define PKT3_OCCLUSION_QUERY 0x1F /* new for CIK */
#define PKT3_SET_PREDICATION 0x20
#define PKT3_COND_EXEC 0x22
#define PKT3_PRED_EXEC 0x23
-#define PKT3_START_3D_CMDBUF 0x24
#define PKT3_DRAW_INDEX_2 0x27
#define PKT3_CONTEXT_CONTROL 0x28
#define PKT3_INDEX_TYPE0x2A
-#define PKT3_DRAW_INDEX0x2B
#define PKT3_DRAW_INDEX_AUTO 0x2D
-#define PKT3_DRAW_INDEX_IMMD 0x2E
+#define PKT3_DRAW_INDEX_IMMD 0x2E /* not on CIK */
#define PKT3_NUM_INSTANCES 0x2F
#define PKT3_STRMOUT_BUFFER_UPDATE 0x34
#define PKT3_WRITE_DATA0x37
@@ -97,22 +98,24 @@
#define PKT3_WRITE_DATA_ENGINE_SEL_PFP 1
#define PKT3_WRITE_DATA_ENGINE_SEL_CE 2
#define PKT3_MEM_SEMAPHORE 0x39
-#define PKT3_MPEG_INDEX0x3A
+#define PKT3_MPEG_INDEX0x3A /* not on CIK */
#define PKT3_WAIT_REG_MEM 0x3C
#defineWAIT_REG_MEM_EQUAL 3
-#define PKT3_MEM_WRITE 0x3D
+#define PKT3_MEM_WRITE 0x3D /* not on CIK */
#define PKT3_INDIRECT_BUFFER 0x32
-#define PKT3_SURFACE_SYNC 0x43
-#define PKT3_ME_INITIALIZE 0x44
+#define PKT3_SURFACE_SYNC 0x43 /* deprecated on CIK, use
ACQUIRE_MEM */
+#define PKT3_ME_INITIALIZE 0x44 /* not on CIK */
#define PKT3_COND_WRITE0x45
#define PKT3_EVENT_WRITE 0x46
#define PKT3_EVENT_WRITE_EOP 0x47
#define PKT3_EVENT_WRITE_EOS 0x48
-#define PKT3_ONE_REG_WRITE 0x57
+#define PKT3_ONE_REG_WRITE 0x57 /* not on CIK */
+#define PKT3_ACQUIRE_MEM 0x58 /* new for CIK */
#define PKT3_SET_CONFIG_REG0x68
#define PKT3_SET_CONTEXT_REG 0x69
#define PKT3_SET_SH_REG0x76
#define PKT3_SET_SH_REG_OFFSET 0x77
+#define PKT3_SET_UCONFIG_REG 0x79 /* new for CIK */
#define PKT_TYPE_S(x) (((x) & 0x3) << 30)
#define PKT_TYPE_G(x) (((x) >> 30) & 0x3)
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Mesa (master): winsys/radeon: add env var to disable VM on Cayman/Trinity
Module: Mesa
Branch: master
Commit: 761320b197ecc87221d070f5e961032ab0b665a4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=761320b197ecc87221d070f5e961032ab0b665a4
Author: Alex Deucher
Date: Fri Jun 7 13:55:27 2013 -0400
winsys/radeon: add env var to disable VM on Cayman/Trinity
Set env var RADEON_VA=0 to disable VM on Cayman/Trinity.
Useful for debugging.
Note: this is a candidate for the 9.1 branch.
Signed-off-by: Alex Deucher
Reviewed-by: Tom Stellard
Reviewed-by: Marek Olšák
---
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 15d5d31..ee4dfa1 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -399,6 +399,8 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
&ws->info.r600_ib_vm_max_size))
ws->info.r600_virtual_address = FALSE;
}
+ if (ws->gen == DRV_R600 && !debug_get_bool_option("RADEON_VA", TRUE))
+ ws->info.r600_virtual_address = FALSE;
}
/* Get max pipes, this is only needed for compute shaders. All evergreen+
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Mesa (master): radeonsi: add Hainan pci ids
Module: Mesa Branch: master Commit: 29b8d6a1dad71dd70797c356a96d038ad2674d5d URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=29b8d6a1dad71dd70797c356a96d038ad2674d5d Author: Alex Deucher Date: Mon May 13 16:25:51 2013 -0400 radeonsi: add Hainan pci ids Note: this is a candidate for the 9.1 branch Signed-off-by: Alex Deucher Reviewed-by: Michel Dänzer --- include/pci_ids/radeonsi_pci_ids.h |7 +++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index 68d7948..f823a2e 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -63,3 +63,10 @@ CHIPSET(0x6620, OLAND_6620, OLAND) CHIPSET(0x6621, OLAND_6621, OLAND) CHIPSET(0x6623, OLAND_6623, OLAND) CHIPSET(0x6631, OLAND_6631, OLAND) + +CHIPSET(0x6660, HAINAN_6660, HAINAN) +CHIPSET(0x6663, HAINAN_6663, HAINAN) +CHIPSET(0x6664, HAINAN_6664, HAINAN) +CHIPSET(0x6665, HAINAN_6665, HAINAN) +CHIPSET(0x6667, HAINAN_6667, HAINAN) +CHIPSET(0x666F, HAINAN_666F, HAINAN) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: add support for hainan chips
Module: Mesa
Branch: master
Commit: 4045c3d0601f1e3280625ed837846ecad5d051f7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4045c3d0601f1e3280625ed837846ecad5d051f7
Author: Alex Deucher
Date: Mon May 13 16:24:02 2013 -0400
radeonsi: add support for hainan chips
Note: this is a candidate for the 9.1 branch
Signed-off-by: Alex Deucher
Reviewed-by: Michel Dänzer
---
src/gallium/drivers/radeonsi/radeonsi_pipe.c |1 +
src/gallium/drivers/radeonsi/si_state.c |3 +++
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c |1 +
src/gallium/winsys/radeon/drm/radeon_winsys.h |1 +
4 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
index 0e6b941..fa40097 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
@@ -300,6 +300,7 @@ static const char *r600_get_family_name(enum radeon_family
family)
case CHIP_PITCAIRN: return "AMD PITCAIRN";
case CHIP_VERDE: return "AMD CAPE VERDE";
case CHIP_OLAND: return "AMD OLAND";
+ case CHIP_HAINAN: return "AMD HAINAN";
default: return "AMD unknown";
}
}
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index be40fdf..ed95b1d 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2791,6 +2791,9 @@ void si_init_config(struct r600_context *rctx)
case CHIP_OLAND:
si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x0082);
break;
+ case CHIP_HAINAN:
+ si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x);
+ break;
default:
si_pm4_set_reg(pm4, R_028350_PA_SC_RASTER_CONFIG, 0x);
break;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 3689020..15d5d31 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -321,6 +321,7 @@ static boolean do_winsys_init(struct radeon_drm_winsys *ws)
case CHIP_PITCAIRN:
case CHIP_VERDE:
case CHIP_OLAND:
+case CHIP_HAINAN:
ws->info.chip_class = TAHITI;
break;
}
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h
b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index 1c2fb69..d0f16e1 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -124,6 +124,7 @@ enum radeon_family {
CHIP_PITCAIRN,
CHIP_VERDE,
CHIP_OLAND,
+CHIP_HAINAN,
CHIP_LAST,
};
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Mesa (master): radeonsi: update r600_get_llvm_processor_name for hainan
Module: Mesa Branch: master Commit: d188f14941deecf0817fd491694c57c9ab6892d4 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d188f14941deecf0817fd491694c57c9ab6892d4 Author: Alex Deucher Date: Mon May 13 16:44:40 2013 -0400 radeonsi: update r600_get_llvm_processor_name for hainan Signed-off-by: Alex Deucher Reviewed-by: Michel Dänzer --- src/gallium/drivers/radeonsi/radeonsi_pipe.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c b/src/gallium/drivers/radeonsi/radeonsi_pipe.c index fa40097..b988e72 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c +++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c @@ -289,6 +289,7 @@ const char *r600_get_llvm_processor_name(enum radeon_family family) case CHIP_PITCAIRN: return "pitcairn"; case CHIP_VERDE: return "verde"; case CHIP_OLAND: return "oland"; + case CHIP_HAINAN: return "hainan"; default: return ""; } } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: don't emit surface_sync after FLUSH_AND_INV_EVENT
Module: Mesa
Branch: master
Commit: 4539f8e20af286d1f521eb016c89c6d9af0b801c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4539f8e20af286d1f521eb016c89c6d9af0b801c
Author: Alex Deucher
Date: Fri May 3 09:56:31 2013 -0400
r600g: don't emit surface_sync after FLUSH_AND_INV_EVENT
It shouldn't be needed since the FLUSH_AND_INV_EVENT has already
made sure the destination caches are flushed. Additionally,
we didn't previously emit the surface_sync until this commit:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5e4c07e7964a3258ed02b530bcdc24c0650204b
Emitting them together causes hangs in compute on cayman/TN
and hangs in Heaven on evergreen.
Note: this patch is a candidate for the 9.1 branch, but requires:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=156bcca62c9f4e79e78929f72bc085757f36a65a
as well.
Reviewed-by: Tom Stellard
Reviewed-by: Marek Olšák
Signed-off-by: Alex Deucher
---
src/gallium/drivers/r600/r600_hw_context.c | 26 --
1 files changed, 0 insertions(+), 26 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_hw_context.c
b/src/gallium/drivers/r600/r600_hw_context.c
index 6d8b2cf..944b666 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -226,32 +226,6 @@ void r600_flush_emit(struct r600_context *rctx)
if (rctx->flags & R600_CONTEXT_FLUSH_AND_INV) {
cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 0, 0);
cs->buf[cs->cdw++] =
EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0);
- if (rctx->chip_class >= EVERGREEN) {
- /* We were previously setting the CB and DB bits on
-* cp_coher_cntl, but this is unnecessary since
-* we are emitting the
-* EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT packet.
-* Setting the CB bits was causing lockups when using
-* compute on cayman.
-*
-* XXX: Do even need to emit a surface sync packet here?
-* Prior to e5e4c07e7964a3258ed02b530bcdc24c0650204b
-* surface sync was not being emitted with the
-* R600_CONTEXT_FLUSH_AND_INV flag.
-*/
- cp_coher_cntl = S_0085F0_TC_ACTION_ENA(1) |
- S_0085F0_DB_ACTION_ENA(1) |
- S_0085F0_SH_ACTION_ENA(1) |
- S_0085F0_SMX_ACTION_ENA(1) |
- S_0085F0_FULL_CACHE_ENA(1);
- } else {
- cp_coher_cntl = S_0085F0_SMX_ACTION_ENA(1) |
- S_0085F0_SH_ACTION_ENA(1) |
- S_0085F0_VC_ACTION_ENA(1) |
- S_0085F0_TC_ACTION_ENA(1) |
- S_0085F0_FULL_CACHE_ENA(1);
- }
- emit_flush = 1;
}
if (rctx->flags & R600_CONTEXT_INVAL_READ_CACHES) {
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Mesa (master): radeonsi: add new SI pci ids
Module: Mesa Branch: master Commit: b5145ca2a810b0a65311a18bffd05db35b2a21d6 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5145ca2a810b0a65311a18bffd05db35b2a21d6 Author: Alex Deucher Date: Thu Apr 25 14:22:46 2013 -0400 radeonsi: add new SI pci ids Note: this is a candidate for the 9.1 branch. Signed-off-by: Alex Deucher --- include/pci_ids/radeonsi_pci_ids.h |3 +++ 1 files changed, 3 insertions(+), 0 deletions(-) diff --git a/include/pci_ids/radeonsi_pci_ids.h b/include/pci_ids/radeonsi_pci_ids.h index 22c96c0..68d7948 100644 --- a/include/pci_ids/radeonsi_pci_ids.h +++ b/include/pci_ids/radeonsi_pci_ids.h @@ -28,6 +28,7 @@ CHIPSET(0x684C, PITCAIRN_684C, PITCAIRN) CHIPSET(0x6820, VERDE_6820, VERDE) CHIPSET(0x6821, VERDE_6821, VERDE) +CHIPSET(0x6822, VERDE_6822, VERDE) CHIPSET(0x6823, VERDE_6823, VERDE) CHIPSET(0x6824, VERDE_6824, VERDE) CHIPSET(0x6825, VERDE_6825, VERDE) @@ -35,11 +36,13 @@ CHIPSET(0x6826, VERDE_6826, VERDE) CHIPSET(0x6827, VERDE_6827, VERDE) CHIPSET(0x6828, VERDE_6828, VERDE) CHIPSET(0x6829, VERDE_6829, VERDE) +CHIPSET(0x682A, VERDE_682A, VERDE) CHIPSET(0x682B, VERDE_682B, VERDE) CHIPSET(0x682D, VERDE_682D, VERDE) CHIPSET(0x682F, VERDE_682F, VERDE) CHIPSET(0x6830, VERDE_6830, VERDE) CHIPSET(0x6831, VERDE_6831, VERDE) +CHIPSET(0x6835, VERDE_6835, VERDE) CHIPSET(0x6837, VERDE_6837, VERDE) CHIPSET(0x6838, VERDE_6838, VERDE) CHIPSET(0x6839, VERDE_6839, VERDE) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: add new richland pci ids
Module: Mesa Branch: master Commit: b3a856dfa90de845868d63041f576475662cd6cf URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3a856dfa90de845868d63041f576475662cd6cf Author: Alex Deucher Date: Thu Apr 25 14:21:15 2013 -0400 r600g: add new richland pci ids Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher --- include/pci_ids/r600_pci_ids.h |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/pci_ids/r600_pci_ids.h b/include/pci_ids/r600_pci_ids.h index 9c9bab2..5036a83 100644 --- a/include/pci_ids/r600_pci_ids.h +++ b/include/pci_ids/r600_pci_ids.h @@ -320,6 +320,8 @@ CHIPSET(0x9998, ARUBA_9998, ARUBA) CHIPSET(0x, ARUBA_, ARUBA) CHIPSET(0x999A, ARUBA_999A, ARUBA) CHIPSET(0x999B, ARUBA_999B, ARUBA) +CHIPSET(0x999C, ARUBA_999C, ARUBA) +CHIPSET(0x999D, ARUBA_999D, ARUBA) CHIPSET(0x99A0, ARUBA_99A0, ARUBA) CHIPSET(0x99A2, ARUBA_99A2, ARUBA) CHIPSET(0x99A4, ARUBA_99A4, ARUBA) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: use CP DMA for buffer clears on evergreen+
Module: Mesa
Branch: master
Commit: 5bbeae7a3d3be17d44b1bc851872a107a75c393b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5bbeae7a3d3be17d44b1bc851872a107a75c393b
Author: Alex Deucher
Date: Wed Apr 24 12:26:52 2013 -0400
r600g: use CP DMA for buffer clears on evergreen+
Lighter weight then using streamout. Only evergreen
and newer asics support embedded data as src with
CP DMA.
Reviewed-by: Jerome Glisse
Reviewed-by: Marek Olšák
Signed-off-by: Alex Deucher
---
src/gallium/drivers/r600/evergreen_hw_context.c | 66 +++
src/gallium/drivers/r600/evergreend.h | 42 ++
src/gallium/drivers/r600/r600_blit.c| 10 +++-
src/gallium/drivers/r600/r600_pipe.h|3 +
4 files changed, 119 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c
b/src/gallium/drivers/r600/evergreen_hw_context.c
index d980c18..7cab879 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -106,3 +106,69 @@ void evergreen_dma_copy(struct r600_context *rctx,
util_range_add(&rdst->valid_buffer_range, dst_offset,
dst_offset + size);
}
+
+/* The max number of bytes to copy per packet. */
+#define CP_DMA_MAX_BYTE_COUNT ((1 << 21) - 8)
+
+void evergreen_cp_dma_clear_buffer(struct r600_context *rctx,
+ struct pipe_resource *dst, uint64_t offset,
+ unsigned size, uint32_t clear_value)
+{
+ struct radeon_winsys_cs *cs = rctx->rings.gfx.cs;
+
+ assert(size);
+ assert(rctx->screen->has_cp_dma);
+
+ offset += r600_resource_va(&rctx->screen->screen, dst);
+
+ /* We flush the caches, because we might read from or write
+* to resources which are bound right now. */
+ rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES |
+ R600_CONTEXT_FLUSH_AND_INV |
+ R600_CONTEXT_FLUSH_AND_INV_CB_META |
+ R600_CONTEXT_FLUSH_AND_INV_DB_META |
+ R600_CONTEXT_STREAMOUT_FLUSH |
+ R600_CONTEXT_WAIT_3D_IDLE;
+
+ while (size) {
+ unsigned sync = 0;
+ unsigned byte_count = MIN2(size, CP_DMA_MAX_BYTE_COUNT);
+ unsigned reloc;
+
+ r600_need_cs_space(rctx, 10 + (rctx->flags ?
R600_MAX_FLUSH_CS_DWORDS : 0), FALSE);
+
+ /* Flush the caches for the first copy only. */
+ if (rctx->flags) {
+ r600_flush_emit(rctx);
+ }
+
+ /* Do the synchronization after the last copy, so that all data
is written to memory. */
+ if (size == byte_count) {
+ sync = PKT3_CP_DMA_CP_SYNC;
+ }
+
+ /* This must be done after r600_need_cs_space. */
+ reloc = r600_context_bo_reloc(rctx, &rctx->rings.gfx,
+ (struct r600_resource*)dst,
RADEON_USAGE_WRITE);
+
+ r600_write_value(cs, PKT3(PKT3_CP_DMA, 4, 0));
+ r600_write_value(cs, clear_value); /* DATA [31:0] */
+ r600_write_value(cs, sync | PKT3_CP_DMA_SRC_SEL(2));/*
CP_SYNC [31] | SRC_SEL[30:29] */
+ r600_write_value(cs, offset); /* DST_ADDR_LO [31:0] */
+ r600_write_value(cs, (offset >> 32) & 0xff);/*
DST_ADDR_HI [7:0] */
+ r600_write_value(cs, byte_count); /* COMMAND [29:22] |
BYTE_COUNT [20:0] */
+
+ r600_write_value(cs, PKT3(PKT3_NOP, 0, 0));
+ r600_write_value(cs, reloc);
+
+ size -= byte_count;
+ offset += byte_count;
+ }
+
+ /* Invalidate the read caches. */
+ rctx->flags |= R600_CONTEXT_INVAL_READ_CACHES;
+
+ util_range_add(&r600_resource(dst)->valid_buffer_range, offset,
+ offset + size);
+}
+
diff --git a/src/gallium/drivers/r600/evergreend.h
b/src/gallium/drivers/r600/evergreend.h
index 53b68a4..5d72432 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -118,6 +118,48 @@
#define PKT3_PREDICATE(x) (((x) >> 0) & 0x1)
#define PKT0(index, count) (PKT_TYPE_S(0) | PKT0_BASE_INDEX_S(index) |
PKT_COUNT_S(count))
+#define PKT3_CP_DMA0x41
+/* 1. header
+ * 2. SRC_ADDR_LO [31:0] or DATA [31:0]
+ * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] |
SRC_ADDR_HI [7:0]
+ * 4. DST_ADDR_LO [31:0]
+ * 5. DST_ADDR_HI [7:0]
+ * 6. COMMAND [29:22] | BYTE_COUNT [20:0]
+ */
+#define PKT3_CP_DMA_CP_SYNC (1 << 31)
+#define PKT3_CP_DMA_SRC_SEL(x) ((x) << 29)
+/* 0 - SRC_ADDR
+ * 1 - GDS (program SAS to 1 as well)
+ * 2 - DATA
+ */
+#define PKT3_
Mesa (9.1): r600g: disable hyperz by default on 9.1
Module: Mesa
Branch: 9.1
Commit: e78b553195309af3063c3dcc6259b41ea0699449
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e78b553195309af3063c3dcc6259b41ea0699449
Author: Alex Deucher
Date: Mon Apr 22 10:08:33 2013 -0400
r600g: disable hyperz by default on 9.1
There are too many cases were we end up with lockups.
Once we sort out the remaining issues on master, they
can be backported and hyperz can be re-enabled on 9.1
Reviewed-by: Michel Dänzer
Signed-off-by: Alex Deucher
---
src/gallium/drivers/r600/r600_pipe.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index a7973a5..80b859f 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -1157,7 +1157,7 @@ struct pipe_screen *r600_screen_create(struct
radeon_winsys *ws)
* case were triggering lockup quickly such as :
* piglit/bin/depthstencil-render-miplevels 1024 d=s=z24_s8
*/
- rscreen->use_hyperz = debug_get_bool_option("R600_HYPERZ", TRUE);
+ rscreen->use_hyperz = debug_get_bool_option("R600_HYPERZ", FALSE);
rscreen->use_hyperz = rscreen->info.drm_minor >= 26 ?
rscreen->use_hyperz : FALSE;
rscreen->global_pool = compute_memory_pool_new(rscreen);
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Mesa (master): r600g: Use virtual address for PIPE_QUERY_SO* in r600_emit_query_end
Module: Mesa Branch: master Commit: 92855bcc95207252045314b658eb10c6305020bc URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=92855bcc95207252045314b658eb10c6305020bc Author: Martin Andersson Date: Mon Mar 25 23:11:34 2013 +0100 r600g: Use virtual address for PIPE_QUERY_SO* in r600_emit_query_end Virtual address is used for PIPE_QUERY_SO* queries in r600_emit_query_begin, but not in r600_emit_query_end. This will trigger a GPU fault when one of those queries is made and virtual address is enabled. Note: this is a candidate for the 9.1 branch Signed-off-by: Alex Deucher --- src/gallium/drivers/r600/r600_query.c |5 +++-- 1 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/r600/r600_query.c b/src/gallium/drivers/r600/r600_query.c index 0335189..782ad26 100644 --- a/src/gallium/drivers/r600/r600_query.c +++ b/src/gallium/drivers/r600/r600_query.c @@ -186,10 +186,11 @@ static void r600_emit_query_end(struct r600_context *ctx, struct r600_query *que case PIPE_QUERY_PRIMITIVES_GENERATED: case PIPE_QUERY_SO_STATISTICS: case PIPE_QUERY_SO_OVERFLOW_PREDICATE: + va += query->buffer.results_end + query->result_size/2; cs->buf[cs->cdw++] = PKT3(PKT3_EVENT_WRITE, 2, 0); cs->buf[cs->cdw++] = EVENT_TYPE(EVENT_TYPE_SAMPLE_STREAMOUTSTATS) | EVENT_INDEX(3); - cs->buf[cs->cdw++] = query->buffer.results_end + query->result_size/2; - cs->buf[cs->cdw++] = 0; + cs->buf[cs->cdw++] = va; + cs->buf[cs->cdw++] = (va >> 32UL) & 0xFF; break; case PIPE_QUERY_TIME_ELAPSED: va += query->buffer.results_end + query->result_size/2; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: don't emit SQ_DYN_GPR_RESOURCE_LIMIT_1 on cayman
Module: Mesa Branch: master Commit: 49c1fc7044eaaa5c2dca05ff4a709be8e3636871 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=49c1fc7044eaaa5c2dca05ff4a709be8e3636871 Author: Alex Deucher Date: Tue Mar 19 18:11:20 2013 -0400 r600g: don't emit SQ_DYN_GPR_RESOURCE_LIMIT_1 on cayman Doesn't exist on the asic and will cause a CS rejection if VM is disabled. Note: this is a candidate for the 9.1 branch. Signed-off-by: Alex Deucher --- src/gallium/drivers/r600/evergreen_state.c |1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index db5484d..7169614 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -2782,7 +2782,6 @@ static void cayman_init_atom_start_cs(struct r600_context *rctx) r600_store_value(cb, 0); /* R_0286E4_SPI_PS_IN_CONTROL_2 */ r600_store_value(cb, 0); /* R_0286E8_SPI_COMPUTE_INPUT_CNTL */ r600_store_context_reg(cb, R_028B54_VGT_SHADER_STAGES_EN, 0); - r600_store_context_reg(cb, R_028838_SQ_DYN_GPR_RESOURCE_LIMIT_1, 0); eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF); eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: emit DB_SRESULTS_COMPARE_STATE0 on r6xx/r7xx
Module: Mesa Branch: master Commit: a9914117ea31ff4bc9d2e575e7366ddef57e5fea URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9914117ea31ff4bc9d2e575e7366ddef57e5fea Author: Alex Deucher Date: Tue Mar 19 14:25:32 2013 -0400 r600g: emit DB_SRESULTS_COMPARE_STATE0 on r6xx/r7xx Not using HiS yet, but matches what we do on evergreen+. Signed-off-by: Alex Deucher --- src/gallium/drivers/r600/r600_state.c |3 ++- src/gallium/drivers/r600/r600d.h |1 + 2 files changed, 3 insertions(+), 1 deletions(-) diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 846c159..c6d98bb 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -2623,7 +2623,8 @@ void r600_init_atom_start_cs(struct r600_context *rctx) r600_store_value(cb, 0); /* R_0286E0_SPI_FOG_FUNC_SCALE */ r600_store_value(cb, 0); /* R_0286E4_SPI_FOG_FUNC_BIAS */ - r600_store_context_reg_seq(cb, R_028D2C_DB_SRESULTS_COMPARE_STATE1, 2); + r600_store_context_reg_seq(cb, R_028D28_DB_SRESULTS_COMPARE_STATE0, 3); + r600_store_value(cb, 0); /* R_028D28_DB_SRESULTS_COMPARE_STATE0 */ r600_store_value(cb, 0); /* R_028D2C_DB_SRESULTS_COMPARE_STATE1 */ r600_store_value(cb, 0); /* R_028D30_DB_PRELOAD_CONTROL */ diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h index 81e5a6c..9b31383 100644 --- a/src/gallium/drivers/r600/r600d.h +++ b/src/gallium/drivers/r600/r600d.h @@ -2318,6 +2318,7 @@ #define R_02880C_DB_SHADER_CONTROL 0x02880C #define R_028D0C_DB_RENDER_CONTROL 0x028D0C #define R_028D10_DB_RENDER_OVERRIDE 0x028D10 +#define R_028D28_DB_SRESULTS_COMPARE_STATE0 0x028D28 #define R_028D2C_DB_SRESULTS_COMPARE_STATE1 0x028D2C #define R_028D30_DB_PRELOAD_CONTROL 0x028D30 #define R_028D44_DB_ALPHA_TO_MASK0x028D44 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (9.1): r600g: Use blitter rather than DMA for 128bpp on cayman (v3)
Module: Mesa
Branch: 9.1
Commit: d0ccb5b91191251c2a76ef43819c0a7704cecaba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d0ccb5b91191251c2a76ef43819c0a7704cecaba
Author: Alex Deucher
Date: Fri Mar 15 14:29:24 2013 -0400
r600g: Use blitter rather than DMA for 128bpp on cayman (v3)
On cayman, 128bpp surfaces require non_disp ordering for hw
access to both linear and tiled surfaces. When we use the 3D
engine we can set the non_disp ordering on both the tiled and
linear sides (via CB or texture), but when we use the DMA
engine, we can only set the non_disp ordering on the tiled
side, so after a L2T operation with the DMA engine, the data
ends up in the wrong order on the tiled side.
v2: cayman/TN only
v3: fix comments
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=60802
Note: this is a candidate for the 9.1 branch.
Signed-off-by: Alex Deucher
(cherry picked from commit 4409758a046a47b09cdd339f97afd22107c68f0c)
---
src/gallium/drivers/r600/evergreen_state.c | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 33f306c..804c037 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3676,6 +3676,17 @@ boolean evergreen_dma_blit(struct pipe_context *ctx,
return FALSE;
}
+ /* 128 bpp surfaces require non_disp_tiling for both
+* tiled and linear buffers on cayman. However, async
+* DMA only supports it on the tiled side. As such
+* the tile order is backwards after a L2T/T2L packet.
+*/
+ if ((rctx->chip_class == CAYMAN) &&
+ (src_mode != dst_mode) &&
+ (util_format_get_blocksize(src->format) >= 16)) {
+ return FALSE;
+ }
+
if (src_mode == dst_mode) {
uint64_t dst_offset, src_offset;
/* simple dma blit would do NOTE code here assume :
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Mesa (9.1): r600g: add Richland APU pci ids
Module: Mesa Branch: 9.1 Commit: 61e7c043ea4b787e0ec47e827fb57f7091a3b61a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=61e7c043ea4b787e0ec47e827fb57f7091a3b61a Author: Alex Deucher Date: Fri Mar 8 13:52:37 2013 -0500 r600g: add Richland APU pci ids Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher (cherry picked from commit 03eef7f8ef98f1008a8687bbd7ee0141b433887a) --- include/pci_ids/r600_pci_ids.h | 11 +++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/include/pci_ids/r600_pci_ids.h b/include/pci_ids/r600_pci_ids.h index 7ceb820..9c9bab2 100644 --- a/include/pci_ids/r600_pci_ids.h +++ b/include/pci_ids/r600_pci_ids.h @@ -298,6 +298,10 @@ CHIPSET(0x9907, ARUBA_9907, ARUBA) CHIPSET(0x9908, ARUBA_9908, ARUBA) CHIPSET(0x9909, ARUBA_9909, ARUBA) CHIPSET(0x990A, ARUBA_990A, ARUBA) +CHIPSET(0x990B, ARUBA_990B, ARUBA) +CHIPSET(0x990C, ARUBA_990C, ARUBA) +CHIPSET(0x990D, ARUBA_990D, ARUBA) +CHIPSET(0x990E, ARUBA_990E, ARUBA) CHIPSET(0x990F, ARUBA_990F, ARUBA) CHIPSET(0x9910, ARUBA_9910, ARUBA) CHIPSET(0x9913, ARUBA_9913, ARUBA) @@ -309,6 +313,13 @@ CHIPSET(0x9991, ARUBA_9991, ARUBA) CHIPSET(0x9992, ARUBA_9992, ARUBA) CHIPSET(0x9993, ARUBA_9993, ARUBA) CHIPSET(0x9994, ARUBA_9994, ARUBA) +CHIPSET(0x9995, ARUBA_9995, ARUBA) +CHIPSET(0x9996, ARUBA_9996, ARUBA) +CHIPSET(0x9997, ARUBA_9997, ARUBA) +CHIPSET(0x9998, ARUBA_9998, ARUBA) +CHIPSET(0x, ARUBA_, ARUBA) +CHIPSET(0x999A, ARUBA_999A, ARUBA) +CHIPSET(0x999B, ARUBA_999B, ARUBA) CHIPSET(0x99A0, ARUBA_99A0, ARUBA) CHIPSET(0x99A2, ARUBA_99A2, ARUBA) CHIPSET(0x99A4, ARUBA_99A4, ARUBA) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: properly set non_disp tiling mode for DMA (v2)
Module: Mesa Branch: master Commit: 2da8ee16a8b126d15f34552916c77b203be326db URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2da8ee16a8b126d15f34552916c77b203be326db Author: Alex Deucher Date: Fri Mar 15 15:11:01 2013 -0400 r600g: properly set non_disp tiling mode for DMA (v2) Needs to be set for depth, stencil, and fmask just like other blocks. v2: drop additional cayman bits for now Signed-off-by: Alex Deucher --- src/gallium/drivers/r600/evergreen_state.c |8 ++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 6b6d93e..db5484d 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -3528,7 +3528,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx, struct r600_texture *rdst = (struct r600_texture*)dst; unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size; unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode; - unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split; + unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0; uint64_t base, addr; /* make sure that the dma ring is only one active */ @@ -3541,6 +3541,10 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx, dst_mode = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED ? RADEON_SURF_MODE_LINEAR : dst_mode; assert(dst_mode != src_mode); + /* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */ + if (util_format_has_depth(util_format_description(src->format))) + non_disp_tiling = 1; + y = 0; sub_cmd = 0x8; lbpp = util_logbase2(bpp); @@ -3620,7 +3624,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx, cs->buf[cs->cdw++] = (pitch_tile_max << 0) | ((height - 1) << 16); cs->buf[cs->cdw++] = (slice_tile_max << 0); cs->buf[cs->cdw++] = (x << 0) | (z << 18); - cs->buf[cs->cdw++] = (y << 0) | (tile_split << 21) | (nbanks << 25); + cs->buf[cs->cdw++] = (y << 0) | (tile_split << 21) | (nbanks << 25) | (non_disp_tiling << 28); cs->buf[cs->cdw++] = addr & 0xfffc; cs->buf[cs->cdw++] = (addr >> 32UL) & 0xff; copy_height -= cheight; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: Use blitter rather than DMA for 128bpp on cayman (v3)
Module: Mesa
Branch: master
Commit: 4409758a046a47b09cdd339f97afd22107c68f0c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4409758a046a47b09cdd339f97afd22107c68f0c
Author: Alex Deucher
Date: Fri Mar 15 14:29:24 2013 -0400
r600g: Use blitter rather than DMA for 128bpp on cayman (v3)
On cayman, 128bpp surfaces require non_disp ordering for hw
access to both linear and tiled surfaces. When we use the 3D
engine we can set the non_disp ordering on both the tiled and
linear sides (via CB or texture), but when we use the DMA
engine, we can only set the non_disp ordering on the tiled
side, so after a L2T operation with the DMA engine, the data
ends up in the wrong order on the tiled side.
v2: cayman/TN only
v3: fix comments
Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=60802
Note: this is a candidate for the 9.1 branch.
Signed-off-by: Alex Deucher
---
src/gallium/drivers/r600/evergreen_state.c | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 2bdefb0..6b6d93e 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3674,6 +3674,17 @@ boolean evergreen_dma_blit(struct pipe_context *ctx,
return FALSE;
}
+ /* 128 bpp surfaces require non_disp_tiling for both
+* tiled and linear buffers on cayman. However, async
+* DMA only supports it on the tiled side. As such
+* the tile order is backwards after a L2T/T2L packet.
+*/
+ if ((rctx->chip_class == CAYMAN) &&
+ (src_mode != dst_mode) &&
+ (util_format_get_blocksize(src->format) >= 16)) {
+ return FALSE;
+ }
+
if (src_mode == dst_mode) {
uint64_t dst_offset, src_offset;
/* simple dma blit would do NOTE code here assume :
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Mesa (master): r600g: add Richland APU pci ids
Module: Mesa Branch: master Commit: 03eef7f8ef98f1008a8687bbd7ee0141b433887a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=03eef7f8ef98f1008a8687bbd7ee0141b433887a Author: Alex Deucher Date: Fri Mar 8 13:52:37 2013 -0500 r600g: add Richland APU pci ids Note: this is a candidate for the stable branches. Signed-off-by: Alex Deucher --- include/pci_ids/r600_pci_ids.h | 11 +++ 1 files changed, 11 insertions(+), 0 deletions(-) diff --git a/include/pci_ids/r600_pci_ids.h b/include/pci_ids/r600_pci_ids.h index 7ceb820..9c9bab2 100644 --- a/include/pci_ids/r600_pci_ids.h +++ b/include/pci_ids/r600_pci_ids.h @@ -298,6 +298,10 @@ CHIPSET(0x9907, ARUBA_9907, ARUBA) CHIPSET(0x9908, ARUBA_9908, ARUBA) CHIPSET(0x9909, ARUBA_9909, ARUBA) CHIPSET(0x990A, ARUBA_990A, ARUBA) +CHIPSET(0x990B, ARUBA_990B, ARUBA) +CHIPSET(0x990C, ARUBA_990C, ARUBA) +CHIPSET(0x990D, ARUBA_990D, ARUBA) +CHIPSET(0x990E, ARUBA_990E, ARUBA) CHIPSET(0x990F, ARUBA_990F, ARUBA) CHIPSET(0x9910, ARUBA_9910, ARUBA) CHIPSET(0x9913, ARUBA_9913, ARUBA) @@ -309,6 +313,13 @@ CHIPSET(0x9991, ARUBA_9991, ARUBA) CHIPSET(0x9992, ARUBA_9992, ARUBA) CHIPSET(0x9993, ARUBA_9993, ARUBA) CHIPSET(0x9994, ARUBA_9994, ARUBA) +CHIPSET(0x9995, ARUBA_9995, ARUBA) +CHIPSET(0x9996, ARUBA_9996, ARUBA) +CHIPSET(0x9997, ARUBA_9997, ARUBA) +CHIPSET(0x9998, ARUBA_9998, ARUBA) +CHIPSET(0x, ARUBA_, ARUBA) +CHIPSET(0x999A, ARUBA_999A, ARUBA) +CHIPSET(0x999B, ARUBA_999B, ARUBA) CHIPSET(0x99A0, ARUBA_99A0, ARUBA) CHIPSET(0x99A2, ARUBA_99A2, ARUBA) CHIPSET(0x99A4, ARUBA_99A4, ARUBA) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (9.1): r600g: pad the DMA CS to a multiple of 8 dwords
Module: Mesa
Branch: 9.1
Commit: 09199c68627f738b51bb9fd385e4528b3f0fbc77
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=09199c68627f738b51bb9fd385e4528b3f0fbc77
Author: Marek Olšák
Date: Wed Feb 27 21:24:02 2013 +0100
r600g: pad the DMA CS to a multiple of 8 dwords
Tested-by: Andreas Boll
NOTE: This is a candidate for the 9.1 branch.
(cherry picked from commit c77917d35fdf64d9f194fbecc4748213621eefc8)
---
src/gallium/drivers/r600/r600_pipe.c | 16 ++--
1 files changed, 14 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index a59578d..a7973a5 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -22,6 +22,7 @@
*/
#include "r600_pipe.h"
#include "r600_public.h"
+#include "r600d.h"
#include
#include "pipe/p_shader_tokens.h"
@@ -165,12 +166,23 @@ static void r600_flush_gfx_ring(void *ctx, unsigned flags)
static void r600_flush_dma_ring(void *ctx, unsigned flags)
{
struct r600_context *rctx = (struct r600_context *)ctx;
+ struct radeon_winsys_cs *cs = rctx->rings.dma.cs;
+ unsigned padding_dw, i;
- if (!rctx->rings.dma.cs->cdw) {
+ if (!cs->cdw) {
return;
}
+
+ /* Pad the DMA CS to a multiple of 8 dwords. */
+ padding_dw = 8 - cs->cdw % 8;
+ if (padding_dw < 8) {
+ for (i = 0; i < padding_dw; i++) {
+ cs->buf[cs->cdw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0,
0);
+ }
+ }
+
rctx->rings.dma.flushing = true;
- rctx->ws->cs_flush(rctx->rings.dma.cs, flags);
+ rctx->ws->cs_flush(cs, flags);
rctx->rings.dma.flushing = false;
}
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Mesa (9.1): r600g: Check comp_mask before merging export instructions
Module: Mesa
Branch: 9.1
Commit: 1dc162d52fab6a7cd5e5e7fd60c9af603a1e541e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1dc162d52fab6a7cd5e5e7fd60c9af603a1e541e
Author: Vincent Lejeune
Date: Sun Mar 3 21:35:38 2013 +0100
r600g: Check comp_mask before merging export instructions
Fixes a llvm uncovered (rare) bug where consecutive exports were
merged even if they have incompatible mask.
(cherry picked from commit 83e7d111afd8d340ce8fe13ea139271400eb362e)
---
src/gallium/drivers/r600/r600_asm.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index 451b072..bda425c 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -322,6 +322,7 @@ int r600_bytecode_add_output(struct r600_bytecode *bc,
const struct r600_bytecod
output->swizzle_y == bc->cf_last->output.swizzle_y &&
output->swizzle_z == bc->cf_last->output.swizzle_z &&
output->swizzle_w == bc->cf_last->output.swizzle_w &&
+ output->comp_mask == bc->cf_last->output.comp_mask &&
(output->burst_count + bc->cf_last->output.burst_count) <= 16) {
if ((output->gpr + output->burst_count) ==
bc->cf_last->output.gpr &&
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Mesa (9.1): r600g: fix check_and_set_bank_swizzle for cayman
Module: Mesa
Branch: 9.1
Commit: 9a5f5137739acebfa3408aa8368a5a407ff9ef9c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a5f5137739acebfa3408aa8368a5a407ff9ef9c
Author: Vadim Girlin
Date: Tue Feb 26 20:50:25 2013 +0400
r600g: fix check_and_set_bank_swizzle for cayman
Tested-by: Vincent Lejeune
Reviewed-by: Vincent Lejeune
(cherry picked from commit 138b5b9a12b7e1537494aac556589ac9981b557b)
---
src/gallium/drivers/r600/r600_asm.c | 10 +++---
1 files changed, 3 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index f25c6aa..451b072 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -873,12 +873,6 @@ static int check_and_set_bank_swizzle(struct r600_bytecode
*bc,
bank_swizzle[4] = SQ_ALU_SCL_210;
while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
- if (max_slots == 4) {
- for (i = 0; i < max_slots; i++) {
- if (bank_swizzle[i] == SQ_ALU_VEC_210)
- return -1;
- }
- }
init_bank_swizzle(&bs);
if (scalar_only == false) {
for (i = 0; i < 4; i++) {
@@ -910,8 +904,10 @@ static int check_and_set_bank_swizzle(struct r600_bytecode
*bc,
bank_swizzle[i]++;
if (bank_swizzle[i] <= SQ_ALU_VEC_210)
break;
- else
+ else if (i < max_slots - 1)
bank_swizzle[i] =
SQ_ALU_VEC_012;
+ else
+ return -1;
}
}
}
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Mesa (9.1): winsys/radeon: Only add bo to hash table when creating flink
Module: Mesa
Branch: 9.1
Commit: cd77c77bb958e53ea873a887a40179da1c2ce3fd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd77c77bb958e53ea873a887a40179da1c2ce3fd
Author: Martin Andersson
Date: Fri Mar 1 22:34:28 2013 +0100
winsys/radeon: Only add bo to hash table when creating flink
The problem is that we mix bo handles and flinked names in the hash
table. Because kms type handles are not flinked they should not be
added to the hash table. If we do that we will sooner or later
get a situation where we will overwrite a correct entry because
the bo handle was the same as a flinked name.
Note: this is a candidate for the stable branches.
Reviewed-by: Jerome Glisse
Signed-off-by: Alex Deucher
(cherry picked from commit d96d8ed910dcecf4511fbc8c24de292cf04ee1d4)
---
src/gallium/winsys/radeon/drm/radeon_drm_bo.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 2d41c26..f4ac526 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -957,16 +957,16 @@ static boolean radeon_winsys_bo_get_handle(struct
pb_buffer *buffer,
bo->flinked = TRUE;
bo->flink = flink.name;
+
+pipe_mutex_lock(bo->mgr->bo_handles_mutex);
+util_hash_table_set(bo->mgr->bo_handles,
(void*)(uintptr_t)bo->flink, bo);
+pipe_mutex_unlock(bo->mgr->bo_handles_mutex);
}
whandle->handle = bo->flink;
} else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
whandle->handle = bo->handle;
}
-pipe_mutex_lock(bo->mgr->bo_handles_mutex);
-util_hash_table_set(bo->mgr->bo_handles,
(void*)(uintptr_t)whandle->handle, bo);
-pipe_mutex_unlock(bo->mgr->bo_handles_mutex);
-
whandle->stride = stride;
return TRUE;
}
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Mesa (master): winsys/radeon: Only add bo to hash table when creating flink
Module: Mesa
Branch: master
Commit: d96d8ed910dcecf4511fbc8c24de292cf04ee1d4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d96d8ed910dcecf4511fbc8c24de292cf04ee1d4
Author: Martin Andersson
Date: Fri Mar 1 22:34:28 2013 +0100
winsys/radeon: Only add bo to hash table when creating flink
The problem is that we mix bo handles and flinked names in the hash
table. Because kms type handles are not flinked they should not be
added to the hash table. If we do that we will sooner or later
get a situation where we will overwrite a correct entry because
the bo handle was the same as a flinked name.
Note: this is a candidate for the stable branches.
Reviewed-by: Jerome Glisse
Signed-off-by: Alex Deucher
---
src/gallium/winsys/radeon/drm/radeon_drm_bo.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 2d41c26..f4ac526 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -957,16 +957,16 @@ static boolean radeon_winsys_bo_get_handle(struct
pb_buffer *buffer,
bo->flinked = TRUE;
bo->flink = flink.name;
+
+pipe_mutex_lock(bo->mgr->bo_handles_mutex);
+util_hash_table_set(bo->mgr->bo_handles,
(void*)(uintptr_t)bo->flink, bo);
+pipe_mutex_unlock(bo->mgr->bo_handles_mutex);
}
whandle->handle = bo->flink;
} else if (whandle->type == DRM_API_HANDLE_TYPE_KMS) {
whandle->handle = bo->handle;
}
-pipe_mutex_lock(bo->mgr->bo_handles_mutex);
-util_hash_table_set(bo->mgr->bo_handles,
(void*)(uintptr_t)whandle->handle, bo);
-pipe_mutex_unlock(bo->mgr->bo_handles_mutex);
-
whandle->stride = stride;
return TRUE;
}
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Mesa (master): r600g: enable CP DMA on 6xx
Module: Mesa
Branch: master
Commit: a40ba43d78fe8e6ee145785df54b50dd7c7f929a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a40ba43d78fe8e6ee145785df54b50dd7c7f929a
Author: Alex Deucher
Date: Fri Mar 1 12:11:31 2013 -0500
r600g: enable CP DMA on 6xx
Tested across several 6xx parts, no piglit regressions.
Signed-off-by: Alex Deucher
---
src/gallium/drivers/r600/r600_pipe.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index e81856c..78002ae 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -1123,7 +1123,7 @@ struct pipe_screen *r600_screen_create(struct
radeon_winsys *ws)
break;
}
- rscreen->has_cp_dma = rscreen->info.drm_minor >= 27 &&
rscreen->chip_class >= R700;
+ rscreen->has_cp_dma = rscreen->info.drm_minor >= 27;
if (r600_init_tiling(rscreen)) {
FREE(rscreen);
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Mesa (master): r600g: add missing emit_flush for R600_CONTEXT_FLUSH_AND_INV case
Module: Mesa
Branch: master
Commit: e5e4c07e7964a3258ed02b530bcdc24c0650204b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5e4c07e7964a3258ed02b530bcdc24c0650204b
Author: Alex Deucher
Date: Fri Feb 22 09:21:30 2013 -0500
r600g: add missing emit_flush for R600_CONTEXT_FLUSH_AND_INV case
We set the cp_coher_cntl bits but never emit them.
Signed-off-by: Alex Deucher
Reviewed-by: Jerome Glisse
Reviewed-by: Marek Olšák
---
src/gallium/drivers/r600/r600_hw_context.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_hw_context.c
b/src/gallium/drivers/r600/r600_hw_context.c
index 9a93edd..ec098c1 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -680,6 +680,7 @@ void r600_flush_emit(struct r600_context *rctx)
S_0085F0_TC_ACTION_ENA(1) |
S_0085F0_FULL_CACHE_ENA(1);
}
+ emit_flush = 1;
}
if (rctx->flags & R600_CONTEXT_INVAL_READ_CACHES) {
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