Mesa (master): i965: Set max texture buffer size to hardware limit

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 52e5ad7bf8c731280ca4506b7d38e8c7a8e734b9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=52e5ad7bf8c731280ca4506b7d38e8c7a8e734b9

Author: Chris Forbes 
Date:   Wed Jun  3 12:11:27 2015 +1200

i965: Set max texture buffer size to hardware limit

Previously we were leaving this at the default of 64K, which meets the
spec but is too small for some real uses. The hardware can handle up to
128M.

User was complaining about this on freenode ##OpenGL today.

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_context.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 274a237..652d9a3 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -545,6 +545,7 @@ brw_initialize_context_constants(struct brw_context *brw)
 */
ctx->Const.UniformBufferOffsetAlignment = 16;
ctx->Const.TextureBufferOffsetAlignment = 16;
+   ctx->Const.MaxTextureBufferSize = 128 * 1024 * 1024;
 
if (brw->gen >= 6) {
   ctx->Const.MaxVarying = 32;

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Mesa (master): relnotes: Note support for viewport arrays on i965/Gen6.

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 1fcdb2ce794d14545b06640b2316c629a3bde3ee
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1fcdb2ce794d14545b06640b2316c629a3bde3ee

Author: Chris Forbes 
Date:   Wed May  6 19:05:17 2015 +1200

relnotes: Note support for viewport arrays on i965/Gen6.

Signed-off-by: Chris Forbes 

---

 docs/relnotes/10.6.0.html |1 +
 1 file changed, 1 insertion(+)

diff --git a/docs/relnotes/10.6.0.html b/docs/relnotes/10.6.0.html
index 6c5bc8c..fb1a928 100644
--- a/docs/relnotes/10.6.0.html
+++ b/docs/relnotes/10.6.0.html
@@ -57,6 +57,7 @@ Note: some of the new features are only available with 
certain drivers.
 GL_ARB_program_interface_query (all drivers)
 GL_ARB_texture_stencil8 on nv50, nvc0, r600, radeonsi, softpipe
 GL_ARB_uniform_buffer_object on freedreno
+GL_ARB_viewport_array, GL_AMD_vertex_shader_viewport_index on 
i965/gen6
 GL_EXT_draw_buffers2 on freedreno
 GL_OES_EGL_sync on all drivers
 EGL_KHR_fence_sync on freedreno, nv50, nvc0, r600, radeonsi

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Mesa (master): i965/gen6: setup limits for ARB_viewport_array

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 0374159b0ce3c4634364ca5ab257e305765d4879
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0374159b0ce3c4634364ca5ab257e305765d4879

Author: Chris Forbes 
Date:   Wed May  6 14:43:34 2015 +1200

i965/gen6: setup limits for ARB_viewport_array

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_context.c |4 ++--
 src/mesa/drivers/dri/i965/brw_defines.h |2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index 6c00f6c..fd7420a 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -598,8 +598,8 @@ brw_initialize_context_constants(struct brw_context *brw)
ctx->Const.ShaderCompilerOptions[MESA_SHADER_COMPUTE].NirOptions = 
&nir_options;
 
/* ARB_viewport_array */
-   if (brw->gen >= 7 && ctx->API == API_OPENGL_CORE) {
-  ctx->Const.MaxViewports = GEN7_NUM_VIEWPORTS;
+   if (brw->gen >= 6 && ctx->API == API_OPENGL_CORE) {
+  ctx->Const.MaxViewports = GEN6_NUM_VIEWPORTS;
   ctx->Const.ViewportSubpixelBits = 0;
 
   /* Cast to float before negating because MaxViewportWidth is unsigned.
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 7b5dd45..83d7a35 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1712,7 +1712,7 @@ enum brw_message_target {
 # define GEN6_CC_VIEWPORT_MODIFY   (1 << 12)
 # define GEN6_SF_VIEWPORT_MODIFY   (1 << 11)
 # define GEN6_CLIP_VIEWPORT_MODIFY (1 << 10)
-# define GEN7_NUM_VIEWPORTS16
+# define GEN6_NUM_VIEWPORTS16
 
 #define _3DSTATE_VIEWPORT_STATE_POINTERS_CC0x7823 /* GEN7+ */
 #define _3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL 0x7821 /* GEN7+ */

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Mesa (master): i965/gen6: Upload all the SF viewports

[Chris Forbes]

Module: Mesa
Branch: master
Commit: c41f6252006e9730097b1dab01f6dff1769413de
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c41f6252006e9730097b1dab01f6dff1769413de

Author: Chris Forbes 
Date:   Wed May  6 17:35:37 2015 +1200

i965/gen6: Upload all the SF viewports

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_structs.h |2 ++
 src/mesa/drivers/dri/i965/gen6_viewport_state.c |   29 +--
 2 files changed, 19 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_structs.h 
b/src/mesa/drivers/dri/i965/brw_structs.h
index 7c97a95..55338c0 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -639,6 +639,8 @@ struct gen6_sf_viewport {
float m30;
float m31;
float m32;
+
+   unsigned pad0[2];
 };
 
 struct gen7_sf_clip_viewport {
diff --git a/src/mesa/drivers/dri/i965/gen6_viewport_state.c 
b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
index 95d204f..2fb0182 100644
--- a/src/mesa/drivers/dri/i965/gen6_viewport_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
@@ -81,14 +81,14 @@ static void
 gen6_upload_sf_vp(struct brw_context *brw)
 {
struct gl_context *ctx = &brw->ctx;
-   struct brw_sf_viewport *sfv;
+   struct gen6_sf_viewport *sfv;
GLfloat y_scale, y_bias;
-   double scale[3], translate[3];
const bool render_to_fbo = _mesa_is_user_fbo(ctx->DrawBuffer);
 
sfv = brw_state_batch(brw, AUB_TRACE_SF_VP_STATE,
-sizeof(*sfv), 32, &brw->sf.vp_offset);
-   memset(sfv, 0, sizeof(*sfv));
+ sizeof(*sfv) * ctx->Const.MaxViewports,
+ 32, &brw->sf.vp_offset);
+   memset(sfv, 0, sizeof(*sfv) * ctx->Const.MaxViewports);
 
/* _NEW_BUFFERS */
if (render_to_fbo) {
@@ -99,14 +99,19 @@ gen6_upload_sf_vp(struct brw_context *brw)
   y_bias = ctx->DrawBuffer->Height;
}
 
-   /* _NEW_VIEWPORT */
-   _mesa_get_viewport_xform(ctx, 0, scale, translate);
-   sfv->viewport.m00 = scale[0];
-   sfv->viewport.m11 = scale[1] * y_scale;
-   sfv->viewport.m22 = scale[2];
-   sfv->viewport.m30 = translate[0];
-   sfv->viewport.m31 = translate[1] * y_scale + y_bias;
-   sfv->viewport.m32 = translate[2];
+   for (unsigned i = 0; i < ctx->Const.MaxViewports; i++) {
+  double scale[3], translate[3];
+
+  /* _NEW_VIEWPORT */
+  _mesa_get_viewport_xform(ctx, i, scale, translate);
+  sfv[i].m00 = scale[0];
+  sfv[i].m11 = scale[1] * y_scale;
+  sfv[i].m22 = scale[2];
+  sfv[i].m30 = translate[0];
+  sfv[i].m31 = translate[1] * y_scale + y_bias;
+  sfv[i].m32 = translate[2];
+
+   }
 
brw->ctx.NewDriverState |= BRW_NEW_SF_VP;
 }

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Mesa (master): i965/gen6: Enable ARB_viewport_array and AMD_vertex_shader_viewport_index

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 5fc23375e80dd2084f30700bdd3216082f662acc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5fc23375e80dd2084f30700bdd3216082f662acc

Author: Chris Forbes 
Date:   Wed May  6 17:45:11 2015 +1200

i965/gen6: Enable ARB_viewport_array and AMD_vertex_shader_viewport_index

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/intel_extensions.c |   16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
b/src/mesa/drivers/dri/i965/intel_extensions.c
index c28c171..3088a1a 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -292,6 +292,14 @@ intelInitExtensions(struct gl_context *ctx)
   /* Test if the kernel has the ioctl. */
   if (drm_intel_reg_read(brw->bufmgr, TIMESTAMP, &dummy) == 0)
  ctx->Extensions.ARB_timer_query = true;
+
+  /* Only enable this in core profile because other parts of Mesa behave
+   * slightly differently when the extension is enabled.
+   */
+  if (ctx->API == API_OPENGL_CORE) {
+ ctx->Extensions.ARB_viewport_array = true;
+ ctx->Extensions.AMD_vertex_shader_viewport_index = true;
+  }
}
 
if (brw->gen >= 5) {
@@ -313,14 +321,6 @@ intelInitExtensions(struct gl_context *ctx)
  ctx->Extensions.ARB_draw_indirect = true;
   }
 
-  /* Only enable this in core profile because other parts of Mesa behave
-   * slightly differently when the extension is enabled.
-   */
-  if (ctx->API == API_OPENGL_CORE) {
- ctx->Extensions.ARB_viewport_array = true;
- ctx->Extensions.AMD_vertex_shader_viewport_index = true;
-  }
-
   ctx->Extensions.ARB_texture_compression_bptc = true;
   ctx->Extensions.ARB_derivative_control = true;
}

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Mesa (master): i965/gen6: Upload all the clip viewports

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 2a8835d4854a49087fb032a927209dac50dfa827
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a8835d4854a49087fb032a927209dac50dfa827

Author: Chris Forbes 
Date:   Wed May  6 17:34:27 2015 +1200

i965/gen6: Upload all the clip viewports

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/gen6_viewport_state.c |   40 ---
 1 file changed, 21 insertions(+), 19 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_viewport_state.c 
b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
index 0c63283..95d204f 100644
--- a/src/mesa/drivers/dri/i965/gen6_viewport_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_viewport_state.c
@@ -42,27 +42,29 @@ gen6_upload_clip_vp(struct brw_context *brw)
struct brw_clipper_viewport *vp;
 
vp = brw_state_batch(brw, AUB_TRACE_CLIP_VP_STATE,
-   sizeof(*vp), 32, &brw->clip.vp_offset);
+sizeof(*vp) * ctx->Const.MaxViewports, 32, 
&brw->clip.vp_offset);
 
-   /* According to the "Vertex X,Y Clamping and Quantization" section of the
-* Strips and Fans documentation, objects must not have a screen-space
-* extents of over 8192 pixels, or they may be mis-rasterized.  The maximum
-* screen space coordinates of a small object may larger, but we have no
-* way to enforce the object size other than through clipping.
-*
-* If you're surprised that we set clip to -gbx to +gbx and it seems like
-* we'll end up with 16384 wide, note that for a 8192-wide render target,
-* we'll end up with a normal (-1, 1) clip volume that just covers the
-* drawable.
-*/
-   const float maximum_post_clamp_delta = 8192;
-   float gbx = maximum_post_clamp_delta / ctx->ViewportArray[0].Width;
-   float gby = maximum_post_clamp_delta / ctx->ViewportArray[0].Height;
+   for (unsigned i = 0; i < ctx->Const.MaxViewports; i++) {
+  /* According to the "Vertex X,Y Clamping and Quantization" section of the
+   * Strips and Fans documentation, objects must not have a screen-space
+   * extents of over 8192 pixels, or they may be mis-rasterized.  The 
maximum
+   * screen space coordinates of a small object may larger, but we have no
+   * way to enforce the object size other than through clipping.
+   *
+   * If you're surprised that we set clip to -gbx to +gbx and it seems like
+   * we'll end up with 16384 wide, note that for a 8192-wide render target,
+   * we'll end up with a normal (-1, 1) clip volume that just covers the
+   * drawable.
+   */
+  const float maximum_post_clamp_delta = 8192;
+  float gbx = maximum_post_clamp_delta / ctx->ViewportArray[i].Width;
+  float gby = maximum_post_clamp_delta / ctx->ViewportArray[i].Height;
 
-   vp->xmin = -gbx;
-   vp->xmax = gbx;
-   vp->ymin = -gby;
-   vp->ymax = gby;
+  vp[i].xmin = -gbx;
+  vp[i].xmax = gbx;
+  vp[i].ymin = -gby;
+  vp[i].ymax = gby;
+   }
 
brw->ctx.NewDriverState |= BRW_NEW_CLIP_VP;
 }

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Mesa (master): i965/gen4-5: Cope with immutable-format texture revalidation

[Chris Forbes]

Module: Mesa
Branch: master
Commit: f68a973dfb8926ac872b0b0e3b4b5c2163389d06
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f68a973dfb8926ac872b0b0e3b4b5c2163389d06

Author: Chris Forbes 
Date:   Mon Dec  8 20:37:00 2014 +1300

i965/gen4-5: Cope with immutable-format texture revalidation

This is unfortunately sometimes necessary due to rebasing levels when
rendering into them.

16 piglits crash -> pass, when building mesa with debug enabled.

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/intel_tex_validate.c |   13 ++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_tex_validate.c 
b/src/mesa/drivers/dri/i965/intel_tex_validate.c
index 0bf0393..1d82768 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_validate.c
@@ -98,10 +98,17 @@ intel_finalize_mipmap_tree(struct brw_context *brw, GLuint 
unit)
   return true;
}
 
-   /* Immutable textures should not get this far -- they should have been
-* created in a validated state, and nothing can invalidate them.
+   /* On recent generations, immutable textures should not get this far
+* -- they should have been created in a validated state, and nothing
+* can invalidate them.
+*
+* Unfortunately, this is not true on pre-Sandybridge hardware -- when
+* rendering into an immutable-format depth texture we may have to rebase
+* the rendered levels to meet alignment requirements.
+*
+* FINISHME: Avoid doing this.
 */
-   assert(!tObj->Immutable);
+   assert(!tObj->Immutable || brw->gen < 6);
 
firstImage = intel_texture_image(tObj->Image[0][tObj->BaseLevel]);
 

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Mesa (master): i965/disasm: Fix format strings

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 21ff9bfe1cea8c0a51e9f607cc580df62baa3445
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=21ff9bfe1cea8c0a51e9f607cc580df62baa3445

Author: Chris Forbes 
Date:   Sat Mar 14 07:10:11 2015 +1300

i965/disasm: Fix format strings

Most of the brw_inst_* api returns 64bit values. This fixes disassembly
of sampler messages, etc.

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 

---

 src/mesa/drivers/dri/i965/brw_disasm.c |   48 
 1 file changed, 24 insertions(+), 24 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
b/src/mesa/drivers/dri/i965/brw_disasm.c
index c92c534..c41dde2 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -729,7 +729,7 @@ dest(FILE *file, struct brw_context *brw, brw_inst *inst)
  if (err == -1)
 return 0;
  if (brw_inst_dst_da1_subreg_nr(brw, inst))
-format(file, ".%d", brw_inst_dst_da1_subreg_nr(brw, inst) /
+format(file, ".%ld", brw_inst_dst_da1_subreg_nr(brw, inst) /
reg_type_size[brw_inst_dst_reg_type(brw, inst)]);
  string(file, "<");
  err |= control(file, "horiz stride", horiz_stride,
@@ -740,7 +740,7 @@ dest(FILE *file, struct brw_context *brw, brw_inst *inst)
   } else {
  string(file, "g[a0");
  if (brw_inst_dst_ia_subreg_nr(brw, inst))
-format(file, ".%d", brw_inst_dst_ia_subreg_nr(brw, inst) /
+format(file, ".%ld", brw_inst_dst_ia_subreg_nr(brw, inst) /
reg_type_size[brw_inst_dst_reg_type(brw, inst)]);
  if (brw_inst_dst_ia1_addr_imm(brw, inst))
 format(file, " %d", brw_inst_dst_ia1_addr_imm(brw, inst));
@@ -758,7 +758,7 @@ dest(FILE *file, struct brw_context *brw, brw_inst *inst)
  if (err == -1)
 return 0;
  if (brw_inst_dst_da16_subreg_nr(brw, inst))
-format(file, ".%d", brw_inst_dst_da16_subreg_nr(brw, inst) /
+format(file, ".%ld", brw_inst_dst_da16_subreg_nr(brw, inst) /
reg_type_size[brw_inst_dst_reg_type(brw, inst)]);
  string(file, "<1>");
  err |= control(file, "writemask", writemask,
@@ -789,7 +789,7 @@ dest_3src(FILE *file, struct brw_context *brw, brw_inst 
*inst)
if (err == -1)
   return 0;
if (brw_inst_3src_dst_subreg_nr(brw, inst))
-  format(file, ".%d", brw_inst_3src_dst_subreg_nr(brw, inst));
+  format(file, ".%ld", brw_inst_3src_dst_subreg_nr(brw, inst));
string(file, "<1>");
err |= control(file, "writemask", writemask,
   brw_inst_3src_dst_writemask(brw, inst), NULL);
@@ -1225,9 +1225,9 @@ brw_disassemble_inst(FILE *file, struct brw_context *brw, 
brw_inst *inst,
   string(file, "(");
   err |= control(file, "predicate inverse", pred_inv,
  brw_inst_pred_inv(brw, inst), NULL);
-  format(file, "f%d", brw->gen >= 7 ? brw_inst_flag_reg_nr(brw, inst) : 0);
+  format(file, "f%ld", brw->gen >= 7 ? brw_inst_flag_reg_nr(brw, inst) : 
0);
   if (brw_inst_flag_subreg_nr(brw, inst))
- format(file, ".%d", brw_inst_flag_subreg_nr(brw, inst));
+ format(file, ".%ld", brw_inst_flag_subreg_nr(brw, inst));
   if (brw_inst_access_mode(brw, inst) == BRW_ALIGN_1) {
  err |= control(file, "predicate control align1", pred_ctrl_align1,
 brw_inst_pred_control(brw, inst), NULL);
@@ -1261,10 +1261,10 @@ brw_disassemble_inst(FILE *file, struct brw_context 
*brw, brw_inst *inst,
   (brw->gen < 6 || (opcode != BRW_OPCODE_SEL &&
 opcode != BRW_OPCODE_IF &&
 opcode != BRW_OPCODE_WHILE))) {
- format(file, ".f%d",
+ format(file, ".f%ld",
 brw->gen >= 7 ? brw_inst_flag_reg_nr(brw, inst) : 0);
  if (brw_inst_flag_subreg_nr(brw, inst))
-format(file, ".%d", brw_inst_flag_subreg_nr(brw, inst));
+format(file, ".%ld", brw_inst_flag_subreg_nr(brw, inst));
   }
}
 
@@ -1276,7 +1276,7 @@ brw_disassemble_inst(FILE *file, struct brw_context *brw, 
brw_inst *inst,
}
 
if (opcode == BRW_OPCODE_SEND && brw->gen < 6)
-  format(file, " %d", brw_inst_base_mrf(brw, inst));
+  format(file, " %ld", brw_inst_base_mrf(brw, inst));
 
if (has_uip(brw, opcode)) {
   /* Instructions that have UIP also have JIP. */
@@ -1297,7 +1297,7 @@ brw_disassemble_inst(FILE *file, struct brw_context *brw, 
brw_inst *inst,
   pad(file, 16);
   format(file, "J

Mesa (master): i965/disasm: Mark format() as being printf-style.

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 7c3095d6b71c410fd625ead797c78a0f5376904d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c3095d6b71c410fd625ead797c78a0f5376904d

Author: Chris Forbes 
Date:   Sat Mar 14 07:10:10 2015 +1300

i965/disasm: Mark format() as being printf-style.

This allows us to get warnings from GCC when we mess up the format
strings.

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 

---

 src/mesa/drivers/dri/i965/brw_disasm.c |3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
b/src/mesa/drivers/dri/i965/brw_disasm.c
index 863a6b3..c92c534 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -597,6 +597,9 @@ string(FILE *file, const char *string)
 }
 
 static int
+format(FILE *f, const char *format, ...) PRINTFLIKE(2, 3);
+
+static int
 format(FILE *f, const char *format, ...)
 {
char buf[1024];

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Mesa (master): i965/gs: Check newly-generated GS-out VUE map against correct stage

[Chris Forbes]

Module: Mesa
Branch: master
Commit: b51ff50a767cc78d678ed3d2c25995f5c4194fea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b51ff50a767cc78d678ed3d2c25995f5c4194fea

Author: Chris Forbes 
Date:   Sat Feb 28 19:57:20 2015 +1300

i965/gs: Check newly-generated GS-out VUE map against correct stage

Previously, we compared our new GS-out VUE map to the existing *VS*-out
VUE map, which is bogus.

This would mostly manifest as redundant dirty flagging where the GS is
in use but the VS and GS output layouts differ; but there is a scary
case where we would fail to flag a GS-out layout change if it happened
to match the VS-out layout.

Signed-off-by: Chris Forbes 
Cc: "10.5, 10.4" 
Reviewed-by: Matt Turner 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=5

---

 src/mesa/drivers/dri/i965/brw_gs.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_gs.c 
b/src/mesa/drivers/dri/i965/brw_gs.c
index 1fba76a..efcff09 100644
--- a/src/mesa/drivers/dri/i965/brw_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_gs.c
@@ -357,7 +357,7 @@ brw_upload_gs_prog(struct brw_context *brw)
}
brw->gs.base.prog_data = &brw->gs.prog_data->base.base;
 
-   if (memcmp(&brw->vs.prog_data->base.vue_map, &brw->vue_map_geom_out,
+   if (memcmp(&brw->gs.prog_data->base.vue_map, &brw->vue_map_geom_out,
   sizeof(brw->vue_map_geom_out)) != 0) {
   brw->vue_map_geom_out = brw->gs.prog_data->base.vue_map;
   brw->state.dirty.brw |= BRW_NEW_VUE_MAP_GEOM_OUT;

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Mesa (master): mesa: Make renderbuffer FBO attachments not layered

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 1581e12aba3712fe4884586c7be6087b0a4a0041
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1581e12aba3712fe4884586c7be6087b0a4a0041

Author: James Legg 
Date:   Sat Feb  7 23:33:15 2015 +

mesa: Make renderbuffer FBO attachments not layered

For framebuffer completeness checks, consider renderbuffers as not
layered. Previously, they would have counted as layered if a layered
textured had previously been bound to the same attachment point. This
could cause framebuffer completeness checks to incorrectly fail with
GL_FRAMEBUFFER_INCOMPLETE_LAYER_TARGETS, even if no layered attachments
were present.

Reviewed-by: Chris Forbes 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89026

---

 src/mesa/main/fbobject.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index 3305151..dae9d4e 100644
--- a/src/mesa/main/fbobject.c
+++ b/src/mesa/main/fbobject.c
@@ -468,6 +468,7 @@ set_renderbuffer_attachment(struct gl_context *ctx,
remove_attachment(ctx, att);
att->Type = GL_RENDERBUFFER_EXT;
att->Texture = NULL; /* just to be safe */
+   att->Layered = GL_FALSE;
att->Complete = GL_FALSE;
_mesa_reference_renderbuffer(&att->Renderbuffer, rb);
 }

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Mesa (master): st/mesa: mark constant array of swizzles as static const

[Chris Forbes]

Module: Mesa
Branch: master
Commit: cfb5b1c59eb42a7a1c0972aa1947050b2e04ba9b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cfb5b1c59eb42a7a1c0972aa1947050b2e04ba9b

Author: Nils Wallménius 
Date:   Thu Jan 22 20:47:28 2015 +0100

st/mesa: mark constant array of swizzles as static const

This saves about 0.5k in the text section for a gallium driver
on amd64.

Reviewed-by: Chris Forbes 

---

 src/mesa/state_tracker/st_glsl_to_tgsi.cpp |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index b84f39d..a9ea8c8 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -486,7 +486,7 @@ fail_link(struct gl_shader_program *prog, const char *fmt, 
...)
 static int
 swizzle_for_size(int size)
 {
-   int size_swizzles[4] = {
+   static const int size_swizzles[4] = {
   MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_X, SWIZZLE_X, SWIZZLE_X),
   MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Y, SWIZZLE_Y),
   MAKE_SWIZZLE4(SWIZZLE_X, SWIZZLE_Y, SWIZZLE_Z, SWIZZLE_Z),

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Mesa (master): mesa: Add ARB_shader_precision infrastructure

[Chris Forbes]

Module: Mesa
Branch: master
Commit: d36fa60191359af9ac1e1889bcdc95c3b9d65332
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d36fa60191359af9ac1e1889bcdc95c3b9d65332

Author: Micah Fedke 
Date:   Wed Dec 31 14:16:52 2014 -0600

mesa: Add ARB_shader_precision infrastructure

Reviewed-by: Ian Romanick 
Reviewed-by: Chris Forbes 

---

 src/glsl/glcpp/glcpp-parse.y|3 +++
 src/glsl/glsl_parser_extras.cpp |1 +
 src/glsl/glsl_parser_extras.h   |2 ++
 src/mapi/glapi/gen/gl_API.xml   |6 +-
 src/mesa/main/extensions.c  |1 +
 src/mesa/main/mtypes.h  |1 +
 6 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y
index 9e705ef..e5bebe5 100644
--- a/src/glsl/glcpp/glcpp-parse.y
+++ b/src/glsl/glcpp/glcpp-parse.y
@@ -2474,6 +2474,9 @@ _glcpp_parser_handle_version_declaration(glcpp_parser_t 
*parser, intmax_t versio
 
   if (extensions->ARB_derivative_control)
  add_builtin_define(parser, "GL_ARB_derivative_control", 1);
+
+  if (extensions->ARB_shader_precision)
+ add_builtin_define(parser, "GL_ARB_shader_precision", 1);
   }
}
 
diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp
index 6d18cd4..ccdf031 100644
--- a/src/glsl/glsl_parser_extras.cpp
+++ b/src/glsl/glsl_parser_extras.cpp
@@ -532,6 +532,7 @@ static const _mesa_glsl_extension 
_mesa_glsl_supported_extensions[] = {
EXT(ARB_shader_atomic_counters, true,  false, 
ARB_shader_atomic_counters),
EXT(ARB_shader_bit_encoding,true,  false, 
ARB_shader_bit_encoding),
EXT(ARB_shader_image_load_store,true,  false, 
ARB_shader_image_load_store),
+   EXT(ARB_shader_precision,   true,  false, ARB_shader_precision),
EXT(ARB_shader_stencil_export,  true,  false, 
ARB_shader_stencil_export),
EXT(ARB_shader_texture_lod, true,  false, 
ARB_shader_texture_lod),
EXT(ARB_shading_language_420pack,   true,  false, 
ARB_shading_language_420pack),
diff --git a/src/glsl/glsl_parser_extras.h b/src/glsl/glsl_parser_extras.h
index 4887672..843fdae 100644
--- a/src/glsl/glsl_parser_extras.h
+++ b/src/glsl/glsl_parser_extras.h
@@ -424,6 +424,8 @@ struct _mesa_glsl_parse_state {
bool ARB_shader_bit_encoding_warn;
bool ARB_shader_image_load_store_enable;
bool ARB_shader_image_load_store_warn;
+   bool ARB_shader_precision_enable;
+   bool ARB_shader_precision_warn;
bool ARB_shader_stencil_export_enable;
bool ARB_shader_stencil_export_warn;
bool ARB_shader_texture_lod_enable;
diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml
index 2d6bed2..e3cbab3 100644
--- a/src/mapi/glapi/gen/gl_API.xml
+++ b/src/mapi/glapi/gen/gl_API.xml
@@ -8247,7 +8247,11 @@
 
 http://www.w3.org/2001/XInclude"/>
 
-
+
+  
+
+
+
 
 http://www.w3.org/2001/XInclude"/>
 
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index e5bac7f..16f1241 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main/extensions.c
@@ -148,6 +148,7 @@ static const struct extension extension_table[] = {
{ "GL_ARB_shader_bit_encoding", o(ARB_shader_bit_encoding), 
GL, 2010 },
{ "GL_ARB_shader_image_load_store", 
o(ARB_shader_image_load_store), GL, 2011 },
{ "GL_ARB_shader_objects",  o(dummy_true),  
GL, 2002 },
+   { "GL_ARB_shader_precision",o(ARB_shader_precision),
GL, 2010 },
{ "GL_ARB_shader_stencil_export",   
o(ARB_shader_stencil_export),   GL, 2009 },
{ "GL_ARB_shader_texture_lod",  o(ARB_shader_texture_lod),  
GL, 2009 },
{ "GL_ARB_shading_language_100",o(dummy_true),  
GLL,2003 },
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index b95dfb9..4c83379 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -3757,6 +3757,7 @@ struct gl_extensions
GLboolean ARB_shader_atomic_counters;
GLboolean ARB_shader_bit_encoding;
GLboolean ARB_shader_image_load_store;
+   GLboolean ARB_shader_precision;
GLboolean ARB_shader_stencil_export;
GLboolean ARB_shader_texture_lod;
GLboolean ARB_shading_language_packing;

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Mesa (master): glcpp: Disallow undefining GL_* builtin macros.

[Chris Forbes]

Module: Mesa
Branch: master
Commit: b49a069bd3c96c8a144bb671863d0757fb421a07
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b49a069bd3c96c8a144bb671863d0757fb421a07

Author: Chris Forbes 
Date:   Sun Nov 30 09:54:59 2014 +1300

glcpp: Disallow undefining GL_* builtin macros.

Fixes the piglit test: spec/glsl-es-3.00/compiler/undef-GL_ES.vert

Signed-off-by: Chris Forbes 
Reviewed-by: Anuj Phogat 
Reviewed-by: Ian Romanick 

---

 src/glsl/glcpp/glcpp-parse.y |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y
index f1119eb..2877924 100644
--- a/src/glsl/glcpp/glcpp-parse.y
+++ b/src/glsl/glcpp/glcpp-parse.y
@@ -290,7 +290,8 @@ control_line_success:
macro_t *macro;
if (strcmp("__LINE__", $4) == 0
|| strcmp("__FILE__", $4) == 0
-   || strcmp("__VERSION__", $4) == 0)
+   || strcmp("__VERSION__", $4) == 0
+   || strncmp("GL_", $4, 3) == 0)
glcpp_error(& @1, parser, "Built-in (pre-defined)"
" macro names can not be undefined.");
 

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Mesa (master): glcpp: Fix `can not` to `cannot` in error message

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 6b0196934509ac76293581f7ca69a3399ffb2e0a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b0196934509ac76293581f7ca69a3399ffb2e0a

Author: Chris Forbes 
Date:   Sun Dec  7 11:49:28 2014 +1300

glcpp: Fix `can not` to `cannot` in error message

Signed-off-by: Chris Forbes 

---

 src/glsl/glcpp/glcpp-parse.y  |2 +-
 src/glsl/glcpp/tests/120-undef-builtin.c.expected |6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y
index 2877924..9b1a4f4 100644
--- a/src/glsl/glcpp/glcpp-parse.y
+++ b/src/glsl/glcpp/glcpp-parse.y
@@ -293,7 +293,7 @@ control_line_success:
|| strcmp("__VERSION__", $4) == 0
|| strncmp("GL_", $4, 3) == 0)
glcpp_error(& @1, parser, "Built-in (pre-defined)"
-   " macro names can not be undefined.");
+   " macro names cannot be undefined.");
 
macro = hash_table_find (parser->defines, $4);
if (macro) {
diff --git a/src/glsl/glcpp/tests/120-undef-builtin.c.expected 
b/src/glsl/glcpp/tests/120-undef-builtin.c.expected
index cdb9c29..3b736df 100644
--- a/src/glsl/glcpp/tests/120-undef-builtin.c.expected
+++ b/src/glsl/glcpp/tests/120-undef-builtin.c.expected
@@ -1,6 +1,6 @@
-0:1(1): preprocessor error: Built-in (pre-defined) macro names can not be 
undefined.
-0:2(1): preprocessor error: Built-in (pre-defined) macro names can not be 
undefined.
-0:3(1): preprocessor error: Built-in (pre-defined) macro names can not be 
undefined.
+0:1(1): preprocessor error: Built-in (pre-defined) macro names cannot be 
undefined.
+0:2(1): preprocessor error: Built-in (pre-defined) macro names cannot be 
undefined.
+0:3(1): preprocessor error: Built-in (pre-defined) macro names cannot be 
undefined.
 
 
 

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Mesa (master): i965/Gen6-7: Fix point sprites with PolygonMode(GL_POINT)

[Chris Forbes]

Module: Mesa
Branch: master
Commit: ed56c16820aea0e115768d77861fe266380f2595
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed56c16820aea0e115768d77861fe266380f2595

Author: Chris Forbes 
Date:   Fri Dec  5 19:43:13 2014 +1300

i965/Gen6-7: Fix point sprites with PolygonMode(GL_POINT)

This was an oversight in the original patch. When PolygonMode is
used, then front faces, back faces, or both may be rendered as
points and are affected by point sprite state.

Note that SNB/IVB can't actually be fully conformant here, for
a legacy context -- we don't have separate sets of pointsprite
enables for front and back faces. Haswell ignores pointsprite
state correctly in hardware for non-point rasterization, so can
do this correctly, but it doesn't seem worth it.

Signed-off-by: Chris Forbes 
Cc: "10.4" 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86764
Reviewed-by: Matt Turner 

---

 src/mesa/drivers/dri/i965/gen6_sf_state.c |6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c 
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index ccb6b30..fc73c57 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -133,6 +133,12 @@ static bool
 is_drawing_points(const struct brw_context *brw)
 {
/* Determine if the primitives *reaching the SF* are points */
+   /* _NEW_POLYGON */
+   if (brw->ctx.Polygon.FrontMode == GL_POINT ||
+   brw->ctx.Polygon.BackMode == GL_POINT) {
+  return true;
+   }
+
if (brw->geometry_program) {
   /* BRW_NEW_GEOMETRY_PROGRAM */
   return brw->geometry_program->OutputType == GL_POINTS;

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Mesa (master): i965: Add opcode names for FS interpolation opcodes

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 680f72d6f2259a1dd382a1876a594b407f933278
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=680f72d6f2259a1dd382a1876a594b407f933278

Author: Chris Forbes 
Date:   Sun Dec  7 10:07:16 2014 +1300

i965: Add opcode names for FS interpolation opcodes

Signed-off-by: Chris Forbes 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_shader.cpp |9 +
 1 file changed, 9 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp 
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 183a4f1..8f6a3de 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -498,6 +498,15 @@ brw_instruction_name(enum opcode op)
case FS_OPCODE_PLACEHOLDER_HALT:
   return "placeholder_halt";
 
+   case FS_OPCODE_INTERPOLATE_AT_CENTROID:
+  return "interp_centroid";
+   case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
+  return "interp_sample";
+   case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
+  return "interp_shared_offset";
+   case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
+  return "interp_per_slot_offset";
+
case VS_OPCODE_URB_WRITE:
   return "vs_urb_write";
case VS_OPCODE_PULL_CONSTANT_LOAD:

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Mesa (master): i965: Fix regs read for FS_OPCODE_INTERP_PER_SLOT_OFFSET

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 092c73a7c32b240a26ffeab2ee475f6d590540b2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=092c73a7c32b240a26ffeab2ee475f6d590540b2

Author: Chris Forbes 
Date:   Sun Dec  7 10:12:36 2014 +1300

i965: Fix regs read for FS_OPCODE_INTERP_PER_SLOT_OFFSET

Dead code elimination was eating the Y offset.

Fixes the piglit test:
spec/ARB_gpu_shader5/arb_gpu_shader5-interpolateAtOffset-nonconst

Signed-off-by: Chris Forbes 
Reviewed-by: Jason Ekstrand 

---

 src/mesa/drivers/dri/i965/brw_fs.cpp |2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 37857e9..389c8ae 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -902,6 +902,8 @@ fs_inst::regs_read(fs_visitor *v, int arg) const
   return mlen;
} else if (opcode == SHADER_OPCODE_UNTYPED_SURFACE_READ && arg == 0) {
   return mlen;
+   } else if (opcode == FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET && arg == 0) {
+  return mlen;
}
 
switch (src[arg].file) {

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Mesa (master): i965/Gen6-7: Do not replace texcoords with point coord if not drawing points

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 0008d0e59eff365079323918508ffc87355a6bfd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0008d0e59eff365079323918508ffc87355a6bfd

Author: Chris Forbes 
Date:   Tue Nov 25 09:44:19 2014 +1300

i965/Gen6-7: Do not replace texcoords with point coord if not drawing points

Fixes broken rendering in Windows-based QtQuick2 apps run through Wine.
This library sets all texture units' GL_COORD_REPLACE, leaves point
sprite mode enabled, and then draws a triangle fan.

Will need a slightly different fix for Gen4-5, but I don't have my old
machines in a usable state currently.

V2: - Simplify patch -- the real changes are no longer duplicated across
  the Gen6 and Gen7 atoms.
- Also don't clobber attr overrides -- which matters on Haswell too,
  and fixes the other half of the problem
- Fix newly-introduced warnings
V3: - Use BRW_NEW_GEOMETRY_PROGRAM and brw->geometry_program rather than
  core flag and state; keep the state flags in order.

Signed-off-by: Chris Forbes 
Cc: "10.4" 
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84651
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/gen6_sf_state.c |   57 +++--
 src/mesa/drivers/dri/i965/gen7_sf_state.c |4 +-
 2 files changed, 49 insertions(+), 12 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c 
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 24d2754..fd7c395 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -129,6 +129,20 @@ get_attr_override(const struct brw_vue_map *vue_map, int 
urb_entry_read_offset,
 }
 
 
+static bool
+is_drawing_points(const struct brw_context *brw)
+{
+   /* Determine if the primitives *reaching the SF* are points */
+   if (brw->geometry_program) {
+  /* BRW_NEW_GEOMETRY_PROGRAM */
+  return brw->geometry_program->OutputType == GL_POINTS;
+   } else {
+  /* BRW_NEW_PRIMITIVE */
+  return brw->primitive == _3DPRIM_POINTLIST;
+   }
+}
+
+
 /**
  * Create the mapping from the FS inputs we produce to the previous pipeline
  * stage (GS or VS) outputs they source from.
@@ -149,6 +163,23 @@ calculate_attr_overrides(const struct brw_context *brw,
/* _NEW_LIGHT */
bool shade_model_flat = brw->ctx.Light.ShadeModel == GL_FLAT;
 
+   /* From the Ivybridge PRM, Vol 2 Part 1, 3DSTATE_SBE,
+* description of dw10 Point Sprite Texture Coordinate Enable:
+*
+* "This field must be programmed to zero when non-point primitives
+* are rendered."
+*
+* The SandyBridge PRM doesn't explicitly say that point sprite enables
+* must be programmed to zero when rendering non-point primitives, but
+* the IvyBridge PRM does, and if we don't, we get garbage.
+*
+* This is not required on Haswell, as the hardware ignores this state
+* when drawing non-points -- although we do still need to be careful to
+* correctly set the attr overrides.
+*/
+   /* BRW_NEW_PRIMITIVE | BRW_NEW_GEOMETRY_PROGRAM */
+   bool drawing_points = is_drawing_points(brw);
+
/* Initialize all the attr_overrides to 0.  In the loop below we'll modify
 * just the ones that correspond to inputs used by the fs.
 */
@@ -167,18 +198,20 @@ calculate_attr_overrides(const struct brw_context *brw,
 
   /* _NEW_POINT */
   bool point_sprite = false;
-  if (brw->ctx.Point.PointSprite &&
- (attr >= VARYING_SLOT_TEX0 && attr <= VARYING_SLOT_TEX7) &&
- brw->ctx.Point.CoordReplace[attr - VARYING_SLOT_TEX0]) {
- point_sprite = true;
+  if (drawing_points) {
+ if (brw->ctx.Point.PointSprite &&
+ (attr >= VARYING_SLOT_TEX0 && attr <= VARYING_SLOT_TEX7) &&
+ brw->ctx.Point.CoordReplace[attr - VARYING_SLOT_TEX0]) {
+point_sprite = true;
+ }
+
+ if (attr == VARYING_SLOT_PNTC)
+point_sprite = true;
+
+ if (point_sprite)
+*point_sprite_enables |= (1 << input_index);
   }
 
-  if (attr == VARYING_SLOT_PNTC)
- point_sprite = true;
-
-  if (point_sprite)
-*point_sprite_enables |= (1 << input_index);
-
   /* flat shading */
   if (interp_qualifier == INTERP_QUALIFIER_FLAT ||
   (shade_model_flat && is_gl_Color &&
@@ -410,7 +443,9 @@ const struct brw_tracked_state gen6_sf_state = {
_NEW_POINT |
 _NEW_MULTISAMPLE),
   .brw   = (BRW_NEW_CONTEXT |
-   BRW_NEW_FRAGMENT_PROGRAM |
+BRW_NEW_FRAGMENT_PROGRAM |
+BRW_NEW_GEOMETRY_PROGRAM |
+BRW_NEW_PRIMITIVE |
 BRW_NEW_VUE_MAP_GEOM_OUT),
   .cache = CACHE_NEW_WM_PROG
},
diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c 
b/src/mesa/drivers/dri/i9

Mesa (master): mesa: Fix Get(GL_TRANSPOSE_CURRENT_MATRIX_ARB) to transpose

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 2b4fe85f0ea613463b8bba3149183eca97e98e75
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b4fe85f0ea613463b8bba3149183eca97e98e75

Author: Chris Forbes 
Date:   Mon Nov 24 21:44:38 2014 +1300

mesa: Fix Get(GL_TRANSPOSE_CURRENT_MATRIX_ARB) to transpose

This was just returning the same value as GL_CURRENT_MATRIX_ARB.
Spotted while investigating something else in apitrace.

Signed-off-by: Chris Forbes 
Cc: "10.3 10.4" 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/main/get_hash_params.py |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/main/get_hash_params.py b/src/mesa/main/get_hash_params.py
index a931d9d..09a61ac 100644
--- a/src/mesa/main/get_hash_params.py
+++ b/src/mesa/main/get_hash_params.py
@@ -627,7 +627,7 @@ descriptor=[
 # == GL_CURRENT_MATRIX_NV
   [ "CURRENT_MATRIX_ARB", "LOC_CUSTOM, TYPE_MATRIX, 0, 
extra_ARB_vertex_program_ARB_fragment_program" ],
 # == GL_CURRENT_MATRIX_NV
-  [ "TRANSPOSE_CURRENT_MATRIX_ARB", "LOC_CUSTOM, TYPE_MATRIX, 0, 
extra_ARB_vertex_program_ARB_fragment_program" ],
+  [ "TRANSPOSE_CURRENT_MATRIX_ARB", "LOC_CUSTOM, TYPE_MATRIX_T, 0, 
extra_ARB_vertex_program_ARB_fragment_program" ],
 # == GL_PROGRAM_ERROR_POSITION_NV
   [ "PROGRAM_ERROR_POSITION_ARB", "CONTEXT_INT(Program.ErrorPos), 
extra_ARB_vertex_program_ARB_fragment_program" ],
 

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Mesa (master): glsl: Generate unique names for each const array lowered to uniforms

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 129178893b2260df22db96327c5ca9c2ce7db046
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=129178893b2260df22db96327c5ca9c2ce7db046

Author: Chris Forbes 
Date:   Tue Nov 18 21:15:05 2014 +1300

glsl: Generate unique names for each const array lowered to uniforms

Uniform names (even for hidden uniforms) are required to be unique; some
parts of the compiler assume they can be looked up by name.

Fixes the piglit test: tests/spec/glsl-1.20/linker/array-initializers-1

Signed-off-by: Chris Forbes 
Cc: "10.4" 
Reviewed-by: Kenneth Graunke 

---

 src/glsl/lower_const_arrays_to_uniforms.cpp |6 +-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/glsl/lower_const_arrays_to_uniforms.cpp 
b/src/glsl/lower_const_arrays_to_uniforms.cpp
index b3c0ee2..700e903 100644
--- a/src/glsl/lower_const_arrays_to_uniforms.cpp
+++ b/src/glsl/lower_const_arrays_to_uniforms.cpp
@@ -49,6 +49,7 @@ public:
{
   instructions = insts;
   progress = false;
+  index = 0;
}
 
bool run()
@@ -62,6 +63,7 @@ public:
 private:
exec_list *instructions;
bool progress;
+   unsigned index;
 };
 
 void
@@ -76,8 +78,10 @@ lower_const_array_visitor::handle_rvalue(ir_rvalue **rvalue)
 
void *mem_ctx = ralloc_parent(con);
 
+   char *uniform_name = ralloc_asprintf(mem_ctx, "constarray__%d", index++);
+
ir_variable *uni =
-  new(mem_ctx) ir_variable(con->type, "constarray", ir_var_uniform);
+  new(mem_ctx) ir_variable(con->type, uniform_name, ir_var_uniform);
uni->constant_initializer = con;
uni->constant_value = con;
uni->data.has_initializer = true;

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Mesa (master): i965: Handle nested uniform array indexing

[Chris Forbes]

Module: Mesa
Branch: master
Commit: adefccd12a534f0deac7b78db73693fe1dcef2ec
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=adefccd12a534f0deac7b78db73693fe1dcef2ec

Author: Chris Forbes 
Date:   Tue Nov 18 21:15:06 2014 +1300

i965: Handle nested uniform array indexing

When converting a uniform array reference to a pull constant load, the
`reladdr` expression itself may have its own `reladdr`, arbitrarily
deeply. This arises from expressions like:

   a[b[x]] where a, b are uniform arrays (or lowered const arrays),
   and x is not a constant.

Just iterate the lowering to pull constants until we stop seeing these
nested. For most shaders, there will be only one pass through this loop.

Fixes the piglit test:
tests/spec/glsl-1.20/linker/double-indirect-1.shader_test

Signed-off-by: Chris Forbes 
Cc: "10.3 10.4" 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |   66 +---
 1 file changed, 37 insertions(+), 29 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 7d4bf55..5cc2abd 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -3353,6 +3353,7 @@ 
vec4_visitor::move_uniform_array_access_to_pull_constants()
 {
int pull_constant_loc[this->uniforms];
memset(pull_constant_loc, -1, sizeof(pull_constant_loc));
+   bool nested_reladdr;
 
/* Walk through and find array access of uniforms.  Put a copy of that
 * uniform in the pull constant buffer.
@@ -3360,44 +3361,51 @@ 
vec4_visitor::move_uniform_array_access_to_pull_constants()
 * Note that we don't move constant-indexed accesses to arrays.  No
 * testing has been done of the performance impact of this choice.
 */
-   foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {
-  for (int i = 0 ; i < 3; i++) {
-if (inst->src[i].file != UNIFORM || !inst->src[i].reladdr)
-   continue;
+   do {
+  nested_reladdr = false;
 
-int uniform = inst->src[i].reg;
+  foreach_block_and_inst_safe(block, vec4_instruction, inst, cfg) {
+ for (int i = 0 ; i < 3; i++) {
+if (inst->src[i].file != UNIFORM || !inst->src[i].reladdr)
+   continue;
 
-/* If this array isn't already present in the pull constant buffer,
- * add it.
- */
-if (pull_constant_loc[uniform] == -1) {
-   const gl_constant_value **values =
-   &stage_prog_data->param[uniform * 4];
+int uniform = inst->src[i].reg;
 
-   pull_constant_loc[uniform] = stage_prog_data->nr_pull_params / 4;
+if (inst->src[i].reladdr->reladdr)
+   nested_reladdr = true;  /* will need another pass */
 
-   assert(uniform < uniform_array_size);
-   for (int j = 0; j < uniform_size[uniform] * 4; j++) {
-  stage_prog_data->pull_param[stage_prog_data->nr_pull_params++]
-  = values[j];
-   }
-}
+/* If this array isn't already present in the pull constant buffer,
+ * add it.
+ */
+if (pull_constant_loc[uniform] == -1) {
+   const gl_constant_value **values =
+  &stage_prog_data->param[uniform * 4];
 
-/* Set up the annotation tracking for new generated instructions. */
-base_ir = inst->ir;
-current_annotation = inst->annotation;
+   pull_constant_loc[uniform] = stage_prog_data->nr_pull_params / 
4;
 
-dst_reg temp = dst_reg(this, glsl_type::vec4_type);
+   assert(uniform < uniform_array_size);
+   for (int j = 0; j < uniform_size[uniform] * 4; j++) {
+  
stage_prog_data->pull_param[stage_prog_data->nr_pull_params++]
+ = values[j];
+   }
+}
 
-emit_pull_constant_load(block, inst, temp, inst->src[i],
-pull_constant_loc[uniform]);
+/* Set up the annotation tracking for new generated instructions. 
*/
+base_ir = inst->ir;
+current_annotation = inst->annotation;
 
-inst->src[i].file = temp.file;
-inst->src[i].reg = temp.reg;
-inst->src[i].reg_offset = temp.reg_offset;
-inst->src[i].reladdr = NULL;
+dst_reg temp = dst_reg(this, glsl_type::vec4_type);
+
+emit_pull_constant_load(block, inst, temp, inst->src[i],
+pull_constant_loc[uniform]);
+
+inst->src[i].file = temp.file;
+inst->src[i].reg = temp.reg;
+inst->src[i].reg_offset = temp.reg_offset;
+inst->src[i].reladdr = NULL;
+ }
   }
-   }
+   } while (nes

Mesa (master): mesa: Fix function name in GetActiveUniformName error

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 89b9ef937c11598817e0ec2d20d70b5254d4e406
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=89b9ef937c11598817e0ec2d20d70b5254d4e406

Author: Chris Forbes 
Date:   Sun Nov 23 13:31:10 2014 +1300

mesa: Fix function name in GetActiveUniformName error

Signed-off-by: Chris Forbes 

---

 src/mesa/main/uniforms.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/main/uniforms.c b/src/mesa/main/uniforms.c
index f7d5e89..d2d70e7 100644
--- a/src/mesa/main/uniforms.c
+++ b/src/mesa/main/uniforms.c
@@ -1208,7 +1208,7 @@ _mesa_GetActiveUniformName(GLuint program, GLuint 
uniformIndex,
struct gl_shader_program *shProg;
 
if (!ctx->Extensions.ARB_uniform_buffer_object) {
-  _mesa_error(ctx, GL_INVALID_OPERATION, "glGetActiveUniformBlockiv");
+  _mesa_error(ctx, GL_INVALID_OPERATION, "glGetActiveUniformName");
   return;
}
 

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Mesa (master): i965: Fix sampler state pointer adjustment for nonconst samplers

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 1ca88aa58217239da84a426c29f05b5b53855951
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1ca88aa58217239da84a426c29f05b5b53855951

Author: Chris Forbes 
Date:   Wed Nov  5 06:41:13 2014 +1300

i965: Fix sampler state pointer adjustment for nonconst samplers

This started hitting an assertion recently. Only affects Haswell
(Ivybridge doesn't support this meddling with the sampler state pointer,
and ARB_gpu_shader5 is not enabled yet on Broadwell)

14 Piglits crash->pass.

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_eu_emit.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index bb6334b..bb12a26 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -2409,7 +2409,7 @@ void brw_adjust_sampler_state_pointer(struct brw_compile 
*p,
 
   struct brw_reg temp = vec1(retype(scratch, BRW_REGISTER_TYPE_UD));
 
-  brw_AND(p, temp, sampler_index, brw_imm_ud(0x0f0));
+  brw_AND(p, temp, get_element_ud(sampler_index, 0), brw_imm_ud(0x0f0));
   brw_SHL(p, temp, temp, brw_imm_ud(4));
   brw_ADD(p,
   get_element_ud(header, 3),

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Mesa (master): mesa: Fix order of errors for glDrawTransformFeedbackStream

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 0d5f4960a468947f9862bf5de2a71fce63b50cf7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d5f4960a468947f9862bf5de2a71fce63b50cf7

Author: Chris Forbes 
Date:   Sat Oct 18 21:12:07 2014 +1300

mesa: Fix order of errors for glDrawTransformFeedbackStream

The OpenGL 4.0 core profile specification, section 2.17.3
Transform Feedback Draw Operations says:

   "The error INVALID_VALUE is generated if  is greater
than or equal to the value of MAX_VERTEX_STREAMS.
...
The error INVALID_OPERATION
is generated if EndTransformFeedback has never been called
while the object named by id was bound."

Fixes the piglit test:
   
ARB_transform_feedback3/arb_transform_feedback3-draw_using_invalid_stream_index
   (with the test itself fixed to eliminate an unrelated failure)

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/main/api_validate.c |   10 +-
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/mesa/main/api_validate.c b/src/mesa/main/api_validate.c
index 9b80600..a3a2d25 100644
--- a/src/mesa/main/api_validate.c
+++ b/src/mesa/main/api_validate.c
@@ -749,17 +749,17 @@ _mesa_validate_DrawTransformFeedback(struct gl_context 
*ctx,
   return GL_FALSE;
}
 
-   if (!obj->EndedAnytime) {
-  _mesa_error(ctx, GL_INVALID_OPERATION, "glDrawTransformFeedback*");
-  return GL_FALSE;
-   }
-
if (stream >= ctx->Const.MaxVertexStreams) {
   _mesa_error(ctx, GL_INVALID_VALUE,
   "glDrawTransformFeedbackStream*(index>=MaxVertexStream)");
   return GL_FALSE;
}
 
+   if (!obj->EndedAnytime) {
+  _mesa_error(ctx, GL_INVALID_OPERATION, "glDrawTransformFeedback*");
+  return GL_FALSE;
+   }
+
if (numInstances <= 0) {
   if (numInstances < 0)
  _mesa_error(ctx, GL_INVALID_VALUE,

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Mesa (master): i965: Dirty state in BO reallocation based on usage history

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 1655f6fc61a2502d8c1fb87344f5e8b25bff8081
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1655f6fc61a2502d8c1fb87344f5e8b25bff8081

Author: Chris Forbes 
Date:   Wed Oct  1 19:29:25 2014 +1300

i965: Dirty state in BO reallocation based on usage history

Signed-off-by: Chris Forbes 
Reviewed-by: Anuj Phogat 

---

 src/mesa/drivers/dri/i965/intel_buffer_objects.c |5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c 
b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index 82e0744..9298e24 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -110,7 +110,10 @@ intel_bufferobj_alloc_buffer(struct brw_context *brw,
 
/* the buffer might be bound as a uniform buffer, need to update it
 */
-   brw->state.dirty.brw |= BRW_NEW_UNIFORM_BUFFER;
+   if (intel_obj->Base.UsageHistory & USAGE_UNIFORM_BUFFER)
+  brw->state.dirty.brw |= BRW_NEW_UNIFORM_BUFFER;
+   if (intel_obj->Base.UsageHistory & USAGE_TEXTURE_BUFFER)
+  brw->state.dirty.brw |= BRW_NEW_TEXTURE_BUFFER;
 
intel_bufferobj_mark_inactive(intel_obj);
 }

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Mesa (master): meta/msaa-blit: consider weird sample count case unreachable

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 81041c4a4a170e6bb332013085117d3fc67d517b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=81041c4a4a170e6bb332013085117d3fc67d517b

Author: Chris Forbes 
Date:   Sat Oct 11 18:19:17 2014 +1300

meta/msaa-blit: consider weird sample count case unreachable

Suppresses a bunch of warning noise about sample_map possibly being used
uninitialized.

Signed-off-by: Chris Forbes 
Reviewed-by: Anuj Phogat 

---

 src/mesa/drivers/common/meta_blit.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/common/meta_blit.c 
b/src/mesa/drivers/common/meta_blit.c
index c6616d9..01cb532 100644
--- a/src/mesa/drivers/common/meta_blit.c
+++ b/src/mesa/drivers/common/meta_blit.c
@@ -134,6 +134,7 @@ setup_glsl_msaa_blit_scaled_shader(struct gl_context *ctx,
   break;
default:
   _mesa_problem(ctx, "Unsupported sample count %d\n", samples);
+  unreachable("Unsupported sample count");
}
 
/* Create sample map string. */

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Mesa (master): mesa: Add usage history bitfield to buffer objects

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 3d989467f1700219b053317e8aafd2965f051273
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3d989467f1700219b053317e8aafd2965f051273

Author: Chris Forbes 
Date:   Wed Oct  1 19:19:47 2014 +1300

mesa: Add usage history bitfield to buffer objects

In the drivers, we occasionally want to reallocate the backing
store for a buffer object; often to avoid waiting for the GPU
to be finished with the previous contents.

At the point that happens, we don't have a good way of determining
where else the buffer object may be bound, and so no good way of
determining which dirty flags need to be raised -- it's fairly
expensive to go looking at all the possible binding points.

Until now, we've considered any BO to be possibly bound as a UBO or
TexBO, and flagged all that state to be reemitted.

Instead, remember what kinds of binding point this buffer has ever
been used with, so that the drivers can flag only what they need.
I don't expect these bits to ever be reset, but that doesn't matter
for reasonable apps.

Signed-off-by: Chris Forbes 
Reviewed-by: Anuj Phogat 

---

 src/mesa/main/mtypes.h |9 +
 1 file changed, 9 insertions(+)

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 5e9453b..881c26c 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -1465,6 +1465,14 @@ struct gl_buffer_mapping {
 
 
 /**
+ * Usages we've seen for a buffer object.
+ */
+typedef enum {
+   USAGE_UNIFORM_BUFFER = 0x1,
+} gl_buffer_usage;
+
+
+/**
  * GL_ARB_vertex/pixel_buffer_object buffer object
  */
 struct gl_buffer_object
@@ -1481,6 +1489,7 @@ struct gl_buffer_object
GLboolean Written;   /**< Ever written to? (for debugging) */
GLboolean Purgeable; /**< Is the buffer purgeable under memory pressure? */
GLboolean Immutable; /**< GL_ARB_buffer_storage */
+   gl_buffer_usage UsageHistory; /**< How has this buffer been used so far? */
 
struct gl_buffer_mapping Mappings[MAP_COUNT];
 };

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Mesa (master): i965: Flag BRW_ATOMIC_COUNTER_BUFFER when a possible ABO is respecified

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 2883aff3becbb5a71b0bd270266e58114c98ef12
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2883aff3becbb5a71b0bd270266e58114c98ef12

Author: Chris Forbes 
Date:   Sun Oct 12 12:28:43 2014 +1300

i965: Flag BRW_ATOMIC_COUNTER_BUFFER when a possible ABO is respecified

Signed-off-by: Chris Forbes 
Reviewed-by: Francisco Jerez 

---

 src/mesa/drivers/dri/i965/intel_buffer_objects.c |2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c 
b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index 9298e24..50523fe 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -114,6 +114,8 @@ intel_bufferobj_alloc_buffer(struct brw_context *brw,
   brw->state.dirty.brw |= BRW_NEW_UNIFORM_BUFFER;
if (intel_obj->Base.UsageHistory & USAGE_TEXTURE_BUFFER)
   brw->state.dirty.brw |= BRW_NEW_TEXTURE_BUFFER;
+   if (intel_obj->Base.UsageHistory & USAGE_ATOMIC_COUNTER_BUFFER)
+  brw->state.dirty.brw |= BRW_NEW_ATOMIC_BUFFER;
 
intel_bufferobj_mark_inactive(intel_obj);
 }

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Mesa (master): i965/disasm: Add missing message type for Gen7 DP untyped surface read

[Chris Forbes]

Module: Mesa
Branch: master
Commit: f1261db1eea0bea739d5d9e6e1f4ef8192431e26
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f1261db1eea0bea739d5d9e6e1f4ef8192431e26

Author: Chris Forbes 
Date:   Tue Sep 23 22:16:23 2014 +1200

i965/disasm: Add missing message type for Gen7 DP untyped surface read

This is used to implement GLSL's atomicCounter() intrinsic. Previously
it *worked*, but the disassembly was bogus.

Signed-off-by: Chris Forbes 
Reviewed-by: Francisco Jerez 

---

 src/mesa/drivers/dri/i965/brw_disasm.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
b/src/mesa/drivers/dri/i965/brw_disasm.c
index a729d11..53ec767 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -434,6 +434,7 @@ static const char *const dp_dc0_msg_type_gen7[16] = {
[GEN7_DATAPORT_DC_OWORD_DUAL_BLOCK_READ] = "DC OWORD dual block read",
[GEN7_DATAPORT_DC_DWORD_SCATTERED_READ] = "DC DWORD scattered read",
[GEN7_DATAPORT_DC_BYTE_SCATTERED_READ] = "DC byte scattered read",
+   [GEN7_DATAPORT_DC_UNTYPED_SURFACE_READ] = "DC untyped surface read",
[GEN7_DATAPORT_DC_UNTYPED_ATOMIC_OP] = "DC untyped atomic",
[GEN7_DATAPORT_DC_MEMORY_FENCE] = "DC mfence",
[GEN7_DATAPORT_DC_OWORD_BLOCK_WRITE] = "DC OWORD block write",

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Mesa (master): i965: Correctly use ABO count to trigger flagging of new surfaces.

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 0dc56600aa0fae509b60da09f57d1f649125be04
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0dc56600aa0fae509b60da09f57d1f649125be04

Author: Chris Forbes 
Date:   Tue Sep 23 22:16:21 2014 +1200

i965: Correctly use ABO count to trigger flagging of new surfaces.

This would have *almost never* actually been an issue, since other state
tends to get flagged at the same time as new ABOs -- but still bogus.

Signed-off-by: Chris Forbes 
Reviewed-by: Francisco Jerez 

---

 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index d35dee0..ef46dd7 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -919,7 +919,7 @@ brw_upload_abo_surfaces(struct brw_context *brw,
&surf_offsets[i], true);
}
 
-   if (prog->NumUniformBlocks)
+   if (prog->NumAtomicBuffers)
   brw->state.dirty.brw |= BRW_NEW_SURFACES;
 }
 

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Mesa (master): mesa: Mark buffer objects that are used as TexBOs

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 8db38ba4d2f6dee62009f40208cb11bc6547167f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8db38ba4d2f6dee62009f40208cb11bc6547167f

Author: Chris Forbes 
Date:   Wed Oct  1 20:04:37 2014 +1300

mesa: Mark buffer objects that are used as TexBOs

Signed-off-by: Chris Forbes 
Reviewed-by: Anuj Phogat 

---

 src/mesa/main/mtypes.h   |3 +++
 src/mesa/main/teximage.c |6 ++
 2 files changed, 9 insertions(+)

diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 881c26c..2a01508 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -1469,6 +1469,7 @@ struct gl_buffer_mapping {
  */
 typedef enum {
USAGE_UNIFORM_BUFFER = 0x1,
+   USAGE_TEXTURE_BUFFER = 0x2,
 } gl_buffer_usage;
 
 
@@ -4069,6 +4070,8 @@ struct gl_driver_flags
 */
uint64_t NewUniformBuffer;
 
+   uint64_t NewTextureBuffer;
+
/**
 * gl_context::AtomicBufferBindings
 */
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index c0298af..4f4bb11 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -4652,6 +4652,12 @@ texbufferrange(struct gl_context *ctx, GLenum target, 
GLenum internalFormat,
   texObj->BufferSize = size;
}
_mesa_unlock_texture(ctx, texObj);
+
+   ctx->NewDriverState |= ctx->DriverFlags.NewTextureBuffer;
+
+   if (bufObj) {
+  bufObj->UsageHistory |= USAGE_TEXTURE_BUFFER;
+   }
 }
 
 

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Mesa (master): i965: Have mesa flag BRW_NEW_TEXTURE_BUFFER when a TexBO binding changes

[Chris Forbes]

Module: Mesa
Branch: master
Commit: c442745981ff307c7d45db4f059728912cda8220
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c442745981ff307c7d45db4f059728912cda8220

Author: Chris Forbes 
Date:   Wed Oct  1 21:31:45 2014 +1300

i965: Have mesa flag BRW_NEW_TEXTURE_BUFFER when a TexBO binding changes

Signed-off-by: Chris Forbes 
Reviewed-by: Anuj Phogat 

---

 src/mesa/drivers/dri/i965/brw_state_upload.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 4ca7cb4..a691319 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -399,6 +399,7 @@ void brw_init_state( struct brw_context *brw )
ctx->DriverFlags.NewTransformFeedbackProg = BRW_NEW_TRANSFORM_FEEDBACK;
ctx->DriverFlags.NewRasterizerDiscard = BRW_NEW_RASTERIZER_DISCARD;
ctx->DriverFlags.NewUniformBuffer = BRW_NEW_UNIFORM_BUFFER;
+   ctx->DriverFlags.NewTextureBuffer = BRW_NEW_TEXTURE_BUFFER;
ctx->DriverFlags.NewAtomicBuffer = BRW_NEW_ATOMIC_BUFFER;
 }
 

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Mesa (master): i965: No longer reemit textures on BRW_NEW_UNIFORM_BUFFER

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 25189c72ce49a4af81a270e11f3a987669727406
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=25189c72ce49a4af81a270e11f3a987669727406

Author: Chris Forbes 
Date:   Wed Oct  1 20:38:43 2014 +1300

i965: No longer reemit textures on BRW_NEW_UNIFORM_BUFFER

This didn't make any sense, but papered over the missing TexBO flagging
we've just fixed, in a bunch of cases.

Signed-off-by: Chris Forbes 
Reviewed-by: Anuj Phogat 

---

 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 87d6577..d35dee0 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -296,7 +296,7 @@ brw_update_texture_surface(struct gl_context *ctx,
struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit);
uint32_t *surf;
 
-   /* BRW_NEW_UNIFORM_BUFFER */
+   /* BRW_NEW_TEXTURE_BUFFER */
if (tObj->Target == GL_TEXTURE_BUFFER) {
   brw_update_buffer_texture_surface(ctx, unit, surf_offset);
   return;
@@ -824,7 +824,6 @@ const struct brw_tracked_state brw_texture_surfaces = {
.dirty = {
   .mesa = _NEW_TEXTURE,
   .brw = BRW_NEW_BATCH |
- BRW_NEW_UNIFORM_BUFFER |
  BRW_NEW_TEXTURE_BUFFER |
  BRW_NEW_VERTEX_PROGRAM |
  BRW_NEW_GEOMETRY_PROGRAM |

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Mesa (master): mesa: Mark buffer objects which are bound as UBOs

[Chris Forbes]

Module: Mesa
Branch: master
Commit: fe3133fe78a2cfe8a36d1b6a9eb4a9e89f3f59ed
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fe3133fe78a2cfe8a36d1b6a9eb4a9e89f3f59ed

Author: Chris Forbes 
Date:   Wed Oct  1 19:27:11 2014 +1300

mesa: Mark buffer objects which are bound as UBOs

When a buffer object is bound to one of the indexed uniform buffer
binding points, assume that from that point on it may be used as
a uniform buffer.

Signed-off-by: Chris Forbes 
Reviewed-by: Anuj Phogat 

---

 src/mesa/main/bufferobj.c |6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index b6879ce..c92056a 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -2652,6 +2652,12 @@ set_ubo_binding(struct gl_context *ctx,
binding->Offset = offset;
binding->Size = size;
binding->AutomaticSize = autoSize;
+
+   /* If this is a real buffer object, mark it has having been used
+* at some point as a UBO.
+*/
+   if (size >= 0)
+  bufObj->UsageHistory |= USAGE_UNIFORM_BUFFER;
 }
 
 /**

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Mesa (master): mesa: Mark buffer objects that are used as atomic counter buffers

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 7bd6dfe93401ad6d6ba5018cbe167be8ce29d09d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7bd6dfe93401ad6d6ba5018cbe167be8ce29d09d

Author: Chris Forbes 
Date:   Sun Oct 12 12:27:31 2014 +1300

mesa: Mark buffer objects that are used as atomic counter buffers

Signed-off-by: Chris Forbes 
Reviewed-by: Francisco Jerez 

---

 src/mesa/main/bufferobj.c |1 +
 src/mesa/main/mtypes.h|1 +
 2 files changed, 2 insertions(+)

diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index c92056a..d648308 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -2770,6 +2770,7 @@ set_atomic_buffer_binding(struct gl_context *ctx,
} else {
   binding->Offset = offset;
   binding->Size = size;
+  bufObj->UsageHistory |= USAGE_ATOMIC_COUNTER_BUFFER;
}
 }
 
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 2a01508..9f44eda 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -1470,6 +1470,7 @@ struct gl_buffer_mapping {
 typedef enum {
USAGE_UNIFORM_BUFFER = 0x1,
USAGE_TEXTURE_BUFFER = 0x2,
+   USAGE_ATOMIC_COUNTER_BUFFER = 0x4,
 } gl_buffer_usage;
 
 

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Mesa (master): i965: Add new dirty flag for new TexBOs.

[Chris Forbes]

Module: Mesa
Branch: master
Commit: be5df289416f7b4b24811722cea8da9a3fe75ee3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=be5df289416f7b4b24811722cea8da9a3fe75ee3

Author: Chris Forbes 
Date:   Wed Oct  1 20:09:17 2014 +1300

i965: Add new dirty flag for new TexBOs.

Signed-off-by: Chris Forbes 
Reviewed-by: Anuj Phogat 

---

 src/mesa/drivers/dri/i965/brw_context.h  |2 ++
 src/mesa/drivers/dri/i965/brw_state_upload.c |1 +
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |1 +
 3 files changed, 4 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index 884e28b..45d72d2 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -182,6 +182,7 @@ enum brw_state_id {
BRW_STATE_INTERPOLATION_MAP,
BRW_STATE_PUSH_CONSTANT_ALLOCATION,
BRW_STATE_NUM_SAMPLES,
+   BRW_STATE_TEXTURE_BUFFER,
BRW_NUM_STATE_BITS
 };
 
@@ -222,6 +223,7 @@ enum brw_state_id {
 #define BRW_NEW_INTERPOLATION_MAP   (1ull << BRW_STATE_INTERPOLATION_MAP)
 #define BRW_NEW_PUSH_CONSTANT_ALLOCATION (1ull << 
BRW_STATE_PUSH_CONSTANT_ALLOCATION)
 #define BRW_NEW_NUM_SAMPLES (1ull << BRW_STATE_NUM_SAMPLES)
+#define BRW_NEW_TEXTURE_BUFFER  (1ull << BRW_STATE_TEXTURE_BUFFER)
 
 struct brw_state_flags {
/** State update flags signalled by mesa internals */
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c 
b/src/mesa/drivers/dri/i965/brw_state_upload.c
index 9e3cfb8..4ca7cb4 100644
--- a/src/mesa/drivers/dri/i965/brw_state_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
@@ -513,6 +513,7 @@ static struct dirty_bit_map brw_bits[] = {
DEFINE_BIT(BRW_NEW_INTERPOLATION_MAP),
DEFINE_BIT(BRW_NEW_PUSH_CONSTANT_ALLOCATION),
DEFINE_BIT(BRW_NEW_NUM_SAMPLES),
+   DEFINE_BIT(BRW_NEW_TEXTURE_BUFFER),
{0, 0, 0}
 };
 
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 23ec821..87d6577 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -825,6 +825,7 @@ const struct brw_tracked_state brw_texture_surfaces = {
   .mesa = _NEW_TEXTURE,
   .brw = BRW_NEW_BATCH |
  BRW_NEW_UNIFORM_BUFFER |
+ BRW_NEW_TEXTURE_BUFFER |
  BRW_NEW_VERTEX_PROGRAM |
  BRW_NEW_GEOMETRY_PROGRAM |
  BRW_NEW_FRAGMENT_PROGRAM,

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Mesa (master): i965: Fix typo in comment

[Chris Forbes]

Module: Mesa
Branch: master
Commit: e4e3b0fc0dfbd57e13359ffdd9660128711aaa72
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e4e3b0fc0dfbd57e13359ffdd9660128711aaa72

Author: Chris Forbes 
Date:   Tue Sep 23 21:27:24 2014 +1200

i965: Fix typo in comment

Signed-off-by: Chris Forbes 

---

 src/mesa/drivers/dri/i965/brw_wm_surface_state.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 4a3111a..23ec821 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -389,7 +389,7 @@ brw_create_constant_surface(struct brw_context *brw,
  * Set up a binding table entry for use by stream output logic (transform
  * feedback).
  *
- * buffer_size_minus_1 must me less than BRW_MAX_NUM_BUFFER_ENTRIES.
+ * buffer_size_minus_1 must be less than BRW_MAX_NUM_BUFFER_ENTRIES.
  */
 void
 brw_update_sol_surface(struct brw_context *brw,

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Mesa (master): i965: Fix spelling of GEN7_SAMPLER_EWA_ANISOTROPIC_ALGORITHM

[Chris Forbes]

Module: Mesa
Branch: master
Commit: d8c5c4f3e480a6edfd9b4b83c35cee07c70dd421
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8c5c4f3e480a6edfd9b4b83c35cee07c70dd421

Author: Chris Forbes 
Date:   Sun Sep 28 17:07:37 2014 +1300

i965: Fix spelling of GEN7_SAMPLER_EWA_ANISOTROPIC_ALGORITHM

Signed-off-by: Chris Forbes 

---

 src/mesa/drivers/dri/i965/brw_defines.h   |2 +-
 src/mesa/drivers/dri/i965/brw_sampler_state.c |2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 2faebe8..94d146c 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -640,7 +640,7 @@
 
 #define GEN7_SAMPLER_LOD_BIAS_MASK  INTEL_MASK(13, 1)
 #define GEN7_SAMPLER_LOD_BIAS_SHIFT 1
-#define GEN7_SAMPLER_EWA_ANISOTROPIC_ALGORIHTM  (1 << 0)
+#define GEN7_SAMPLER_EWA_ANISOTROPIC_ALGORITHM  (1 << 0)
 
 /* SAMPLER_STATE DW1 */
 #define GEN4_SAMPLER_MIN_LOD_MASK   INTEL_MASK(31, 22)
diff --git a/src/mesa/drivers/dri/i965/brw_sampler_state.c 
b/src/mesa/drivers/dri/i965/brw_sampler_state.c
index 544aa57..5855af6 100644
--- a/src/mesa/drivers/dri/i965/brw_sampler_state.c
+++ b/src/mesa/drivers/dri/i965/brw_sampler_state.c
@@ -115,7 +115,7 @@ brw_emit_sampler_state(struct brw_context *brw,
   ss[0] |= SET_FIELD(lod_bias & 0x1fff, GEN7_SAMPLER_LOD_BIAS);
 
   if (min_filter == BRW_MAPFILTER_ANISOTROPIC)
- ss[0] |= GEN7_SAMPLER_EWA_ANISOTROPIC_ALGORIHTM;
+ ss[0] |= GEN7_SAMPLER_EWA_ANISOTROPIC_ALGORITHM;
 
   ss[1] = SET_FIELD(min_lod, GEN7_SAMPLER_MIN_LOD) |
   SET_FIELD(max_lod, GEN7_SAMPLER_MAX_LOD) |

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Mesa (master): i965/gen6: Enable GL 3.3 and GLSL 3.30

[Chris Forbes]

Module: Mesa
Branch: master
Commit: c4ed6c730f5fab03e19bf009d1ed85da3fd966db
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c4ed6c730f5fab03e19bf009d1ed85da3fd966db

Author: Chris Forbes 
Date:   Sat Sep 20 10:39:37 2014 +1200

i965/gen6: Enable GL 3.3 and GLSL 3.30

Tested on my snb-gt2:

4 tests skip->pass in spec/EXT_texture_array
51 tests skip->pass in spec.glsl-3.30
4 tests skip->pass in spec/!OpenGL 3.3
No regressions; no skip->fail changes.

Signed-off-by: Chris Forbes 
Reviewed-by: Jordan Justen 

---

 src/mesa/drivers/dri/i965/intel_extensions.c |4 +---
 src/mesa/drivers/dri/i965/intel_screen.c |7 +--
 2 files changed, 2 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
b/src/mesa/drivers/dri/i965/intel_extensions.c
index b7c64c6..4e6627e 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -243,10 +243,8 @@ intelInitExtensions(struct gl_context *ctx)
ctx->Extensions.OES_standard_derivatives = true;
ctx->Extensions.OES_EGL_image_external = true;
 
-   if (brw->gen >= 7)
+   if (brw->gen >= 6)
   ctx->Const.GLSLVersion = 330;
-   else if (brw->gen >= 6)
-  ctx->Const.GLSLVersion = 150;
else
   ctx->Const.GLSLVersion = 120;
_mesa_override_glsl_version(&ctx->Const);
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c 
b/src/mesa/drivers/dri/i965/intel_screen.c
index 8070e97..41964ec 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -1269,13 +1269,8 @@ set_max_gl_versions(struct intel_screen *screen)
switch (screen->devinfo->gen) {
case 8:
case 7:
-  psp->max_gl_core_version = 33;
-  psp->max_gl_compat_version = 30;
-  psp->max_gl_es1_version = 11;
-  psp->max_gl_es2_version = 30;
-  break;
case 6:
-  psp->max_gl_core_version = 32;
+  psp->max_gl_core_version = 33;
   psp->max_gl_compat_version = 30;
   psp->max_gl_es1_version = 11;
   psp->max_gl_es2_version = 30;

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Mesa (master): i965/vec4: slightly improve insn dumping with no srcs

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 667f758788f0796d9be16f0f361022d447f622f5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=667f758788f0796d9be16f0f361022d447f622f5

Author: Chris Forbes 
Date:   Tue Sep  9 19:55:28 2014 +1200

i965/vec4: slightly improve insn dumping with no srcs

Previously, we would get a trailing ', ' which looked strange.

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_vec4.cpp |5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 0f13c0d..9102be2 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -1337,7 +1337,10 @@ vec4_visitor::dump_instruction(backend_instruction 
*be_inst, FILE *file)
   if (inst->dst.writemask & 8)
  fprintf(file, "w");
}
-   fprintf(file, ":%s, ", brw_reg_type_letters(inst->dst.type));
+   fprintf(file, ":%s", brw_reg_type_letters(inst->dst.type));
+
+   if (inst->src[0].file != BAD_FILE)
+  fprintf(file, ", ");
 
for (int i = 0; i < 3 && inst->src[i].file != BAD_FILE; i++) {
   if (inst->src[i].negate)

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Mesa (master): glsl: fix error message for redeclaring gl_PerVertex as output

[Chris Forbes]

Module: Mesa
Branch: master
Commit: b84c02f9cdcc23ecff7f21df28a827f71be9e5fd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b84c02f9cdcc23ecff7f21df28a827f71be9e5fd

Author: Chris Forbes 
Date:   Tue Sep  9 19:55:29 2014 +1200

glsl: fix error message for redeclaring gl_PerVertex as output

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/glsl/ast_to_hir.cpp |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/glsl/ast_to_hir.cpp b/src/glsl/ast_to_hir.cpp
index 3b38dcf..5ec1614 100644
--- a/src/glsl/ast_to_hir.cpp
+++ b/src/glsl/ast_to_hir.cpp
@@ -5462,7 +5462,7 @@ ast_interface_block::hir(exec_list *instructions,
  }
  if (this->instance_name != NULL) {
 _mesa_glsl_error(&loc, state,
- "gl_PerVertex input may not be redeclared with "
+ "gl_PerVertex output may not be redeclared with "
  "an instance name");
  }
  break;

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Mesa (master): glsl: Remove bogus "OUPTUT" token

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 38a3490368f6f365890de11a5f2d983b40fbd243
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=38a3490368f6f365890de11a5f2d983b40fbd243

Author: Chris Forbes 
Date:   Fri Aug 22 20:59:42 2014 +1200

glsl: Remove bogus "OUPTUT" token

This is never used. There is another token "OUTPUT" which the lexer can
generate, though. This has been around since the dawn of time; is most
likely a typo.

Signed-off-by: Chris Forbes 

---

 src/glsl/glsl_parser.yy |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/glsl/glsl_parser.yy b/src/glsl/glsl_parser.yy
index 4c87163..2f30b85 100644
--- a/src/glsl/glsl_parser.yy
+++ b/src/glsl/glsl_parser.yy
@@ -179,7 +179,7 @@ static bool match_layout_qualifier(const char *s1, const 
char *s2,
 */
 %token ASM CLASS UNION ENUM TYPEDEF TEMPLATE THIS PACKED_TOK GOTO
 %token INLINE_TOK NOINLINE PUBLIC_TOK STATIC EXTERN EXTERNAL
-%token LONG_TOK SHORT_TOK DOUBLE_TOK HALF FIXED_TOK UNSIGNED INPUT_TOK OUPTUT
+%token LONG_TOK SHORT_TOK DOUBLE_TOK HALF FIXED_TOK UNSIGNED INPUT_TOK
 %token HVEC2 HVEC3 HVEC4 DVEC2 DVEC3 DVEC4 FVEC2 FVEC3 FVEC4
 %token SAMPLER3DRECT
 %token SIZEOF CAST NAMESPACE USING

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Mesa (master): docs: Update who is working on tessellation

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 01887593a424824426eda75ff90b5e2a49876e86
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=01887593a424824426eda75ff90b5e2a49876e86

Author: Chris Forbes 
Date:   Tue Aug 26 07:51:11 2014 +1200

docs: Update who is working on tessellation

Signed-off-by: Chris Forbes 

---

 docs/GL3.txt |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index 76412c3..0d884c6 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -110,7 +110,7 @@ GL 4.0, GLSL 4.00:
   GL_ARB_gpu_shader_fp64   started (Dave)
   GL_ARB_sample_shadingDONE (i965, nv50, nvc0, 
radeonsi)
   GL_ARB_shader_subroutine not started
-  GL_ARB_tessellation_shader   started (Fabian)
+  GL_ARB_tessellation_shader   started (Chris, Ilia)
   GL_ARB_texture_buffer_object_rgb32   DONE (i965, nvc0, r600, 
radeonsi, softpipe)
   GL_ARB_texture_cube_map_arrayDONE (i965, nv50, nvc0, 
r600, radeonsi, softpipe)
   GL_ARB_texture_gatherDONE (i965, nv50, nvc0, 
r600, radeonsi)

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Mesa (master): docs: Mark off ARB_conditional_render_inverted for i965

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 1c4f141a542eb21f76df021464c3a9237ff0f376
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c4f141a542eb21f76df021464c3a9237ff0f376

Author: Chris Forbes 
Date:   Tue Aug 19 23:33:24 2014 +1200

docs: Mark off ARB_conditional_render_inverted for i965

Signed-off-by: Chris Forbes 
Reviewed-by: Ilia Mirkin 

---

 docs/GL3.txt|2 +-
 docs/relnotes/10.3.html |2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index 5549b30..76412c3 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -186,7 +186,7 @@ GL 4.5, GLSL 4.50:
 
   GL_ARB_ES3_1_compatibility   not started
   GL_ARB_clip_control  not started
-  GL_ARB_conditional_render_inverted   DONE (nvc0, softpipe, 
llvmpipe)
+  GL_ARB_conditional_render_inverted   DONE (i965, nvc0, 
softpipe, llvmpipe)
   GL_ARB_cull_distance not started
   GL_ARB_derivative_controlDONE (i965, nv50, nvc0, 
r600)
   GL_ARB_direct_state_access   not started
diff --git a/docs/relnotes/10.3.html b/docs/relnotes/10.3.html
index 5f4f8fd..fa4ea23 100644
--- a/docs/relnotes/10.3.html
+++ b/docs/relnotes/10.3.html
@@ -47,7 +47,7 @@ Note: some of the new features are only available with 
certain drivers.
 GL_ARB_ES3_compatibility on nv50, nvc0, r600, radeonsi, softpipe, 
llvmpipe
 GL_ARB_clear_texture on i965
 GL_ARB_compressed_texture_pixel_storage on all drivers
-GL_ARB_conditional_render_inverted on nvc0, softpipe, llvmpipe
+GL_ARB_conditional_render_inverted on i965, nvc0, softpipe, llvmpipe
 GL_ARB_derivative_control on i965, nv50, nvc0, r600
 GL_ARB_draw_indirect on nvc0, radeonsi
 GL_ARB_explicit_uniform_location (all drivers that support GLSL)

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Mesa (master): mesa: Add support for inverted s/w conditional rendering

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 3f8ad326276d14f3e38b4b5a58547227911d1ee7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f8ad326276d14f3e38b4b5a58547227911d1ee7

Author: Chris Forbes 
Date:   Tue Aug 19 23:23:08 2014 +1200

mesa: Add support for inverted s/w conditional rendering

Signed-off-by: Chris Forbes 
Reviewed-by: Ilia Mirkin 

---

 src/mesa/main/condrender.c |   13 +
 1 file changed, 13 insertions(+)

diff --git a/src/mesa/main/condrender.c b/src/mesa/main/condrender.c
index 54cd423..75f9d74 100644
--- a/src/mesa/main/condrender.c
+++ b/src/mesa/main/condrender.c
@@ -162,12 +162,25 @@ _mesa_check_conditional_render(struct gl_context *ctx)
  ctx->Driver.WaitQuery(ctx, q);
   }
   return q->Result > 0;
+   case GL_QUERY_BY_REGION_WAIT_INVERTED:
+  /* fall-through */
+   case GL_QUERY_WAIT_INVERTED:
+  if (!q->Ready) {
+ ctx->Driver.WaitQuery(ctx, q);
+  }
+  return q->Result == 0;
case GL_QUERY_BY_REGION_NO_WAIT:
   /* fall-through */
case GL_QUERY_NO_WAIT:
   if (!q->Ready)
  ctx->Driver.CheckQuery(ctx, q);
   return q->Ready ? (q->Result > 0) : GL_TRUE;
+   case GL_QUERY_BY_REGION_NO_WAIT_INVERTED:
+  /* fall-through */
+   case GL_QUERY_NO_WAIT_INVERTED:
+  if (!q->Ready)
+ ctx->Driver.CheckQuery(ctx, q);
+  return q->Ready ? (q->Result == 0) : GL_TRUE;
default:
   _mesa_problem(ctx, "Bad cond render mode %s in "
 " _mesa_check_conditional_render()",

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Mesa (master): i965: Enable ARB_conditional_render_inverted on Gen6+.

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 06ca96daadf88713a74c58761cb14edc5867e9b4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=06ca96daadf88713a74c58761cb14edc5867e9b4

Author: Chris Forbes 
Date:   Tue Aug 19 23:30:50 2014 +1200

i965: Enable ARB_conditional_render_inverted on Gen6+.

The extension requires GL 3.0, so enable on just the generations
exposing that.

Signed-off-by: Chris Forbes 
Reviewed-by: Ilia Mirkin 

---

 src/mesa/drivers/dri/i965/intel_extensions.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
b/src/mesa/drivers/dri/i965/intel_extensions.c
index 1d18c83..046d2a1 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -272,6 +272,7 @@ intelInitExtensions(struct gl_context *ctx)
   ctx->Extensions.ARB_texture_multisample = true;
   ctx->Extensions.ARB_sample_shading = true;
   ctx->Extensions.ARB_texture_gather = true;
+  ctx->Extensions.ARB_conditional_render_inverted = true;
 
   /* Test if the kernel has the ioctl. */
   if (drm_intel_reg_read(brw->bufmgr, TIMESTAMP, &dummy) == 0)

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Mesa (master): docs: Update relnotes for ARB_gpu_shader5

[Chris Forbes]

Module: Mesa
Branch: master
Commit: f1370fed2cfea49c40c259d40d1a26402fc5dd56
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f1370fed2cfea49c40c259d40d1a26402fc5dd56

Author: Chris Forbes 
Date:   Sun Aug 10 16:22:35 2014 +1200

docs: Update relnotes for ARB_gpu_shader5

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 

---

 docs/relnotes/10.3.html |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/relnotes/10.3.html b/docs/relnotes/10.3.html
index cb65685..0f22d70 100644
--- a/docs/relnotes/10.3.html
+++ b/docs/relnotes/10.3.html
@@ -51,7 +51,7 @@ Note: some of the new features are only available with 
certain drivers.
 GL_ARB_draw_indirect on nvc0, radeonsi
 GL_ARB_explicit_uniform_location (all drivers that support GLSL)
 GL_ARB_fragment_layer_viewport on nv50, nvc0, llvmpipe, r600
-GL_ARB_gpu_shader5 on nvc0
+GL_ARB_gpu_shader5 on i965/gen7, nvc0
 GL_ARB_multi_draw_indirect on nvc0, radeonsi
 GL_ARB_sample_shading on radeonsi
 GL_ARB_seamless_cubemap_per_texture on i965, llvmpipe, nvc0, r600, 
radeonsi, softpipe

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Mesa (master): i965: Enable ARB_gpu_shader5 on Gen7

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 4a3667993e8c3bace135791efbe2163a82bbfc56
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a3667993e8c3bace135791efbe2163a82bbfc56

Author: Chris Forbes 
Date:   Sun Aug 10 14:36:25 2014 +1200

i965: Enable ARB_gpu_shader5 on Gen7

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 

---

 src/mesa/drivers/dri/i965/intel_extensions.c |3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
b/src/mesa/drivers/dri/i965/intel_extensions.c
index c672044..1d18c83 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -329,4 +329,7 @@ intelInitExtensions(struct gl_context *ctx)
 
if (brw->gen >= 7)
   ctx->Extensions.ARB_shader_atomic_counters = true;
+
+   if (brw->gen == 7)
+  ctx->Extensions.ARB_gpu_shader5 = true;
 }

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Mesa (master): docs: Mark off ARB_gpu_shader5 for i965

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 139f127aac335e6c1713f06d76db96f898729ce4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=139f127aac335e6c1713f06d76db96f898729ce4

Author: Chris Forbes 
Date:   Sun Aug 10 16:08:36 2014 +1200

docs: Mark off ARB_gpu_shader5 for i965

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 

---

 docs/GL3.txt |   18 +-
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index 0666fb9..12b8f62 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -94,18 +94,18 @@ GL 4.0, GLSL 4.00:
 
   GL_ARB_draw_buffers_blendDONE (i965, nv50, nvc0, 
r600, radeonsi, softpipe)
   GL_ARB_draw_indirect DONE (i965, nvc0, 
radeonsi, softpipe, llvmpipe)
-  GL_ARB_gpu_shader5   DONE (nvc0)
+  GL_ARB_gpu_shader5   DONE (i965, nvc0)
   - 'precise' qualifierDONE
   - Dynamically uniform sampler array indices  DONE ()
-  - Dynamically uniform UBO array indices  DONE (i965)
+  - Dynamically uniform UBO array indices  DONE ()
   - Implicit signed -> unsigned conversionsDONE
-  - Fused multiply-add DONE (i965)
-  - Packing/bitfield/conversion functions  DONE (i965, r600)
-  - Enhanced textureGather DONE (i965, r600, 
radeonsi)
-  - Geometry shader instancing DONE (i965)
-  - Geometry shader multiple streams   DONE (i965)
-  - Enhanced per-sample shadingDONE (i965, r600)
-  - Interpolation functionsDONE (i965)
+  - Fused multiply-add DONE ()
+  - Packing/bitfield/conversion functions  DONE (r600)
+  - Enhanced textureGather DONE (r600, radeonsi)
+  - Geometry shader instancing DONE ()
+  - Geometry shader multiple streams   DONE ()
+  - Enhanced per-sample shadingDONE (r600)
+  - Interpolation functionsDONE ()
   - New overload resolution rules  DONE
   GL_ARB_gpu_shader_fp64   started (Dave)
   GL_ARB_sample_shadingDONE (i965, nv50, nvc0, 
radeonsi)

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Mesa (master): i965/fs: Use brw_adjust_sampler_state_pointer in fs generator too

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 2b1204aa96cb2d1aa66cecde810b9224d457a580
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b1204aa96cb2d1aa66cecde810b9224d457a580

Author: Chris Forbes 
Date:   Sun Aug 10 11:54:47 2014 +1200

i965/fs: Use brw_adjust_sampler_state_pointer in fs generator too

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_fs_generator.cpp |   17 +
 1 file changed, 1 insertion(+), 16 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index d905567..bc1e7bf 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -573,22 +573,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg 
dst, struct brw_reg src
brw_imm_ud(inst->texture_offset));
  }
 
- if (sampler >= 16) {
-/* The "Sampler Index" field can only store values between 0 and 
15.
- * However, we can add an offset to the "Sampler State Pointer"
- * field, effectively selecting a different set of 16 samplers.
- *
- * The "Sampler State Pointer" needs to be aligned to a 32-byte
- * offset, and each sampler state is only 16-bytes, so we can't
- * exclusively use the offset - we have to use both.
- */
-assert(brw->gen >= 8 || brw->is_haswell);
-const int sampler_state_size = 16; /* 16 bytes */
-brw_ADD(p,
-get_element_ud(header_reg, 3),
-get_element_ud(brw_vec8_grf(0, 0), 3),
-brw_imm_ud(16 * (sampler / 16) * sampler_state_size));
- }
+ brw_adjust_sampler_state_pointer(p, header_reg, sampler_index, dst);
  brw_pop_insn_state(p);
   }
}

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Mesa (master): i965/fs: Refactor generate_tex in prep for nonconst sampler indexing

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 4ba5171f307873c7f5d6ac07f86bfbc26a82e00e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4ba5171f307873c7f5d6ac07f86bfbc26a82e00e

Author: Chris Forbes 
Date:   Sun Aug 10 11:58:06 2014 +1200

i965/fs: Refactor generate_tex in prep for nonconst sampler indexing

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_fs_generator.cpp |   47 +---
 1 file changed, 25 insertions(+), 22 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index bc1e7bf..c7c8c5f 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -538,11 +538,8 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg 
dst, struct brw_reg src
   src.nr++;
}
 
-   assert(sampler_index.file == BRW_IMMEDIATE_VALUE);
assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
 
-   uint32_t sampler = sampler_index.dw1.ud;
-
/* Load the message header if present.  If there's a texture offset,
 * we need to set it up explicitly and load the offset bitfield.
 * Otherwise, we can use an implied move from g0 to the first message reg.
@@ -578,25 +575,31 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg 
dst, struct brw_reg src
   }
}
 
-   uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
-  inst->opcode == SHADER_OPCODE_TG4_OFFSET)
-  ? prog_data->base.binding_table.gather_texture_start
-  : prog_data->base.binding_table.texture_start) + sampler;
-
-   brw_SAMPLE(p,
- retype(dst, BRW_REGISTER_TYPE_UW),
- inst->base_mrf,
- src,
-  surface_index,
- sampler % 16,
- msg_type,
- rlen,
- inst->mlen,
- inst->header_present,
- simd_mode,
- return_format);
-
-   brw_mark_surface_used(&prog_data->base, surface_index);
+   uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
+ inst->opcode == SHADER_OPCODE_TG4_OFFSET)
+ ? prog_data->base.binding_table.gather_texture_start
+ : prog_data->base.binding_table.texture_start;
+
+   if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
+  uint32_t sampler = sampler_index.dw1.ud;
+
+  brw_SAMPLE(p,
+ retype(dst, BRW_REGISTER_TYPE_UW),
+ inst->base_mrf,
+ src,
+ sampler + base_binding_table_index,
+ sampler % 16,
+ msg_type,
+ rlen,
+ inst->mlen,
+ inst->header_present,
+ simd_mode,
+ return_format);
+
+  brw_mark_surface_used(&prog_data->base, sampler + 
base_binding_table_index);
+   } else {
+  /* XXX: Non-const sampler index */
+   }
 }
 
 

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Mesa (master): i965: Extract helper function for surface state pointer adjustment

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 8ce3fa8e91e96adac9ba909876d3b3066bdcd723
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ce3fa8e91e96adac9ba909876d3b3066bdcd723

Author: Chris Forbes 
Date:   Sun Aug 10 11:49:31 2014 +1200

i965: Extract helper function for surface state pointer adjustment

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_eu.h   |5 
 src/mesa/drivers/dri/i965/brw_eu_emit.c  |   35 ++
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp |   17 +--
 3 files changed, 41 insertions(+), 16 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_eu.h 
b/src/mesa/drivers/dri/i965/brw_eu.h
index 5122e63..e6c26e3 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -281,6 +281,11 @@ void brw_SAMPLE(struct brw_compile *p,
unsigned simd_mode,
unsigned return_format);
 
+void brw_adjust_sampler_state_pointer(struct brw_compile *p,
+  struct brw_reg header,
+  struct brw_reg sampler_index,
+  struct brw_reg scratch);
+
 void gen4_math(struct brw_compile *p,
   struct brw_reg dest,
   unsigned function,
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index c18ac3a..3626bf4 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -2355,6 +2355,41 @@ void brw_SAMPLE(struct brw_compile *p,
return_format);
 }
 
+/* Adjust the message header's sampler state pointer to
+ * select the correct group of 16 samplers.
+ */
+void brw_adjust_sampler_state_pointer(struct brw_compile *p,
+  struct brw_reg header,
+  struct brw_reg sampler_index,
+  struct brw_reg scratch)
+{
+   /* The "Sampler Index" field can only store values between 0 and 15.
+* However, we can add an offset to the "Sampler State Pointer"
+* field, effectively selecting a different set of 16 samplers.
+*
+* The "Sampler State Pointer" needs to be aligned to a 32-byte
+* offset, and each sampler state is only 16-bytes, so we can't
+* exclusively use the offset - we have to use both.
+*/
+
+   struct brw_context *brw = p->brw;
+
+   if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
+  const int sampler_state_size = 16; /* 16 bytes */
+  uint32_t sampler = sampler_index.dw1.ud;
+
+  if (sampler >= 16) {
+ assert(brw->is_haswell || brw->gen >= 8);
+ brw_ADD(p,
+ get_element_ud(header, 3),
+ get_element_ud(brw_vec8_grf(0, 0), 3),
+ brw_imm_ud(16 * (sampler / 16) * sampler_state_size));
+  }
+   } else {
+  /* XXX: Non-const sampler array indexing case */
+   }
+}
+
 /* All these variables are pretty confusing - we might be better off
  * using bitmasks and macros for this, in the old style.  Or perhaps
  * just having the caller instantiate the fields in dword3 itself.
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index f5e459a..01c543a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -344,22 +344,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
 brw_imm_ud(inst->texture_offset));
  }
 
- if (sampler >= 16) {
-/* The "Sampler Index" field can only store values between 0 and 
15.
- * However, we can add an offset to the "Sampler State Pointer"
- * field, effectively selecting a different set of 16 samplers.
- *
- * The "Sampler State Pointer" needs to be aligned to a 32-byte
- * offset, and each sampler state is only 16-bytes, so we can't
- * exclusively use the offset - we have to use both.
- */
-const int sampler_state_size = 16; /* 16 bytes */
-assert(brw->gen >= 8 || brw->is_haswell);
-brw_ADD(p,
-get_element_ud(header, 3),
-get_element_ud(brw_vec8_grf(0, 0), 3),
-brw_imm_ud(16 * (sampler / 16) * sampler_state_size));
- }
+ brw_adjust_sampler_state_pointer(p, header, sampler_index, dst);
  brw_pop_insn_state(p);
   }
}

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Mesa (master): i965/vec4: Add support for non-const sampler indices in generator

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 301b71557b2f24f7f59402f634cd531d0adb3349
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=301b71557b2f24f7f59402f634cd531d0adb3349

Author: Chris Forbes 
Date:   Sun Aug 10 11:42:08 2014 +1200

i965/vec4: Add support for non-const sampler indices in generator

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp |   52 +-
 1 file changed, 51 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 2bf72c1..1b1e647 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -383,7 +383,57 @@ vec4_generator::generate_tex(vec4_instruction *inst,
 
   brw_mark_surface_used(&prog_data->base, sampler + 
base_binding_table_index);
} else {
-  /* XXX: Non-constant sampler index. */
+  /* Non-constant sampler index. */
+  /* Note: this clobbers `dst` as a temporary before emitting the send */
+
+  struct brw_reg addr = vec1(retype(brw_address_reg(0), 
BRW_REGISTER_TYPE_UD));
+  struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
+
+  struct brw_reg sampler_reg = vec1(retype(sampler_index, 
BRW_REGISTER_TYPE_UD));
+
+  brw_push_insn_state(p);
+  brw_set_default_mask_control(p, BRW_MASK_DISABLE);
+  brw_set_default_access_mode(p, BRW_ALIGN_1);
+
+  /* Some care required: `sampler` and `temp` may alias:
+   *addr = sampler & 0xff
+   *temp = (sampler << 8) & 0xf00
+   *addr = addr | temp
+   */
+  brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
+  brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
+  brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
+  brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
+  brw_OR(p, addr, addr, temp);
+
+  /* a0.0 |=  */
+  brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
+  brw_set_sampler_message(p, insn_or,
+  0 /* surface */,
+  0 /* sampler */,
+  msg_type,
+  1 /* rlen */,
+  inst->mlen /* mlen */,
+  inst->header_present /* header */,
+  BRW_SAMPLER_SIMD_MODE_SIMD4X2,
+  return_format);
+  brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
+  brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
+  brw_set_src0(p, insn_or, addr);
+  brw_set_dest(p, insn_or, addr);
+
+
+  /* dst = send(offset, a0.0) */
+  brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
+  brw_set_dest(p, insn_send, dst);
+  brw_set_src0(p, insn_send, src);
+  brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
+
+  brw_pop_insn_state(p);
+
+  /* visitor knows more than we do about the surface limit required,
+   * so has already done marking.
+   */
}
 }
 

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Mesa (master): i965: Generalize sampler state pointer mangling for non-const

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 86dc34a0b0d967e9c8611bc29178fdb1de22c724
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=86dc34a0b0d967e9c8611bc29178fdb1de22c724

Author: Chris Forbes 
Date:   Sun Aug 10 11:39:44 2014 +1200

i965: Generalize sampler state pointer mangling for non-const

For now, assume that the addressed sampler can be in any of the
16-sampler banks. If we preserved range information this far, we
could avoid emitting these instructions if the sampler were known
to be contained within one bank.

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_eu_emit.c |   14 +-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 3626bf4..39f94e9 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -2386,7 +2386,19 @@ void brw_adjust_sampler_state_pointer(struct brw_compile 
*p,
  brw_imm_ud(16 * (sampler / 16) * sampler_state_size));
   }
} else {
-  /* XXX: Non-const sampler array indexing case */
+  /* Non-const sampler array indexing case */
+  if (brw->gen < 8 && !brw->is_haswell) {
+ return;
+  }
+
+  struct brw_reg temp = vec1(retype(scratch, BRW_REGISTER_TYPE_UD));
+
+  brw_AND(p, temp, sampler_index, brw_imm_ud(0x0f0));
+  brw_SHL(p, temp, temp, brw_imm_ud(4));
+  brw_ADD(p,
+  get_element_ud(header, 3),
+  get_element_ud(brw_vec8_grf(0, 0), 3),
+  temp);
}
 }
 

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Mesa (master): i965/vec4: Add support for nonconst sampler indexing in VS visitor

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 2cd6169e9298e75e4f71c358471b80eb8bf19f11
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2cd6169e9298e75e4f71c358471b80eb8bf19f11

Author: Chris Forbes 
Date:   Sat Aug  9 22:08:11 2014 +1200

i965/vec4: Add support for nonconst sampler indexing in VS visitor

V2: Set force_writemask_all on ADD; this *is* necessary in the VS case
too.

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_vec4.h   |2 +-
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |   54 +---
 2 files changed, 50 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 67132c0..c59d24f 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -526,7 +526,7 @@ public:
void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 
uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
-   src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, uint32_t 
sampler);
+   src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, src_reg sampler);
void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
void swizzle_result(ir_texture *ir, src_reg orig_val, uint32_t sampler);
 
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 10d96c7..f22d38d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -2305,7 +2305,7 @@ vec4_visitor::visit(ir_call *ir)
 }
 
 src_reg
-vec4_visitor::emit_mcs_fetch(ir_texture *ir, src_reg coordinate, uint32_t 
sampler)
+vec4_visitor::emit_mcs_fetch(ir_texture *ir, src_reg coordinate, src_reg 
sampler)
 {
vec4_instruction *inst = new(mem_ctx) vec4_instruction(this, 
SHADER_OPCODE_TXF_MCS);
inst->base_mrf = 2;
@@ -2313,7 +2313,7 @@ vec4_visitor::emit_mcs_fetch(ir_texture *ir, src_reg 
coordinate, uint32_t sample
inst->dst = dst_reg(this, glsl_type::uvec4_type);
inst->dst.writemask = WRITEMASK_XYZW;
 
-   inst->src[1] = src_reg(sampler);
+   inst->src[1] = sampler;
 
/* parameters are: u, v, r, lod; lod will always be zero due to api 
restrictions */
int param_base = inst->base_mrf;
@@ -2330,12 +2330,56 @@ vec4_visitor::emit_mcs_fetch(ir_texture *ir, src_reg 
coordinate, uint32_t sample
return src_reg(inst->dst);
 }
 
+static bool
+is_high_sampler(struct brw_context *brw, src_reg sampler)
+{
+   if (brw->gen < 8 && !brw->is_haswell)
+  return false;
+
+   return sampler.file != IMM || sampler.fixed_hw_reg.dw1.ud >= 16;
+}
+
 void
 vec4_visitor::visit(ir_texture *ir)
 {
uint32_t sampler =
   _mesa_get_sampler_uniform_value(ir->sampler, shader_prog, prog);
 
+   ir_rvalue *nonconst_sampler_index =
+  _mesa_get_sampler_array_nonconst_index(ir->sampler);
+
+   /* Handle non-constant sampler array indexing */
+   src_reg sampler_reg;
+   if (nonconst_sampler_index) {
+  /* The highest sampler which may be used by this operation is
+   * the last element of the array. Mark it here, because the generator
+   * doesn't have enough information to determine the bound.
+   */
+  uint32_t array_size = ir->sampler->as_dereference_array()
+ ->array->type->array_size();
+
+  uint32_t max_used = sampler + array_size - 1;
+  if (ir->op == ir_tg4 && brw->gen < 8) {
+ max_used += prog_data->base.binding_table.gather_texture_start;
+  } else {
+ max_used += prog_data->base.binding_table.texture_start;
+  }
+
+  brw_mark_surface_used(&prog_data->base, max_used);
+
+  /* Emit code to evaluate the actual indexing expression */
+  nonconst_sampler_index->accept(this);
+  dst_reg temp(this, glsl_type::uint_type);
+  emit(ADD(temp, this->result, src_reg(sampler)))
+ ->force_writemask_all = true;
+  sampler_reg = src_reg(temp);
+   } else {
+  /* Single sampler, or constant array index; the indexing expression
+   * is just an immediate.
+   */
+  sampler_reg = src_reg(sampler);
+   }
+
/* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
 * emitting anything other than setting up the constant result.
 */
@@ -2403,7 +2447,7 @@ vec4_visitor::visit(ir_texture *ir)
   sample_index_type = ir->lod_info.sample_index->type;
 
   if (brw->gen >= 7 && key->tex.compressed_multisample_layout_mask & 
(1<header_present =
   brw->gen < 5 || inst->texture_offset != 0 || ir->op == ir_tg4 ||
-  sampler >= 16;
+  is_high_sampler(brw, sampler_reg);
inst->base_mrf = 2;
inst->mlen = inst->header_present + 1; /* always at least one */
inst->dst = dst_reg(this, ir->type);
inst->dst.writemask = WRITEMASK_XYZW;
inst->

Mesa (master): i965/fs: Add support for non-const sampler indices in generator

[Chris Forbes]

Module: Mesa
Branch: master
Commit: fbfcd671a1c74eebc00c56f609a8792fedb0a45d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fbfcd671a1c74eebc00c56f609a8792fedb0a45d

Author: Chris Forbes 
Date:   Sun Aug 10 12:02:22 2014 +1200

i965/fs: Add support for non-const sampler indices in generator

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_fs_generator.cpp |   52 +++-
 1 file changed, 51 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index c7c8c5f..1cf5a88 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -598,7 +598,57 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg 
dst, struct brw_reg src
 
   brw_mark_surface_used(&prog_data->base, sampler + 
base_binding_table_index);
} else {
-  /* XXX: Non-const sampler index */
+  /* Non-const sampler index */
+  /* Note: this clobbers `dst` as a temporary before emitting the send */
+
+  struct brw_reg addr = vec1(retype(brw_address_reg(0), 
BRW_REGISTER_TYPE_UD));
+  struct brw_reg temp = vec1(retype(dst, BRW_REGISTER_TYPE_UD));
+
+  struct brw_reg sampler_reg = vec1(retype(sampler_index, 
BRW_REGISTER_TYPE_UD));
+
+  brw_push_insn_state(p);
+  brw_set_default_mask_control(p, BRW_MASK_DISABLE);
+  brw_set_default_access_mode(p, BRW_ALIGN_1);
+
+  /* Some care required: `sampler` and `temp` may alias:
+   *addr = sampler & 0xff
+   *temp = (sampler << 8) & 0xf00
+   *addr = addr | temp
+   */
+  brw_ADD(p, addr, sampler_reg, brw_imm_ud(base_binding_table_index));
+  brw_SHL(p, temp, sampler_reg, brw_imm_ud(8u));
+  brw_AND(p, temp, temp, brw_imm_ud(0x0f00));
+  brw_AND(p, addr, addr, brw_imm_ud(0x0ff));
+  brw_OR(p, addr, addr, temp);
+
+  /* a0.0 |=  */
+  brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
+  brw_set_sampler_message(p, insn_or,
+  0 /* surface */,
+  0 /* sampler */,
+  msg_type,
+  rlen,
+  inst->mlen /* mlen */,
+  inst->header_present /* header */,
+  simd_mode,
+  return_format);
+  brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
+  brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
+  brw_set_src0(p, insn_or, addr);
+  brw_set_dest(p, insn_or, addr);
+
+
+  /* dst = send(offset, a0.0) */
+  brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
+  brw_set_dest(p, insn_send, dst);
+  brw_set_src0(p, insn_send, src);
+  brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
+
+  brw_pop_insn_state(p);
+
+  /* visitor knows more than we do about the surface limit required,
+   * so has already done marking.
+   */
}
 }
 

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Mesa (master): i965/vec4: Refactor generate_tex in prep for non-const samplers

[Chris Forbes]

Module: Mesa
Branch: master
Commit: f7146d1a946003bfbb6bc9fc6462a4c827cd93ba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f7146d1a946003bfbb6bc9fc6462a4c827cd93ba

Author: Chris Forbes 
Date:   Sun Aug 10 11:50:16 2014 +1200

i965/vec4: Refactor generate_tex in prep for non-const samplers

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp |   47 --
 1 file changed, 25 insertions(+), 22 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 01c543a..2bf72c1 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -314,11 +314,8 @@ vec4_generator::generate_tex(vec4_instruction *inst,
 
assert(msg_type != -1);
 
-   assert(sampler_index.file == BRW_IMMEDIATE_VALUE);
assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
 
-   uint32_t sampler = sampler_index.dw1.ud;
-
/* Load the message header if present.  If there's a texture offset, we need
 * to set it up explicitly and load the offset bitfield.  Otherwise, we can
 * use an implied move from g0 to the first message register.
@@ -363,25 +360,31 @@ vec4_generator::generate_tex(vec4_instruction *inst,
   break;
}
 
-   uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
-  inst->opcode == SHADER_OPCODE_TG4_OFFSET)
-  ? prog_data->base.binding_table.gather_texture_start
-  : prog_data->base.binding_table.texture_start) + sampler;
-
-   brw_SAMPLE(p,
- dst,
- inst->base_mrf,
- src,
-  surface_index,
- sampler % 16,
- msg_type,
- 1, /* response length */
- inst->mlen,
- inst->header_present,
- BRW_SAMPLER_SIMD_MODE_SIMD4X2,
- return_format);
-
-   brw_mark_surface_used(&prog_data->base, surface_index);
+   uint32_t base_binding_table_index = (inst->opcode == SHADER_OPCODE_TG4 ||
+ inst->opcode == SHADER_OPCODE_TG4_OFFSET)
+ ? prog_data->base.binding_table.gather_texture_start
+ : prog_data->base.binding_table.texture_start;
+
+   if (sampler_index.file == BRW_IMMEDIATE_VALUE) {
+  uint32_t sampler = sampler_index.dw1.ud;
+
+  brw_SAMPLE(p,
+ dst,
+ inst->base_mrf,
+ src,
+ sampler + base_binding_table_index,
+ sampler % 16,
+ msg_type,
+ 1, /* response length */
+ inst->mlen,
+ inst->header_present,
+ BRW_SAMPLER_SIMD_MODE_SIMD4X2,
+ return_format);
+
+  brw_mark_surface_used(&prog_data->base, sampler + 
base_binding_table_index);
+   } else {
+  /* XXX: Non-constant sampler index. */
+   }
 }
 
 void

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Mesa (master): i965/fs: Add support for nonconst sampler indexing in FS visitor

[Chris Forbes]

Module: Mesa
Branch: master
Commit: abedd05bcdcfbe44d95338f92488c233187279a0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=abedd05bcdcfbe44d95338f92488c233187279a0

Author: Chris Forbes 
Date:   Sun Aug 10 12:12:06 2014 +1200

i965/fs: Add support for nonconst sampler indexing in FS visitor

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_fs.h   |4 +-
 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |   60 +++---
 2 files changed, 55 insertions(+), 9 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
b/src/mesa/drivers/dri/i965/brw_fs.h
index 5aa0ca6..0f8fb2d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -380,8 +380,8 @@ public:
   fs_reg sample_index, uint32_t sampler);
fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
   fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
-  fs_reg sample_index, fs_reg mcs, uint32_t 
sampler);
-   fs_reg emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, uint32_t sampler);
+  fs_reg sample_index, fs_reg mcs, fs_reg sampler);
+   fs_reg emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, fs_reg sampler);
void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
fs_reg fix_math_operand(fs_reg src);
fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 5d439fc..05082ee 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1434,10 +1434,19 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg 
dst, fs_reg coordinate,
return inst;
 }
 
+static bool
+is_high_sampler(struct brw_context *brw, fs_reg sampler)
+{
+   if (brw->gen < 8 && !brw->is_haswell)
+  return false;
+
+   return sampler.file != IMM || sampler.fixed_hw_reg.dw1.ud >= 16;
+}
+
 fs_inst *
 fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
   fs_reg shadow_c, fs_reg lod, fs_reg lod2,
-  fs_reg sample_index, fs_reg mcs, uint32_t 
sampler)
+  fs_reg sample_index, fs_reg mcs, fs_reg sampler)
 {
int reg_width = dispatch_width / 8;
bool header_present = false;
@@ -1448,7 +1457,8 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, 
fs_reg coordinate,
}
int length = 0;
 
-   if (ir->op == ir_tg4 || (ir->offset && ir->op != ir_txf) || sampler >= 16) {
+   if (ir->op == ir_tg4 || (ir->offset && ir->op != ir_txf) ||
+   is_high_sampler(brw, sampler)) {
   /* For general texture offsets (no txf workaround), we need a header to
* put them in.  Note that for SIMD16 we're making space for two actual
* hardware registers here, so the emit will have to fix up for this.
@@ -1623,7 +1633,7 @@ fs_visitor::emit_texture_gen7(ir_texture *ir, fs_reg dst, 
fs_reg coordinate,
default:
   unreachable("not reached");
}
-   fs_inst *inst = emit(opcode, dst, src_payload, fs_reg(sampler));
+   fs_inst *inst = emit(opcode, dst, src_payload, sampler);
inst->base_mrf = -1;
if (reg_width == 2)
   inst->mlen = length * reg_width - header_present;
@@ -1756,7 +1766,7 @@ fs_visitor::rescale_texcoord(ir_texture *ir, fs_reg 
coordinate,
 
 /* Sample from the MCS surface attached to this multisample texture. */
 fs_reg
-fs_visitor::emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, uint32_t sampler)
+fs_visitor::emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, fs_reg sampler)
 {
int reg_width = dispatch_width / 8;
int length = ir->coordinate->type->vector_elements;
@@ -1774,7 +1784,7 @@ fs_visitor::emit_mcs_fetch(ir_texture *ir, fs_reg 
coordinate, uint32_t sampler)
 
emit(LOAD_PAYLOAD(payload, sources, length));
 
-   fs_inst *inst = emit(SHADER_OPCODE_TXF_MCS, dest, payload, fs_reg(sampler));
+   fs_inst *inst = emit(SHADER_OPCODE_TXF_MCS, dest, payload, sampler);
inst->base_mrf = -1;
inst->mlen = length * reg_width;
inst->header_present = false;
@@ -1792,6 +1802,42 @@ fs_visitor::visit(ir_texture *ir)
 
uint32_t sampler =
   _mesa_get_sampler_uniform_value(ir->sampler, shader_prog, prog);
+
+   ir_rvalue *nonconst_sampler_index =
+  _mesa_get_sampler_array_nonconst_index(ir->sampler);
+
+   /* Handle non-constant sampler array indexing */
+   fs_reg sampler_reg;
+   if (nonconst_sampler_index) {
+  /* The highest sampler which may be used by this operation is
+   * the last element of the array. Mark it here, because the generator
+   * doesn't have enough information to determine the bound.
+   */
+  uint32_t array_size = ir->sampler->as

Mesa (master): docs: Mark off ARB_gpu_shader5 UBO array indexing for i965

[Chris Forbes]

Module: Mesa
Branch: master
Commit: ceaf823e2333e8b41a508b58d18e0054b9b1fd4d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ceaf823e2333e8b41a508b58d18e0054b9b1fd4d

Author: Chris Forbes 
Date:   Sun Aug  3 12:32:10 2014 +1200

docs: Mark off ARB_gpu_shader5 UBO array indexing for i965

Signed-off-by: Chris Forbes 

---

 docs/GL3.txt |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index 65ff5ba..0666fb9 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -97,7 +97,7 @@ GL 4.0, GLSL 4.00:
   GL_ARB_gpu_shader5   DONE (nvc0)
   - 'precise' qualifierDONE
   - Dynamically uniform sampler array indices  DONE ()
-  - Dynamically uniform UBO array indices  DONE ()
+  - Dynamically uniform UBO array indices  DONE (i965)
   - Implicit signed -> unsigned conversionsDONE
   - Fused multiply-add DONE (i965)
   - Packing/bitfield/conversion functions  DONE (i965, r600)

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Mesa (master): i965/vec4: Generate indirect sends for nonconstant UBO array access

[Chris Forbes]

Module: Mesa
Branch: master
Commit: a55eae9b6d822ab1d5e61b400426b9350e152cc4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a55eae9b6d822ab1d5e61b400426b9350e152cc4

Author: Chris Forbes 
Date:   Sun Jul 13 11:43:11 2014 +1200

i965/vec4: Generate indirect sends for nonconstant UBO array access

Signed-off-by: Chris Forbes 

---

 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp |   77 +-
 1 file changed, 62 insertions(+), 15 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index c63b47a..f5e459a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -840,23 +840,70 @@ 
vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
  struct brw_reg surf_index,
  struct brw_reg offset)
 {
-   assert(surf_index.file == BRW_IMMEDIATE_VALUE &&
- surf_index.type == BRW_REGISTER_TYPE_UD);
+   assert(surf_index.type == BRW_REGISTER_TYPE_UD);
 
-   brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
-   brw_set_dest(p, insn, dst);
-   brw_set_src0(p, insn, offset);
-   brw_set_sampler_message(p, insn,
-   surf_index.dw1.ud,
-   0, /* LD message ignores sampler unit */
-   GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
-   1, /* rlen */
-   1, /* mlen */
-   false, /* no header */
-   BRW_SAMPLER_SIMD_MODE_SIMD4X2,
-   0);
+   if (surf_index.file == BRW_IMMEDIATE_VALUE) {
 
-   brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
+  brw_inst *insn = brw_next_insn(p, BRW_OPCODE_SEND);
+  brw_set_dest(p, insn, dst);
+  brw_set_src0(p, insn, offset);
+  brw_set_sampler_message(p, insn,
+  surf_index.dw1.ud,
+  0, /* LD message ignores sampler unit */
+  GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
+  1, /* rlen */
+  1, /* mlen */
+  false, /* no header */
+  BRW_SAMPLER_SIMD_MODE_SIMD4X2,
+  0);
+
+  brw_mark_surface_used(&prog_data->base, surf_index.dw1.ud);
+
+   } else {
+
+  struct brw_reg addr = vec1(retype(brw_address_reg(0), 
BRW_REGISTER_TYPE_UD));
+
+  brw_push_insn_state(p);
+  brw_set_default_mask_control(p, BRW_MASK_DISABLE);
+  brw_set_default_access_mode(p, BRW_ALIGN_1);
+
+  /* a0.0 = surf_index & 0xff */
+  brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
+  brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
+  brw_set_dest(p, insn_and, addr);
+  brw_set_src0(p, insn_and, vec1(retype(surf_index, 
BRW_REGISTER_TYPE_UD)));
+  brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
+
+
+  /* a0.0 |=  */
+  brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
+  brw_set_sampler_message(p, insn_or,
+  0 /* surface */,
+  0 /* sampler */,
+  GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
+  1 /* rlen */,
+  1 /* mlen */,
+  false /* header */,
+  BRW_SAMPLER_SIMD_MODE_SIMD4X2,
+  0);
+  brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
+  brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
+  brw_set_src0(p, insn_or, addr);
+  brw_set_dest(p, insn_or, addr);
+
+
+  /* dst = send(offset, a0.0) */
+  brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
+  brw_set_dest(p, insn_send, dst);
+  brw_set_src0(p, insn_send, offset);
+  brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
+
+  brw_pop_insn_state(p);
+
+  /* visitor knows more than we do about the surface limit required,
+   * so has already done marking.
+   */
+   }
 }
 
 void

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Mesa (master): i965/fs: Generate indirect sends for nonconstant UBO array accesses

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 3fd359b10dab59803c3c41664d3e2b9235ef2abc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3fd359b10dab59803c3c41664d3e2b9235ef2abc

Author: Chris Forbes 
Date:   Sat Aug  2 14:27:21 2014 +1200

i965/fs: Generate indirect sends for nonconstant UBO array accesses

Signed-off-by: Chris Forbes 

---

 src/mesa/drivers/dri/i965/brw_fs_generator.cpp |  174 ++--
 1 file changed, 135 insertions(+), 39 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 5fda22b..d905567 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -845,39 +845,88 @@ 
fs_generator::generate_uniform_pull_constant_load_gen7(fs_inst *inst,
struct brw_reg offset)
 {
assert(inst->mlen == 0);
-
-   assert(index.file == BRW_IMMEDIATE_VALUE &&
- index.type == BRW_REGISTER_TYPE_UD);
-   uint32_t surf_index = index.dw1.ud;
+   assert(index.type == BRW_REGISTER_TYPE_UD);
 
assert(offset.file == BRW_GENERAL_REGISTER_FILE);
/* Reference just the dword we need, to avoid angering validate_reg(). */
offset = brw_vec1_grf(offset.nr, 0);
 
-   brw_push_insn_state(p);
-   brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
-   brw_set_default_mask_control(p, BRW_MASK_DISABLE);
-   brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
-   brw_pop_insn_state(p);
-
/* We use the SIMD4x2 mode because we want to end up with 4 components in
 * the destination loaded consecutively from the same offset (which appears
 * in the first component, and the rest are ignored).
 */
dst.width = BRW_WIDTH_4;
-   brw_set_dest(p, send, dst);
-   brw_set_src0(p, send, offset);
-   brw_set_sampler_message(p, send,
-   surf_index,
-   0, /* LD message ignores sampler unit */
-   GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
-   1, /* rlen */
-   1, /* mlen */
-   false, /* no header */
-   BRW_SAMPLER_SIMD_MODE_SIMD4X2,
-   0);
 
-   brw_mark_surface_used(&prog_data->base, surf_index);
+   if (index.file == BRW_IMMEDIATE_VALUE) {
+
+  uint32_t surf_index = index.dw1.ud;
+
+  brw_push_insn_state(p);
+  brw_set_default_compression_control(p, BRW_COMPRESSION_NONE);
+  brw_set_default_mask_control(p, BRW_MASK_DISABLE);
+  brw_inst *send = brw_next_insn(p, BRW_OPCODE_SEND);
+  brw_pop_insn_state(p);
+
+  brw_set_dest(p, send, dst);
+  brw_set_src0(p, send, offset);
+  brw_set_sampler_message(p, send,
+  surf_index,
+  0, /* LD message ignores sampler unit */
+  GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
+  1, /* rlen */
+  1, /* mlen */
+  false, /* no header */
+  BRW_SAMPLER_SIMD_MODE_SIMD4X2,
+  0);
+
+  brw_mark_surface_used(&prog_data->base, surf_index);
+
+   } else {
+
+  struct brw_reg addr = vec1(retype(brw_address_reg(0), 
BRW_REGISTER_TYPE_UD));
+
+  brw_push_insn_state(p);
+  brw_set_default_mask_control(p, BRW_MASK_DISABLE);
+  brw_set_default_access_mode(p, BRW_ALIGN_1);
+
+  /* a0.0 = surf_index & 0xff */
+  brw_inst *insn_and = brw_next_insn(p, BRW_OPCODE_AND);
+  brw_inst_set_exec_size(p->brw, insn_and, BRW_EXECUTE_1);
+  brw_set_dest(p, insn_and, addr);
+  brw_set_src0(p, insn_and, vec1(retype(index, BRW_REGISTER_TYPE_UD)));
+  brw_set_src1(p, insn_and, brw_imm_ud(0x0ff));
+
+
+  /* a0.0 |=  */
+  brw_inst *insn_or = brw_next_insn(p, BRW_OPCODE_OR);
+  brw_set_sampler_message(p, insn_or,
+  0 /* surface */,
+  0 /* sampler */,
+  GEN5_SAMPLER_MESSAGE_SAMPLE_LD,
+  1 /* rlen */,
+  1 /* mlen */,
+  false /* header */,
+  BRW_SAMPLER_SIMD_MODE_SIMD4X2,
+  0);
+  brw_inst_set_exec_size(p->brw, insn_or, BRW_EXECUTE_1);
+  brw_inst_set_src1_reg_type(p->brw, insn_or, BRW_REGISTER_TYPE_UD);
+  brw_set_src0(p, insn_or, addr);
+  brw_set_dest(p, insn_or, addr);
+
+
+  /* dst = send(offset, a0.0) */
+  brw_inst *insn_send = brw_next_insn(p, BRW_OPCODE_SEND);
+  brw_set_dest(p, insn_send, dst);
+  brw_set_src0(p, insn_send, offset);
+  brw_set_indirect_send_descriptor(p, insn_send, BRW_SFID_SAMPLER, addr);
+
+  brw_pop_insn_state(p);
+
+  /* visitor knows more than we do about the surface limit r

Mesa (master): i965: Adjust set_message_descriptor to handle non-sends

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 17e0fa9a066967ee7765d857e3a91f3a6bd4e566
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=17e0fa9a066967ee7765d857e3a91f3a6bd4e566

Author: Chris Forbes 
Date:   Sun Aug  3 12:02:25 2014 +1200

i965: Adjust set_message_descriptor to handle non-sends

We're about to be using this infrastructure to build descriptors in
src1 of non-send instructions, when preparing to do an indirect send.

Don't accidentally clobber the conditionalmod field of those
instructions with SFID bits, which aren't part of the descriptor.

Signed-off-by: Chris Forbes 

---

 src/mesa/drivers/dri/i965/brw_eu_emit.c |   14 +-
 1 file changed, 13 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index c2a4083..c18ac3a 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -540,7 +540,19 @@ brw_set_message_descriptor(struct brw_compile *p,
struct brw_context *brw = p->brw;
 
brw_set_src1(p, inst, brw_imm_d(0));
-   brw_inst_set_sfid(brw, inst, sfid);
+
+   /* For indirect sends, `inst` will not be the SEND/SENDC instruction
+* itself; instead, it will be a MOV/OR into the address register.
+*
+* In this case, we avoid setting the extended message descriptor bits,
+* since they go on the later SEND/SENDC instead and if set here would
+* instead clobber the conditionalmod bits.
+*/
+   unsigned opcode = brw_inst_opcode(brw, inst);
+   if (opcode == BRW_OPCODE_SEND || opcode == BRW_OPCODE_SENDC) {
+  brw_inst_set_sfid(brw, inst, sfid);
+   }
+
brw_inst_set_mlen(brw, inst, msg_length);
brw_inst_set_rlen(brw, inst, response_length);
brw_inst_set_eot(brw, inst, end_of_thread);

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Mesa (master): i965: Add low-level support for indirect sends

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 3512c79789e3b924c4f639a157cac7b80fea16f2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3512c79789e3b924c4f639a157cac7b80fea16f2

Author: Chris Forbes 
Date:   Sun Aug  3 11:44:25 2014 +1200

i965: Add low-level support for indirect sends

This provides a reasonable place to enforce the hardware restriction
that indirect descriptors must be in a0.0

Signed-off-by: Chris Forbes 

---

 src/mesa/drivers/dri/i965/brw_eu.h  |5 +
 src/mesa/drivers/dri/i965/brw_eu_emit.c |   15 +++
 2 files changed, 20 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_eu.h 
b/src/mesa/drivers/dri/i965/brw_eu.h
index 93f0345..5122e63 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -205,6 +205,11 @@ void brw_set_sampler_message(struct brw_compile *p,
  unsigned simd_mode,
  unsigned return_format);
 
+void brw_set_indirect_send_descriptor(struct brw_compile *p,
+  brw_inst *insn,
+  unsigned sfid,
+  struct brw_reg descriptor);
+
 void brw_set_dp_read_message(struct brw_compile *p,
 brw_inst *insn,
 unsigned binding_table_index,
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 65c06ec..c2a4083 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -760,6 +760,21 @@ brw_set_sampler_message(struct brw_compile *p,
}
 }
 
+void brw_set_indirect_send_descriptor(struct brw_compile *p,
+  brw_inst *insn,
+  unsigned sfid,
+  struct brw_reg descriptor)
+{
+   /* Only a0.0 may be used as SEND's descriptor operand. */
+   assert(descriptor.file == BRW_ARCHITECTURE_REGISTER_FILE);
+   assert(descriptor.type == BRW_REGISTER_TYPE_UD);
+   assert(descriptor.nr == BRW_ARF_ADDRESS);
+   assert(descriptor.subnr == 0);
+
+   brw_set_message_descriptor(p, insn, sfid, 0, 0, false, false);
+   brw_set_src1(p, insn, descriptor);
+}
+
 static void
 gen7_set_dp_scratch_message(struct brw_compile *p,
 brw_inst *inst,

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Mesa (master): i965/vec4: Add visitor support for nonconst ubo block indexing

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 70354ca6686f137859912e9ffdd24a8e6f45e2d5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=70354ca6686f137859912e9ffdd24a8e6f45e2d5

Author: Chris Forbes 
Date:   Sun Jun 29 12:30:04 2014 +1200

i965/vec4: Add visitor support for nonconst ubo block indexing

Signed-off-by: Chris Forbes 

---

 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |   29 +---
 1 file changed, 26 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index b17ef34..10d96c7 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -1624,7 +1624,7 @@ vec4_visitor::visit(ir_expression *ir)
   break;
 
case ir_binop_ubo_load: {
-  ir_constant *uniform_block = ir->operands[0]->as_constant();
+  ir_constant *const_uniform_block = ir->operands[0]->as_constant();
   ir_constant *const_offset_ir = ir->operands[1]->as_constant();
   unsigned const_offset = const_offset_ir ? const_offset_ir->value.u[0] : 
0;
   src_reg offset;
@@ -1634,8 +1634,31 @@ vec4_visitor::visit(ir_expression *ir)
 
   src_reg packed_consts = src_reg(this, glsl_type::vec4_type);
   packed_consts.type = result.type;
-  src_reg surf_index =
- src_reg(prog_data->base.binding_table.ubo_start + 
uniform_block->value.u[0]);
+  src_reg surf_index;
+
+  if (const_uniform_block) {
+ /* The block index is a constant, so just emit the binding table entry
+  * as an immediate.
+  */
+ surf_index = src_reg(prog_data->base.binding_table.ubo_start +
+  const_uniform_block->value.u[0]);
+  } else {
+ /* The block index is not a constant. Evaluate the index expression
+  * per-channel and add the base UBO index; the generator will select
+  * a value from any live channel.
+  */
+ surf_index = src_reg(this, glsl_type::uint_type);
+ emit(ADD(dst_reg(surf_index), op[0],
+  src_reg(prog_data->base.binding_table.ubo_start)));
+
+ /* Assume this may touch any UBO. It would be nice to provide
+  * a tighter bound, but the array information is already lowered away.
+  */
+ brw_mark_surface_used(&prog_data->base,
+   prog_data->base.binding_table.ubo_start +
+   shader_prog->NumUniformBlocks - 1);
+  }
+
   if (const_offset_ir) {
  if (brw->gen >= 8) {
 /* Store the offset in a GRF so we can send-from-GRF. */

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Mesa (master): i965/fs: Add visitor support for nonconstant UBO indices

[Chris Forbes]

Module: Mesa
Branch: master
Commit: ad9fce6811894e53819709a861624b7c642b234d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad9fce6811894e53819709a861624b7c642b234d

Author: Chris Forbes 
Date:   Sun May 18 12:38:57 2014 +1200

i965/fs: Add visitor support for nonconstant UBO indices

Signed-off-by: Chris Forbes 

---

 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |   30 +++---
 1 file changed, 27 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index f72909e..5d439fc 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -900,10 +900,34 @@ fs_visitor::visit(ir_expression *ir)
   /* This IR node takes a constant uniform block and a constant or
* variable byte offset within the block and loads a vector from that.
*/
-  ir_constant *uniform_block = ir->operands[0]->as_constant();
+  ir_constant *const_uniform_block = ir->operands[0]->as_constant();
   ir_constant *const_offset = ir->operands[1]->as_constant();
-  fs_reg surf_index = fs_reg(prog_data->base.binding_table.ubo_start +
- uniform_block->value.u[0]);
+  fs_reg surf_index;
+
+  if (const_uniform_block) {
+ /* The block index is a constant, so just emit the binding table entry
+  * as an immediate.
+  */
+ surf_index = fs_reg(prog_data->base.binding_table.ubo_start +
+ const_uniform_block->value.u[0]);
+  } else {
+ /* The block index is not a constant. Evaluate the index expression
+  * per-channel and add the base UBO index; the generator will select
+  * a value from any live channel.
+  */
+ surf_index = fs_reg(this, glsl_type::uint_type);
+ emit(ADD(surf_index, op[0],
+  fs_reg(prog_data->base.binding_table.ubo_start)))
+->force_writemask_all = true;
+
+ /* Assume this may touch any UBO. It would be nice to provide
+  * a tighter bound, but the array information is already lowered away.
+  */
+ brw_mark_surface_used(&prog_data->base,
+   prog_data->base.binding_table.ubo_start +
+   shader_prog->NumUniformBlocks - 1);
+  }
+
   if (const_offset) {
  fs_reg packed_consts = fs_reg(this, glsl_type::float_type);
  packed_consts.type = result.type;

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Mesa (master): docs: Mark off ARB_derivative_control for i965.

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 417cc8b2c837c4269a38aaad0a1109373b1f98c6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=417cc8b2c837c4269a38aaad0a1109373b1f98c6

Author: Chris Forbes 
Date:   Thu Aug 14 21:14:47 2014 +1200

docs: Mark off ARB_derivative_control for i965.

Also update 10.3 relnotes to match.

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 

---

 docs/GL3.txt|2 +-
 docs/relnotes/10.3.html |2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index e1fda45..65ff5ba 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -188,7 +188,7 @@ GL 4.5, GLSL 4.50:
   GL_ARB_clip_control  not started
   GL_ARB_conditional_render_inverted   not started
   GL_ARB_cull_distance not started
-  GL_ARB_derivative_controlDONE (nv50, nvc0)
+  GL_ARB_derivative_controlDONE (i965, nv50, nvc0)
   GL_ARB_direct_state_access   not started
   GL_ARB_get_texture_sub_image started (Brian Paul)
   GL_ARB_shader_texture_image_samples  not started
diff --git a/docs/relnotes/10.3.html b/docs/relnotes/10.3.html
index 3e469a1..cb65685 100644
--- a/docs/relnotes/10.3.html
+++ b/docs/relnotes/10.3.html
@@ -47,7 +47,7 @@ Note: some of the new features are only available with 
certain drivers.
 GL_ARB_ES3_compatibility on nv50, nvc0, r600, radeonsi, softpipe, 
llvmpipe
 GL_ARB_clear_texture on i965
 GL_ARB_compressed_texture_pixel_storage on all drivers
-GL_ARB_derivative_control on nv50, nvc0
+GL_ARB_derivative_control on i965, nv50, nvc0
 GL_ARB_draw_indirect on nvc0, radeonsi
 GL_ARB_explicit_uniform_location (all drivers that support GLSL)
 GL_ARB_fragment_layer_viewport on nv50, nvc0, llvmpipe, r600

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Mesa (master): i965/vec4: Assert that fine/coarse derivative ops don' t appear

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 587e6e78984cd7490ac68b83d0b751bf23256595
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=587e6e78984cd7490ac68b83d0b751bf23256595

Author: Chris Forbes 
Date:   Thu Aug 14 20:38:33 2014 +1200

i965/vec4: Assert that fine/coarse derivative ops don't appear

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 

---

 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |4 
 1 file changed, 4 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index ce64b30..b17ef34 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -1350,7 +1350,11 @@ vec4_visitor::visit(ir_expression *ir)
   break;
 
case ir_unop_dFdx:
+   case ir_unop_dFdx_coarse:
+   case ir_unop_dFdx_fine:
case ir_unop_dFdy:
+   case ir_unop_dFdy_coarse:
+   case ir_unop_dFdy_fine:
   unreachable("derivatives not valid in vertex shader");
 
case ir_unop_bitfield_reverse:

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Mesa (master): glsl: Mark program as using dFdy if coarse/ fine variant is used

[Chris Forbes]

Module: Mesa
Branch: master
Commit: eba0c54f6229868339ec80f799a6b7b9fb6a05ec
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eba0c54f6229868339ec80f799a6b7b9fb6a05ec

Author: Chris Forbes 
Date:   Thu Aug 14 21:03:53 2014 +1200

glsl: Mark program as using dFdy if coarse/fine variant is used

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 

---

 src/glsl/ir_set_program_inouts.cpp |4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/glsl/ir_set_program_inouts.cpp 
b/src/glsl/ir_set_program_inouts.cpp
index 5163eb2..97ead75 100644
--- a/src/glsl/ir_set_program_inouts.cpp
+++ b/src/glsl/ir_set_program_inouts.cpp
@@ -306,7 +306,9 @@ ir_visitor_status
 ir_set_program_inouts_visitor::visit_enter(ir_expression *ir)
 {
if (this->shader_stage == MESA_SHADER_FRAGMENT &&
-   ir->operation == ir_unop_dFdy) {
+   (ir->operation == ir_unop_dFdy ||
+ir->operation == ir_unop_dFdy_coarse ||
+ir->operation == ir_unop_dFdy_fine)) {
   gl_fragment_program *fprog = (gl_fragment_program *) prog;
   fprog->UsesDFdy = true;
}

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Mesa (master): i965: Enable ARB_derivative_control on Gen7+.

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 654b7788ebe7db63a3c5442d4eb1144b9284e9af
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=654b7788ebe7db63a3c5442d4eb1144b9284e9af

Author: Chris Forbes 
Date:   Thu Aug 14 21:11:28 2014 +1200

i965: Enable ARB_derivative_control on Gen7+.

The extension says GL 4.0 is required. We'll meet the spirit
of that restriction by enabling on just those generations which will
soon support GL 4.0 (Gen7+), although it's technically supportable on
all generations.

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 

---

 src/mesa/drivers/dri/i965/intel_extensions.c |1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c 
b/src/mesa/drivers/dri/i965/intel_extensions.c
index e134cd9..c672044 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -305,6 +305,7 @@ intelInitExtensions(struct gl_context *ctx)
   }
 
   ctx->Extensions.ARB_texture_compression_bptc = true;
+  ctx->Extensions.ARB_derivative_control = true;
}
 
if (brw->gen >= 8) {

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Mesa (master): i965/fs: Support fine/coarse derivative opcodes

[Chris Forbes]

Module: Mesa
Branch: master
Commit: a39622452069b76f7562472cc15ddefd2db4b503
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a39622452069b76f7562472cc15ddefd2db4b503

Author: Chris Forbes 
Date:   Thu Aug 14 20:59:15 2014 +1200

i965/fs: Support fine/coarse derivative opcodes

The quality level (fine/coarse/dont-care) is plumbed through to the
generator as a constant in src1.

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 

---

 src/mesa/drivers/dri/i965/brw_defines.h|6 +
 src/mesa/drivers/dri/i965/brw_fs.h |4 ++--
 .../dri/i965/brw_fs_channel_expressions.cpp|4 
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp |   24 +++-
 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp   |   16 +++--
 5 files changed, 44 insertions(+), 10 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 3564041..1322ed2 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1004,6 +1004,12 @@ enum opcode {
GS_OPCODE_GET_INSTANCE_ID,
 };
 
+enum brw_derivative_quality {
+   BRW_DERIVATIVE_BY_HINT = 0,
+   BRW_DERIVATIVE_FINE = 1,
+   BRW_DERIVATIVE_COARSE = 2,
+};
+
 enum brw_urb_write_flags {
BRW_URB_WRITE_NO_FLAGS = 0,
 
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
b/src/mesa/drivers/dri/i965/brw_fs.h
index 5cad504..a838e74 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -604,9 +604,9 @@ private:
void generate_math_g45(fs_inst *inst,
  struct brw_reg dst,
  struct brw_reg src);
-   void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
+   void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src, 
struct brw_reg quality);
void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
- bool negate_value);
+ struct brw_reg quality, bool negate_value);
void generate_scratch_write(fs_inst *inst, struct brw_reg src);
void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
index 4113f47..d98b7eb 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
@@ -237,7 +237,11 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment 
*ir)
case ir_unop_sin_reduced:
case ir_unop_cos_reduced:
case ir_unop_dFdx:
+   case ir_unop_dFdx_coarse:
+   case ir_unop_dFdx_fine:
case ir_unop_dFdy:
+   case ir_unop_dFdy_coarse:
+   case ir_unop_dFdy_fine:
case ir_unop_bitfield_reverse:
case ir_unop_bit_count:
case ir_unop_find_msb:
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 1190f1f..6efd41c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -644,11 +644,17 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg 
dst, struct brw_reg src
  * appropriate swizzling.
  */
 void
-fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg 
src)
+fs_generator::generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg 
src,
+   struct brw_reg quality)
 {
unsigned vstride, width;
+   assert(quality.file == BRW_IMMEDIATE_VALUE);
+   assert(quality.type == BRW_REGISTER_TYPE_D);
 
-   if (key->high_quality_derivatives) {
+   int quality_value = quality.dw1.d;
+
+   if (quality_value == BRW_DERIVATIVE_FINE ||
+  (key->high_quality_derivatives && quality_value != 
BRW_DERIVATIVE_COARSE)) {
   /* produce accurate derivatives */
   vstride = BRW_VERTICAL_STRIDE_2;
   width = BRW_WIDTH_2;
@@ -680,9 +686,15 @@ fs_generator::generate_ddx(fs_inst *inst, struct brw_reg 
dst, struct brw_reg src
  */
 void
 fs_generator::generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg 
src,
- bool negate_value)
+ struct brw_reg quality, bool negate_value)
 {
-   if (key->high_quality_derivatives) {
+   assert(quality.file == BRW_IMMEDIATE_VALUE);
+   assert(quality.type == BRW_REGISTER_TYPE_D);
+
+   int quality_value = quality.dw1.d;
+
+   if (quality_value == BRW_DERIVATIVE_FINE ||
+  (key->high_quality_derivatives && quality_value != 
BRW_DERIVATIVE_COARSE)) {
   /* From the Ivy Bridge PRM, volume 4 part 3, section 3.3.9 (Register
* Region Restrictions):
*
@@ -1655,14 +1667,14 @@ fs_generator::generate_code(exec_list *instructions)
 generate_tex(inst, dst, src[0], src[1]);
 break;
   case FS_OPCODE_DDX:
-generate_ddx(inst, dst, sr

Mesa (master): mesa: Make ARB_gpu_shader5 core-profile-only

[Chris Forbes]

Module: Mesa
Branch: master
Commit: c1df492d03862f75698ba5d50d4f46cd528ffc0d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c1df492d03862f75698ba5d50d4f46cd528ffc0d

Author: Chris Forbes 
Date:   Sun Aug 10 16:10:29 2014 +1200

mesa: Make ARB_gpu_shader5 core-profile-only

Requires GLSL 1.50 or higher, which we only support in the core profile.

V2: Fix broken alignment

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 

---

 src/mesa/main/extensions.c |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index 4f322d0..ba26e46 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main/extensions.c
@@ -116,7 +116,7 @@ static const struct extension extension_table[] = {
{ "GL_ARB_framebuffer_object",  o(ARB_framebuffer_object),  
GL, 2005 },
{ "GL_ARB_framebuffer_sRGB",o(EXT_framebuffer_sRGB),
GL, 1998 },
{ "GL_ARB_get_program_binary",  o(dummy_true),  
GL, 2010 },
-   { "GL_ARB_gpu_shader5", o(ARB_gpu_shader5), 
GL, 2010 },
+   { "GL_ARB_gpu_shader5", o(ARB_gpu_shader5), 
GLC,2010 },
{ "GL_ARB_half_float_pixel",o(dummy_true),  
GL, 2003 },
{ "GL_ARB_half_float_vertex",   o(ARB_half_float_vertex),   
GL, 2008 },
{ "GL_ARB_instanced_arrays",o(ARB_instanced_arrays),
GL, 2008 },

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Mesa (master): mesa: Add a new function for getting the nonconst sampler array index

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 3b48f6a4c06db57a7203d247994b05e55c9418c1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b48f6a4c06db57a7203d247994b05e55c9418c1

Author: Chris Forbes 
Date:   Sun Aug  3 19:55:55 2014 +1200

mesa: Add a new function for getting the nonconst sampler array index

If the array index is not a constant expression, the existing support
will assume a zero offset (giving us the sampler index of the base of
the array).

For dynamically uniform indexing of sampler arrays, we need both that
and the indexing expression.

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 
Reviewed-by: Ilia Mirkin 

---

 src/mesa/program/sampler.cpp |   11 +++
 src/mesa/program/sampler.h   |3 +++
 2 files changed, 14 insertions(+)

diff --git a/src/mesa/program/sampler.cpp b/src/mesa/program/sampler.cpp
index e6532be..29a5408 100644
--- a/src/mesa/program/sampler.cpp
+++ b/src/mesa/program/sampler.cpp
@@ -134,3 +134,14 @@ _mesa_get_sampler_uniform_value(class ir_dereference 
*sampler,
return shader_program->UniformStorage[location].sampler[shader].index +
   getname.offset;
 }
+
+
+extern "C" class ir_rvalue *
+_mesa_get_sampler_array_nonconst_index(class ir_dereference *sampler)
+{
+   ir_dereference_array *deref_arr = sampler->as_dereference_array();
+   if (!deref_arr || deref_arr->array_index->as_constant())
+  return NULL;
+
+   return deref_arr->array_index;
+}
diff --git a/src/mesa/program/sampler.h b/src/mesa/program/sampler.h
index 22467e9..8b7c3b6 100644
--- a/src/mesa/program/sampler.h
+++ b/src/mesa/program/sampler.h
@@ -27,3 +27,6 @@ int
 _mesa_get_sampler_uniform_value(class ir_dereference *sampler,
struct gl_shader_program *shader_program,
const struct gl_program *prog);
+
+class ir_rvalue *
+_mesa_get_sampler_array_nonconst_index(class ir_dereference *sampler);

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Mesa (master): glsl: Allow dynamically uniform sampler array indexing with 4.0/gs5

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 1b4761bc27a50208dba2bc028c9835fed572e696
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b4761bc27a50208dba2bc028c9835fed572e696

Author: Chris Forbes 
Date:   Sun Aug  3 17:57:05 2014 +1200

glsl: Allow dynamically uniform sampler array indexing with 4.0/gs5

V2: Expand comment to explain what dynamically uniform expressions are
about.

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 
Reviewed-by: Ilia Mirkin 

---

 src/glsl/ast_array_index.cpp |9 -
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/src/glsl/ast_array_index.cpp b/src/glsl/ast_array_index.cpp
index 50f9987..5ca85f6 100644
--- a/src/glsl/ast_array_index.cpp
+++ b/src/glsl/ast_array_index.cpp
@@ -213,6 +213,13 @@ _mesa_ast_array_index_to_hir(void *mem_ctx,
* as using a loop counter as the index to an array of samplers.  If the
* loop in unrolled, the code should compile correctly.  Instead, emit a
* warning.
+   *
+   * In GLSL 4.00 / ARB_gpu_shader5, this requirement is relaxed again to 
allow
+   * indexing with dynamically uniform expressions. Note that these are not
+   * required to be uniforms or expressions based on them, but merely that 
the
+   * values must not diverge between shader invocations run together. If 
the
+   * values *do* diverge, then the behavior of the operation requiring a
+   * dynamically uniform expression is undefined.
*/
   if (array->type->element_type()->is_sampler()) {
 if (!state->is_version(130, 100)) {
@@ -227,7 +234,7 @@ _mesa_ast_array_index_to_hir(void *mem_ctx,
  "expressions will be forbidden in GLSL 1.30 "
  "and later");
}
-} else {
+} else if (!state->is_version(400, 0) && 
!state->ARB_gpu_shader5_enable) {
_mesa_glsl_error(&loc, state,
 "sampler arrays indexed with non-constant "
 "expressions is forbidden in GLSL 1.30 and "

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Mesa (master): i965/vec4: Pass sampler index in src1 for texture ops

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 1a3fd11aefdf6ed327f633ea7e13bae2e8a92ca7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a3fd11aefdf6ed327f633ea7e13bae2e8a92ca7

Author: Chris Forbes 
Date:   Mon Aug  4 19:37:58 2014 +1200

i965/vec4: Pass sampler index in src1 for texture ops

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 
Reviewed-by: Ian Romanick 

---

 src/mesa/drivers/dri/i965/brw_vec4.h   |6 +++---
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |   12 
 2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 950b592..74a0568 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -526,10 +526,10 @@ public:
void emit_pack_half_2x16(dst_reg dst, src_reg src0);
void emit_unpack_half_2x16(dst_reg dst, src_reg src0);
 
-   uint32_t gather_channel(ir_texture *ir, int sampler);
-   src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, int sampler);
+   uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
+   src_reg emit_mcs_fetch(ir_texture *ir, src_reg coordinate, uint32_t 
sampler);
void emit_gen6_gather_wa(uint8_t wa, dst_reg dst);
-   void swizzle_result(ir_texture *ir, src_reg orig_val, int sampler);
+   void swizzle_result(ir_texture *ir, src_reg orig_val, uint32_t sampler);
 
void emit_ndc_computation();
void emit_psiz_and_flags(struct brw_reg reg);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 822eb6c..a47c3a6 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -2277,7 +2277,7 @@ vec4_visitor::visit(ir_call *ir)
 }
 
 src_reg
-vec4_visitor::emit_mcs_fetch(ir_texture *ir, src_reg coordinate, int sampler)
+vec4_visitor::emit_mcs_fetch(ir_texture *ir, src_reg coordinate, uint32_t 
sampler)
 {
vec4_instruction *inst = new(mem_ctx) vec4_instruction(this, 
SHADER_OPCODE_TXF_MCS);
inst->base_mrf = 2;
@@ -2286,6 +2286,8 @@ vec4_visitor::emit_mcs_fetch(ir_texture *ir, src_reg 
coordinate, int sampler)
inst->dst = dst_reg(this, glsl_type::uvec4_type);
inst->dst.writemask = WRITEMASK_XYZW;
 
+   inst->src[1] = src_reg(sampler);
+
/* parameters are: u, v, r, lod; lod will always be zero due to api 
restrictions */
int param_base = inst->base_mrf;
int coord_mask = (1 << ir->coordinate->type->vector_elements) - 1;
@@ -2304,7 +2306,7 @@ vec4_visitor::emit_mcs_fetch(ir_texture *ir, src_reg 
coordinate, int sampler)
 void
 vec4_visitor::visit(ir_texture *ir)
 {
-   int sampler =
+   uint32_t sampler =
   _mesa_get_sampler_uniform_value(ir->sampler, shader_prog, prog);
 
/* When tg4 is used with the degenerate ZERO/ONE swizzles, don't bother
@@ -2437,6 +2439,8 @@ vec4_visitor::visit(ir_texture *ir)
inst->dst.writemask = WRITEMASK_XYZW;
inst->shadow_compare = ir->shadow_comparitor != NULL;
 
+   inst->src[1] = src_reg(sampler);
+
/* MRF for the first parameter */
int param_base = inst->base_mrf + inst->header_present;
 
@@ -2588,7 +2592,7 @@ vec4_visitor::emit_gen6_gather_wa(uint8_t wa, dst_reg dst)
  * Set up the gather channel based on the swizzle, for gather4.
  */
 uint32_t
-vec4_visitor::gather_channel(ir_texture *ir, int sampler)
+vec4_visitor::gather_channel(ir_texture *ir, uint32_t sampler)
 {
ir_constant *chan = ir->lod_info.component->as_constant();
int swiz = GET_SWZ(key->tex.swizzles[sampler], chan->value.i[0]);
@@ -2609,7 +2613,7 @@ vec4_visitor::gather_channel(ir_texture *ir, int sampler)
 }
 
 void
-vec4_visitor::swizzle_result(ir_texture *ir, src_reg orig_val, int sampler)
+vec4_visitor::swizzle_result(ir_texture *ir, src_reg orig_val, uint32_t 
sampler)
 {
int s = key->tex.swizzles[sampler];
 

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Mesa (master): i965/blorp: Put sampler index in src1 of texture ops

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 191bc64f824beae1df9c82a9931a7776eda16e36
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=191bc64f824beae1df9c82a9931a7776eda16e36

Author: Chris Forbes 
Date:   Sun Aug  3 21:39:13 2014 +1200

i965/blorp: Put sampler index in src1 of texture ops

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 
Reviewed-by: Ian Romanick 

---

 src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
index 9459d5c..acaf92b 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
@@ -78,7 +78,8 @@ brw_blorp_eu_emitter::emit_texture_lookup(const struct 
brw_reg &dst,
   unsigned base_mrf,
   unsigned msg_length)
 {
-   fs_inst *inst = new (mem_ctx) fs_inst(op, dst, brw_message_reg(base_mrf));
+   fs_inst *inst = new (mem_ctx) fs_inst(op, dst, brw_message_reg(base_mrf),
+ fs_reg(0u));
 
inst->base_mrf = base_mrf;
inst->mlen = msg_length;

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Mesa (master): i965/fs: pass sampler as src1 of texture op

[Chris Forbes]

Module: Mesa
Branch: master
Commit: a578592fd28e5528ee32d8a1a1f7138cb977cf1b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a578592fd28e5528ee32d8a1a1f7138cb977cf1b

Author: Chris Forbes 
Date:   Sun Aug  3 21:13:02 2014 +1200

i965/fs: pass sampler as src1 of texture op

Reviewed-by: Matt Turner 
Reviewed-by: Ian Romanick 

---

 src/mesa/drivers/dri/i965/brw_fs.h   |   15 ++---
 src/mesa/drivers/dri/i965/brw_fs_fp.cpp  |4 ++--
 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |   29 +-
 3 files changed, 25 insertions(+), 23 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
b/src/mesa/drivers/dri/i965/brw_fs.h
index 9ba3f38..47aebad 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -241,8 +241,8 @@ public:
void visit(ir_emit_vertex *);
void visit(ir_end_primitive *);
 
-   uint32_t gather_channel(ir_texture *ir, int sampler);
-   void swizzle_result(ir_texture *ir, fs_reg orig_val, int sampler);
+   uint32_t gather_channel(ir_texture *ir, uint32_t sampler);
+   void swizzle_result(ir_texture *ir, fs_reg orig_val, uint32_t sampler);
 
fs_inst *emit(fs_inst *inst);
void emit(exec_list list);
@@ -371,16 +371,17 @@ public:
void emit_interpolation_setup_gen6();
void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
fs_reg rescale_texcoord(ir_texture *ir, fs_reg coordinate,
-   bool is_rect, int sampler, int texunit);
+   bool is_rect, uint32_t sampler, int texunit);
fs_inst *emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- fs_reg shadow_comp, fs_reg lod, fs_reg lod2);
+  fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
+  uint32_t sampler);
fs_inst *emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
   fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
-  fs_reg sample_index);
+  fs_reg sample_index, uint32_t sampler);
fs_inst *emit_texture_gen7(ir_texture *ir, fs_reg dst, fs_reg coordinate,
   fs_reg shadow_comp, fs_reg lod, fs_reg lod2,
-  fs_reg sample_index, fs_reg mcs, int sampler);
-   fs_reg emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, int sampler);
+  fs_reg sample_index, fs_reg mcs, uint32_t 
sampler);
+   fs_reg emit_mcs_fetch(ir_texture *ir, fs_reg coordinate, uint32_t sampler);
void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
fs_reg fix_math_operand(fs_reg src);
fs_inst *emit_math(enum opcode op, fs_reg dst, fs_reg src0);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
index 0c5daa7..35c056f 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
@@ -493,9 +493,9 @@ fs_visitor::emit_fragment_program_code()
  if (brw->gen >= 7) {
 inst = emit_texture_gen7(ir, dst, coordinate, shadow_c, lod, dpdy, 
sample_index, fs_reg(0u), fpi->TexSrcUnit);
  } else if (brw->gen >= 5) {
-inst = emit_texture_gen5(ir, dst, coordinate, shadow_c, lod, dpdy, 
sample_index);
+inst = emit_texture_gen5(ir, dst, coordinate, shadow_c, lod, dpdy, 
sample_index, fpi->TexSrcUnit);
  } else {
-inst = emit_texture_gen4(ir, dst, coordinate, shadow_c, lod, dpdy);
+inst = emit_texture_gen4(ir, dst, coordinate, shadow_c, lod, dpdy, 
fpi->TexSrcUnit);
  }
 
  inst->sampler = fpi->TexSrcUnit;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index a5a1d1a..534c652 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1095,7 +1095,8 @@ fs_visitor::visit(ir_assignment *ir)
 
 fs_inst *
 fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, fs_reg coordinate,
- fs_reg shadow_c, fs_reg lod, fs_reg dPdy)
+  fs_reg shadow_c, fs_reg lod, fs_reg dPdy,
+  uint32_t sampler)
 {
int mlen;
int base_mrf = 1;
@@ -1240,7 +1241,7 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, 
fs_reg coordinate,
   unreachable("not reached");
}
 
-   fs_inst *inst = emit(opcode, dst, reg_undef);
+   fs_inst *inst = emit(opcode, dst, reg_undef, fs_reg(sampler));
inst->base_mrf = base_mrf;
inst->mlen = mlen;
inst->header_present = true;
@@ -1268,7 +1269,7 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg dst, 
fs_reg coordinate,
 fs_inst *
 fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg dst, fs_reg coordinate,
   fs_reg shadow_c, fs_reg lod, fs_reg lod2,
-   

Mesa (master): i965/fs: Collect all emits of texture ops for Gen5/ 6 into one place

[Chris Forbes]

Module: Mesa
Branch: master
Commit: f6a0192f7d9ae91128d4006a906305b46a817fdf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f6a0192f7d9ae91128d4006a906305b46a817fdf

Author: Chris Forbes 
Date:   Sun Aug  3 20:48:20 2014 +1200

i965/fs: Collect all emits of texture ops for Gen5/6 into one place

Reduces duplication, and will do so even more when we change the sampler
plumbing.

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 
Reviewed-by: Ian Romanick 

---

 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |   31 +++---
 1 file changed, 18 insertions(+), 13 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 0e09087..a5a1d1a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1300,24 +1300,24 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg 
dst, fs_reg coordinate,
   mlen += reg_width;
}
 
-   fs_inst *inst = NULL;
+   enum opcode opcode;
switch (ir->op) {
case ir_tex:
-  inst = emit(SHADER_OPCODE_TEX, dst, reg_undef);
+  opcode = SHADER_OPCODE_TEX;
   break;
case ir_txb:
   mlen = MAX2(mlen, header_present + 4 * reg_width);
   emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
   mlen += reg_width;
 
-  inst = emit(FS_OPCODE_TXB, dst, reg_undef);
+  opcode = FS_OPCODE_TXB;
   break;
case ir_txl:
   mlen = MAX2(mlen, header_present + 4 * reg_width);
   emit(MOV(fs_reg(MRF, base_mrf + mlen), lod));
   mlen += reg_width;
 
-  inst = emit(SHADER_OPCODE_TXL, dst, reg_undef);
+  opcode = SHADER_OPCODE_TXL;
   break;
case ir_txd: {
   mlen = MAX2(mlen, header_present + 4 * reg_width); /* skip over 'ai' */
@@ -1341,23 +1341,26 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg 
dst, fs_reg coordinate,
 mlen += reg_width;
   }
 
-  inst = emit(SHADER_OPCODE_TXD, dst);
+  opcode = SHADER_OPCODE_TXD;
   break;
}
case ir_txs:
   emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), lod));
   mlen += reg_width;
-  inst = emit(SHADER_OPCODE_TXS, dst, reg_undef);
+
+  opcode = SHADER_OPCODE_TXS;
   break;
case ir_query_levels:
   emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), 
fs_reg(0u)));
   mlen += reg_width;
-  inst = emit(SHADER_OPCODE_TXS, dst, reg_undef);
+
+  opcode = SHADER_OPCODE_TXS;
   break;
case ir_txf:
   mlen = header_present + 4 * reg_width;
   emit(MOV(fs_reg(MRF, base_mrf + mlen - reg_width, BRW_REGISTER_TYPE_UD), 
lod));
-  inst = emit(SHADER_OPCODE_TXF, dst, reg_undef);
+
+  opcode = SHADER_OPCODE_TXF;
   break;
case ir_txf_ms:
   mlen = header_present + 4 * reg_width;
@@ -1367,18 +1370,20 @@ fs_visitor::emit_texture_gen5(ir_texture *ir, fs_reg 
dst, fs_reg coordinate,
   /* sample index */
   emit(MOV(fs_reg(MRF, base_mrf + mlen, BRW_REGISTER_TYPE_UD), 
sample_index));
   mlen += reg_width;
-  inst = emit(SHADER_OPCODE_TXF_CMS, dst, reg_undef);
+
+  opcode = SHADER_OPCODE_TXF_CMS;
   break;
case ir_lod:
-  inst = emit(SHADER_OPCODE_LOD, dst, reg_undef);
+  opcode = SHADER_OPCODE_LOD;
   break;
case ir_tg4:
-  inst = emit(SHADER_OPCODE_TG4, dst, reg_undef);
+  opcode = SHADER_OPCODE_TG4;
   break;
default:
-  fail("unrecognized texture opcode");
-  break;
+  unreachable("not reached");
}
+
+   fs_inst *inst = emit(opcode, dst, reg_undef);
inst->base_mrf = base_mrf;
inst->mlen = mlen;
inst->header_present = header_present;

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Mesa (master): i965/vec4/Gen4-7: Use src1 for sampler_index instead of -> sampler field

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 6be68767b9b5344d5753b8909f5ec8f57309b71a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6be68767b9b5344d5753b8909f5ec8f57309b71a

Author: Chris Forbes 
Date:   Mon Aug  4 19:41:03 2014 +1200

i965/vec4/Gen4-7: Use src1 for sampler_index instead of ->sampler field

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 
Reviewed-by: Ian Romanick 

---

 src/mesa/drivers/dri/i965/brw_vec4.h |5 +++--
 src/mesa/drivers/dri/i965/brw_vec4_generator.cpp |   18 --
 2 files changed, 15 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 74a0568..7c2721d 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -644,8 +644,9 @@ private:
struct brw_reg src1);
 
void generate_tex(vec4_instruction *inst,
-struct brw_reg dst,
-struct brw_reg src);
+ struct brw_reg dst,
+ struct brw_reg src,
+ struct brw_reg sampler_index);
 
void generate_vs_urb_write(vec4_instruction *inst);
void generate_gs_urb_write(vec4_instruction *inst);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 2129007..f362221f 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -225,7 +225,8 @@ vec4_generator::generate_math2_gen4(vec4_instruction *inst,
 void
 vec4_generator::generate_tex(vec4_instruction *inst,
  struct brw_reg dst,
- struct brw_reg src)
+ struct brw_reg src,
+ struct brw_reg sampler_index)
 {
int msg_type = -1;
 
@@ -313,6 +314,11 @@ vec4_generator::generate_tex(vec4_instruction *inst,
 
assert(msg_type != -1);
 
+   assert(sampler_index.file == BRW_IMMEDIATE_VALUE);
+   assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
+
+   uint32_t sampler = sampler_index.dw1.ud;
+
/* Load the message header if present.  If there's a texture offset, we need
 * to set it up explicitly and load the offset bitfield.  Otherwise, we can
 * use an implied move from g0 to the first message register.
@@ -338,7 +344,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
 brw_imm_ud(inst->texture_offset));
  }
 
- if (inst->sampler >= 16) {
+ if (sampler >= 16) {
 /* The "Sampler Index" field can only store values between 0 and 
15.
  * However, we can add an offset to the "Sampler State Pointer"
  * field, effectively selecting a different set of 16 samplers.
@@ -352,7 +358,7 @@ vec4_generator::generate_tex(vec4_instruction *inst,
 brw_ADD(p,
 get_element_ud(header, 3),
 get_element_ud(brw_vec8_grf(0, 0), 3),
-brw_imm_ud(16 * (inst->sampler / 16) * 
sampler_state_size));
+brw_imm_ud(16 * (sampler / 16) * sampler_state_size));
  }
  brw_pop_insn_state(p);
   }
@@ -375,14 +381,14 @@ vec4_generator::generate_tex(vec4_instruction *inst,
uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
   inst->opcode == SHADER_OPCODE_TG4_OFFSET)
   ? prog_data->base.binding_table.gather_texture_start
-  : prog_data->base.binding_table.texture_start) + inst->sampler;
+  : prog_data->base.binding_table.texture_start) + sampler;
 
brw_SAMPLE(p,
  dst,
  inst->base_mrf,
  src,
   surface_index,
- inst->sampler % 16,
+ sampler % 16,
  msg_type,
  1, /* response length */
  inst->mlen,
@@ -1131,7 +1137,7 @@ 
vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
case SHADER_OPCODE_TXS:
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
-  generate_tex(inst, dst, src[0]);
+  generate_tex(inst, dst, src[0], src[1]);
   break;
 
case VS_OPCODE_URB_WRITE:

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Mesa (master): i965/vec4: Collect all emits of texture ops into one place

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 2f4e12a83503f541dd63ac5e17b8044d3ae0f6c8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2f4e12a83503f541dd63ac5e17b8044d3ae0f6c8

Author: Chris Forbes 
Date:   Sun Aug  3 22:01:11 2014 +1200

i965/vec4: Collect all emits of texture ops into one place

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 
Reviewed-by: Ian Romanick 

---

 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |   38 
 1 file changed, 12 insertions(+), 26 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index c46325a..822eb6c 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -2393,33 +2393,17 @@ vec4_visitor::visit(ir_texture *ir)
   break;
}
 
-   vec4_instruction *inst = NULL;
+   enum opcode opcode;
switch (ir->op) {
-   case ir_tex:
-   case ir_txl:
-  inst = new(mem_ctx) vec4_instruction(this, SHADER_OPCODE_TXL);
-  break;
-   case ir_txd:
-  inst = new(mem_ctx) vec4_instruction(this, SHADER_OPCODE_TXD);
-  break;
-   case ir_txf:
-  inst = new(mem_ctx) vec4_instruction(this, SHADER_OPCODE_TXF);
-  break;
-   case ir_txf_ms:
-  inst = new(mem_ctx) vec4_instruction(this, SHADER_OPCODE_TXF_CMS);
-  break;
-   case ir_txs:
-  inst = new(mem_ctx) vec4_instruction(this, SHADER_OPCODE_TXS);
-  break;
-   case ir_tg4:
-  if (has_nonconstant_offset)
- inst = new(mem_ctx) vec4_instruction(this, SHADER_OPCODE_TG4_OFFSET);
-  else
- inst = new(mem_ctx) vec4_instruction(this, SHADER_OPCODE_TG4);
-  break;
-   case ir_query_levels:
-  inst = new(mem_ctx) vec4_instruction(this, SHADER_OPCODE_TXS);
-  break;
+   case ir_tex: opcode = SHADER_OPCODE_TXL; break;
+   case ir_txl: opcode = SHADER_OPCODE_TXL; break;
+   case ir_txd: opcode = SHADER_OPCODE_TXD; break;
+   case ir_txf: opcode = SHADER_OPCODE_TXF; break;
+   case ir_txf_ms: opcode = SHADER_OPCODE_TXF_CMS; break;
+   case ir_txs: opcode = SHADER_OPCODE_TXS; break;
+   case ir_tg4: opcode = has_nonconstant_offset
+ ? SHADER_OPCODE_TG4_OFFSET : SHADER_OPCODE_TG4; break;
+   case ir_query_levels: opcode = SHADER_OPCODE_TXS; break;
case ir_txb:
   unreachable("TXB is not valid for vertex shaders.");
case ir_lod:
@@ -2428,6 +2412,8 @@ vec4_visitor::visit(ir_texture *ir)
   unreachable("Unrecognized tex op");
}
 
+   vec4_instruction *inst = new(mem_ctx) vec4_instruction(this, opcode);
+
if (ir->offset != NULL && ir->op != ir_txf)
   inst->texture_offset = brw_texture_offset(ctx, 
ir->offset->as_constant());
 

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Mesa (master): i965/fs: Collect all emits of texture ops for Gen4 into one place

[Chris Forbes]

Module: Mesa
Branch: master
Commit: d1b136fdd0312a53691f8788b17b01ae967351f4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1b136fdd0312a53691f8788b17b01ae967351f4

Author: Chris Forbes 
Date:   Sun Aug  3 20:48:20 2014 +1200

i965/fs: Collect all emits of texture ops for Gen4 into one place

Reduces duplication, and will do so even more when we change the sampler
plumbing.

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 
Reviewed-by: Ian Romanick 

---

 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |   31 +-
 1 file changed, 11 insertions(+), 20 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 752e5a4..0e09087 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1227,29 +1227,20 @@ fs_visitor::emit_texture_gen4(ir_texture *ir, fs_reg 
dst, fs_reg coordinate,
 BRW_REGISTER_TYPE_F));
}
 
-   fs_inst *inst = NULL;
+   enum opcode opcode;
+
switch (ir->op) {
-   case ir_tex:
-  inst = emit(SHADER_OPCODE_TEX, dst, reg_undef);
-  break;
-   case ir_txb:
-  inst = emit(FS_OPCODE_TXB, dst, reg_undef);
-  break;
-   case ir_txl:
-  inst = emit(SHADER_OPCODE_TXL, dst, reg_undef);
-  break;
-   case ir_txd:
-  inst = emit(SHADER_OPCODE_TXD, dst, reg_undef);
-  break;
-   case ir_txs:
-  inst = emit(SHADER_OPCODE_TXS, dst, reg_undef);
-  break;
-   case ir_txf:
-  inst = emit(SHADER_OPCODE_TXF, dst, reg_undef);
-  break;
+   case ir_tex: opcode = SHADER_OPCODE_TEX; break;
+   case ir_txb: opcode = FS_OPCODE_TXB; break;
+   case ir_txl: opcode = SHADER_OPCODE_TXL; break;
+   case ir_txd: opcode = SHADER_OPCODE_TXD; break;
+   case ir_txs: opcode = SHADER_OPCODE_TXS; break;
+   case ir_txf: opcode = SHADER_OPCODE_TXF; break;
default:
-  fail("unrecognized texture opcode");
+  unreachable("not reached");
}
+
+   fs_inst *inst = emit(opcode, dst, reg_undef);
inst->base_mrf = base_mrf;
inst->mlen = mlen;
inst->header_present = true;

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Mesa (master): i965/fs/Gen8: Pass sampler_index to generate_tex

[Chris Forbes]

Module: Mesa
Branch: master
Commit: db09fd595743443974ccc14fbdb1c4e3733ab525
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=db09fd595743443974ccc14fbdb1c4e3733ab525

Author: Chris Forbes 
Date:   Sun Aug  3 21:23:31 2014 +1200

i965/fs/Gen8: Pass sampler_index to generate_tex

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 
Reviewed-by: Ian Romanick 

---

 src/mesa/drivers/dri/i965/brw_fs.h  |3 ++-
 src/mesa/drivers/dri/i965/gen8_fs_generator.cpp |   18 --
 2 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
b/src/mesa/drivers/dri/i965/brw_fs.h
index f3ce4e0..dfb13ea 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -717,7 +717,8 @@ private:
void generate_fb_write(fs_inst *inst);
void generate_linterp(fs_inst *inst, struct brw_reg dst,
  struct brw_reg *src);
-   void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
+   void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
+ struct brw_reg sampler_index);
void generate_math1(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
void generate_math2(fs_inst *inst, struct brw_reg dst,
struct brw_reg src0, struct brw_reg src1);
diff --git a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp 
b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
index 4e53d15..f4aae67 100644
--- a/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/gen8_fs_generator.cpp
@@ -153,7 +153,8 @@ gen8_fs_generator::generate_linterp(fs_inst *inst,
 void
 gen8_fs_generator::generate_tex(fs_inst *ir,
 struct brw_reg dst,
-struct brw_reg src)
+struct brw_reg src,
+struct brw_reg sampler_index)
 {
int msg_type = -1;
int rlen = 4;
@@ -238,6 +239,11 @@ gen8_fs_generator::generate_tex(fs_inst *ir,
   dst = vec16(dst);
}
 
+   assert(sampler_index.file == BRW_IMMEDIATE_VALUE);
+   assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
+
+   uint32_t sampler = sampler_index.dw1.ud;
+
if (ir->header_present) {
   /* The send-from-GRF for SIMD16 texturing with a header has an extra
* hardware register allocated to it, which we need to skip over (since
@@ -258,7 +264,7 @@ gen8_fs_generator::generate_tex(fs_inst *ir,
  brw_imm_ud(ir->texture_offset));
   }
 
-  if (ir->sampler >= 16) {
+  if (sampler >= 16) {
  /* The "Sampler Index" field can only store values between 0 and 15.
   * However, we can add an offset to the "Sampler State Pointer"
   * field, effectively selecting a different set of 16 samplers.
@@ -271,7 +277,7 @@ gen8_fs_generator::generate_tex(fs_inst *ir,
  gen8_instruction *add =
 ADD(get_element_ud(src, 3),
 get_element_ud(brw_vec8_grf(0, 0), 3),
-brw_imm_ud(16 * (ir->sampler / 16) * sampler_state_size));
+brw_imm_ud(16 * (sampler / 16) * sampler_state_size));
  gen8_set_mask_control(add, BRW_MASK_DISABLE);
   }
 
@@ -279,14 +285,14 @@ gen8_fs_generator::generate_tex(fs_inst *ir,
}
 
uint32_t surf_index =
-  prog_data->base.binding_table.texture_start + ir->sampler;
+  prog_data->base.binding_table.texture_start + sampler;
 
gen8_instruction *inst = next_inst(BRW_OPCODE_SEND);
gen8_set_dst(brw, inst, dst);
gen8_set_src0(brw, inst, src);
gen8_set_sampler_message(brw, inst,
 surf_index,
-ir->sampler % 16,
+sampler % 16,
 msg_type,
 rlen,
 ir->mlen,
@@ -1137,7 +1143,7 @@ gen8_fs_generator::generate_code(exec_list *instructions)
   case SHADER_OPCODE_LOD:
   case SHADER_OPCODE_TG4:
   case SHADER_OPCODE_TG4_OFFSET:
- generate_tex(ir, dst, src[0]);
+ generate_tex(ir, dst, src[0], src[1]);
  break;
 
   case FS_OPCODE_DDX:

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Mesa (master): i965/fs/Gen4-7: Pass sampler_index to generate_tex

[Chris Forbes]

Module: Mesa
Branch: master
Commit: ba5f7a361a14612dd39a8aeb6332f9db3205d675
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba5f7a361a14612dd39a8aeb6332f9db3205d675

Author: Chris Forbes 
Date:   Sun Aug  3 21:23:31 2014 +1200

i965/fs/Gen4-7: Pass sampler_index to generate_tex

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 
Reviewed-by: Ian Romanick 

---

 src/mesa/drivers/dri/i965/brw_fs.h |3 ++-
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp |   18 --
 2 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
b/src/mesa/drivers/dri/i965/brw_fs.h
index 47aebad..f3ce4e0 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -594,7 +594,8 @@ private:
void generate_pixel_xy(struct brw_reg dst, bool is_x);
void generate_linterp(fs_inst *inst, struct brw_reg dst,
 struct brw_reg *src);
-   void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
+   void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
+ struct brw_reg sampler_index);
void generate_math_gen6(fs_inst *inst,
struct brw_reg dst,
struct brw_reg src0,
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index ac2f1b4..cec2e82 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -368,7 +368,8 @@ fs_generator::generate_math_g45(fs_inst *inst,
 }
 
 void
-fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg 
src)
+fs_generator::generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg 
src,
+   struct brw_reg sampler_index)
 {
int msg_type = -1;
int rlen = 4;
@@ -536,6 +537,11 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg 
dst, struct brw_reg src
   src.nr++;
}
 
+   assert(sampler_index.file == BRW_IMMEDIATE_VALUE);
+   assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
+
+   uint32_t sampler = sampler_index.dw1.ud;
+
/* Load the message header if present.  If there's a texture offset,
 * we need to set it up explicitly and load the offset bitfield.
 * Otherwise, we can use an implied move from g0 to the first message reg.
@@ -566,7 +572,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg 
dst, struct brw_reg src
brw_imm_ud(inst->texture_offset));
  }
 
- if (inst->sampler >= 16) {
+ if (sampler >= 16) {
 /* The "Sampler Index" field can only store values between 0 and 
15.
  * However, we can add an offset to the "Sampler State Pointer"
  * field, effectively selecting a different set of 16 samplers.
@@ -580,7 +586,7 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg 
dst, struct brw_reg src
 brw_ADD(p,
 get_element_ud(header_reg, 3),
 get_element_ud(brw_vec8_grf(0, 0), 3),
-brw_imm_ud(16 * (inst->sampler / 16) * 
sampler_state_size));
+brw_imm_ud(16 * (sampler / 16) * sampler_state_size));
  }
  brw_pop_insn_state(p);
   }
@@ -589,14 +595,14 @@ fs_generator::generate_tex(fs_inst *inst, struct brw_reg 
dst, struct brw_reg src
uint32_t surface_index = ((inst->opcode == SHADER_OPCODE_TG4 ||
   inst->opcode == SHADER_OPCODE_TG4_OFFSET)
   ? prog_data->base.binding_table.gather_texture_start
-  : prog_data->base.binding_table.texture_start) + inst->sampler;
+  : prog_data->base.binding_table.texture_start) + sampler;
 
brw_SAMPLE(p,
  retype(dst, BRW_REGISTER_TYPE_UW),
  inst->base_mrf,
  src,
   surface_index,
- inst->sampler % 16,
+ sampler % 16,
  msg_type,
  rlen,
  inst->mlen,
@@ -1645,7 +1651,7 @@ fs_generator::generate_code(exec_list *instructions)
   case SHADER_OPCODE_LOD:
   case SHADER_OPCODE_TG4:
   case SHADER_OPCODE_TG4_OFFSET:
-generate_tex(inst, dst, src[0]);
+generate_tex(inst, dst, src[0], src[1]);
 break;
   case FS_OPCODE_DDX:
 generate_ddx(inst, dst, src[0]);

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Mesa (master): i965/vec4/Gen8: Use src1 for sampler_index instead of -> sampler field

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 298da9fa2adba3f0f4c89220c696684937016f7c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=298da9fa2adba3f0f4c89220c696684937016f7c

Author: Chris Forbes 
Date:   Mon Aug  4 19:41:03 2014 +1200

i965/vec4/Gen8: Use src1 for sampler_index instead of ->sampler field

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 
Reviewed-by: Ian Romanick 

---

 src/mesa/drivers/dri/i965/brw_vec4.h  |3 ++-
 src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp |   19 +--
 2 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h 
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 7c2721d..9001286 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -727,7 +727,8 @@ private:
   struct brw_reg *src);
 
void generate_tex(vec4_instruction *inst,
- struct brw_reg dst);
+ struct brw_reg dst,
+ struct brw_reg sampler_index);
 
void generate_urb_write(vec4_instruction *ir, bool copy_g0);
void generate_gs_thread_end(vec4_instruction *ir);
diff --git a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp 
b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
index ee8e85e..6951f88 100644
--- a/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/gen8_vec4_generator.cpp
@@ -50,7 +50,8 @@ gen8_vec4_generator::~gen8_vec4_generator()
 }
 
 void
-gen8_vec4_generator::generate_tex(vec4_instruction *ir, struct brw_reg dst)
+gen8_vec4_generator::generate_tex(vec4_instruction *ir, struct brw_reg dst,
+  struct brw_reg sampler_index)
 {
int msg_type = 0;
 
@@ -100,6 +101,11 @@ gen8_vec4_generator::generate_tex(vec4_instruction *ir, 
struct brw_reg dst)
   unreachable("should not get here: invalid VS texture opcode");
}
 
+   assert(sampler_index.file == BRW_IMMEDIATE_VALUE);
+   assert(sampler_index.type == BRW_REGISTER_TYPE_UD);
+
+   uint32_t sampler = sampler_index.dw1.ud;
+
if (ir->header_present) {
   MOV_RAW(retype(brw_message_reg(ir->base_mrf), BRW_REGISTER_TYPE_UD),
   retype(brw_vec8_grf(0, 0), BRW_REGISTER_TYPE_UD));
@@ -113,7 +119,7 @@ gen8_vec4_generator::generate_tex(vec4_instruction *ir, 
struct brw_reg dst)
  brw_imm_ud(ir->texture_offset));
   }
 
-  if (ir->sampler >= 16) {
+  if (sampler >= 16) {
  /* The "Sampler Index" field can only store values between 0 and 15.
   * However, we can add an offset to the "Sampler State Pointer"
   * field, effectively selecting a different set of 16 samplers.
@@ -126,7 +132,7 @@ gen8_vec4_generator::generate_tex(vec4_instruction *ir, 
struct brw_reg dst)
  gen8_instruction *add =
 ADD(get_element_ud(brw_message_reg(ir->base_mrf), 3),
 get_element_ud(brw_vec8_grf(0, 0), 3),
-brw_imm_ud(16 * (ir->sampler / 16) * sampler_state_size));
+brw_imm_ud(16 * (sampler / 16) * sampler_state_size));
  gen8_set_mask_control(add, BRW_MASK_DISABLE);
   }
 
@@ -134,14 +140,14 @@ gen8_vec4_generator::generate_tex(vec4_instruction *ir, 
struct brw_reg dst)
}
 
uint32_t surf_index =
-  prog_data->base.binding_table.texture_start + ir->sampler;
+  prog_data->base.binding_table.texture_start + sampler;
 
gen8_instruction *inst = next_inst(BRW_OPCODE_SEND);
gen8_set_dst(brw, inst, dst);
gen8_set_src0(brw, inst, brw_message_reg(ir->base_mrf));
gen8_set_sampler_message(brw, inst,
 surf_index,
-ir->sampler % 16,
+sampler % 16,
 msg_type,
 1,
 ir->mlen,
@@ -765,7 +771,8 @@ 
gen8_vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
case SHADER_OPCODE_TXS:
case SHADER_OPCODE_TG4:
case SHADER_OPCODE_TG4_OFFSET:
-  generate_tex(ir, dst);
+  /* note: src[0] is unused. */
+  generate_tex(ir, dst, src[1]);
   break;
 
case VS_OPCODE_URB_WRITE:

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Mesa (master): i965: Get rid of backend_instruction::sampler

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 0f4c5a70c6e759e3a7bddd7f1c2d2b8d219552a4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0f4c5a70c6e759e3a7bddd7f1c2d2b8d219552a4

Author: Chris Forbes 
Date:   Sun Aug  3 21:40:00 2014 +1200

i965: Get rid of backend_instruction::sampler

The generators no longer use this.

Signed-off-by: Chris Forbes 
Reviewed-by: Matt Turner 
Reviewed-by: Ian Romanick 

---

 src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp |1 -
 src/mesa/drivers/dri/i965/brw_fs.cpp|1 -
 src/mesa/drivers/dri/i965/brw_fs_cse.cpp|1 -
 src/mesa/drivers/dri/i965/brw_fs_fp.cpp |1 -
 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp|3 ---
 src/mesa/drivers/dri/i965/brw_shader.h  |1 -
 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp  |3 ---
 7 files changed, 11 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp 
b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
index acaf92b..5a485df 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp
@@ -83,7 +83,6 @@ brw_blorp_eu_emitter::emit_texture_lookup(const struct 
brw_reg &dst,
 
inst->base_mrf = base_mrf;
inst->mlen = msg_length;
-   inst->sampler = 0;
inst->header_present = false;
 
insts.push_tail(inst);
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 13ef6dd..bf95b57 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -348,7 +348,6 @@ fs_inst::equals(fs_inst *inst) const
conditional_mod == inst->conditional_mod &&
mlen == inst->mlen &&
base_mrf == inst->base_mrf &&
-   sampler == inst->sampler &&
target == inst->target &&
eot == inst->eot &&
header_present == inst->header_present &&
diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
index 63d87f9..01790ad 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
@@ -157,7 +157,6 @@ instructions_match(fs_inst *a, fs_inst *b)
   a->mlen == b->mlen &&
   a->regs_written == b->regs_written &&
   a->base_mrf == b->base_mrf &&
-  a->sampler == b->sampler &&
   a->eot == b->eot &&
   a->header_present == b->header_present &&
   a->shadow_compare == b->shadow_compare)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
index 35c056f..8d07be2 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
@@ -498,7 +498,6 @@ fs_visitor::emit_fragment_program_code()
 inst = emit_texture_gen4(ir, dst, coordinate, shadow_c, lod, dpdy, 
fpi->TexSrcUnit);
  }
 
- inst->sampler = fpi->TexSrcUnit;
  inst->shadow_compare = fpi->TexShadow;
 
  /* Reuse the GLSL swizzle_result() handler. */
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 534c652..4701e61 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -1745,7 +1745,6 @@ fs_visitor::emit_mcs_fetch(ir_texture *ir, fs_reg 
coordinate, uint32_t sampler)
inst->regs_written = 4; /* we only care about one reg of response,
 * but the sampler always writes 4/8
 */
-   inst->sampler = sampler;
 
return dest;
 }
@@ -1867,8 +1866,6 @@ fs_visitor::visit(ir_texture *ir)
if (ir->op == ir_tg4)
   inst->texture_offset |= gather_channel(ir, sampler) << 16; // M0.2:16-17
 
-   inst->sampler = sampler;
-
if (ir->shadow_comparitor)
   inst->shadow_compare = true;
 
diff --git a/src/mesa/drivers/dri/i965/brw_shader.h 
b/src/mesa/drivers/dri/i965/brw_shader.h
index 5c48671..5980cf0 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.h
+++ b/src/mesa/drivers/dri/i965/brw_shader.h
@@ -108,7 +108,6 @@ struct backend_instruction {
 
uint32_t texture_offset; /**< Texture offset bitfield */
uint32_t offset; /**< spill/unspill offset */
-   uint8_t sampler;
uint8_t mlen; /**< SEND message length */
int8_t base_mrf; /**< First MRF in the SEND message, if mlen is nonzero. */
uint8_t target; /**< MRT target. */
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index a47c3a6..1b46850 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/b

Mesa (master): define GL_OES_standard_derivatives if extension is supported

[Chris Forbes]

Module: Mesa
Branch: master
Commit: e41cc453619c7bef7871b78a631a0eb22e3a762d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e41cc453619c7bef7871b78a631a0eb22e3a762d

Author: Kevin Rogovin 
Date:   Mon May 19 10:52:44 2014 +0300

define GL_OES_standard_derivatives if extension is supported

Define the macro GL_OES_standard_derivatives as 1 if the extension
GL_OES_standard_derivatives is supported.

V2 [Chris]: Correct trailing whitespace

Reviewed-by: Chris Forbes 

---

 src/glsl/glcpp/glcpp-parse.y |2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y
index 4ee4110..e2e8aca 100644
--- a/src/glsl/glcpp/glcpp-parse.y
+++ b/src/glsl/glcpp/glcpp-parse.y
@@ -2232,6 +2232,8 @@ _glcpp_parser_handle_version_declaration(glcpp_parser_t 
*parser, intmax_t versio
   if (extensions != NULL) {
  if (extensions->OES_EGL_image_external)
 add_builtin_define(parser, "GL_OES_EGL_image_external", 1);
+  if (extensions->OES_standard_derivatives)
+ add_builtin_define(parser, "GL_OES_standard_derivatives", 1);
   }
} else {
   add_builtin_define(parser, "GL_ARB_draw_buffers", 1);

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Mesa (master): glsl: Accept nonconstant array references in lower_ubo_reference

[Chris Forbes]

Module: Mesa
Branch: master
Commit: be237a61297936227b2f4afc2ac28f60c3c76bbf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=be237a61297936227b2f4afc2ac28f60c3c76bbf

Author: Chris Forbes 
Date:   Fri May 16 22:07:24 2014 +1200

glsl: Accept nonconstant array references in lower_ubo_reference

Instead of falling back to just the block name (which we won't find),
look for the first element of the block array. We'll deal with the rest
in the backend by arranging for the blocks to be laid out contiguously.

V2: Squashed together patches 3, 5 of V1, plus a naming tweak.

Signed-off-by: Chris Forbes 
Reviewed-by: Ilia Mirkin 
Reviewed-by: Kenneth Graunke 

---

 src/glsl/lower_ubo_reference.cpp |   43 --
 1 file changed, 32 insertions(+), 11 deletions(-)

diff --git a/src/glsl/lower_ubo_reference.cpp b/src/glsl/lower_ubo_reference.cpp
index 9729ea0..67b752d 100644
--- a/src/glsl/lower_ubo_reference.cpp
+++ b/src/glsl/lower_ubo_reference.cpp
@@ -69,9 +69,11 @@ public:
  * \c UniformBlocks array.
  */
 static const char *
-interface_field_name(void *mem_ctx, char *base_name, ir_dereference *d)
+interface_field_name(void *mem_ctx, char *base_name, ir_dereference *d,
+ ir_rvalue **nonconst_block_index)
 {
-   ir_constant *previous_index = NULL;
+   ir_rvalue *previous_index = NULL;
+   *nonconst_block_index = NULL;
 
while (d != NULL) {
   switch (d->ir_type) {
@@ -79,13 +81,21 @@ interface_field_name(void *mem_ctx, char *base_name, 
ir_dereference *d)
  ir_dereference_variable *v = (ir_dereference_variable *) d;
  if (previous_index
  && v->var->is_interface_instance()
- && v->var->type->is_array())
-return ralloc_asprintf(mem_ctx,
-   "%s[%d]",
-   base_name,
-   previous_index->get_uint_component(0));
- else
+ && v->var->type->is_array()) {
+
+ir_constant *const_index = previous_index->as_constant();
+if (!const_index) {
+   *nonconst_block_index = previous_index;
+   return ralloc_asprintf(mem_ctx, "%s[0]", base_name);
+} else {
+   return ralloc_asprintf(mem_ctx,
+  "%s[%d]",
+  base_name,
+  const_index->get_uint_component(0));
+}
+ } else {
 return base_name;
+ }
 
  break;
   }
@@ -101,7 +111,8 @@ interface_field_name(void *mem_ctx, char *base_name, 
ir_dereference *d)
  ir_dereference_array *a = (ir_dereference_array *) d;
 
  d = a->array->as_dereference();
- previous_index = a->array_index->as_constant();
+ previous_index = a->array_index;
+
  break;
   }
 
@@ -131,14 +142,24 @@ lower_ubo_reference_visitor::handle_rvalue(ir_rvalue 
**rvalue)
 
mem_ctx = ralloc_parent(*rvalue);
 
+   ir_rvalue *nonconst_block_index;
const char *const field_name =
   interface_field_name(mem_ctx, (char *) var->get_interface_type()->name,
-   deref);
+   deref, &nonconst_block_index);
 
this->uniform_block = NULL;
for (unsigned i = 0; i < shader->NumUniformBlocks; i++) {
   if (strcmp(field_name, shader->UniformBlocks[i].Name) == 0) {
- this->uniform_block = new(mem_ctx) ir_constant(i);
+
+ ir_constant *index = new(mem_ctx) ir_constant(i);
+
+ if (nonconst_block_index) {
+if (nonconst_block_index->type != glsl_type::uint_type)
+   nonconst_block_index = i2u(nonconst_block_index);
+this->uniform_block = add(nonconst_block_index, index);
+ } else {
+this->uniform_block = index;
+ }
 
  struct gl_uniform_block *block = &shader->UniformBlocks[i];
 

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Mesa (master): glsl: No longer require ubo block index to be constant in ir_validate

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 74e100affc0ac1bced4787067274579d8f0d137f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=74e100affc0ac1bced4787067274579d8f0d137f

Author: Chris Forbes 
Date:   Sun May 18 12:19:04 2014 +1200

glsl: No longer require ubo block index to be constant in ir_validate

Signed-off-by: Chris Forbes 
Reviewed-by: Ilia Mirkin 
Reviewed-by: Kenneth Graunke 

---

 src/glsl/ir_validate.cpp |1 -
 1 file changed, 1 deletion(-)

diff --git a/src/glsl/ir_validate.cpp b/src/glsl/ir_validate.cpp
index 37e1ce3..4f85b7d 100644
--- a/src/glsl/ir_validate.cpp
+++ b/src/glsl/ir_validate.cpp
@@ -495,7 +495,6 @@ ir_validate::visit_leave(ir_expression *ir)
   break;
 
case ir_binop_ubo_load:
-  assert(ir->operands[0]->as_constant());
   assert(ir->operands[0]->type == glsl_type::uint_type);
 
   assert(ir->operands[1]->type == glsl_type::uint_type);

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Mesa (master): glsl: Allow non-constant UBO array indexing with GLSL4/ ARB_gpu_shader5.

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 8eae5ceb99b71854db566e18222f400641c23f39
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8eae5ceb99b71854db566e18222f400641c23f39

Author: Chris Forbes 
Date:   Fri May 16 21:10:18 2014 +1200

glsl: Allow non-constant UBO array indexing with GLSL4/ARB_gpu_shader5.

Signed-off-by: Chris Forbes 
Reviewed-by: Ilia Mirkin 
Reviewed-by: Kenneth Graunke 

---

 src/glsl/ast_array_index.cpp |3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/glsl/ast_array_index.cpp b/src/glsl/ast_array_index.cpp
index f3b060e..50f9987 100644
--- a/src/glsl/ast_array_index.cpp
+++ b/src/glsl/ast_array_index.cpp
@@ -181,7 +181,8 @@ _mesa_ast_array_index_to_hir(void *mem_ctx,
   if (array->type->is_unsized_array()) {
 _mesa_glsl_error(&loc, state, "unsized array index must be constant");
   } else if (array->type->fields.array->is_interface()
- && array->variable_referenced()->data.mode == ir_var_uniform) 
{
+ && array->variable_referenced()->data.mode == ir_var_uniform
+ && !state->is_version(400, 0) && 
!state->ARB_gpu_shader5_enable) {
 /* Page 46 in section 4.3.7 of the OpenGL ES 3.00 spec says:
  *
  * "All indexes used to index a uniform block array must be

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Mesa (master): glsl: Mark entire UBO array active if indexed with non-constant.

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 9c90a633786ab8e204c118ec92015eb3ae194349
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9c90a633786ab8e204c118ec92015eb3ae194349

Author: Chris Forbes 
Date:   Fri May 16 21:28:09 2014 +1200

glsl: Mark entire UBO array active if indexed with non-constant.

Without doing a lot more work, we have no idea which indices may
be used at runtime, so just mark them all.

Signed-off-by: Chris Forbes 
Reviewed-by: Ilia Mirkin 
Reviewed-by: Kenneth Graunke 

---

 src/glsl/link_uniform_block_active_visitor.cpp |   50 +++-
 1 file changed, 31 insertions(+), 19 deletions(-)

diff --git a/src/glsl/link_uniform_block_active_visitor.cpp 
b/src/glsl/link_uniform_block_active_visitor.cpp
index d19ce20..854309f 100644
--- a/src/glsl/link_uniform_block_active_visitor.cpp
+++ b/src/glsl/link_uniform_block_active_visitor.cpp
@@ -109,32 +109,44 @@ 
link_uniform_block_active_visitor::visit_enter(ir_dereference_array *ir)
assert((b->num_array_elements == 0) == (b->array_elements == NULL));
assert(b->type != NULL);
 
-   /* Determine whether or not this array index has already been added to the
-* list of active array indices.  At this point all constant folding must
-* have occured, and the array index must be a constant.
-*/
ir_constant *c = ir->array_index->as_constant();
-   assert(c != NULL);
 
-   const unsigned idx = c->get_uint_component(0);
+   if (c) {
+  /* Index is a constant, so mark just that element used, if not already */
+  const unsigned idx = c->get_uint_component(0);
 
-   unsigned i;
-   for (i = 0; i < b->num_array_elements; i++) {
-  if (b->array_elements[i] == idx)
-break;
-   }
+  unsigned i;
+  for (i = 0; i < b->num_array_elements; i++) {
+ if (b->array_elements[i] == idx)
+break;
+  }
 
-   assert(i <= b->num_array_elements);
+  assert(i <= b->num_array_elements);
 
-   if (i == b->num_array_elements) {
-  b->array_elements = reralloc(this->mem_ctx,
-  b->array_elements,
-  unsigned,
-  b->num_array_elements + 1);
+  if (i == b->num_array_elements) {
+ b->array_elements = reralloc(this->mem_ctx,
+  b->array_elements,
+  unsigned,
+  b->num_array_elements + 1);
 
-  b->array_elements[b->num_array_elements] = idx;
+ b->array_elements[b->num_array_elements] = idx;
 
-  b->num_array_elements++;
+ b->num_array_elements++;
+  }
+   } else {
+  /* The array index is not a constant, so mark the entire array used. */
+  assert(b->type->is_array());
+  if (b->num_array_elements < b->type->length) {
+ b->num_array_elements = b->type->length;
+ b->array_elements = reralloc(this->mem_ctx,
+  b->array_elements,
+  unsigned,
+  b->num_array_elements);
+
+ for (unsigned i = 0; i < b->num_array_elements; i++) {
+b->array_elements[i] = i;
+ }
+  }
}
 
return visit_continue_with_parent;

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Mesa (master): glsl: Convert uniform_block in lower_ubo_reference to ir_rvalue.

[Chris Forbes]

Module: Mesa
Branch: master
Commit: c59802d3a147956d4f33586bb6221cd236987ee2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c59802d3a147956d4f33586bb6221cd236987ee2

Author: Chris Forbes 
Date:   Sun May 18 12:03:54 2014 +1200

glsl: Convert uniform_block in lower_ubo_reference to ir_rvalue.

Previously this was a block index with special semantics for -1.
With ARB_gpu_shader5, this need not be a compile-time constant, so
allow any rvalue here and convert the -1 to a NULL pointer.

Signed-off-by: Chris Forbes 
Reviewed-by: Ilia Mirkin 
Reviewed-by: Kenneth Graunke 

---

 src/glsl/lower_ubo_reference.cpp |   15 ---
 1 file changed, 8 insertions(+), 7 deletions(-)

diff --git a/src/glsl/lower_ubo_reference.cpp b/src/glsl/lower_ubo_reference.cpp
index 90e65bd..9729ea0 100644
--- a/src/glsl/lower_ubo_reference.cpp
+++ b/src/glsl/lower_ubo_reference.cpp
@@ -57,7 +57,7 @@ public:
void *mem_ctx;
struct gl_shader *shader;
struct gl_uniform_buffer_variable *ubo_var;
-   unsigned uniform_block;
+   ir_rvalue *uniform_block;
bool progress;
 };
 
@@ -135,10 +135,10 @@ lower_ubo_reference_visitor::handle_rvalue(ir_rvalue 
**rvalue)
   interface_field_name(mem_ctx, (char *) var->get_interface_type()->name,
deref);
 
-   this->uniform_block = -1;
+   this->uniform_block = NULL;
for (unsigned i = 0; i < shader->NumUniformBlocks; i++) {
   if (strcmp(field_name, shader->UniformBlocks[i].Name) == 0) {
- this->uniform_block = i;
+ this->uniform_block = new(mem_ctx) ir_constant(i);
 
  struct gl_uniform_block *block = &shader->UniformBlocks[i];
 
@@ -149,7 +149,7 @@ lower_ubo_reference_visitor::handle_rvalue(ir_rvalue 
**rvalue)
   }
}
 
-   assert(this->uniform_block != (unsigned) -1);
+   assert(this->uniform_block);
 
ir_rvalue *offset = new(mem_ctx) ir_constant(0u);
unsigned const_offset = 0;
@@ -267,11 +267,12 @@ ir_expression *
 lower_ubo_reference_visitor::ubo_load(const glsl_type *type,
  ir_rvalue *offset)
 {
+   ir_rvalue *block_ref = this->uniform_block->clone(mem_ctx, NULL);
return new(mem_ctx)
   ir_expression(ir_binop_ubo_load,
-   type,
-   new(mem_ctx) ir_constant(this->uniform_block),
-   offset);
+type,
+block_ref,
+offset);
 
 }
 

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Mesa (master): mesa: Fix regression introduced by commit "mesa: fix packing of float texels to GL_SHORT/GL_BYTE".

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 4ceb612a10d7776631b196ae13be9c5588154468
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4ceb612a10d7776631b196ae13be9c5588154468

Author: Pavel Popov 
Date:   Mon Jun 30 22:21:56 2014 +0700

mesa: Fix regression introduced by commit "mesa: fix packing of float texels to 
GL_SHORT/GL_BYTE".

This commit "mesa: fix packing of float texels to GL_SHORT/GL_BYTE" replaced 
*_TO_BYTE to *_TO_BYTE_TEX because *_TO_FLOAT_TEX are used to unpack the texels 
to floats.
In this case *_TO_FLOATZ in function extract_float_rgba also should be replaced 
to *_TO_FLOAT_TEX. Underline that these macros automatically preserve zero when 
converting.

The regression was observed on 3 oglconform tests:
snorm-textures basic.getTexImage
snorm-textures advanced.mipmap.manual.getTex
snorm-textures advanced.mipmap.upload.getTex

Signed-off-by: Pavel Popov 
Reviewed-by: Chris Forbes 

---

 src/mesa/main/pack.c |   16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mesa/main/pack.c b/src/mesa/main/pack.c
index 5ebaaf6..649a74c 100644
--- a/src/mesa/main/pack.c
+++ b/src/mesa/main/pack.c
@@ -3183,10 +3183,10 @@ extract_float_rgba(GLuint n, GLfloat rgba[][4],
  PROCESS(aSrc, ACOMP, 1.0F, 255, GLubyte, UBYTE_TO_FLOAT);
  break;
   case GL_BYTE:
- PROCESS(rSrc, RCOMP, 0.0F,   0, GLbyte, BYTE_TO_FLOATZ);
- PROCESS(gSrc, GCOMP, 0.0F,   0, GLbyte, BYTE_TO_FLOATZ);
- PROCESS(bSrc, BCOMP, 0.0F,   0, GLbyte, BYTE_TO_FLOATZ);
- PROCESS(aSrc, ACOMP, 1.0F, 127, GLbyte, BYTE_TO_FLOATZ);
+ PROCESS(rSrc, RCOMP, 0.0F,   0, GLbyte, BYTE_TO_FLOAT_TEX);
+ PROCESS(gSrc, GCOMP, 0.0F,   0, GLbyte, BYTE_TO_FLOAT_TEX);
+ PROCESS(bSrc, BCOMP, 0.0F,   0, GLbyte, BYTE_TO_FLOAT_TEX);
+ PROCESS(aSrc, ACOMP, 1.0F, 127, GLbyte, BYTE_TO_FLOAT_TEX);
  break;
   case GL_UNSIGNED_SHORT:
  PROCESS(rSrc, RCOMP, 0.0F,  0, GLushort, USHORT_TO_FLOAT);
@@ -3195,10 +3195,10 @@ extract_float_rgba(GLuint n, GLfloat rgba[][4],
  PROCESS(aSrc, ACOMP, 1.0F, 0x, GLushort, USHORT_TO_FLOAT);
  break;
   case GL_SHORT:
- PROCESS(rSrc, RCOMP, 0.0F, 0, GLshort, SHORT_TO_FLOATZ);
- PROCESS(gSrc, GCOMP, 0.0F, 0, GLshort, SHORT_TO_FLOATZ);
- PROCESS(bSrc, BCOMP, 0.0F, 0, GLshort, SHORT_TO_FLOATZ);
- PROCESS(aSrc, ACOMP, 1.0F, 32767, GLshort, SHORT_TO_FLOATZ);
+ PROCESS(rSrc, RCOMP, 0.0F, 0, GLshort, SHORT_TO_FLOAT_TEX);
+ PROCESS(gSrc, GCOMP, 0.0F, 0, GLshort, SHORT_TO_FLOAT_TEX);
+ PROCESS(bSrc, BCOMP, 0.0F, 0, GLshort, SHORT_TO_FLOAT_TEX);
+ PROCESS(aSrc, ACOMP, 1.0F, 32767, GLshort, SHORT_TO_FLOAT_TEX);
  break;
   case GL_UNSIGNED_INT:
  PROCESS(rSrc, RCOMP, 0.0F,  0, GLuint, UINT_TO_FLOAT);

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Mesa (master): i965/vec4: Silence warnings about unhandled interpolation ops

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 5899a45a5bc0d05be6895970234e49ca70984aee
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5899a45a5bc0d05be6895970234e49ca70984aee

Author: Chris Forbes 
Date:   Sun Jul 13 11:13:18 2014 +1200

i965/vec4: Silence warnings about unhandled interpolation ops

Signed-off-by: Chris Forbes 

---

 src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 65eb2da..e16e93c 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -1768,6 +1768,9 @@ vec4_visitor::visit(ir_expression *ir)
case ir_unop_unpack_half_2x16_split_x:
case ir_unop_unpack_half_2x16_split_y:
case ir_binop_pack_half_2x16_split:
+   case ir_unop_interpolate_at_centroid:
+   case ir_binop_interpolate_at_sample:
+   case ir_binop_interpolate_at_offset:
   unreachable("not reached: should not occur in vertex shader");
case ir_binop_ldexp:
   unreachable("not reached: should be handled by ldexp_to_arith()");

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Mesa (master): docs: Mark off ARB_gpu_shader5 interpolation functions for i965

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 1e4068ca4539b405995a8a39e6245a188d9d61ac
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e4068ca4539b405995a8a39e6245a188d9d61ac

Author: Chris Forbes 
Date:   Sun Jul 13 10:04:25 2014 +1200

docs: Mark off ARB_gpu_shader5 interpolation functions for i965

Signed-off-by: Chris Forbes 

---

 docs/GL3.txt |2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/GL3.txt b/docs/GL3.txt
index 296e14c..a2f438b 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -110,7 +110,7 @@ GL 4.0:
   - Geometry shader instancing DONE (i965, nvc0)
   - Geometry shader multiple streams   DONE (i965, nvc0)
   - Enhanced per-sample shadingDONE (i965)
-  - Interpolation functionsstarted (Chris)
+  - Interpolation functionsDONE (i965)
   - New overload resolution rules  DONE
   GL_ARB_gpu_shader_fp64   started (Dave)
   GL_ARB_sample_shadingDONE (i965, nv50, nvc0, 
radeonsi)

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Mesa (master): i965/fs: Skip channel expressions splitting for interpolation

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 5ed147c26f800ffb11fb80b92aec9a772982aff6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ed147c26f800ffb11fb80b92aec9a772982aff6

Author: Chris Forbes 
Date:   Sun Nov 17 20:07:46 2013 +1300

i965/fs: Skip channel expressions splitting for interpolation

The backend will have to do a message send, so we want to keep these in
one piece, just like texture ops.

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 .../dri/i965/brw_fs_channel_expressions.cpp|   25 
 1 file changed, 25 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
index 9fe0ffc..4113f47 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
@@ -75,6 +75,18 @@ channel_expressions_predicate(ir_instruction *ir)
if (!expr)
   return false;
 
+   switch (expr->operation) {
+  /* these opcodes need to act on the whole vector,
+   * just like texturing.
+   */
+  case ir_unop_interpolate_at_centroid:
+  case ir_binop_interpolate_at_offset:
+  case ir_binop_interpolate_at_sample:
+ return false;
+  default:
+ break;
+   }
+
for (i = 0; i < expr->get_num_operands(); i++) {
   if (expr->operands[i]->type->is_vector())
 return true;
@@ -153,6 +165,16 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment 
*ir)
if (!found_vector)
   return visit_continue;
 
+   switch (expr->operation) {
+  case ir_unop_interpolate_at_centroid:
+  case ir_binop_interpolate_at_offset:
+  case ir_binop_interpolate_at_sample:
+ return visit_continue;
+
+  default:
+ break;
+   }
+
/* Store the expression operands in temps so we can use them
 * multiple times.
 */
@@ -414,6 +436,9 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment 
*ir)
case ir_unop_unpack_half_2x16_split_x:
case ir_unop_unpack_half_2x16_split_y:
case ir_binop_pack_half_2x16_split:
+   case ir_unop_interpolate_at_centroid:
+   case ir_binop_interpolate_at_offset:
+   case ir_binop_interpolate_at_sample:
   unreachable("not reached: expression operates on scalars only");
}
 

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Mesa (master): i965/fs: add generator support for pixel interpolator query

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 6e91f2df958c835a1973e32d71578fa295ef00a8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e91f2df958c835a1973e32d71578fa295ef00a8

Author: Chris Forbes 
Date:   Mon Nov 18 21:13:13 2013 +1300

i965/fs: add generator support for pixel interpolator query

V5: - Split into separate opcodes
- Pass message data in src1 immediate
- Put noperspective bit in fs_inst rather than adding any junk to
  backend_instruction

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_defines.h|4 +++
 src/mesa/drivers/dri/i965/brw_fs.cpp   |8 +
 src/mesa/drivers/dri/i965/brw_fs.h |7 +
 src/mesa/drivers/dri/i965/brw_fs_generator.cpp |   40 
 4 files changed, 59 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index e528232..8b73c5c 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -853,6 +853,10 @@ enum opcode {
FS_OPCODE_UNPACK_HALF_2x16_SPLIT_X,
FS_OPCODE_UNPACK_HALF_2x16_SPLIT_Y,
FS_OPCODE_PLACEHOLDER_HALT,
+   FS_OPCODE_INTERPOLATE_AT_CENTROID,
+   FS_OPCODE_INTERPOLATE_AT_SAMPLE,
+   FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET,
+   FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET,
 
VS_OPCODE_URB_WRITE,
VS_OPCODE_PULL_CONSTANT_LOAD,
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp 
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index a3ad375..951d69f 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -370,6 +370,10 @@ fs_inst::is_send_from_grf() const
 {
return (opcode == FS_OPCODE_VARYING_PULL_CONSTANT_LOAD_GEN7 ||
opcode == SHADER_OPCODE_SHADER_TIME_ADD ||
+   opcode == FS_OPCODE_INTERPOLATE_AT_CENTROID ||
+   opcode == FS_OPCODE_INTERPOLATE_AT_SAMPLE ||
+   opcode == FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET ||
+   opcode == FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET ||
(opcode == FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD &&
 src[1].file == GRF) ||
(is_tex() && src[0].file == GRF));
@@ -837,6 +841,10 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
   return 2;
case SHADER_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
+   case FS_OPCODE_INTERPOLATE_AT_CENTROID:
+   case FS_OPCODE_INTERPOLATE_AT_SAMPLE:
+   case FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET:
+   case FS_OPCODE_INTERPOLATE_AT_PER_SLOT_OFFSET:
   return 0;
default:
   unreachable("not reached");
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
b/src/mesa/drivers/dri/i965/brw_fs.h
index 537f10e..1d3f9d0 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -196,6 +196,7 @@ public:
bool shadow_compare:1;
bool force_uncompressed:1;
bool force_sechalf:1;
+   bool pi_noperspective:1;   /**< Pixel interpolator noperspective flag */
 };
 
 /**
@@ -623,6 +624,12 @@ private:
  struct brw_reg offset);
void generate_mov_dispatch_to_flags(fs_inst *inst);
 
+   void generate_pixel_interpolator_query(fs_inst *inst,
+  struct brw_reg dst,
+  struct brw_reg src,
+  struct brw_reg msg_data,
+  unsigned msg_type);
+
void generate_set_omask(fs_inst *inst,
struct brw_reg dst,
struct brw_reg sample_mask);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index eae55f0..8e4a31d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -995,6 +995,26 @@ fs_generator::generate_mov_dispatch_to_flags(fs_inst *inst)
brw_pop_insn_state(p);
 }
 
+void
+fs_generator::generate_pixel_interpolator_query(fs_inst *inst,
+struct brw_reg dst,
+struct brw_reg src,
+struct brw_reg msg_data,
+unsigned msg_type)
+{
+   assert(msg_data.file == BRW_IMMEDIATE_VALUE &&
+  msg_data.type == BRW_REGISTER_TYPE_UD);
+
+   brw_pixel_interpolator_query(p,
+ retype(dst, BRW_REGISTER_TYPE_UW),
+ src,
+ inst->pi_noperspective,
+ msg_type,
+ msg_data.dw1.ud,
+ inst->mlen,
+ inst->regs_written);
+}
+
 
 static uint32_t brw_file_from_reg(fs_reg *reg)
 {
@@ -1730,6 +1750,26 @@ fs_generator::generate_code(exec_list *instructions)
  }
  break;
 
+  case FS_OPCODE_INTERPOLATE_AT_CENTROID:
+ generate_pix

Mesa (master): i965/fs: add support for ir_*_interpolate_at_* expressions

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 9c0bddf73525677acaf2b136cf54375a6ac2c2b9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9c0bddf73525677acaf2b136cf54375a6ac2c2b9

Author: Chris Forbes 
Date:   Sun Nov 17 20:00:00 2013 +1300

i965/fs: add support for ir_*_interpolate_at_* expressions

SIMD8-only for now.

V5: - Fix style complaints
- Move prototype to be with other oddball emit functions
- Use unreachable() instead of assert() where possible

V6: - Describe what is happening with the clamping
- Add reg_width to make some expressions clearer

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_fs.h   |2 +
 src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |  150 +-
 2 files changed, 150 insertions(+), 2 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_fs.h 
b/src/mesa/drivers/dri/i965/brw_fs.h
index 1d3f9d0..6f169dc 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -439,6 +439,8 @@ public:
void emit_untyped_surface_read(unsigned surf_index, fs_reg dst,
   fs_reg offset);
 
+   void emit_interpolate_expression(ir_expression *ir);
+
bool try_rewrite_rhs_to_dst(ir_assignment *ir,
   fs_reg dst,
   fs_reg src,
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp 
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 8e8affa..90bf3fa 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -344,6 +344,133 @@ fs_visitor::try_emit_mad(ir_expression *ir)
return true;
 }
 
+static int
+pack_pixel_offset(float x)
+{
+   /* Clamp upper end of the range to +7/16. See explanation in non-constant
+* offset case below. */
+   int n = MIN2((int)(x * 16), 7);
+   return n & 0xf;
+}
+
+void
+fs_visitor::emit_interpolate_expression(ir_expression *ir)
+{
+   /* in SIMD16 mode, the pixel interpolator returns coords interleaved
+* 8 channels at a time, same as the barycentric coords presented in
+* the FS payload. this requires a bit of extra work to support.
+*/
+   no16("interpolate_at_* not yet supported in SIMD16 mode.");
+
+   ir_dereference * deref = ir->operands[0]->as_dereference();
+   ir_swizzle * swiz = NULL;
+   if (!deref) {
+  /* the api does not allow a swizzle here, but the varying packing code
+   * may have pushed one into here.
+   */
+  swiz = ir->operands[0]->as_swizzle();
+  assert(swiz);
+  deref = swiz->val->as_dereference();
+   }
+   assert(deref);
+   ir_variable * var = deref->variable_referenced();
+   assert(var);
+
+   /* 1. collect interpolation factors */
+
+   fs_reg dst_x = fs_reg(this, glsl_type::get_instance(ir->type->base_type, 2, 
1));
+   fs_reg dst_y = dst_x;
+   dst_y.reg_offset++;
+
+   /* for most messages, we need one reg of ignored data; the hardware 
requires mlen==1
+* even when there is no payload. in the per-slot offset case, we'll 
replace this with
+* the proper source data. */
+   fs_reg src = fs_reg(this, glsl_type::float_type);
+   int mlen = 1; /* one reg unless overriden */
+   int reg_width = dispatch_width / 8;
+   fs_inst *inst;
+
+   switch (ir->operation) {
+   case ir_unop_interpolate_at_centroid:
+  inst = emit(FS_OPCODE_INTERPOLATE_AT_CENTROID, dst_x, src, fs_reg(0u));
+  break;
+
+   case ir_binop_interpolate_at_sample: {
+  ir_constant *sample_num = ir->operands[1]->as_constant();
+  assert(sample_num || !"nonconstant sample number should have been 
lowered.");
+
+  unsigned msg_data = sample_num->value.i[0] << 4;
+  inst = emit(FS_OPCODE_INTERPOLATE_AT_SAMPLE, dst_x, src, 
fs_reg(msg_data));
+  break;
+   }
+
+   case ir_binop_interpolate_at_offset: {
+  ir_constant *const_offset = ir->operands[1]->as_constant();
+  if (const_offset) {
+ unsigned msg_data = pack_pixel_offset(const_offset->value.f[0]) |
+(pack_pixel_offset(const_offset->value.f[1]) << 4);
+ inst = emit(FS_OPCODE_INTERPOLATE_AT_SHARED_OFFSET, dst_x, src,
+ fs_reg(msg_data));
+  } else {
+ /* pack the operands: hw wants offsets as 4 bit signed ints */
+ ir->operands[1]->accept(this);
+ src = fs_reg(this, glsl_type::ivec2_type);
+ fs_reg src2 = src;
+ for (int i = 0; i < 2; i++) {
+fs_reg temp = fs_reg(this, glsl_type::float_type);
+emit(MUL(temp, this->result, fs_reg(16.0f)));
+emit(MOV(src2, temp));  /* float to int */
+
+/* Clamp the upper end of the range to +7/16. ARB_gpu_shader5 
requires
+ * that we support a maximum offset of +0.5, which isn't 
representable
+ * in a S0.4 value -- if we did

Mesa (master): i965/disasm: add support for pixel interpolator messages

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 0b0572a2ad4c7ca8b437589291e47180c733c371
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b0572a2ad4c7ca8b437589291e47180c733c371

Author: Chris Forbes 
Date:   Mon Nov 18 21:24:24 2013 +1300

i965/disasm: add support for pixel interpolator messages

V3: Rework for brw_inst changes

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_disasm.c |   17 +
 1 file changed, 17 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c 
b/src/mesa/drivers/dri/i965/brw_disasm.c
index f37da19..d7362c1 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -473,6 +473,13 @@ static const char *const aop[16] = {
[BRW_AOP_PREDEC] = "predec",
 };
 
+static const char * const pixel_interpolator_msg_types[4] = {
+[GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET] = "per_message_offset",
+[GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE] = "sample_position",
+[GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID] = "centroid",
+[GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET] = "per_slot_offset",
+};
+
 static const char *const math_function[16] = {
[BRW_MATH_FUNCTION_INV]= "inv",
[BRW_MATH_FUNCTION_LOG]= "log",
@@ -1473,6 +1480,16 @@ brw_disassemble_inst(FILE *file, struct brw_context 
*brw, brw_inst *inst,
 /* FALLTHROUGH */
  }
 
+ case GEN7_SFID_PIXEL_INTERPOLATOR:
+if (brw->gen >= 7) {
+   format(file, " (%s, %s, 0x%02x)",
+  brw_inst_pi_nopersp(brw, inst) ? "linear" : "persp",
+  
pixel_interpolator_msg_types[brw_inst_pi_message_type(brw, inst)],
+  brw_inst_pi_message_data(brw, inst));
+   break;
+}
+/* FALLTHROUGH */
+
  default:
 format(file, "unsupported shared function ID %d", sfid);
 break;

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Mesa (master): i965: add low-level support for send to pixel interpolator

[Chris Forbes]

Module: Mesa
Branch: master
Commit: d732598b63eb0cd103f06bccd99d13d732028d79
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d732598b63eb0cd103f06bccd99d13d732028d79

Author: Chris Forbes 
Date:   Sun Nov 17 21:47:22 2013 +1300

i965: add low-level support for send to pixel interpolator

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_eu.h  |   10 ++
 src/mesa/drivers/dri/i965/brw_eu_emit.c |   28 
 2 files changed, 38 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_eu.h 
b/src/mesa/drivers/dri/i965/brw_eu.h
index 3164c80..63cb20b 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -372,6 +372,16 @@ brw_untyped_surface_read(struct brw_compile *p,
  unsigned msg_length,
  unsigned response_length);
 
+void
+brw_pixel_interpolator_query(struct brw_compile *p,
+ struct brw_reg dest,
+ struct brw_reg mrf,
+ bool noperspective,
+ unsigned mode,
+ unsigned data,
+ unsigned msg_length,
+ unsigned response_length);
+
 /***
  * brw_eu_util.c:
  */
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c 
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 3f00e4d..12424bd 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -2633,6 +2633,34 @@ brw_untyped_surface_read(struct brw_compile *p,
   brw_inst_access_mode(brw, insn) == BRW_ALIGN_1);
 }
 
+void
+brw_pixel_interpolator_query(struct brw_compile *p,
+ struct brw_reg dest,
+ struct brw_reg mrf,
+ bool noperspective,
+ unsigned mode,
+ unsigned data,
+ unsigned msg_length,
+ unsigned response_length)
+{
+   const struct brw_context *brw = p->brw;
+   struct brw_inst *insn = next_insn(p, BRW_OPCODE_SEND);
+
+   brw_set_dest(p, insn, dest);
+   brw_set_src0(p, insn, mrf);
+   brw_set_message_descriptor(p, insn, GEN7_SFID_PIXEL_INTERPOLATOR,
+  msg_length, response_length,
+  false /* header is never present for PI */,
+  false);
+
+   brw_inst_set_pi_simd_mode(
+ brw, insn, brw_inst_exec_size(brw, insn) == BRW_EXECUTE_16);
+   brw_inst_set_pi_slot_group(brw, insn, 0); /* zero unless 32/64px dispatch */
+   brw_inst_set_pi_nopersp(brw, insn, noperspective);
+   brw_inst_set_pi_message_type(brw, insn, mode);
+   brw_inst_set_pi_message_data(brw, insn, data);
+}
+
 /**
  * This instruction is generated as a single-channel align1 instruction by
  * both the VS and FS stages when using INTEL_DEBUG=shader_time.

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Mesa (master): i965: Add message descriptor bit definitions for pixel interpolator

[Chris Forbes]

Module: Mesa
Branch: master
Commit: 1b6163bdf5c69408e04c9685f9f98f842bb14b5a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b6163bdf5c69408e04c9685f9f98f842bb14b5a

Author: Chris Forbes 
Date:   Sat Jul 12 13:21:01 2014 +1200

i965: Add message descriptor bit definitions for pixel interpolator

These got lost in the big brw_inst shakeup.

Signed-off-by: Chris Forbes 
Reviewed-by: Kenneth Graunke 

---

 src/mesa/drivers/dri/i965/brw_defines.h |5 +
 src/mesa/drivers/dri/i965/brw_inst.h|   11 +++
 2 files changed, 16 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h 
b/src/mesa/drivers/dri/i965/brw_defines.h
index 0dadcb3..e528232 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1295,6 +1295,11 @@ enum brw_message_target {
(1 << 17))
 #define GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT12
 
+#define GEN7_PIXEL_INTERPOLATOR_LOC_SHARED_OFFSET 0
+#define GEN7_PIXEL_INTERPOLATOR_LOC_SAMPLE1
+#define GEN7_PIXEL_INTERPOLATOR_LOC_CENTROID  2
+#define GEN7_PIXEL_INTERPOLATOR_LOC_PER_SLOT_OFFSET   3
+
 /* HSW */
 #define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ  0
 #define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ1
diff --git a/src/mesa/drivers/dri/i965/brw_inst.h 
b/src/mesa/drivers/dri/i965/brw_inst.h
index ac00fd4..e880c9f 100644
--- a/src/mesa/drivers/dri/i965/brw_inst.h
+++ b/src/mesa/drivers/dri/i965/brw_inst.h
@@ -527,6 +527,17 @@ F(ts_opcode,   MD( 0),  MD( 0))
 /** @} */
 
 /**
+ * Pixel Interpolator message function control bits:
+ *  @{
+ */
+F(pi_simd_mode,  MD(16),  MD(16))
+F(pi_nopersp,MD(14),  MD(14))
+F(pi_message_type,   MD(13),  MD(12))
+F(pi_slot_group, MD(11),  MD(11))
+F(pi_message_data,   MD(7),   MD(0))
+/** @} */
+
+/**
  * Immediates:
  *  @{
  */

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