Mesa (master): meta: Expand the vertex structure for the GenerateMipmap and decompress paths
Module: Mesa
Branch: master
Commit: 83c90c9239404412dc61aa3b0229ebd56a1406cf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=83c90c9239404412dc61aa3b0229ebd56a1406cf
Author: Ian Romanick ian.d.roman...@intel.com
Date: Sat Dec 14 00:57:06 2013 -0800
meta: Expand the vertex structure for the GenerateMipmap and decompress paths
Final intermediate step leading to some code sharing. Note that the new
GemerateMipmap and decompress vertex structures are the same as the new vertex
structure in BlitFramebuffer and the others.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/common/meta.c | 29 +
1 file changed, 21 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index e56440f..0c5c63d 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -3249,10 +3249,10 @@ setup_texture_coords(GLenum faceTarget,
GLint width,
GLint height,
GLint depth,
- GLfloat coords0[3],
- GLfloat coords1[3],
- GLfloat coords2[3],
- GLfloat coords3[3])
+ GLfloat coords0[4],
+ GLfloat coords1[4],
+ GLfloat coords2[4],
+ GLfloat coords3[4])
{
static const GLfloat st[4][2] = {
{0.0f, 0.0f}, {1.0f, 0.0f}, {1.0f, 1.0f}, {0.0f, 1.0f}
@@ -3260,6 +3260,13 @@ setup_texture_coords(GLenum faceTarget,
GLuint i;
GLfloat r;
+ /* Currently all texture targets want the W component to be 1.0.
+*/
+ coords0[3] = 1.0F;
+ coords1[3] = 1.0F;
+ coords2[3] = 1.0F;
+ coords3[3] = 1.0F;
+
switch (faceTarget) {
case GL_TEXTURE_1D:
case GL_TEXTURE_2D:
@@ -3396,7 +3403,7 @@ static void
setup_ff_generate_mipmap(struct gen_mipmap_state *mipmap)
{
struct vertex {
- GLfloat x, y, tex[3];
+ GLfloat x, y, z, tex[4];
};
if (mipmap-VAO == 0) {
@@ -3473,7 +3480,7 @@ setup_glsl_generate_mipmap(struct gl_context *ctx,
GLenum target)
{
struct vertex {
- GLfloat x, y, tex[3];
+ GLfloat x, y, z, tex[4];
};
struct glsl_sampler *sampler;
const char *vs_source;
@@ -3619,7 +3626,7 @@ _mesa_meta_GenerateMipmap(struct gl_context *ctx, GLenum
target,
{
struct gen_mipmap_state *mipmap = ctx-Meta-Mipmap;
struct vertex {
- GLfloat x, y, tex[3];
+ GLfloat x, y, z, tex[4];
};
struct vertex verts[4];
const GLuint baseLevel = texObj-BaseLevel;
@@ -3709,6 +3716,9 @@ _mesa_meta_GenerateMipmap(struct gl_context *ctx, GLenum
target,
else
assert(!genMipmapSave);
+ /* Silence valgrind warnings about reading uninitialized stack. */
+ memset(verts, 0, sizeof(verts));
+
/* Setup texture coordinates */
setup_texture_coords(faceTarget,
slice,
@@ -4018,7 +4028,7 @@ decompress_texture_image(struct gl_context *ctx,
const GLenum target = texObj-Target;
GLenum faceTarget;
struct vertex {
- GLfloat x, y, tex[3];
+ GLfloat x, y, z, tex[4];
};
struct vertex verts[4];
GLuint fboDrawSave, fboReadSave;
@@ -4127,6 +4137,9 @@ decompress_texture_image(struct gl_context *ctx,
_mesa_BindSampler(ctx-Texture.CurrentUnit, decompress-Sampler);
}
+ /* Silence valgrind warnings about reading uninitialized stack. */
+ memset(verts, 0, sizeof(verts));
+
setup_texture_coords(faceTarget, slice, width, height, depth,
verts[0].tex,
verts[1].tex,
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Mesa (master): meta: Track the _mesa_meta_DrawPixels VBO just like the others
Module: Mesa
Branch: master
Commit: beb33fc5b719f608db2036360f1a2e482ec3e4ec
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=beb33fc5b719f608db2036360f1a2e482ec3e4ec
Author: Ian Romanick ian.d.roman...@intel.com
Date: Sat Dec 14 12:03:01 2013 -0800
meta: Track the _mesa_meta_DrawPixels VBO just like the others
All of the other meta routines have a particular pattern for creating
and tracking the VAO and VBO. This one function deviated from that
pattern for no apparent reason.
Almost all of the code added in this patch will be removed shortly.
v2: Drop glDeleteBuffers() of the old, now-uninitialized vbo variable.
Fixes getteximage-formats and fbo-mipmap-copypix regression when 2
landed in the variable (change by anholt).
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/common/meta.c | 44
1 file changed, 26 insertions(+), 18 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 0c5c63d..51ea42a 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -263,6 +263,7 @@ struct copypix_state
struct drawpix_state
{
GLuint VAO;
+ GLuint VBO;
GLuint StencilFP; /** Fragment program for drawing stencil images */
GLuint DepthFP; /** Fragment program for drawing depth images */
@@ -2561,6 +2562,9 @@ meta_drawpix_cleanup(struct drawpix_state *drawpix)
if (drawpix-VAO != 0) {
_mesa_DeleteVertexArrays(1, drawpix-VAO);
drawpix-VAO = 0;
+
+ _mesa_DeleteBuffers(1, drawpix-VBO);
+ drawpix-VBO = 0;
}
if (drawpix-StencilFP != 0) {
@@ -2732,7 +2736,6 @@ _mesa_meta_DrawPixels(struct gl_context *ctx,
GLenum texIntFormat;
GLboolean fallback, newTex;
GLbitfield metaExtraSave = 0x0;
- GLuint vbo;
/*
* Determine if we can do the glDrawPixels with texture mapping.
@@ -2824,6 +2827,27 @@ _mesa_meta_DrawPixels(struct gl_context *ctx,
newTex = alloc_texture(tex, width, height, texIntFormat);
+ if (drawpix-VAO == 0) {
+ /* one-time setup: create vertex array object */
+ _mesa_GenVertexArrays(1, drawpix-VAO);
+ _mesa_BindVertexArray(drawpix-VAO);
+
+ /* create vertex array buffer */
+ _mesa_GenBuffers(1, drawpix-VBO);
+ _mesa_BindBuffer(GL_ARRAY_BUFFER_ARB, drawpix-VBO);
+ _mesa_BufferData(GL_ARRAY_BUFFER_ARB, sizeof(verts),
+ NULL, GL_DYNAMIC_DRAW_ARB);
+
+ /* setup vertex arrays */
+ _mesa_VertexPointer(3, GL_FLOAT, sizeof(struct vertex), OFFSET(x));
+ _mesa_TexCoordPointer(2, GL_FLOAT, sizeof(struct vertex), OFFSET(tex));
+ _mesa_EnableClientState(GL_VERTEX_ARRAY);
+ _mesa_EnableClientState(GL_TEXTURE_COORD_ARRAY);
+ } else {
+ _mesa_BindVertexArray(drawpix-VAO);
+ _mesa_BindBuffer(GL_ARRAY_BUFFER_ARB, drawpix-VBO);
+ }
+
/* Silence valgrind warnings about reading uninitialized stack. */
memset(verts, 0, sizeof(verts));
@@ -2857,24 +2881,10 @@ _mesa_meta_DrawPixels(struct gl_context *ctx,
verts[3].tex[1] = tex-Ttop;
}
- if (drawpix-VAO == 0) {
- /* one-time setup: create vertex array object */
- _mesa_GenVertexArrays(1, drawpix-VAO);
- }
- _mesa_BindVertexArray(drawpix-VAO);
-
- /* create vertex array buffer */
- _mesa_GenBuffers(1, vbo);
- _mesa_BindBuffer(GL_ARRAY_BUFFER_ARB, vbo);
+ /* upload new vertex data */
_mesa_BufferData(GL_ARRAY_BUFFER_ARB, sizeof(verts),
verts, GL_DYNAMIC_DRAW_ARB);
- /* setup vertex arrays */
- _mesa_VertexPointer(3, GL_FLOAT, sizeof(struct vertex), OFFSET(x));
- _mesa_TexCoordPointer(2, GL_FLOAT, sizeof(struct vertex), OFFSET(tex));
- _mesa_EnableClientState(GL_VERTEX_ARRAY);
- _mesa_EnableClientState(GL_TEXTURE_COORD_ARRAY);
-
/* set given unpack params */
ctx-Unpack = *unpack;
@@ -2944,8 +2954,6 @@ _mesa_meta_DrawPixels(struct gl_context *ctx,
_mesa_set_enable(ctx, tex-Target, GL_FALSE);
- _mesa_DeleteBuffers(1, vbo);
-
/* restore unpack params */
ctx-Unpack = unpackSave;
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Mesa (master): meta: Expand the vertex structure for the BlitFramebuffer paths
Module: Mesa
Branch: master
Commit: 9b4e659e62795375b96d9977dff0e436e6066f54
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b4e659e62795375b96d9977dff0e436e6066f54
Author: Ian Romanick ian.d.roman...@intel.com
Date: Fri Dec 13 19:04:20 2013 -0800
meta: Expand the vertex structure for the BlitFramebuffer paths
This is the first of several steps leading to some code sharing.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/common/meta.c | 66 ++--
1 file changed, 36 insertions(+), 30 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index f12bcaa..99163d6 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -1459,7 +1459,7 @@ static void
setup_ff_blit_framebuffer(struct blit_state *blit)
{
struct vertex {
- GLfloat x, y, s, t;
+ GLfloat x, y, z, tex[4];
};
struct vertex verts[4];
@@ -1478,7 +1478,7 @@ setup_ff_blit_framebuffer(struct blit_state *blit)
/* setup vertex arrays */
_mesa_VertexPointer(2, GL_FLOAT, sizeof(struct vertex), OFFSET(x));
- _mesa_TexCoordPointer(2, GL_FLOAT, sizeof(struct vertex), OFFSET(s));
+ _mesa_TexCoordPointer(2, GL_FLOAT, sizeof(struct vertex), OFFSET(tex));
_mesa_EnableClientState(GL_VERTEX_ARRAY);
_mesa_EnableClientState(GL_TEXTURE_COORD_ARRAY);
}
@@ -1496,7 +1496,7 @@ setup_glsl_blit_framebuffer(struct gl_context *ctx,
GLenum target)
{
struct vertex {
- GLfloat x, y, s, t;
+ GLfloat x, y, z, tex[4];
};
struct vertex verts[4];
const char *vs_source;
@@ -1526,7 +1526,7 @@ setup_glsl_blit_framebuffer(struct gl_context *ctx,
_mesa_VertexAttribPointer(0, 2, GL_FLOAT, GL_FALSE,
sizeof(struct vertex), OFFSET(x));
_mesa_VertexAttribPointer(1, 2, GL_FLOAT, GL_FALSE,
- sizeof(struct vertex), OFFSET(s));
+ sizeof(struct vertex), OFFSET(tex));
_mesa_EnableVertexAttribArray(0);
_mesa_EnableVertexAttribArray(1);
@@ -1727,7 +1727,7 @@ blitframebuffer_texture(struct gl_context *ctx,
/* Prepare vertex data (the VBO was previously created and bound) */
{
struct vertex {
- GLfloat x, y, s, t;
+ GLfloat x, y, z, tex[4];
};
struct vertex verts[4];
GLfloat s0, t0, s1, t1;
@@ -1748,6 +1748,9 @@ blitframebuffer_texture(struct gl_context *ctx,
t1 = (float) srcY1;
}
+/* Silence valgrind warnings about reading uninitialized stack. */
+memset(verts, 0, sizeof(verts));
+
/* setup vertex positions */
verts[0].x = -1.0F * flipX;
verts[0].y = -1.0F * flipY;
@@ -1758,14 +1761,14 @@ blitframebuffer_texture(struct gl_context *ctx,
verts[3].x = -1.0F * flipX;
verts[3].y = 1.0F * flipY;
-verts[0].s = s0;
-verts[0].t = t0;
-verts[1].s = s1;
-verts[1].t = t0;
-verts[2].s = s1;
-verts[2].t = t1;
-verts[3].s = s0;
-verts[3].t = t1;
+verts[0].tex[0] = s0;
+verts[0].tex[1] = t0;
+verts[1].tex[0] = s1;
+verts[1].tex[1] = t0;
+verts[2].tex[0] = s1;
+verts[2].tex[1] = t1;
+verts[3].tex[0] = s0;
+verts[3].tex[1] = t1;
_mesa_BufferSubData(GL_ARRAY_BUFFER_ARB, 0, sizeof(verts), verts);
}
@@ -1826,7 +1829,7 @@ _mesa_meta_BlitFramebuffer(struct gl_context *ctx,
const GLint flipY = srcFlipY * dstFlipY;
struct vertex {
- GLfloat x, y, s, t;
+ GLfloat x, y, z, tex[4];
};
struct vertex verts[4];
GLboolean newTex;
@@ -1875,6 +1878,9 @@ _mesa_meta_BlitFramebuffer(struct gl_context *ctx,
_mesa_BindVertexArray(blit-VAO);
_mesa_BindBuffer(GL_ARRAY_BUFFER_ARB, blit-VBO);
+ /* Silence valgrind warnings about reading uninitialized stack. */
+ memset(verts, 0, sizeof(verts));
+
/* Continue with normal approach which involves copying the src rect
* into a temporary texture and is blitted by drawing a textured quad.
*/
@@ -1913,14 +1919,14 @@ _mesa_meta_BlitFramebuffer(struct gl_context *ctx,
rb_base_format, filter);
/* texcoords (after texture allocation!) */
{
- verts[0].s = 1.0F;
- verts[0].t = 1.0F;
- verts[1].s = tex-Sright - 1.0F;
- verts[1].t = 1.0F;
- verts[2].s = tex-Sright - 1.0F;
- verts[2].t = tex-Ttop - 1.0F;
- verts[3].s = 1.0F;
- verts[3].t = tex-Ttop - 1.0F;
+ verts[0].tex[0] = 1.0F;
+ verts[0].tex[1] = 1.0F;
+ verts
Mesa (master): meta: Expand the vertex structure for the DrawPixels paths
Module: Mesa
Branch: master
Commit: 897f97566898b6ddde710c8c4e83ecf163c2c62f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=897f97566898b6ddde710c8c4e83ecf163c2c62f
Author: Ian Romanick ian.d.roman...@intel.com
Date: Sat Dec 14 00:55:50 2013 -0800
meta: Expand the vertex structure for the DrawPixels paths
Another step leading to some code sharing. Note that the new DrawPixels
vertex structure is the same as the new vertex structure in BlitFramebuffer
and the others.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/common/meta.c | 23 +--
1 file changed, 13 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index e9113e9..e56440f 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -2726,7 +2726,7 @@ _mesa_meta_DrawPixels(struct gl_context *ctx,
const struct gl_pixelstore_attrib unpackSave = ctx-Unpack;
const GLuint origStencilMask = ctx-Stencil.WriteMask[0];
struct vertex {
- GLfloat x, y, z, s, t;
+ GLfloat x, y, z, tex[4];
};
struct vertex verts[4];
GLenum texIntFormat;
@@ -2824,6 +2824,9 @@ _mesa_meta_DrawPixels(struct gl_context *ctx,
newTex = alloc_texture(tex, width, height, texIntFormat);
+ /* Silence valgrind warnings about reading uninitialized stack. */
+ memset(verts, 0, sizeof(verts));
+
/* vertex positions, texcoords (after texture allocation!) */
{
const GLfloat x0 = (GLfloat) x;
@@ -2835,23 +2838,23 @@ _mesa_meta_DrawPixels(struct gl_context *ctx,
verts[0].x = x0;
verts[0].y = y0;
verts[0].z = z;
- verts[0].s = 0.0F;
- verts[0].t = 0.0F;
+ verts[0].tex[0] = 0.0F;
+ verts[0].tex[1] = 0.0F;
verts[1].x = x1;
verts[1].y = y0;
verts[1].z = z;
- verts[1].s = tex-Sright;
- verts[1].t = 0.0F;
+ verts[1].tex[0] = tex-Sright;
+ verts[1].tex[1] = 0.0F;
verts[2].x = x1;
verts[2].y = y1;
verts[2].z = z;
- verts[2].s = tex-Sright;
- verts[2].t = tex-Ttop;
+ verts[2].tex[0] = tex-Sright;
+ verts[2].tex[1] = tex-Ttop;
verts[3].x = x0;
verts[3].y = y1;
verts[3].z = z;
- verts[3].s = 0.0F;
- verts[3].t = tex-Ttop;
+ verts[3].tex[0] = 0.0F;
+ verts[3].tex[1] = tex-Ttop;
}
if (drawpix-VAO == 0) {
@@ -2868,7 +2871,7 @@ _mesa_meta_DrawPixels(struct gl_context *ctx,
/* setup vertex arrays */
_mesa_VertexPointer(3, GL_FLOAT, sizeof(struct vertex), OFFSET(x));
- _mesa_TexCoordPointer(2, GL_FLOAT, sizeof(struct vertex), OFFSET(s));
+ _mesa_TexCoordPointer(2, GL_FLOAT, sizeof(struct vertex), OFFSET(tex));
_mesa_EnableClientState(GL_VERTEX_ARRAY);
_mesa_EnableClientState(GL_TEXTURE_COORD_ARRAY);
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Mesa (master): meta: Refactor common VAO and VBO initialization code
Module: Mesa
Branch: master
Commit: f34d599a5b86fe05be22201e7cf279d5578feb7f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f34d599a5b86fe05be22201e7cf279d5578feb7f
Author: Ian Romanick ian.d.roman...@intel.com
Date: Sat Dec 14 11:24:36 2013 -0800
meta: Refactor common VAO and VBO initialization code
v2: Clean up some stray binding calls
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Brian Paul bri...@vmware.com (v1)
Reviewed-by: Eric Anholt e...@anholt.net (v2)
---
src/mesa/drivers/common/meta.c | 326
1 file changed, 99 insertions(+), 227 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 51ea42a..cdff990 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -351,6 +351,10 @@ struct gl_meta_state
struct drawtex_state DrawTex; /** For _mesa_meta_DrawTex() */
};
+struct vertex {
+ GLfloat x, y, z, tex[4];
+};
+
static void meta_glsl_blit_cleanup(struct blit_state *blit);
static void cleanup_temp_texture(struct temp_texture *tex);
static void meta_glsl_clear_cleanup(struct clear_state *clear);
@@ -426,6 +430,89 @@ link_program_with_debug(struct gl_context *ctx, GLuint
program)
}
/**
+ * Configure vertex buffer and vertex array objects for tests
+ *
+ * Regardless of whether a new VAO and new VBO are created, the objects
+ * referenced by \c VAO and \c VBO will be bound into the GL state vector
+ * when this function terminates.
+ *
+ * \param VAO Storage for vertex array object handle. If 0, a new VAO
+ * will be created.
+ * \param VBO Storage for vertex buffer object handle. If 0, a new VBO
+ * will be created. The new VBO will have storage for 4
+ * \c vertex structures.
+ * \param use_generic_attributes Should generic attributes 0 and 1 be used,
+ * or should traditional, fixed-function color and texture
+ * coordinate be used?
+ * \param vertex_size Number of components for attribute 0 / vertex.
+ * \param texcoord_size Number of components for attribute 1 / texture
+ * coordinate. If this is 0, attribute 1 will not be set or
+ * enabled.
+ * \param color_size Number of components for attribute 1 / primary color.
+ * If this is 0, attribute 1 will not be set or enabled.
+ *
+ * \note Either \c texcoord_size or \c color_size \b must be zero! The same
+ * data location is used for both values, so only one can be active at a time.
+ *
+ * \note If \c use_generic_attributes is \c true, \c color_size must be zero.
+ * Use \c texcoord_size instead.
+ */
+static void
+setup_vertex_objects(GLuint *VAO, GLuint *VBO, bool use_generic_attributes,
+ unsigned vertex_size, unsigned texcoord_size,
+ unsigned color_size)
+{
+ if (*VAO == 0) {
+ assert(*VBO == 0);
+ assert(color_size == 0 || texcoord_size == 0);
+
+ /* create vertex array object */
+ _mesa_GenVertexArrays(1, VAO);
+ _mesa_BindVertexArray(*VAO);
+
+ /* create vertex array buffer */
+ _mesa_GenBuffers(1, VBO);
+ _mesa_BindBuffer(GL_ARRAY_BUFFER, *VBO);
+ _mesa_BufferData(GL_ARRAY_BUFFER, 4 * sizeof(struct vertex), NULL,
+ GL_DYNAMIC_DRAW);
+
+ /* setup vertex arrays */
+ if (use_generic_attributes) {
+ assert(color_size == 0);
+
+ _mesa_VertexAttribPointer(0, vertex_size, GL_FLOAT, GL_FALSE,
+ sizeof(struct vertex), OFFSET(x));
+ _mesa_EnableVertexAttribArray(0);
+
+ if (texcoord_size 0) {
+_mesa_VertexAttribPointer(1, texcoord_size, GL_FLOAT, GL_FALSE,
+ sizeof(struct vertex), OFFSET(tex));
+_mesa_EnableVertexAttribArray(1);
+ }
+ } else {
+ _mesa_VertexPointer(vertex_size, GL_FLOAT, sizeof(struct vertex),
+ OFFSET(x));
+ _mesa_EnableClientState(GL_VERTEX_ARRAY);
+
+ if (texcoord_size 0) {
+_mesa_TexCoordPointer(texcoord_size, GL_FLOAT,
+ sizeof(struct vertex), OFFSET(tex));
+_mesa_EnableClientState(GL_TEXTURE_COORD_ARRAY);
+ }
+
+ if (color_size 0) {
+_mesa_ColorPointer(color_size, GL_FLOAT,
+ sizeof(struct vertex), OFFSET(tex));
+_mesa_EnableClientState(GL_COLOR_ARRAY);
+ }
+ }
+ } else {
+ _mesa_BindVertexArray(*VAO);
+ _mesa_BindBuffer(GL_ARRAY_BUFFER, *VBO);
+ }
+}
+
+/**
* Initialize meta-ops for a context.
* To be called once during context creation.
*/
@@ -1459,30 +1546,7 @@ init_blit_depth_pixels(struct gl_context *ctx)
static void
setup_ff_blit_framebuffer(struct blit_state *blit)
{
- struct vertex {
- GLfloat x, y, z, tex[4
Mesa (master): meta: Silence unused parameter warning in _mesa_meta_CopyTexSubImage
Module: Mesa Branch: master Commit: 54b108282836b68b0db7b3c9a9ba096f99d65f16 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=54b108282836b68b0db7b3c9a9ba096f99d65f16 Author: Ian Romanick ian.d.roman...@intel.com Date: Tue Dec 17 13:38:50 2013 -0800 meta: Silence unused parameter warning in _mesa_meta_CopyTexSubImage drivers/common/meta.c: In function '_mesa_meta_CopyTexSubImage': drivers/common/meta.c:3744:52: warning: unused parameter 'rb' [-Wunused-parameter] Unfortunately, the parameter can't just be removed because it is part of the dd_function_table::CopyTexSubImage interface. Signed-off-by: Ian Romanick ian.d.roman...@intel.com Reviewed-by: Eric Anholt e...@anholt.net --- src/mesa/drivers/common/meta.c |6 ++ 1 file changed, 6 insertions(+) diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c index 566e598..5dbeaeb 100644 --- a/src/mesa/drivers/common/meta.c +++ b/src/mesa/drivers/common/meta.c @@ -3821,6 +3821,12 @@ _mesa_meta_CopyTexSubImage(struct gl_context *ctx, GLuint dims, GLint bpp; void *buf; + /* The gl_renderbuffer is part of the interface for +* dd_function_table::CopyTexSubImage, but this implementation does not use +* it. +*/ + (void) rb; + /* Choose format/type for temporary image buffer */ format = _mesa_get_format_base_format(texImage-TexFormat); if (format == GL_LUMINANCE || ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa: GL_ARB_half_float_pixel is not optional
Module: Mesa
Branch: master
Commit: 1edca151a00134778b959366d5e7c0a3b63cc8f7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1edca151a00134778b959366d5e7c0a3b63cc8f7
Author: Ian Romanick ian.d.roman...@intel.com
Date: Mon Jan 13 15:23:48 2014 -0800
mesa: GL_ARB_half_float_pixel is not optional
Almost every driver already supported it. All current and future
Gallium drivers always support it, and most existing classic drivers
support it.
This only changes radeon and nouveau.
This extension only adds data types that can be passed to, for example,
glTexImage2D. It does not add internal formats. Since you can already
pass GL_FLOAT to glTexImage2D this shouldn't pose any additional issues
with those drivers. Note that r200 and i915 already supported this
extension, and they don't support floating-point textures either.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Eric Anholt e...@anholt.net
---
docs/GL3.txt |2 +-
src/mesa/drivers/dri/i915/intel_extensions.c |1 -
src/mesa/drivers/dri/i965/intel_extensions.c |1 -
src/mesa/drivers/dri/r200/r200_context.c |1 -
src/mesa/main/extensions.c |3 +--
src/mesa/main/glformats.c| 24 ++--
src/mesa/main/mtypes.h |1 -
src/mesa/main/teximage.c | 17 ++---
src/mesa/main/version.c |1 -
src/mesa/state_tracker/st_extensions.c |1 -
10 files changed, 10 insertions(+), 42 deletions(-)
diff --git a/docs/GL3.txt b/docs/GL3.txt
index c678e4a..06ce417 100644
--- a/docs/GL3.txt
+++ b/docs/GL3.txt
@@ -30,7 +30,7 @@ GL 3.0 --- all DONE: i965, nv50, nvc0, r600, radeonsi
GL_EXT_texture_shared_exponentDONE (swrast)
Float depth buffers (GL_ARB_depth_buffer_float) DONE ()
Framebuffer objects (GL_ARB_framebuffer_object) DONE (r300, swrast)
- GL_ARB_half_float_pixel DONE (r300, swrast)
+ GL_ARB_half_float_pixel DONE (all drivers)
GL_ARB_half_float_vertex DONE (r300, swrast)
GL_EXT_texture_integerDONE ()
GL_EXT_texture_array DONE ()
diff --git a/src/mesa/drivers/dri/i915/intel_extensions.c
b/src/mesa/drivers/dri/i915/intel_extensions.c
index 9da12dc..11be004 100644
--- a/src/mesa/drivers/dri/i915/intel_extensions.c
+++ b/src/mesa/drivers/dri/i915/intel_extensions.c
@@ -47,7 +47,6 @@ intelInitExtensions(struct gl_context *ctx)
ctx-Extensions.ARB_draw_elements_base_vertex = true;
ctx-Extensions.ARB_explicit_attrib_location = true;
ctx-Extensions.ARB_framebuffer_object = true;
- ctx-Extensions.ARB_half_float_pixel = true;
ctx-Extensions.ARB_internalformat_query = true;
ctx-Extensions.ARB_map_buffer_range = true;
ctx-Extensions.ARB_point_sprite = true;
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index eb3f2c7..ef9aa55 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++ b/src/mesa/drivers/dri/i965/intel_extensions.c
@@ -174,7 +174,6 @@ intelInitExtensions(struct gl_context *ctx)
ctx-Extensions.ARB_fragment_program_shadow = true;
ctx-Extensions.ARB_fragment_shader = true;
ctx-Extensions.ARB_framebuffer_object = true;
- ctx-Extensions.ARB_half_float_pixel = true;
ctx-Extensions.ARB_half_float_vertex = true;
ctx-Extensions.ARB_instanced_arrays = true;
ctx-Extensions.ARB_internalformat_query = true;
diff --git a/src/mesa/drivers/dri/r200/r200_context.c
b/src/mesa/drivers/dri/r200/r200_context.c
index 0043090..71dfcf3 100644
--- a/src/mesa/drivers/dri/r200/r200_context.c
+++ b/src/mesa/drivers/dri/r200/r200_context.c
@@ -366,7 +366,6 @@ GLboolean r200CreateContext( gl_api api,
_math_matrix_ctr( rmesa-tmpmat );
_math_matrix_set_identity( rmesa-tmpmat );
- ctx-Extensions.ARB_half_float_pixel = true;
ctx-Extensions.ARB_occlusion_query = true;
ctx-Extensions.ARB_point_sprite = true;
ctx-Extensions.ARB_texture_border_clamp = true;
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index 5f741fb..bc63b26 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main/extensions.c
@@ -106,7 +106,7 @@ static const struct extension extension_table[] = {
{ GL_ARB_framebuffer_sRGB,o(EXT_framebuffer_sRGB),
GL, 1998 },
{ GL_ARB_get_program_binary, o(dummy_true),
GL, 2010 },
{ GL_ARB_gpu_shader5, o(ARB_gpu_shader5),
GL, 2010 },
- { GL_ARB_half_float_pixel,o(ARB_half_float_pixel),
GL, 2003 },
+ { GL_ARB_half_float_pixel,o(dummy_true
Mesa (master): meta: Silence unused parameter warning in setup_drawpix_texture
Module: Mesa
Branch: master
Commit: d156281cfe8f2ceeb562afda4984972028a74e86
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d156281cfe8f2ceeb562afda4984972028a74e86
Author: Ian Romanick ian.d.roman...@intel.com
Date: Mon Dec 16 19:07:24 2013 -0800
meta: Silence unused parameter warning in setup_drawpix_texture
drivers/common/meta.c: In function 'setup_drawpix_texture':
drivers/common/meta.c:1572:30: warning: unused parameter 'texIntFormat'
[-Wunused-parameter]
setup_drawpix_texture has never used this paramater. Before the
refactor commit 04f8193aa it was used in several locations. After that
commit, texIntFormat was only used in alloc_texture.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/common/meta.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index cdff990..566e598 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -1467,7 +1467,6 @@ static void
setup_drawpix_texture(struct gl_context *ctx,
struct temp_texture *tex,
GLboolean newTex,
- GLenum texIntFormat,
GLsizei width, GLsizei height,
GLenum format, GLenum type,
const GLvoid *pixels)
@@ -1980,7 +1979,7 @@ _mesa_meta_BlitFramebuffer(struct gl_context *ctx,
newTex = alloc_texture(depthTex, srcW, srcH, GL_DEPTH_COMPONENT);
_mesa_ReadPixels(srcX, srcY, srcW, srcH, GL_DEPTH_COMPONENT,
GL_UNSIGNED_INT, tmp);
- setup_drawpix_texture(ctx, depthTex, newTex, GL_DEPTH_COMPONENT,
+ setup_drawpix_texture(ctx, depthTex, newTex,
srcW, srcH, GL_DEPTH_COMPONENT,
GL_UNSIGNED_INT, tmp);
@@ -2838,7 +2837,7 @@ _mesa_meta_DrawPixels(struct gl_context *ctx,
if (!drawpix-StencilFP)
init_draw_stencil_pixels(ctx);
- setup_drawpix_texture(ctx, tex, newTex, texIntFormat, width, height,
+ setup_drawpix_texture(ctx, tex, newTex, width, height,
GL_ALPHA, type, pixels);
_mesa_ColorMask(GL_FALSE, GL_FALSE, GL_FALSE, GL_FALSE);
@@ -2881,14 +2880,14 @@ _mesa_meta_DrawPixels(struct gl_context *ctx,
_mesa_ProgramLocalParameter4fvARB(GL_FRAGMENT_PROGRAM_ARB, 0,
ctx-Current.RasterColor);
- setup_drawpix_texture(ctx, tex, newTex, texIntFormat, width, height,
+ setup_drawpix_texture(ctx, tex, newTex, width, height,
format, type, pixels);
_mesa_DrawArrays(GL_TRIANGLE_FAN, 0, 4);
}
else {
/* Drawing RGBA */
- setup_drawpix_texture(ctx, tex, newTex, texIntFormat, width, height,
+ setup_drawpix_texture(ctx, tex, newTex, width, height,
format, type, pixels);
_mesa_DrawArrays(GL_TRIANGLE_FAN, 0, 4);
}
@@ -3072,7 +3071,7 @@ _mesa_meta_Bitmap(struct gl_context *ctx,
_mesa_set_enable(ctx, GL_ALPHA_TEST, GL_TRUE);
_mesa_AlphaFunc(GL_NOTEQUAL, UBYTE_TO_FLOAT(bg));
- setup_drawpix_texture(ctx, tex, newTex, texIntFormat, width, height,
+ setup_drawpix_texture(ctx, tex, newTex, width, height,
GL_ALPHA, GL_UNSIGNED_BYTE, bitmap8);
_mesa_DrawArrays(GL_TRIANGLE_FAN, 0, 4);
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Mesa (master): mesa: Fix extension dependency for half-float TexBOs
Module: Mesa
Branch: master
Commit: 6d6a29018119fd414973ad051fc2271c784ef0f1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6d6a29018119fd414973ad051fc2271c784ef0f1
Author: Ian Romanick ian.d.roman...@intel.com
Date: Mon Jan 13 15:18:23 2014 -0800
mesa: Fix extension dependency for half-float TexBOs
Half-float TexBOs should require both GL_ARB_half_float_pixel and
GL_ARB_texture_float. This doesn't matter much in practice. Every
driver that supports GL_ARB_texture_buffer_object already supports
GL_ARB_half_float_pixel. We only expose the TexBO extension in core
profiles, and those require GL_ARB_texture_float.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/main/teximage.c | 13 -
1 file changed, 12 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 4d635fe..07ac1e1 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -4186,7 +4186,18 @@ _mesa_validate_texbuffer_format(const struct gl_context
*ctx,
if (datatype == GL_FLOAT !ctx-Extensions.ARB_texture_float)
return MESA_FORMAT_NONE;
- if (datatype == GL_HALF_FLOAT !ctx-Extensions.ARB_half_float_pixel)
+ /* The GL_ARB_texture_buffer_object spec says:
+*
+* If ARB_texture_float is not supported, references to the
+* floating-point internal formats provided by that extension should be
+* removed, and such formats may not be passed to TexBufferARB.
+*
+* As a result, GL_HALF_FLOAT internal format depends on both
+* GL_ARB_texture_float and GL_ARB_half_float_pixel.
+*/
+ if (datatype == GL_HALF_FLOAT
+ !(ctx-Extensions.ARB_half_float_pixel
+ ctx-Extensions.ARB_texture_float))
return MESA_FORMAT_NONE;
if (!ctx-Extensions.ARB_texture_rg) {
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Mesa (master): meta: Use common vertex setup code for _mesa_meta_Bitmap too
Module: Mesa
Branch: master
Commit: b514f241019c6ce5ee0905c6f0a59eae1ddc03e6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b514f241019c6ce5ee0905c6f0a59eae1ddc03e6
Author: Ian Romanick ian.d.roman...@intel.com
Date: Sat Dec 14 19:33:02 2013 -0800
meta: Use common vertex setup code for _mesa_meta_Bitmap too
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/common/meta.c | 48 ++--
1 file changed, 12 insertions(+), 36 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 73832e4..6ffa416 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -2942,9 +2942,6 @@ _mesa_meta_Bitmap(struct gl_context *ctx,
const GLenum texIntFormat = GL_ALPHA;
const struct gl_pixelstore_attrib unpackSave = *unpack;
GLubyte fg, bg;
- struct vertex {
- GLfloat x, y, z, s, t, r, g, b, a;
- };
struct vertex verts[4];
GLboolean newTex;
GLubyte *bitmap8;
@@ -2978,34 +2975,13 @@ _mesa_meta_Bitmap(struct gl_context *ctx,
MESA_META_VERTEX |
MESA_META_VIEWPORT));
- if (bitmap-VAO == 0) {
- /* one-time setup */
-
- /* create vertex array object */
- _mesa_GenVertexArrays(1, bitmap-VAO);
- _mesa_BindVertexArray(bitmap-VAO);
-
- /* create vertex array buffer */
- _mesa_GenBuffers(1, bitmap-VBO);
- _mesa_BindBuffer(GL_ARRAY_BUFFER_ARB, bitmap-VBO);
- _mesa_BufferData(GL_ARRAY_BUFFER_ARB, sizeof(verts),
- NULL, GL_DYNAMIC_DRAW_ARB);
-
- /* setup vertex arrays */
- _mesa_VertexPointer(3, GL_FLOAT, sizeof(struct vertex), OFFSET(x));
- _mesa_TexCoordPointer(2, GL_FLOAT, sizeof(struct vertex), OFFSET(s));
- _mesa_ColorPointer(4, GL_FLOAT, sizeof(struct vertex), OFFSET(r));
- _mesa_EnableClientState(GL_VERTEX_ARRAY);
- _mesa_EnableClientState(GL_TEXTURE_COORD_ARRAY);
- _mesa_EnableClientState(GL_COLOR_ARRAY);
- }
- else {
- _mesa_BindVertexArray(bitmap-VAO);
- _mesa_BindBuffer(GL_ARRAY_BUFFER_ARB, bitmap-VBO);
- }
+ setup_vertex_objects(bitmap-VAO, bitmap-VBO, false, 3, 2, 4);
newTex = alloc_texture(tex, width, height, texIntFormat);
+ /* Silence valgrind warnings about reading uninitialized stack. */
+ memset(verts, 0, sizeof(verts));
+
/* vertex positions, texcoords, colors (after texture allocation!) */
{
const GLfloat x0 = (GLfloat) x;
@@ -3018,23 +2994,23 @@ _mesa_meta_Bitmap(struct gl_context *ctx,
verts[0].x = x0;
verts[0].y = y0;
verts[0].z = z;
- verts[0].s = 0.0F;
- verts[0].t = 0.0F;
+ verts[0].tex[0] = 0.0F;
+ verts[0].tex[1] = 0.0F;
verts[1].x = x1;
verts[1].y = y0;
verts[1].z = z;
- verts[1].s = tex-Sright;
- verts[1].t = 0.0F;
+ verts[1].tex[0] = tex-Sright;
+ verts[1].tex[1] = 0.0F;
verts[2].x = x1;
verts[2].y = y1;
verts[2].z = z;
- verts[2].s = tex-Sright;
- verts[2].t = tex-Ttop;
+ verts[2].tex[0] = tex-Sright;
+ verts[2].tex[1] = tex-Ttop;
verts[3].x = x0;
verts[3].y = y1;
verts[3].z = z;
- verts[3].s = 0.0F;
- verts[3].t = tex-Ttop;
+ verts[3].tex[0] = 0.0F;
+ verts[3].tex[1] = tex-Ttop;
for (i = 0; i 4; i++) {
verts[i].r = ctx-Current.RasterColor[0];
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Mesa (master): meta: Add cubemap array support to generic blit shader code
Module: Mesa
Branch: master
Commit: daa3eea8774f2ced9573e54f68332c4a7ce0c143
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=daa3eea8774f2ced9573e54f68332c4a7ce0c143
Author: Ian Romanick ian.d.roman...@intel.com
Date: Mon Dec 16 17:10:29 2013 -0800
meta: Add cubemap array support to generic blit shader code
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/common/meta.c | 12
1 file changed, 12 insertions(+)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 353aa39..4d4f877 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -237,6 +237,7 @@ struct sampler_table {
struct glsl_sampler sampler_cubemap;
struct glsl_sampler sampler_1d_array;
struct glsl_sampler sampler_2d_array;
+ struct glsl_sampler sampler_cubemap_array;
};
/**
@@ -480,6 +481,7 @@ setup_shader_for_sampler(struct gl_context *ctx, struct
glsl_sampler *sampler)
fs_source = ralloc_asprintf(mem_ctx,
#extension GL_EXT_texture_array : enable\n
+ #extension GL_ARB_texture_cube_map_array:
enable\n
#ifdef GL_ES\n
precision highp float;\n
#endif\n
@@ -507,6 +509,7 @@ setup_shader_for_sampler(struct gl_context *ctx, struct
glsl_sampler *sampler)
_mesa_is_desktop_gl(ctx) ? 130 : 300 es);
fs_source = ralloc_asprintf(mem_ctx,
#version %s\n
+ #extension GL_ARB_texture_cube_map_array:
enable\n
#ifdef GL_ES\n
precision highp float;\n
#endif\n
@@ -3305,6 +3308,8 @@ setup_texture_coords(GLenum faceTarget,
assert(0);
}
+ coord[3] = (float) (slice / 6);
+
switch (faceTarget) {
case GL_TEXTURE_CUBE_MAP_POSITIVE_X:
coord[0] = 1.0f;
@@ -3388,6 +3393,11 @@ setup_texture_sampler(GLenum target, struct
sampler_table *table)
table-sampler_2d_array.func = texture2DArray;
table-sampler_2d_array.texcoords = texCoords.xyz;
return table-sampler_2d_array;
+ case GL_TEXTURE_CUBE_MAP_ARRAY:
+ table-sampler_cubemap_array.type = samplerCubeArray;
+ table-sampler_cubemap_array.func = textureCubeArray;
+ table-sampler_cubemap_array.texcoords = texCoords.xyzw;
+ return table-sampler_cubemap_array;
default:
_mesa_problem(NULL, Unexpected texture target 0x%x in
setup_texture_sampler()\n, target);
@@ -3405,6 +3415,7 @@ sampler_table_cleanup(struct sampler_table *table)
_mesa_DeleteObjectARB(table-sampler_cubemap.shader_prog);
_mesa_DeleteObjectARB(table-sampler_1d_array.shader_prog);
_mesa_DeleteObjectARB(table-sampler_2d_array.shader_prog);
+ _mesa_DeleteObjectARB(table-sampler_cubemap_array.shader_prog);
table-sampler_1d.shader_prog = 0;
table-sampler_2d.shader_prog = 0;
@@ -3413,6 +3424,7 @@ sampler_table_cleanup(struct sampler_table *table)
table-sampler_cubemap.shader_prog = 0;
table-sampler_1d_array.shader_prog = 0;
table-sampler_2d_array.shader_prog = 0;
+ table-sampler_cubemap_array.shader_prog = 0;
}
static void
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Mesa (master): meta: Use common GLSL code for blits
Module: Mesa
Branch: master
Commit: c1417aae6c468adafdb64bd8f64ff348ece27b06
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c1417aae6c468adafdb64bd8f64ff348ece27b06
Author: Ian Romanick ian.d.roman...@intel.com
Date: Mon Dec 16 13:10:53 2013 -0800
meta: Use common GLSL code for blits
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/common/meta.c | 108 +---
1 file changed, 13 insertions(+), 95 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index a40bf08..75fb7a5 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -247,8 +247,7 @@ struct blit_state
GLuint VAO;
GLuint VBO;
GLuint DepthFP;
- GLuint ShaderProg;
- GLuint RectShaderProg;
+ struct sampler_table samplers;
struct temp_texture depthTex;
};
@@ -487,6 +486,7 @@ setup_shader_for_sampler(struct gl_context *ctx, struct
glsl_sampler *sampler)
void main()\n
{\n
gl_FragColor = %s(texSampler, %s);\n
+ gl_FragDepth = gl_FragColor.x;\n
}\n,
sampler-type,
sampler-func, sampler-texcoords);
@@ -515,6 +515,7 @@ setup_shader_for_sampler(struct gl_context *ctx, struct
glsl_sampler *sampler)
void main()\n
{\n
out_color = texture(texSampler, %s);\n
+ gl_FragDepth = out_color.x;\n
}\n,
_mesa_is_desktop_gl(ctx) ? 130 : 300 es,
sampler-type,
@@ -1661,98 +1662,18 @@ setup_glsl_blit_framebuffer(struct gl_context *ctx,
struct blit_state *blit,
GLenum target)
{
- const char *vs_source;
- char *fs_source;
- GLuint vs, fs;
- void *mem_ctx;
- GLuint ShaderProg;
- GLboolean texture_2d = (target == GL_TEXTURE_2D);
+ struct glsl_sampler *sampler;
/* target = GL_TEXTURE_RECTANGLE is not supported in GLES 3.0 */
- assert(_mesa_is_desktop_gl(ctx) || texture_2d);
+ assert(_mesa_is_desktop_gl(ctx) || target == GL_TEXTURE_2D);
setup_vertex_objects(blit-VAO, blit-VBO, true, 2, 2, 0);
/* Generate a relevant fragment shader program for the texture target */
- if ((target == GL_TEXTURE_2D blit-ShaderProg != 0) ||
- (target == GL_TEXTURE_RECTANGLE blit-RectShaderProg != 0)) {
- return;
- }
-
- mem_ctx = ralloc_context(NULL);
-
- if (ctx-Const.GLSLVersion 130) {
- vs_source =
- attribute vec2 position;\n
- attribute vec2 textureCoords;\n
- varying vec2 texCoords;\n
- void main()\n
- {\n
-texCoords = textureCoords;\n
-gl_Position = vec4(position, 0.0, 1.0);\n
- }\n;
-
- fs_source = ralloc_asprintf(mem_ctx,
- #ifdef GL_ES\n
- precision highp float;\n
- #endif\n
- uniform %s texSampler;\n
- varying vec2 texCoords;\n
- void main()\n
- {\n
- gl_FragColor = %s(texSampler,
texCoords);\n
- gl_FragDepth = gl_FragColor.r;\n
- }\n,
- texture_2d ? sampler2D : sampler2DRect,
- texture_2d ? texture2D : texture2DRect);
- }
- else {
- vs_source = ralloc_asprintf(mem_ctx,
- #version %s\n
- in vec2 position;\n
- in vec2 textureCoords;\n
- out vec2 texCoords;\n
- void main()\n
- {\n
- texCoords = textureCoords;\n
- gl_Position = vec4(position, 0.0,
1.0);\n
- }\n,
- _mesa_is_desktop_gl(ctx) ? 130 : 300 es);
- fs_source = ralloc_asprintf(mem_ctx,
- #version %s\n
- #ifdef GL_ES\n
- precision highp float;\n
- #endif\n
- uniform %s texSampler;\n
- in vec2 texCoords;\n
- out vec4 out_color;\n
- \n
Mesa (master): meta: Add rectangle textures to the shader-per-sampler-type table
Module: Mesa
Branch: master
Commit: 4825af972a7e318f34ca20a32e8e1597f90ae90c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4825af972a7e318f34ca20a32e8e1597f90ae90c
Author: Ian Romanick ian.d.roman...@intel.com
Date: Mon Dec 16 11:56:26 2013 -0800
meta: Add rectangle textures to the shader-per-sampler-type table
Rectangle textures were not necessary for mipmap generation (because
they cannot have mipmaps), but all of the future users of this common
code will need to support rectangle textures.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/common/meta.c |8
1 file changed, 8 insertions(+)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index f07d308..40e1f37 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -233,6 +233,7 @@ struct sampler_table {
struct glsl_sampler sampler_1d;
struct glsl_sampler sampler_2d;
struct glsl_sampler sampler_3d;
+ struct glsl_sampler sampler_rect;
struct glsl_sampler sampler_cubemap;
struct glsl_sampler sampler_1d_array;
struct glsl_sampler sampler_2d_array;
@@ -3434,6 +3435,11 @@ setup_texture_sampler(GLenum target, struct
sampler_table *table)
table-sampler_2d.func = texture2D;
table-sampler_2d.texcoords = texCoords.xy;
return table-sampler_2d;
+ case GL_TEXTURE_RECTANGLE:
+ table-sampler_rect.type = sampler2DRect;
+ table-sampler_rect.func = texture2DRect;
+ table-sampler_rect.texcoords = texCoords.xy;
+ return table-sampler_rect;
case GL_TEXTURE_3D:
/* Code for mipmap generation with 3D textures is not used yet.
* It's a sw fallback.
@@ -3470,6 +3476,7 @@ sampler_table_cleanup(struct sampler_table *table)
_mesa_DeleteObjectARB(table-sampler_1d.shader_prog);
_mesa_DeleteObjectARB(table-sampler_2d.shader_prog);
_mesa_DeleteObjectARB(table-sampler_3d.shader_prog);
+ _mesa_DeleteObjectARB(table-sampler_rect.shader_prog);
_mesa_DeleteObjectARB(table-sampler_cubemap.shader_prog);
_mesa_DeleteObjectARB(table-sampler_1d_array.shader_prog);
_mesa_DeleteObjectARB(table-sampler_2d_array.shader_prog);
@@ -3477,6 +3484,7 @@ sampler_table_cleanup(struct sampler_table *table)
table-sampler_1d.shader_prog = 0;
table-sampler_2d.shader_prog = 0;
table-sampler_3d.shader_prog = 0;
+ table-sampler_rect.shader_prog = 0;
table-sampler_cubemap.shader_prog = 0;
table-sampler_1d_array.shader_prog = 0;
table-sampler_2d_array.shader_prog = 0;
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Mesa (master): meta: Improve GLSL version check
Module: Mesa
Branch: master
Commit: d524654c34c42fff785dcdc08c9a73abd88fbf45
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d524654c34c42fff785dcdc08c9a73abd88fbf45
Author: Ian Romanick ian.d.roman...@intel.com
Date: Mon Dec 16 13:10:11 2013 -0800
meta: Improve GLSL version check
We want to use the GLSL 1.30-ish path for OpenGL ES 3.0.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/common/meta.c |7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 40e1f37..a40bf08 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -461,7 +461,12 @@ setup_shader_for_sampler(struct gl_context *ctx, struct
glsl_sampler *sampler)
if (sampler-shader_prog != 0)
return sampler-shader_prog;
- if (ctx-API == API_OPENGLES2 || ctx-Const.GLSLVersion 130) {
+ /* The version check is a little tricky. API is set to API_OPENGLES2 even
+* for OpenGL ES 3.0 contexts, and GLSLVersion may be set to 140, for
+* example, in an OpenGL ES 2.0 context.
+*/
+ if ((ctx-API == API_OPENGLES2 ctx-Version 30)
+ || ctx-Const.GLSLVersion 130) {
vs_source =
attribute vec2 position;\n
attribute vec3 textureCoords;\n
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Mesa (master): meta: Use GLSL to decompress 2D-array textures
Module: Mesa
Branch: master
Commit: b2ad3dbfa436ff205bffca5333ec0061208d52ae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b2ad3dbfa436ff205bffca5333ec0061208d52ae
Author: Ian Romanick ian.d.roman...@intel.com
Date: Mon Dec 16 15:01:54 2013 -0800
meta: Use GLSL to decompress 2D-array textures
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72582
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/common/meta.c | 35 ++-
1 file changed, 30 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 75fb7a5..b09e9a3 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -324,6 +324,8 @@ struct decompress_state
GLuint VAO;
GLuint VBO, FBO, RBO, Sampler;
GLint Width, Height;
+
+ struct sampler_table samplers;
};
/**
@@ -3860,6 +3862,10 @@ decompress_texture_image(struct gl_context *ctx,
GLuint fboDrawSave, fboReadSave;
GLuint rbSave;
GLuint samplerSave;
+ const bool use_glsl_version = ctx-Extensions.ARB_vertex_shader
+ ctx-Extensions.ARB_fragment_shader
+ (ctx-API != API_OPENGLES);
+ GLuint shaderProg = 0;
if (slice 0) {
assert(target == GL_TEXTURE_3D ||
@@ -3876,9 +3882,8 @@ decompress_texture_image(struct gl_context *ctx,
assert(!No compressed 3D textures.);
return;
- case GL_TEXTURE_2D_ARRAY:
case GL_TEXTURE_CUBE_MAP_ARRAY:
- /* These targets are just broken currently. */
+ /* This target is just broken currently. */
return;
case GL_TEXTURE_CUBE_MAP:
@@ -3924,7 +3929,20 @@ decompress_texture_image(struct gl_context *ctx,
decompress-Height = height;
}
- setup_ff_tnl_for_blit(decompress-VAO, decompress-VBO, 3);
+ if (use_glsl_version) {
+ struct glsl_sampler *sampler;
+
+ setup_vertex_objects(decompress-VAO, decompress-VBO, true,
+ 2, 3, 0);
+
+ /* Generate a relevant fragment shader program for the texture target */
+ sampler = setup_texture_sampler(target, decompress-samplers);
+ assert(sampler != NULL);
+
+ shaderProg = setup_shader_for_sampler(ctx, sampler);
+ } else {
+ setup_ff_tnl_for_blit(decompress-VAO, decompress-VBO, 3);
+ }
if (!decompress-Sampler) {
_mesa_GenSamplers(1, decompress-Sampler);
@@ -3968,7 +3986,13 @@ decompress_texture_image(struct gl_context *ctx,
/* setup texture state */
_mesa_BindTexture(target, texObj-Name);
- _mesa_set_enable(ctx, target, GL_TRUE);
+
+ if (!use_glsl_version)
+ _mesa_set_enable(ctx, target, GL_TRUE);
+ else {
+ assert(shaderProg != 0);
+ _mesa_UseProgram(shaderProg);
+ }
{
/* save texture object state */
@@ -4028,7 +4052,8 @@ decompress_texture_image(struct gl_context *ctx,
}
/* disable texture unit */
- _mesa_set_enable(ctx, target, GL_FALSE);
+ if (!use_glsl_version)
+ _mesa_set_enable(ctx, target, GL_FALSE);
_mesa_BindSampler(ctx-Texture.CurrentUnit, samplerSave);
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Mesa (master): meta: Get the correct info log
Module: Mesa Branch: master Commit: e68aa128492a65cc4eb610c3b8afa497d1868157 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e68aa128492a65cc4eb610c3b8afa497d1868157 Author: Ian Romanick ian.d.roman...@intel.com Date: Mon Dec 16 16:25:07 2013 -0800 meta: Get the correct info log Signed-off-by: Ian Romanick ian.d.roman...@intel.com Reviewed-by: Eric Anholt e...@anholt.net --- src/mesa/drivers/common/meta.c |2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c index c24b823..353aa39 100644 --- a/src/mesa/drivers/common/meta.c +++ b/src/mesa/drivers/common/meta.c @@ -403,7 +403,7 @@ compile_shader_with_debug(struct gl_context *ctx, GLenum target, const GLcharARB return 0; } - _mesa_GetProgramInfoLog(shader, size, NULL, info); + _mesa_GetShaderInfoLog(shader, size, NULL, info); _mesa_problem(ctx, meta program compile failed:\n%s\n source:\n%s\n, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): meta: Add storage to the vertex structure for R, G, B, and A
Module: Mesa
Branch: master
Commit: 75227a09681f1cb89c2a5e9257acb1c703335597
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=75227a09681f1cb89c2a5e9257acb1c703335597
Author: Ian Romanick ian.d.roman...@intel.com
Date: Sat Dec 14 19:32:39 2013 -0800
meta: Add storage to the vertex structure for R, G, B, and A
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/common/meta.c | 15 ++-
1 file changed, 6 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index eb75e58..73832e4 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -353,6 +353,7 @@ struct gl_meta_state
struct vertex {
GLfloat x, y, z, tex[4];
+ GLfloat r, g, b, a;
};
static void meta_glsl_blit_cleanup(struct blit_state *blit);
@@ -451,9 +452,6 @@ link_program_with_debug(struct gl_context *ctx, GLuint
program)
* \param color_size Number of components for attribute 1 / primary color.
* If this is 0, attribute 1 will not be set or enabled.
*
- * \note Either \c texcoord_size or \c color_size \b must be zero! The same
- * data location is used for both values, so only one can be active at a time.
- *
* \note If \c use_generic_attributes is \c true, \c color_size must be zero.
* Use \c texcoord_size instead.
*/
@@ -464,7 +462,6 @@ setup_vertex_objects(GLuint *VAO, GLuint *VBO, bool
use_generic_attributes,
{
if (*VAO == 0) {
assert(*VBO == 0);
- assert(color_size == 0 || texcoord_size == 0);
/* create vertex array object */
_mesa_GenVertexArrays(1, VAO);
@@ -502,7 +499,7 @@ setup_vertex_objects(GLuint *VAO, GLuint *VBO, bool
use_generic_attributes,
if (color_size 0) {
_mesa_ColorPointer(color_size, GL_FLOAT,
- sizeof(struct vertex), OFFSET(tex));
+ sizeof(struct vertex), OFFSET(r));
_mesa_EnableClientState(GL_COLOR_ARRAY);
}
}
@@ -2141,10 +2138,10 @@ _mesa_meta_Clear(struct gl_context *ctx, GLbitfield
buffers)
/* vertex colors */
for (i = 0; i 4; i++) {
- verts[i].tex[0] = ctx-Color.ClearColor.f[0];
- verts[i].tex[1] = ctx-Color.ClearColor.f[1];
- verts[i].tex[2] = ctx-Color.ClearColor.f[2];
- verts[i].tex[3] = ctx-Color.ClearColor.f[3];
+ verts[i].r = ctx-Color.ClearColor.f[0];
+ verts[i].g = ctx-Color.ClearColor.f[1];
+ verts[i].b = ctx-Color.ClearColor.f[2];
+ verts[i].a = ctx-Color.ClearColor.f[3];
}
/* upload new vertex data */
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Mesa (master): meta: Use common routine to configure fixed-function TNL state
Module: Mesa
Branch: master
Commit: 5e5d87ff329530664772a2c3ea4377c146591622
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e5d87ff329530664772a2c3ea4377c146591622
Author: Ian Romanick ian.d.roman...@intel.com
Date: Sat Dec 14 11:36:32 2013 -0800
meta: Use common routine to configure fixed-function TNL state
Also... glOrtho(-1.0, 1.0, -1.0, 1.0, -1.0, 1.0) *is* the identity
matrix, so drop the unnecessary call to _mesa_Ortho.
v2: Rename setup_ff_TNL_for_blit() to setup_ff_tnl_for_blit(). Seems
silly to capitalize one out of two to three acronyms in the name
(change by anholt, acked by idr).
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Brian Paul bri...@vmware.com (v1)
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/common/meta.c | 31 ---
1 file changed, 8 insertions(+), 23 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 5dbeaeb..eb75e58 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -1543,15 +1543,13 @@ init_blit_depth_pixels(struct gl_context *ctx)
}
static void
-setup_ff_blit_framebuffer(struct blit_state *blit)
+setup_ff_tnl_for_blit(GLuint *VAO, GLuint *VBO, unsigned texcoord_size)
{
- setup_vertex_objects(blit-VAO, blit-VBO, false, 2, 2, 0);
+ setup_vertex_objects(VAO, VBO, false, 2, texcoord_size, 0);
/* setup projection matrix */
_mesa_MatrixMode(GL_PROJECTION);
_mesa_LoadIdentity();
- _mesa_Ortho(-1.0, 1.0, -1.0, 1.0, -1.0, 1.0);
-
}
static void
@@ -1723,7 +1721,9 @@ blitframebuffer_texture(struct gl_context *ctx,
_mesa_UseProgram(blit-RectShaderProg);
}
else {
-setup_ff_blit_framebuffer(ctx-Meta-Blit);
+setup_ff_tnl_for_blit(ctx-Meta-Blit.VAO,
+ ctx-Meta-Blit.VBO,
+ 2);
}
_mesa_GenSamplers(1, sampler);
@@ -1902,7 +1902,7 @@ _mesa_meta_BlitFramebuffer(struct gl_context *ctx,
_mesa_UseProgram(blit-RectShaderProg);
}
else {
- setup_ff_blit_framebuffer(blit);
+ setup_ff_tnl_for_blit(blit-VAO, blit-VBO, 2);
}
/* Silence valgrind warnings about reading uninitialized stack. */
@@ -3346,19 +3346,6 @@ setup_texture_coords(GLenum faceTarget,
}
}
-
-static void
-setup_ff_generate_mipmap(struct gen_mipmap_state *mipmap)
-{
- setup_vertex_objects(mipmap-VAO, mipmap-VBO, false, 2, 3, 0);
-
- /* setup projection matrix */
- _mesa_MatrixMode(GL_PROJECTION);
- _mesa_LoadIdentity();
- _mesa_Ortho(-1.0, 1.0, -1.0, 1.0, -1.0, 1.0);
-}
-
-
static struct glsl_sampler *
setup_texture_sampler(GLenum target, struct gen_mipmap_state *mipmap)
{
@@ -3573,7 +3560,7 @@ _mesa_meta_GenerateMipmap(struct gl_context *ctx, GLenum
target,
_mesa_UseProgram(mipmap-ShaderProg);
}
else {
- setup_ff_generate_mipmap(mipmap);
+ setup_ff_tnl_for_blit(mipmap-VAO, mipmap-VBO, 3);
_mesa_set_enable(ctx, target, GL_TRUE);
}
@@ -4004,7 +3991,7 @@ decompress_texture_image(struct gl_context *ctx,
decompress-Height = height;
}
- setup_vertex_objects(decompress-VAO, decompress-VBO, false, 2, 3, 0);
+ setup_ff_tnl_for_blit(decompress-VAO, decompress-VBO, 3);
if (!decompress-Sampler) {
_mesa_GenSamplers(1, decompress-Sampler);
@@ -4041,8 +4028,6 @@ decompress_texture_image(struct gl_context *ctx,
verts[3].x = -1.0F;
verts[3].y = 1.0F;
- _mesa_MatrixMode(GL_PROJECTION);
- _mesa_LoadIdentity();
_mesa_set_viewport(ctx, 0, 0, 0, width, height);
/* upload new vertex data */
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Mesa (master): meta: Expand texture coordinate from vec3 to vec4
Module: Mesa
Branch: master
Commit: 10f7c544772a4b0b1f69d8e9fe4efd593c94418b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=10f7c544772a4b0b1f69d8e9fe4efd593c94418b
Author: Ian Romanick ian.d.roman...@intel.com
Date: Mon Dec 16 15:35:02 2013 -0800
meta: Expand texture coordinate from vec3 to vec4
This will be necessary to support cubemap array textures because they
use all four components.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/common/meta.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index b09e9a3..c24b823 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -471,7 +471,7 @@ setup_shader_for_sampler(struct gl_context *ctx, struct
glsl_sampler *sampler)
vs_source =
attribute vec2 position;\n
attribute vec3 textureCoords;\n
- varying vec3 texCoords;\n
+ varying vec4 texCoords;\n
void main()\n
{\n
texCoords = textureCoords;\n
@@ -484,7 +484,7 @@ setup_shader_for_sampler(struct gl_context *ctx, struct
glsl_sampler *sampler)
precision highp float;\n
#endif\n
uniform %s texSampler;\n
- varying vec3 texCoords;\n
+ varying vec4 texCoords;\n
void main()\n
{\n
gl_FragColor = %s(texSampler, %s);\n
@@ -497,8 +497,8 @@ setup_shader_for_sampler(struct gl_context *ctx, struct
glsl_sampler *sampler)
vs_source = ralloc_asprintf(mem_ctx,
#version %s\n
in vec2 position;\n
- in vec3 textureCoords;\n
- out vec3 texCoords;\n
+ in vec4 textureCoords;\n
+ out vec4 texCoords;\n
void main()\n
{\n
texCoords = textureCoords;\n
@@ -511,7 +511,7 @@ setup_shader_for_sampler(struct gl_context *ctx, struct
glsl_sampler *sampler)
precision highp float;\n
#endif\n
uniform %s texSampler;\n
- in vec3 texCoords;\n
+ in vec4 texCoords;\n
out vec4 out_color;\n
\n
void main()\n
@@ -3371,12 +3371,12 @@ setup_texture_sampler(GLenum target, struct
sampler_table *table)
*/
table-sampler_3d.type = sampler3D;
table-sampler_3d.func = texture3D;
- table-sampler_3d.texcoords = texCoords;
+ table-sampler_3d.texcoords = texCoords.xyz;
return table-sampler_3d;
case GL_TEXTURE_CUBE_MAP:
table-sampler_cubemap.type = samplerCube;
table-sampler_cubemap.func = textureCube;
- table-sampler_cubemap.texcoords = texCoords;
+ table-sampler_cubemap.texcoords = texCoords.xyz;
return table-sampler_cubemap;
case GL_TEXTURE_1D_ARRAY:
table-sampler_1d_array.type = sampler1DArray;
@@ -3386,7 +3386,7 @@ setup_texture_sampler(GLenum target, struct sampler_table
*table)
case GL_TEXTURE_2D_ARRAY:
table-sampler_2d_array.type = sampler2DArray;
table-sampler_2d_array.func = texture2DArray;
- table-sampler_2d_array.texcoords = texCoords;
+ table-sampler_2d_array.texcoords = texCoords.xyz;
return table-sampler_2d_array;
default:
_mesa_problem(NULL, Unexpected texture target 0x%x in
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Mesa (master): meta: Refactor the table of glsl_sampler structures
Module: Mesa
Branch: master
Commit: ed3bc38ee7dd4a11046036432ab40f753c4644b5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed3bc38ee7dd4a11046036432ab40f753c4644b5
Author: Ian Romanick ian.d.roman...@intel.com
Date: Mon Dec 16 11:52:38 2013 -0800
meta: Refactor the table of glsl_sampler structures
This will allow the same table of shader-per-sampler-type to be used for
paths in meta other than just mipmap generation. This is also the
reason the declarations of the structures was moved towards the top of
the file.
v2: Code formatting change suggested by Brian.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/common/meta.c | 128 ++--
1 file changed, 72 insertions(+), 56 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 6ffa416..d01d016 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -215,6 +215,28 @@ struct temp_texture
GLfloat Sright, Ttop; /** right, top texcoords */
};
+/**
+ * State for GLSL texture sampler which is used to generate fragment
+ * shader in _mesa_meta_generate_mipmap().
+ */
+struct glsl_sampler {
+ const char *type;
+ const char *func;
+ const char *texcoords;
+ GLuint shader_prog;
+};
+
+/**
+ * Table of all sampler types and shaders for accessing them.
+ */
+struct sampler_table {
+ struct glsl_sampler sampler_1d;
+ struct glsl_sampler sampler_2d;
+ struct glsl_sampler sampler_3d;
+ struct glsl_sampler sampler_cubemap;
+ struct glsl_sampler sampler_1d_array;
+ struct glsl_sampler sampler_2d_array;
+};
/**
* State for glBlitFramebufer()
@@ -281,17 +303,6 @@ struct bitmap_state
};
/**
- * State for GLSL texture sampler which is used to generate fragment
- * shader in _mesa_meta_generate_mipmap().
- */
-struct glsl_sampler {
- const char *type;
- const char *func;
- const char *texcoords;
- GLuint shader_prog;
-};
-
-/**
* State for _mesa_meta_generate_mipmap()
*/
struct gen_mipmap_state
@@ -301,12 +312,8 @@ struct gen_mipmap_state
GLuint FBO;
GLuint Sampler;
GLuint ShaderProg;
- struct glsl_sampler sampler_1d;
- struct glsl_sampler sampler_2d;
- struct glsl_sampler sampler_3d;
- struct glsl_sampler sampler_cubemap;
- struct glsl_sampler sampler_1d_array;
- struct glsl_sampler sampler_2d_array;
+
+ struct sampler_table samplers;
};
/**
@@ -356,12 +363,16 @@ struct vertex {
GLfloat r, g, b, a;
};
+static struct glsl_sampler *
+setup_texture_sampler(GLenum target, struct sampler_table *table);
+
static void meta_glsl_blit_cleanup(struct blit_state *blit);
static void cleanup_temp_texture(struct temp_texture *tex);
static void meta_glsl_clear_cleanup(struct clear_state *clear);
static void meta_glsl_generate_mipmap_cleanup(struct gen_mipmap_state *mipmap);
static void meta_decompress_cleanup(struct decompress_state *decompress);
static void meta_drawpix_cleanup(struct drawpix_state *drawpix);
+static void sampler_table_cleanup(struct sampler_table *table);
static GLuint
compile_shader_with_debug(struct gl_context *ctx, GLenum target, const
GLcharARB *source)
@@ -3320,42 +3331,42 @@ setup_texture_coords(GLenum faceTarget,
}
static struct glsl_sampler *
-setup_texture_sampler(GLenum target, struct gen_mipmap_state *mipmap)
+setup_texture_sampler(GLenum target, struct sampler_table *table)
{
switch(target) {
case GL_TEXTURE_1D:
- mipmap-sampler_1d.type = sampler1D;
- mipmap-sampler_1d.func = texture1D;
- mipmap-sampler_1d.texcoords = texCoords.x;
- return mipmap-sampler_1d;
+ table-sampler_1d.type = sampler1D;
+ table-sampler_1d.func = texture1D;
+ table-sampler_1d.texcoords = texCoords.x;
+ return table-sampler_1d;
case GL_TEXTURE_2D:
- mipmap-sampler_2d.type = sampler2D;
- mipmap-sampler_2d.func = texture2D;
- mipmap-sampler_2d.texcoords = texCoords.xy;
- return mipmap-sampler_2d;
+ table-sampler_2d.type = sampler2D;
+ table-sampler_2d.func = texture2D;
+ table-sampler_2d.texcoords = texCoords.xy;
+ return table-sampler_2d;
case GL_TEXTURE_3D:
/* Code for mipmap generation with 3D textures is not used yet.
* It's a sw fallback.
*/
- mipmap-sampler_3d.type = sampler3D;
- mipmap-sampler_3d.func = texture3D;
- mipmap-sampler_3d.texcoords = texCoords;
- return mipmap-sampler_3d;
+ table-sampler_3d.type = sampler3D;
+ table-sampler_3d.func = texture3D;
+ table-sampler_3d.texcoords = texCoords;
+ return table-sampler_3d;
case GL_TEXTURE_CUBE_MAP:
- mipmap-sampler_cubemap.type = samplerCube;
- mipmap-sampler_cubemap.func = textureCube;
- mipmap-sampler_cubemap.texcoords = texCoords;
- return mipmap-sampler_cubemap;
+ table-sampler_cubemap.type = samplerCube
Mesa (master): meta: Refactor shader generation code out of mipmap generation path
Module: Mesa
Branch: master
Commit: f5a477ab76b6e0b268387699cd2253a43db0dfae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5a477ab76b6e0b268387699cd2253a43db0dfae
Author: Ian Romanick ian.d.roman...@intel.com
Date: Mon Dec 16 11:54:08 2013 -0800
meta: Refactor shader generation code out of mipmap generation path
This is quite like code we want for blits. Pull it out so that it can
be shared by other paths.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/common/meta.c | 169 +---
1 file changed, 91 insertions(+), 78 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index d01d016..f07d308 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -442,6 +442,96 @@ link_program_with_debug(struct gl_context *ctx, GLuint
program)
}
/**
+ * Generate a generic shader to blit from a texture to a framebuffer
+ *
+ * \param ctx Current GL context
+ * \param texTarget Texture target that will be the source of the blit
+ *
+ * \returns a handle to a shader program on success or zero on failure.
+ */
+static GLuint
+setup_shader_for_sampler(struct gl_context *ctx, struct glsl_sampler *sampler)
+{
+ const char *vs_source;
+ char *fs_source;
+ GLuint vs, fs;
+ void *const mem_ctx = ralloc_context(NULL);
+
+ if (sampler-shader_prog != 0)
+ return sampler-shader_prog;
+
+ if (ctx-API == API_OPENGLES2 || ctx-Const.GLSLVersion 130) {
+ vs_source =
+ attribute vec2 position;\n
+ attribute vec3 textureCoords;\n
+ varying vec3 texCoords;\n
+ void main()\n
+ {\n
+texCoords = textureCoords;\n
+gl_Position = vec4(position, 0.0, 1.0);\n
+ }\n;
+
+ fs_source = ralloc_asprintf(mem_ctx,
+ #extension GL_EXT_texture_array : enable\n
+ #ifdef GL_ES\n
+ precision highp float;\n
+ #endif\n
+ uniform %s texSampler;\n
+ varying vec3 texCoords;\n
+ void main()\n
+ {\n
+ gl_FragColor = %s(texSampler, %s);\n
+ }\n,
+ sampler-type,
+ sampler-func, sampler-texcoords);
+ }
+ else {
+ vs_source = ralloc_asprintf(mem_ctx,
+ #version %s\n
+ in vec2 position;\n
+ in vec3 textureCoords;\n
+ out vec3 texCoords;\n
+ void main()\n
+ {\n
+ texCoords = textureCoords;\n
+ gl_Position = vec4(position, 0.0,
1.0);\n
+ }\n,
+ _mesa_is_desktop_gl(ctx) ? 130 : 300 es);
+ fs_source = ralloc_asprintf(mem_ctx,
+ #version %s\n
+ #ifdef GL_ES\n
+ precision highp float;\n
+ #endif\n
+ uniform %s texSampler;\n
+ in vec3 texCoords;\n
+ out vec4 out_color;\n
+ \n
+ void main()\n
+ {\n
+ out_color = texture(texSampler, %s);\n
+ }\n,
+ _mesa_is_desktop_gl(ctx) ? 130 : 300 es,
+ sampler-type,
+ sampler-texcoords);
+ }
+
+ vs = compile_shader_with_debug(ctx, GL_VERTEX_SHADER, vs_source);
+ fs = compile_shader_with_debug(ctx, GL_FRAGMENT_SHADER, fs_source);
+
+ sampler-shader_prog = _mesa_CreateProgramObjectARB();
+ _mesa_AttachShader(sampler-shader_prog, fs);
+ _mesa_DeleteObjectARB(fs);
+ _mesa_AttachShader(sampler-shader_prog, vs);
+ _mesa_DeleteObjectARB(vs);
+ _mesa_BindAttribLocation(sampler-shader_prog, 0, position);
+ _mesa_BindAttribLocation(sampler-shader_prog, 1, texcoords);
+ link_program_with_debug(ctx, sampler-shader_prog);
+ ralloc_free(mem_ctx);
+
+ return sampler-shader_prog;
+}
+
+/**
* Configure vertex buffer and vertex array objects for tests
*
* Regardless of whether a new VAO and new VBO are created, the objects
@@ -3398,91 +3488,14 @@ setup_glsl_generate_mipmap(struct gl_context *ctx,
GLenum target)
{
struct glsl_sampler
Mesa (master): meta: Enable cubemap array texture support to decompress_texture_image
Module: Mesa
Branch: master
Commit: 4cffd3e791e4696ac672f2053b821937a2a5fb58
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4cffd3e791e4696ac672f2053b821937a2a5fb58
Author: Ian Romanick ian.d.roman...@intel.com
Date: Mon Dec 16 17:11:15 2013 -0800
meta: Enable cubemap array texture support to decompress_texture_image
Fixed piglit test getteximage-targets S3TC CUBE_ARRAY on systems that
don't have libtxc_dxtn installed.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/common/meta.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/common/meta.c b/src/mesa/drivers/common/meta.c
index 4d4f877..8569391 100644
--- a/src/mesa/drivers/common/meta.c
+++ b/src/mesa/drivers/common/meta.c
@@ -3881,7 +3881,8 @@ decompress_texture_image(struct gl_context *ctx,
if (slice 0) {
assert(target == GL_TEXTURE_3D ||
- target == GL_TEXTURE_2D_ARRAY);
+ target == GL_TEXTURE_2D_ARRAY ||
+ target == GL_TEXTURE_CUBE_MAP_ARRAY);
}
switch (target) {
@@ -3895,8 +3896,8 @@ decompress_texture_image(struct gl_context *ctx,
return;
case GL_TEXTURE_CUBE_MAP_ARRAY:
- /* This target is just broken currently. */
- return;
+ faceTarget = GL_TEXTURE_CUBE_MAP_POSITIVE_X + (slice % 6);
+ break;
case GL_TEXTURE_CUBE_MAP:
faceTarget = GL_TEXTURE_CUBE_MAP_POSITIVE_X + texImage-Face;
@@ -3945,7 +3946,7 @@ decompress_texture_image(struct gl_context *ctx,
struct glsl_sampler *sampler;
setup_vertex_objects(decompress-VAO, decompress-VBO, true,
- 2, 3, 0);
+ 2, 4, 0);
/* Generate a relevant fragment shader program for the texture target */
sampler = setup_texture_sampler(target, decompress-samplers);
@@ -4097,8 +4098,7 @@ _mesa_meta_GetTexImage(struct gl_context *ctx,
* unsigned, normalized values. We could handle signed and unnormalized
* with floating point renderbuffers...
*/
- if (texImage-TexObject-Target != GL_TEXTURE_CUBE_MAP_ARRAY
-_mesa_is_format_compressed(texImage-TexFormat)
+ if (_mesa_is_format_compressed(texImage-TexFormat)
_mesa_get_format_datatype(texImage-TexFormat)
== GL_UNSIGNED_NORMALIZED) {
struct gl_texture_object *texObj = texImage-TexObject;
@@ -4107,7 +4107,8 @@ _mesa_meta_GetTexImage(struct gl_context *ctx,
_mesa_unlock_texture(ctx, texObj);
for (slice = 0; slice texImage-Depth; slice++) {
void *dst;
- if (texImage-TexObject-Target == GL_TEXTURE_2D_ARRAY) {
+ if (texImage-TexObject-Target == GL_TEXTURE_2D_ARRAY
+ || texImage-TexObject-Target == GL_TEXTURE_CUBE_MAP_ARRAY) {
/* Setup pixel packing. SkipPixels and SkipRows will be applied
* in the decompress_texture_image() function's call to
* glReadPixels but we need to compute the dest slice's address
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Mesa (master): glsl: Optimize triop_csel with all-true or all-false.
Module: Mesa Branch: master Commit: 1e12dafcac4aac50bc588cead4cc0d6291718edd URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e12dafcac4aac50bc588cead4cc0d6291718edd Author: Eric Anholt e...@anholt.net Date: Fri Nov 1 12:29:12 2013 -0700 glsl: Optimize triop_csel with all-true or all-false. Reviewed-by: Matt Turner matts...@gmail.com --- src/glsl/opt_algebraic.cpp |7 +++ 1 file changed, 7 insertions(+) diff --git a/src/glsl/opt_algebraic.cpp b/src/glsl/opt_algebraic.cpp index 7863fe8..1b4d319 100644 --- a/src/glsl/opt_algebraic.cpp +++ b/src/glsl/opt_algebraic.cpp @@ -571,6 +571,13 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir) } break; + case ir_triop_csel: + if (is_vec_one(op_const[0])) +return ir-operands[1]; + if (is_vec_zero(op_const[0])) +return ir-operands[2]; + break; + default: break; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Remove redundant check in blitter-based glBlitFramebuffer().
Module: Mesa
Branch: master
Commit: b5e5f34dd2d47622a41ff9908088c37dfbcca4cd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b5e5f34dd2d47622a41ff9908088c37dfbcca4cd
Author: Eric Anholt e...@anholt.net
Date: Mon Sep 30 15:19:54 2013 -0700
i965: Remove redundant check in blitter-based glBlitFramebuffer().
The intel_miptree_blit() code checks the format for us now, plus it
handles xrgb vs argb for us.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/intel_fbo.c | 10 --
1 file changed, 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
b/src/mesa/drivers/dri/i965/intel_fbo.c
index d99f9a6..6180fc6 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -739,16 +739,6 @@ intel_blit_framebuffer_with_blitter(struct gl_context *ctx,
return mask;
}
- mesa_format src_format = _mesa_get_srgb_format_linear(src_rb-Format);
- mesa_format dst_format = _mesa_get_srgb_format_linear(dst_rb-Format);
- if (src_format != dst_format) {
-perf_debug(glBlitFramebuffer(): unsupported blit from %s to %s.
- Falling back to software rendering.\n,
- _mesa_get_format_name(src_format),
- _mesa_get_format_name(dst_format));
-return mask;
- }
-
if (!intel_miptree_blit(brw,
src_irb-mt,
src_irb-mt_level, src_irb-mt_layer,
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Mesa (master): glsl: Optimize ~~x into x.
Module: Mesa
Branch: master
Commit: 2c2aa353366c610382273bea10656e6d6960ce3b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c2aa353366c610382273bea10656e6d6960ce3b
Author: Eric Anholt e...@anholt.net
Date: Sat Jan 18 10:36:28 2014 -0800
glsl: Optimize ~~x into x.
v2: Fix pasteo of an extra abs being inserted (caught by many). Rewrite
to drop the silly switch statement.
Reviewed-by: Matt Turner matts...@gmail.com (v1)
---
src/glsl/opt_algebraic.cpp |5 +
1 file changed, 5 insertions(+)
diff --git a/src/glsl/opt_algebraic.cpp b/src/glsl/opt_algebraic.cpp
index d1f6435..681973d 100644
--- a/src/glsl/opt_algebraic.cpp
+++ b/src/glsl/opt_algebraic.cpp
@@ -218,6 +218,11 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir)
this-mem_ctx = ralloc_parent(ir);
switch (ir-operation) {
+ case ir_unop_bit_not:
+ if (op_expr[0] op_expr[0]-operation == ir_unop_bit_not)
+ return op_expr[0]-operands[0];
+ break;
+
case ir_unop_abs:
if (op_expr[0] == NULL)
break;
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Mesa (master): glsl: Optimize log(exp(x)) and exp(log(x)) into x.
Module: Mesa
Branch: master
Commit: 6d7c123d6ce46e71ef22e431b76e972b9be1a157
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6d7c123d6ce46e71ef22e431b76e972b9be1a157
Author: Eric Anholt e...@anholt.net
Date: Sat Jan 18 10:47:19 2014 -0800
glsl: Optimize log(exp(x)) and exp(log(x)) into x.
Reviewed-by: Matt Turner matts...@gmail.com
---
src/glsl/opt_algebraic.cpp | 36
1 file changed, 36 insertions(+)
diff --git a/src/glsl/opt_algebraic.cpp b/src/glsl/opt_algebraic.cpp
index 681973d..1e71581 100644
--- a/src/glsl/opt_algebraic.cpp
+++ b/src/glsl/opt_algebraic.cpp
@@ -245,6 +245,42 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir)
}
break;
+ case ir_unop_exp:
+ if (op_expr[0] == NULL)
+break;
+
+ if (op_expr[0]-operation == ir_unop_log) {
+ return op_expr[0]-operands[0];
+ }
+ break;
+
+ case ir_unop_log:
+ if (op_expr[0] == NULL)
+break;
+
+ if (op_expr[0]-operation == ir_unop_exp) {
+ return op_expr[0]-operands[0];
+ }
+ break;
+
+ case ir_unop_exp2:
+ if (op_expr[0] == NULL)
+break;
+
+ if (op_expr[0]-operation == ir_unop_log2) {
+ return op_expr[0]-operands[0];
+ }
+ break;
+
+ case ir_unop_log2:
+ if (op_expr[0] == NULL)
+break;
+
+ if (op_expr[0]-operation == ir_unop_exp2) {
+ return op_expr[0]-operands[0];
+ }
+ break;
+
case ir_unop_logic_not: {
enum ir_expression_operation new_op = ir_unop_logic_not;
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Mesa (master): glsl: Optimize pow(x, 1) - x.
Module: Mesa Branch: master Commit: d72956790fed5f62b8eea5938ed432544530f7bd URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d72956790fed5f62b8eea5938ed432544530f7bd Author: Eric Anholt e...@anholt.net Date: Sat Jan 18 10:57:29 2014 -0800 glsl: Optimize pow(x, 1) - x. total instructions in shared programs: 1627826 - 1627754 (-0.00%) instructions in affected programs: 6640 - 6568 (-1.08%) GAINED:0 LOST: 0 (HoN and savage2) Reviewed-by: Matt Turner matts...@gmail.com --- src/glsl/opt_algebraic.cpp |4 1 file changed, 4 insertions(+) diff --git a/src/glsl/opt_algebraic.cpp b/src/glsl/opt_algebraic.cpp index 1e71581..953b03c 100644 --- a/src/glsl/opt_algebraic.cpp +++ b/src/glsl/opt_algebraic.cpp @@ -520,6 +520,10 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir) if (is_vec_one(op_const[0])) return op_const[0]; + /* x^1 == x */ + if (is_vec_one(op_const[1])) + return ir-operands[0]; + /* pow(2,x) == exp2(x) */ if (is_vec_two(op_const[0])) return expr(ir_unop_exp2, ir-operands[1]); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Add some informative debug when the X Server botches DRI2 GetBuffers.
Module: Mesa
Branch: master
Commit: 0f6279bab29614e3764a333242680ead78068d91
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0f6279bab29614e3764a333242680ead78068d91
Author: Eric Anholt e...@anholt.net
Date: Mon Dec 30 18:19:21 2013 -0800
i965: Add some informative debug when the X Server botches DRI2 GetBuffers.
We've had various bug reports over the years where miptrees are missing,
and when I screwed it up while adding DRI2 to the modesetting driver, I
figured I should put the info necessary for debug here.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_context.c | 12 +++-
1 file changed, 11 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 6a3a4f1..1879abe 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1290,14 +1290,24 @@ intel_process_dri2_buffer(struct brw_context *brw,
buffer-pitch,
buffer-name,
buffer_name);
- if (!region)
+ if (!region) {
+ fprintf(stderr,
+ Failed to make region for returned DRI2 buffer
+ (%dx%d, named %d).\n
+ This is likely a bug in the X Server that will lead to a
+ crash soon.\n,
+ drawable-w, drawable-h, buffer-name);
return;
+ }
rb-mt = intel_miptree_create_for_dri2_buffer(brw,
buffer-attachment,
intel_rb_format(rb),
num_samples,
region);
+
+ assert(rb-mt);
+
intel_region_release(region);
}
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Mesa (master): glsl: Optimize lrp(x, x, coefficient) -- x.
Module: Mesa
Branch: master
Commit: 44577c48573acdbc8a708e6613f367507e9eafc5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=44577c48573acdbc8a708e6613f367507e9eafc5
Author: Eric Anholt e...@anholt.net
Date: Sat Jan 18 11:00:51 2014 -0800
glsl: Optimize lrp(x, x, coefficient) -- x.
total instructions in shared programs: 1627754 - 1624534 (-0.20%)
instructions in affected programs: 45748 - 42528 (-7.04%)
GAINED:3
LOST: 0
(serious sam, humus domino demo)
Reviewed-by: Matt Turner matts...@gmail.com
---
src/glsl/opt_algebraic.cpp |2 ++
1 file changed, 2 insertions(+)
diff --git a/src/glsl/opt_algebraic.cpp b/src/glsl/opt_algebraic.cpp
index 953b03c..392051f 100644
--- a/src/glsl/opt_algebraic.cpp
+++ b/src/glsl/opt_algebraic.cpp
@@ -553,6 +553,8 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir)
return ir-operands[0];
} else if (is_vec_one(op_const[2])) {
return ir-operands[1];
+ } else if (ir-operands[0]-equals(ir-operands[1])) {
+ return ir-operands[0];
}
break;
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Mesa (master): glsl: Optimize various cases of fma (aka MAD).
Module: Mesa
Branch: master
Commit: de796b0ef09f05ca3f8a568ed07293e28ae697b0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=de796b0ef09f05ca3f8a568ed07293e28ae697b0
Author: Eric Anholt e...@anholt.net
Date: Sat Jan 18 11:06:16 2014 -0800
glsl: Optimize various cases of fma (aka MAD).
Reviewed-by: Matt Turner matts...@gmail.com
---
src/glsl/opt_algebraic.cpp | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/glsl/opt_algebraic.cpp b/src/glsl/opt_algebraic.cpp
index 392051f..7863fe8 100644
--- a/src/glsl/opt_algebraic.cpp
+++ b/src/glsl/opt_algebraic.cpp
@@ -547,6 +547,19 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir)
break;
+ case ir_triop_fma:
+ /* Operands are op0 * op1 + op2. */
+ if (is_vec_zero(op_const[0]) || is_vec_zero(op_const[1])) {
+ return ir-operands[2];
+ } else if (is_vec_zero(op_const[2])) {
+ return mul(ir-operands[0], ir-operands[1]);
+ } else if (is_vec_one(op_const[0])) {
+ return add(ir-operands[1], ir-operands[2]);
+ } else if (is_vec_one(op_const[1])) {
+ return add(ir-operands[0], ir-operands[2]);
+ }
+ break;
+
case ir_triop_lrp:
/* Operands are (x, y, a). */
if (is_vec_zero(op_const[2])) {
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Mesa (master): dri3: Track current Present swap mode and adjust buffer counts
Module: Mesa
Branch: master
Commit: 3fbd1b0cb576b46ac8df2697cb388db78f48012d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3fbd1b0cb576b46ac8df2697cb388db78f48012d
Author: Keith Packard kei...@keithp.com
Date: Sun Jan 26 16:14:29 2014 -0800
dri3: Track current Present swap mode and adjust buffer counts
This automatically adjusts the number of buffers that we want based on
what swapping mode the X server is using and the current swap interval:
swap mode intervalbuffers
copy 0 1
copy0 2
flip 0 2
flip0 3
Note that flip with swap interval 0 is currently limited to twice the
underlying refresh rate because of how the kernel manages flipping. Moving
from 3 to 4 buffers would help, but that seems ridiculous.
v2: Just update num_back at the point that the values that change num_back
change. This means we'll have the updated value at the point that the
freeing of old going-to-be-unused backbuffers happens, which might not
have been the case before (change by anholt, acked by keithp).
Signed-off-by: Keith Packard kei...@keithp.com
Signed-off-by: Eric Anholt e...@anholt.net
Reviewed-by: Eric Anholt e...@anholt.net
---
src/glx/dri3_glx.c | 35 ++-
src/glx/dri3_priv.h | 24 +---
2 files changed, 35 insertions(+), 24 deletions(-)
diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c
index 94f0eca..70ec057 100644
--- a/src/glx/dri3_glx.c
+++ b/src/glx/dri3_glx.c
@@ -270,6 +270,16 @@ static void
dri3_free_render_buffer(struct dri3_drawable *pdraw, struct dri3_buffer
*buffer);
static void
+dri3_update_num_back(struct dri3_drawable *priv)
+{
+ priv-num_back = 1;
+ if (priv-flipping)
+ priv-num_back++;
+ if (priv-swap_interval == 0)
+ priv-num_back++;
+}
+
+static void
dri3_destroy_drawable(__GLXDRIdrawable *base)
{
struct dri3_screen *psc = (struct dri3_screen *) base-psc;
@@ -326,6 +336,8 @@ dri3_create_drawable(struct glx_screen *base, XID xDrawable,
break;
}
+ dri3_update_num_back(pdraw);
+
(void) __glXInitialize(psc-base.dpy);
/* Create a new drawable */
@@ -373,6 +385,15 @@ dri3_handle_present_event(struct dri3_drawable *priv,
xcb_present_generic_event_
priv-recv_sbc = (priv-send_sbc 0xLL) | ce-serial;
if (priv-recv_sbc priv-send_sbc)
priv-recv_sbc -= 0x1;
+ switch (ce-mode) {
+ case XCB_PRESENT_COMPLETE_MODE_FLIP:
+priv-flipping = true;
+break;
+ case XCB_PRESENT_COMPLETE_MODE_COPY:
+priv-flipping = false;
+break;
+ }
+ dri3_update_num_back(priv);
} else {
priv-recv_msc_serial = ce-serial;
}
@@ -389,6 +410,10 @@ dri3_handle_present_event(struct dri3_drawable *priv,
xcb_present_generic_event_
if (buf buf-pixmap == ie-pixmap) {
buf-busy = 0;
+if (priv-num_back = b b DRI3_MAX_BACK) {
+ dri3_free_render_buffer(priv, buf);
+ priv-buffers[b] = NULL;
+}
break;
}
}
@@ -1067,10 +1092,9 @@ dri3_find_back(xcb_connection_t *c, struct dri3_drawable
*priv)
xcb_present_generic_event_t *ge;
for (;;) {
-
- for (b = 0; b DRI3_NUM_BACK; b++) {
- intid = DRI3_BACK_ID(b);
- struct dri3_buffer*buffer = priv-buffers[id];
+ for (b = 0; b priv-num_back; b++) {
+ int id = DRI3_BACK_ID(b);
+ struct dri3_buffer *buffer = priv-buffers[id];
if (!buffer)
return b;
@@ -1185,7 +1209,7 @@ dri3_free_buffers(__DRIdrawable *driDrawable,
switch (buffer_type) {
case dri3_buffer_back:
first_id = DRI3_BACK_ID(0);
- n_id = DRI3_NUM_BACK;
+ n_id = DRI3_MAX_BACK;
break;
case dri3_buffer_front:
first_id = DRI3_FRONT_ID;
@@ -1437,6 +1461,7 @@ dri3_set_swap_interval(__GLXDRIdrawable *pdraw, int
interval)
}
priv-swap_interval = interval;
+ dri3_update_num_back(priv);
return 0;
}
diff --git a/src/glx/dri3_priv.h b/src/glx/dri3_priv.h
index 9d142cf..1d124f8 100644
--- a/src/glx/dri3_priv.h
+++ b/src/glx/dri3_priv.h
@@ -143,25 +143,9 @@ struct dri3_context
__DRIcontext *driContext;
};
-#define DRI3_NUM_BACK 2
+#define DRI3_MAX_BACK 3
#define DRI3_BACK_ID(i) (i)
-#define DRI3_FRONT_ID (DRI3_NUM_BACK)
-
-static inline int
-dri3_buf_id_next(int buf_id)
-{
- if (buf_id == DRI3_NUM_BACK - 1)
- return 0;
- return buf_id + 1;
-}
-
-static inline int
-dri3_buf_id_prev(int buf_id)
-{
- if (buf_id == 0)
- return DRI3_NUM_BACK - 1;
- return buf_id - 1;
-}
+#define DRI3_FRONT_ID (DRI3_MAX_BACK)
static inline int
dri3_pixmap_buf_id(enum dri3_buffer_type buffer_type)
@@ -172,7 +156,7
Mesa (master): dri3, i915, i965: Add __DRI_IMAGE_FOURCC_SARGB8888
Module: Mesa
Branch: master
Commit: aea4757eb4caf6f980fdaa2b9345f26329c29d12
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aea4757eb4caf6f980fdaa2b9345f26329c29d12
Author: Keith Packard kei...@keithp.com
Date: Thu Nov 21 20:08:35 2013 -0800
dri3, i915, i965: Add __DRI_IMAGE_FOURCC_SARGB
The __DRIimage createImageFromFds function takes a fourcc code, but there was
no fourcc code that match __DRI_IMAGE_FORMAT_SARGB8. This adds a define for
that format, adds a translation in DRI3 from __DRI_IMAGE_FORMAT_SARGB8 to
__DRI_IMAGE_FOURCC_SARGB and then adds translations *back* to
__IMAGE_FORMAT_SARGB8 in both the i915 and i965 drivers.
I'll refrain from comments on whether I think having two separate sets of
format defines in dri_interface.h is a good idea or not...
Fixes piglit glx-tfp and glx-visuals-depth
Signed-off-by: Keith Packard kei...@keithp.com
Reviewed-by: Eric Anholt e...@anholt.net
---
include/GL/internal/dri_interface.h |1 +
src/glx/dri3_glx.c |1 +
src/mesa/drivers/dri/i915/intel_screen.c |3 +++
src/mesa/drivers/dri/i965/intel_screen.c |3 +++
4 files changed, 8 insertions(+)
diff --git a/include/GL/internal/dri_interface.h
b/include/GL/internal/dri_interface.h
index 81f7e60..9e82904 100644
--- a/include/GL/internal/dri_interface.h
+++ b/include/GL/internal/dri_interface.h
@@ -1041,6 +1041,7 @@ struct __DRIdri2ExtensionRec {
#define __DRI_IMAGE_FOURCC_XRGB0x34325258
#define __DRI_IMAGE_FOURCC_ABGR0x34324241
#define __DRI_IMAGE_FOURCC_XBGR0x34324258
+#define __DRI_IMAGE_FOURCC_SARGB0x83324258
#define __DRI_IMAGE_FOURCC_YUV410 0x39565559
#define __DRI_IMAGE_FOURCC_YUV411 0x31315559
#define __DRI_IMAGE_FOURCC_YUV420 0x32315559
diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c
index c91f500..94f0eca 100644
--- a/src/glx/dri3_glx.c
+++ b/src/glx/dri3_glx.c
@@ -937,6 +937,7 @@ image_format_to_fourcc(int format)
/* Convert from __DRI_IMAGE_FORMAT to __DRI_IMAGE_FOURCC (sigh) */
switch (format) {
+ case __DRI_IMAGE_FORMAT_SARGB8: return __DRI_IMAGE_FOURCC_SARGB;
case __DRI_IMAGE_FORMAT_RGB565: return __DRI_IMAGE_FOURCC_RGB565;
case __DRI_IMAGE_FORMAT_XRGB: return __DRI_IMAGE_FOURCC_XRGB;
case __DRI_IMAGE_FORMAT_ARGB: return __DRI_IMAGE_FOURCC_ARGB;
diff --git a/src/mesa/drivers/dri/i915/intel_screen.c
b/src/mesa/drivers/dri/i915/intel_screen.c
index f3c0fa3..b34c815 100644
--- a/src/mesa/drivers/dri/i915/intel_screen.c
+++ b/src/mesa/drivers/dri/i915/intel_screen.c
@@ -184,6 +184,9 @@ static struct intel_image_format intel_image_formats[] = {
{ __DRI_IMAGE_FOURCC_ARGB, __DRI_IMAGE_COMPONENTS_RGBA, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB, 4 } } },
+ { __DRI_IMAGE_FOURCC_SARGB, __DRI_IMAGE_COMPONENTS_RGBA, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8, 4 } } },
+
{ __DRI_IMAGE_FOURCC_XRGB, __DRI_IMAGE_COMPONENTS_RGB, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB, 4 }, } },
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index 7700a4e..b2bd47c 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -220,6 +220,9 @@ static struct intel_image_format intel_image_formats[] = {
{ __DRI_IMAGE_FOURCC_ARGB, __DRI_IMAGE_COMPONENTS_RGBA, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_ARGB, 4 } } },
+ { __DRI_IMAGE_FOURCC_SARGB, __DRI_IMAGE_COMPONENTS_RGBA, 1,
+ { { 0, 0, 0, __DRI_IMAGE_FORMAT_SARGB8, 4 } } },
+
{ __DRI_IMAGE_FOURCC_XRGB, __DRI_IMAGE_COMPONENTS_RGB, 1,
{ { 0, 0, 0, __DRI_IMAGE_FORMAT_XRGB, 4 }, } },
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Mesa (master): dri3: Flush XCB before blocking for special events
Module: Mesa Branch: master Commit: f12d6d613acd3f85309e4a3063871b188c93a145 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f12d6d613acd3f85309e4a3063871b188c93a145 Author: Keith Packard kei...@keithp.com Date: Mon Nov 25 22:57:42 2013 -0800 dri3: Flush XCB before blocking for special events XCB doesn't flush the output buffer automatically, so we have to call xcb_flush ourselves before waiting. Signed-off-by: Keith Packard kei...@keithp.com Reviewed-by: Eric Anholt e...@anholt.net --- src/glx/dri3_glx.c |2 ++ 1 file changed, 2 insertions(+) diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c index 79bc5f0..c91f500 100644 --- a/src/glx/dri3_glx.c +++ b/src/glx/dri3_glx.c @@ -406,6 +406,7 @@ dri3_wait_for_event(__GLXDRIdrawable *pdraw) xcb_generic_event_t *ev; xcb_present_generic_event_t *ge; + xcb_flush(c); ev = xcb_wait_for_special_event(c, priv-special_event); if (!ev) return false; @@ -1075,6 +1076,7 @@ dri3_find_back(xcb_connection_t *c, struct dri3_drawable *priv) if (!buffer-busy) return b; } + xcb_flush(c); ev = xcb_wait_for_special_event(c, priv-special_event); if (!ev) return -1; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): dri3: Fix dri3_wait_for_sbc to wait for completion of requested SBC
Module: Mesa
Branch: master
Commit: 1525474eadf5ca000162e05b99d591998d1ed3f6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1525474eadf5ca000162e05b99d591998d1ed3f6
Author: Keith Packard kei...@keithp.com
Date: Mon Nov 25 21:21:40 2013 -0800
dri3: Fix dri3_wait_for_sbc to wait for completion of requested SBC
Eric figured out that glXWaitForSbcOML wanted to block until the requested
SBC had been completed, which means to wait until the
PresentCompleteNotify event for that SBC had been received.
This replaces the simple sleep(1) loop (which was bogus) with a loop that
just checks to see if we've seen the specified SBC value come back in a
PresentCompleteNotify event yet.
The change is a bit larger than that as I've broken out a piece of common
code to wait for and process a single Present event for the target
drawable.
Signed-off-by: Keith Packard kei...@keithp.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/glx/dri3_glx.c | 55 +---
1 file changed, 39 insertions(+), 16 deletions(-)
diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c
index 7b78cd1..8efc270 100644
--- a/src/glx/dri3_glx.c
+++ b/src/glx/dri3_glx.c
@@ -398,14 +398,33 @@ dri3_handle_present_event(struct dri3_drawable *priv,
xcb_present_generic_event_
free(ge);
}
+static bool
+dri3_wait_for_event(__GLXDRIdrawable *pdraw)
+{
+ xcb_connection_t *c = XGetXCBConnection(pdraw-psc-dpy);
+ struct dri3_drawable *priv = (struct dri3_drawable *) pdraw;
+ xcb_generic_event_t *ev;
+ xcb_present_generic_event_t *ge;
+
+ ev = xcb_wait_for_special_event(c, priv-special_event);
+ if (!ev)
+ return false;
+ ge = (void *) ev;
+ dri3_handle_present_event(priv, ge);
+ return true;
+}
+
+/** dri3_wait_for_msc
+ *
+ * Get the X server to send an event when the target msc/divisor/remainder is
+ * reached.
+ */
static int
dri3_wait_for_msc(__GLXDRIdrawable *pdraw, int64_t target_msc, int64_t divisor,
int64_t remainder, int64_t *ust, int64_t *msc, int64_t *sbc)
{
xcb_connection_t *c = XGetXCBConnection(pdraw-psc-dpy);
struct dri3_drawable *priv = (struct dri3_drawable *) pdraw;
- xcb_generic_event_t *ev;
- xcb_present_generic_event_t *ge;
uint32_t msc_serial;
/* Ask for the an event for the target MSC */
@@ -422,11 +441,8 @@ dri3_wait_for_msc(__GLXDRIdrawable *pdraw, int64_t
target_msc, int64_t divisor,
/* Wait for the event */
if (priv-special_event) {
while ((int32_t) (msc_serial - priv-recv_msc_serial) 0) {
- ev = xcb_wait_for_special_event(c, priv-special_event);
- if (!ev)
-break;
- ge = (void *) ev;
- dri3_handle_present_event(priv, ge);
+ if (!dri3_wait_for_event(pdraw))
+return 0;
}
}
@@ -437,6 +453,11 @@ dri3_wait_for_msc(__GLXDRIdrawable *pdraw, int64_t
target_msc, int64_t divisor,
return 1;
}
+/** dri3_drawable_get_msc
+ *
+ * Return the current UST/MSC/SBC triplet by asking the server
+ * for an event
+ */
static int
dri3_drawable_get_msc(struct glx_screen *psc, __GLXDRIdrawable *pdraw,
int64_t *ust, int64_t *msc, int64_t *sbc)
@@ -446,12 +467,9 @@ dri3_drawable_get_msc(struct glx_screen *psc,
__GLXDRIdrawable *pdraw,
/** dri3_wait_for_sbc
*
- * Wait for the swap buffer count to increase. The only way this
- * can happen is if some other thread is doing swap buffers as
- * we no longer share swap buffer counts with other processes.
- *
- * I'm not sure this is actually useful as such, and so this
- * implementation is a kludge that just polls once a second
+ * Wait for the completed swap buffer count to reach the specified
+ * target. Presumably the application knows that this will be reached with
+ * outstanding complete events, or we're going to be here awhile.
*/
static int
dri3_wait_for_sbc(__GLXDRIdrawable *pdraw, int64_t target_sbc, int64_t *ust,
@@ -459,10 +477,15 @@ dri3_wait_for_sbc(__GLXDRIdrawable *pdraw, int64_t
target_sbc, int64_t *ust,
{
struct dri3_drawable *priv = (struct dri3_drawable *) pdraw;
- while (priv-send_sbc target_sbc) {
- sleep(1);
+ while (priv-recv_sbc target_sbc) {
+ if (!dri3_wait_for_event(pdraw))
+ return 0;
}
- return dri3_wait_for_msc(pdraw, 0, 0, 0, ust, msc, sbc);
+
+ *ust = priv-ust;
+ *msc = priv-msc;
+ *sbc = priv-recv_sbc;
+ return 1;
}
/**
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Mesa (master): dri3: Track full 64-bit SBC numbers, instead of just 32-bits
Module: Mesa
Branch: master
Commit: 71d614250ed1f83d8da3adb8e855ee00201c70da
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=71d614250ed1f83d8da3adb8e855ee00201c70da
Author: Keith Packard kei...@keithp.com
Date: Mon Nov 25 21:14:55 2013 -0800
dri3: Track full 64-bit SBC numbers, instead of just 32-bits
Tracking the full 64-bit SBC values makes it clearer how those values are
being used, and simplifies the wait_msc code. The only trick is in
re-constructing the full 64-bit value from Present's 32-bit serial number
that we use to pass the SBC value from request to event.
Signed-off-by: Keith Packard kei...@keithp.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/glx/dri3_glx.c | 34 +-
src/glx/dri3_priv.h | 16 +---
2 files changed, 30 insertions(+), 20 deletions(-)
diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c
index 2a9f0b7..7b78cd1 100644
--- a/src/glx/dri3_glx.c
+++ b/src/glx/dri3_glx.c
@@ -365,10 +365,17 @@ dri3_handle_present_event(struct dri3_drawable *priv,
xcb_present_generic_event_
case XCB_PRESENT_COMPLETE_NOTIFY: {
xcb_present_complete_notify_event_t *ce = (void *) ge;
- if (ce-kind == XCB_PRESENT_COMPLETE_KIND_PIXMAP)
- priv-present_event_serial = ce-serial;
- else
- priv-present_msc_event_serial = ce-serial;
+ /* Compute the processed SBC number from the received 32-bit serial
number merged
+ * with the upper 32-bits of the sent 64-bit serial number while
checking for
+ * wrap
+ */
+ if (ce-kind == XCB_PRESENT_COMPLETE_KIND_PIXMAP) {
+ priv-recv_sbc = (priv-send_sbc 0xLL) | ce-serial;
+ if (priv-recv_sbc priv-send_sbc)
+priv-recv_sbc -= 0x1;
+ } else {
+ priv-recv_msc_serial = ce-serial;
+ }
priv-ust = ce-ust;
priv-msc = ce-msc;
break;
@@ -399,12 +406,13 @@ dri3_wait_for_msc(__GLXDRIdrawable *pdraw, int64_t
target_msc, int64_t divisor,
struct dri3_drawable *priv = (struct dri3_drawable *) pdraw;
xcb_generic_event_t *ev;
xcb_present_generic_event_t *ge;
+ uint32_t msc_serial;
/* Ask for the an event for the target MSC */
- ++priv-present_msc_request_serial;
+ msc_serial = ++priv-send_msc_serial;
xcb_present_notify_msc(c,
priv-base.xDrawable,
- priv-present_msc_request_serial,
+ msc_serial,
target_msc,
divisor,
remainder);
@@ -413,7 +421,7 @@ dri3_wait_for_msc(__GLXDRIdrawable *pdraw, int64_t
target_msc, int64_t divisor,
/* Wait for the event */
if (priv-special_event) {
- while (priv-present_msc_request_serial !=
priv-present_msc_event_serial) {
+ while ((int32_t) (msc_serial - priv-recv_msc_serial) 0) {
ev = xcb_wait_for_special_event(c, priv-special_event);
if (!ev)
break;
@@ -424,7 +432,7 @@ dri3_wait_for_msc(__GLXDRIdrawable *pdraw, int64_t
target_msc, int64_t divisor,
*ust = priv-ust;
*msc = priv-msc;
- *sbc = priv-sbc;
+ *sbc = priv-recv_sbc;
return 1;
}
@@ -451,7 +459,7 @@ dri3_wait_for_sbc(__GLXDRIdrawable *pdraw, int64_t
target_sbc, int64_t *ust,
{
struct dri3_drawable *priv = (struct dri3_drawable *) pdraw;
- while (priv-sbc target_sbc) {
+ while (priv-send_sbc target_sbc) {
sleep(1);
}
return dri3_wait_for_msc(pdraw, 0, 0, 0, ust, msc, sbc);
@@ -1282,15 +1290,15 @@ dri3_swap_buffers(__GLXDRIdrawable *pdraw, int64_t
target_msc, int64_t divisor,
/* Compute when we want the frame shown by taking the last known
successful
* MSC and adding in a swap interval for each outstanding swap request
*/
- ++priv-present_request_serial;
+ ++priv-send_sbc;
if (target_msc == 0)
- target_msc = priv-msc + priv-swap_interval *
(priv-present_request_serial - priv-present_event_serial);
+ target_msc = priv-msc + priv-swap_interval * (priv-send_sbc -
priv-recv_sbc);
priv-buffers[buf_id]-busy = 1;
xcb_present_pixmap(c,
priv-base.xDrawable,
priv-buffers[buf_id]-pixmap,
- priv-present_request_serial,
+ (uint32_t) priv-send_sbc,
0,/* valid */
0,/* update */
0,/* x_off */
@@ -1302,7 +1310,7 @@ dri3_swap_buffers(__GLXDRIdrawable *pdraw, int64_t
target_msc, int64_t divisor,
target_msc,
divisor,
remainder, 0, NULL);
- ret = ++priv-sbc;
+ ret = (int64_t) priv-send_sbc;
/* If there's a fake front, then copy the source back buffer
Mesa (master): dri3: Enable GLX_INTEL_swap_event
Module: Mesa
Branch: master
Commit: 09d6c1972037a5519488094afd225f793d2188d0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=09d6c1972037a5519488094afd225f793d2188d0
Author: Keith Packard kei...@keithp.com
Date: Mon Nov 25 21:24:54 2013 -0800
dri3: Enable GLX_INTEL_swap_event
Now that we're tracking SBC values correctly, and the X server has the
ability to send the GLX swap events from a PresentPixmap request, enable
this extension.
Signed-off-by: Keith Packard kei...@keithp.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/glx/dri3_glx.c | 18 +-
1 file changed, 1 insertion(+), 17 deletions(-)
diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c
index 8efc270..79bc5f0 100644
--- a/src/glx/dri3_glx.c
+++ b/src/glx/dri3_glx.c
@@ -1524,23 +1524,7 @@ dri3_bind_extensions(struct dri3_screen *psc, struct
glx_display * priv,
__glXEnableDirectExtension(psc-base, GLX_SGI_swap_control);
__glXEnableDirectExtension(psc-base, GLX_MESA_swap_control);
__glXEnableDirectExtension(psc-base, GLX_SGI_make_current_read);
-
- /*
-* GLX_INTEL_swap_event is broken on the server side, where it's
-* currently unconditionally enabled. This completely breaks
-* systems running on drivers which don't support that extension.
-* There's no way to test for its presence on this side, so instead
-* of disabling it unconditionally, just disable it for drivers
-* which are known to not support it, or for DDX drivers supporting
-* only an older (pre-ScheduleSwap) version of DRI2.
-*
-* This is a hack which is required until:
-* http://lists.x.org/archives/xorg-devel/2013-February/035449.html
-* is merged and updated xserver makes it's way into distros:
-*/
-// if (pdp-swapAvailable strcmp(driverName, vmwgfx) != 0) {
-// __glXEnableDirectExtension(psc-base, GLX_INTEL_swap_event);
-// }
+ __glXEnableDirectExtension(psc-base, GLX_INTEL_swap_event);
mask = psc-image_driver-getAPIMask(psc-driScreen);
___
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Mesa (master): dri2: Trust our own driver name lookup over the server's.
Module: Mesa
Branch: master
Commit: 7bd95ec437a5b1052fa17780a9d66677ec1fdc35
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7bd95ec437a5b1052fa17780a9d66677ec1fdc35
Author: Eric Anholt e...@anholt.net
Date: Thu Jan 23 10:21:09 2014 -0800
dri2: Trust our own driver name lookup over the server's.
This allows Mesa to choose to rename driver .sos (or split drivers),
without needing a flag day with the corresponding 2D driver.
v2: Undo the loader-only-for-dri3 change.
Reviewed-by: Keith Packard kei...@keithp.com [v1]
Reviewed-by: Kristian Høgsberg k...@bitplanet.net [v1]
---
src/glx/Makefile.am |2 +-
src/glx/dri2_glx.c | 12 +++-
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/src/glx/Makefile.am b/src/glx/Makefile.am
index 69a6bf9..54a0cc0 100644
--- a/src/glx/Makefile.am
+++ b/src/glx/Makefile.am
@@ -100,9 +100,9 @@ libglx_la_SOURCES = \
if HAVE_DRI3
libglx_la_SOURCES += \
dri3_glx.c
+endif
libglx_la_LIBADD = $(top_builddir)/src/loader/libloader.la
-endif
GL_LIBS = \
libglx.la \
diff --git a/src/glx/dri2_glx.c b/src/glx/dri2_glx.c
index 4e2c16a..0a0dac9 100644
--- a/src/glx/dri2_glx.c
+++ b/src/glx/dri2_glx.c
@@ -51,6 +51,7 @@
#include dri2.h
#include dri_common.h
#include dri2_priv.h
+#include loader.h
/* From xmlpool/options.h, user exposed so should be stable */
#define DRI_CONF_VBLANK_NEVER 0
@@ -1156,7 +1157,7 @@ dri2CreateScreen(int screen, struct glx_display * priv)
struct dri2_screen *psc;
__GLXDRIscreen *psp;
struct glx_config *configs = NULL, *visuals = NULL;
- char *driverName, *deviceName, *tmp;
+ char *driverName = NULL, *loader_driverName, *deviceName, *tmp;
drm_magic_t magic;
int i;
@@ -1193,6 +1194,15 @@ dri2CreateScreen(int screen, struct glx_display * priv)
goto handle_error;
}
+ /* If Mesa knows about the appropriate driver for this fd, then trust it.
+* Otherwise, default to the server's value.
+*/
+ loader_driverName = loader_get_driver_for_fd(psc-fd, 0);
+ if (loader_driverName) {
+ free(driverName);
+ driverName = loader_driverName;
+ }
+
psc-driver = driOpenDriver(driverName);
if (psc-driver == NULL) {
ErrorMessageF(driver pointer missing\n);
___
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Mesa (master): dri: Reuse dri_message to implement our other message handlers.
Module: Mesa
Branch: master
Commit: 867d7c0e108a4e6511305f82b18ea6f606a18427
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=867d7c0e108a4e6511305f82b18ea6f606a18427
Author: Eric Anholt e...@anholt.net
Date: Thu Jan 23 11:14:16 2014 -0800
dri: Reuse dri_message to implement our other message handlers.
Reviewed-by: Keith Packard kei...@keithp.com
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
src/glx/dri_common.c | 60 --
src/glx/dri_common.h |7 +++---
2 files changed, 4 insertions(+), 63 deletions(-)
diff --git a/src/glx/dri_common.c b/src/glx/dri_common.c
index 93c45ea..0dd8982 100644
--- a/src/glx/dri_common.c
+++ b/src/glx/dri_common.c
@@ -73,66 +73,6 @@ dri_message(int level, const char *f, ...)
}
}
-/**
- * Print informational message to stderr if LIBGL_DEBUG is set to
- * verbose.
- */
-_X_HIDDEN void
-InfoMessageF(const char *f, ...)
-{
- va_list args;
- const char *env;
-
- if ((env = getenv(LIBGL_DEBUG)) strstr(env, verbose)) {
- fprintf(stderr, libGL: );
- va_start(args, f);
- vfprintf(stderr, f, args);
- va_end(args);
- }
-}
-
-/**
- * Print error message to stderr if LIBGL_DEBUG is set to anything but
- * quiet, (do nothing if LIBGL_DEBUG is unset).
- */
-_X_HIDDEN void
-ErrorMessageF(const char *f, ...)
-{
- va_list args;
- const char *env;
-
- if ((env = getenv(LIBGL_DEBUG)) !strstr(env, quiet)) {
- fprintf(stderr, libGL error: );
- va_start(args, f);
- vfprintf(stderr, f, args);
- va_end(args);
- }
-}
-
-/**
- * Print error message unless LIBGL_DEBUG is set to quiet.
- *
- * The distinction between CriticalErrorMessageF and ErrorMessageF is
- * that critcial errors will be printed by default, (even when
- * LIBGL_DEBUG is unset).
- */
-_X_HIDDEN void
-CriticalErrorMessageF(const char *f, ...)
-{
- va_list args;
- const char *env;
-
- if (!(env = getenv(LIBGL_DEBUG)) || !strstr(env, quiet)) {
- fprintf(stderr, libGL error: );
- va_start(args, f);
- vfprintf(stderr, f, args);
- va_end(args);
-
- if (!env || !strstr(env, verbose))
- fprintf(stderr, libGL error: Try again with LIBGL_DEBUG=verbose for
more details.\n);
- }
-}
-
#ifndef DEFAULT_DRIVER_DIR
/* this is normally defined in Mesa/configs/default with
DRI_DRIVER_SEARCH_PATH */
#define DEFAULT_DRIVER_DIR /usr/local/lib/dri
diff --git a/src/glx/dri_common.h b/src/glx/dri_common.h
index 425d89f..6234fd8 100644
--- a/src/glx/dri_common.h
+++ b/src/glx/dri_common.h
@@ -38,6 +38,7 @@
#include GL/internal/dri_interface.h
#include stdbool.h
+#include loader.h
#if (__GNUC__ = 3)
#define PRINTFLIKE(f, a) __attribute__ ((format(__printf__, f, a)))
@@ -69,9 +70,9 @@ extern const __DRIsystemTimeExtension systemTimeExtension;
extern void dri_message(int level, const char *f, ...) PRINTFLIKE(2, 3);
-extern void InfoMessageF(const char *f, ...);
-extern void ErrorMessageF(const char *f, ...);
-extern void CriticalErrorMessageF(const char *f, ...);
+#define InfoMessageF(...) dri_message(_LOADER_INFO, __VA_ARGS__)
+#define ErrorMessageF(...) dri_message(_LOADER_WARNING, __VA_ARGS__)
+#define CriticalErrorMessageF(...) dri_message(_LOADER_FATAL, __VA_ARGS__)
extern void *driOpenDriver(const char *driverName);
___
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Mesa (master): dri3: Fix two little memory leaks.
Module: Mesa Branch: master Commit: 378e7ad26f11aacd02a131262646e48c362539ef URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=378e7ad26f11aacd02a131262646e48c362539ef Author: Eric Anholt e...@anholt.net Date: Thu Jan 23 10:25:58 2014 -0800 dri3: Fix two little memory leaks. Noticed when valgrinding an unrelated bug. Reviewed-by: Keith Packard kei...@keithp.com Reviewed-by: Kristian Høgsberg k...@bitplanet.net --- src/glx/dri3_glx.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c index 9068ff9..3e82965 100644 --- a/src/glx/dri3_glx.c +++ b/src/glx/dri3_glx.c @@ -1338,14 +1338,13 @@ dri3_open(Display *dpy, xcb_dri3_open_cookie_t cookie; xcb_dri3_open_reply_t*reply; xcb_connection_t *c = XGetXCBConnection(dpy); - xcb_generic_error_t *error; int fd; cookie = xcb_dri3_open(c, root, provider); - reply = xcb_dri3_open_reply(c, cookie, error); + reply = xcb_dri3_open_reply(c, cookie, NULL); if (!reply) return -1; @@ -1799,6 +1798,7 @@ dri3_create_display(Display * dpy) } pdp-presentMajor = present_reply-major_version; pdp-presentMinor = present_reply-minor_version; + free(present_reply); pdp-base.destroyDisplay = dri3_destroy_display; pdp-base.createScreen = dri3_create_screen; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): loader: Add missing \n on message printing
Module: Mesa
Branch: master
Commit: a6031a82f9b0851ef17d1136e34c1eb2a2b07a70
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a6031a82f9b0851ef17d1136e34c1eb2a2b07a70
Author: Emil Velikov emil.l.veli...@gmail.com
Date: Mon Jan 27 12:53:32 2014 +
loader: Add missing \n on message printing
Cover both loader and glx/dri_glx
Drop \n from the default loader logger
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/glx/dri_glx.c |8
src/loader/loader.c | 23 +++
2 files changed, 15 insertions(+), 16 deletions(-)
diff --git a/src/glx/dri_glx.c b/src/glx/dri_glx.c
index 2e00bf0..03ecc5b 100644
--- a/src/glx/dri_glx.c
+++ b/src/glx/dri_glx.c
@@ -418,7 +418,7 @@ CallCreateNewScreen(Display *dpy, int scrn, struct
dri_screen *psc,
framebuffer.size, framebuffer.stride,
framebuffer.dev_priv_size,
framebuffer.dev_priv)) {
- ErrorMessageF(XF86DRIGetDeviceInfo failed);
+ ErrorMessageF(XF86DRIGetDeviceInfo failed\n);
goto handle_error;
}
@@ -429,7 +429,7 @@ CallCreateNewScreen(Display *dpy, int scrn, struct
dri_screen *psc,
status = drmMap(fd, hFB, framebuffer.size,
(drmAddressPtr) framebuffer.base);
if (status != 0) {
- ErrorMessageF(drmMap of framebuffer failed (%s), strerror(-status));
+ ErrorMessageF(drmMap of framebuffer failed (%s)\n, strerror(-status));
goto handle_error;
}
@@ -438,7 +438,7 @@ CallCreateNewScreen(Display *dpy, int scrn, struct
dri_screen *psc,
*/
status = drmMap(fd, hSAREA, SAREA_MAX, pSAREA);
if (status != 0) {
- ErrorMessageF(drmMap of SAREA failed (%s), strerror(-status));
+ ErrorMessageF(drmMap of SAREA failed (%s)\n, strerror(-status));
goto handle_error;
}
@@ -453,7 +453,7 @@ CallCreateNewScreen(Display *dpy, int scrn, struct
dri_screen *psc,
driver_configs, psc);
if (psp == NULL) {
- ErrorMessageF(Calling driver entry point failed);
+ ErrorMessageF(Calling driver entry point failed\n);
goto handle_error;
}
diff --git a/src/loader/loader.c b/src/loader/loader.c
index 63b977a..6d179a1 100644
--- a/src/loader/loader.c
+++ b/src/loader/loader.c
@@ -85,7 +85,6 @@ static void default_logger(int level, const char *fmt, ...)
va_start(args, fmt);
vfprintf(stderr, fmt, args);
va_end(args);
- fprintf(stderr, \n);
}
}
@@ -127,14 +126,14 @@ udev_device_new_from_fd(struct udev *udev, int fd)
(struct udev *udev, char type, dev_t devnum));
if (fstat(fd, buf) 0) {
- log_(_LOADER_WARNING, MESA-LOADER: failed to stat fd %d, fd);
+ log_(_LOADER_WARNING, MESA-LOADER: failed to stat fd %d\n, fd);
return NULL;
}
device = udev_device_new_from_devnum(udev, 'c', buf.st_rdev);
if (device == NULL) {
log_(_LOADER_WARNING,
- MESA-LOADER: could not create udev device for fd %d, fd);
+ MESA-LOADER: could not create udev device for fd %d\n, fd);
return NULL;
}
@@ -165,14 +164,14 @@ loader_get_pci_id_for_fd(int fd, int *vendor_id, int
*chip_id)
parent = udev_device_get_parent(device);
if (parent == NULL) {
- log_(_LOADER_WARNING, MESA-LOADER: could not get parent device);
+ log_(_LOADER_WARNING, MESA-LOADER: could not get parent device\n);
goto out;
}
pci_id = udev_device_get_property_value(parent, PCI_ID);
if (pci_id == NULL ||
sscanf(pci_id, %x:%x, vendor_id, chip_id) != 2) {
- log_(_LOADER_WARNING, MESA-LOADER: malformed or no PCI ID);
+ log_(_LOADER_WARNING, MESA-LOADER: malformed or no PCI ID\n);
*chip_id = -1;
goto out;
}
@@ -202,11 +201,11 @@ loader_get_pci_id_for_fd(int fd, int *vendor_id, int
*chip_id)
version = drmGetVersion(fd);
if (!version) {
- log_(_LOADER_WARNING, MESA-LOADER: invalid drm fd);
+ log_(_LOADER_WARNING, MESA-LOADER: invalid drm fd\n);
return FALSE;
}
if (!version-name) {
- log_(_LOADER_WARNING, MESA-LOADER: unable to determine the driver
name);
+ log_(_LOADER_WARNING, MESA-LOADER: unable to determine the driver
name\n);
drmFreeVersion(version);
return FALSE;
}
@@ -222,7 +221,7 @@ loader_get_pci_id_for_fd(int fd, int *vendor_id, int
*chip_id)
gp.value = chip_id;
ret = drmCommandWriteRead(fd, DRM_I915_GETPARAM, gp, sizeof(gp));
if (ret) {
- log_(_LOADER_WARNING, MESA-LOADER: failed to get param for i915);
+ log_(_LOADER_WARNING, MESA-LOADER: failed to get param for i915\n);
*chip_id = -1;
}
}
@@ -237,7 +236,7 @@ loader_get_pci_id_for_fd(int fd, int *vendor_id, int
*chip_id)
info.value = (unsigned long) chip_id;
ret = drmCommandWriteRead(fd, DRM_RADEON_INFO, info, sizeof(info
Mesa (master): loader: Use dlsym to get our udev symbols instead of explicit linking.
Module: Mesa
Branch: master
Commit: 4556c734700da2dd95d4f148d6929a537882bade
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4556c734700da2dd95d4f148d6929a537882bade
Author: Eric Anholt e...@anholt.net
Date: Thu Jan 23 13:12:26 2014 -0800
loader: Use dlsym to get our udev symbols instead of explicit linking.
Steam links against libudev.so.0, while we're linking against
libudev.so.1. The result is that the symbol names (which are the same in
the two libraries) end up conflicting, and some of the usage of .so.1
calls the .so.0 bits, which have different internal structures, and
segfaults happen.
By using a dlopen() with RTLD_LOCAL, we can explicitly look for the
symbols we want, while they get the symbols they want.
Reviewed-by: Keith Packard kei...@keithp.com
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
Tested-by: Alexandre Demers alexandre.f.dem...@gmail.com
Tested-by: Mike Lothian m...@fireburn.co.uk
---
configure.ac |2 +-
src/egl/main/Makefile.am |2 +-
src/loader/Makefile.am |5 +
src/loader/loader.c | 42 ++
4 files changed, 45 insertions(+), 6 deletions(-)
diff --git a/configure.ac b/configure.ac
index 33ac922..d266d96 100644
--- a/configure.ac
+++ b/configure.ac
@@ -858,7 +858,7 @@ xyesno)
if test x$enable_dri3$have_libudev = xyesyes; then
X11_INCLUDES=$X11_INCLUDES $LIBUDEV_CFLAGS
-GL_LIB_DEPS=$GL_LIB_DEPS $LIBUDEV_LIBS
+GL_LIB_DEPS=$GL_LIB_DEPS
fi
# need DRM libs, $PTHREAD_LIBS, etc.
diff --git a/src/egl/main/Makefile.am b/src/egl/main/Makefile.am
index 60cb600..e12aeae 100644
--- a/src/egl/main/Makefile.am
+++ b/src/egl/main/Makefile.am
@@ -112,7 +112,7 @@ if HAVE_EGL_DRIVER_DRI2
AM_CFLAGS += -D_EGL_BUILT_IN_DRIVER_DRI2
AM_CFLAGS += -DHAVE_XCB_DRI2
libEGL_la_LIBADD += ../drivers/dri2/libegl_dri2.la
-libEGL_la_LIBADD += $(LIBUDEV_LIBS) $(DLOPEN_LIBS) $(LIBDRM_LIBS)
+libEGL_la_LIBADD += $(DLOPEN_LIBS) $(LIBDRM_LIBS)
endif
# Provide compatibility with scripts for the old Mesa build system for
diff --git a/src/loader/Makefile.am b/src/loader/Makefile.am
index 371dd57..bddf7ac 100644
--- a/src/loader/Makefile.am
+++ b/src/loader/Makefile.am
@@ -29,9 +29,6 @@ libloader_la_CPPFLAGS = \
$(VISIBILITY_CFLAGS) \
$(LIBUDEV_CFLAGS)
-libloader_la_LIBADD = \
- $(LIBUDEV_LIBS)
-
if !HAVE_LIBDRM
libloader_la_CPPFLAGS += \
-D__NOT_HAVE_DRM_H
@@ -39,7 +36,7 @@ else
libloader_la_CPPFLAGS += \
$(LIBDRM_CFLAGS)
-libloader_la_LIBADD += \
+libloader_la_LIBADD = \
$(LIBDRM_LIBS)
endif
diff --git a/src/loader/loader.c b/src/loader/loader.c
index a5bd769..63b977a 100644
--- a/src/loader/loader.c
+++ b/src/loader/loader.c
@@ -67,6 +67,8 @@
#include stdarg.h
#include stdio.h
#include string.h
+#include assert.h
+#include dlfcn.h
#include loader.h
#ifndef __NOT_HAVE_DRM_H
@@ -92,11 +94,37 @@ static void (*log_)(int level, const char *fmt, ...) =
default_logger;
#ifdef HAVE_LIBUDEV
#include libudev.h
+static void *udev_handle = NULL;
+
+static void *
+udev_dlopen_handle(void)
+{
+ if (!udev_handle) {
+ udev_handle = dlopen(libudev.so.1, RTLD_LOCAL | RTLD_LAZY);
+ }
+
+ return udev_handle;
+}
+
+static void *
+asserted_dlsym(void *dlopen_handle, const char *name)
+{
+ void *result = dlsym(dlopen_handle, name);
+ assert(result);
+ return result;
+}
+
+#define UDEV_SYMBOL(ret, name, args) \
+ ret (*name) args = asserted_dlsym(udev_dlopen_handle(), #name);
+
+
static inline struct udev_device *
udev_device_new_from_fd(struct udev *udev, int fd)
{
struct udev_device *device;
struct stat buf;
+ UDEV_SYMBOL(struct udev_device *, udev_device_new_from_devnum,
+ (struct udev *udev, char type, dev_t devnum));
if (fstat(fd, buf) 0) {
log_(_LOADER_WARNING, MESA-LOADER: failed to stat fd %d, fd);
@@ -119,6 +147,14 @@ loader_get_pci_id_for_fd(int fd, int *vendor_id, int
*chip_id)
struct udev *udev = NULL;
struct udev_device *device = NULL, *parent;
const char *pci_id;
+ UDEV_SYMBOL(struct udev *, udev_new, (void));
+ UDEV_SYMBOL(struct udev_device *, udev_device_get_parent,
+ (struct udev_device *));
+ UDEV_SYMBOL(const char *, udev_device_get_property_value,
+ (struct udev_device *, const char *));
+ UDEV_SYMBOL(struct udev_device *, udev_device_unref,
+ (struct udev_device *));
+ UDEV_SYMBOL(struct udev *, udev_unref, (struct udev *));
*chip_id = -1;
@@ -240,6 +276,12 @@ loader_get_device_name_for_fd(int fd)
struct udev *udev;
struct udev_device *device;
const char *const_device_name;
+ UDEV_SYMBOL(struct udev *, udev_new, (void));
+ UDEV_SYMBOL(const char *, udev_device_get_devnode,
+ (struct udev_device *));
+ UDEV_SYMBOL(struct udev_device *, udev_device_unref,
+ (struct udev_device *));
+ UDEV_SYMBOL(struct udev *, udev_unref, (struct
Mesa (master): dri: Fix the logger error message handling.
Module: Mesa
Branch: master
Commit: 4a8da40fc089d465b72ecee89e24cd92e6714669
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a8da40fc089d465b72ecee89e24cd92e6714669
Author: Eric Anholt e...@anholt.net
Date: Thu Jan 23 11:03:53 2014 -0800
dri: Fix the logger error message handling.
Since the loader changes, there has been a compiler warning that the
prototype didn't match. It turns out that if a loader error message was
ever thrown, you'd segfault because of trying to use the warning level as
a format string.
Reviewed-by: Keith Packard kei...@keithp.com
Tested-by: Keith Packard kei...@keithp.com
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
src/glx/dri3_glx.c |2 +-
src/glx/dri_common.c | 25 +
src/glx/dri_common.h | 10 --
3 files changed, 34 insertions(+), 3 deletions(-)
diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c
index 3e82965..2a9f0b7 100644
--- a/src/glx/dri3_glx.c
+++ b/src/glx/dri3_glx.c
@@ -1803,7 +1803,7 @@ dri3_create_display(Display * dpy)
pdp-base.destroyDisplay = dri3_destroy_display;
pdp-base.createScreen = dri3_create_screen;
- loader_set_logger(ErrorMessageF);
+ loader_set_logger(dri_message);
i = 0;
pdp-loader_extensions[i++] = imageLoaderExtension.base;
diff --git a/src/glx/dri_common.c b/src/glx/dri_common.c
index b5058c9..93c45ea 100644
--- a/src/glx/dri_common.c
+++ b/src/glx/dri_common.c
@@ -40,6 +40,7 @@
#include stdarg.h
#include glxclient.h
#include dri_common.h
+#include loader.h
#ifndef RTLD_NOW
#define RTLD_NOW 0
@@ -48,6 +49,30 @@
#define RTLD_GLOBAL 0
#endif
+_X_HIDDEN void
+dri_message(int level, const char *f, ...)
+{
+ va_list args;
+ int threshold = _LOADER_WARNING;
+ const char *libgl_debug;
+
+ libgl_debug = getenv(LIBGL_DEBUG);
+ if (libgl_debug) {
+ if (strstr(libgl_debug, quiet))
+ threshold = _LOADER_FATAL;
+ else if (strstr(libgl_debug, verbose))
+ threshold = _LOADER_DEBUG;
+ }
+
+ /* Note that the _LOADER_* levels are lower numbers for more severe. */
+ if (level = threshold) {
+ fprintf(stderr, libGL%s: , level = _LOADER_WARNING ? error : );
+ va_start(args, f);
+ vfprintf(stderr, f, args);
+ va_end(args);
+ }
+}
+
/**
* Print informational message to stderr if LIBGL_DEBUG is set to
* verbose.
diff --git a/src/glx/dri_common.h b/src/glx/dri_common.h
index 4fe0d3f..425d89f 100644
--- a/src/glx/dri_common.h
+++ b/src/glx/dri_common.h
@@ -39,6 +39,12 @@
#include GL/internal/dri_interface.h
#include stdbool.h
+#if (__GNUC__ = 3)
+#define PRINTFLIKE(f, a) __attribute__ ((format(__printf__, f, a)))
+#else
+#define PRINTFLIKE(f, a)
+#endif
+
typedef struct __GLXDRIconfigPrivateRec __GLXDRIconfigPrivate;
struct __GLXDRIconfigPrivateRec
@@ -61,10 +67,10 @@ driReleaseDrawables(struct glx_context *gc);
extern const __DRIsystemTimeExtension systemTimeExtension;
-extern void InfoMessageF(const char *f, ...);
+extern void dri_message(int level, const char *f, ...) PRINTFLIKE(2, 3);
+extern void InfoMessageF(const char *f, ...);
extern void ErrorMessageF(const char *f, ...);
-
extern void CriticalErrorMessageF(const char *f, ...);
extern void *driOpenDriver(const char *driverName);
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Mesa (master): dri2: Open the fd before loading the driver.
Module: Mesa
Branch: master
Commit: be7a6976a8335a2e1a177769e96f7310ca6770d1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=be7a6976a8335a2e1a177769e96f7310ca6770d1
Author: Eric Anholt e...@anholt.net
Date: Thu Jan 23 10:17:11 2014 -0800
dri2: Open the fd before loading the driver.
I want to stop trusting the server for the driver name, and instead decide
on our own based on the fd, so I needed this code motion.
Reviewed-by: Keith Packard kei...@keithp.com
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
src/glx/dri2_glx.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/src/glx/dri2_glx.c b/src/glx/dri2_glx.c
index ae807ee..4e2c16a 100644
--- a/src/glx/dri2_glx.c
+++ b/src/glx/dri2_glx.c
@@ -1179,6 +1179,20 @@ dri2CreateScreen(int screen, struct glx_display * priv)
return NULL;
}
+#ifdef O_CLOEXEC
+ psc-fd = open(deviceName, O_RDWR | O_CLOEXEC);
+ if (psc-fd == -1 errno == EINVAL)
+#endif
+ {
+ psc-fd = open(deviceName, O_RDWR);
+ if (psc-fd != -1)
+ fcntl(psc-fd, F_SETFD, fcntl(psc-fd, F_GETFD) | FD_CLOEXEC);
+ }
+ if (psc-fd 0) {
+ ErrorMessageF(failed to open drm device: %s\n, strerror(errno));
+ goto handle_error;
+ }
+
psc-driver = driOpenDriver(driverName);
if (psc-driver == NULL) {
ErrorMessageF(driver pointer missing\n);
@@ -1201,20 +1215,6 @@ dri2CreateScreen(int screen, struct glx_display * priv)
goto handle_error;
}
-#ifdef O_CLOEXEC
- psc-fd = open(deviceName, O_RDWR | O_CLOEXEC);
- if (psc-fd == -1 errno == EINVAL)
-#endif
- {
- psc-fd = open(deviceName, O_RDWR);
- if (psc-fd != -1)
- fcntl(psc-fd, F_SETFD, fcntl(psc-fd, F_GETFD) | FD_CLOEXEC);
- }
- if (psc-fd 0) {
- ErrorMessageF(failed to open drm device: %s\n, strerror(errno));
- goto handle_error;
- }
-
if (drmGetMagic(psc-fd, magic)) {
ErrorMessageF(failed to get magic\n);
goto handle_error;
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Mesa (master): driconf: Synchronize po files
Module: Mesa Branch: master Commit: 822b4315b7eb9d7659d7954416ffe441fd364730 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=822b4315b7eb9d7659d7954416ffe441fd364730 Author: Alex Henrie alexhenri...@gmail.com Date: Wed Jan 15 10:41:46 2014 -0700 driconf: Synchronize po files See the instructions in Makefile.am under Updating existing translations. Reviewed-by: Eric Anholt e...@anholt.net --- src/mesa/drivers/dri/common/xmlpool/de.po | 235 - src/mesa/drivers/dri/common/xmlpool/es.po | 212 ++ src/mesa/drivers/dri/common/xmlpool/fr.po | 199 src/mesa/drivers/dri/common/xmlpool/nl.po | 197 src/mesa/drivers/dri/common/xmlpool/sv.po | 216 +- 5 files changed, 702 insertions(+), 357 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=822b4315b7eb9d7659d7954416ffe441fd364730 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): driconf: Correct and update Spanish translations
Module: Mesa Branch: master Commit: 84529a5ddb214961d0a743c68a4b8e13fb7ab34b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=84529a5ddb214961d0a743c68a4b8e13fb7ab34b Author: Alex Henrie alexhenri...@gmail.com Date: Wed Jan 15 10:42:05 2014 -0700 driconf: Correct and update Spanish translations Reviewed-by: Eric Anholt e...@anholt.net --- src/mesa/drivers/dri/common/xmlpool/es.po | 64 +++-- 1 file changed, 33 insertions(+), 31 deletions(-) diff --git a/src/mesa/drivers/dri/common/xmlpool/es.po b/src/mesa/drivers/dri/common/xmlpool/es.po index e5b4d1a..4a6ab91 100644 --- a/src/mesa/drivers/dri/common/xmlpool/es.po +++ b/src/mesa/drivers/dri/common/xmlpool/es.po @@ -10,23 +10,23 @@ msgstr Project-Id-Version: es\n Report-Msgid-Bugs-To: \n POT-Creation-Date: 2014-01-13 22:30-0700\n -PO-Revision-Date: 2005-04-12 20:26+0200\n -Last-Translator: David Rubio Miguélez de...@ono.com\n +PO-Revision-Date: 2014-01-15 10:34-0700\n +Last-Translator: Alex Henrie alexhenri...@gmail.com\n Language-Team: Spanish e...@li.org\n Language: es\n MIME-Version: 1.0\n Content-Type: text/plain; charset=UTF-8\n Content-Transfer-Encoding: 8bit\n Plural-Forms: nplurals=2; plural=(n != 1);\n -X-Generator: KBabel 1.10\n +X-Generator: Poedit 1.5.4\n #: t_options.h:56 msgid Debugging -msgstr Depurando +msgstr Depuración #: t_options.h:60 msgid Disable 3D acceleration -msgstr Desactivar aceleración 3D +msgstr Deshabilitar aceleración 3D #: t_options.h:65 msgid Show performance boxes @@ -34,36 +34,41 @@ msgstr Mostrar cajas de rendimiento #: t_options.h:70 msgid Enable flushing batchbuffer after each draw call -msgstr +msgstr Habilitar vaciado del batchbuffer después de cada llamada de dibujo #: t_options.h:75 msgid Enable flushing GPU caches with each draw call -msgstr +msgstr Habilitar vaciado de los cachés GPU con cada llamada de dibujo #: t_options.h:80 msgid Disable throttling on first batch after flush -msgstr +msgstr Deshabilitar regulación del primer lote después de vaciar #: t_options.h:85 msgid Force GLSL extension default behavior to 'warn' msgstr +Forzar que el comportamiento por defecto de las extensiones GLSL sea 'warn' #: t_options.h:90 msgid Disable dual source blending -msgstr +msgstr Deshabilitar mezcla de fuente dual #: t_options.h:95 msgid Disable backslash-based line continuations in GLSL source msgstr +Deshabilitar continuaciones de línea basadas en barra inversa en el código +GLSL #: t_options.h:100 msgid Disable GL_ARB_shader_bit_encoding -msgstr +msgstr Deshabilitar GL_ARB_shader_bit_encoding #: t_options.h:105 msgid Force a default GLSL version for shaders that lack an explicit #version line msgstr +Forzar una versión de GLSL por defecto en los shaders a los cuales les falta +una línea #version explícita #: t_options.h:115 msgid Image Quality @@ -75,7 +80,7 @@ msgstr Profundidad de color de textura #: t_options.h:129 msgid Prefer frame buffer color depth -msgstr Preferir profundidad de color del \framebuffer\ +msgstr Preferir profundidad de color del framebuffer #: t_options.h:130 msgid Prefer 32 bits per texel @@ -101,8 +106,8 @@ msgstr Prohibir valores negativos de Nivel De Detalle (LOD) de texturas msgid Enable S3TC texture compression even if software support is not available msgstr -Activar la compresión de texturas S3TC incluso si el soporte por software no -está disponible +Habilitar la compresión de texturas S3TC incluso si el soporte por software +no está disponible #: t_options.h:155 msgid Initial color reduction method @@ -150,31 +155,35 @@ msgstr Búfer de profundidad en coma flotante #: t_options.h:190 msgid A post-processing filter to cel-shade the output -msgstr +msgstr Un filtro de postprocesamiento para aplicar cel shading a la salida #: t_options.h:195 msgid A post-processing filter to remove the red channel -msgstr +msgstr Un filtro de postprocesamiento para eliminar el canal rojo #: t_options.h:200 msgid A post-processing filter to remove the green channel -msgstr +msgstr Un filtro de postprocesamiento para eliminar el canal verde #: t_options.h:205 msgid A post-processing filter to remove the blue channel -msgstr +msgstr Un filtro de postprocesamiento para eliminar el canal azul #: t_options.h:210 msgid Morphological anti-aliasing based on Jimenez\\' MLAA. 0 to disable, 8 for default quality msgstr +Antialiasing morfológico basado en el MLAA de Jimenez. 0 para deshabilitar, +8 para calidad por defecto #: t_options.h:215 msgid Morphological anti-aliasing based on Jimenez\\' MLAA. 0 to disable, 8 for default quality. Color version, usable with 2d GL apps msgstr +Antialiasing morfológico basado en el MLAA de Jimenez. 0 para deshabilitar, +8 para calidad por defecto. Versión en color, usable con aplicaciones GL 2D #: t_options.h:225 msgid Performance @@ -200,12 +209,12 @@ msgstr Pasar por alto la tubería TCL msgid
Mesa (master): driconf: Add Catalan translations
Module: Mesa Branch: master Commit: d5e5367e8992c2e5322d35fba8d86c33a0db6825 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=d5e5367e8992c2e5322d35fba8d86c33a0db6825 Author: Alex Henrie alexhenri...@gmail.com Date: Wed Jan 15 10:42:23 2014 -0700 driconf: Add Catalan translations See the instructions in Makefile.am under Adding new translations. Reviewed-by: Eric Anholt e...@anholt.net --- src/mesa/drivers/dri/common/xmlpool/Makefile.am |2 +- src/mesa/drivers/dri/common/xmlpool/ca.po | 321 +++ 2 files changed, 322 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/common/xmlpool/Makefile.am b/src/mesa/drivers/dri/common/xmlpool/Makefile.am index ad7887d..0908c82 100644 --- a/src/mesa/drivers/dri/common/xmlpool/Makefile.am +++ b/src/mesa/drivers/dri/common/xmlpool/Makefile.am @@ -41,7 +41,7 @@ # - info gettext # The set of supported languages. Add languages as needed. -POS=de.po es.po nl.po fr.po sv.po +POS=ca.po de.po es.po nl.po fr.po sv.po # # Don't change anything below, unless you know what you're doing. diff --git a/src/mesa/drivers/dri/common/xmlpool/ca.po b/src/mesa/drivers/dri/common/xmlpool/ca.po new file mode 100644 index 000..c0cf7f6 --- /dev/null +++ b/src/mesa/drivers/dri/common/xmlpool/ca.po @@ -0,0 +1,321 @@ +# Language translations for Mesa package +# Traduccions al català del paquet «Mesa». +# +# Copyright © 2014 Alex Henrie alexhenri...@gmail.com +# +# Permission is hereby granted, free of charge, to any person obtaining a +# copy of this software and associated documentation files (the Software), +# to deal in the Software without restriction, including without limitation +# the rights to use, copy, modify, merge, publish, distribute, sublicense, +# and/or sell copies of the Software, and to permit persons to whom the +# Software is furnished to do so, subject to the following conditions: +# +# The above copyright notice and this permission notice (including the next +# paragraph) shall be included in all copies or substantial portions of the +# Software. +# +# THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL +# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING +# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS +# IN THE SOFTWARE. + +msgid +msgstr +Project-Id-Version: Mesa 10.1.0-devel\n +Report-Msgid-Bugs-To: \n +POT-Creation-Date: 2014-01-13 22:30-0700\n +PO-Revision-Date: 2014-01-15 10:37-0700\n +Last-Translator: Alex Henrie alexhenri...@gmail.com\n +Language-Team: Catalan c...@li.org\n +Language: ca\n +MIME-Version: 1.0\n +Content-Type: text/plain; charset=UTF-8\n +Content-Transfer-Encoding: 8bit\n +X-Generator: Poedit 1.5.4\n + +#: t_options.h:56 +msgid Debugging +msgstr Depuració + +#: t_options.h:60 +msgid Disable 3D acceleration +msgstr Deshabilita l'acceleració 3D + +#: t_options.h:65 +msgid Show performance boxes +msgstr Mostra les caixes de rendiment + +#: t_options.h:70 +msgid Enable flushing batchbuffer after each draw call +msgstr Habilita el buidatge del batchbuffer després de cada trucada de dibuix + +#: t_options.h:75 +msgid Enable flushing GPU caches with each draw call +msgstr +Habilita el buidatge de les memòries cau de GPU amb cada trucada de dibuix + +#: t_options.h:80 +msgid Disable throttling on first batch after flush +msgstr Deshabilita la regulació en el primer lot després de buidar + +#: t_options.h:85 +msgid Force GLSL extension default behavior to 'warn' +msgstr +Força que el comportament per defecte de les extensions GLSL sigui 'warn' + +#: t_options.h:90 +msgid Disable dual source blending +msgstr Deshabilita la barreja de font dual + +#: t_options.h:95 +msgid Disable backslash-based line continuations in GLSL source +msgstr +Deshabilitar les continuacions de línia basades en barra invertida en la +font GLSL + +#: t_options.h:100 +msgid Disable GL_ARB_shader_bit_encoding +msgstr Deshabilita el GL_ARB_shader_bit_encoding + +#: t_options.h:105 +msgid +Force a default GLSL version for shaders that lack an explicit #version line +msgstr +Força una versió GLSL per defecte en els shaders als quals falta una línia +#version explícita + +#: t_options.h:115 +msgid Image Quality +msgstr Qualitat d'Imatge + +#: t_options.h:128 +msgid Texture color depth +msgstr Profunditat de color de textura + +#: t_options.h:129 +msgid Prefer frame buffer color depth +msgstr Prefereix profunditat de color del framebuffer + +#: t_options.h:130 +msgid Prefer 32 bits per texel +msgstr Prefereix 32 bits per texel + +#: t_options.h:131 +msgid Prefer 16 bits per texel +msgstr Prefereix 16 bits per texel + +#: t_options.h:132 +msgid Force 16 bits per texel +msgstr Força 16 bits per texel
Mesa (master): i965: Remove CACHED_BATCH support altogether.
Module: Mesa
Branch: master
Commit: 1c5e2965a0de296240dd8f5af12482164416b7f1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c5e2965a0de296240dd8f5af12482164416b7f1
Author: Kenneth Graunke kenn...@whitecape.org
Date: Mon Aug 26 13:11:21 2013 -0700
i965: Remove CACHED_BATCH support altogether.
Using an unoptimized variant of glamor spending 50% of its CPU time in
brw_draw_prims() (and hitting the cache *very* frequently):
N Min MaxMedian AvgStddev
x 200 29200 40500 34900 34750 958.43256
+ 200 31000 40300 34700 34622 916.35941
No difference proven at 95.0% confidence
Similarly, no difference on GLB2.7:
N Min MaxMedian AvgStddev
x 63 64.1 71.36 70.69 70.113175 1.6782026
+ 63 63.6 71.18 70.75 70.223651 1.6044186
No difference proven at 95.0% confidence
v2: Rebase on master (by anholt)
v3: Add a missing BEGIN_BATCH(3) to aa_line_parameters -- CACHED_BATCH
didn't have the asserts about batchbuffer usage that ADVANCE_BATCH
does, so we started assertion failing.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Signed-off-by: Eric Anholt e...@anholt.net
Reviewed-by: Eric Anholt e...@anholt.net
---
src/mesa/drivers/dri/i965/brw_cc.c|2 +-
src/mesa/drivers/dri/i965/brw_curbe.c |2 +-
src/mesa/drivers/dri/i965/brw_draw_upload.c |4 +--
src/mesa/drivers/dri/i965/brw_misc_state.c|9 +++---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 42 -
src/mesa/drivers/dri/i965/intel_batchbuffer.h |3 --
6 files changed, 9 insertions(+), 53 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cc.c
b/src/mesa/drivers/dri/i965/brw_cc.c
index 840f960..2f4e9dc 100644
--- a/src/mesa/drivers/dri/i965/brw_cc.c
+++ b/src/mesa/drivers/dri/i965/brw_cc.c
@@ -247,7 +247,7 @@ static void upload_blend_constant_color(struct brw_context
*brw)
OUT_BATCH_F(ctx-Color.BlendColorUnclamped[1]);
OUT_BATCH_F(ctx-Color.BlendColorUnclamped[2]);
OUT_BATCH_F(ctx-Color.BlendColorUnclamped[3]);
- CACHED_BATCH();
+ ADVANCE_BATCH();
}
const struct brw_tracked_state brw_blend_constant_color = {
diff --git a/src/mesa/drivers/dri/i965/brw_curbe.c
b/src/mesa/drivers/dri/i965/brw_curbe.c
index 9e556fb..bb1c797 100644
--- a/src/mesa/drivers/dri/i965/brw_curbe.c
+++ b/src/mesa/drivers/dri/i965/brw_curbe.c
@@ -161,7 +161,7 @@ void brw_upload_cs_urb_state(struct brw_context *brw)
assert(brw-urb.nr_cs_entries);
OUT_BATCH((brw-urb.csize - 1) 4 | brw-urb.nr_cs_entries);
}
- CACHED_BATCH();
+ ADVANCE_BATCH();
}
static GLfloat fixed_plane[6][4] = {
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index 4959a08..5418398 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -643,7 +643,7 @@ static void brw_emit_vertices(struct brw_context *brw)
(BRW_VE1_COMPONENT_STORE_0 BRW_VE1_COMPONENT_1_SHIFT) |
(BRW_VE1_COMPONENT_STORE_0 BRW_VE1_COMPONENT_2_SHIFT) |
(BRW_VE1_COMPONENT_STORE_1_FLT BRW_VE1_COMPONENT_3_SHIFT));
- CACHED_BATCH();
+ ADVANCE_BATCH();
return;
}
@@ -808,7 +808,7 @@ static void brw_emit_vertices(struct brw_context *brw)
OUT_BATCH(dw1);
}
- CACHED_BATCH();
+ ADVANCE_BATCH();
}
const struct brw_tracked_state brw_vertices = {
diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c
b/src/mesa/drivers/dri/i965/brw_misc_state.c
index 6d1004e..70dc071 100644
--- a/src/mesa/drivers/dri/i965/brw_misc_state.c
+++ b/src/mesa/drivers/dri/i965/brw_misc_state.c
@@ -778,7 +778,7 @@ static void upload_polygon_stipple(struct brw_context *brw)
for (i = 0; i 32; i++)
OUT_BATCH(ctx-PolygonStipple[i]);
}
- CACHED_BATCH();
+ ADVANCE_BATCH();
}
const struct brw_tracked_state brw_polygon_stipple = {
@@ -822,7 +822,7 @@ static void upload_polygon_stipple_offset(struct
brw_context *brw)
OUT_BATCH((32 - (ctx-DrawBuffer-Height 31)) 31);
else
OUT_BATCH(0);
- CACHED_BATCH();
+ ADVANCE_BATCH();
}
const struct brw_tracked_state brw_polygon_stipple_offset = {
@@ -852,11 +852,12 @@ static void upload_aa_line_parameters(struct brw_context
*brw)
if (brw-gen == 6)
intel_emit_post_sync_nonzero_flush(brw);
+ BEGIN_BATCH(3);
OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS 16 | (3 - 2));
/* use legacy aa line coverage computation */
OUT_BATCH(0);
OUT_BATCH(0);
- CACHED_BATCH();
+ ADVANCE_BATCH();
}
const struct brw_tracked_state brw_aa_line_parameters = {
@@ -901,7 +902,7 @@ static void upload_line_stipple(struct brw_context *brw)
OUT_BATCH(tmpi 16 | ctx-Line.StippleFactor);
}
- CACHED_BATCH
Mesa (master): i965: Stop doing our optimization on a copy of the GLSL IR.
Module: Mesa
Branch: master
Commit: 26a3bf5c726199d7664d5878ef1f73592e55caa7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=26a3bf5c726199d7664d5878ef1f73592e55caa7
Author: Eric Anholt e...@anholt.net
Date: Thu Nov 28 00:48:57 2013 -0800
i965: Stop doing our optimization on a copy of the GLSL IR.
The original intent was that we'd keep a driver-private copy, and there
would be the normal copy for swrast to make use of without the tuning (or
anything more invasive we might do) specific to i965. Only, we don't
generate swrast code any more, because swrast can't render current shaders
anyway. Thus, our private copy is rather a waste, and we can just do our
backend-specific operations on the linked shader.
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i965/brw_context.h |3 --
src/mesa/drivers/dri/i965/brw_fs.cpp |4 +-
src/mesa/drivers/dri/i965/brw_shader.cpp | 55 +
src/mesa/drivers/dri/i965/brw_vec4.cpp|4 +-
src/mesa/drivers/dri/i965/brw_vec4_gs_visitor.cpp |2 +-
5 files changed, 28 insertions(+), 40 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index e19ffc0..9c51646 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -320,9 +320,6 @@ struct brw_shader {
struct gl_shader base;
bool compiled_once;
-
- /** Shader IR transformed for native compile, at link time. */
- struct exec_list *ir;
};
/* Note: If adding fields that need anything besides a normal memcmp() for
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index baf9220..3536cbe 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -3156,7 +3156,7 @@ fs_visitor::run()
* functions called main).
*/
if (shader) {
- foreach_list(node, *shader-ir) {
+ foreach_list(node, *shader-base.ir) {
ir_instruction *ir = (ir_instruction *)node;
base_ir = ir;
this-result = reg_undef;
@@ -3305,7 +3305,7 @@ brw_wm_fs_emit(struct brw_context *brw, struct
brw_wm_compile *c,
if (unlikely(INTEL_DEBUG DEBUG_WM)) {
if (prog) {
printf(GLSL IR for native fragment shader %d:\n, prog-Name);
- _mesa_print_ir(shader-ir, NULL);
+ _mesa_print_ir(shader-base.ir, NULL);
printf(\n\n);
} else {
printf(ARB_fragment_program %d ir for native fragment shader\n,
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index cf9ca4b..5752348 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -135,24 +135,18 @@ brw_link_shader(struct gl_context *ctx, struct
gl_shader_program *shProg)
_mesa_copy_linked_program_data((gl_shader_stage) stage, shProg, prog);
- void *mem_ctx = ralloc_context(NULL);
bool progress;
- if (shader-ir)
-ralloc_free(shader-ir);
- shader-ir = new(shader) exec_list;
- clone_ir_list(mem_ctx, shader-ir, shader-base.ir);
-
/* lower_packing_builtins() inserts arithmetic instructions, so it
* must precede lower_instructions().
*/
- brw_lower_packing_builtins(brw, (gl_shader_stage) stage, shader-ir);
- do_mat_op_to_vec(shader-ir);
+ brw_lower_packing_builtins(brw, (gl_shader_stage) stage,
shader-base.ir);
+ do_mat_op_to_vec(shader-base.ir);
const int bitfield_insert = brw-gen = 7
? BITFIELD_INSERT_TO_BFM_BFI
: 0;
const int lrp_to_arith = brw-gen 6 ? LRP_TO_ARITH : 0;
- lower_instructions(shader-ir,
+ lower_instructions(shader-base.ir,
MOD_TO_FRACT |
DIV_TO_MUL_RCP |
SUB_TO_ADD_NEG |
@@ -166,17 +160,17 @@ brw_link_shader(struct gl_context *ctx, struct
gl_shader_program *shProg)
* if-statements need to be flattened.
*/
if (brw-gen 6)
-lower_if_to_cond_assign(shader-ir, 16);
-
- do_lower_texture_projection(shader-ir);
- brw_lower_texture_gradients(brw, shader-ir);
- do_vec_index_to_cond_assign(shader-ir);
- lower_vector_insert(shader-ir, true);
- brw_do_cubemap_normalize(shader-ir);
- brw_do_lower_offset_arrays(shader-ir);
- brw_do_lower_unnormalized_offset(shader-ir);
- lower_noise(shader-ir);
- lower_quadop_vector(shader-ir, false);
+lower_if_to_cond_assign(shader-base.ir, 16);
+
+ do_lower_texture_projection(shader-base.ir);
+ brw_lower_texture_gradients(brw, shader-base.ir);
+ do_vec_index_to_cond_assign(shader-base.ir);
+ lower_vector_insert(shader-base.ir, true);
+ brw_do_cubemap_normalize(shader-base.ir
Mesa (master): i965: Replace 8-wide and 16-wide with SIMD8 and SIMD16.
Module: Mesa
Branch: master
Commit: 746e3e3b3ad20a29ee6de64d663d2dc11deac06e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=746e3e3b3ad20a29ee6de64d663d2dc11deac06e
Author: Eric Anholt e...@anholt.net
Date: Tue Nov 12 15:33:27 2013 -0800
i965: Replace 8-wide and 16-wide with SIMD8 and SIMD16.
Those are the terms used in the docs, and think n-wide was something I
just happened to say. Note that shader-db needs updating for the
INTEL_DEBUG=fs parsing.
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i965/brw_eu.c |8 +++---
src/mesa/drivers/dri/i965/brw_fs.cpp | 30 ++--
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 14 -
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp |8 +++---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 22 +++---
.../drivers/dri/i965/brw_schedule_instructions.cpp |6 ++--
6 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu.c
b/src/mesa/drivers/dri/i965/brw_eu.c
index 5a07d83..dee9112 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -112,7 +112,7 @@ brw_set_compression_control(struct brw_compile *p,
p-compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
if (p-brw-gen = 6) {
- /* Since we don't use the 32-wide support in gen6, we translate
+ /* Since we don't use the SIMD32 support in gen6, we translate
* the pre-gen6 compression control here.
*/
switch (compression_control) {
@@ -123,12 +123,12 @@ brw_set_compression_control(struct brw_compile *p,
p-current-header.compression_control = GEN6_COMPRESSION_1Q;
break;
case BRW_COMPRESSION_2NDHALF:
-/* For 8-wide, this is use the second set of 8 bits. */
+/* For SIMD8, this is use the second set of 8 bits. */
p-current-header.compression_control = GEN6_COMPRESSION_2Q;
break;
case BRW_COMPRESSION_COMPRESSED:
-/* For 16-wide instruction compression, use the first set of 16 bits
- * since we don't do 32-wide dispatch.
+/* For SIMD16 instruction compression, use the first set of 16 bits
+ * since we don't do SIMD32 dispatch.
*/
p-current-header.compression_control = GEN6_COMPRESSION_1H;
break;
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 3536cbe..37329b9 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -856,7 +856,7 @@ import_uniforms_callback(const void *key,
hash_table_insert(dst_ht, data, key);
}
-/* For 16-wide, we need to follow from the uniform setup of 8-wide dispatch.
+/* For SIMD16, we need to follow from the uniform setup of SIMD8 dispatch.
* This brings in those uniform definitions
*/
void
@@ -1340,7 +1340,7 @@ fs_visitor::emit_math(enum opcode opcode, fs_reg dst,
fs_reg src0, fs_reg src1)
case SHADER_OPCODE_INT_QUOTIENT:
case SHADER_OPCODE_INT_REMAINDER:
if (brw-gen = 7 dispatch_width == 16)
-fail(16-wide INTDIV unsupported\n);
+fail(SIMD16 INTDIV unsupported\n);
break;
case SHADER_OPCODE_POW:
break;
@@ -1764,7 +1764,7 @@ fs_visitor::remove_dead_constants()
c-prog_data.nr_params = new_nr_params;
} else {
- /* This should have been generated in the 8-wide pass already. */
+ /* This should have been generated in the SIMD8 pass already. */
assert(this-params_remap);
}
@@ -1883,7 +1883,7 @@ fs_visitor::setup_pull_constants()
return;
if (dispatch_width == 16) {
- fail(Pull constants not supported in 16-wide\n);
+ fail(Pull constants not supported in SIMD16\n);
return;
}
@@ -2557,7 +2557,7 @@ static void
clear_deps_for_inst_src(fs_inst *inst, int dispatch_width, bool *deps,
int first_grf, int grf_len)
{
- bool inst_16wide = (dispatch_width 8
+ bool inst_simd16 = (dispatch_width 8
!inst-force_uncompressed
!inst-force_sechalf);
@@ -2576,7 +2576,7 @@ clear_deps_for_inst_src(fs_inst *inst, int
dispatch_width, bool *deps,
if (grf = first_grf
grf first_grf + grf_len) {
deps[grf - first_grf] = false;
- if (inst_16wide)
+ if (inst_simd16)
deps[grf - first_grf + 1] = false;
}
}
@@ -2634,7 +2634,7 @@
fs_visitor::insert_gen4_pre_send_dependency_workarounds(fs_inst *inst)
return;
}
- bool scan_inst_16wide = (dispatch_width 8
+ bool scan_inst_simd16 = (dispatch_width 8
!scan_inst-force_uncompressed
!scan_inst-force_sechalf);
@@ -2651,7 +2651,7 @@
fs_visitor::insert_gen4_pre_send_dependency_workarounds(fs_inst *inst)
needs_dep[reg
Mesa (master): i965: Don't call the blitter on addresses it can't handle.
Module: Mesa
Branch: master
Commit: bdc5241af4aa9afbd66f6c96ee6d20e09f77ea89
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bdc5241af4aa9afbd66f6c96ee6d20e09f77ea89
Author: Eric Anholt e...@anholt.net
Date: Mon Dec 23 15:30:03 2013 -0800
i965: Don't call the blitter on addresses it can't handle.
Noticed by tex3d-maxsize on my next commit to check that our addresses
don't overflow.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/intel_blit.c| 20
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 23 ---
2 files changed, 40 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
b/src/mesa/drivers/dri/i965/intel_blit.c
index 7bc289f..13cc777 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -229,12 +229,32 @@ intel_miptree_blit(struct brw_context *brw,
src_x += src_image_x;
src_y += src_image_y;
+ /* The blitter interprets the 16-bit src x/y as a signed 16-bit value,
+* where negative values are invalid. The values we're working with are
+* unsigned, so make sure we don't overflow.
+*/
+ if (src_x = 32768 || src_y = 32768) {
+ perf_debug(Falling back due to =32k src offset (%d, %d)\n,
+ src_x, src_y);
+ return false;
+ }
+
uint32_t dst_image_x, dst_image_y;
intel_miptree_get_image_offset(dst_mt, dst_level, dst_slice,
dst_image_x, dst_image_y);
dst_x += dst_image_x;
dst_y += dst_image_y;
+ /* The blitter interprets the 16-bit destination x/y as a signed 16-bit
+* value. The values we're working with are unsigned, so make sure we
+* don't overflow.
+*/
+ if (dst_x = 32768 || dst_y = 32768) {
+ perf_debug(Falling back due to =32k dst offset (%d, %d)\n,
+ dst_x, dst_y);
+ return false;
+ }
+
if (!intelEmitCopyBlit(brw,
src_mt-cpp,
src_pitch,
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index de47143..0818226 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -443,7 +443,8 @@ intel_miptree_choose_tiling(struct brw_context *brw,
if (minimum_pitch 64)
return I915_TILING_NONE;
- if (ALIGN(minimum_pitch, 512) = 32768) {
+ if (ALIGN(minimum_pitch, 512) = 32768 ||
+ mt-total_width = 32768 || mt-total_height = 32768) {
perf_debug(%dx%d miptree too large to blit, falling back to untiled,
mt-total_width, mt-total_height);
return I915_TILING_NONE;
@@ -2233,6 +2234,22 @@ intel_miptree_release_map(struct intel_mipmap_tree *mt,
*map = NULL;
}
+static bool
+can_blit_slice(struct intel_mipmap_tree *mt,
+ unsigned int level, unsigned int slice)
+{
+ uint32_t image_x;
+ uint32_t image_y;
+ intel_miptree_get_image_offset(mt, level, slice, image_x, image_y);
+ if (image_x = 32768 || image_y = 32768)
+ return false;
+
+ if (mt-region-pitch = 32768)
+ return false;
+
+ return true;
+}
+
static void
intel_miptree_map_singlesample(struct brw_context *brw,
struct intel_mipmap_tree *mt,
@@ -2276,11 +2293,11 @@ intel_miptree_map_singlesample(struct brw_context *brw,
!mt-compressed
(mt-region-tiling == I915_TILING_X ||
(brw-gen = 6 mt-region-tiling == I915_TILING_Y))
-mt-region-pitch 32768) {
+can_blit_slice(mt, level, slice)) {
intel_miptree_map_blit(brw, mt, map, level, slice);
} else if (mt-region-tiling != I915_TILING_NONE
mt-region-bo-size = brw-max_gtt_map_object_size) {
- assert(mt-region-pitch 32768);
+ assert(can_blit_slice(mt, level, slice));
intel_miptree_map_blit(brw, mt, map, level, slice);
#ifdef __SSE4_1__
} else if (!(mode GL_MAP_WRITE_BIT) !mt-compressed) {
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Mesa (master): i965: Don' t do the temporary-and-blit-copy for INVALIDATE_RANGE maps.
Module: Mesa
Branch: master
Commit: f46563fe1c8a5560e4de0adf03e3d8770b7fc734
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f46563fe1c8a5560e4de0adf03e3d8770b7fc734
Author: Eric Anholt e...@anholt.net
Date: Tue Dec 24 15:11:54 2013 -0800
i965: Don't do the temporary-and-blit-copy for INVALIDATE_RANGE maps.
We definitely want to fall through to the unsynchronized map case, instead
of wasting bandwidth on a copy. Prevents a -43.2407% +/- 1.06113% (n=49)
performance regression on aa10perf when teaching glamor to provide the
GL_INVALIDATE_RANGE_BIT information.
This is a performance fix, which I usually wouldn't cherry-pick to stable.
But this was really was just a bug in the code, its presence would
discourage developers from giving us the best information they can, and I
think we've got fairly high confidence in the unsynchronized map path
already.
Cc: 10.0 9.2 mesa-sta...@lists.freedesktop.org
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/intel_buffer_objects.c |3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index cab805a..84bc29d 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -357,7 +357,8 @@ intel_bufferobj_map_range(struct gl_context * ctx,
* BO, and we'll copy what they put in there out at unmap or
* FlushRange time.
*/
- if ((access GL_MAP_INVALIDATE_RANGE_BIT)
+ if (!(access GL_MAP_UNSYNCHRONIZED_BIT)
+ (access GL_MAP_INVALIDATE_RANGE_BIT)
drm_intel_bo_busy(intel_obj-buffer)) {
if (access GL_MAP_FLUSH_EXPLICIT_BIT) {
intel_obj-range_map_buffer = malloc(length);
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Mesa (master): i965: Fix handling of MESA_pack_invert in blit (PBO) readpixels.
Module: Mesa
Branch: master
Commit: e186b927b8254ce62e0d47db90d16cd4253b3db5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e186b927b8254ce62e0d47db90d16cd4253b3db5
Author: Eric Anholt e...@anholt.net
Date: Mon Dec 23 12:11:25 2013 -0800
i965: Fix handling of MESA_pack_invert in blit (PBO) readpixels.
Fixes piglit GL_MESA_pack_invert/readpixels and GPU hangs with glamor and
cairo-gl.
Cc: 10.0 9.2 mesa-sta...@lists.freedesktop.org
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/intel_pixel_read.c |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c
b/src/mesa/drivers/dri/i965/intel_pixel_read.c
index 0f6d2aa..2c85811 100644
--- a/src/mesa/drivers/dri/i965/intel_pixel_read.c
+++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c
@@ -106,13 +106,15 @@ do_blit_readpixels(struct gl_context * ctx,
/* Mesa flips the dst_stride for pack-Invert, but we want our mt to have a
* normal dst_stride.
*/
+ struct gl_pixelstore_attrib uninverted_pack = *pack;
if (pack-Invert) {
dst_stride = -dst_stride;
dst_flip = true;
+ uninverted_pack.Invert = false;
}
dst_offset = (GLintptr)pixels;
- dst_offset += _mesa_image_offset(2, pack, width, height,
+ dst_offset += _mesa_image_offset(2, uninverted_pack, width, height,
format, type, 0, 0, 0);
if (!_mesa_clip_copytexsubimage(ctx,
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Mesa (master): i965: Add a safety check for emitting blits.
Module: Mesa Branch: master Commit: 98cdb2ceede34ad04cd8f65691bd96fbb44bcced URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=98cdb2ceede34ad04cd8f65691bd96fbb44bcced Author: Eric Anholt e...@anholt.net Date: Mon Dec 23 01:26:56 2013 -0800 i965: Add a safety check for emitting blits. With all of the flipping and pitch twiddling and miptree layout involved in our blits, there are lots of ways for us to scribble outside of a buffer. Put in a check that we're not about to do so. This catches a bug that glamor was running into. Reviewed-by: Kenneth Graunke kenn...@whitecape.org Reviewed-by: Ian Romanick ian.d.roman...@intel.com Reviewed-by: Anuj Phogat anuj.pho...@gmail.com --- src/mesa/drivers/dri/i965/intel_blit.c |4 1 file changed, 4 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 13cc777..9162b1f 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -391,6 +391,10 @@ intelEmitCopyBlit(struct brw_context *brw, assert(dst_x dst_x2); assert(dst_y dst_y2); + assert(src_offset + (src_y + h - 1) * abs(src_pitch) + + (w * cpp) = src_buffer-size); + assert(dst_offset + (dst_y + h - 1) * abs(dst_pitch) + + (w * cpp) = dst_buffer-size); BEGIN_BATCH_BLT_TILED(8, dst_y_tiled, src_y_tiled); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Add an assert for when SET_FIELD' s value exceeds the field size.
Module: Mesa
Branch: master
Commit: 5d2e86924ebe7b520a5964e9c90c5bb7213c67cf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d2e86924ebe7b520a5964e9c90c5bb7213c67cf
Author: Eric Anholt e...@anholt.net
Date: Mon Dec 23 01:39:42 2013 -0800
i965: Add an assert for when SET_FIELD's value exceeds the field size.
This was one of the things we always wanted to do to this, to make it more
useful than just (value FIELD_MASK).
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_defines.h |8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 0fc24a7..78df0b8 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -30,7 +30,13 @@
*/
#define INTEL_MASK(high, low) (((1((high)-(low)+1))-1)(low))
-#define SET_FIELD(value, field) (((value) field ## _SHIFT) field ## _MASK)
+#define SET_FIELD(value, field) \
+ ({ \
+ uint32_t fieldval = (value) field ## _SHIFT; \
+ assert((fieldval ~ field ## _MASK) == 0); \
+ fieldval field ## _MASK;\
+ })
+
#define GET_FIELD(word, field) (((word) field ## _MASK) field ## _SHIFT)
#ifndef BRW_DEFINES_H
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Mesa (master): i965: Fix incorrect bounds tracking for blit readpixels' s GPU access.
Module: Mesa Branch: master Commit: a4b222ac135c28a3bc95cc0d9fd29378540c8def URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4b222ac135c28a3bc95cc0d9fd29378540c8def Author: Eric Anholt e...@anholt.net Date: Mon Dec 23 01:56:26 2013 -0800 i965: Fix incorrect bounds tracking for blit readpixels's GPU access. While incorrect, it probably wouldn't affect anyone ever: You'd have to do an appropriately-formatted readpixels into a PBO, then overwrite the tail end of the updated area of the PBO with glBufferSubData(), and you wouldn't get appropriate synchronization. Reviewed-by: Kenneth Graunke kenn...@whitecape.org Reviewed-by: Ian Romanick ian.d.roman...@intel.com Reviewed-by: Anuj Phogat anuj.pho...@gmail.com --- src/mesa/drivers/dri/i965/intel_pixel_read.c |3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c b/src/mesa/drivers/dri/i965/intel_pixel_read.c index 08cb762..0f6d2aa 100644 --- a/src/mesa/drivers/dri/i965/intel_pixel_read.c +++ b/src/mesa/drivers/dri/i965/intel_pixel_read.c @@ -127,8 +127,7 @@ do_blit_readpixels(struct gl_context * ctx, brw-front_buffer_dirty = dirty; dst_buffer = intel_bufferobj_buffer(brw, dst, - dst_offset, width * height * - irb-mt-cpp); + dst_offset, height * dst_stride); struct intel_mipmap_tree *pbo_mt = intel_miptree_create_for_bo(brw, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Use SET_FIELD to safety check our x/ y offsets in blits.
Module: Mesa
Branch: master
Commit: 66524daf175950bd7266fc3cbb4125c24984a482
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=66524daf175950bd7266fc3cbb4125c24984a482
Author: Eric Anholt e...@anholt.net
Date: Mon Dec 23 01:48:09 2013 -0800
i965: Use SET_FIELD to safety check our x/y offsets in blits.
The earlier assert made sure that our math didn't exceed our bounds, but
this makes sure that we don't overflow from the high bits X into the low
bits of Y. We've already put checks in intel_miptree_blit(), but I've
wanted to expand the type in our protoype from short to uint32_t, and we
could get in trouble with intel_emit_linear_blit() if we did.
v2: Add Ken's comment about the funny language extension used.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Ian Romanick ian.d.roman...@intel.com (v1)
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com (v1)
---
src/mesa/drivers/dri/i965/brw_defines.h |6 ++
src/mesa/drivers/dri/i965/intel_blit.c | 15 ---
2 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 78df0b8..142b2db 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -30,6 +30,7 @@
*/
#define INTEL_MASK(high, low) (((1((high)-(low)+1))-1)(low))
+/* Using the GNU statement expression extension */
#define SET_FIELD(value, field) \
({ \
uint32_t fieldval = (value) field ## _SHIFT; \
@@ -1919,6 +1920,11 @@ enum brw_wm_barycentric_interp_mode {
#define CMD_MI_FLUSH 0x0200
+# define BLT_X_SHIFT 0
+# define BLT_X_MASKINTEL_MASK(15, 0)
+# define BLT_Y_SHIFT 16
+# define BLT_Y_MASKINTEL_MASK(31, 16)
+
#define GEN5_MI_REPORT_PERF_COUNT ((0x26 23) | (3 - 2))
/* DW0 */
# define GEN5_MI_COUNTER_SET_0 (0 6)
diff --git a/src/mesa/drivers/dri/i965/intel_blit.c
b/src/mesa/drivers/dri/i965/intel_blit.c
index 9162b1f..330bac4 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -33,6 +33,7 @@
#include main/fbobject.h
#include brw_context.h
+#include brw_defines.h
#include intel_blit.h
#include intel_buffers.h
#include intel_fbo.h
@@ -400,12 +401,12 @@ intelEmitCopyBlit(struct brw_context *brw,
OUT_BATCH(CMD | (8 - 2));
OUT_BATCH(BR13 | (uint16_t)dst_pitch);
- OUT_BATCH((dst_y 16) | dst_x);
- OUT_BATCH((dst_y2 16) | dst_x2);
+ OUT_BATCH(SET_FIELD(dst_y, BLT_Y) | SET_FIELD(dst_x, BLT_X));
+ OUT_BATCH(SET_FIELD(dst_y2, BLT_Y) | SET_FIELD(dst_x2, BLT_X));
OUT_RELOC(dst_buffer,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
dst_offset);
- OUT_BATCH((src_y 16) | src_x);
+ OUT_BATCH(SET_FIELD(src_y, BLT_Y) | SET_FIELD(src_x, BLT_X));
OUT_BATCH((uint16_t)src_pitch);
OUT_RELOC(src_buffer, I915_GEM_DOMAIN_RENDER, 0, src_offset);
@@ -479,8 +480,8 @@ intelEmitImmediateColorExpandBlit(struct brw_context *brw,
OUT_BATCH(0); /* pattern base addr */
OUT_BATCH(blit_cmd | ((3 - 2) + dwords));
- OUT_BATCH((y 16) | x);
- OUT_BATCH(((y + h) 16) | (x + w));
+ OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
+ OUT_BATCH(SET_FIELD(y + h, BLT_Y) | SET_FIELD(x + w, BLT_X));
ADVANCE_BATCH();
intel_batchbuffer_data(brw, src_bits, dwords * 4, BLT_RING);
@@ -588,8 +589,8 @@ intel_miptree_set_alpha_to_one(struct brw_context *brw,
BEGIN_BATCH_BLT_TILED(6, dst_y_tiled, false);
OUT_BATCH(CMD | (6 - 2));
OUT_BATCH(BR13);
- OUT_BATCH((y 16) | x);
- OUT_BATCH(((y + height) 16) | (x + width));
+ OUT_BATCH(SET_FIELD(y, BLT_Y) | SET_FIELD(x, BLT_X));
+ OUT_BATCH(SET_FIELD(y + height, BLT_Y) | SET_FIELD(x + width, BLT_X));
OUT_RELOC(region-bo,
I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER,
0);
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Mesa (master): i965: Fix streamed state dumping/ annotation after the blorp-flush change.
Module: Mesa Branch: master Commit: 5891f981452c1c5ed45b5a7e5fe54a9884ced2b6 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=5891f981452c1c5ed45b5a7e5fe54a9884ced2b6 Author: Eric Anholt e...@anholt.net Date: Tue Nov 19 16:00:28 2013 -0800 i965: Fix streamed state dumping/annotation after the blorp-flush change. I think I was thinking of the batch command packet cache when I pasted this in, but this counter is only used for dumping out streamed state for INTEL_DEBUG=batch and for putting annotations in our aub files. Cc: 10.0 mesa-sta...@lists.freedesktop.org Reviewed-by: Kenneth Graunke kenn...@whitecape.org --- src/mesa/drivers/dri/i965/brw_blorp.cpp |1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index e555f46..6b3600d 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.cpp +++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp @@ -266,7 +266,6 @@ retry: */ brw-state.dirty.brw = ~0; brw-state.dirty.cache = ~0; - brw-state_batch_count = 0; brw-batch.need_workaround_flush = true; brw-ib.type = -1; intel_batchbuffer_clear_cache(brw); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa: Remove the ralloc canary on release builds.
Module: Mesa
Branch: master
Commit: 09db4940eede4236b47e1328503a719719f5c981
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=09db4940eede4236b47e1328503a719719f5c981
Author: Eric Anholt e...@anholt.net
Date: Thu Nov 21 23:29:56 2013 -0800
mesa: Remove the ralloc canary on release builds.
The canary is basically just to give a better debugging message when you
ralloc_free() something that wasn't rallocated. Reduces maximum memory
usage of apitrace replay of the dota2 demo by 60MB on my 64-bit system (so
half that on a real 32-bit dota2 environment).
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/glsl/ralloc.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/src/glsl/ralloc.c b/src/glsl/ralloc.c
index e79dad7..36bc61f 100644
--- a/src/glsl/ralloc.c
+++ b/src/glsl/ralloc.c
@@ -53,8 +53,10 @@ _CRTIMP int _vscprintf(const char *format, va_list argptr);
struct ralloc_header
{
+#ifdef DEBUG
/* A canary value used to determine whether a pointer is ralloc'd. */
unsigned canary;
+#endif
struct ralloc_header *parent;
@@ -78,7 +80,9 @@ get_header(const void *ptr)
{
ralloc_header *info = (ralloc_header *) (((char *) ptr) -
sizeof(ralloc_header));
+#ifdef DEBUG
assert(info-canary == CANARY);
+#endif
return info;
}
@@ -117,7 +121,9 @@ ralloc_size(const void *ctx, size_t size)
add_child(parent, info);
+#ifdef DEBUG
info-canary = CANARY;
+#endif
return PTR_FROM_HEADER(info);
}
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Mesa (master): i965/fs: Make the first pre-allocation heuristic be the post heuristic.
Module: Mesa
Branch: master
Commit: 46cf80fb366cb14827724a7fea004e81400cc602
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=46cf80fb366cb14827724a7fea004e81400cc602
Author: Eric Anholt e...@anholt.net
Date: Tue Nov 19 13:07:12 2013 -0800
i965/fs: Make the first pre-allocation heuristic be the post heuristic.
I recently made us try two different things that tried to reduce register
pressure so that we would be more likely to allocate successfully. But
now that we have the logic for trying two, we can make the first thing we
try be the normal, not-prioritizing-register-pressure heuristic.
This means one less scheduling pass in the common case of that heuristic
not producing spills, plus the best schedule we know how to produce, if
that one happens to succeed. This is important, because our register
allocation produces a lot of possibly avoidable dependencies for the
post-register-allocation schedule, despite ra_set_allocate_round_robin().
GLB2.7: 1.04127% +/- 0.732461% fps improvement (n=31)
nexuiz: No difference (n=5)
lightsmark: 0.838512% +/- 0.300147% fps improvement (n=86)
minecraft apitrace: No difference (n=15)
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 62 +---
.../drivers/dri/i965/brw_schedule_instructions.cpp |4 +-
src/mesa/drivers/dri/i965/brw_shader.h |1 +
3 files changed, 44 insertions(+), 23 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index d004521..261f906 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -3192,6 +3192,7 @@ fs_visitor::run()
{
sanity_param_count = fp-Base.Parameters-NumParameters;
uint32_t orig_nr_params = c-prog_data.nr_params;
+ bool allocated_without_spills;
assign_binding_table_offsets();
@@ -3276,27 +3277,45 @@ fs_visitor::run()
assign_curb_setup();
assign_urb_setup();
- schedule_instructions(SCHEDULE_PRE_NON_LIFO);
+ static enum instruction_scheduler_mode pre_modes[] = {
+ SCHEDULE_PRE,
+ SCHEDULE_PRE_NON_LIFO,
+ SCHEDULE_PRE_LIFO,
+ };
- if (0)
-assign_regs_trivial();
- else {
- if (!assign_regs(false)) {
-/* Try a non-spilling register allocation again with a different
- * scheduling heuristic.
- */
-schedule_instructions(SCHEDULE_PRE_LIFO);
-if (!assign_regs(false)) {
- if (dispatch_width == 16) {
- fail(Failure to register allocate. Reduce number of
- live scalar values to avoid this.);
- } else {
- while (!assign_regs(true)) {
- if (failed)
-break;
- }
- }
-}
+ /* Try each scheduling heuristic to see if it can successfully register
+ * allocate without spilling. They should be ordered by decreasing
+ * performance but increasing likelihood of allocating.
+ */
+ for (unsigned i = 0; i ARRAY_SIZE(pre_modes); i++) {
+ schedule_instructions(pre_modes[i]);
+
+ if (0) {
+assign_regs_trivial();
+allocated_without_spills = true;
+ } else {
+allocated_without_spills = assign_regs(false);
+ }
+ if (allocated_without_spills)
+break;
+ }
+
+ if (!allocated_without_spills) {
+ /* We assume that any spilling is worse than just dropping back to
+ * SIMD8. There's probably actually some intermediate point where
+ * SIMD16 with a couple of spills is still better.
+ */
+ if (dispatch_width == 16) {
+fail(Failure to register allocate. Reduce number of
+ live scalar values to avoid this.);
+ }
+
+ /* Since we're out of heuristics, just go spill registers until we
+ * get an allocation.
+ */
+ while (!assign_regs(true)) {
+if (failed)
+ break;
}
}
}
@@ -3311,7 +3330,8 @@ fs_visitor::run()
if (failed)
return false;
- schedule_instructions(SCHEDULE_POST);
+ if (!allocated_without_spills)
+ schedule_instructions(SCHEDULE_POST);
if (dispatch_width == 8) {
c-prog_data.reg_blocks = brw_register_blocks(grf_used);
diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 1050d67..baf67fb 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -1140,10 +1140,10 @@
fs_instruction_scheduler::choose_instruction_to_schedule()
{
schedule_node *chosen = NULL;
- if (post_reg_alloc) {
+ if (mode == SCHEDULE_PRE || mode == SCHEDULE_POST) {
int
Mesa (master): mesa: Fix setup of LocalParams array.
Module: Mesa
Branch: master
Commit: 81ff29e30c573fcc134bf717670015ab4654ebcd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=81ff29e30c573fcc134bf717670015ab4654ebcd
Author: Eric Anholt e...@anholt.net
Date: Mon Nov 18 09:55:00 2013 -0800
mesa: Fix setup of LocalParams array.
i965 passed piglit, but swrast and gallium both segfaulted without this.
i965 happened to work because it never ran _mesa_load_state_parameters()
on the new program before the test called glProgramLocalParameter(), which
was allocating a LocalParams array for the fallback path.
v2: Since v1 threw away old localparams data, leaked old LocalParams
memory, only fixed fragment programs, and I was dubious of my previous
invariants already (nothing but program_parse.y will generate
LocalParams, and only that one path of program_parse.y will), just
late-allocate localparams at the other point of dereferencing them.
This adds overhead to _mesa_load_state_parameter, which is
uncomfortable, but I'm pretty sure that giant switch statement is
super slow already.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=71734
Tested-by: Michel Dänzer michel.daen...@amd.com
---
src/mesa/program/prog_statevars.c | 14 ++
src/mesa/program/program_parse.y |7 ---
2 files changed, 14 insertions(+), 7 deletions(-)
diff --git a/src/mesa/program/prog_statevars.c
b/src/mesa/program/prog_statevars.c
index f6fd535..58e1f49 100644
--- a/src/mesa/program/prog_statevars.c
+++ b/src/mesa/program/prog_statevars.c
@@ -368,6 +368,13 @@ _mesa_fetch_state(struct gl_context *ctx, const
gl_state_index state[],
COPY_4V(value, ctx-FragmentProgram.Parameters[idx]);
return;
case STATE_LOCAL:
+ if (!ctx-FragmentProgram.Current-Base.LocalParams) {
+ ctx-FragmentProgram.Current-Base.LocalParams =
+ calloc(MAX_PROGRAM_LOCAL_PARAMS, sizeof(float[4]));
+ if (!ctx-FragmentProgram.Current-Base.LocalParams)
+ return;
+ }
+
COPY_4V(value,
ctx-FragmentProgram.Current-Base.LocalParams[idx]);
return;
default:
@@ -387,6 +394,13 @@ _mesa_fetch_state(struct gl_context *ctx, const
gl_state_index state[],
COPY_4V(value, ctx-VertexProgram.Parameters[idx]);
return;
case STATE_LOCAL:
+ if (!ctx-VertexProgram.Current-Base.LocalParams) {
+ ctx-VertexProgram.Current-Base.LocalParams =
+ calloc(MAX_PROGRAM_LOCAL_PARAMS, sizeof(float[4]));
+ if (!ctx-VertexProgram.Current-Base.LocalParams)
+ return;
+ }
+
COPY_4V(value,
ctx-VertexProgram.Current-Base.LocalParams[idx]);
return;
default:
diff --git a/src/mesa/program/program_parse.y b/src/mesa/program/program_parse.y
index 03c0a3d..a76db4e 100644
--- a/src/mesa/program/program_parse.y
+++ b/src/mesa/program/program_parse.y
@@ -25,7 +25,6 @@
#include stdlib.h
#include string.h
-#include main/macros.h
#include main/mtypes.h
#include main/imports.h
#include program/program.h
@@ -2560,12 +2559,6 @@ initialize_symbol_from_param(struct gl_program *prog,
param_var-type = at_param;
param_var-param_binding_type = PROGRAM_STATE_VAR;
- /* Dynamically allocate LocalParams, since it's a large array to have
-* statically in every gl_program otherwise.
-*/
- if (state_tokens[1] == STATE_LOCAL !prog-LocalParams)
- prog-LocalParams = calloc(MAX_PROGRAM_LOCAL_PARAMS, sizeof(float[4]));
-
/* If we are adding a STATE_ENV or STATE_LOCAL that has multiple elements,
* we need to unroll it and call add_state_reference() for each row
*/
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Mesa (master): glsl: Apply the transformation 1/rsq(x) == sqrt(x) in opt_algebraic.
Module: Mesa
Branch: master
Commit: aa6d7bc6d601c8803b136f427b8d86aa1043450c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aa6d7bc6d601c8803b136f427b8d86aa1043450c
Author: Eric Anholt e...@anholt.net
Date: Thu Nov 7 12:15:13 2013 -0800
glsl: Apply the transformation 1/rsq(x) == sqrt(x) in opt_algebraic.
The comment was stale, because the lowering in question wasn't happening
in lower_instructions.cpp. Presumably if the lowering ever moves there,
we can plumb the lowering mask through to opt_algebraic.
total instructions in shared programs: 1618696 - 1616810 (-0.12%)
instructions in affected programs: 243018 - 241132 (-0.78%)
GAINED:0
LOST: 0
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
src/glsl/opt_algebraic.cpp |7 ---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/glsl/opt_algebraic.cpp b/src/glsl/opt_algebraic.cpp
index 448f27e..05a5899 100644
--- a/src/glsl/opt_algebraic.cpp
+++ b/src/glsl/opt_algebraic.cpp
@@ -420,10 +420,11 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir)
if (op_expr[0] op_expr[0]-operation == ir_unop_rcp)
return op_expr[0]-operands[0];
- /* FINISHME: We should do rcp(rsq(x)) - sqrt(x) for some
- * backends, except that some backends will have done sqrt -
- * rcp(rsq(x)) and we don't want to undo it for them.
+ /* While ir_to_mesa.cpp will lower sqrt(x) to rcp(rsq(x)), it does so at
+ * its IR level, so we can always apply this transformation.
*/
+ if (op_expr[0] op_expr[0]-operation == ir_unop_rsq)
+ return sqrt(op_expr[0]-operands[0]);
/* As far as we know, all backends are OK with rsq. */
if (op_expr[0] op_expr[0]-operation == ir_unop_sqrt) {
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Mesa (master): glsl: Apply the transformation (a a) - a in opt_algebraic.
Module: Mesa
Branch: master
Commit: 58a98d32e451762934ca8c38135357f36e29654f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=58a98d32e451762934ca8c38135357f36e29654f
Author: Eric Anholt e...@anholt.net
Date: Thu Oct 31 09:32:42 2013 -0700
glsl: Apply the transformation (a a) - a in opt_algebraic.
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
src/glsl/opt_algebraic.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/src/glsl/opt_algebraic.cpp b/src/glsl/opt_algebraic.cpp
index 3da27e5..ea3c386 100644
--- a/src/glsl/opt_algebraic.cpp
+++ b/src/glsl/opt_algebraic.cpp
@@ -357,7 +357,6 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir)
break;
case ir_binop_logic_and:
- /* FINISHME: Also simplify (a a) to (a). */
if (is_vec_one(op_const[0])) {
return ir-operands[1];
} else if (is_vec_one(op_const[1])) {
@@ -371,6 +370,9 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir)
*/
return logic_not(logic_or(op_expr[0]-operands[0],
op_expr[1]-operands[0]));
+ } else if (ir-operands[0]-equals(ir-operands[1])) {
+ /* (a a) == a */
+ return ir-operands[0];
}
break;
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Mesa (master): glsl: Apply the transformation (a ^^ a) - false in opt_algebraic.
Module: Mesa
Branch: master
Commit: 477f8cd08bb8467d28fdfd6c25fe358957e3da58
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=477f8cd08bb8467d28fdfd6c25fe358957e3da58
Author: Eric Anholt e...@anholt.net
Date: Thu Nov 7 12:10:25 2013 -0800
glsl: Apply the transformation (a ^^ a) - false in opt_algebraic.
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
src/glsl/opt_algebraic.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/src/glsl/opt_algebraic.cpp b/src/glsl/opt_algebraic.cpp
index ea3c386..448f27e 100644
--- a/src/glsl/opt_algebraic.cpp
+++ b/src/glsl/opt_algebraic.cpp
@@ -377,7 +377,6 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir)
break;
case ir_binop_logic_xor:
- /* FINISHME: Also simplify (a ^^ a) to (false). */
if (is_vec_zero(op_const[0])) {
return ir-operands[1];
} else if (is_vec_zero(op_const[1])) {
@@ -386,6 +385,9 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir)
return logic_not(ir-operands[1]);
} else if (is_vec_one(op_const[1])) {
return logic_not(ir-operands[0]);
+ } else if (ir-operands[0]-equals(ir-operands[1])) {
+ /* (a ^^ a) == false */
+return ir_constant::zero(mem_ctx, ir-type);
}
break;
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Mesa (master): glsl: Move the CSE equality functions to the ir class.
Module: Mesa
Branch: master
Commit: 8957c6b887ff09f44e7b491e7a0551e94a265b8d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8957c6b887ff09f44e7b491e7a0551e94a265b8d
Author: Eric Anholt e...@anholt.net
Date: Wed Oct 30 23:56:18 2013 -0700
glsl: Move the CSE equality functions to the ir class.
I want to reuse them in opt_algebraic.
v2: Merge in Chris Forbes's break fix.
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
src/glsl/Makefile.sources |1 +
src/glsl/ir.h | 22 +
src/glsl/ir_equals.cpp| 198 +
src/glsl/opt_cse.cpp | 180 +
4 files changed, 222 insertions(+), 179 deletions(-)
diff --git a/src/glsl/Makefile.sources b/src/glsl/Makefile.sources
index 744b0ad..2e81ded 100644
--- a/src/glsl/Makefile.sources
+++ b/src/glsl/Makefile.sources
@@ -33,6 +33,7 @@ LIBGLSL_FILES = \
$(GLSL_SRCDIR)/ir_clone.cpp \
$(GLSL_SRCDIR)/ir_constant_expression.cpp \
$(GLSL_SRCDIR)/ir.cpp \
+ $(GLSL_SRCDIR)/ir_equals.cpp \
$(GLSL_SRCDIR)/ir_expression_flattening.cpp \
$(GLSL_SRCDIR)/ir_function_can_inline.cpp \
$(GLSL_SRCDIR)/ir_function_detect_recursion.cpp \
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index 2f06fb9..7859702 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -139,6 +139,16 @@ public:
virtual class ir_jump * as_jump() { return NULL; }
/*@}*/
+ /**
+* IR equality method: Return true if the referenced instruction would
+* return the same value as this one.
+*
+* This intended to be used for CSE and algebraic optimizations, on rvalues
+* in particular. No support for other instruction types (assignments,
+* jumps, calls, etc.) is planned.
+*/
+ virtual bool equals(ir_instruction *ir);
+
protected:
ir_instruction()
{
@@ -1405,6 +1415,8 @@ public:
return this;
}
+ virtual bool equals(ir_instruction *ir);
+
virtual ir_expression *clone(void *mem_ctx, struct hash_table *ht) const;
/**
@@ -1739,6 +1751,8 @@ public:
virtual ir_visitor_status accept(ir_hierarchical_visitor *);
+ virtual bool equals(ir_instruction *ir);
+
/**
* Return a string representing the ir_texture_opcode.
*/
@@ -1843,6 +1857,8 @@ public:
virtual ir_visitor_status accept(ir_hierarchical_visitor *);
+ virtual bool equals(ir_instruction *ir);
+
bool is_lvalue() const
{
return val-is_lvalue() !mask.has_duplicates;
@@ -1907,6 +1923,8 @@ public:
return this;
}
+ virtual bool equals(ir_instruction *ir);
+
/**
* Get the variable that is ultimately referenced by an r-value
*/
@@ -1965,6 +1983,8 @@ public:
return this;
}
+ virtual bool equals(ir_instruction *ir);
+
/**
* Get the variable that is ultimately referenced by an r-value
*/
@@ -2099,6 +2119,8 @@ public:
virtual ir_visitor_status accept(ir_hierarchical_visitor *);
+ virtual bool equals(ir_instruction *ir);
+
/**
* Get a particular component of a constant as a specific type
*
diff --git a/src/glsl/ir_equals.cpp b/src/glsl/ir_equals.cpp
new file mode 100644
index 000..7cfe1e6
--- /dev/null
+++ b/src/glsl/ir_equals.cpp
@@ -0,0 +1,198 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#include ir.h
+
+/**
+ * Helper for checking equality when one instruction might be NULL, since you
+ * can't access a's vtable in that case.
+ */
+static bool
+possibly_null_equals(ir_instruction *a, ir_instruction *b)
+{
+ if (!a || !b)
+ return !a !b;
+
+ return a-equals(b);
+}
+
+/**
+ * The base equality function: Return not equal for anything we don't know
+ * about.
+ */
+bool
+ir_instruction::equals(ir_instruction *ir)
+{
+ return false;
+}
+
+bool
+ir_constant
Mesa (master): glsl: Apply the transformation (a || a) - a in opt_algebraic.
Module: Mesa
Branch: master
Commit: ee2704826264eba22d095c3e1e03a8532b7bd1e6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee2704826264eba22d095c3e1e03a8532b7bd1e6
Author: Eric Anholt e...@anholt.net
Date: Thu Oct 31 00:10:32 2013 -0700
glsl: Apply the transformation (a || a) - a in opt_algebraic.
total instructions in shared programs: 1732385 - 1732373 (-0.00%)
instructions in affected programs: 416 - 404 (-2.88%)
GAINED:0
LOST: 0
(That's 4 already-short fragment shaders in dota2)
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
src/glsl/opt_algebraic.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/src/glsl/opt_algebraic.cpp b/src/glsl/opt_algebraic.cpp
index a07e153..3da27e5 100644
--- a/src/glsl/opt_algebraic.cpp
+++ b/src/glsl/opt_algebraic.cpp
@@ -388,7 +388,6 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir)
break;
case ir_binop_logic_or:
- /* FINISHME: Also simplify (a || a) to (a). */
if (is_vec_zero(op_const[0])) {
return ir-operands[1];
} else if (is_vec_zero(op_const[1])) {
@@ -407,6 +406,9 @@ ir_algebraic_visitor::handle_expression(ir_expression *ir)
*/
return logic_not(logic_and(op_expr[0]-operands[0],
op_expr[1]-operands[0]));
+ } else if (ir-operands[0]-equals(ir-operands[1])) {
+ /* (a || a) == a */
+ return ir-operands[0];
}
break;
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Mesa (master): mesa: Dynamically allocate the storage for program local parameters.
Module: Mesa
Branch: master
Commit: e5885c119de1e508099cce1c9f8ff00fab88
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e5885c119de1e508099cce1c9f8ff00fab88
Author: Eric Anholt e...@anholt.net
Date: Fri Sep 20 10:13:32 2013 -0700
mesa: Dynamically allocate the storage for program local parameters.
The array was 64kb per struct gl_program, plus we statically stored a copy
of one on disk for _mesa_DummyProgram. Given that most struct gl_programs
we generate are for GLSL shaders that don't have local parameters, this
was a waste.
Since you can store and fetch parameters beyond what the program actually
uses, we do have to do a late allocation if necessary at
GetProgramLocalParameter time.
Reduces peak memory usage in the dota2 trace I made by 76MB (4.5%)
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/main/arbprogram.c |6 ++
src/mesa/main/mtypes.h | 11 +--
src/mesa/program/program.c | 12 +++-
src/mesa/program/program_parse.y |7 +++
4 files changed, 33 insertions(+), 3 deletions(-)
diff --git a/src/mesa/main/arbprogram.c b/src/mesa/main/arbprogram.c
index 51a2993..8bd3f0b 100644
--- a/src/mesa/main/arbprogram.c
+++ b/src/mesa/main/arbprogram.c
@@ -265,6 +265,12 @@ get_local_param_pointer(struct gl_context *ctx, const char
*func,
return GL_FALSE;
}
+ if (!prog-LocalParams) {
+ prog-LocalParams = calloc(maxParams, sizeof(float[4]));
+ if (!prog-LocalParams)
+ return GL_FALSE;
+ }
+
*param = prog-LocalParams[index];
return GL_TRUE;
}
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 0f470da..67c4996 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2035,8 +2035,15 @@ struct gl_program
/** Named parameters, constants, etc. from program text */
struct gl_program_parameter_list *Parameters;
- /** Numbered local parameters */
- GLfloat LocalParams[MAX_PROGRAM_LOCAL_PARAMS][4];
+
+ /**
+* Local parameters used by the program.
+*
+* It's dynamically allocated because it is rarely used (just
+* assembly-style programs), and MAX_PROGRAM_LOCAL_PARAMS entries once it's
+* allocated.
+*/
+ GLfloat (*LocalParams)[4];
/** Map from sampler unit to texture unit (set by glUniform1i()) */
GLubyte SamplerUnits[MAX_SAMPLERS];
diff --git a/src/mesa/program/program.c b/src/mesa/program/program.c
index b7b5140..01f8c6f 100644
--- a/src/mesa/program/program.c
+++ b/src/mesa/program/program.c
@@ -349,6 +349,7 @@ _mesa_delete_program(struct gl_context *ctx, struct
gl_program *prog)
return;
free(prog-String);
+ free(prog-LocalParams);
if (prog-Instructions) {
_mesa_free_instructions(prog-Instructions, prog-NumInstructions);
@@ -477,7 +478,16 @@ _mesa_clone_program(struct gl_context *ctx, const struct
gl_program *prog)
if (prog-Parameters)
clone-Parameters = _mesa_clone_parameter_list(prog-Parameters);
- memcpy(clone-LocalParams, prog-LocalParams, sizeof(clone-LocalParams));
+ if (prog-LocalParams) {
+ clone-LocalParams = malloc(MAX_PROGRAM_LOCAL_PARAMS *
+ sizeof(float[4]));
+ if (!clone-LocalParams) {
+ _mesa_reference_program(ctx, clone, NULL);
+ return NULL;
+ }
+ memcpy(clone-LocalParams, prog-LocalParams,
+ MAX_PROGRAM_LOCAL_PARAMS * sizeof(float[4]));
+ }
clone-IndirectRegisterFiles = prog-IndirectRegisterFiles;
clone-NumInstructions = prog-NumInstructions;
clone-NumTemporaries = prog-NumTemporaries;
diff --git a/src/mesa/program/program_parse.y b/src/mesa/program/program_parse.y
index a76db4e..03c0a3d 100644
--- a/src/mesa/program/program_parse.y
+++ b/src/mesa/program/program_parse.y
@@ -25,6 +25,7 @@
#include stdlib.h
#include string.h
+#include main/macros.h
#include main/mtypes.h
#include main/imports.h
#include program/program.h
@@ -2559,6 +2560,12 @@ initialize_symbol_from_param(struct gl_program *prog,
param_var-type = at_param;
param_var-param_binding_type = PROGRAM_STATE_VAR;
+ /* Dynamically allocate LocalParams, since it's a large array to have
+* statically in every gl_program otherwise.
+*/
+ if (state_tokens[1] == STATE_LOCAL !prog-LocalParams)
+ prog-LocalParams = calloc(MAX_PROGRAM_LOCAL_PARAMS, sizeof(float[4]));
+
/* If we are adding a STATE_ENV or STATE_LOCAL that has multiple elements,
* we need to unroll it and call add_state_reference() for each row
*/
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Mesa (master): mesa: Update a comment about valid values of a field.
Module: Mesa
Branch: master
Commit: fddc17ab365370f9afb6b44fb3e2bbf68d450968
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fddc17ab365370f9afb6b44fb3e2bbf68d450968
Author: Eric Anholt e...@anholt.net
Date: Wed Nov 13 13:36:30 2013 -0800
mesa: Update a comment about valid values of a field.
Notably, ENV and LOCAL aren't used any more (replaced by STATE_VAR), but
apparently CONSTANT is.
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/program/program_parser.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/mesa/program/program_parser.h
b/src/mesa/program/program_parser.h
index ca36bb6..04c64f4 100644
--- a/src/mesa/program/program_parser.h
+++ b/src/mesa/program/program_parser.h
@@ -44,7 +44,7 @@ struct asm_symbol {
unsigned output_binding; /** Output / result register number. */
/**
-* One of PROGRAM_STATE_VAR, PROGRAM_LOCAL_PARAM, or PROGRAM_ENV_PARAM.
+* One of PROGRAM_STATE_VAR or PROGRAM_CONSTANT.
*/
unsigned param_binding_type;
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Mesa (master): mesa: Remove PROGRAM_ENV_PARAM enum.
Module: Mesa
Branch: master
Commit: bb1f0969756fbb827c4b2520c632daa15342b064
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb1f0969756fbb827c4b2520c632daa15342b064
Author: Eric Anholt e...@anholt.net
Date: Wed Nov 13 13:41:28 2013 -0800
mesa: Remove PROGRAM_ENV_PARAM enum.
This has been replaced with referring to env parameters using
PROGRAM_STATE_VAR and _mesa_load_state_parameters.
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i915/i915_fragprog.c |8
src/mesa/drivers/dri/r200/r200_vertprog.c |1 -
src/mesa/main/mtypes.h |8 +++-
src/mesa/program/prog_execute.c|5 -
src/mesa/program/prog_print.c |5 -
src/mesa/program/program.c |3 ---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp |7 +--
src/mesa/state_tracker/st_mesa_to_tgsi.c |5 +
8 files changed, 5 insertions(+), 37 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c
b/src/mesa/drivers/dri/i915/i915_fragprog.c
index fcdca75..dff4b9f 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -160,14 +160,6 @@ src_vector(struct i915_fragment_program *p,
/* Various paramters and env values. All emitted to
* hardware as program constants.
*/
-
- case PROGRAM_ENV_PARAM:
- src =
- i915_emit_param4fv(p,
-p-ctx-FragmentProgram.Parameters[source-
- Index]);
- break;
-
case PROGRAM_CONSTANT:
case PROGRAM_STATE_VAR:
case PROGRAM_UNIFORM:
diff --git a/src/mesa/drivers/dri/r200/r200_vertprog.c
b/src/mesa/drivers/dri/r200/r200_vertprog.c
index 5f15a57..2397473 100644
--- a/src/mesa/drivers/dri/r200/r200_vertprog.c
+++ b/src/mesa/drivers/dri/r200/r200_vertprog.c
@@ -210,7 +210,6 @@ static unsigned long t_src_class(gl_register_file file)
case PROGRAM_INPUT:
return VSF_IN_CLASS_ATTR;
- case PROGRAM_ENV_PARAM:
case PROGRAM_CONSTANT:
case PROGRAM_STATE_VAR:
return VSF_IN_CLASS_PARAM;
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 82c915f..0f470da 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -1930,10 +1930,9 @@ struct gl_perf_monitor_state
* NOTE: first four tokens must fit into 2 bits (see t_vb_arbprogram.c)
* All values should fit in a 4-bit field.
*
- * NOTE: PROGRAM_ENV_PARAM, PROGRAM_STATE_VAR,
- * PROGRAM_CONSTANT, and PROGRAM_UNIFORM can all be considered to
- * be uniform variables since they can only be set outside glBegin/End.
- * They're also all stored in the same Parameters array.
+ * NOTE: PROGRAM_STATE_VAR, PROGRAM_CONSTANT, and PROGRAM_UNIFORM can all be
+ * considered to be uniform variables since they can only be set outside
+ * glBegin/End. They're also all stored in the same Parameters array.
*/
typedef enum
{
@@ -1941,7 +1940,6 @@ typedef enum
PROGRAM_ARRAY, /** Arrays Matrixes */
PROGRAM_INPUT, /** machine-Inputs[] */
PROGRAM_OUTPUT, /** machine-Outputs[] */
- PROGRAM_ENV_PARAM, /** gl_program-Parameters[] */
PROGRAM_STATE_VAR, /** gl_program-Parameters[] */
PROGRAM_CONSTANT,/** gl_program-Parameters[] */
PROGRAM_UNIFORM, /** gl_program-Parameters[] */
diff --git a/src/mesa/program/prog_execute.c b/src/mesa/program/prog_execute.c
index 4a64147..115525e 100644
--- a/src/mesa/program/prog_execute.c
+++ b/src/mesa/program/prog_execute.c
@@ -118,11 +118,6 @@ get_src_register_pointer(const struct prog_src_register
*source,
return ZeroVec;
return machine-Outputs[reg];
- case PROGRAM_ENV_PARAM:
- if (reg = MAX_PROGRAM_ENV_PARAMS)
- return ZeroVec;
- return machine-EnvParams[reg];
-
case PROGRAM_STATE_VAR:
/* Fallthrough */
case PROGRAM_CONSTANT:
diff --git a/src/mesa/program/prog_print.c b/src/mesa/program/prog_print.c
index e503cb6..fa120cc 100644
--- a/src/mesa/program/prog_print.c
+++ b/src/mesa/program/prog_print.c
@@ -50,8 +50,6 @@ _mesa_register_file_name(gl_register_file f)
switch (f) {
case PROGRAM_TEMPORARY:
return TEMP;
- case PROGRAM_ENV_PARAM:
- return ENV;
case PROGRAM_STATE_VAR:
return STATE;
case PROGRAM_INPUT:
@@ -380,9 +378,6 @@ reg_string(gl_register_file f, GLint index,
gl_prog_print_mode mode,
case PROGRAM_TEMPORARY:
sprintf(str, temp%d, index);
break;
- case PROGRAM_ENV_PARAM:
- sprintf(str, program.env[%s%d], addr, index);
- break;
case PROGRAM_CONSTANT: /* extension */
sprintf(str, constant[%s%d], addr, index);
break;
diff --git a/src/mesa/program/program.c b/src/mesa/program/program.c
index e8bb7d7..b7b5140 100644
--- a/src/mesa/program/program.c
+++ b/src/mesa/program/program.c
@@ -909,9 +909,6
Mesa (master): mesa: Remove PROGRAM_LOCAL_PARAM enum.
Module: Mesa
Branch: master
Commit: 33b0455211019988fe418cca5dfac62c7902c861
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=33b0455211019988fe418cca5dfac62c7902c861
Author: Eric Anholt e...@anholt.net
Date: Wed Nov 13 13:38:37 2013 -0800
mesa: Remove PROGRAM_LOCAL_PARAM enum.
This has been replaced with referring to local parameters using
PROGRAM_STATE_VAR and _mesa_load_state_parameters.
Reviewed-by: Brian Paul bri...@vmware.com
Reviewed-by: Ian Romanick ian.d.roman...@intel.com
---
src/mesa/drivers/dri/i915/i915_fragprog.c |3 ---
src/mesa/drivers/dri/r200/r200_vertprog.c |1 -
src/mesa/main/mtypes.h |1 -
src/mesa/program/prog_execute.c|5 -
src/mesa/program/prog_print.c |5 -
src/mesa/program/program.c |3 ---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp |7 +--
src/mesa/state_tracker/st_mesa_to_tgsi.c |5 +
8 files changed, 2 insertions(+), 28 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c
b/src/mesa/drivers/dri/i915/i915_fragprog.c
index 67eff76..fcdca75 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -160,9 +160,6 @@ src_vector(struct i915_fragment_program *p,
/* Various paramters and env values. All emitted to
* hardware as program constants.
*/
- case PROGRAM_LOCAL_PARAM:
- src = i915_emit_param4fv(p, program-Base.LocalParams[source-Index]);
- break;
case PROGRAM_ENV_PARAM:
src =
diff --git a/src/mesa/drivers/dri/r200/r200_vertprog.c
b/src/mesa/drivers/dri/r200/r200_vertprog.c
index 461b7cb..5f15a57 100644
--- a/src/mesa/drivers/dri/r200/r200_vertprog.c
+++ b/src/mesa/drivers/dri/r200/r200_vertprog.c
@@ -210,7 +210,6 @@ static unsigned long t_src_class(gl_register_file file)
case PROGRAM_INPUT:
return VSF_IN_CLASS_ATTR;
- case PROGRAM_LOCAL_PARAM:
case PROGRAM_ENV_PARAM:
case PROGRAM_CONSTANT:
case PROGRAM_STATE_VAR:
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 41ffdb7..82c915f 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -1941,7 +1941,6 @@ typedef enum
PROGRAM_ARRAY, /** Arrays Matrixes */
PROGRAM_INPUT, /** machine-Inputs[] */
PROGRAM_OUTPUT, /** machine-Outputs[] */
- PROGRAM_LOCAL_PARAM, /** gl_program-LocalParams[] */
PROGRAM_ENV_PARAM, /** gl_program-Parameters[] */
PROGRAM_STATE_VAR, /** gl_program-Parameters[] */
PROGRAM_CONSTANT,/** gl_program-Parameters[] */
diff --git a/src/mesa/program/prog_execute.c b/src/mesa/program/prog_execute.c
index 560332a..4a64147 100644
--- a/src/mesa/program/prog_execute.c
+++ b/src/mesa/program/prog_execute.c
@@ -118,11 +118,6 @@ get_src_register_pointer(const struct prog_src_register
*source,
return ZeroVec;
return machine-Outputs[reg];
- case PROGRAM_LOCAL_PARAM:
- if (reg = MAX_PROGRAM_LOCAL_PARAMS)
- return ZeroVec;
- return machine-CurProgram-LocalParams[reg];
-
case PROGRAM_ENV_PARAM:
if (reg = MAX_PROGRAM_ENV_PARAMS)
return ZeroVec;
diff --git a/src/mesa/program/prog_print.c b/src/mesa/program/prog_print.c
index fa9063f..e503cb6 100644
--- a/src/mesa/program/prog_print.c
+++ b/src/mesa/program/prog_print.c
@@ -50,8 +50,6 @@ _mesa_register_file_name(gl_register_file f)
switch (f) {
case PROGRAM_TEMPORARY:
return TEMP;
- case PROGRAM_LOCAL_PARAM:
- return LOCAL;
case PROGRAM_ENV_PARAM:
return ENV;
case PROGRAM_STATE_VAR:
@@ -385,9 +383,6 @@ reg_string(gl_register_file f, GLint index,
gl_prog_print_mode mode,
case PROGRAM_ENV_PARAM:
sprintf(str, program.env[%s%d], addr, index);
break;
- case PROGRAM_LOCAL_PARAM:
- sprintf(str, program.local[%s%d], addr, index);
- break;
case PROGRAM_CONSTANT: /* extension */
sprintf(str, constant[%s%d], addr, index);
break;
diff --git a/src/mesa/program/program.c b/src/mesa/program/program.c
index a102ec1..e8bb7d7 100644
--- a/src/mesa/program/program.c
+++ b/src/mesa/program/program.c
@@ -912,9 +912,6 @@ _mesa_valid_register_index(const struct gl_context *ctx,
case PROGRAM_ENV_PARAM:
return index = 0 index (GLint) c-MaxEnvParams;
- case PROGRAM_LOCAL_PARAM:
- return index = 0 index (GLint) c-MaxLocalParams;
-
case PROGRAM_UNIFORM:
case PROGRAM_STATE_VAR:
/* aka constant buffer */
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 0eaf746..78baf89 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -70,8 +70,7 @@ extern C {
}
#define PROGRAM_IMMEDIATE PROGRAM_FILE_MAX
-#define PROGRAM_ANY_CONST ((1 PROGRAM_LOCAL_PARAM) | \
- (1 PROGRAM_ENV_PARAM) |\
+#define PROGRAM_ANY_CONST ((1
Mesa (master): i965/fs: Do instruction pre-scheduling just before register allocation.
Module: Mesa
Branch: master
Commit: fbd8303a943d0d491b7c2415eb237a0731c7dec5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fbd8303a943d0d491b7c2415eb237a0731c7dec5
Author: Eric Anholt e...@anholt.net
Date: Wed Nov 6 17:43:25 2013 -0800
i965/fs: Do instruction pre-scheduling just before register allocation.
Long ago, the HW_REG usage in assign_curb/urb_setup() were scheduling
barriers, so we had to run scheduler before them in order for it to be
able to do basically anything. Now that that's fixed, we can delay the
scheduling until we go to allocate (which will make the next change less
scary).
Cc: 10.0 mesa-sta...@lists.freedesktop.org
Reviewed-by: Matt Turner matts...@gmail.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index ee7b07d..afa82c9 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -3281,13 +3281,13 @@ fs_visitor::run()
progress = compute_to_mrf() || progress;
} while (progress);
- schedule_instructions(false);
-
lower_uniform_pull_constant_loads();
assign_curb_setup();
assign_urb_setup();
+ schedule_instructions(false);
+
if (0)
assign_regs_trivial();
else {
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Mesa (master): i965: Add a warning if something ever hits a bug I noticed.
Module: Mesa
Branch: master
Commit: 8bd45a7e7ed8be3f5bb13689d249fc886cf73067
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8bd45a7e7ed8be3f5bb13689d249fc886cf73067
Author: Eric Anholt e...@anholt.net
Date: Thu Oct 31 10:14:17 2013 -0700
i965: Add a warning if something ever hits a bug I noticed.
We'd have to map the VBO and rewrite things to a lower stride to fix it.
Reviewed-by: Matt Turner matts...@gmail.com
---
src/mesa/drivers/dri/i965/brw_draw_upload.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw_upload.c
b/src/mesa/drivers/dri/i965/brw_draw_upload.c
index e2002e8..57b81df 100644
--- a/src/mesa/drivers/dri/i965/brw_draw_upload.c
+++ b/src/mesa/drivers/dri/i965/brw_draw_upload.c
@@ -609,6 +609,7 @@ static void brw_prepare_vertices(struct brw_context *brw)
static void brw_emit_vertices(struct brw_context *brw)
{
+ struct gl_context *ctx = brw-ctx;
GLuint i, nr_elements;
brw_prepare_vertices(brw);
@@ -680,6 +681,9 @@ static void brw_emit_vertices(struct brw_context *brw)
if (brw-gen == 7)
dw0 |= GEN7_MOCS_L3 16;
+ WARN_ONCE(buffer-stride = (brw-gen = 5 ? 2048 : 2047),
+ VBO stride %d too large, bad rendering may occur\n,
+ buffer-stride);
OUT_BATCH(dw0 | (buffer-stride BRW_VB0_PITCH_SHIFT));
OUT_RELOC(buffer-bo, I915_GEM_DOMAIN_VERTEX, 0, buffer-offset);
if (brw-gen = 5) {
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Mesa (master): i965/fs: Prefer things we know reduce reg pressure when pre-scheduling.
Module: Mesa
Branch: master
Commit: bc0e3bb4d05fbb5e8e2af8dce8170cb78cfe0e70
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bc0e3bb4d05fbb5e8e2af8dce8170cb78cfe0e70
Author: Eric Anholt e...@anholt.net
Date: Mon Oct 14 11:38:09 2013 -0700
i965/fs: Prefer things we know reduce reg pressure when pre-scheduling.
Previously, the best thing we had was to schedule the things unblocked by
the last chosen instruction, on the hope that it would be consuming two
values at the end of their live intervals while only producing one new
value. But that's just a guess, and we can do counting of usage of
registers to know when an instruction would (almost surely) reduce
register pressure.
The only failure mode I know of in this new dominant heuristic is that
inside of a loop when scheduling the iterator (for example), choosing the
last use of the iterator doesn't actually reduce the live interval of the
iterator. But it doesn't seem to matter in shader-db:
total instructions in shared programs: 1618700 - 1618700 (0.00%)
instructions in affected programs: 0 - 0
GAINED:13
LOST: 0
Note: The new functions are made virtual because I expect we'll soon lift
the pre-regalloc scheduling heuristic over to the vec4 backend.
Cc: 10.0 mesa-sta...@lists.freedesktop.org
Reviewed-by: Matt Turner matts...@gmail.com
---
.../drivers/dri/i965/brw_schedule_instructions.cpp | 144
1 files changed, 144 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 5a42513..53fffa7 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -417,6 +417,13 @@ public:
this-instructions_to_schedule = 0;
this-post_reg_alloc = post_reg_alloc;
this-time = 0;
+ if (!post_reg_alloc) {
+ this-remaining_grf_uses = rzalloc_array(mem_ctx, int, grf_count);
+ this-grf_active = rzalloc_array(mem_ctx, bool, grf_count);
+ } else {
+ this-remaining_grf_uses = NULL;
+ this-grf_active = NULL;
+ }
}
~instruction_scheduler()
@@ -442,6 +449,10 @@ public:
*/
virtual int issue_time(backend_instruction *inst) = 0;
+ virtual void count_remaining_grf_uses(backend_instruction *inst) = 0;
+ virtual void update_register_pressure(backend_instruction *inst) = 0;
+ virtual int get_register_pressure_benefit(backend_instruction *inst) = 0;
+
void schedule_instructions(backend_instruction *next_block_header);
void *mem_ctx;
@@ -452,6 +463,22 @@ public:
int time;
exec_list instructions;
backend_visitor *bv;
+
+ /**
+* Number of instructions left to schedule that reference each vgrf.
+*
+* Used so that we can prefer scheduling instructions that will end the
+* live intervals of multiple variables, to reduce register pressure.
+*/
+ int *remaining_grf_uses;
+
+ /**
+* Tracks whether each VGRF has had an instruction scheduled that uses it.
+*
+* This is used to estimate whether scheduling a new instruction will
+* increase register pressure.
+*/
+ bool *grf_active;
};
class fs_instruction_scheduler : public instruction_scheduler
@@ -463,6 +490,10 @@ public:
schedule_node *choose_instruction_to_schedule();
int issue_time(backend_instruction *inst);
fs_visitor *v;
+
+ void count_remaining_grf_uses(backend_instruction *inst);
+ void update_register_pressure(backend_instruction *inst);
+ int get_register_pressure_benefit(backend_instruction *inst);
};
fs_instruction_scheduler::fs_instruction_scheduler(fs_visitor *v,
@@ -473,6 +504,72 @@
fs_instruction_scheduler::fs_instruction_scheduler(fs_visitor *v,
{
}
+void
+fs_instruction_scheduler::count_remaining_grf_uses(backend_instruction *be)
+{
+ fs_inst *inst = (fs_inst *)be;
+
+ if (!remaining_grf_uses)
+ return;
+
+ if (inst-dst.file == GRF)
+ remaining_grf_uses[inst-dst.reg]++;
+
+ for (int i = 0; i 3; i++) {
+ if (inst-src[i].file != GRF)
+ continue;
+
+ remaining_grf_uses[inst-src[i].reg]++;
+ }
+}
+
+void
+fs_instruction_scheduler::update_register_pressure(backend_instruction *be)
+{
+ fs_inst *inst = (fs_inst *)be;
+
+ if (!remaining_grf_uses)
+ return;
+
+ if (inst-dst.file == GRF) {
+ remaining_grf_uses[inst-dst.reg]--;
+ grf_active[inst-dst.reg] = true;
+ }
+
+ for (int i = 0; i 3; i++) {
+ if (inst-src[i].file == GRF) {
+ remaining_grf_uses[inst-src[i].reg]--;
+ grf_active[inst-src[i].reg] = true;
+ }
+ }
+}
+
+int
+fs_instruction_scheduler::get_register_pressure_benefit(backend_instruction
*be)
+{
+ fs_inst *inst = (fs_inst *)be;
+ int benefit = 0;
+
+ if (inst-dst.file == GRF) {
+ if (remaining_grf_uses[inst-dst.reg] == 1)
+ benefit += v
Mesa (master): i965/fs: Fix message setup for SIMD8 spills.
Module: Mesa Branch: master Commit: 7c90947a0ba7f61b58a6fd5b94a08587e68d978e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=7c90947a0ba7f61b58a6fd5b94a08587e68d978e Author: Eric Anholt e...@anholt.net Date: Mon Nov 4 22:56:33 2013 -0800 i965/fs: Fix message setup for SIMD8 spills. In the SIMD16 spilling changes, I replaced a 1 in the spill path with mlen, but obviously it wasn't mlen before because spills have the g0 header along with the payload. The interface I was trying to use was asking for how many physical regs we're writing, so we're looking for 1 or 2. I'm guessing this actually passed piglit because the high 8 bits of the execution mask in SIMD8 mode are all 0s. Cc: 10.0 mesa-sta...@lists.freedesktop.org Reviewed-by: Paul Berry stereotype...@gmail.com --- src/mesa/drivers/dri/i965/brw_fs_generator.cpp |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 6678553..cc58ff2 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -757,7 +757,7 @@ fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src) retype(brw_message_reg(inst-base_mrf + 1), BRW_REGISTER_TYPE_UD), retype(src, BRW_REGISTER_TYPE_UD)); brw_oword_block_write_scratch(p, brw_message_reg(inst-base_mrf), - inst-mlen, inst-offset); + dispatch_width / 8, inst-offset); } void ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/fs: Try a different pre-scheduling heuristic if the first spills.
Module: Mesa
Branch: master
Commit: e9daead784921e453906853a4a78a2f3135af2e0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9daead784921e453906853a4a78a2f3135af2e0
Author: Eric Anholt e...@anholt.net
Date: Wed Nov 6 17:38:23 2013 -0800
i965/fs: Try a different pre-scheduling heuristic if the first spills.
Since LIFO fails on some shaders in one particular way, and non-LIFO
systematically fails in another way on different kinds of shaders, try
them both, and pick whichever one successfully register allocates first.
Slightly prefer non-LIFO in case we produce extra dependencies in register
allocation, since it should start out with fewer stalls than LIFO.
This is madness, but I haven't come up with another way to get unigine
tropics to not spill while keeping other programs from not spilling and
retaining the non-unigine performance wins from texture-grf.
total instructions in shared programs: 1626728 - 1626288 (-0.03%)
instructions in affected programs: 1015 - 575 (-43.35%)
GAINED:50
LOST: 0
Improves Unigine Tropics performance by 14.5257% +/- 0.241838% (n=38)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70445
Cc: 10.0 mesa-sta...@lists.freedesktop.org
Reviewed-by: Matt Turner matts...@gmail.com
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 25 +--
src/mesa/drivers/dri/i965/brw_fs.h |4 +-
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 10 +--
.../drivers/dri/i965/brw_schedule_instructions.cpp | 85 +++-
src/mesa/drivers/dri/i965/brw_shader.h |6 ++
5 files changed, 76 insertions(+), 54 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index afa82c9..f89390c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -3286,15 +3286,28 @@ fs_visitor::run()
assign_curb_setup();
assign_urb_setup();
- schedule_instructions(false);
+ schedule_instructions(SCHEDULE_PRE_NON_LIFO);
if (0)
assign_regs_trivial();
else {
-while (!assign_regs()) {
- if (failed)
- break;
-}
+ if (!assign_regs(false)) {
+/* Try a non-spilling register allocation again with a different
+ * scheduling heuristic.
+ */
+schedule_instructions(SCHEDULE_PRE_LIFO);
+if (!assign_regs(false)) {
+ if (dispatch_width == 16) {
+ fail(Failure to register allocate. Reduce number of
+ live scalar values to avoid this.);
+ } else {
+ while (!assign_regs(true)) {
+ if (failed)
+break;
+ }
+ }
+}
+ }
}
}
assert(force_uncompressed_stack == 0);
@@ -3309,7 +3322,7 @@ fs_visitor::run()
if (failed)
return false;
- schedule_instructions(true);
+ schedule_instructions(SCHEDULE_POST);
if (dispatch_width == 8) {
c-prog_data.reg_blocks = brw_register_blocks(grf_used);
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index dcd5b19..529bd3a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -291,7 +291,7 @@ public:
void assign_curb_setup();
void calculate_urb_setup();
void assign_urb_setup();
- bool assign_regs();
+ bool assign_regs(bool allow_spilling);
void assign_regs_trivial();
void get_used_mrfs(bool *mrf_used);
void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
@@ -322,7 +322,7 @@ public:
bool remove_dead_constants();
bool remove_duplicate_mrf_writes();
bool virtual_grf_interferes(int a, int b);
- void schedule_instructions(bool post_reg_alloc);
+ void schedule_instructions(instruction_scheduler_mode mode);
void insert_gen4_send_dependency_workarounds();
void insert_gen4_pre_send_dependency_workarounds(fs_inst *inst);
void insert_gen4_post_send_dependency_workarounds(fs_inst *inst);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index d9e80d0..8567afd 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -417,7 +417,7 @@ fs_visitor::setup_mrf_hack_interference(struct ra_graph *g,
int first_mrf_node)
}
bool
-fs_visitor::assign_regs()
+fs_visitor::assign_regs(bool allow_spilling)
{
/* Most of this allocation was written for a reg_width of 1
* (dispatch_width == 8). In extending to 16-wide, the code was
@@ -496,14 +496,10 @@ fs_visitor::assign_regs()
if (reg == -1) {
fail(no register to spill:\n);
dump_instructions();
- } else if (dispatch_width == 16) {
-fail(Failure
Mesa (master): i965: Fix undefined value usage in ABO setup.
Module: Mesa Branch: master Commit: 9b3e1592c26a183580342282e509d906d78bb6f6 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b3e1592c26a183580342282e509d906d78bb6f6 Author: Eric Anholt e...@anholt.net Date: Tue Nov 5 16:24:58 2013 -0800 i965: Fix undefined value usage in ABO setup. Fixes a compiler warning. Cc: 10.0 mesa-sta...@lists.freedesktop.org Reviewed-by: Matt Turner matts...@gmail.com --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 2088688..662c975 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -890,7 +890,7 @@ brw_upload_abo_surfaces(struct brw_context *brw, struct intel_buffer_object *intel_bo = intel_buffer_object(binding-BufferObject); drm_intel_bo *bo = intel_bufferobj_buffer( - brw, intel_bo, binding-Offset, bo-size - binding-Offset); + brw, intel_bo, binding-Offset, intel_bo-Base.Size - binding-Offset); brw-vtbl.create_raw_surface(brw, bo, binding-Offset, bo-size - binding-Offset, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965/fs: Ignore actual latency pre-reg-alloc.
Module: Mesa
Branch: master
Commit: f72a0d99fed5d6205431a59775484cde3442cceb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f72a0d99fed5d6205431a59775484cde3442cceb
Author: Eric Anholt e...@anholt.net
Date: Tue Nov 5 23:30:33 2013 -0800
i965/fs: Ignore actual latency pre-reg-alloc.
We care about depth-until-program-end, as a proxy for make sure I
schedule those early instructions that open up the other things that can
make progress while keeping register pressure low, not actual latency
(since we're relying on the post-register-alloc scheduling to actually
schedule for the hardware).
total instructions in shared programs: 1609931 - 1609931 (0.00%)
instructions in affected programs: 0 - 0
GAINED:55
LOST: 43
Cc: 10.0 mesa-sta...@lists.freedesktop.org
Reviewed-by: Matt Turner matts...@gmail.com
---
.../drivers/dri/i965/brw_schedule_instructions.cpp | 50 +++
1 files changed, 29 insertions(+), 21 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 53fffa7..5710380 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -56,29 +56,12 @@ using namespace brw;
static bool debug = false;
+class instruction_scheduler;
+
class schedule_node : public exec_node
{
public:
- schedule_node(backend_instruction *inst, const struct brw_context *brw)
- {
- this-inst = inst;
- this-child_array_size = 0;
- this-children = NULL;
- this-child_latency = NULL;
- this-child_count = 0;
- this-parent_count = 0;
- this-unblocked_time = 0;
- this-cand_generation = 0;
-
- /* We can't measure Gen6 timings directly but expect them to be much
- * closer to Gen7 than Gen4.
- */
- if (brw-gen = 6)
- set_latency_gen7(brw-is_haswell);
- else
- set_latency_gen4();
- }
-
+ schedule_node(backend_instruction *inst, instruction_scheduler *sched);
void set_latency_gen4();
void set_latency_gen7(bool is_haswell);
@@ -607,10 +590,35 @@
vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction *b
return 0;
}
+schedule_node::schedule_node(backend_instruction *inst,
+ instruction_scheduler *sched)
+{
+ struct brw_context *brw = sched-bv-brw;
+
+ this-inst = inst;
+ this-child_array_size = 0;
+ this-children = NULL;
+ this-child_latency = NULL;
+ this-child_count = 0;
+ this-parent_count = 0;
+ this-unblocked_time = 0;
+ this-cand_generation = 0;
+
+ /* We can't measure Gen6 timings directly but expect them to be much
+* closer to Gen7 than Gen4.
+*/
+ if (!sched-post_reg_alloc)
+ this-latency = 1;
+ else if (brw-gen = 6)
+ set_latency_gen7(brw-is_haswell);
+ else
+ set_latency_gen4();
+}
+
void
instruction_scheduler::add_inst(backend_instruction *inst)
{
- schedule_node *n = new(mem_ctx) schedule_node(inst, bv-brw);
+ schedule_node *n = new(mem_ctx) schedule_node(inst, this);
assert(!inst-is_head_sentinel());
assert(!inst-is_tail_sentinel());
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Mesa (master): i965: Avoid flushing the batch for every blorp op.
Module: Mesa
Branch: master
Commit: 185b5a54c94ce11487146042c8eec24909187ed6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=185b5a54c94ce11487146042c8eec24909187ed6
Author: Eric Anholt e...@anholt.net
Date: Tue Jun 18 13:52:03 2013 -0700
i965: Avoid flushing the batch for every blorp op.
This brings over the batch-wrap-prevention and aperture space checking
code from the normal brw_draw.c path, so that we don't need to flush the
batch every time.
There's a risk here if the intel_emit_post_sync_nonzero_flush() call isn't
high enough up in the state emit sequences -- before, we implicitly had
one at the batch flush before any state was emitted, so Mesa's workaround
emits didn't really matter. Since the SNB fixes by Ken, I didn't see any
regressions after 3 piglit runs.
Improves cairo-gl performance by 13.7733% +/- 1.74876% (n=30/32)
Improves minecraft apitrace performance by 1.03183% +/- 0.482297% (n=90).
Reduces low-resolution GLB 2.7 performance by 1.17553% +/- 0.432263% (n=88)
Reduces Lightsmark performance by 3.70246% +/- 0.322432% (n=126)
No statistically significant performance difference on unigine tropics
(n=10)
No statistically significant performance difference on openarena (n=755)
The two apps that are hurt happen to include stalls on busy buffer
objects, so I think this is an effect of missing out on an opportune
flush.
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Paul Berry stereotype...@gmail.com
---
src/mesa/drivers/dri/i965/brw_blorp.cpp | 50 ++
src/mesa/drivers/dri/i965/brw_blorp.h|4 --
src/mesa/drivers/dri/i965/gen6_blorp.cpp | 12 ---
src/mesa/drivers/dri/i965/gen7_blorp.cpp |1 -
4 files changed, 50 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp
b/src/mesa/drivers/dri/i965/brw_blorp.cpp
index 91df346..4cbcebe 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.cpp
+++ b/src/mesa/drivers/dri/i965/brw_blorp.cpp
@@ -21,6 +21,7 @@
* IN THE SOFTWARE.
*/
+#include errno.h
#include intel_batchbuffer.h
#include intel_fbo.h
@@ -195,6 +196,26 @@ intel_hiz_exec(struct brw_context *brw, struct
intel_mipmap_tree *mt,
void
brw_blorp_exec(struct brw_context *brw, const brw_blorp_params *params)
{
+ struct gl_context *ctx = brw-ctx;
+ uint32_t estimated_max_batch_usage = 1500;
+ bool check_aperture_failed_once = false;
+
+ /* Flush the sampler and render caches. We definitely need to flush the
+* sampler cache so that we get updated contents from the render cache for
+* the glBlitFramebuffer() source. Also, we are sometimes warned in the
+* docs to flush the cache between reinterpretations of the same surface
+* data with different formats, which blorp does for stencil and depth
+* data.
+*/
+ intel_batchbuffer_emit_mi_flush(brw);
+
+retry:
+ intel_batchbuffer_require_space(brw, estimated_max_batch_usage, false);
+ intel_batchbuffer_save_state(brw);
+ drm_intel_bo *saved_bo = brw-batch.bo;
+ uint32_t saved_used = brw-batch.used;
+ uint32_t saved_state_batch_offset = brw-batch.state_batch_offset;
+
switch (brw-gen) {
case 6:
gen6_blorp_exec(brw, params);
@@ -208,6 +229,35 @@ brw_blorp_exec(struct brw_context *brw, const
brw_blorp_params *params)
break;
}
+ /* Make sure we didn't wrap the batch unintentionally, and make sure we
+* reserved enough space that a wrap will never happen.
+*/
+ assert(brw-batch.bo == saved_bo);
+ assert((brw-batch.used - saved_used) * 4 +
+ (saved_state_batch_offset - brw-batch.state_batch_offset)
+ estimated_max_batch_usage);
+ /* Shut up compiler warnings on release build */
+ (void)saved_bo;
+ (void)saved_used;
+ (void)saved_state_batch_offset;
+
+ /* Check if the blorp op we just did would make our batch likely to fail to
+* map all the BOs into the GPU at batch exec time later. If so, flush the
+* batch and try again with nothing else in the batch.
+*/
+ if (dri_bufmgr_check_aperture_space(brw-batch.bo, 1)) {
+ if (!check_aperture_failed_once) {
+ check_aperture_failed_once = true;
+ intel_batchbuffer_reset_to_saved(brw);
+ intel_batchbuffer_flush(brw);
+ goto retry;
+ } else {
+ int ret = intel_batchbuffer_flush(brw);
+ WARN_ONCE(ret == -ENOSPC,
+ i965: blorp emit exceeded available aperture space\n);
+ }
+ }
+
if (unlikely(brw-always_flush_batch))
intel_batchbuffer_flush(brw);
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.h
b/src/mesa/drivers/dri/i965/brw_blorp.h
index 07ab805..85bf099 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.h
+++ b/src/mesa/drivers/dri/i965/brw_blorp.h
@@ -371,10 +371,6 @@ void
gen6_blorp_init(struct brw_context *brw);
void
-gen6_blorp_emit_batch_head(struct brw_context *brw,
- const brw_blorp_params *params);
-
-void
Mesa (master): drivers/dri/common: A few dri2 functions are not actually DRI2 specific
Module: Mesa
Branch: master
Commit: f66a6c5fe7dad343c73c8d772c6363599dfd6b43
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f66a6c5fe7dad343c73c8d772c6363599dfd6b43
Author: Keith Packard kei...@keithp.com
Date: Mon Jun 3 20:49:25 2013 -0700
drivers/dri/common: A few dri2 functions are not actually DRI2 specific
This just renames them so that they can be used with the DRI3 extension
without causing too much confusion.
Signed-off-by: Keith Packard kei...@keithp.com
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
include/GL/internal/dri_interface.h| 61 +-
src/mesa/drivers/dri/common/dri_util.c | 74
2 files changed, 76 insertions(+), 59 deletions(-)
diff --git a/include/GL/internal/dri_interface.h
b/include/GL/internal/dri_interface.h
index 01233d3..b0fa02f 100644
--- a/include/GL/internal/dri_interface.h
+++ b/include/GL/internal/dri_interface.h
@@ -763,6 +763,40 @@ struct __DRIswrastExtensionRec {
};
+/** Common DRI function definitions, shared among DRI2 and Image extensions
+ */
+
+typedef __DRIscreen *
+(*__DRIcreateNewScreen2Func)(int screen, int fd,
+ const __DRIextension **extensions,
+ const __DRIextension **driver_extensions,
+ const __DRIconfig ***driver_configs,
+ void *loaderPrivate);
+
+typedef __DRIdrawable *
+(*__DRIcreateNewDrawableFunc)(__DRIscreen *screen,
+ const __DRIconfig *config,
+ void *loaderPrivate);
+
+typedef __DRIcontext *
+(*__DRIcreateNewContextFunc)(__DRIscreen *screen,
+ const __DRIconfig *config,
+ __DRIcontext *shared,
+ void *loaderPrivate);
+
+typedef __DRIcontext *
+(*__DRIcreateContextAttribsFunc)(__DRIscreen *screen,
+ int api,
+ const __DRIconfig *config,
+ __DRIcontext *shared,
+ unsigned num_attribs,
+ const uint32_t *attribs,
+ unsigned *error,
+ void *loaderPrivate);
+
+typedef unsigned int
+(*__DRIgetAPIMaskFunc)(__DRIscreen *screen);
+
/**
* DRI2 Loader extension.
*/
@@ -910,17 +944,11 @@ struct __DRIdri2ExtensionRec {
const __DRIconfig ***driver_configs,
void *loaderPrivate);
-__DRIdrawable *(*createNewDrawable)(__DRIscreen *screen,
- const __DRIconfig *config,
- void *loaderPrivate);
-
-__DRIcontext *(*createNewContext)(__DRIscreen *screen,
- const __DRIconfig *config,
- __DRIcontext *shared,
- void *loaderPrivate);
+ __DRIcreateNewDrawableFunc createNewDrawable;
+ __DRIcreateNewContextFunccreateNewContext;
/* Since version 2 */
- unsigned int (*getAPIMask)(__DRIscreen *screen);
+ __DRIgetAPIMaskFunc getAPIMask;
__DRIcontext *(*createNewContextForAPI)(__DRIscreen *screen,
int api,
@@ -943,25 +971,14 @@ struct __DRIdri2ExtensionRec {
*
* \sa __DRIswrastExtensionRec::createContextAttribs
*/
- __DRIcontext *(*createContextAttribs)(__DRIscreen *screen,
-int api,
-const __DRIconfig *config,
-__DRIcontext *shared,
-unsigned num_attribs,
-const uint32_t *attribs,
-unsigned *error,
-void *loaderPrivate);
+ __DRIcreateContextAttribsFunccreateContextAttribs;
/**
* createNewScreen with the driver's extension list passed in.
*
* \since version 4
*/
-__DRIscreen *(*createNewScreen2)(int screen, int fd,
- const __DRIextension **loader_extensions,
- const __DRIextension **driver_extensions,
- const __DRIconfig ***driver_configs,
- void *loaderPrivate);
+ __DRIcreateNewScreen2FunccreateNewScreen2;
};
diff --git a/src/mesa/drivers/dri/common/dri_util.c
b/src/mesa/drivers/dri/common/dri_util.c
index 8eb2de2..a694114 100644
--- a/src/mesa/drivers/dri/common/dri_util.c
+++ b/src/mesa/drivers/dri/common/dri_util.c
@@ -106,10 +106,10 @@ const struct __DriverAPIRec *globalDriverAPI =
driDriverAPI;
* Display.
*/
static
Mesa (master): Define __DRI_IMAGE_FORMAT_SARGB8
Module: Mesa
Branch: master
Commit: aba6b84ce52c27b642d01bafd1703386bda97f3a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aba6b84ce52c27b642d01bafd1703386bda97f3a
Author: Keith Packard kei...@keithp.com
Date: Mon Nov 4 17:27:43 2013 -0800
Define __DRI_IMAGE_FORMAT_SARGB8
This format will be used by the i965 driver
Signed-off-by: Keith Packard kei...@keithp.com
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
include/GL/internal/dri_interface.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/include/GL/internal/dri_interface.h
b/include/GL/internal/dri_interface.h
index b0fa02f..fdd7f94 100644
--- a/include/GL/internal/dri_interface.h
+++ b/include/GL/internal/dri_interface.h
@@ -1013,6 +1013,7 @@ struct __DRIdri2ExtensionRec {
#define __DRI_IMAGE_FORMAT_NONE 0x1008
#define __DRI_IMAGE_FORMAT_XRGB2101010 0x1009
#define __DRI_IMAGE_FORMAT_ARGB2101010 0x100a
+#define __DRI_IMAGE_FORMAT_SARGB8 0x100b
#define __DRI_IMAGE_USE_SHARE 0x0001
#define __DRI_IMAGE_USE_SCANOUT0x0002
___
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Mesa (master): dri/common: Add functions mapping MESA_FORMAT_* - __DRI_IMAGE_FORMAT_*
Module: Mesa
Branch: master
Commit: b7818b8c36f9850acb17402d05593cff6c2532f0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7818b8c36f9850acb17402d05593cff6c2532f0
Author: Keith Packard kei...@keithp.com
Date: Mon Nov 4 17:29:08 2013 -0800
dri/common: Add functions mapping MESA_FORMAT_* - __DRI_IMAGE_FORMAT_*
The __DRI_IMAGE_FORMAT codes are used by the image extension, drivers need to
be able to translate between them. Instead of duplicating this translation in
each driver, create a shared version.
Signed-off-by: Keith Packard kei...@keithp.com
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
src/mesa/drivers/dri/common/dri_util.c | 62
src/mesa/drivers/dri/common/dri_util.h |6 +++
2 files changed, 68 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/common/dri_util.c
b/src/mesa/drivers/dri/common/dri_util.c
index a694114..46a2da4 100644
--- a/src/mesa/drivers/dri/common/dri_util.c
+++ b/src/mesa/drivers/dri/common/dri_util.c
@@ -797,3 +797,65 @@ driUpdateFramebufferSize(struct gl_context *ctx, const
__DRIdrawable *dPriv)
assert(fb-Height == dPriv-h);
}
}
+
+uint32_t
+driGLFormatToImageFormat(gl_format format)
+{
+ switch (format) {
+ case MESA_FORMAT_RGB565:
+ return __DRI_IMAGE_FORMAT_RGB565;
+ case MESA_FORMAT_XRGB:
+ return __DRI_IMAGE_FORMAT_XRGB;
+ case MESA_FORMAT_ARGB2101010:
+ return __DRI_IMAGE_FORMAT_ARGB2101010;
+ case MESA_FORMAT_XRGB2101010_UNORM:
+ return __DRI_IMAGE_FORMAT_XRGB2101010;
+ case MESA_FORMAT_ARGB:
+ return __DRI_IMAGE_FORMAT_ARGB;
+ case MESA_FORMAT_RGBA_REV:
+ return __DRI_IMAGE_FORMAT_ABGR;
+ case MESA_FORMAT_RGBX_REV:
+ return __DRI_IMAGE_FORMAT_XBGR;
+ case MESA_FORMAT_R8:
+ return __DRI_IMAGE_FORMAT_R8;
+ case MESA_FORMAT_GR88:
+ return __DRI_IMAGE_FORMAT_GR88;
+ case MESA_FORMAT_NONE:
+ return __DRI_IMAGE_FORMAT_NONE;
+ case MESA_FORMAT_SARGB8:
+ return __DRI_IMAGE_FORMAT_SARGB8;
+ default:
+ return 0;
+ }
+}
+
+gl_format
+driImageFormatToGLFormat(uint32_t image_format)
+{
+ switch (image_format) {
+ case __DRI_IMAGE_FORMAT_RGB565:
+ return MESA_FORMAT_RGB565;
+ case __DRI_IMAGE_FORMAT_XRGB:
+ return MESA_FORMAT_XRGB;
+ case __DRI_IMAGE_FORMAT_ARGB2101010:
+ return MESA_FORMAT_ARGB2101010;
+ case __DRI_IMAGE_FORMAT_XRGB2101010:
+ return MESA_FORMAT_XRGB2101010_UNORM;
+ case __DRI_IMAGE_FORMAT_ARGB:
+ return MESA_FORMAT_ARGB;
+ case __DRI_IMAGE_FORMAT_ABGR:
+ return MESA_FORMAT_RGBA_REV;
+ case __DRI_IMAGE_FORMAT_XBGR:
+ return MESA_FORMAT_RGBX_REV;
+ case __DRI_IMAGE_FORMAT_R8:
+ return MESA_FORMAT_R8;
+ case __DRI_IMAGE_FORMAT_GR88:
+ return MESA_FORMAT_GR88;
+ case __DRI_IMAGE_FORMAT_SARGB8:
+ return MESA_FORMAT_SARGB8;
+ case __DRI_IMAGE_FORMAT_NONE:
+ return MESA_FORMAT_NONE;
+ default:
+ return MESA_FORMAT_NONE;
+ }
+}
diff --git a/src/mesa/drivers/dri/common/dri_util.h
b/src/mesa/drivers/dri/common/dri_util.h
index b3c2165..7fab3e5 100644
--- a/src/mesa/drivers/dri/common/dri_util.h
+++ b/src/mesa/drivers/dri/common/dri_util.h
@@ -273,6 +273,12 @@ struct __DRIdrawableRec {
} dri2;
};
+extern uint32_t
+driGLFormatToImageFormat(gl_format format);
+
+extern gl_format
+driImageFormatToGLFormat(uint32_t image_format);
+
extern void
dri2InvalidateDrawable(__DRIdrawable *drawable);
___
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Mesa (master): dri/intel: Add explicit size parameter to intel_region_alloc_for_fd
Module: Mesa
Branch: master
Commit: bf6591e948d95b73c5b8d10fa448ec87e9572b8e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bf6591e948d95b73c5b8d10fa448ec87e9572b8e
Author: Keith Packard kei...@keithp.com
Date: Mon Jun 3 20:59:31 2013 -0700
dri/intel: Add explicit size parameter to intel_region_alloc_for_fd
Instead of assuming that the size will be height * pitch, have the caller pass
in the size explicitly.
Signed-off-by: Keith Packard kei...@keithp.com
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
src/mesa/drivers/dri/i915/intel_regions.c |4 ++--
src/mesa/drivers/dri/i915/intel_regions.h |2 +-
src/mesa/drivers/dri/i915/intel_screen.c |4 ++--
src/mesa/drivers/dri/i965/intel_regions.c |4 ++--
src/mesa/drivers/dri/i965/intel_regions.h |1 +
src/mesa/drivers/dri/i965/intel_screen.c |4 ++--
6 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/intel_regions.c
b/src/mesa/drivers/dri/i915/intel_regions.c
index 44f7030..9f5b89e 100644
--- a/src/mesa/drivers/dri/i915/intel_regions.c
+++ b/src/mesa/drivers/dri/i915/intel_regions.c
@@ -209,6 +209,7 @@ struct intel_region *
intel_region_alloc_for_fd(struct intel_screen *screen,
GLuint cpp,
GLuint width, GLuint height, GLuint pitch,
+ GLuint size,
int fd, const char *name)
{
struct intel_region *region;
@@ -216,8 +217,7 @@ intel_region_alloc_for_fd(struct intel_screen *screen,
int ret;
uint32_t bit_6_swizzle, tiling;
- buffer = drm_intel_bo_gem_create_from_prime(screen-bufmgr,
- fd, height * pitch);
+ buffer = drm_intel_bo_gem_create_from_prime(screen-bufmgr, fd, size);
if (buffer == NULL)
return NULL;
ret = drm_intel_bo_get_tiling(buffer, tiling, bit_6_swizzle);
diff --git a/src/mesa/drivers/dri/i915/intel_regions.h
b/src/mesa/drivers/dri/i915/intel_regions.h
index 5c612a9..6bc4a42 100644
--- a/src/mesa/drivers/dri/i915/intel_regions.h
+++ b/src/mesa/drivers/dri/i915/intel_regions.h
@@ -91,7 +91,7 @@ struct intel_region *
intel_region_alloc_for_fd(struct intel_screen *screen,
GLuint cpp,
GLuint width, GLuint height, GLuint pitch,
- int fd, const char *name);
+ GLuint size, int fd, const char *name);
bool
intel_region_flink(struct intel_region *region, uint32_t *name);
diff --git a/src/mesa/drivers/dri/i915/intel_screen.c
b/src/mesa/drivers/dri/i915/intel_screen.c
index 7b73b80..d46d0eb 100644
--- a/src/mesa/drivers/dri/i915/intel_screen.c
+++ b/src/mesa/drivers/dri/i915/intel_screen.c
@@ -654,8 +654,8 @@ intel_create_image_from_fds(__DRIscreen *screen,
return NULL;
image-region = intel_region_alloc_for_fd(intelScreen,
- 1, width, height,
- strides[0], fds[0], image);
+ f-planes[0].cpp, width, height,
strides[0],
+ height * strides[0], fds[0],
image);
if (image-region == NULL) {
free(image);
return NULL;
diff --git a/src/mesa/drivers/dri/i965/intel_regions.c
b/src/mesa/drivers/dri/i965/intel_regions.c
index a6b80fd..3920f4f 100644
--- a/src/mesa/drivers/dri/i965/intel_regions.c
+++ b/src/mesa/drivers/dri/i965/intel_regions.c
@@ -209,6 +209,7 @@ struct intel_region *
intel_region_alloc_for_fd(struct intel_screen *screen,
GLuint cpp,
GLuint width, GLuint height, GLuint pitch,
+ GLuint size,
int fd, const char *name)
{
struct intel_region *region;
@@ -216,8 +217,7 @@ intel_region_alloc_for_fd(struct intel_screen *screen,
int ret;
uint32_t bit_6_swizzle, tiling;
- buffer = drm_intel_bo_gem_create_from_prime(screen-bufmgr,
- fd, height * pitch);
+ buffer = drm_intel_bo_gem_create_from_prime(screen-bufmgr, fd, size);
if (buffer == NULL)
return NULL;
ret = drm_intel_bo_get_tiling(buffer, tiling, bit_6_swizzle);
diff --git a/src/mesa/drivers/dri/i965/intel_regions.h
b/src/mesa/drivers/dri/i965/intel_regions.h
index f08a113..05dfef3 100644
--- a/src/mesa/drivers/dri/i965/intel_regions.h
+++ b/src/mesa/drivers/dri/i965/intel_regions.h
@@ -92,6 +92,7 @@ struct intel_region *
intel_region_alloc_for_fd(struct intel_screen *screen,
GLuint cpp,
GLuint width, GLuint height, GLuint pitch,
+ GLuint size,
int fd, const char *name);
bool
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index
Mesa (master): dri/intel: Split out DRI2 buffer update code to separate function
Module: Mesa
Branch: master
Commit: 888533dcd6fe30fc0729ef4ae8fa495c69dcc629
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=888533dcd6fe30fc0729ef4ae8fa495c69dcc629
Author: Keith Packard kei...@keithp.com
Date: Mon Jun 3 20:56:41 2013 -0700
dri/intel: Split out DRI2 buffer update code to separate function
Make an easy place to splice in a DRI3 version of this function
Signed-off-by: Keith Packard kei...@keithp.com
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
---
src/mesa/drivers/dri/i915/intel_context.c | 90 -
src/mesa/drivers/dri/i965/brw_context.c | 22 ++-
2 files changed, 68 insertions(+), 44 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/intel_context.c
b/src/mesa/drivers/dri/i915/intel_context.c
index baa8b6e..1568a16 100644
--- a/src/mesa/drivers/dri/i915/intel_context.c
+++ b/src/mesa/drivers/dri/i915/intel_context.c
@@ -141,15 +141,58 @@ intel_process_dri2_buffer(struct intel_context *intel,
struct intel_renderbuffer *rb,
const char *buffer_name);
-void
-intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
+static void
+intel_update_dri2_buffers(struct intel_context *intel, __DRIdrawable *drawable)
{
- struct gl_framebuffer *fb = drawable-driverPrivate;
- struct intel_renderbuffer *rb;
- struct intel_context *intel = context-driverPrivate;
__DRIbuffer *buffers = NULL;
int i, count;
const char *region_name;
+ struct intel_renderbuffer *rb;
+ struct gl_framebuffer *fb = drawable-driverPrivate;
+
+ intel_query_dri2_buffers(intel, drawable, buffers, count);
+
+ if (buffers == NULL)
+ return;
+
+ for (i = 0; i count; i++) {
+ switch (buffers[i].attachment) {
+ case __DRI_BUFFER_FRONT_LEFT:
+ rb = intel_get_renderbuffer(fb, BUFFER_FRONT_LEFT);
+ region_name = dri2 front buffer;
+ break;
+
+ case __DRI_BUFFER_FAKE_FRONT_LEFT:
+ rb = intel_get_renderbuffer(fb, BUFFER_FRONT_LEFT);
+ region_name = dri2 fake front buffer;
+ break;
+
+ case __DRI_BUFFER_BACK_LEFT:
+ rb = intel_get_renderbuffer(fb, BUFFER_BACK_LEFT);
+ region_name = dri2 back buffer;
+ break;
+
+ case __DRI_BUFFER_DEPTH:
+ case __DRI_BUFFER_HIZ:
+ case __DRI_BUFFER_DEPTH_STENCIL:
+ case __DRI_BUFFER_STENCIL:
+ case __DRI_BUFFER_ACCUM:
+ default:
+ fprintf(stderr,
+ unhandled buffer attach event, attachment type %d\n,
+ buffers[i].attachment);
+ return;
+ }
+
+ intel_process_dri2_buffer(intel, drawable, buffers[i], rb, region_name);
+ }
+}
+
+void
+intel_update_renderbuffers(__DRIcontext *context, __DRIdrawable *drawable)
+{
+ struct intel_context *intel = context-driverPrivate;
+ __DRIscreen *screen = intel-intelScreen-driScrnPriv;
/* Set this up front, so that in case our buffers get invalidated
* while we're getting new buffers, we don't clobber the stamp and
@@ -159,42 +202,7 @@ intel_update_renderbuffers(__DRIcontext *context,
__DRIdrawable *drawable)
if (unlikely(INTEL_DEBUG DEBUG_DRI))
fprintf(stderr, enter %s, drawable %p\n, __func__, drawable);
- intel_query_dri2_buffers(intel, drawable, buffers, count);
-
- if (buffers == NULL)
- return;
-
- for (i = 0; i count; i++) {
- switch (buffers[i].attachment) {
- case __DRI_BUFFER_FRONT_LEFT:
- rb = intel_get_renderbuffer(fb, BUFFER_FRONT_LEFT);
- region_name = dri2 front buffer;
- break;
-
- case __DRI_BUFFER_FAKE_FRONT_LEFT:
- rb = intel_get_renderbuffer(fb, BUFFER_FRONT_LEFT);
- region_name = dri2 fake front buffer;
- break;
-
- case __DRI_BUFFER_BACK_LEFT:
- rb = intel_get_renderbuffer(fb, BUFFER_BACK_LEFT);
- region_name = dri2 back buffer;
- break;
-
- case __DRI_BUFFER_DEPTH:
- case __DRI_BUFFER_HIZ:
- case __DRI_BUFFER_DEPTH_STENCIL:
- case __DRI_BUFFER_STENCIL:
- case __DRI_BUFFER_ACCUM:
- default:
- fprintf(stderr,
- unhandled buffer attach event, attachment type %d\n,
- buffers[i].attachment);
- return;
- }
-
- intel_process_dri2_buffer(intel, drawable, buffers[i], rb,
region_name);
- }
+ intel_update_dri2_buffers(intel, drawable);
driUpdateFramebufferSize(intel-ctx, drawable);
}
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 700230b..f9623bb 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -1028,12 +1028,11 @@ intel_process_dri2_buffer(struct brw_context *brw,
struct intel_renderbuffer *rb,
const char *buffer_name);
-void
Mesa (master): glx: Add a more informative debug message in a DRI3 error path.
Module: Mesa
Branch: master
Commit: 4b5d0d10f106ef7659917235dfbcd6d0e00e5bf0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4b5d0d10f106ef7659917235dfbcd6d0e00e5bf0
Author: Eric Anholt e...@anholt.net
Date: Thu Nov 7 15:44:57 2013 -0800
glx: Add a more informative debug message in a DRI3 error path.
---
src/glx/dri3_glx.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c
index a78fc80..61cb2de 100644
--- a/src/glx/dri3_glx.c
+++ b/src/glx/dri3_glx.c
@@ -1579,6 +1579,7 @@ static const struct glx_screen_vtable dri3_screen_vtable
= {
static struct glx_screen *
dri3_create_screen(int screen, struct glx_display * priv)
{
+ xcb_connection_t *c = XGetXCBConnection(priv-dpy);
const __DRIconfig **driver_configs;
const __DRIextension **extensions;
const struct dri3_display *const pdp = (struct dri3_display *)
@@ -1602,9 +1603,15 @@ dri3_create_screen(int screen, struct glx_display * priv)
psc-fd = dri3_open(priv-dpy, RootWindow(priv-dpy, screen), None);
if (psc-fd 0) {
+ int conn_error = xcb_connection_has_error(c);
+
glx_screen_cleanup(psc-base);
free(psc);
InfoMessageF(screen %d does not appear to be DRI3 capable\n, screen);
+
+ if (conn_error)
+ ErrorMessageF(Connection closed during DRI3 initialization failure);
+
return NULL;
}
deviceName = NULL;
___
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Mesa (master): dri3: Fix pixmap buf_id computation
Module: Mesa
Branch: master
Commit: 035cce83f7b3d9a037c9e7cc17a212d6cf7e927f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=035cce83f7b3d9a037c9e7cc17a212d6cf7e927f
Author: Keith Packard kei...@keithp.com
Date: Thu Nov 7 19:01:48 2013 -0800
dri3: Fix pixmap buf_id computation
Looks like some kind of rebase damage to me...
Signed-off-by: Keith Packard kei...@keithp.com
Reviewed-by: Eric Anholt e...@anholt.net
---
src/glx/dri3_glx.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/glx/dri3_glx.c b/src/glx/dri3_glx.c
index 61cb2de..0c8e064 100644
--- a/src/glx/dri3_glx.c
+++ b/src/glx/dri3_glx.c
@@ -945,7 +945,7 @@ dri3_get_pixmap_buffer(__DRIdrawable *driDrawable,
void *loaderPrivate)
{
struct dri3_drawable *pdraw = loaderPrivate;
- int buf_id = buffer_type ==
dri3_pixmap_buf_id(buffer_type);
+ int buf_id =
dri3_pixmap_buf_id(buffer_type);
struct dri3_buffer *buffer = pdraw-buffers[buf_id];
Pixmap pixmap;
xcb_dri3_buffer_from_pixmap_cookie_t bp_cookie;
___
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Mesa (master): Add DRI3+Present loader
Module: Mesa Branch: master Commit: 2d94601582e4f0fcaf8c02a15b23cba39dec7bb1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d94601582e4f0fcaf8c02a15b23cba39dec7bb1 Author: Keith Packard kei...@keithp.com Date: Mon Nov 4 18:15:51 2013 -0800 Add DRI3+Present loader Uses the __DRIimage loader interfaces. v2: Fix _XIOErrors when DRI3 isn't present (change by anholt). Apparently XCB just terminates your connection if you don't check for extensions before using them, instead of returning an error like you'd expect. Signed-off-by: Keith Packard kei...@keithp.com Reviewed-by: Kristian Høgsberg k...@bitplanet.net Reviewed-by: Eric Anholt e...@anholt.net --- configure.ac | 12 +- src/glx/Makefile.am |2 + src/glx/dri3_common.c | 146 src/glx/dri3_glx.c| 1831 + src/glx/dri3_priv.h | 209 ++ src/glx/glxclient.h |2 + src/glx/glxext.c |6 +- 7 files changed, 2204 insertions(+), 4 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=2d94601582e4f0fcaf8c02a15b23cba39dec7bb1 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): dri/i915,dri/i965: Use driGLFormatToImageFormat and driImageFormatToGLFormat
Module: Mesa
Branch: master
Commit: 1f085ba18fb11ca7d378bb2b4423702b1c823786
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f085ba18fb11ca7d378bb2b4423702b1c823786
Author: Keith Packard kei...@keithp.com
Date: Mon Nov 4 17:33:34 2013 -0800
dri/i915,dri/i965: Use driGLFormatToImageFormat and driImageFormatToGLFormat
Remove private versions of these functions
Signed-off-by: Keith Packard kei...@keithp.com
Reviewed-by: Jordan Justen jordan.l.jus...@intel.com
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
---
src/mesa/drivers/dri/i915/intel_screen.c | 53 ++---
src/mesa/drivers/dri/i965/intel_screen.c | 63 ++
2 files changed, 8 insertions(+), 108 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/intel_screen.c
b/src/mesa/drivers/dri/i915/intel_screen.c
index d46d0eb..d93bd9b 100644
--- a/src/mesa/drivers/dri/i915/intel_screen.c
+++ b/src/mesa/drivers/dri/i915/intel_screen.c
@@ -245,32 +245,8 @@ intel_allocate_image(int dri_format, void *loaderPrivate)
image-dri_format = dri_format;
image-offset = 0;
-switch (dri_format) {
-case __DRI_IMAGE_FORMAT_RGB565:
- image-format = MESA_FORMAT_RGB565;
- break;
-case __DRI_IMAGE_FORMAT_XRGB:
- image-format = MESA_FORMAT_XRGB;
- break;
-case __DRI_IMAGE_FORMAT_ARGB:
- image-format = MESA_FORMAT_ARGB;
- break;
-case __DRI_IMAGE_FORMAT_ABGR:
- image-format = MESA_FORMAT_RGBA_REV;
- break;
-case __DRI_IMAGE_FORMAT_XBGR:
- image-format = MESA_FORMAT_RGBX_REV;
- break;
-case __DRI_IMAGE_FORMAT_R8:
- image-format = MESA_FORMAT_R8;
- break;
-case __DRI_IMAGE_FORMAT_GR88:
- image-format = MESA_FORMAT_GR88;
- break;
-case __DRI_IMAGE_FORMAT_NONE:
- image-format = MESA_FORMAT_NONE;
- break;
-default:
+image-format = driImageFormatToGLFormat(dri_format);
+if (image-format == 0) {
free(image);
return NULL;
}
@@ -319,27 +295,6 @@ intel_setup_image_from_dimensions(__DRIimage *image)
image-tile_y = 0;
}
-static inline uint32_t
-intel_dri_format(GLuint format)
-{
- switch (format) {
- case MESA_FORMAT_RGB565:
- return __DRI_IMAGE_FORMAT_RGB565;
- case MESA_FORMAT_XRGB:
- return __DRI_IMAGE_FORMAT_XRGB;
- case MESA_FORMAT_ARGB:
- return __DRI_IMAGE_FORMAT_ARGB;
- case MESA_FORMAT_RGBA_REV:
- return __DRI_IMAGE_FORMAT_ABGR;
- case MESA_FORMAT_R8:
- return __DRI_IMAGE_FORMAT_R8;
- case MESA_FORMAT_RG88:
- return __DRI_IMAGE_FORMAT_GR88;
- }
-
- return MESA_FORMAT_NONE;
-}
-
static __DRIimage *
intel_create_image_from_name(__DRIscreen *screen,
int width, int height, int format,
@@ -397,7 +352,7 @@ intel_create_image_from_renderbuffer(__DRIcontext *context,
image-data = loaderPrivate;
intel_region_reference(image-region, irb-mt-region);
intel_setup_image_from_dimensions(image);
- image-dri_format = intel_dri_format(image-format);
+ image-dri_format = driGLFormatToImageFormat(image-format);
rb-NeedsFinishRenderTexture = true;
return image;
@@ -451,7 +406,7 @@ intel_create_image_from_texture(__DRIcontext *context, int
target,
image-format = obj-Image[face][level]-TexFormat;
image-data = loaderPrivate;
intel_setup_image_from_mipmap_tree(intel, image, iobj-mt, level, zoffset);
- image-dri_format = intel_dri_format(image-format);
+ image-dri_format = driGLFormatToImageFormat(image-format);
if (image-dri_format == MESA_FORMAT_NONE) {
*error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
free(image);
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c
b/src/mesa/drivers/dri/i965/intel_screen.c
index a319b99..099cabf 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -299,38 +299,8 @@ intel_allocate_image(int dri_format, void *loaderPrivate)
image-dri_format = dri_format;
image-offset = 0;
-switch (dri_format) {
-case __DRI_IMAGE_FORMAT_RGB565:
- image-format = MESA_FORMAT_RGB565;
- break;
-case __DRI_IMAGE_FORMAT_XRGB:
- image-format = MESA_FORMAT_XRGB;
- break;
-case __DRI_IMAGE_FORMAT_ARGB2101010:
- image-format = MESA_FORMAT_ARGB2101010;
- break;
-case __DRI_IMAGE_FORMAT_XRGB2101010:
- image-format = MESA_FORMAT_XRGB2101010_UNORM;
- break;
-case __DRI_IMAGE_FORMAT_ARGB:
- image-format = MESA_FORMAT_ARGB;
- break;
-case __DRI_IMAGE_FORMAT_ABGR:
- image-format = MESA_FORMAT_RGBA_REV;
- break;
-case __DRI_IMAGE_FORMAT_XBGR:
- image-format = MESA_FORMAT_RGBX_REV;
- break;
-case __DRI_IMAGE_FORMAT_R8:
- image-format = MESA_FORMAT_R8;
- break;
-case __DRI_IMAGE_FORMAT_GR88:
- image-format = MESA_FORMAT_GR88;
- break;
Mesa (master): dri: add __DRIimageLoaderExtension and __DRIimageDriverExtension
Module: Mesa
Branch: master
Commit: 442442026eb241f05f2b7c03da304e0be047a7da
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=442442026eb241f05f2b7c03da304e0be047a7da
Author: Keith Packard kei...@keithp.com
Date: Mon Nov 4 18:09:51 2013 -0800
dri: add __DRIimageLoaderExtension and __DRIimageDriverExtension
These provide an interface between the driver and the loader to allocate
color buffers through the DRIimage extension interface rather than through a
loader-specific extension (as is used by DRI2, for instance).
The driver uses the loader 'getBuffers' interface to allocate color buffers.
The loader uses the createNewScreen2, createNewDrawable, createNewContext,
getAPIMask and createContextAttribs APIS (mostly shared with DRI2).
This interface will work with the DRI3 loader, and should also work with GBM
and other loaders so that drivers need not be customized for each new loader
interface, as long as they provide this image interface.
v2: Fix build of i915 and i965 together (by anholt)
Signed-off-by: Keith Packard kei...@keithp.com
Reviewed-by: Kristian Høgsberg k...@bitplanet.net
Reviewed-by: Eric Anholt e...@anholt.net
---
include/GL/internal/dri_interface.h | 76
src/mesa/drivers/dri/common/dri_util.c| 13 +++
src/mesa/drivers/dri/common/dri_util.h|6 ++
src/mesa/drivers/dri/i915/intel_context.c | 113 +++-
src/mesa/drivers/dri/i915/intel_mipmap_tree.c | 33 +++
src/mesa/drivers/dri/i915/intel_mipmap_tree.h |8 ++
src/mesa/drivers/dri/i915/intel_screen.c |1 +
src/mesa/drivers/dri/i915/intel_screen.h |1 +
src/mesa/drivers/dri/i965/brw_context.c | 114 +++-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 61 +
src/mesa/drivers/dri/i965/intel_mipmap_tree.h |8 ++
src/mesa/drivers/dri/i965/intel_screen.c |5 +-
12 files changed, 428 insertions(+), 11 deletions(-)
diff --git a/include/GL/internal/dri_interface.h
b/include/GL/internal/dri_interface.h
index fdd7f94..ed43257 100644
--- a/include/GL/internal/dri_interface.h
+++ b/include/GL/internal/dri_interface.h
@@ -86,6 +86,10 @@ typedef struct __DRIdri2LoaderExtensionRec
__DRIdri2LoaderExtension;
typedef struct __DRI2flushExtensionRec __DRI2flushExtension;
typedef struct __DRI2throttleExtensionRec __DRI2throttleExtension;
+
+typedef struct __DRIimageLoaderExtensionRec __DRIimageLoaderExtension;
+typedef struct __DRIimageDriverExtensionRec __DRIimageDriverExtension;
+
/*@}*/
@@ -1334,4 +1338,76 @@ struct __DRI2rendererQueryExtensionRec {
int (*queryString)(__DRIscreen *screen, int attribute, const char **val);
};
+/**
+ * Image Loader extension. Drivers use this to allocate color buffers
+ */
+
+enum __DRIimageBufferMask {
+ __DRI_IMAGE_BUFFER_BACK = (1 0),
+ __DRI_IMAGE_BUFFER_FRONT = (1 1)
+};
+
+struct __DRIimageList {
+ uint32_t image_mask;
+ __DRIimage *back;
+ __DRIimage *front;
+};
+
+#define __DRI_IMAGE_LOADER DRI_IMAGE_LOADER
+#define __DRI_IMAGE_LOADER_VERSION 1
+
+struct __DRIimageLoaderExtensionRec {
+__DRIextension base;
+
+ /**
+* Allocate color buffers.
+*
+* \param driDrawable
+* \param width Width of allocated buffers
+* \param height Height of allocated buffers
+* \param format one of __DRI_IMAGE_FORMAT_*
+* \param stamp Address of variable to be updated when
+* getBuffers must be called again
+* \param loaderPrivate The loaderPrivate for driDrawable
+* \param buffer_maskSet of buffers to allocate
+* \param buffersReturned buffers
+*/
+ int (*getBuffers)(__DRIdrawable *driDrawable,
+ unsigned int format,
+ uint32_t *stamp,
+ void *loaderPrivate,
+ uint32_t buffer_mask,
+ struct __DRIimageList *buffers);
+
+/**
+ * Flush pending front-buffer rendering
+ *
+ * Any rendering that has been performed to the
+ * fake front will be flushed to the front
+ *
+ * \param driDrawableDrawable whose front-buffer is to be flushed
+ * \param loaderPrivate Loader's private data that was previously passed
+ * into __DRIdri2ExtensionRec::createNewDrawable
+ */
+void (*flushFrontBuffer)(__DRIdrawable *driDrawable, void *loaderPrivate);
+};
+
+/**
+ * DRI extension.
+ */
+
+#define __DRI_IMAGE_DRIVER DRI_IMAGE_DRIVER
+#define __DRI_IMAGE_DRIVER_VERSION 1
+
+struct __DRIimageDriverExtensionRec {
+ __DRIextension base;
+
+ /* Common DRI functions, shared with DRI2 */
+ __DRIcreateNewScreen2FunccreateNewScreen2;
+ __DRIcreateNewDrawableFunc createNewDrawable;
+ __DRIcreateNewContextFunccreateNewContext;
+ __DRIcreateContextAttribsFunc
Mesa (master): i965: Tell the unit states how many binding table entries we have.
Module: Mesa
Branch: master
Commit: ff337bc80069c74c6ad5d4ce84cd2029282d9e93
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff337bc80069c74c6ad5d4ce84cd2029282d9e93
Author: Eric Anholt e...@anholt.net
Date: Fri Nov 1 17:43:43 2013 -0700
i965: Tell the unit states how many binding table entries we have.
Before the series with 3c9dc2d31b80fc73bffa1f40a91443a53229c8e2 to
dynamically assign our binding table indices, we didn't really track our
binding table count per shader, so we never filled in these fields.
Affects cairo-gl trace runtime by -2.47953% +/- 1.07281% (n=20)
Reviewed-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_vs_state.c |3 ++-
src/mesa/drivers/dri/i965/brw_wm_state.c |3 ++-
src/mesa/drivers/dri/i965/gen6_vs_state.c |4 +++-
src/mesa/drivers/dri/i965/gen6_wm_state.c |5 +
src/mesa/drivers/dri/i965/gen7_gs_state.c |4 +++-
src/mesa/drivers/dri/i965/gen7_vs_state.c |4 +++-
src/mesa/drivers/dri/i965/gen7_wm_state.c |4
7 files changed, 22 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vs_state.c
b/src/mesa/drivers/dri/i965/brw_vs_state.c
index cdffac3..216b3dd 100644
--- a/src/mesa/drivers/dri/i965/brw_vs_state.c
+++ b/src/mesa/drivers/dri/i965/brw_vs_state.c
@@ -79,7 +79,8 @@ brw_upload_vs_unit(struct brw_context *brw)
*/
vs-thread1.single_program_flow = (brw-gen == 5);
- vs-thread1.binding_table_entry_count = 0;
+ vs-thread1.binding_table_entry_count =
+ brw-vs.prog_data-base.base.binding_table.size_bytes / 4;
if (brw-vs.prog_data-base.total_scratch != 0) {
vs-thread2.scratch_space_base_pointer =
diff --git a/src/mesa/drivers/dri/i965/brw_wm_state.c
b/src/mesa/drivers/dri/i965/brw_wm_state.c
index 9aa32c0..406dbbe 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_state.c
@@ -120,7 +120,8 @@ brw_upload_wm_unit(struct brw_context *brw)
else
wm-thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754;
- wm-thread1.binding_table_entry_count = 0;
+ wm-thread1.binding_table_entry_count =
+ brw-wm.prog_data-base.binding_table.size_bytes / 4;
if (brw-wm.prog_data-total_scratch != 0) {
wm-thread2.scratch_space_base_pointer =
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c
b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index 569ec8c..80129cd 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -165,7 +165,9 @@ upload_vs_state(struct brw_context *brw)
OUT_BATCH(_3DSTATE_VS 16 | (6 - 2));
OUT_BATCH(stage_state-prog_offset);
OUT_BATCH(floating_point_mode |
-((ALIGN(stage_state-sampler_count, 4)/4)
GEN6_VS_SAMPLER_COUNT_SHIFT));
+((ALIGN(stage_state-sampler_count, 4)/4)
GEN6_VS_SAMPLER_COUNT_SHIFT) |
+ ((brw-vs.prog_data-base.base.binding_table.size_bytes / 4)
+ GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
if (brw-vs.prog_data-base.total_scratch) {
OUT_RELOC(stage_state-scratch_bo,
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c
b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index 42d8789..5773246 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -146,6 +146,11 @@ upload_wm_state(struct brw_context *brw)
/* CACHE_NEW_SAMPLER */
dw2 |= (ALIGN(brw-wm.base.sampler_count, 4) / 4)
GEN6_WM_SAMPLER_COUNT_SHIFT;
+
+ /* CACHE_NEW_WM_PROG */
+ dw2 |= ((brw-wm.prog_data-base.binding_table.size_bytes / 4)
+ GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT);
+
dw4 |= (brw-wm.prog_data-first_curbe_grf
GEN6_WM_DISPATCH_START_GRF_SHIFT_0);
dw4 |= (brw-wm.prog_data-first_curbe_grf_16
diff --git a/src/mesa/drivers/dri/i965/gen7_gs_state.c
b/src/mesa/drivers/dri/i965/gen7_gs_state.c
index 2602200..584f2db 100644
--- a/src/mesa/drivers/dri/i965/gen7_gs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_gs_state.c
@@ -85,7 +85,9 @@ upload_gs_state(struct brw_context *brw)
OUT_BATCH(_3DSTATE_GS 16 | (7 - 2));
OUT_BATCH(stage_state-prog_offset);
OUT_BATCH(((ALIGN(stage_state-sampler_count, 4)/4)
- GEN6_GS_SAMPLER_COUNT_SHIFT));
+ GEN6_GS_SAMPLER_COUNT_SHIFT) |
+((brw-gs.prog_data-base.base.binding_table.size_bytes / 4)
+ GEN6_GS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
if (brw-gs.prog_data-base.total_scratch) {
OUT_RELOC(stage_state-scratch_bo,
diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c
b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index 4fd1913..1e76eb1 100644
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c
@@ -100,7 +100,9 @@ upload_vs_state(struct brw_context *brw)
OUT_BATCH(stage_state-prog_offset);
OUT_BATCH(floating_point_mode |
((ALIGN(stage_state-sampler_count, 4)/4
Mesa (master): i965: Fix context initialization after 2f896627175384fd5
Module: Mesa
Branch: master
Commit: 3f319eef76a31776085accb38c06851bc04f64b8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f319eef76a31776085accb38c06851bc04f64b8
Author: Eric Anholt e...@anholt.net
Date: Mon Nov 4 15:49:52 2013 -0800
i965: Fix context initialization after 2f896627175384fd5
You can't return stack-initialized values and expect anything good to
happen.
Reviewed-by: Chad Versace chad.vers...@linux.intel.com
Reviewed-by: Matt Turner matts...@gmail.com
---
src/mesa/drivers/dri/i965/brw_context.c |9 ++---
1 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 1f4fbbf..ab420fb 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -275,12 +275,15 @@ brw_init_driver_functions(struct brw_context *brw,
static const int*
brw_supported_msaa_modes(const struct brw_context *brw)
{
+ static const int gen7_samples[] = {8, 4, 0};
+ static const int gen6_samples[] = {4, 0};
+ static const int gen4_samples[] = {0};
if (brw-gen = 7) {
- return (int[]){8, 4, 0};
+ return gen7_samples;
} else if (brw-gen == 6) {
- return (int[]){4, 0};
+ return gen6_samples;
} else {
- return (int[]){0};
+ return gen4_samples;
}
}
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Mesa (master): i965/vec4: Don't overwrite op[1] when doing a UBO load.
Module: Mesa
Branch: master
Commit: 3641b97bdce558d980799b00422c6aee7d472cf5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3641b97bdce558d980799b00422c6aee7d472cf5
Author: Eric Anholt e...@anholt.net
Date: Wed Oct 30 17:09:53 2013 -0700
i965/vec4: Don't overwrite op[1] when doing a UBO load.
Prior to the GLSL CSE pass, all of our testing happened to have a freshly
computed temporary in op[1], from the multiply by 16 to get a byte offset.
As of CSE you'll get var_refs of a reused value when you've got multiple
loads from the same offset.
Make a proper temporary for computing our temporary value, to avoid
shifting the value farther and farther down. Avoids a regression in
gs-float-array-variable-index
Reviewed-by: Paul Berry stereotype...@gmail.com
---
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 16a188f..7a0dfa5 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -1569,7 +1569,7 @@ vec4_visitor::visit(ir_expression *ir)
ir_constant *uniform_block = ir-operands[0]-as_constant();
ir_constant *const_offset_ir = ir-operands[1]-as_constant();
unsigned const_offset = const_offset_ir ? const_offset_ir-value.u[0] :
0;
- src_reg offset = op[1];
+ src_reg offset;
/* Now, load the vector from that offset. */
assert(ir-type-is_vector() || ir-type-is_scalar());
@@ -1581,7 +1581,8 @@ vec4_visitor::visit(ir_expression *ir)
if (const_offset_ir) {
offset = src_reg(const_offset / 16);
} else {
- emit(SHR(dst_reg(offset), offset, src_reg(4)));
+ offset = src_reg(this, glsl_type::uint_type);
+ emit(SHR(dst_reg(offset), op[1], src_reg(4)));
}
vec4_instruction *pull =
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Mesa (master): glsl: Add a CSE pass.
Module: Mesa
Branch: master
Commit: fd05ede0d05ee896cf07e2f690ddb42567f9f606
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fd05ede0d05ee896cf07e2f690ddb42567f9f606
Author: Eric Anholt e...@anholt.net
Date: Thu Oct 17 10:28:40 2013 -0700
glsl: Add a CSE pass.
This only operates on constant/uniform values for now, because otherwise I'd
have to deal with killing my available CSE entries when assignments happen,
and getting even this working in the tree ir was painful enough.
As is, it has the following effect in shader-db:
total instructions in shared programs: 1524077 - 1521964 (-0.14%)
instructions in affected programs: 50629 - 48516 (-4.17%)
GAINED:0
LOST: 0
And, for tropics, that accounts for most of the effect, the FPS
improvement is 11.67% +/- 0.72% (n=3).
v2: Use read_only field of the variable, manually check the lod_info union
members, use get_num_operands(), rename cse_operands_visitor to
is_cse_candidate_visitor, move all is-a-candidate logic to that
function, and call it before checking for CSE on a given rvalue, more
comments, use private keyword.
Reviewed-by: Paul Berry stereotype...@gmail.com
---
src/glsl/Makefile.sources |1 +
src/glsl/glsl_parser_extras.cpp |1 +
src/glsl/ir.h |6 +
src/glsl/ir_optimization.h |1 +
src/glsl/opt_cse.cpp| 599 +++
5 files changed, 608 insertions(+), 0 deletions(-)
diff --git a/src/glsl/Makefile.sources b/src/glsl/Makefile.sources
index 2f7bfa1..2aabc05 100644
--- a/src/glsl/Makefile.sources
+++ b/src/glsl/Makefile.sources
@@ -83,6 +83,7 @@ LIBGLSL_FILES = \
$(GLSL_SRCDIR)/opt_constant_variable.cpp \
$(GLSL_SRCDIR)/opt_copy_propagation.cpp \
$(GLSL_SRCDIR)/opt_copy_propagation_elements.cpp \
+ $(GLSL_SRCDIR)/opt_cse.cpp \
$(GLSL_SRCDIR)/opt_dead_builtin_varyings.cpp \
$(GLSL_SRCDIR)/opt_dead_code.cpp \
$(GLSL_SRCDIR)/opt_dead_code_local.cpp \
diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp
index 77e8816..6589b51 100644
--- a/src/glsl/glsl_parser_extras.cpp
+++ b/src/glsl/glsl_parser_extras.cpp
@@ -1604,6 +1604,7 @@ do_common_optimization(exec_list *ir, bool linked,
else
progress = do_constant_variable_unlinked(ir) || progress;
progress = do_constant_folding(ir) || progress;
+ progress = do_cse(ir) || progress;
progress = do_algebraic(ir) || progress;
progress = do_lower_jumps(ir) || progress;
progress = do_vec_index_to_swizzle(ir) || progress;
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index 5b30fe5..2f06fb9 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -133,6 +133,7 @@ public:
virtual class ir_return *as_return() { return NULL; }
virtual class ir_if *as_if() { return NULL; }
virtual class ir_swizzle * as_swizzle() { return NULL; }
+ virtual class ir_texture * as_texture() { return NULL; }
virtual class ir_constant * as_constant() { return NULL; }
virtual class ir_discard * as_discard() { return NULL; }
virtual class ir_jump * as_jump() { return NULL; }
@@ -1731,6 +1732,11 @@ public:
v-visit(this);
}
+ virtual ir_texture *as_texture()
+ {
+ return this;
+ }
+
virtual ir_visitor_status accept(ir_hierarchical_visitor *);
/**
diff --git a/src/glsl/ir_optimization.h b/src/glsl/ir_optimization.h
index 074686c..3ca9f57 100644
--- a/src/glsl/ir_optimization.h
+++ b/src/glsl/ir_optimization.h
@@ -77,6 +77,7 @@ bool do_constant_variable_unlinked(exec_list *instructions);
bool do_copy_propagation(exec_list *instructions);
bool do_copy_propagation_elements(exec_list *instructions);
bool do_constant_propagation(exec_list *instructions);
+bool do_cse(exec_list *instructions);
void do_dead_builtin_varyings(struct gl_context *ctx,
gl_shader *producer, gl_shader *consumer,
unsigned num_tfeedback_decls,
diff --git a/src/glsl/opt_cse.cpp b/src/glsl/opt_cse.cpp
new file mode 100644
index 000..c0fdb23
--- /dev/null
+++ b/src/glsl/opt_cse.cpp
@@ -0,0 +1,599 @@
+/*
+ * Copyright © 2013 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies
Mesa (master): i965/fs: Prefer more-critical instructions of the same age in LIFO scheduling.
Module: Mesa
Branch: master
Commit: 20dbeadd83ffca2345c4ba1f1ac27c19bade0d4a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=20dbeadd83ffca2345c4ba1f1ac27c19bade0d4a
Author: Eric Anholt e...@anholt.net
Date: Mon Oct 28 15:17:07 2013 -0700
i965/fs: Prefer more-critical instructions of the same age in LIFO scheduling.
When faced with a million instructions that all became candidates at the
same time (none of which individually reduce register pressure), the ones
on the critical path are more likely to be the ones that will free up some
candidates soon.
shader-db:
total instructions in shared programs: 1681070 - 1681070 (0.00%)
instructions in affected programs: 0 - 0
GAINED:40
LOST: 74
Fixes indistinguishable-from-hanging behavior in GLES3conform's
uniform_buffer_object_max_uniform_block_size test, regressed by
c3c9a8c85758796a26b48e484286e6b6f5a5299a. Given that
93bd627d5a6c485948b94488e6cd53a06b7ebdcf was unlocked by that commit, the
net effect on 16-wide program count is still quite positive, and I think
this should give us more stable scheduling (less dependency on original
instruction emit order).
v2: Comment suggestions by Paul
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=70943
Reviewed-by: Paul Berry stereotype...@gmail.com
---
.../drivers/dri/i965/brw_schedule_instructions.cpp | 82
1 files changed, 67 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 8437a4e..5093dd5 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -68,6 +68,7 @@ public:
this-child_count = 0;
this-parent_count = 0;
this-unblocked_time = 0;
+ this-cand_generation = 0;
/* We can't measure Gen6 timings directly but expect them to be much
* closer to Gen7 than Gen4.
@@ -91,6 +92,12 @@ public:
int latency;
/**
+* Which iteration of pushing groups of children onto the candidates list
+* this node was a part of.
+*/
+ unsigned cand_generation;
+
+ /**
* This is the sum of the instruction's latency plus the maximum delay of
* its children, or just the issue_time if it's a leaf node.
*/
@@ -973,26 +980,68 @@ fs_instruction_scheduler::choose_instruction_to_schedule()
* variables so that we can avoid register spilling, or get 16-wide
* shaders which naturally do a better job of hiding instruction
* latency.
- *
- * To do so, schedule our instructions in a roughly LIFO/depth-first
- * order: when new instructions become available as a result of
- * scheduling something, choose those first so that our result
- * hopefully is consumed quickly.
- *
- * The exception is messages that generate more than one result
- * register (AKA texturing). In those cases, the LIFO search would
- * normally tend to choose them quickly (because scheduling the
- * previous message not only unblocked the children using its result,
- * but also the MRF setup for the next sampler message, which in turn
- * unblocks the next sampler message).
*/
foreach_list(node, instructions) {
schedule_node *n = (schedule_node *)node;
fs_inst *inst = (fs_inst *)n-inst;
- chosen = n;
- if (v-brw-gen = 7 || inst-regs_written = 1)
-break;
+ if (!chosen) {
+chosen = n;
+continue;
+ }
+
+ /* Prefer instructions that recently became available for scheduling.
+ * These are the things that are most likely to (eventually) make a
+ * variable dead and reduce register pressure. Typical register
+ * pressure estimates don't work for us because most of our pressure
+ * comes from texturing, where no single instruction to schedule will
+ * make a vec4 value dead.
+ */
+ if (n-cand_generation chosen-cand_generation) {
+chosen = n;
+continue;
+ } else if (n-cand_generation chosen-cand_generation) {
+continue;
+ }
+
+ /* On MRF-using chips, prefer non-SEND instructions. If we don't do
+ * this, then because we prefer instructions that just became
+ * candidates, we'll end up in a pattern of scheduling a SEND, then
+ * the MRFs for the next SEND, then the next SEND, then the MRFs,
+ * etc., without ever consuming the results of a send.
+ */
+ if (v-brw-gen 7) {
+fs_inst *chosen_inst = (fs_inst *)chosen-inst;
+
+/* We use regs_written 1 as our test for the kind of send
+ * instruction to avoid -- only sends generate many regs, and a
+ * single-result send is probably
Mesa (master): i965: Compute the node's delay time for scheduling.
Module: Mesa
Branch: master
Commit: 017361dd37b678efa44facc4a396784f4ce980bc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=017361dd37b678efa44facc4a396784f4ce980bc
Author: Eric Anholt e...@anholt.net
Date: Mon Oct 28 00:11:45 2013 -0700
i965: Compute the node's delay time for scheduling.
This is a step in doing scheduling as described in Muchnick (p538). A
difference is that our latency function is only specific to one
instruction (it doesn't describe, for example, the different latency
between WAR of a send's arguments and RAW of a send's destination), but
that's changeable later. We also don't separately compute the postorder
traversal of the graph, since we can use the setting of the delay field as
the visited flag.
Reviewed-by: Paul Berry stereotype...@gmail.com
---
.../drivers/dri/i965/brw_schedule_instructions.cpp | 28
1 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
index 27de0e6..8437a4e 100644
--- a/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
@@ -89,6 +89,12 @@ public:
int child_array_size;
int unblocked_time;
int latency;
+
+ /**
+* This is the sum of the instruction's latency plus the maximum delay of
+* its children, or just the issue_time if it's a leaf node.
+*/
+ int delay;
};
void
@@ -365,6 +371,7 @@ public:
void run(exec_list *instructions);
void add_inst(backend_instruction *inst);
+ void compute_delay(schedule_node *node);
virtual void calculate_deps() = 0;
virtual schedule_node *choose_instruction_to_schedule() = 0;
@@ -439,6 +446,21 @@ instruction_scheduler::add_inst(backend_instruction *inst)
instructions.push_tail(n);
}
+/** Recursive computation of the delay member of a node. */
+void
+instruction_scheduler::compute_delay(schedule_node *n)
+{
+ if (!n-child_count) {
+ n-delay = issue_time(n-inst);
+ } else {
+ for (int i = 0; i n-child_count; i++) {
+ if (!n-children[i]-delay)
+compute_delay(n-children[i]);
+ n-delay = MAX2(n-delay, n-latency + n-children[i]-delay);
+ }
+ }
+}
+
/**
* Add a dependency between two instruction nodes.
*
@@ -1118,6 +1140,12 @@ instruction_scheduler::run(exec_list *all_instructions)
break;
}
calculate_deps();
+
+ foreach_list(node, instructions) {
+ schedule_node *n = (schedule_node *)node;
+ compute_delay(n);
+ }
+
schedule_instructions(next_block_header);
}
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Mesa (master): i965/fs: Split find what MRFs were used to a helper function.
Module: Mesa
Branch: master
Commit: b3f6690406ed6c427d0bedfd1be481ea224418e4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3f6690406ed6c427d0bedfd1be481ea224418e4
Author: Eric Anholt e...@anholt.net
Date: Tue Oct 29 12:18:10 2013 -0700
i965/fs: Split find what MRFs were used to a helper function.
I'm going to need to reuse this for fixing register spilling on SIMD16.
Note that BRW_MAX_MRF is 16, which is the same as BRW_MAX_GRF -
GEN7_MRF_HACK_START.
Reviewed-by: Paul Berry stereotype...@gmail.com
---
src/mesa/drivers/dri/i965/brw_fs.h|1 +
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 33 +++--
2 files changed, 25 insertions(+), 9 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 5f331e1..50a045e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -289,6 +289,7 @@ public:
void assign_urb_setup();
bool assign_regs();
void assign_regs_trivial();
+ void get_used_mrfs(bool *mrf_used);
void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
int first_payload_node);
void setup_mrf_hack_interference(struct ra_graph *g,
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 157c9ae..0b00b91 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -347,18 +347,20 @@ fs_visitor::setup_payload_interference(struct ra_graph *g,
}
/**
- * Sets interference between virtual GRFs and usage of the high GRFs for SEND
- * messages (treated as MRFs in code generation).
+ * Sets the mrf_used array to indicate which MRFs are used by the shader IR
+ *
+ * This is used in assign_regs() to decide which of the GRFs that we use as
+ * MRFs on gen7 get normally register allocated, and in register spilling to
+ * see if we can actually use MRFs to do spills without overwriting normal MRF
+ * contents.
*/
void
-fs_visitor::setup_mrf_hack_interference(struct ra_graph *g, int first_mrf_node)
+fs_visitor::get_used_mrfs(bool *mrf_used)
{
- int mrf_count = BRW_MAX_GRF - GEN7_MRF_HACK_START;
int reg_width = dispatch_width / 8;
- /* Identify all the MRFs used in the program. */
- bool mrf_used[mrf_count];
- memset(mrf_used, 0, sizeof(mrf_used));
+ memset(mrf_used, 0, BRW_MAX_MRF * sizeof(bool));
+
foreach_list(node, this-instructions) {
fs_inst *inst = (fs_inst *)node;
@@ -380,9 +382,22 @@ fs_visitor::setup_mrf_hack_interference(struct ra_graph
*g, int first_mrf_node)
}
}
}
+}
+
+/**
+ * Sets interference between virtual GRFs and usage of the high GRFs for SEND
+ * messages (treated as MRFs in code generation).
+ */
+void
+fs_visitor::setup_mrf_hack_interference(struct ra_graph *g, int first_mrf_node)
+{
+ int reg_width = dispatch_width / 8;
+
+ bool mrf_used[BRW_MAX_MRF];
+ get_used_mrfs(mrf_used);
- for (int i = 0; i mrf_count; i++) {
- /* Mark each payload reg node as being allocated to its physical
register.
+ for (int i = 0; i BRW_MAX_MRF; i++) {
+ /* Mark each MRF reg node as being allocated to its physical register.
*
* The alternative would be to have per-physical-register classes, which
* would just be silly.
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Mesa (master): i965/fs: Update an ancient, wrong comment about reg_offset.
Module: Mesa Branch: master Commit: 32ac5634d6c830c93dad5349418ec8db85ec6bde URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=32ac5634d6c830c93dad5349418ec8db85ec6bde Author: Eric Anholt e...@anholt.net Date: Tue Oct 29 01:06:09 2013 -0700 i965/fs: Update an ancient, wrong comment about reg_offset. This hasn't been true since SIMD16 mode was added. Reviewed-by: Paul Berry stereotype...@gmail.com --- src/mesa/drivers/dri/i965/brw_fs.h |8 +--- 1 files changed, 5 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs.h b/src/mesa/drivers/dri/i965/brw_fs.h index 5b78313..5f331e1 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.h +++ b/src/mesa/drivers/dri/i965/brw_fs.h @@ -88,9 +88,11 @@ public: */ int reg; /** -* For virtual registers, this is a hardware register offset from -* the start of the register block (for example, a constant index -* in an array access). +* Offset from the start of the contiguous register block. +* +* For pre-register-allocation GRFs, this is in units of a float per pixel +* (1 hardware register for SIMD8 mode, or 2 registers for SIMD16 mode). +* For uniforms, this is in units of 1 float. */ int reg_offset; /** Register type. BRW_REGISTER_TYPE_* */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: Merge together opcodes for SHADER_OPCODE_GEN4_SCRATCH_READ/WRITE
Module: Mesa
Branch: master
Commit: 6032261682388ced64bd33328a5025f561927a38
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6032261682388ced64bd33328a5025f561927a38
Author: Eric Anholt e...@anholt.net
Date: Wed Oct 16 11:45:06 2013 -0700
i965: Merge together opcodes for SHADER_OPCODE_GEN4_SCRATCH_READ/WRITE
I'm going to be introducing gen7 variants, and the previous naming was
going to get confusing.
Reviewed-by: Paul Berry stereotype...@gmail.com
---
src/mesa/drivers/dri/i965/brw_defines.h|7 +++
src/mesa/drivers/dri/i965/brw_fs.cpp |4 ++--
src/mesa/drivers/dri/i965/brw_fs.h |4 ++--
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 12 ++--
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 12 +++-
src/mesa/drivers/dri/i965/brw_shader.cpp | 14 +-
src/mesa/drivers/dri/i965/brw_vec4.cpp |4 ++--
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp |4 ++--
.../drivers/dri/i965/brw_vec4_reg_allocate.cpp |4 ++--
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp |4 ++--
10 files changed, 33 insertions(+), 36 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index fbc787a..2248693 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -778,14 +778,15 @@ enum opcode {
SHADER_OPCODE_UNTYPED_ATOMIC,
SHADER_OPCODE_UNTYPED_SURFACE_READ,
+ SHADER_OPCODE_GEN4_SCRATCH_READ,
+ SHADER_OPCODE_GEN4_SCRATCH_WRITE,
+
FS_OPCODE_DDX,
FS_OPCODE_DDY,
FS_OPCODE_PIXEL_X,
FS_OPCODE_PIXEL_Y,
FS_OPCODE_CINTERP,
FS_OPCODE_LINTERP,
- FS_OPCODE_SPILL,
- FS_OPCODE_UNSPILL,
FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD,
FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD_GEN7,
FS_OPCODE_VARYING_PULL_CONSTANT_LOAD,
@@ -799,8 +800,6 @@ enum opcode {
FS_OPCODE_PLACEHOLDER_HALT,
VS_OPCODE_URB_WRITE,
- VS_OPCODE_SCRATCH_READ,
- VS_OPCODE_SCRATCH_WRITE,
VS_OPCODE_PULL_CONSTANT_LOAD,
VS_OPCODE_PULL_CONSTANT_LOAD_GEN7,
VS_OPCODE_UNPACK_FLAGS_SIMD4X2,
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index db48da2..5e95d3a 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -766,11 +766,11 @@ fs_visitor::implied_mrf_writes(fs_inst *inst)
case FS_OPCODE_FB_WRITE:
return 2;
case FS_OPCODE_UNIFORM_PULL_CONSTANT_LOAD:
- case FS_OPCODE_UNSPILL:
+ case SHADER_OPCODE_GEN4_SCRATCH_READ:
return 1;
case FS_OPCODE_VARYING_PULL_CONSTANT_LOAD:
return inst-mlen;
- case FS_OPCODE_SPILL:
+ case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
return 2;
case SHADER_OPCODE_UNTYPED_ATOMIC:
case SHADER_OPCODE_UNTYPED_SURFACE_READ:
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index fb1da4c..0512ab4 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -523,8 +523,8 @@ private:
void generate_ddx(fs_inst *inst, struct brw_reg dst, struct brw_reg src);
void generate_ddy(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
bool negate_value);
- void generate_spill(fs_inst *inst, struct brw_reg src);
- void generate_unspill(fs_inst *inst, struct brw_reg dst);
+ void generate_scratch_write(fs_inst *inst, struct brw_reg src);
+ void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
struct brw_reg index,
struct brw_reg offset);
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index e16d874..2172949 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -749,7 +749,7 @@ fs_generator::generate_discard_jump(fs_inst *inst)
}
void
-fs_generator::generate_spill(fs_inst *inst, struct brw_reg src)
+fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src)
{
assert(inst-mlen != 0);
@@ -761,7 +761,7 @@ fs_generator::generate_spill(fs_inst *inst, struct brw_reg
src)
}
void
-fs_generator::generate_unspill(fs_inst *inst, struct brw_reg dst)
+fs_generator::generate_scratch_read(fs_inst *inst, struct brw_reg dst)
{
assert(inst-mlen != 0);
@@ -1579,12 +1579,12 @@ fs_generator::generate_code(exec_list *instructions)
generate_ddy(inst, dst, src[0], c-key.render_to_fbo);
break;
- case FS_OPCODE_SPILL:
-generate_spill(inst, src[0]);
+ case SHADER_OPCODE_GEN4_SCRATCH_WRITE:
+generate_scratch_write(inst, src[0]);
break;
- case FS_OPCODE_UNSPILL:
-generate_unspill(inst, dst);
+ case SHADER_OPCODE_GEN4_SCRATCH_READ
Mesa (master): i965/fs: Use the gen7 scratch read opcode when possible.
Module: Mesa
Branch: master
Commit: 8dfc9f038ee3f6a57f0a3f3cc641b0866a6111b7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8dfc9f038ee3f6a57f0a3f3cc641b0866a6111b7
Author: Eric Anholt e...@anholt.net
Date: Wed Oct 16 11:51:22 2013 -0700
i965/fs: Use the gen7 scratch read opcode when possible.
This avoids a lot of message setup we had to do otherwise. Improves
GLB2.7 performance with register spilling force enabled by 1.6442% +/-
0.553218% (n=4).
v2: Use BRW_PREDICATE_NONE, improve a comment (by Paul).
Reviewed-by: Paul Berry stereotype...@gmail.com
---
src/mesa/drivers/dri/i965/brw_defines.h|7 +++
src/mesa/drivers/dri/i965/brw_eu.h |5 ++
src/mesa/drivers/dri/i965/brw_eu_emit.c| 42
src/mesa/drivers/dri/i965/brw_fs.h |1 +
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 10 +
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 15 ++-
.../drivers/dri/i965/brw_schedule_instructions.cpp | 12 ++
src/mesa/drivers/dri/i965/brw_shader.cpp |2 +
8 files changed, 91 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 2248693..bad6d40 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -780,6 +780,7 @@ enum opcode {
SHADER_OPCODE_GEN4_SCRATCH_READ,
SHADER_OPCODE_GEN4_SCRATCH_WRITE,
+ SHADER_OPCODE_GEN7_SCRATCH_READ,
FS_OPCODE_DDX,
FS_OPCODE_DDY,
@@ -1141,6 +1142,12 @@ enum brw_message_target {
#define GEN7_DATAPORT_DC_BYTE_SCATTERED_WRITE 12
#define GEN7_DATAPORT_DC_UNTYPED_SURFACE_WRITE 13
+#define GEN7_DATAPORT_SCRATCH_READ((1 18) | \
+ (0 17))
+#define GEN7_DATAPORT_SCRATCH_WRITE ((1 18) | \
+ (1 17))
+#define GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT12
+
/* HSW */
#define HSW_DATAPORT_DC_PORT0_OWORD_BLOCK_READ 0
#define HSW_DATAPORT_DC_PORT0_UNALIGNED_OWORD_BLOCK_READ1
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
b/src/mesa/drivers/dri/i965/brw_eu.h
index 1a448d0..01f8bcc 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -379,6 +379,11 @@ void brw_oword_block_write_scratch(struct brw_compile *p,
int num_regs,
GLuint offset);
+void gen7_block_read_scratch(struct brw_compile *p,
+ struct brw_reg dest,
+ int num_regs,
+ GLuint offset);
+
void brw_shader_time_add(struct brw_compile *p,
struct brw_reg payload,
uint32_t surf_index);
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 34239be..cc093e0 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -2055,6 +2055,48 @@ brw_oword_block_read_scratch(struct brw_compile *p,
}
}
+void
+gen7_block_read_scratch(struct brw_compile *p,
+struct brw_reg dest,
+int num_regs,
+GLuint offset)
+{
+ dest = retype(dest, BRW_REGISTER_TYPE_UW);
+
+ struct brw_instruction *insn = next_insn(p, BRW_OPCODE_SEND);
+
+ assert(insn-header.predicate_control == BRW_PREDICATE_NONE);
+ insn-header.compression_control = BRW_COMPRESSION_NONE;
+
+ brw_set_dest(p, insn, dest);
+
+ /* The HW requires that the header is present; this is to get the g0.5
+* scratch offset.
+*/
+ bool header_present = true;
+ brw_set_src0(p, insn, brw_vec8_grf(0, 0));
+
+ brw_set_message_descriptor(p, insn,
+ GEN7_SFID_DATAPORT_DATA_CACHE,
+ 1, /* mlen: just g0 */
+ num_regs,
+ header_present,
+ false);
+
+ insn-bits3.ud |= GEN7_DATAPORT_SCRATCH_READ;
+
+ assert(num_regs == 1 || num_regs == 2 || num_regs == 4);
+ insn-bits3.ud |= (num_regs - 1) GEN7_DATAPORT_SCRATCH_NUM_REGS_SHIFT;
+
+ /* According to the docs, offset is A 12-bit HWord offset into the memory
+* Immediate Memory buffer as specified by binding table 0xFF. An HWORD
+* is 32 bytes, which happens to be the size of a register.
+*/
+ offset /= REG_SIZE;
+ assert(offset (1 12));
+ insn-bits3.ud |= offset;
+}
+
/**
* Read a float[4] vector from the data port Data Cache (const buffer).
* Location (in buffer) should be a multiple of 16.
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 0512ab4..a3a4dc0 100644
Mesa (master): i965/fs: Exit the compile if spilling would overwrite in-use MRFs.
Module: Mesa
Branch: master
Commit: 537f183fe67e0cf9f5737106d914cdabcf5d002e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=537f183fe67e0cf9f5737106d914cdabcf5d002e
Author: Eric Anholt e...@anholt.net
Date: Tue Oct 29 12:46:18 2013 -0700
i965/fs: Exit the compile if spilling would overwrite in-use MRFs.
I believe this will never happen in SIMD8 mode, but it could for SIMD16
when we fix it.
v2: Fix off-by-one in my register counting comment (caught by Paul).
Reviewed-by: Paul Berry stereotype...@gmail.com (v1)
---
src/mesa/drivers/dri/i965/brw_fs.h|1 +
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 22 +
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp |2 +
3 files changed, 25 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 50a045e..fb1da4c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -466,6 +466,7 @@ public:
fs_reg shader_start_time;
int grf_used;
+ bool spilled_any_registers;
const unsigned dispatch_width; /** 8 or 16 */
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index d86027e..35dae84 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -643,6 +643,28 @@ fs_visitor::spill_reg(int spill_reg)
unsigned int spill_offset = c-last_scratch;
assert(ALIGN(spill_offset, 16) == spill_offset); /* oword read/write req. */
c-last_scratch += size * REG_SIZE;
+ int spill_base_mrf = dispatch_width 8 ? 13 : 14;
+
+ /* Spills may use MRFs 13-15 in the SIMD16 case. Our texturing is done
+* using up to 11 MRFs starting from either m1 or m2, and fb writes can use
+* up to m13 (gen6+ simd16: 2 header + 8 color + 2 src0alpha + 2 omask) or
+* m15 (gen4-5 simd16: 2 header + 8 color + 1 aads + 2 src depth + 2 dst
+* depth), starting from m1. In summary: We may not be able to spill in
+* SIMD16 mode, because we'd stomp the FB writes.
+*/
+ if (!spilled_any_registers) {
+ bool mrf_used[BRW_MAX_MRF];
+ get_used_mrfs(mrf_used);
+
+ for (int i = spill_base_mrf; i BRW_MAX_MRF; i++) {
+ if (mrf_used[i]) {
+fail(Register spilling not supported with m%d used, i);
+ return;
+ }
+ }
+
+ spilled_any_registers = true;
+ }
/* Generate spill/unspill instructions for the objects being
* spilled. Right now, we spill or unspill the whole thing to a
diff --git a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
index 71b4bf9..0e2dfd3 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
@@ -2722,6 +2722,8 @@ fs_visitor::fs_visitor(struct brw_context *brw,
this-force_uncompressed_stack = 0;
this-force_sechalf_stack = 0;
+ this-spilled_any_registers = false;
+
memset(this-param_size, 0, sizeof(this-param_size));
}
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Mesa (master): i965/fs: Fix register unspills from a reg_offset.
Module: Mesa
Branch: master
Commit: 32182bb004923c8746803aa88d4b4505e4124b8c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=32182bb004923c8746803aa88d4b4505e4124b8c
Author: Eric Anholt e...@anholt.net
Date: Wed Oct 16 12:39:07 2013 -0700
i965/fs: Fix register unspills from a reg_offset.
We were clearing the reg_offset before trying to use it. Oops. Fixes
glsl-fs-texture2drect with the reg spilling debug enabled.
Reviewed-by: Paul Berry stereotype...@gmail.com
---
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 64fb78b..0102b2e 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -677,13 +677,13 @@ fs_visitor::spill_reg(int spill_reg)
if (inst-src[i].file == GRF
inst-src[i].reg == spill_reg) {
int regs_read = inst-regs_read(this, i);
+int subset_spill_offset = (spill_offset +
+ reg_size * inst-src[i].reg_offset);
inst-src[i].reg = virtual_grf_alloc(regs_read);
inst-src[i].reg_offset = 0;
-emit_unspill(inst, inst-src[i],
- spill_offset + reg_size * inst-src[i].reg_offset,
- regs_read);
+emit_unspill(inst, inst-src[i], subset_spill_offset, regs_read);
}
}
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Mesa (master): i965/fs: Fix register spilling for 16-wide.
Module: Mesa
Branch: master
Commit: 0e20051f54f31f83edba9ac9f8f3a16bb747c698
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e20051f54f31f83edba9ac9f8f3a16bb747c698
Author: Eric Anholt e...@anholt.net
Date: Wed Oct 16 12:16:51 2013 -0700
i965/fs: Fix register spilling for 16-wide.
Things blew up when I enabled the debug register spill code without
disabling 16-wide, so I decided to just fix 16-wide spilling.
We still don't generate 16-wide when register spilling happens as part of
allocation (since we expect it to be slower), but now we can experiment
with allowing it in some cases in the future.
Reviewed-by: Paul Berry stereotype...@gmail.com
---
src/mesa/drivers/dri/i965/brw_fs_generator.cpp|8
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 19 +--
2 files changed, 13 insertions(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index ef85837..e16d874 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -756,8 +756,8 @@ fs_generator::generate_spill(fs_inst *inst, struct brw_reg
src)
brw_MOV(p,
retype(brw_message_reg(inst-base_mrf + 1), BRW_REGISTER_TYPE_UD),
retype(src, BRW_REGISTER_TYPE_UD));
- brw_oword_block_write_scratch(p, brw_message_reg(inst-base_mrf), 1,
-inst-offset);
+ brw_oword_block_write_scratch(p, brw_message_reg(inst-base_mrf),
+ inst-mlen, inst-offset);
}
void
@@ -765,8 +765,8 @@ fs_generator::generate_unspill(fs_inst *inst, struct
brw_reg dst)
{
assert(inst-mlen != 0);
- brw_oword_block_read_scratch(p, dst, brw_message_reg(inst-base_mrf), 1,
- inst-offset);
+ brw_oword_block_read_scratch(p, dst, brw_message_reg(inst-base_mrf),
+dispatch_width / 8, inst-offset);
}
void
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
index 35dae84..64fb78b 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
@@ -547,15 +547,12 @@ fs_visitor::emit_unspill(fs_inst *inst, fs_reg dst,
uint32_t spill_offset,
unspill_inst-ir = inst-ir;
unspill_inst-annotation = inst-annotation;
- /* Choose a MRF that won't conflict with an MRF that's live across the
- * spill. Nothing else will make it up to MRF 14/15.
- */
unspill_inst-base_mrf = 14;
unspill_inst-mlen = 1; /* header contains offset */
inst-insert_before(unspill_inst);
dst.reg_offset++;
- spill_offset += REG_SIZE;
+ spill_offset += dispatch_width * sizeof(float);
}
}
@@ -639,10 +636,10 @@ fs_visitor::choose_spill_reg(struct ra_graph *g)
void
fs_visitor::spill_reg(int spill_reg)
{
+ int reg_size = dispatch_width * sizeof(float);
int size = virtual_grf_sizes[spill_reg];
unsigned int spill_offset = c-last_scratch;
assert(ALIGN(spill_offset, 16) == spill_offset); /* oword read/write req. */
- c-last_scratch += size * REG_SIZE;
int spill_base_mrf = dispatch_width 8 ? 13 : 14;
/* Spills may use MRFs 13-15 in the SIMD16 case. Our texturing is done
@@ -666,6 +663,8 @@ fs_visitor::spill_reg(int spill_reg)
spilled_any_registers = true;
}
+ c-last_scratch += size * reg_size;
+
/* Generate spill/unspill instructions for the objects being
* spilled. Right now, we spill or unspill the whole thing to a
* virtual grf of the same size. For most instructions, though, we
@@ -683,7 +682,7 @@ fs_visitor::spill_reg(int spill_reg)
inst-src[i].reg_offset = 0;
emit_unspill(inst, inst-src[i],
- spill_offset + REG_SIZE * inst-src[i].reg_offset,
+ spill_offset + reg_size * inst-src[i].reg_offset,
regs_read);
}
}
@@ -691,7 +690,7 @@ fs_visitor::spill_reg(int spill_reg)
if (inst-dst.file == GRF
inst-dst.reg == spill_reg) {
int subset_spill_offset = (spill_offset +
-REG_SIZE * inst-dst.reg_offset);
+reg_size * inst-dst.reg_offset);
inst-dst.reg = virtual_grf_alloc(inst-regs_written);
inst-dst.reg_offset = 0;
@@ -714,11 +713,11 @@ fs_visitor::spill_reg(int spill_reg)
fs_inst *spill_inst = new(mem_ctx) fs_inst(FS_OPCODE_SPILL,
reg_null_f, spill_src);
spill_src.reg_offset++;
- spill_inst-offset = subset_spill_offset + chan * REG_SIZE;
+ spill_inst-offset = subset_spill_offset + chan * reg_size;
spill_inst-ir = inst-ir;
spill_inst-annotation = inst-annotation;
- spill_inst-base_mrf
