Mesa (master): winsys/radeon: fix indentation
Module: Mesa
Branch: master
Commit: cce58147eb1450a26c03756af37da52d180580c4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cce58147eb1450a26c03756af37da52d180580c4
Author: Jerome Glisse jgli...@redhat.com
Date: Thu Jul 24 17:30:31 2014 -0400
winsys/radeon: fix indentation
Can we please keep it clean and avoid ending up in messy situation
like ddx.
Signed-off-by: Jérôme Glisse jgli...@redhat.com
---
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 58 -
1 file changed, 29 insertions(+), 29 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index 3596f8d..a06ecb2 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -155,7 +155,7 @@ static struct radeon_winsys_cs *
radeon_drm_cs_create(struct radeon_winsys *rws,
enum ring_type ring_type,
void (*flush)(void *ctx, unsigned flags,
- struct pipe_fence_handle **fence),
+ struct pipe_fence_handle **fence),
void *flush_ctx,
struct radeon_winsys_cs_handle *trace_buf)
{
@@ -196,10 +196,10 @@ radeon_drm_cs_create(struct radeon_winsys *rws,
#define OUT_CS(cs, value) (cs)-buf[(cs)-cdw++] = (value)
static INLINE void update_reloc(struct drm_radeon_cs_reloc *reloc,
- enum radeon_bo_domain rd,
- enum radeon_bo_domain wd,
- unsigned priority,
- enum radeon_bo_domain *added_domains)
+enum radeon_bo_domain rd,
+enum radeon_bo_domain wd,
+unsigned priority,
+enum radeon_bo_domain *added_domains)
{
*added_domains = (rd | wd) ~(reloc-read_domains | reloc-write_domain);
@@ -434,33 +434,33 @@ static void radeon_drm_cs_flush(struct radeon_winsys_cs
*rcs,
switch (cs-base.ring_type) {
case RING_DMA:
- /* pad DMA ring to 8 DWs */
- if (cs-ws-info.chip_class = SI) {
- while (rcs-cdw 7)
- OUT_CS(cs-base, 0xf000); /* NOP packet */
- } else {
- while (rcs-cdw 7)
- OUT_CS(cs-base, 0x); /* NOP packet */
- }
- break;
+/* pad DMA ring to 8 DWs */
+if (cs-ws-info.chip_class = SI) {
+while (rcs-cdw 7)
+OUT_CS(cs-base, 0xf000); /* NOP packet */
+} else {
+while (rcs-cdw 7)
+OUT_CS(cs-base, 0x); /* NOP packet */
+}
+break;
case RING_GFX:
- /* pad DMA ring to 8 DWs to meet CP fetch alignment requirements
-* r6xx, requires at least 4 dw alignment to avoid a hw bug.
-*/
- if (cs-ws-info.chip_class = SI) {
- while (rcs-cdw 7)
- OUT_CS(cs-base, 0x8000); /* type2 nop packet
*/
- } else {
- while (rcs-cdw 7)
- OUT_CS(cs-base, 0x1000); /* type3 nop packet
*/
- }
- break;
+/* pad DMA ring to 8 DWs to meet CP fetch alignment requirements
+ * r6xx, requires at least 4 dw alignment to avoid a hw bug.
+ */
+if (cs-ws-info.chip_class = SI) {
+while (rcs-cdw 7)
+OUT_CS(cs-base, 0x8000); /* type2 nop packet */
+} else {
+while (rcs-cdw 7)
+OUT_CS(cs-base, 0x1000); /* type3 nop packet */
+}
+break;
case RING_UVD:
-while (rcs-cdw 15)
- OUT_CS(cs-base, 0x8000); /* type2 nop packet */
- break;
+while (rcs-cdw 15)
+OUT_CS(cs-base, 0x8000); /* type2 nop packet */
+break;
default:
- break;
+break;
}
if (rcs-cdw RADEON_MAX_CMDBUF_DWORDS) {
___
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mesa-commit@lists.freedesktop.org
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Mesa (master): r600g: force full cache for hyperz
Module: Mesa Branch: master Commit: c7a13dc5f530783e2ec22af2e1d7206b4754da48 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c7a13dc5f530783e2ec22af2e1d7206b4754da48 Author: Jerome Glisse jgli...@redhat.com Date: Wed Apr 24 19:15:52 2013 -0400 r600g: force full cache for hyperz Seems that in some case allowing half cache usage confuse the gpu and trigger lockup. Force full cache use. Should fix : https://bugs.freedesktop.org/show_bug.cgi?id=59592 https://bugs.freedesktop.org/show_bug.cgi?id=60848 https://bugs.freedesktop.org/show_bug.cgi?id=60969 https://bugs.freedesktop.org/show_bug.cgi?id=61747 https://bugs.freedesktop.org/show_bug.cgi?id=62466 https://bugs.freedesktop.org/show_bug.cgi?id=62669 https://bugs.freedesktop.org/show_bug.cgi?id=62721 https://bugs.freedesktop.org/show_bug.cgi?id=63124 Signed-off-by: Jerome Glisse jgli...@redhat.com --- src/gallium/drivers/r600/evergreen_state.c |1 + src/gallium/drivers/r600/r600_state.c |1 + 2 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 13f0678..6797b22 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -1691,6 +1691,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx, surf-db_htile_data_base = va 8; surf-db_htile_surface = S_028ABC_HTILE_WIDTH(1) | S_028ABC_HTILE_HEIGHT(1) | + S_028ABC_FULL_CACHE(1) | S_028ABC_LINEAR(1); surf-db_depth_info |= S_028040_TILE_SURFACE_ENABLE(1); surf-db_preload_control = 0; diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index b054fef..4e0e4a6 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -1532,6 +1532,7 @@ static void r600_init_depth_surface(struct r600_context *rctx, surf-db_htile_data_base = va 8; surf-db_htile_surface = S_028D24_HTILE_WIDTH(1) | S_028D24_HTILE_HEIGHT(1) | + S_028D24_FULL_CACHE(1) | S_028D24_LINEAR(1); /* preload is not working properly on r6xx/r7xx */ surf-db_depth_info |= S_028010_TILE_SURFACE_ENABLE(1); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): winsys/radeon: consolidate tracing into winsys v2
Module: Mesa
Branch: master
Commit: abb96fdea70546f974ba59cbd00bc54afee9cfdb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=abb96fdea70546f974ba59cbd00bc54afee9cfdb
Author: Jerome Glisse jgli...@redhat.com
Date: Tue Apr 23 19:22:33 2013 -0400
winsys/radeon: consolidate tracing into winsys v2
This move the tracing timeout and printing into winsys and add
an debug environement variable for it (R600_DEBUG=trace_cs).
Lot of file touched because of winsys API changes.
v2: Do not write lockup file if ib uniq id does not match last one
Signed-off-by: Jerome Glisse jgli...@redhat.com
Reviewed-by: Marek Olšák mar...@gmail.com
---
src/gallium/drivers/r300/r300_context.c|2 +-
src/gallium/drivers/r300/r300_flush.c |6 ++--
src/gallium/drivers/r600/evergreen_compute.c |2 +-
src/gallium/drivers/r600/r600_hw_context.c | 36 +---
src/gallium/drivers/r600/r600_pipe.c | 17 +
src/gallium/drivers/r600/r600_pipe.h | 11 +-
src/gallium/drivers/r600/r600_state_common.c |4 --
src/gallium/drivers/radeon/radeon_uvd.c|4 +-
src/gallium/drivers/radeonsi/r600_hw_context.c |2 +-
src/gallium/drivers/radeonsi/radeonsi_compute.c|2 +-
src/gallium/drivers/radeonsi/radeonsi_pipe.c |2 +-
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 19 ++
src/gallium/winsys/radeon/drm/radeon_drm_cs.h | 11 +++---
src/gallium/winsys/radeon/drm/radeon_drm_cs_dump.c | 30 ++--
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c |2 +-
src/gallium/winsys/radeon/drm/radeon_winsys.h | 13 +--
16 files changed, 68 insertions(+), 95 deletions(-)
diff --git a/src/gallium/drivers/r300/r300_context.c
b/src/gallium/drivers/r300/r300_context.c
index 340a7f0..ba1859b 100644
--- a/src/gallium/drivers/r300/r300_context.c
+++ b/src/gallium/drivers/r300/r300_context.c
@@ -379,7 +379,7 @@ struct pipe_context* r300_create_context(struct
pipe_screen* screen,
sizeof(struct pipe_transfer), 64,
UTIL_SLAB_SINGLETHREADED);
-r300-cs = rws-cs_create(rws, RING_GFX);
+r300-cs = rws-cs_create(rws, RING_GFX, NULL);
if (r300-cs == NULL)
goto fail;
diff --git a/src/gallium/drivers/r300/r300_flush.c
b/src/gallium/drivers/r300/r300_flush.c
index 10c4a30..709fe52 100644
--- a/src/gallium/drivers/r300/r300_flush.c
+++ b/src/gallium/drivers/r300/r300_flush.c
@@ -52,7 +52,7 @@ static void r300_flush_and_cleanup(struct r300_context *r300,
unsigned flags)
}
r300-flush_counter++;
-r300-rws-cs_flush(r300-cs, flags);
+r300-rws-cs_flush(r300-cs, flags, 0);
r300-dirty_hw = 0;
/* New kitchen sink, baby. */
@@ -100,11 +100,11 @@ void r300_flush(struct pipe_context *pipe,
* and we cannot emit an empty CS. Let's write to some reg. */
CS_LOCALS(r300);
OUT_CS_REG(RB3D_COLOR_CHANNEL_MASK, 0);
-r300-rws-cs_flush(r300-cs, flags);
+r300-rws-cs_flush(r300-cs, flags, 0);
} else {
/* Even if hw is not dirty, we should at least reset the CS in case
* the space checking failed for the first draw operation. */
-r300-rws-cs_flush(r300-cs, flags);
+r300-rws-cs_flush(r300-cs, flags, 0);
}
}
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index 489629f..d6b0a47 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -463,7 +463,7 @@ static void compute_emit_cs(struct r600_context *ctx, const
uint *block_layout,
flush_flags |= RADEON_FLUSH_KEEP_TILING_FLAGS;
}
- ctx-ws-cs_flush(ctx-rings.gfx.cs, flush_flags);
+ ctx-ws-cs_flush(ctx-rings.gfx.cs, flush_flags,
ctx-screen-cs_count++);
ctx-flags = 0;
diff --git a/src/gallium/drivers/r600/r600_hw_context.c
b/src/gallium/drivers/r600/r600_hw_context.c
index b4fb3bf..3abce1e 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -137,21 +137,17 @@ void r600_need_cs_space(struct r600_context *ctx,
unsigned num_dw,
for (i = 0; i R600_NUM_ATOMS; i++) {
if (ctx-atoms[i] ctx-atoms[i]-dirty) {
num_dw += ctx-atoms[i]-num_dw;
-#if R600_TRACE_CS
if (ctx-screen-trace_bo) {
num_dw += R600_TRACE_CS_DWORDS;
}
-#endif
}
}
/* The upper-bound of how much space a draw command would take.
*/
num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
-#if R600_TRACE_CS
if (ctx-screen-trace_bo) {
num_dw
Mesa (master): radeonsi: add support for compressed texture v2
Module: Mesa
Branch: master
Commit: d0e9aaa31cb13404914aea292879739d4044f856
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d0e9aaa31cb13404914aea292879739d4044f856
Author: Jerome Glisse jgli...@redhat.com
Date: Mon Apr 8 10:57:05 2013 -0400
radeonsi: add support for compressed texture v2
Most test pass, issue are with border color and swizzle.
Based on ircnickmaelcum patch.
v2: Restaged commit hunk
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/radeonsi/si_state.c | 71 ++-
src/gallium/drivers/radeonsi/sid.h |7 +++
2 files changed, 76 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 61ede64..a39843c 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -30,6 +30,7 @@
#include util/u_helpers.h
#include util/u_math.h
#include util/u_pack_color.h
+#include util/u_format_s3tc.h
#include tgsi/tgsi_parse.h
#include radeonsi_pipe.h
#include radeonsi_shader.h
@@ -1164,6 +1165,8 @@ static uint32_t si_translate_texformat(struct pipe_screen
*screen,
const struct util_format_description
*desc,
int first_non_void)
{
+ struct r600_screen *rscreen = (struct r600_screen*)screen;
+ bool enable_s3tc = rscreen-info.drm_minor = 31;
boolean uniform = TRUE;
int i;
@@ -1205,7 +1208,51 @@ static uint32_t si_translate_texformat(struct
pipe_screen *screen,
break;
}
- /* TODO compressed formats */
+ if (desc-layout == UTIL_FORMAT_LAYOUT_RGTC) {
+ if (!enable_s3tc)
+ goto out_unknown;
+
+ switch (format) {
+ case PIPE_FORMAT_RGTC1_SNORM:
+ case PIPE_FORMAT_LATC1_SNORM:
+ case PIPE_FORMAT_RGTC1_UNORM:
+ case PIPE_FORMAT_LATC1_UNORM:
+ return V_008F14_IMG_DATA_FORMAT_BC4;
+ case PIPE_FORMAT_RGTC2_SNORM:
+ case PIPE_FORMAT_LATC2_SNORM:
+ case PIPE_FORMAT_RGTC2_UNORM:
+ case PIPE_FORMAT_LATC2_UNORM:
+ return V_008F14_IMG_DATA_FORMAT_BC5;
+ default:
+ goto out_unknown;
+ }
+ }
+
+ if (desc-layout == UTIL_FORMAT_LAYOUT_S3TC) {
+
+ if (!enable_s3tc)
+ goto out_unknown;
+
+ if (!util_format_s3tc_enabled) {
+ goto out_unknown;
+ }
+
+ switch (format) {
+ case PIPE_FORMAT_DXT1_RGB:
+ case PIPE_FORMAT_DXT1_RGBA:
+ case PIPE_FORMAT_DXT1_SRGB:
+ case PIPE_FORMAT_DXT1_SRGBA:
+ return V_008F14_IMG_DATA_FORMAT_BC1;
+ case PIPE_FORMAT_DXT3_RGBA:
+ case PIPE_FORMAT_DXT3_SRGBA:
+ return V_008F14_IMG_DATA_FORMAT_BC2;
+ case PIPE_FORMAT_DXT5_RGBA:
+ case PIPE_FORMAT_DXT5_SRGBA:
+ return V_008F14_IMG_DATA_FORMAT_BC3;
+ default:
+ goto out_unknown;
+ }
+ }
if (format == PIPE_FORMAT_R9G9B9E5_FLOAT) {
return V_008F14_IMG_DATA_FORMAT_5_9_9_9;
@@ -2109,7 +2156,27 @@ static struct pipe_sampler_view
*si_create_sampler_view(struct pipe_context *ctx
break;
default:
if (first_non_void 0) {
- num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
+ if (util_format_is_compressed(pipe_format)) {
+ switch (pipe_format) {
+ case PIPE_FORMAT_DXT1_SRGB:
+ case PIPE_FORMAT_DXT1_SRGBA:
+ case PIPE_FORMAT_DXT3_SRGBA:
+ case PIPE_FORMAT_DXT5_SRGBA:
+ num_format =
V_008F14_IMG_NUM_FORMAT_SRGB;
+ break;
+ case PIPE_FORMAT_RGTC1_SNORM:
+ case PIPE_FORMAT_LATC1_SNORM:
+ case PIPE_FORMAT_RGTC2_SNORM:
+ case PIPE_FORMAT_LATC2_SNORM:
+ num_format =
V_008F14_IMG_NUM_FORMAT_SNORM;
+ break;
+ default:
+ num_format =
V_008F14_IMG_NUM_FORMAT_UNORM;
+ break;
+ }
+ } else {
+ num_format = V_008F14_IMG_NUM_FORMAT_FLOAT;
+ }
} else if (desc-colorspace == UTIL_FORMAT_COLORSPACE_SRGB
Mesa (master): radeonsi: add 2d tiling support for texture v3
Module: Mesa
Branch: master
Commit: dc21e30a6283629bed6db282caff0af13f3b88ec
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc21e30a6283629bed6db282caff0af13f3b88ec
Author: Jerome Glisse jgli...@redhat.com
Date: Fri Mar 22 17:55:49 2013 -0400
radeonsi: add 2d tiling support for texture v3
v2: Remove left over code
v3: Restage properly the commit so hunk of first one are not in
second one.
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
configure.ac|2 +-
src/gallium/drivers/radeonsi/r600_texture.c | 11 +++-
src/gallium/drivers/radeonsi/si_state.c | 79 ---
3 files changed, 20 insertions(+), 72 deletions(-)
diff --git a/configure.ac b/configure.ac
index 70c598e..6ffe3f2 100644
--- a/configure.ac
+++ b/configure.ac
@@ -31,7 +31,7 @@ AC_SUBST([OSMESA_VERSION])
dnl Versions for external dependencies
LIBDRM_REQUIRED=2.4.24
-LIBDRM_RADEON_REQUIRED=2.4.42
+LIBDRM_RADEON_REQUIRED=2.4.44
LIBDRM_INTEL_REQUIRED=2.4.38
LIBDRM_NVVIEUX_REQUIRED=2.4.33
LIBDRM_NOUVEAU_REQUIRED=2.4.33 libdrm = 2.4.41
diff --git a/src/gallium/drivers/radeonsi/r600_texture.c
b/src/gallium/drivers/radeonsi/r600_texture.c
index 1b8382f..8992f9a 100644
--- a/src/gallium/drivers/radeonsi/r600_texture.c
+++ b/src/gallium/drivers/radeonsi/r600_texture.c
@@ -47,7 +47,6 @@ static void r600_copy_to_staging_texture(struct pipe_context
*ctx, struct r600_t
transfer-box);
}
-
/* Copy from a transfer's staging texture to a full GPU one. */
static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct
r600_transfer *rtransfer)
{
@@ -152,12 +151,12 @@ static int r600_init_surface(struct r600_screen *rscreen,
if (!is_flushed_depth is_depth) {
surface-flags |= RADEON_SURF_ZBUFFER;
-
if (is_stencil) {
surface-flags |= RADEON_SURF_SBUFFER |
RADEON_SURF_HAS_SBUFFER_MIPTREE;
}
}
+ surface-flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
return 0;
}
@@ -530,7 +529,11 @@ struct pipe_resource *si_texture_create(struct pipe_screen
*screen,
if (!(templ-flags R600_RESOURCE_FLAG_TRANSFER)
!(templ-bind PIPE_BIND_SCANOUT)) {
- array_mode = V_009910_ARRAY_1D_TILED_THIN1;
+ if (util_format_is_compressed(templ-format)) {
+ array_mode = V_009910_ARRAY_1D_TILED_THIN1;
+ } else {
+ array_mode = V_009910_ARRAY_2D_TILED_THIN1;
+ }
}
r = r600_init_surface(rscreen, surface, templ, array_mode,
@@ -620,6 +623,8 @@ struct pipe_resource *si_texture_from_handle(struct
pipe_screen *screen,
if (r) {
return NULL;
}
+ /* always set the scanout flags */
+ surface.flags |= RADEON_SURF_SCANOUT;
return (struct pipe_resource *)r600_texture_create_object(screen,
templ, array_mode,
stride, 0,
buf, FALSE, surface);
}
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index ca9e8b4..61ede64 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1541,67 +1541,16 @@ boolean si_is_format_supported(struct pipe_screen
*screen,
return retval == usage;
}
-static unsigned si_tile_mode_index(struct r600_resource_texture *rtex,
unsigned level)
-{
- if (util_format_is_depth_or_stencil(rtex-real_format)) {
- if (rtex-surface.level[level].mode == RADEON_SURF_MODE_1D) {
- return 4;
- } else if (rtex-surface.level[level].mode ==
RADEON_SURF_MODE_2D) {
- switch (rtex-real_format) {
- case PIPE_FORMAT_Z16_UNORM:
- return 5;
- case PIPE_FORMAT_S8_UINT_Z24_UNORM:
- case PIPE_FORMAT_X8Z24_UNORM:
- case PIPE_FORMAT_Z24X8_UNORM:
- case PIPE_FORMAT_Z24_UNORM_S8_UINT:
- case PIPE_FORMAT_Z32_FLOAT:
- case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT:
- return 6;
- default:
- return 7;
- }
- }
- }
+static unsigned si_tile_mode_index(struct r600_resource_texture *rtex,
unsigned level, bool stencil)
+{
+ unsigned tile_mode_index = 0;
- switch (rtex-surface.level[level].mode) {
- default:
- assert(!Invalid surface mode);
- /* Fall through */
- case RADEON_SURF_MODE_LINEAR_ALIGNED:
- return 8;
- case RADEON_SURF_MODE_1D:
- if (rtex-surface.flags RADEON_SURF_SCANOUT)
- return 9;
- else
Mesa (master): winsys/radeon: add command stream replay dump for faulty lockup v3
Module: Mesa
Branch: master
Commit: b8998f976ee11e5bdffa78cd78278deeed2789c1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b8998f976ee11e5bdffa78cd78278deeed2789c1
Author: Jerome Glisse jgli...@redhat.com
Date: Wed Mar 27 11:04:29 2013 -0400
winsys/radeon: add command stream replay dump for faulty lockup v3
Build time option, set RADEON_CS_DUMP_ON_LOCKUP to 1 in radeon_drm_cs.h to
enable it.
When enabled after each cs submission the code will try to detect lockup by
waiting on one of the buffer of the cs to become idle, after a timeout it
will consider that the cs triggered a lockup and will write a radeon_lockup.c
file in current directory that have all information for replaying the cs.
To build this file :
gcc -O0 -g radeon_lockup.c -ldrm -o radeon_lockup -I/usr/include/libdrm
v2: Add radeon_ctx.h file to mesa git tree
v3: Slightly improve dumped file for easier editing, only dump first faulty cs
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/winsys/radeon/drm/Makefile.sources |1 +
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 80 ---
src/gallium/winsys/radeon/drm/radeon_drm_bo.h |2 +
src/gallium/winsys/radeon/drm/radeon_drm_cs.c |4 +
src/gallium/winsys/radeon/drm/radeon_drm_cs.h |6 +
src/gallium/winsys/radeon/drm/radeon_drm_cs_dump.c | 152 +
src/gallium/winsys/radeon/tools/radeon_ctx.h | 235
7 files changed, 443 insertions(+), 37 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/Makefile.sources
b/src/gallium/winsys/radeon/drm/Makefile.sources
index 1d18d61..4ca5ebb 100644
--- a/src/gallium/winsys/radeon/drm/Makefile.sources
+++ b/src/gallium/winsys/radeon/drm/Makefile.sources
@@ -1,4 +1,5 @@
C_SOURCES := \
radeon_drm_bo.c \
radeon_drm_cs.c \
+ radeon_drm_cs_dump.c \
radeon_drm_winsys.c
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 61570d0..9e45dcc 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -396,14 +396,54 @@ static void radeon_bo_destroy(struct pb_buffer *_buf)
FREE(bo);
}
+void *radeon_bo_do_map(struct radeon_bo *bo)
+{
+struct drm_radeon_gem_mmap args = {0};
+void *ptr;
+
+/* Return the pointer if it's already mapped. */
+if (bo-ptr)
+return bo-ptr;
+
+/* Map the buffer. */
+pipe_mutex_lock(bo-map_mutex);
+/* Return the pointer if it's already mapped (in case of a race). */
+if (bo-ptr) {
+pipe_mutex_unlock(bo-map_mutex);
+return bo-ptr;
+}
+args.handle = bo-handle;
+args.offset = 0;
+args.size = (uint64_t)bo-base.size;
+if (drmCommandWriteRead(bo-rws-fd,
+DRM_RADEON_GEM_MMAP,
+args,
+sizeof(args))) {
+pipe_mutex_unlock(bo-map_mutex);
+fprintf(stderr, radeon: gem_mmap failed: %p 0x%08X\n,
+bo, bo-handle);
+return NULL;
+}
+
+ptr = os_mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED,
+ bo-rws-fd, args.addr_ptr);
+if (ptr == MAP_FAILED) {
+pipe_mutex_unlock(bo-map_mutex);
+fprintf(stderr, radeon: mmap failed, errno: %i\n, errno);
+return NULL;
+}
+bo-ptr = ptr;
+pipe_mutex_unlock(bo-map_mutex);
+
+return bo-ptr;
+}
+
static void *radeon_bo_map(struct radeon_winsys_cs_handle *buf,
struct radeon_winsys_cs *rcs,
enum pipe_transfer_usage usage)
{
struct radeon_bo *bo = (struct radeon_bo*)buf;
struct radeon_drm_cs *cs = (struct radeon_drm_cs*)rcs;
-struct drm_radeon_gem_mmap args = {0};
-void *ptr;
/* If it's not unsynchronized bo_map, flush CS if needed and then wait. */
if (!(usage PIPE_TRANSFER_UNSYNCHRONIZED)) {
@@ -466,41 +506,7 @@ static void *radeon_bo_map(struct radeon_winsys_cs_handle
*buf,
}
}
-/* Return the pointer if it's already mapped. */
-if (bo-ptr)
-return bo-ptr;
-
-/* Map the buffer. */
-pipe_mutex_lock(bo-map_mutex);
-/* Return the pointer if it's already mapped (in case of a race). */
-if (bo-ptr) {
-pipe_mutex_unlock(bo-map_mutex);
-return bo-ptr;
-}
-args.handle = bo-handle;
-args.offset = 0;
-args.size = (uint64_t)bo-base.size;
-if (drmCommandWriteRead(bo-rws-fd,
-DRM_RADEON_GEM_MMAP,
-args,
-sizeof(args))) {
-pipe_mutex_unlock(bo-map_mutex);
-fprintf(stderr, radeon: gem_mmap failed: %p 0x%08X\n,
-bo, bo-handle);
-return NULL;
-}
-
-ptr = os_mmap(0, args.size, PROT_READ|PROT_WRITE, MAP_SHARED,
- bo-rws-fd, args.addr_ptr);
-if (ptr == MAP_FAILED) {
-pipe_mutex_unlock(bo
Mesa (master): r600g: workaround hyperz lockup on evergreen
Module: Mesa
Branch: master
Commit: 6bc7605745d53df94398b724b66db74d23d09e03
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6bc7605745d53df94398b724b66db74d23d09e03
Author: Jerome Glisse jgli...@redhat.com
Date: Wed Feb 20 16:20:17 2013 -0500
r600g: workaround hyperz lockup on evergreen
This work around disable hyperz if write to zbuffer is disabled. Somehow
using hyperz when not writting to the zbuffer trigger GPU lockup. See :
https://bugs.freedesktop.org/show_bug.cgi?id=60848
Candidate for 9.1
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_state.c | 10 +-
src/gallium/drivers/r600/r600_pipe.h |4 +++-
src/gallium/drivers/r600/r600_state.c|1 +
src/gallium/drivers/r600/r600_state_common.c | 10 ++
4 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 4a91942..2e301bc 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -858,6 +858,7 @@ static void *evergreen_create_dsa_state(struct pipe_context
*ctx,
dsa-valuemask[1] = state-stencil[1].valuemask;
dsa-writemask[0] = state-stencil[0].writemask;
dsa-writemask[1] = state-stencil[1].writemask;
+ dsa-zwritemask = state-depth.writemask;
db_depth_control = S_028800_Z_ENABLE(state-depth.enabled) |
S_028800_Z_WRITE_ENABLE(state-depth.writemask) |
@@ -2286,7 +2287,14 @@ static void evergreen_emit_db_misc_state(struct
r600_context *rctx, struct r600_
}
db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
}
- if (rctx-db_state.rsurf rctx-db_state.rsurf-htile_enabled) {
+ /* FIXME we should be able to use hyperz even if we are not writing to
+* zbuffer but somehow this trigger GPU lockup. See :
+*
+* https://bugs.freedesktop.org/show_bug.cgi?id=60848
+*
+* Disable hyperz for now if not writing to zbuffer.
+*/
+ if (rctx-db_state.rsurf rctx-db_state.rsurf-htile_enabled
rctx-zwritemask) {
/* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL
*/
db_render_override |=
S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
/* This is to fix a lockup when hyperz and alpha test are
enabled at
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index 88b587e..1d0ad79 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -298,7 +298,8 @@ struct r600_dsa_state {
unsignedalpha_ref;
ubyte valuemask[2];
ubyte writemask[2];
- unsignedsx_alpha_test_control;
+ unsignedzwritemask;
+ unsignedsx_alpha_test_control;
};
struct r600_pipe_shader;
@@ -513,6 +514,7 @@ struct r600_context {
boolalpha_to_one;
boolforce_blend_disable;
boolean dual_src_blend;
+ unsignedzwritemask;
/* Index buffer. */
struct pipe_index_bufferindex_buffer;
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index c6559bb..2d3ec93 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -842,6 +842,7 @@ static void *r600_create_dsa_state(struct pipe_context *ctx,
dsa-valuemask[1] = state-stencil[1].valuemask;
dsa-writemask[0] = state-stencil[0].writemask;
dsa-writemask[1] = state-stencil[1].writemask;
+ dsa-zwritemask = state-depth.writemask;
db_depth_control = S_028800_Z_ENABLE(state-depth.enabled) |
S_028800_Z_WRITE_ENABLE(state-depth.writemask) |
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index 1654233..fae28bc 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -284,6 +284,16 @@ static void r600_bind_dsa_state(struct pipe_context *ctx,
void *state)
ref.valuemask[1] = dsa-valuemask[1];
ref.writemask[0] = dsa-writemask[0];
ref.writemask[1] = dsa-writemask[1];
+ if (rctx-zwritemask != dsa-zwritemask) {
+ rctx-zwritemask = dsa-zwritemask;
+ if (rctx-chip_class = EVERGREEN) {
+ /* work around some issue when not writting to zbuffer
+* we are having lockup on evergreen so do not enable
+* hyperz when not writting zbuffer
+*/
+ rctx-db_misc_state.atom.dirty = true
Mesa (9.1): r600g: workaround hyperz lockup on evergreen
Module: Mesa
Branch: 9.1
Commit: b199a6414d02e271847cb556cc5f789b4b057105
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b199a6414d02e271847cb556cc5f789b4b057105
Author: Jerome Glisse jgli...@redhat.com
Date: Wed Feb 20 16:20:17 2013 -0500
r600g: workaround hyperz lockup on evergreen
This work around disable hyperz if write to zbuffer is disabled. Somehow
using hyperz when not writting to the zbuffer trigger GPU lockup. See :
https://bugs.freedesktop.org/show_bug.cgi?id=60848
Candidate for 9.1
Signed-off-by: Jerome Glisse jgli...@redhat.com
(cherry picked from commit 6bc7605745d53df94398b724b66db74d23d09e03)
---
src/gallium/drivers/r600/evergreen_state.c | 10 +-
src/gallium/drivers/r600/r600_pipe.h |4 +++-
src/gallium/drivers/r600/r600_state.c|1 +
src/gallium/drivers/r600/r600_state_common.c | 10 ++
4 files changed, 23 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 389ad3c..a982317 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -808,6 +808,7 @@ static void *evergreen_create_dsa_state(struct pipe_context
*ctx,
dsa-valuemask[1] = state-stencil[1].valuemask;
dsa-writemask[0] = state-stencil[0].writemask;
dsa-writemask[1] = state-stencil[1].writemask;
+ dsa-zwritemask = state-depth.writemask;
db_depth_control = S_028800_Z_ENABLE(state-depth.enabled) |
S_028800_Z_WRITE_ENABLE(state-depth.writemask) |
@@ -,7 +2223,14 @@ static void evergreen_emit_db_misc_state(struct
r600_context *rctx, struct r600_
}
db_render_override |= S_02800C_NOOP_CULL_DISABLE(1);
}
- if (rctx-db_state.rsurf rctx-db_state.rsurf-htile_enabled) {
+ /* FIXME we should be able to use hyperz even if we are not writing to
+* zbuffer but somehow this trigger GPU lockup. See :
+*
+* https://bugs.freedesktop.org/show_bug.cgi?id=60848
+*
+* Disable hyperz for now if not writing to zbuffer.
+*/
+ if (rctx-db_state.rsurf rctx-db_state.rsurf-htile_enabled
rctx-zwritemask) {
/* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL
*/
db_render_override |=
S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
/* This is to fix a lockup when hyperz and alpha test are
enabled at
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index ec59c92..1be4321 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -298,7 +298,8 @@ struct r600_dsa_state {
unsignedalpha_ref;
ubyte valuemask[2];
ubyte writemask[2];
- unsignedsx_alpha_test_control;
+ unsignedzwritemask;
+ unsignedsx_alpha_test_control;
};
struct r600_pipe_shader;
@@ -513,6 +514,7 @@ struct r600_context {
boolalpha_to_one;
boolforce_blend_disable;
boolean dual_src_blend;
+ unsignedzwritemask;
/* Index buffer. */
struct pipe_index_bufferindex_buffer;
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 3f165f7..314c9ae 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -802,6 +802,7 @@ static void *r600_create_dsa_state(struct pipe_context *ctx,
dsa-valuemask[1] = state-stencil[1].valuemask;
dsa-writemask[0] = state-stencil[0].writemask;
dsa-writemask[1] = state-stencil[1].writemask;
+ dsa-zwritemask = state-depth.writemask;
db_depth_control = S_028800_Z_ENABLE(state-depth.enabled) |
S_028800_Z_WRITE_ENABLE(state-depth.writemask) |
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index 88bb62b..35d26b3 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -284,6 +284,16 @@ static void r600_bind_dsa_state(struct pipe_context *ctx,
void *state)
ref.valuemask[1] = dsa-valuemask[1];
ref.writemask[0] = dsa-writemask[0];
ref.writemask[1] = dsa-writemask[1];
+ if (rctx-zwritemask != dsa-zwritemask) {
+ rctx-zwritemask = dsa-zwritemask;
+ if (rctx-chip_class = EVERGREEN) {
+ /* work around some issue when not writting to zbuffer
+* we are having lockup on evergreen so do not enable
+* hyperz when not writting zbuffer
Mesa (9.1): r600g: fix lockup when hyperz alpha test are enabled together . v3
Module: Mesa
Branch: 9.1
Commit: 3ae8678f81ac65503595447763cb8447781155ba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3ae8678f81ac65503595447763cb8447781155ba
Author: Jerome Glisse jgli...@redhat.com
Date: Fri Feb 8 16:02:32 2013 -0500
r600g: fix lockup when hyperz alpha test are enabled together. v3
Seems that alpha test being enabled confuse the GPU on the order in
which it should perform the Z testing. So force the order programmed
throught db shader control.
v2: Only force z order when alpha test is enabled
v3: Update db shader when binding new dsa + spelling fix
Signed-off-by: Jerome Glisse jgli...@redhat.com
Reviewed-by: Marek Olšák mar...@gmail.com
(cherry picked from commit 974b482acaf62ced1e8981761a8bda252bd51fe1)
---
src/gallium/drivers/r600/evergreen_state.c | 25 +++--
src/gallium/drivers/r600/r600_state.c| 22 +-
src/gallium/drivers/r600/r600_state_common.c |5 +
3 files changed, 49 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index ad2f731..c39827f 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2225,6 +2225,13 @@ static void evergreen_emit_db_misc_state(struct
r600_context *rctx, struct r600_
if (rctx-db_state.rsurf rctx-db_state.rsurf-htile_enabled) {
/* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL
*/
db_render_override |=
S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_OFF);
+ /* This is to fix a lockup when hyperz and alpha test are
enabled at
+* the same time somehow GPU get confuse on which order to pick
for
+* z test
+*/
+ if (rctx-alphatest_state.sx_alpha_test_control) {
+ db_render_override |= S_02800C_FORCE_SHADER_Z_ORDER(1);
+ }
} else {
db_render_override |=
S_02800C_FORCE_HIZ_ENABLE(V_02800C_FORCE_DISABLE);
}
@@ -3214,7 +3221,7 @@ void evergreen_pipe_shader_ps(struct pipe_context *ctx,
struct r600_pipe_shader
struct r600_context *rctx = (struct r600_context *)ctx;
struct r600_pipe_state *rstate = shader-rstate;
struct r600_shader *rshader = shader-shader;
- unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z,
spi_ps_in_control_1, db_shader_control;
+ unsigned i, exports_ps, num_cout, spi_ps_in_control_0, spi_input_z,
spi_ps_in_control_1, db_shader_control = 0;
int pos_index = -1, face_index = -1;
int ninterp = 0;
boolean have_linear = FALSE, have_centroid = FALSE, have_perspective =
FALSE;
@@ -3224,7 +3231,6 @@ void evergreen_pipe_shader_ps(struct pipe_context *ctx,
struct r600_pipe_shader
rstate-nregs = 0;
- db_shader_control = S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
for (i = 0; i rshader-ninput; i++) {
/* evergreen NUM_INTERP only contains values interpolated into
the LDS,
POSITION goes via GPRs from the SC so isn't counted */
@@ -3458,6 +3464,21 @@ void evergreen_update_db_shader_control(struct
r600_context * rctx)
V_02880C_EXPORT_DB_FULL) |
S_02880C_ALPHA_TO_MASK_DISABLE(rctx-framebuffer.cb0_is_integer);
+ /* When alpha test is enabled we can't trust the hw to make the proper
+* decision on the order in which ztest should be run related to
fragment
+* shader execution.
+*
+* If alpha test is enabled perform early z rejection (RE_Z) but don't
early
+* write to the zbuffer. Write to zbuffer is delayed after fragment
shader
+* execution and thus after alpha test so if discarded by the alpha test
+* the z value is not written.
+*/
+ if (rctx-alphatest_state.sx_alpha_test_control) {
+ db_shader_control |= S_02880C_Z_ORDER(V_02880C_RE_Z);
+ } else {
+ db_shader_control |=
S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
+ }
+
if (db_shader_control != rctx-db_misc_state.db_shader_control) {
rctx-db_misc_state.db_shader_control = db_shader_control;
rctx-db_misc_state.atom.dirty = true;
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 1f50ed6..3f165f7 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -1940,6 +1940,13 @@ static void r600_emit_db_misc_state(struct r600_context
*rctx, struct r600_atom
if (rctx-db_state.rsurf rctx-db_state.rsurf-htile_enabled) {
/* FORCE_OFF means HiZ/HiS are determined by DB_SHADER_CONTROL
*/
db_render_override |=
S_028D10_FORCE_HIZ_ENABLE(V_028D10_FORCE_OFF
Mesa (master): winsys/radeon: fix bo with virtual address referencing mismatch
Module: Mesa Branch: master Commit: a37835c8eda017f0c955e0927e7418e7f3ba3b73 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=a37835c8eda017f0c955e0927e7418e7f3ba3b73 Author: Martin Andersson g02ma...@gmail.com Date: Sat Feb 2 17:55:07 2013 +0100 winsys/radeon: fix bo with virtual address referencing mismatch If the same context try to flink and open the object, use the same bo struct instead of opening a new gem handle for the object. This way we avoid avoid having 2 different handle pointing to the same kernel object which can latter lead to trouble with virtual address. Fix: https://bugs.freedesktop.org/show_bug.cgi?id=60200 Signed-off-by: Martin Andersson g02ma...@gmail.com Reviewed-by: Jerome Glisse jgli...@redhat.com --- src/gallium/winsys/radeon/drm/radeon_drm_bo.c |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c index bb6e954..2d41c26 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c @@ -963,6 +963,10 @@ static boolean radeon_winsys_bo_get_handle(struct pb_buffer *buffer, whandle-handle = bo-handle; } +pipe_mutex_lock(bo-mgr-bo_handles_mutex); +util_hash_table_set(bo-mgr-bo_handles, (void*)(uintptr_t)whandle-handle, bo); +pipe_mutex_unlock(bo-mgr-bo_handles_mutex); + whandle-stride = stride; return TRUE; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (9.1): winsys/radeon: fix bo with virtual address referencing mismatch
Module: Mesa Branch: 9.1 Commit: 3b609f12f691717f297e8cbb5193edfc09670a6c URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b609f12f691717f297e8cbb5193edfc09670a6c Author: Martin Andersson g02ma...@gmail.com Date: Sat Feb 2 17:55:07 2013 +0100 winsys/radeon: fix bo with virtual address referencing mismatch If the same context try to flink and open the object, use the same bo struct instead of opening a new gem handle for the object. This way we avoid avoid having 2 different handle pointing to the same kernel object which can latter lead to trouble with virtual address. Fix: https://bugs.freedesktop.org/show_bug.cgi?id=60200 Signed-off-by: Martin Andersson g02ma...@gmail.com Reviewed-by: Jerome Glisse jgli...@redhat.com (cherry picked from commit a37835c8eda017f0c955e0927e7418e7f3ba3b73) --- src/gallium/winsys/radeon/drm/radeon_drm_bo.c |4 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c index bb6e954..2d41c26 100644 --- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c +++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c @@ -963,6 +963,10 @@ static boolean radeon_winsys_bo_get_handle(struct pb_buffer *buffer, whandle-handle = bo-handle; } +pipe_mutex_lock(bo-mgr-bo_handles_mutex); +util_hash_table_set(bo-mgr-bo_handles, (void*)(uintptr_t)whandle-handle, bo); +pipe_mutex_unlock(bo-mgr-bo_handles_mutex); + whandle-stride = stride; return TRUE; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: make sure async blit is done 8 * pitch at a time v2
Module: Mesa
Branch: master
Commit: 323a4488250f8f4e9981623b795763b86f5cae3f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=323a4488250f8f4e9981623b795763b86f5cae3f
Author: Jerome Glisse jgli...@redhat.com
Date: Wed Feb 6 15:03:17 2013 -0500
r600g: make sure async blit is done 8 * pitch at a time v2
The blit must be aligned on 8 horizontal block.
v2: no need to align the reminder
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/r600_state.c | 13 +++--
1 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 67c4d99..5322850 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -3068,14 +3068,15 @@ static boolean r600_dma_copy_tile(struct r600_context
*rctx,
return FALSE;
}
- size = (copy_height * pitch) 2;
- ncopy = (size / 0x) + !!(size % 0x);
+ /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for
number
+* line in the blit. Compute max 8 line we can copy in the size limit
+*/
+ cheight = ((0x 2) / pitch) 0xfff8;
+ ncopy = (copy_height / cheight) + !!(copy_height % cheight);
r600_need_dma_space(rctx, ncopy * 7);
+
for (i = 0; i ncopy; i++) {
- cheight = copy_height;
- if (((cheight * pitch) 2) 0x) {
- cheight = (0x 2) / pitch;
- }
+ cheight = cheight copy_height ? copy_height : cheight;
size = (cheight * pitch) 2;
/* emit reloc before writting cs so that cs is always in
consistent state */
r600_context_bo_reloc(rctx, rctx-rings.dma, rsrc-resource,
RADEON_USAGE_READ);
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Mesa (9.1): r600g: make sure async blit is done 8 * pitch at a time v2
Module: Mesa
Branch: 9.1
Commit: 99adec8a88f239452feaf1fc58bec72bb8eb3984
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=99adec8a88f239452feaf1fc58bec72bb8eb3984
Author: Jerome Glisse jgli...@redhat.com
Date: Wed Feb 6 15:03:17 2013 -0500
r600g: make sure async blit is done 8 * pitch at a time v2
The blit must be aligned on 8 horizontal block.
v2: no need to align the reminder
Signed-off-by: Jerome Glisse jgli...@redhat.com
(cherry picked from commit 323a4488250f8f4e9981623b795763b86f5cae3f)
---
src/gallium/drivers/r600/r600_state.c | 13 +++--
1 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index bf194f5..1f50ed6 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -3042,14 +3042,15 @@ static boolean r600_dma_copy_tile(struct r600_context
*rctx,
return FALSE;
}
- size = (copy_height * pitch) 2;
- ncopy = (size / 0x) + !!(size % 0x);
+ /* It's a r6xx/r7xx limitation, the blit must be on 8 boundary for
number
+* line in the blit. Compute max 8 line we can copy in the size limit
+*/
+ cheight = ((0x 2) / pitch) 0xfff8;
+ ncopy = (copy_height / cheight) + !!(copy_height % cheight);
r600_need_dma_space(rctx, ncopy * 7);
+
for (i = 0; i ncopy; i++) {
- cheight = copy_height;
- if (((cheight * pitch) 2) 0x) {
- cheight = (0x 2) / pitch;
- }
+ cheight = cheight copy_height ? copy_height : cheight;
size = (cheight * pitch) 2;
/* emit reloc before writting cs so that cs is always in
consistent state */
r600_context_bo_reloc(rctx, rctx-rings.dma, rsrc-resource,
RADEON_USAGE_READ);
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Mesa (master): xorg: fix exa finish access
Module: Mesa Branch: master Commit: 3310acdf4756feb82bf043e7663b6dd8d6e3f7c9 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3310acdf4756feb82bf043e7663b6dd8d6e3f7c9 Author: Jerome Glisse jgli...@redhat.com Date: Fri Feb 8 18:57:42 2013 -0500 xorg: fix exa finish access The exa core will already set the pointer to NULL prior calling the callback function. So don't bail out in the callback if it's already NULL. Signed-off-by: Jerome Glisse jgli...@redhat.com --- src/gallium/state_trackers/xorg/xorg_exa.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/gallium/state_trackers/xorg/xorg_exa.c b/src/gallium/state_trackers/xorg/xorg_exa.c index f010be6..3e764f8 100644 --- a/src/gallium/state_trackers/xorg/xorg_exa.c +++ b/src/gallium/state_trackers/xorg/xorg_exa.c @@ -318,7 +318,7 @@ ExaFinishAccess(PixmapPtr pPix, int index) if (!priv) return; -if (!priv-map_transfer || pPix-devPrivate.ptr == NULL) +if (!priv-map_transfer) return; exa_debug_printf(ExaFinishAccess %d\n, index); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (9.1): xorg: fix exa finish access
Module: Mesa Branch: 9.1 Commit: 18ef6b1265dcd83f511f287388f5e8533e97b35a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=18ef6b1265dcd83f511f287388f5e8533e97b35a Author: Jerome Glisse jgli...@redhat.com Date: Fri Feb 8 18:57:42 2013 -0500 xorg: fix exa finish access The exa core will already set the pointer to NULL prior calling the callback function. So don't bail out in the callback if it's already NULL. Signed-off-by: Jerome Glisse jgli...@redhat.com (cherry picked from commit 3310acdf4756feb82bf043e7663b6dd8d6e3f7c9) --- src/gallium/state_trackers/xorg/xorg_exa.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/gallium/state_trackers/xorg/xorg_exa.c b/src/gallium/state_trackers/xorg/xorg_exa.c index f010be6..3e764f8 100644 --- a/src/gallium/state_trackers/xorg/xorg_exa.c +++ b/src/gallium/state_trackers/xorg/xorg_exa.c @@ -318,7 +318,7 @@ ExaFinishAccess(PixmapPtr pPix, int index) if (!priv) return; -if (!priv-map_transfer || pPix-devPrivate.ptr == NULL) +if (!priv-map_transfer) return; exa_debug_printf(ExaFinishAccess %d\n, index); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): winsys/radeon: improve debuging printing
Module: Mesa
Branch: master
Commit: 9a4768456434f8719e6168254224c9554877230d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a4768456434f8719e6168254224c9554877230d
Author: Jerome Glisse jgli...@redhat.com
Date: Fri Feb 8 20:28:06 2013 -0500
winsys/radeon: improve debuging printing
Make sure one can identify virtual address failure from allocation
failure.
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/winsys/radeon/drm/radeon_drm_bo.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 6daafc3..bb6e954 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -593,10 +593,11 @@ static struct pb_buffer *radeon_bomgr_create_bo(struct
pb_manager *_mgr,
va.offset = bo-va;
r = drmCommandWriteRead(rws-fd, DRM_RADEON_GEM_VA, va, sizeof(va));
if (r va.operation == RADEON_VA_RESULT_ERROR) {
-fprintf(stderr, radeon: Failed to allocate a buffer:\n);
+fprintf(stderr, radeon: Failed to allocate virtual address for
buffer:\n);
fprintf(stderr, radeon:size : %d bytes\n, size);
fprintf(stderr, radeon:alignment : %d bytes\n,
desc-alignment);
fprintf(stderr, radeon:domains : %d\n,
args.initial_domain);
+fprintf(stderr, radeon:va: 0x%016llx\n, (unsigned
long long)bo-va);
radeon_bo_destroy(bo-base);
return NULL;
}
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Mesa (9.1): winsys/radeon: improve debuging printing
Module: Mesa
Branch: 9.1
Commit: a0528269a3673e4c4e43c96a9bdc2cb98f1968f2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0528269a3673e4c4e43c96a9bdc2cb98f1968f2
Author: Jerome Glisse jgli...@redhat.com
Date: Fri Feb 8 20:28:06 2013 -0500
winsys/radeon: improve debuging printing
Make sure one can identify virtual address failure from allocation
failure.
Signed-off-by: Jerome Glisse jgli...@redhat.com
(cherry picked from commit 9a4768456434f8719e6168254224c9554877230d)
---
src/gallium/winsys/radeon/drm/radeon_drm_bo.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 6daafc3..bb6e954 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -593,10 +593,11 @@ static struct pb_buffer *radeon_bomgr_create_bo(struct
pb_manager *_mgr,
va.offset = bo-va;
r = drmCommandWriteRead(rws-fd, DRM_RADEON_GEM_VA, va, sizeof(va));
if (r va.operation == RADEON_VA_RESULT_ERROR) {
-fprintf(stderr, radeon: Failed to allocate a buffer:\n);
+fprintf(stderr, radeon: Failed to allocate virtual address for
buffer:\n);
fprintf(stderr, radeon:size : %d bytes\n, size);
fprintf(stderr, radeon:alignment : %d bytes\n,
desc-alignment);
fprintf(stderr, radeon:domains : %d\n,
args.initial_domain);
+fprintf(stderr, radeon:va: 0x%016llx\n, (unsigned
long long)bo-va);
radeon_bo_destroy(bo-base);
return NULL;
}
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Mesa (master): r600g: fix slice tile max for compressed texture and async dma
Module: Mesa
Branch: master
Commit: 681707abf2121e9d02c6fd13e312fd103f26949c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=681707abf2121e9d02c6fd13e312fd103f26949c
Author: Jerome Glisse jgli...@redhat.com
Date: Wed Feb 6 13:54:02 2013 -0500
r600g: fix slice tile max for compressed texture and async dma
Was using the pixel size instead of the number of block for the slice
tile max computation which resulted in dma writing at wrong address.
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_state.c |6 --
src/gallium/drivers/r600/r600_state.c |6 --
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index f076fca..211c218 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3532,7 +3532,8 @@ static void evergreen_dma_copy_tile(struct r600_context
*rctx,
if (dst_mode == RADEON_SURF_MODE_LINEAR) {
/* T2L */
array_mode = evergreen_array_mode(src_mode);
- slice_tile_max = (((pitch *
rsrc-surface.level[src_level].npix_y) 6) / bpp) - 1;
+ slice_tile_max = (rsrc-surface.level[src_level].nblk_x *
rsrc-surface.level[src_level].nblk_y) 6;
+ slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
/* linear height must be the same as the slice tile max height,
it's ok even
* if the linear destination/source have smaller heigh as the
size of the
* dma packet will be using the copy_height which is always
smaller or equal
@@ -3556,7 +3557,8 @@ static void evergreen_dma_copy_tile(struct r600_context
*rctx,
} else {
/* L2T */
array_mode = evergreen_array_mode(dst_mode);
- slice_tile_max = (((pitch *
rdst-surface.level[dst_level].npix_y) 6) / bpp) - 1;
+ slice_tile_max = (rdst-surface.level[dst_level].nblk_x *
rdst-surface.level[dst_level].nblk_y) 6;
+ slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
/* linear height must be the same as the slice tile max height,
it's ok even
* if the linear destination/source have smaller heigh as the
size of the
* dma packet will be using the copy_height which is always
smaller or equal
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 1e2f2dd..67c4d99 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -3027,7 +3027,8 @@ static boolean r600_dma_copy_tile(struct r600_context
*rctx,
if (dst_mode == RADEON_SURF_MODE_LINEAR) {
/* T2L */
array_mode = r600_array_mode(src_mode);
- slice_tile_max = (((pitch *
rsrc-surface.level[src_level].npix_y) 6) / bpp) - 1;
+ slice_tile_max = (rsrc-surface.level[src_level].nblk_x *
rsrc-surface.level[src_level].nblk_y) 6;
+ slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
/* linear height must be the same as the slice tile max height,
it's ok even
* if the linear destination/source have smaller heigh as the
size of the
* dma packet will be using the copy_height which is always
smaller or equal
@@ -3045,7 +3046,8 @@ static boolean r600_dma_copy_tile(struct r600_context
*rctx,
} else {
/* L2T */
array_mode = r600_array_mode(dst_mode);
- slice_tile_max = (((pitch *
rdst-surface.level[dst_level].npix_y) 6) / bpp) - 1;
+ slice_tile_max = (rdst-surface.level[dst_level].nblk_x *
rdst-surface.level[dst_level].nblk_y) 6;
+ slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
/* linear height must be the same as the slice tile max height,
it's ok even
* if the linear destination/source have smaller heigh as the
size of the
* dma packet will be using the copy_height which is always
smaller or equal
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Mesa (9.1): r600g: fix slice tile max for compressed texture and async dma
Module: Mesa
Branch: 9.1
Commit: d04b50b4de63cc76b2ac2a45e9e63728ae155b36
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d04b50b4de63cc76b2ac2a45e9e63728ae155b36
Author: Jerome Glisse jgli...@redhat.com
Date: Wed Feb 6 13:54:02 2013 -0500
r600g: fix slice tile max for compressed texture and async dma
Was using the pixel size instead of the number of block for the slice
tile max computation which resulted in dma writing at wrong address.
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_state.c |6 --
src/gallium/drivers/r600/r600_state.c |6 --
2 files changed, 8 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 5dd8b13..ad2f731 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3506,7 +3506,8 @@ static void evergreen_dma_copy_tile(struct r600_context
*rctx,
if (dst_mode == RADEON_SURF_MODE_LINEAR) {
/* T2L */
array_mode = evergreen_array_mode(src_mode);
- slice_tile_max = (((pitch *
rsrc-surface.level[src_level].npix_y) 6) / bpp) - 1;
+ slice_tile_max = (rsrc-surface.level[src_level].nblk_x *
rsrc-surface.level[src_level].nblk_y) 6;
+ slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
/* linear height must be the same as the slice tile max height,
it's ok even
* if the linear destination/source have smaller heigh as the
size of the
* dma packet will be using the copy_height which is always
smaller or equal
@@ -3530,7 +3531,8 @@ static void evergreen_dma_copy_tile(struct r600_context
*rctx,
} else {
/* L2T */
array_mode = evergreen_array_mode(dst_mode);
- slice_tile_max = (((pitch *
rdst-surface.level[dst_level].npix_y) 6) / bpp) - 1;
+ slice_tile_max = (rdst-surface.level[dst_level].nblk_x *
rdst-surface.level[dst_level].nblk_y) 6;
+ slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
/* linear height must be the same as the slice tile max height,
it's ok even
* if the linear destination/source have smaller heigh as the
size of the
* dma packet will be using the copy_height which is always
smaller or equal
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 44cd00e..bf194f5 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -3001,7 +3001,8 @@ static boolean r600_dma_copy_tile(struct r600_context
*rctx,
if (dst_mode == RADEON_SURF_MODE_LINEAR) {
/* T2L */
array_mode = r600_array_mode(src_mode);
- slice_tile_max = (((pitch *
rsrc-surface.level[src_level].npix_y) 6) / bpp) - 1;
+ slice_tile_max = (rsrc-surface.level[src_level].nblk_x *
rsrc-surface.level[src_level].nblk_y) 6;
+ slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
/* linear height must be the same as the slice tile max height,
it's ok even
* if the linear destination/source have smaller heigh as the
size of the
* dma packet will be using the copy_height which is always
smaller or equal
@@ -3019,7 +3020,8 @@ static boolean r600_dma_copy_tile(struct r600_context
*rctx,
} else {
/* L2T */
array_mode = r600_array_mode(dst_mode);
- slice_tile_max = (((pitch *
rdst-surface.level[dst_level].npix_y) 6) / bpp) - 1;
+ slice_tile_max = (rdst-surface.level[dst_level].nblk_x *
rdst-surface.level[dst_level].nblk_y) 6;
+ slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
/* linear height must be the same as the slice tile max height,
it's ok even
* if the linear destination/source have smaller heigh as the
size of the
* dma packet will be using the copy_height which is always
smaller or equal
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Mesa (master): r600g: add cs memory usage accounting and limit it v3
Module: Mesa
Branch: master
Commit: 5e0c956cb219e54dfc22e64ac3f00e22619c763f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e0c956cb219e54dfc22e64ac3f00e22619c763f
Author: Jerome Glisse jgli...@redhat.com
Date: Tue Jan 29 12:52:17 2013 -0500
r600g: add cs memory usage accounting and limit it v3
We are now seing cs that can go over the vram+gtt size to avoid
failing flush early cs that goes over 70% (gtt+vram) usage. 70%
is use to allow some fragmentation.
The idea is to compute a gross estimate of memory requirement of
each draw call. After each draw call, memory will be precisely
accounted. So the uncertainty is only on the current draw call.
In practice this gave very good estimate (+/- 10% of the target
memory limit).
v2: Remove left over from testing version, remove useless NULL
checking. Improve commit message.
v3: Add comment to code on memory accounting precision
Signed-off-by: Jerome Glisse jgli...@redhat.com
Reviewed-by: Marek Olšák mar...@gmail.com
---
src/gallium/drivers/r600/evergreen_state.c|4 +++
src/gallium/drivers/r600/r600_hw_context.c| 12 ++
src/gallium/drivers/r600/r600_pipe.h | 28 +
src/gallium/drivers/r600/r600_state.c |3 ++
src/gallium/drivers/r600/r600_state_common.c | 13 ++-
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 11 +
src/gallium/winsys/radeon/drm/radeon_winsys.h | 10 +
7 files changed, 80 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 0a3861f..5dd8b13 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1668,6 +1668,8 @@ static void evergreen_set_framebuffer_state(struct
pipe_context *ctx,
surf = (struct r600_surface*)state-cbufs[i];
rtex = (struct r600_texture*)surf-base.texture;
+ r600_context_add_resource_size(ctx, state-cbufs[i]-texture);
+
if (!surf-color_initialized) {
evergreen_init_color_surface(rctx, surf);
}
@@ -1699,6 +1701,8 @@ static void evergreen_set_framebuffer_state(struct
pipe_context *ctx,
if (state-zsbuf) {
surf = (struct r600_surface*)state-zsbuf;
+ r600_context_add_resource_size(ctx, state-zsbuf-texture);
+
if (!surf-depth_initialized) {
evergreen_init_depth_surface(rctx, surf);
}
diff --git a/src/gallium/drivers/r600/r600_hw_context.c
b/src/gallium/drivers/r600/r600_hw_context.c
index 23f488a..a89f230 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -359,6 +359,16 @@ out_err:
void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
boolean count_draw_in)
{
+ if (!ctx-ws-cs_memory_below_limit(ctx-rings.gfx.cs, ctx-vram,
ctx-gtt)) {
+ ctx-gtt = 0;
+ ctx-vram = 0;
+ ctx-rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
+ return;
+ }
+ /* all will be accounted once relocation are emited */
+ ctx-gtt = 0;
+ ctx-vram = 0;
+
/* The number of dwords we already used in the CS so far. */
num_dw += ctx-rings.gfx.cs-cdw;
@@ -784,6 +794,8 @@ void r600_begin_new_cs(struct r600_context *ctx)
ctx-pm4_dirty_cdwords = 0;
ctx-flags = 0;
+ ctx-gtt = 0;
+ ctx-vram = 0;
/* Begin a new CS. */
r600_emit_command_buffer(ctx-rings.gfx.cs, ctx-start_cs_cmd);
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index 3ff42d3..ec59c92 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -447,6 +447,10 @@ struct r600_context {
unsignedbackend_mask;
unsignedmax_db; /* for OQ */
+ /* current unaccounted memory usage */
+ uint64_tvram;
+ uint64_tgtt;
+
/* Miscellaneous state objects. */
void*custom_dsa_flush;
void*custom_blend_resolve;
@@ -998,4 +1002,28 @@ static INLINE unsigned u_max_layer(struct pipe_resource
*r, unsigned level)
}
}
+static INLINE void r600_context_add_resource_size(struct pipe_context *ctx,
struct pipe_resource *r)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_resource *rr = (struct r600_resource *)r;
+
+ if (r == NULL) {
+ return;
+ }
+
+ /*
+* The idea is to compute a gross estimate of memory requirement of
+* each draw call. After each draw call, memory will be precisely
+* accounted. So the uncertainty is only on the current draw call
Mesa (9.1): r600g: fix htile buffer leak
Module: Mesa Branch: 9.1 Commit: 3b8d4f941f34a5e839c40606074d77822b8ca8c7 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b8d4f941f34a5e839c40606074d77822b8ca8c7 Author: Marek Olšák mar...@gmail.com Date: Thu Jan 31 15:29:16 2013 +0100 r600g: fix htile buffer leak NOTE: This is a candidate for the 9.1 branch. --- src/gallium/drivers/r600/r600_texture.c |1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c index 1d04cc0..85fc887 100644 --- a/src/gallium/drivers/r600/r600_texture.c +++ b/src/gallium/drivers/r600/r600_texture.c @@ -270,6 +270,7 @@ static void r600_texture_destroy(struct pipe_screen *screen, if (rtex-flushed_depth_texture) pipe_resource_reference((struct pipe_resource **)rtex-flushed_depth_texture, NULL); +pipe_resource_reference((struct pipe_resource**)rtex-htile, NULL); pb_reference(resource-buf, NULL); FREE(rtex); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (9.1): r600g: add cs memory usage accounting and limit it v3
Module: Mesa
Branch: 9.1
Commit: 9d8a866db319421b63ef3784ae22e51a06c94803
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d8a866db319421b63ef3784ae22e51a06c94803
Author: Jerome Glisse jgli...@redhat.com
Date: Tue Jan 29 12:52:17 2013 -0500
r600g: add cs memory usage accounting and limit it v3
We are now seing cs that can go over the vram+gtt size to avoid
failing flush early cs that goes over 70% (gtt+vram) usage. 70%
is use to allow some fragmentation.
The idea is to compute a gross estimate of memory requirement of
each draw call. After each draw call, memory will be precisely
accounted. So the uncertainty is only on the current draw call.
In practice this gave very good estimate (+/- 10% of the target
memory limit).
v2: Remove left over from testing version, remove useless NULL
checking. Improve commit message.
v3: Add comment to code on memory accounting precision
Signed-off-by: Jerome Glisse jgli...@redhat.com
Reviewed-by: Marek Olšák mar...@gmail.com
---
src/gallium/drivers/r600/evergreen_state.c|4 +++
src/gallium/drivers/r600/r600_hw_context.c| 12 ++
src/gallium/drivers/r600/r600_pipe.h | 28 +
src/gallium/drivers/r600/r600_state.c |3 ++
src/gallium/drivers/r600/r600_state_common.c | 13 ++-
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 11 +
src/gallium/winsys/radeon/drm/radeon_winsys.h | 10 +
7 files changed, 80 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 0a3861f..5dd8b13 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1668,6 +1668,8 @@ static void evergreen_set_framebuffer_state(struct
pipe_context *ctx,
surf = (struct r600_surface*)state-cbufs[i];
rtex = (struct r600_texture*)surf-base.texture;
+ r600_context_add_resource_size(ctx, state-cbufs[i]-texture);
+
if (!surf-color_initialized) {
evergreen_init_color_surface(rctx, surf);
}
@@ -1699,6 +1701,8 @@ static void evergreen_set_framebuffer_state(struct
pipe_context *ctx,
if (state-zsbuf) {
surf = (struct r600_surface*)state-zsbuf;
+ r600_context_add_resource_size(ctx, state-zsbuf-texture);
+
if (!surf-depth_initialized) {
evergreen_init_depth_surface(rctx, surf);
}
diff --git a/src/gallium/drivers/r600/r600_hw_context.c
b/src/gallium/drivers/r600/r600_hw_context.c
index 23f488a..a89f230 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -359,6 +359,16 @@ out_err:
void r600_need_cs_space(struct r600_context *ctx, unsigned num_dw,
boolean count_draw_in)
{
+ if (!ctx-ws-cs_memory_below_limit(ctx-rings.gfx.cs, ctx-vram,
ctx-gtt)) {
+ ctx-gtt = 0;
+ ctx-vram = 0;
+ ctx-rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
+ return;
+ }
+ /* all will be accounted once relocation are emited */
+ ctx-gtt = 0;
+ ctx-vram = 0;
+
/* The number of dwords we already used in the CS so far. */
num_dw += ctx-rings.gfx.cs-cdw;
@@ -784,6 +794,8 @@ void r600_begin_new_cs(struct r600_context *ctx)
ctx-pm4_dirty_cdwords = 0;
ctx-flags = 0;
+ ctx-gtt = 0;
+ ctx-vram = 0;
/* Begin a new CS. */
r600_emit_command_buffer(ctx-rings.gfx.cs, ctx-start_cs_cmd);
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index 3ff42d3..ec59c92 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -447,6 +447,10 @@ struct r600_context {
unsignedbackend_mask;
unsignedmax_db; /* for OQ */
+ /* current unaccounted memory usage */
+ uint64_tvram;
+ uint64_tgtt;
+
/* Miscellaneous state objects. */
void*custom_dsa_flush;
void*custom_blend_resolve;
@@ -998,4 +1002,28 @@ static INLINE unsigned u_max_layer(struct pipe_resource
*r, unsigned level)
}
}
+static INLINE void r600_context_add_resource_size(struct pipe_context *ctx,
struct pipe_resource *r)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_resource *rr = (struct r600_resource *)r;
+
+ if (r == NULL) {
+ return;
+ }
+
+ /*
+* The idea is to compute a gross estimate of memory requirement of
+* each draw call. After each draw call, memory will be precisely
+* accounted. So the uncertainty is only on the current draw call
Mesa (9.0): r600g: add cs memory usage accounting and limit it v3 ( backport for mesa 9.0)
Module: Mesa
Branch: 9.0
Commit: 78222e63630280b96488de0d51d1b2578e26f814
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=78222e63630280b96488de0d51d1b2578e26f814
Author: Jerome Glisse jgli...@redhat.com
Date: Wed Jan 30 15:02:32 2013 -0500
r600g: add cs memory usage accounting and limit it v3 (backport for mesa 9.0)
We are now seing cs that can go over the vram+gtt size to avoid
failing flush early cs that goes over 70% (gtt+vram) usage. 70%
is use to allow some fragmentation.
The idea is to compute a gross estimate of memory requirement of
each draw call. After each draw call, memory will be precisely
accounted. So the uncertainty is only on the current draw call.
In practice this gave very good estimate (+/- 10% of the target
memory limit).
v2: Remove left over from testing version, remove useless NULL
checking. Improve commit message.
v3: Add comment to code on memory accounting precision
This version is a backport for mesa 9.0
Signed-off-by: Jerome Glisse jgli...@redhat.com
Reviewed-by: Marek Olšák mar...@gmail.com
---
src/gallium/drivers/r600/evergreen_state.c|4 +++
src/gallium/drivers/r600/r600_hw_context.c| 12 ++
src/gallium/drivers/r600/r600_pipe.h | 28 +
src/gallium/drivers/r600/r600_state.c |4 +++
src/gallium/drivers/r600/r600_state_common.c | 13 ++-
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 11 +
src/gallium/winsys/radeon/drm/radeon_winsys.h | 10 +
7 files changed, 81 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 6bf4247..a17ba17 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1721,6 +1721,8 @@ static void evergreen_set_framebuffer_state(struct
pipe_context *ctx,
res = (struct r600_resource*)surf-base.texture;
rtex = (struct r600_texture*)res;
+ r600_context_add_resource_size(ctx, state-cbufs[i]-texture);
+
if (!surf-color_initialized) {
evergreen_init_color_surface(rctx, surf);
}
@@ -1787,6 +1789,8 @@ static void evergreen_set_framebuffer_state(struct
pipe_context *ctx,
surf = (struct r600_surface*)state-zsbuf;
res = (struct r600_resource*)surf-base.texture;
+ r600_context_add_resource_size(ctx, state-zsbuf-texture);
+
if (!surf-depth_initialized) {
evergreen_init_depth_surface(rctx, surf);
}
diff --git a/src/gallium/drivers/r600/r600_hw_context.c
b/src/gallium/drivers/r600/r600_hw_context.c
index af27fd9..d5efd86 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -635,6 +635,16 @@ void r600_need_cs_space(struct r600_context *ctx, unsigned
num_dw,
{
struct r600_atom *state;
+ if (!ctx-ws-cs_memory_below_limit(ctx-cs, ctx-vram, ctx-gtt)) {
+ ctx-gtt = 0;
+ ctx-vram = 0;
+ r600_flush(ctx-context, NULL, RADEON_FLUSH_ASYNC);
+ return;
+ }
+ /* all will be accounted once relocation are emited */
+ ctx-gtt = 0;
+ ctx-vram = 0;
+
/* The number of dwords we already used in the CS so far. */
num_dw += ctx-cs-cdw;
@@ -953,6 +963,8 @@ void r600_context_flush(struct r600_context *ctx, unsigned
flags)
ctx-pm4_dirty_cdwords = 0;
ctx-flags = 0;
+ ctx-gtt = 0;
+ ctx-vram = 0;
/* Begin a new CS. */
r600_emit_atom(ctx, ctx-start_cs_cmd.atom);
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index 721334d..ba75c9d 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -371,6 +371,10 @@ struct r600_context {
unsigned default_ps_gprs, default_vs_gprs;
+ /* current unaccounted memory usage */
+ uint64_tvram;
+ uint64_tgtt;
+
/* States based on r600_atom. */
struct list_headdirty_states;
struct r600_command_buffer start_cs_cmd; /* invariant state mostly
*/
@@ -886,4 +890,28 @@ static INLINE uint64_t r600_resource_va(struct pipe_screen
*screen, struct pipe_
return rscreen-ws-buffer_get_virtual_address(rresource-cs_buf);
}
+static INLINE void r600_context_add_resource_size(struct pipe_context *ctx,
struct pipe_resource *r)
+{
+ struct r600_context *rctx = (struct r600_context *)ctx;
+ struct r600_resource *rr = (struct r600_resource *)r;
+
+ if (r == NULL) {
+ return;
+ }
+
+ /*
+* The idea is to compute a gross estimate of memory requirement of
+* each draw call. After each draw call, memory will be precisely
+* accounted
Mesa (master): radeon/winsys: add dma ring support to winsys v3
Module: Mesa
Branch: master
Commit: 6c064fd7492ea835f873112bc3189bb1920aad32
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6c064fd7492ea835f873112bc3189bb1920aad32
Author: Jerome Glisse jgli...@redhat.com
Date: Mon Jan 7 11:49:23 2013 -0500
radeon/winsys: add dma ring support to winsys v3
Add ring support, you can create a cs for each ring. DMA ring is
bit special regarding relocation as you must emit as much relocation
as there is use of the buffer.
v2: - Improved comment on relocation changes
- Use a single thread to queue cs submittion this simplify driver
code while not impacting performances. Rational for this is that
you have to wait for all previous submission to have completed
so there was never a case while we could have 2 different thread
submitting a command stream at the same time. This code just
consolidate submission into one single thread per winsys.
v3: - Do not use semaphore for empty queue signaling, instead use
cond var. This is because it's tricky to maintain an even number
of call to semaphore wait and semaphore signal (the number of
cs in the stack would for instance make that number vary).
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r300/r300_context.c |2 +-
src/gallium/drivers/r600/r600_pipe.c |2 +-
src/gallium/drivers/radeonsi/radeonsi_pipe.c |2 +-
src/gallium/winsys/radeon/drm/radeon_drm_bo.c |2 +-
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 160 -
src/gallium/winsys/radeon/drm/radeon_drm_cs.h |8 +-
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 87 +++
src/gallium/winsys/radeon/drm/radeon_drm_winsys.h | 17 +++
src/gallium/winsys/radeon/drm/radeon_winsys.h | 20 +++-
9 files changed, 218 insertions(+), 82 deletions(-)
diff --git a/src/gallium/drivers/r300/r300_context.c
b/src/gallium/drivers/r300/r300_context.c
index d8af13f..340a7f0 100644
--- a/src/gallium/drivers/r300/r300_context.c
+++ b/src/gallium/drivers/r300/r300_context.c
@@ -379,7 +379,7 @@ struct pipe_context* r300_create_context(struct
pipe_screen* screen,
sizeof(struct pipe_transfer), 64,
UTIL_SLAB_SINGLETHREADED);
-r300-cs = rws-cs_create(rws);
+r300-cs = rws-cs_create(rws, RING_GFX);
if (r300-cs == NULL)
goto fail;
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index fda5074..e4a35cf 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -289,7 +289,7 @@ static struct pipe_context *r600_create_context(struct
pipe_screen *screen, void
goto fail;
}
- rctx-cs = rctx-ws-cs_create(rctx-ws);
+ rctx-cs = rctx-ws-cs_create(rctx-ws, RING_GFX);
rctx-ws-cs_set_flush_callback(rctx-cs, r600_flush_from_winsys, rctx);
rctx-uploader = u_upload_create(rctx-context, 1024 * 1024, 256,
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
index 2f97609..471dd48 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c
@@ -225,7 +225,7 @@ static struct pipe_context *r600_create_context(struct
pipe_screen *screen, void
case TAHITI:
si_init_state_functions(rctx);
LIST_INITHEAD(rctx-active_query_list);
- rctx-cs = rctx-ws-cs_create(rctx-ws);
+ rctx-cs = rctx-ws-cs_create(rctx-ws, RING_GFX);
rctx-max_db = 8;
si_init_config(rctx);
break;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 897e962..6daafc3 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -453,7 +453,7 @@ static void *radeon_bo_map(struct radeon_winsys_cs_handle
*buf,
} else {
/* Try to avoid busy-waiting in radeon_bo_wait. */
if (p_atomic_read(bo-num_active_ioctls))
-radeon_drm_cs_sync_flush(cs);
+radeon_drm_cs_sync_flush(rcs);
}
radeon_bo_wait((struct pb_buffer*)bo, RADEON_USAGE_READWRITE);
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
index c5e7f1e..cab2704 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.c
@@ -90,6 +90,10 @@
#define RADEON_CS_RING_COMPUTE 1
#endif
+#ifndef RADEON_CS_RING_DMA
+#define RADEON_CS_RING_DMA 2
+#endif
+
#ifndef RADEON_CS_END_OF_FRAME
#define RADEON_CS_END_OF_FRAME 0x04
#endif
@@ -158,10 +162,8 @@ static void radeon_destroy_cs_context(struct
radeon_cs_context *csc)
FREE(csc-relocs
Mesa (master): r600g: add multi ring support with dma as first second ring v4
Module: Mesa Branch: master Commit: bff07638a86d36ac826fb287214eda9ce31c02ad URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=bff07638a86d36ac826fb287214eda9ce31c02ad Author: Jerome Glisse jgli...@redhat.com Date: Mon Jan 7 14:25:11 2013 -0500 r600g: add multi ring support with dma as first second ring v4 We keep track of ring emission order in a stack, whenever we need to flush we empty the stack in a fifo order. There is few helpers function for bo mapping and other ring activities that will make sure that the ring stack is properly flush and submitted. v2: fix st flush path, and other flush path to properly flush all rings if necessary v3: - improve name of ring helpers - make sure that each time a cs is gona be written it endup at top of the stack to avoid any issue such as : STACK[0] = dma (withbo A,B) STACK[1] = gfx (withbo C,D) Now if code try to emit a dma command relative to bo C or D it will start writting cmd stream into the cs and once it reach the point where it adds relocation it will flush. At that point the cs will have cmd that don't have proper relocation into the relocation buffer and kernel will just refuse to run. v4: - Drop the stack idea as it turn out there is no way to use it or benefit from it. Any time the driver start command on other ring, it always need to flush the previous ring. So make code simpler by not using a stack. Signed-off-by: Jerome Glisse jgli...@redhat.com --- src/gallium/drivers/r600/evergreen_compute.c | 30 ++-- .../drivers/r600/evergreen_compute_internal.c | 42 +++--- src/gallium/drivers/r600/evergreen_hw_context.c|4 +- src/gallium/drivers/r600/evergreen_state.c | 56 + src/gallium/drivers/r600/r600_asm.c|3 +- src/gallium/drivers/r600/r600_buffer.c | 17 ++- src/gallium/drivers/r600/r600_hw_context.c | 51 src/gallium/drivers/r600/r600_pipe.c | 142 +--- src/gallium/drivers/r600/r600_pipe.h | 40 +- src/gallium/drivers/r600/r600_query.c | 24 ++-- src/gallium/drivers/r600/r600_shader.c |2 +- src/gallium/drivers/r600/r600_state.c | 48 --- src/gallium/drivers/r600/r600_state_common.c | 29 +++-- src/gallium/drivers/r600/r600_texture.c| 15 +- 14 files changed, 327 insertions(+), 176 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=bff07638a86d36ac826fb287214eda9ce31c02ad ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: add async for staging buffer upload v2
Module: Mesa
Branch: master
Commit: 325422c49449acdd8df1eb2ca8ed81f7696c38cc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=325422c49449acdd8df1eb2ca8ed81f7696c38cc
Author: Jerome Glisse jgli...@redhat.com
Date: Mon Jan 7 17:45:59 2013 -0500
r600g: add async for staging buffer upload v2
v2: Add virtual address to dma src/dst offset for cayman
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_hw_context.c | 46 +
src/gallium/drivers/r600/evergreen_state.c | 201 +++
src/gallium/drivers/r600/evergreend.h | 15 ++
src/gallium/drivers/r600/r600.h | 27 +++
src/gallium/drivers/r600/r600_buffer.c | 27 +++-
src/gallium/drivers/r600/r600_hw_context.c | 48 +-
src/gallium/drivers/r600/r600_pipe.c|6 +-
src/gallium/drivers/r600/r600_pipe.h|9 +
src/gallium/drivers/r600/r600_state.c | 190 +
src/gallium/drivers/r600/r600_state_common.c|6 +-
src/gallium/drivers/r600/r600_texture.c | 24 ++-
src/gallium/drivers/r600/r600d.h| 15 ++
12 files changed, 596 insertions(+), 18 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c
b/src/gallium/drivers/r600/evergreen_hw_context.c
index fa90c9a..ca4f4b3 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -26,6 +26,7 @@
#include r600_hw_context_priv.h
#include evergreend.h
#include util/u_memory.h
+#include util/u_math.h
static const struct r600_reg cayman_config_reg_list[] = {
{R_009100_SPI_CONFIG_CNTL, REG_FLAG_ENABLE_ALWAYS |
REG_FLAG_FLUSH_CHANGE, 0},
@@ -238,3 +239,48 @@ void evergreen_set_streamout_enable(struct r600_context
*ctx, unsigned buffer_en
r600_write_context_reg(cs, R_028B94_VGT_STRMOUT_CONFIG,
S_028B94_STREAMOUT_0_EN(0));
}
}
+
+void evergreen_dma_copy(struct r600_context *rctx,
+ struct pipe_resource *dst,
+ struct pipe_resource *src,
+ unsigned long dst_offset,
+ unsigned long src_offset,
+ unsigned long size)
+{
+ struct radeon_winsys_cs *cs = rctx-rings.dma.cs;
+ unsigned i, ncopy, csize, sub_cmd, shift;
+ struct r600_resource *rdst = (struct r600_resource*)dst;
+ struct r600_resource *rsrc = (struct r600_resource*)src;
+
+ /* make sure that the dma ring is only one active */
+ rctx-rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
+ dst_offset += r600_resource_va(rctx-screen-screen, dst);
+ src_offset += r600_resource_va(rctx-screen-screen, src);
+
+ /* see if we use dword or byte copy */
+ if (!(dst_offset 0x3) !(src_offset 0x3) !(size 0x3)) {
+ size = 2;
+ sub_cmd = 0x00;
+ shift = 2;
+ } else {
+ sub_cmd = 0x40;
+ shift = 0;
+ }
+ ncopy = (size / 0x000f) + !!(size % 0x000f);
+
+ r600_need_dma_space(rctx, ncopy * 5);
+ for (i = 0; i ncopy; i++) {
+ csize = size 0x000f ? size : 0x000f;
+ /* emit reloc before writting cs so that cs is always in
consistent state */
+ r600_context_bo_reloc(rctx, rctx-rings.dma, rsrc,
RADEON_USAGE_READ);
+ r600_context_bo_reloc(rctx, rctx-rings.dma, rdst,
RADEON_USAGE_WRITE);
+ cs-buf[cs-cdw++] = DMA_PACKET(DMA_PACKET_COPY, sub_cmd,
csize);
+ cs-buf[cs-cdw++] = dst_offset 0x;
+ cs-buf[cs-cdw++] = src_offset 0x;
+ cs-buf[cs-cdw++] = (dst_offset 32UL) 0xff;
+ cs-buf[cs-cdw++] = (src_offset 32UL) 0xff;
+ dst_offset += csize shift;
+ src_offset += csize shift;
+ size -= csize;
+ }
+}
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index d03c376..be1c427 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -30,6 +30,20 @@
#include util/u_framebuffer.h
#include util/u_dual_blend.h
#include evergreen_compute.h
+#include util/u_math.h
+
+static INLINE unsigned evergreen_array_mode(unsigned mode)
+{
+ switch (mode) {
+ case RADEON_SURF_MODE_LINEAR_ALIGNED: return
V_028C70_ARRAY_LINEAR_ALIGNED;
+ break;
+ case RADEON_SURF_MODE_1D: return
V_028C70_ARRAY_1D_TILED_THIN1;
+ break;
+ case RADEON_SURF_MODE_2D: return
V_028C70_ARRAY_2D_TILED_THIN1;
+ default:
+ case RADEON_SURF_MODE_LINEAR: return
V_028C70_ARRAY_LINEAR_GENERAL;
+ }
+}
static uint32_t eg_num_banks(uint32_t nbanks)
{
@@ -3445,3 +3459,190 @@ void evergreen_update_db_shader_control(struct
r600_context * rctx)
rctx
Mesa (master): r600g: fix segfault with old kernel
Module: Mesa
Branch: master
Commit: 72916698b056d0559263e84372bb45cd83a1c2c2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=72916698b056d0559263e84372bb45cd83a1c2c2
Author: Jerome Glisse jgli...@redhat.com
Date: Mon Jan 28 14:48:46 2013 -0500
r600g: fix segfault with old kernel
Old kernel do not have dma support, patch pushed were missing some
of the check needed to not use dma.
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_compute.c |4 +++-
src/gallium/drivers/r600/r600_pipe.c | 20 +---
src/gallium/drivers/r600/r600_pipe.h |2 +-
src/gallium/drivers/r600/r600_state_common.c |4 +++-
src/gallium/drivers/r600/r600_texture.c |4 +++-
5 files changed, 23 insertions(+), 11 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index f4a7905..128464e 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -321,7 +321,9 @@ static void compute_emit_cs(struct r600_context *ctx, const
uint *block_layout,
ctx-cs_shader_state.shader-resources;
/* make sure that the gfx ring is only one active */
- ctx-rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
+ if (ctx-rings.dma.cs) {
+ ctx-rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
+ }
/* Initialize all the compute-related registers.
*
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index 6767412..a59578d 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -151,7 +151,9 @@ static void r600_flush_from_st(struct pipe_context *ctx,
*rfence = r600_create_fence(rctx);
}
/* flush gfx dma ring, order does not matter as only one can be live
*/
- rctx-rings.dma.flush(rctx, fflags);
+ if (rctx-rings.dma.cs) {
+ rctx-rings.dma.flush(rctx, fflags);
+ }
rctx-rings.gfx.flush(rctx, fflags);
}
@@ -179,8 +181,10 @@ boolean r600_rings_is_buffer_referenced(struct
r600_context *ctx,
if (ctx-ws-cs_is_buffer_referenced(ctx-rings.gfx.cs, buf, usage)) {
return TRUE;
}
- if (ctx-ws-cs_is_buffer_referenced(ctx-rings.dma.cs, buf, usage)) {
- return TRUE;
+ if (ctx-rings.dma.cs) {
+ if (ctx-ws-cs_is_buffer_referenced(ctx-rings.dma.cs, buf,
usage)) {
+ return TRUE;
+ }
}
return FALSE;
}
@@ -211,10 +215,12 @@ void *r600_buffer_mmap_sync_with_rings(struct
r600_context *ctx,
return NULL;
}
}
- if (ctx-ws-cs_is_buffer_referenced(ctx-rings.dma.cs,
resource-cs_buf, rusage) ctx-rings.dma.cs-cdw) {
- ctx-rings.dma.flush(ctx, flags);
- if (usage PIPE_TRANSFER_DONTBLOCK) {
- return NULL;
+ if (ctx-rings.dma.cs) {
+ if (ctx-ws-cs_is_buffer_referenced(ctx-rings.dma.cs,
resource-cs_buf, rusage) ctx-rings.dma.cs-cdw) {
+ ctx-rings.dma.flush(ctx, flags);
+ if (usage PIPE_TRANSFER_DONTBLOCK) {
+ return NULL;
+ }
}
}
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index 31dcd05..0f51eb2 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -869,7 +869,7 @@ static INLINE unsigned r600_context_bo_reloc(struct
r600_context *ctx,
* look serialized from driver pov
*/
if (!ring-flushing) {
- if (ring == ctx-rings.gfx) {
+ if (ring == ctx-rings.gfx ctx-rings.dma.cs) {
/* flush dma ring */
ctx-rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
} else {
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index b547d64..9386f61 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -1274,7 +1274,9 @@ static void r600_draw_vbo(struct pipe_context *ctx, const
struct pipe_draw_info
}
/* make sure that the gfx ring is only one active */
- rctx-rings.dma.flush(rctx, RADEON_FLUSH_ASYNC);
+ if (rctx-rings.dma.cs) {
+ rctx-rings.dma.flush(rctx, RADEON_FLUSH_ASYNC);
+ }
if (!r600_update_derived_state(rctx)) {
/* useless to render because current rendering command
diff --git a/src/gallium/drivers/r600/r600_texture.c
b/src/gallium/drivers/r600/r600_texture.c
index 96c3729..1d04cc0 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -851,7 +851,9 @@ static
Mesa (master): r600g: real fix for non 3.8 kernel
Module: Mesa
Branch: master
Commit: da638781f63df2020f6e6ab537226cd58232bd99
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=da638781f63df2020f6e6ab537226cd58232bd99
Author: Jerome Glisse jgli...@redhat.com
Date: Mon Jan 28 17:14:09 2013 -0500
r600g: real fix for non 3.8 kernel
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/r600_pipe.h |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index 0f51eb2..3ff42d3 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -869,9 +869,11 @@ static INLINE unsigned r600_context_bo_reloc(struct
r600_context *ctx,
* look serialized from driver pov
*/
if (!ring-flushing) {
- if (ring == ctx-rings.gfx ctx-rings.dma.cs) {
- /* flush dma ring */
- ctx-rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
+ if (ring == ctx-rings.gfx) {
+ if (ctx-rings.dma.cs) {
+ /* flush dma ring */
+ ctx-rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
+ }
} else {
/* flush gfx ring */
ctx-rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (9.1): r600g: real fix for non 3.8 kernel
Module: Mesa
Branch: 9.1
Commit: d8d17441e2b5b777b12b3fdeea9d33aa7510f3f1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8d17441e2b5b777b12b3fdeea9d33aa7510f3f1
Author: Jerome Glisse jgli...@redhat.com
Date: Mon Jan 28 17:14:09 2013 -0500
r600g: real fix for non 3.8 kernel
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/r600_pipe.h |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index 0f51eb2..3ff42d3 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -869,9 +869,11 @@ static INLINE unsigned r600_context_bo_reloc(struct
r600_context *ctx,
* look serialized from driver pov
*/
if (!ring-flushing) {
- if (ring == ctx-rings.gfx ctx-rings.dma.cs) {
- /* flush dma ring */
- ctx-rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
+ if (ring == ctx-rings.gfx) {
+ if (ctx-rings.dma.cs) {
+ /* flush dma ring */
+ ctx-rings.dma.flush(ctx, RADEON_FLUSH_ASYNC);
+ }
} else {
/* flush gfx ring */
ctx-rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC);
___
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mesa-commit@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: use uint64_t instead of unsigned long for proper 32bits cpu support
Module: Mesa
Branch: master
Commit: e1598cb642334c809e6ec219d793e7bc85a213de
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e1598cb642334c809e6ec219d793e7bc85a213de
Author: Jerome Glisse jgli...@redhat.com
Date: Mon Jan 28 19:07:10 2013 -0500
r600g: use uint64_t instead of unsigned long for proper 32bits cpu support
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_hw_context.c |6 +++---
src/gallium/drivers/r600/evergreen_state.c |4 ++--
src/gallium/drivers/r600/r600.h | 12 ++--
src/gallium/drivers/r600/r600_hw_context.c |6 +++---
src/gallium/drivers/r600/r600_state.c |4 ++--
5 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c
b/src/gallium/drivers/r600/evergreen_hw_context.c
index ca4f4b3..bb47530 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -243,9 +243,9 @@ void evergreen_set_streamout_enable(struct r600_context
*ctx, unsigned buffer_en
void evergreen_dma_copy(struct r600_context *rctx,
struct pipe_resource *dst,
struct pipe_resource *src,
- unsigned long dst_offset,
- unsigned long src_offset,
- unsigned long size)
+ uint64_t dst_offset,
+ uint64_t src_offset,
+ uint64_t size)
{
struct radeon_winsys_cs *cs = rctx-rings.dma.cs;
unsigned i, ncopy, csize, sub_cmd, shift;
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index be1c427..0a3861f 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3481,7 +3481,7 @@ static void evergreen_dma_copy_tile(struct r600_context
*rctx,
unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split;
- unsigned long base, addr;
+ uint64_t base, addr;
/* make sure that the dma ring is only one active */
rctx-rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
@@ -3625,7 +3625,7 @@ boolean evergreen_dma_blit(struct pipe_context *ctx,
}
if (src_mode == dst_mode) {
- unsigned long dst_offset, src_offset;
+ uint64_t dst_offset, src_offset;
/* simple dma blit would do NOTE code here assume :
* src_box.x/y == 0
* dst_x/y == 0
diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index a383c90..08b77e4 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -174,9 +174,9 @@ void r600_need_dma_space(struct r600_context *ctx, unsigned
num_dw);
void r600_dma_copy(struct r600_context *rctx,
struct pipe_resource *dst,
struct pipe_resource *src,
- unsigned long dst_offset,
- unsigned long src_offset,
- unsigned long size);
+ uint64_t dst_offset,
+ uint64_t src_offset,
+ uint64_t size);
boolean r600_dma_blit(struct pipe_context *ctx,
struct pipe_resource *dst,
unsigned dst_level,
@@ -187,9 +187,9 @@ boolean r600_dma_blit(struct pipe_context *ctx,
void evergreen_dma_copy(struct r600_context *rctx,
struct pipe_resource *dst,
struct pipe_resource *src,
- unsigned long dst_offset,
- unsigned long src_offset,
- unsigned long size);
+ uint64_t dst_offset,
+ uint64_t src_offset,
+ uint64_t size);
boolean evergreen_dma_blit(struct pipe_context *ctx,
struct pipe_resource *dst,
unsigned dst_level,
diff --git a/src/gallium/drivers/r600/r600_hw_context.c
b/src/gallium/drivers/r600/r600_hw_context.c
index ebafd97..23f488a 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -1160,9 +1160,9 @@ void r600_need_dma_space(struct r600_context *ctx,
unsigned num_dw)
void r600_dma_copy(struct r600_context *rctx,
struct pipe_resource *dst,
struct pipe_resource *src,
- unsigned long dst_offset,
- unsigned long src_offset,
- unsigned long size)
+ uint64_t dst_offset,
+ uint64_t src_offset,
+ uint64_t size)
{
struct radeon_winsys_cs *cs = rctx-rings.dma.cs;
unsigned i, ncopy, csize, shift;
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 6b4b2c3..c0bc2a5 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium
Mesa (9.1): r600g: use uint64_t instead of unsigned long for proper 32bits cpu support
Module: Mesa
Branch: 9.1
Commit: af2d8f8072c53d4c63ed22b74f78213c1181c1eb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=af2d8f8072c53d4c63ed22b74f78213c1181c1eb
Author: Jerome Glisse jgli...@redhat.com
Date: Mon Jan 28 19:07:10 2013 -0500
r600g: use uint64_t instead of unsigned long for proper 32bits cpu support
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_hw_context.c |6 +++---
src/gallium/drivers/r600/evergreen_state.c |4 ++--
src/gallium/drivers/r600/r600.h | 12 ++--
src/gallium/drivers/r600/r600_hw_context.c |6 +++---
src/gallium/drivers/r600/r600_state.c |4 ++--
5 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c
b/src/gallium/drivers/r600/evergreen_hw_context.c
index ca4f4b3..bb47530 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -243,9 +243,9 @@ void evergreen_set_streamout_enable(struct r600_context
*ctx, unsigned buffer_en
void evergreen_dma_copy(struct r600_context *rctx,
struct pipe_resource *dst,
struct pipe_resource *src,
- unsigned long dst_offset,
- unsigned long src_offset,
- unsigned long size)
+ uint64_t dst_offset,
+ uint64_t src_offset,
+ uint64_t size)
{
struct radeon_winsys_cs *cs = rctx-rings.dma.cs;
unsigned i, ncopy, csize, sub_cmd, shift;
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index be1c427..0a3861f 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -3481,7 +3481,7 @@ static void evergreen_dma_copy_tile(struct r600_context
*rctx,
unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split;
- unsigned long base, addr;
+ uint64_t base, addr;
/* make sure that the dma ring is only one active */
rctx-rings.gfx.flush(rctx, RADEON_FLUSH_ASYNC);
@@ -3625,7 +3625,7 @@ boolean evergreen_dma_blit(struct pipe_context *ctx,
}
if (src_mode == dst_mode) {
- unsigned long dst_offset, src_offset;
+ uint64_t dst_offset, src_offset;
/* simple dma blit would do NOTE code here assume :
* src_box.x/y == 0
* dst_x/y == 0
diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index a383c90..08b77e4 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -174,9 +174,9 @@ void r600_need_dma_space(struct r600_context *ctx, unsigned
num_dw);
void r600_dma_copy(struct r600_context *rctx,
struct pipe_resource *dst,
struct pipe_resource *src,
- unsigned long dst_offset,
- unsigned long src_offset,
- unsigned long size);
+ uint64_t dst_offset,
+ uint64_t src_offset,
+ uint64_t size);
boolean r600_dma_blit(struct pipe_context *ctx,
struct pipe_resource *dst,
unsigned dst_level,
@@ -187,9 +187,9 @@ boolean r600_dma_blit(struct pipe_context *ctx,
void evergreen_dma_copy(struct r600_context *rctx,
struct pipe_resource *dst,
struct pipe_resource *src,
- unsigned long dst_offset,
- unsigned long src_offset,
- unsigned long size);
+ uint64_t dst_offset,
+ uint64_t src_offset,
+ uint64_t size);
boolean evergreen_dma_blit(struct pipe_context *ctx,
struct pipe_resource *dst,
unsigned dst_level,
diff --git a/src/gallium/drivers/r600/r600_hw_context.c
b/src/gallium/drivers/r600/r600_hw_context.c
index ebafd97..23f488a 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -1160,9 +1160,9 @@ void r600_need_dma_space(struct r600_context *ctx,
unsigned num_dw)
void r600_dma_copy(struct r600_context *rctx,
struct pipe_resource *dst,
struct pipe_resource *src,
- unsigned long dst_offset,
- unsigned long src_offset,
- unsigned long size)
+ uint64_t dst_offset,
+ uint64_t src_offset,
+ uint64_t size)
{
struct radeon_winsys_cs *cs = rctx-rings.dma.cs;
unsigned i, ncopy, csize, shift;
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 6b4b2c3..c0bc2a5 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium
Mesa (master): r600g/radeon/winsys: indentation cleanup
Module: Mesa
Branch: master
Commit: d499ff98cd69c9ec6c43ad8ececa4c3b61889ab9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d499ff98cd69c9ec6c43ad8ececa4c3b61889ab9
Author: Jerome Glisse jgli...@redhat.com
Date: Fri Jan 4 11:46:13 2013 -0500
r600g/radeon/winsys: indentation cleanup
Signed-off-by: Jerome Glisse jgli...@redhat.com
Reviewed-by: Alex Deucher alexander.deuc...@amd.com
Reviewed-by: Marek Olšák mar...@gmail.com
---
src/gallium/drivers/r600/r600_pipe.c | 18 +-
src/gallium/drivers/r600/r600_pipe.h |2 +-
src/gallium/winsys/radeon/drm/radeon_drm_bo.c |3 +--
src/gallium/winsys/radeon/drm/radeon_drm_cs.h |2 +-
4 files changed, 12 insertions(+), 13 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index f6db3bf..7a7a431 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -292,21 +292,21 @@ static struct pipe_context *r600_create_context(struct
pipe_screen *screen, void
rctx-cs = rctx-ws-cs_create(rctx-ws);
rctx-ws-cs_set_flush_callback(rctx-cs, r600_flush_from_winsys, rctx);
-rctx-uploader = u_upload_create(rctx-context, 1024 * 1024, 256,
- PIPE_BIND_INDEX_BUFFER |
- PIPE_BIND_CONSTANT_BUFFER);
-if (!rctx-uploader)
-goto fail;
+ rctx-uploader = u_upload_create(rctx-context, 1024 * 1024, 256,
+ PIPE_BIND_INDEX_BUFFER |
+ PIPE_BIND_CONSTANT_BUFFER);
+ if (!rctx-uploader)
+ goto fail;
rctx-allocator_fetch_shader = u_suballocator_create(rctx-context, 64
* 1024, 256,
0,
PIPE_USAGE_STATIC, FALSE);
-if (!rctx-allocator_fetch_shader)
-goto fail;
+ if (!rctx-allocator_fetch_shader)
+ goto fail;
rctx-allocator_so_filled_size = u_suballocator_create(rctx-context,
4096, 4,
- 0,
PIPE_USAGE_STATIC, TRUE);
+ 0,
PIPE_USAGE_STATIC, TRUE);
if (!rctx-allocator_so_filled_size)
-goto fail;
+ goto fail;
rctx-blitter = util_blitter_create(rctx-context);
if (rctx-blitter == NULL)
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index 6b7c053..934a6f5 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -408,7 +408,7 @@ struct r600_context {
struct radeon_winsys*ws;
struct radeon_winsys_cs *cs;
struct blitter_context *blitter;
- struct u_upload_mgr *uploader;
+ struct u_upload_mgr *uploader;
struct u_suballocator *allocator_so_filled_size;
struct u_suballocator *allocator_fetch_shader;
struct util_slab_mempoolpool_transfers;
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 07e92c5..897e962 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -802,8 +802,7 @@ static void radeon_bo_set_tiling(struct pb_buffer *_buf,
sizeof(args));
}
-static struct radeon_winsys_cs_handle *radeon_drm_get_cs_handle(
-struct pb_buffer *_buf)
+static struct radeon_winsys_cs_handle *radeon_drm_get_cs_handle(struct
pb_buffer *_buf)
{
/* return radeon_bo. */
return (struct radeon_winsys_cs_handle*)get_radeon_bo(_buf);
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
index 6336d3a..286eb6a 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_cs.h
@@ -33,7 +33,7 @@
struct radeon_cs_context {
uint32_tbuf[RADEON_MAX_CMDBUF_DWORDS];
-int fd;
+int fd;
struct drm_radeon_cscs;
struct drm_radeon_cs_chunk chunks[3];
uint64_tchunk_array[3];
___
mesa-commit mailing list
mesa-commit@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeon/winsys: move radeon family/ class identification to winsys
Module: Mesa
Branch: master
Commit: ca474f98f2cda5cb333e9f851c7e0e31c9a6f823
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca474f98f2cda5cb333e9f851c7e0e31c9a6f823
Author: Jerome Glisse jgli...@redhat.com
Date: Fri Jan 4 16:34:52 2013 -0500
radeon/winsys: move radeon family/class identification to winsys
Upcoming async dma support rely on winsys knowing about GPU families.
Signed-off-by: Jerome Glisse jgli...@redhat.com
Reviewed-by: Alex Deucher alexander.deuc...@amd.com
Reviewed-by: Marek Olšák mar...@gmail.com
---
src/gallium/drivers/r300/r300_chipset.c | 57 ++-
src/gallium/drivers/r300/r300_chipset.h | 27 -
src/gallium/drivers/r300/r300_emit.c |4 +-
src/gallium/drivers/r300/r300_query.c |2 +-
src/gallium/drivers/r300/r300_texture_desc.c | 12 +-
src/gallium/drivers/r600/r600.h | 37 ---
src/gallium/drivers/r600/r600_asm.c |5 +-
src/gallium/drivers/r600/r600_pipe.c | 32 ++
src/gallium/drivers/r600/r600_shader.c|1 +
src/gallium/drivers/radeonsi/r600.h | 12 --
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 96 +++---
src/gallium/winsys/radeon/drm/radeon_drm_winsys.h |6 +-
src/gallium/winsys/radeon/drm/radeon_winsys.h | 112 +
13 files changed, 227 insertions(+), 176 deletions(-)
diff --git a/src/gallium/drivers/r300/r300_chipset.c
b/src/gallium/drivers/r300/r300_chipset.c
index beaa1f4..11061ed 100644
--- a/src/gallium/drivers/r300/r300_chipset.c
+++ b/src/gallium/drivers/r300/r300_chipset.c
@@ -22,6 +22,7 @@
* USE OR OTHER DEALINGS IN THE SOFTWARE. */
#include r300_chipset.h
+#include ../../winsys/radeon/drm/radeon_winsys.h
#include util/u_debug.h
#include util/u_memory.h
@@ -62,7 +63,7 @@ void r300_parse_chipset(uint32_t pci_id, struct
r300_capabilities* caps)
switch (pci_id) {
#define CHIPSET(pci_id, name, chipfamily) \
case pci_id: \
-caps-family = CHIP_FAMILY_##chipfamily; \
+caps-family = CHIP_##chipfamily; \
break;
#include pci_ids/r300_pci_ids.h
#undef CHIPSET
@@ -81,71 +82,71 @@ void r300_parse_chipset(uint32_t pci_id, struct
r300_capabilities* caps)
switch (caps-family) {
-case CHIP_FAMILY_R300:
-case CHIP_FAMILY_R350:
+case CHIP_R300:
+case CHIP_R350:
caps-high_second_pipe = TRUE;
caps-num_vert_fpus = 4;
caps-hiz_ram = R300_HIZ_LIMIT;
caps-zmask_ram = PIPE_ZMASK_SIZE;
break;
-case CHIP_FAMILY_RV350:
-case CHIP_FAMILY_RV370:
+case CHIP_RV350:
+case CHIP_RV370:
caps-high_second_pipe = TRUE;
caps-num_vert_fpus = 2;
caps-zmask_ram = RV3xx_ZMASK_SIZE;
break;
-case CHIP_FAMILY_RV380:
+case CHIP_RV380:
caps-high_second_pipe = TRUE;
caps-num_vert_fpus = 2;
caps-hiz_ram = R300_HIZ_LIMIT;
caps-zmask_ram = RV3xx_ZMASK_SIZE;
break;
-case CHIP_FAMILY_RS400:
-case CHIP_FAMILY_RS600:
-case CHIP_FAMILY_RS690:
-case CHIP_FAMILY_RS740:
+case CHIP_RS400:
+case CHIP_RS600:
+case CHIP_RS690:
+case CHIP_RS740:
break;
-case CHIP_FAMILY_RC410:
-case CHIP_FAMILY_RS480:
+case CHIP_RC410:
+case CHIP_RS480:
caps-zmask_ram = RV3xx_ZMASK_SIZE;
break;
-case CHIP_FAMILY_R420:
-case CHIP_FAMILY_R423:
-case CHIP_FAMILY_R430:
-case CHIP_FAMILY_R480:
-case CHIP_FAMILY_R481:
-case CHIP_FAMILY_RV410:
+case CHIP_R420:
+case CHIP_R423:
+case CHIP_R430:
+case CHIP_R480:
+case CHIP_R481:
+case CHIP_RV410:
caps-num_vert_fpus = 6;
caps-hiz_ram = R300_HIZ_LIMIT;
caps-zmask_ram = PIPE_ZMASK_SIZE;
break;
-case CHIP_FAMILY_R520:
+case CHIP_R520:
caps-num_vert_fpus = 8;
caps-hiz_ram = R300_HIZ_LIMIT;
caps-zmask_ram = PIPE_ZMASK_SIZE;
break;
-case CHIP_FAMILY_RV515:
+case CHIP_RV515:
caps-num_vert_fpus = 2;
caps-hiz_ram = R300_HIZ_LIMIT;
caps-zmask_ram = PIPE_ZMASK_SIZE;
break;
-case CHIP_FAMILY_RV530:
+case CHIP_RV530:
caps-num_vert_fpus = 5;
caps-hiz_ram = RV530_HIZ_LIMIT;
caps-zmask_ram = PIPE_ZMASK_SIZE;
break;
-case CHIP_FAMILY_R580:
-case CHIP_FAMILY_RV560:
-case CHIP_FAMILY_RV570:
+case CHIP_R580:
+case CHIP_RV560:
+case CHIP_RV570:
caps-num_vert_fpus = 8;
caps-hiz_ram = RV530_HIZ_LIMIT;
caps-zmask_ram = PIPE_ZMASK_SIZE;
@@ -153,12 +154,12 @@ void r300_parse_chipset(uint32_t pci_id, struct
r300_capabilities* caps)
}
caps-num_tex_units = 16;
-caps-is_r400 = caps-family = CHIP_FAMILY_R420 caps-family
CHIP_FAMILY_RV515;
-caps-is_r500 = caps-family = CHIP_FAMILY_RV515;
-caps
Mesa (master): r600g: rework flusing and synchronization pattern v7
Module: Mesa
Branch: master
Commit: 24b1206ab2dcd506aaac3ef656aebc8bc20cd27a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=24b1206ab2dcd506aaac3ef656aebc8bc20cd27a
Author: Jerome Glisse jgli...@redhat.com
Date: Thu Nov 1 16:09:40 2012 -0400
r600g: rework flusing and synchronization pattern v7
This bring r600g allmost inline with closed source driver when
it comes to flushing and synchronization pattern.
v2-v4: history lost somewhere in outer space
v5: Fix compute size of flushing, use define for flags, update
worst case cs size requirement for flush, treat rs780 and
newer as r7xx when it comes to streamout.
v6: Fix num dw computation for framebuffer state, remove dead
code, use define instead of hardcoded value.
v7: Remove dead code
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_compute.c |8 +-
.../drivers/r600/evergreen_compute_internal.c |4 +-
src/gallium/drivers/r600/evergreen_state.c |4 +-
src/gallium/drivers/r600/r600.h| 16 +--
src/gallium/drivers/r600/r600_hw_context.c | 178 ++--
src/gallium/drivers/r600/r600_hw_context_priv.h|2 +-
src/gallium/drivers/r600/r600_state.c | 20 ++-
src/gallium/drivers/r600/r600_state_common.c | 19 +--
8 files changed, 89 insertions(+), 162 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index 66b0cc6..ea75d80 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -98,7 +98,7 @@ static void evergreen_cs_set_vertex_buffer(
/* The vertex instructions in the compute shaders use the texture cache,
* so we need to invalidate it. */
- rctx-flags |= R600_CONTEXT_TEX_FLUSH;
+ rctx-flags |= R600_CONTEXT_GPU_FLUSH;
state-enabled_mask |= 1 vb_index;
state-dirty_mask |= 1 vb_index;
state-atom.dirty = true;
@@ -329,7 +329,7 @@ static void compute_emit_cs(struct r600_context *ctx, const
uint *block_layout,
*/
r600_emit_command_buffer(ctx-cs, ctx-start_compute_cs_cmd);
- ctx-flags |= R600_CONTEXT_CB_FLUSH;
+ ctx-flags |= R600_CONTEXT_WAIT_IDLE | R600_CONTEXT_FLUSH_AND_INV;
r600_flush_emit(ctx);
/* Emit colorbuffers. */
@@ -409,7 +409,7 @@ static void compute_emit_cs(struct r600_context *ctx, const
uint *block_layout,
/* XXX evergreen_flush_emit() hardcodes the CP_COHER_SIZE to 0x
*/
- ctx-flags |= R600_CONTEXT_CB_FLUSH;
+ ctx-flags |= R600_CONTEXT_GPU_FLUSH;
r600_flush_emit(ctx);
#if 0
@@ -468,7 +468,7 @@ void evergreen_emit_cs_shader(
r600_write_value(cs, r600_context_bo_reloc(rctx, kernel-code_bo,
RADEON_USAGE_READ));
- rctx-flags |= R600_CONTEXT_SHADERCONST_FLUSH;
+ rctx-flags |= R600_CONTEXT_GPU_FLUSH;
}
static void evergreen_launch_grid(
diff --git a/src/gallium/drivers/r600/evergreen_compute_internal.c
b/src/gallium/drivers/r600/evergreen_compute_internal.c
index f7aebf2..94f556f 100644
--- a/src/gallium/drivers/r600/evergreen_compute_internal.c
+++ b/src/gallium/drivers/r600/evergreen_compute_internal.c
@@ -545,7 +545,7 @@ void evergreen_set_tex_resource(
util_format_get_blockwidth(tmp-resource.b.b.format) *
view-base.texture-width0*height*depth;
- pipe-ctx-flags |= R600_CONTEXT_TEX_FLUSH;
+ pipe-ctx-flags |= R600_CONTEXT_GPU_FLUSH;
evergreen_emit_force_reloc(res);
evergreen_emit_force_reloc(res);
@@ -604,7 +604,7 @@ void evergreen_set_const_cache(
res-usage = RADEON_USAGE_READ;
res-coher_bo_size = size;
- pipe-ctx-flags |= R600_CONTEXT_SHADERCONST_FLUSH;
+ pipe-ctx-flags |= R600_CONTEXT_GPU_FLUSH;
}
struct r600_resource* r600_compute_buffer_alloc_vram(
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 996c1b4..58964c4 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1557,14 +1557,14 @@ static void evergreen_set_framebuffer_state(struct
pipe_context *ctx,
uint32_t i, log_samples;
if (rctx-framebuffer.state.nr_cbufs) {
- rctx-flags |= R600_CONTEXT_CB_FLUSH;
+ rctx-flags |= R600_CONTEXT_WAIT_IDLE |
R600_CONTEXT_FLUSH_AND_INV;
if (rctx-framebuffer.state.cbufs[0]-texture-nr_samples 1) {
rctx-flags |= R600_CONTEXT_FLUSH_AND_INV_CB_META;
}
}
if (rctx-framebuffer.state.zsbuf) {
- rctx-flags |= R600_CONTEXT_DB_FLUSH;
+ rctx-flags |= R600_CONTEXT_WAIT_IDLE |
R600_CONTEXT_FLUSH_AND_INV;
}
util_copy_framebuffer_state(rctx
Mesa (master): r600g: add htile support v16
Module: Mesa
Branch: master
Commit: 6532eb17baff6e61b427f29e076883f8941ae664
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6532eb17baff6e61b427f29e076883f8941ae664
Author: Jerome Glisse jgli...@redhat.com
Date: Thu Oct 11 10:40:30 2012 -0400
r600g: add htile support v16
htile is used for HiZ and HiS support and fast Z/S clears.
This commit just adds the htile setup and Fast Z clear.
We don't take full advantage of HiS with that patch.
v2 really use fast clear, still random issue with some tiles
need to try more flush combination, fix depth/stencil
texture decompression
v3 fix random issue on r6xx/r7xx
v4 rebase on top of lastest mesa, disable CB export when clearing
htile surface to avoid wasting bandwidth
v5 resummarize htile surface when uploading z value. Fix z/stencil
decompression, the custom blitter with custom dsa is no longer
needed.
v6 Reorganize render control/override update mecanism, fixing more
issues in the process.
v7 Add nop after depth surface base update to work around some htile
flushing issue. For htile to 8x8 on r6xx/r7xx as other combination
have issue. Do not enable hyperz when flushing/uncompressing
depth buffer.
v8 Fix htile surface, preload and prefetch setup. Only set preload
and prefetch on htile surface clear like fglrx. Record depth
clear value per level. Support several level for the htile
surface. First depth clear can't be a fast clear.
v9 Fix comments, properly account new register in emit function,
disable fast zclear if clearing different layer of texture
array to different value
v10 Disable hyperz for texture array making test simpler. Force
db_misc_state update when no depth buffer is bound. Remove
unused variable, rename depth_clearstencil to depth_clear.
Don't allocate htile surface for flushed depth. Something
broken the cliprect change, this need to be investigated.
v11 Rebase on top of newer mesa
v12 Rebase on top of newer mesa
v13 Rebase on top of newer mesa, htile surface need to be initialized
to zero, somehow special casing first clear to not use fast clear
and thus initialize the htile surface with proper value does not
work in all case.
v14 Use resource not texture for htile buffer make the htile buffer
size computation easier and simpler. Disable preload on evergreen
as its still troublesome in some case
v15 Cleanup some comment and remove some left over
v16 Define name for bit 20 of CP_COHER_CNTL
Signed-off-by: Pierre-Eric Pelloux-Prayer pell...@gmail.com
Signed-off-by: Alex Deucher alexander.deuc...@amd.com
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_state.c | 65 ---
src/gallium/drivers/r600/evergreend.h |2 +
src/gallium/drivers/r600/r600_blit.c | 28
src/gallium/drivers/r600/r600_hw_context.c |7 ++-
src/gallium/drivers/r600/r600_pipe.c |8 +++
src/gallium/drivers/r600/r600_pipe.h | 26 +++
src/gallium/drivers/r600/r600_resource.h |9
src/gallium/drivers/r600/r600_state.c | 57 ++--
src/gallium/drivers/r600/r600_texture.c| 38
src/gallium/drivers/r600/r600d.h |5 ++
10 files changed, 221 insertions(+), 24 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 58964c4..032af78 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1545,6 +1545,18 @@ static void evergreen_init_depth_surface(struct
r600_context *rctx,
S_028044_FORMAT(V_028044_STENCIL_8);
}
+ surf-htile_enabled = 0;
+ /* use htile only for first level */
+ if (rtex-htile !level) {
+ surf-htile_enabled = 1;
+ surf-db_htile_data_base = 0;
+ surf-db_htile_surface = S_028ABC_HTILE_WIDTH(1) |
+ S_028ABC_HTILE_HEIGHT(1) |
+ S_028ABC_LINEAR(1);
+ surf-db_depth_info |= S_028040_TILE_SURFACE_ENABLE(1);
+ surf-db_preload_control = 0;
+ }
+
surf-depth_initialized = true;
}
@@ -1625,6 +1637,16 @@ static void evergreen_set_framebuffer_state(struct
pipe_context *ctx,
rctx-poly_offset_state.zs_format =
state-zsbuf-format;
rctx-poly_offset_state.atom.dirty = true;
}
+
+ if (rctx-db_state.rsurf != surf) {
+ rctx-db_state.rsurf = surf;
+ rctx-db_state.atom.dirty = true;
+ rctx-db_misc_state.atom.dirty = true;
+ }
+ } else if (rctx-db_state.rsurf) {
+ rctx-db_state.rsurf = NULL;
+ rctx-db_state.atom.dirty = true;
+ rctx-db_misc_state.atom.dirty = true
Mesa (master): r600g: add cs tracing infrastructure for lockup pin pointing
Module: Mesa
Branch: master
Commit: e8ca1a53a625544ea30b394be905ff7e51d78af6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e8ca1a53a625544ea30b394be905ff7e51d78af6
Author: Jerome Glisse jgli...@redhat.com
Date: Wed Dec 19 12:23:50 2012 -0500
r600g: add cs tracing infrastructure for lockup pin pointing
It's a build time option you need to set R600_TRACE_CS to 1 and it
will print to stderr all cs along as cs trace point value which
gave last offset into a cs process by the GPU.
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/r600_hw_context.c | 41 +++
src/gallium/drivers/r600/r600_hw_context_priv.h |5 ++-
src/gallium/drivers/r600/r600_pipe.c| 20 +++
src/gallium/drivers/r600/r600_pipe.h| 16 +
src/gallium/drivers/r600/r600_state_common.c| 26 ++
5 files changed, 106 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_hw_context.c
b/src/gallium/drivers/r600/r600_hw_context.c
index cdd31a4..6c8cb9d 100644
--- a/src/gallium/drivers/r600/r600_hw_context.c
+++ b/src/gallium/drivers/r600/r600_hw_context.c
@@ -27,6 +27,7 @@
#include r600d.h
#include util/u_memory.h
#include errno.h
+#include unistd.h
/* Get backends mask */
void r600_get_backend_mask(struct r600_context *ctx)
@@ -369,6 +370,11 @@ void r600_need_cs_space(struct r600_context *ctx, unsigned
num_dw,
for (i = 0; i R600_NUM_ATOMS; i++) {
if (ctx-atoms[i] ctx-atoms[i]-dirty) {
num_dw += ctx-atoms[i]-num_dw;
+#if R600_TRACE_CS
+ if (ctx-screen-trace_bo) {
+ num_dw += R600_TRACE_CS_DWORDS;
+ }
+#endif
}
}
@@ -376,6 +382,11 @@ void r600_need_cs_space(struct r600_context *ctx, unsigned
num_dw,
/* The upper-bound of how much space a draw command would take.
*/
num_dw += R600_MAX_FLUSH_CS_DWORDS + R600_MAX_DRAW_CS_DWORDS;
+#if R600_TRACE_CS
+ if (ctx-screen-trace_bo) {
+ num_dw += R600_TRACE_CS_DWORDS;
+ }
+#endif
}
/* Count in queries_suspend. */
@@ -717,7 +728,37 @@ void r600_context_flush(struct r600_context *ctx, unsigned
flags)
}
/* Flush the CS. */
+#if R600_TRACE_CS
+ if (ctx-screen-trace_bo) {
+ struct r600_screen *rscreen = ctx-screen;
+ unsigned i;
+
+ for (i = 0; i cs-cdw; i++) {
+ fprintf(stderr, [%4d] [%5d] 0x%08x\n,
rscreen-cs_count, i, cs-buf[i]);
+ }
+ rscreen-cs_count++;
+ }
+#endif
ctx-ws-cs_flush(ctx-cs, flags);
+#if R600_TRACE_CS
+ if (ctx-screen-trace_bo) {
+ struct r600_screen *rscreen = ctx-screen;
+ unsigned i;
+
+ for (i = 0; i 10; i++) {
+ usleep(5);
+ if (!ctx-ws-buffer_is_busy(rscreen-trace_bo-buf,
RADEON_USAGE_READWRITE)) {
+ break;
+ }
+ }
+ if (i == 10) {
+ fprintf(stderr, timeout on cs lockup likely happen at
cs %d dw %d\n,
+ rscreen-trace_ptr[1], rscreen-trace_ptr[0]);
+ } else {
+ fprintf(stderr, cs %d executed in %dms\n,
rscreen-trace_ptr[1], i * 5);
+ }
+ }
+#endif
r600_begin_new_cs(ctx);
}
diff --git a/src/gallium/drivers/r600/r600_hw_context_priv.h
b/src/gallium/drivers/r600/r600_hw_context_priv.h
index 050c472..692e6ec 100644
--- a/src/gallium/drivers/r600/r600_hw_context_priv.h
+++ b/src/gallium/drivers/r600/r600_hw_context_priv.h
@@ -29,8 +29,9 @@
#include r600_pipe.h
/* the number of CS dwords for flushing and drawing */
-#define R600_MAX_FLUSH_CS_DWORDS 12
-#define R600_MAX_DRAW_CS_DWORDS 34
+#define R600_MAX_FLUSH_CS_DWORDS 12
+#define R600_MAX_DRAW_CS_DWORDS34
+#define R600_TRACE_CS_DWORDS 7
/* these flags are used in register flags and added into block flags */
#define REG_FLAG_NEED_BO 1
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index 290aa51..b02f875 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -723,6 +723,12 @@ static void r600_destroy_screen(struct pipe_screen*
pscreen)
rscreen-ws-buffer_unmap(rscreen-fences.bo-cs_buf);
pipe_resource_reference((struct
pipe_resource**)rscreen-fences.bo, NULL);
}
+#if R600_TRACE_CS
+ if (rscreen-trace_bo) {
+ rscreen-ws-buffer_unmap(rscreen-trace_bo-cs_buf);
+ pipe_resource_reference((struct
pipe_resource**)rscreen-trace_bo, NULL);
+ }
+#endif
Mesa (master): Revert r600g: work around ddx over alignment
Module: Mesa
Branch: master
Commit: 50880314e35661f0ea7ab3f092741df79c855d90
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=50880314e35661f0ea7ab3f092741df79c855d90
Author: Jerome Glisse jgli...@redhat.com
Date: Wed Dec 19 09:56:17 2012 -0500
Revert r600g: work around ddx over alignment
This reverts commit d8287bac1fd4a77abc2db38de134f14176740d23.
Cause more issue than it fix. Need to think of a proper solution.
---
src/gallium/drivers/r600/r600_texture.c | 12 +++-
1 files changed, 3 insertions(+), 9 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_texture.c
b/src/gallium/drivers/r600/r600_texture.c
index 9373451..56e9b64 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -89,8 +89,7 @@ static int r600_init_surface(struct r600_screen *rscreen,
struct radeon_surface *surface,
const struct pipe_resource *ptex,
unsigned array_mode,
-bool is_flushed_depth,
-bool from_ddx)
+bool is_flushed_depth)
{
const struct util_format_description *desc =
util_format_description(ptex-format);
@@ -108,10 +107,6 @@ static int r600_init_surface(struct r600_screen *rscreen,
surface-array_size = 1;
surface-last_level = ptex-last_level;
- if (from_ddx) {
- surface-npix_y = align(surface-npix_y, 8);
- }
-
if (rscreen-chip_class = EVERGREEN !is_flushed_depth
ptex-format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
surface-bpe = 4; /* stencil is allocated separately on
evergreen */
@@ -544,8 +539,7 @@ struct pipe_resource *r600_texture_create(struct
pipe_screen *screen,
}
r = r600_init_surface(rscreen, surface, templ, array_mode,
- templ-flags R600_RESOURCE_FLAG_FLUSHED_DEPTH,
- false);
+ templ-flags R600_RESOURCE_FLAG_FLUSHED_DEPTH);
if (r) {
return NULL;
}
@@ -633,7 +627,7 @@ struct pipe_resource *r600_texture_from_handle(struct
pipe_screen *screen,
else
array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
- r = r600_init_surface(rscreen, surface, templ, array_mode, false,
true);
+ r = r600_init_surface(rscreen, surface, templ, array_mode, false);
if (r) {
return NULL;
}
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Mesa (master): r600g: work around ddx over alignment
Module: Mesa
Branch: master
Commit: d8287bac1fd4a77abc2db38de134f14176740d23
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8287bac1fd4a77abc2db38de134f14176740d23
Author: Jerome Glisse jgli...@redhat.com
Date: Tue Dec 18 12:45:31 2012 -0500
r600g: work around ddx over alignment
This force surface allocated from ddx to be consider as height
aligned on 8 and fix 1D-2D tiling transition that result from
this.
Signed-off-by: Jerome Glisse jgli...@redhat.com
Reviewed-by: Marek Olšák mar...@gmail.com
---
src/gallium/drivers/r600/r600_texture.c | 12 +---
1 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_texture.c
b/src/gallium/drivers/r600/r600_texture.c
index 56e9b64..9373451 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -89,7 +89,8 @@ static int r600_init_surface(struct r600_screen *rscreen,
struct radeon_surface *surface,
const struct pipe_resource *ptex,
unsigned array_mode,
-bool is_flushed_depth)
+bool is_flushed_depth,
+bool from_ddx)
{
const struct util_format_description *desc =
util_format_description(ptex-format);
@@ -107,6 +108,10 @@ static int r600_init_surface(struct r600_screen *rscreen,
surface-array_size = 1;
surface-last_level = ptex-last_level;
+ if (from_ddx) {
+ surface-npix_y = align(surface-npix_y, 8);
+ }
+
if (rscreen-chip_class = EVERGREEN !is_flushed_depth
ptex-format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
surface-bpe = 4; /* stencil is allocated separately on
evergreen */
@@ -539,7 +544,8 @@ struct pipe_resource *r600_texture_create(struct
pipe_screen *screen,
}
r = r600_init_surface(rscreen, surface, templ, array_mode,
- templ-flags R600_RESOURCE_FLAG_FLUSHED_DEPTH);
+ templ-flags R600_RESOURCE_FLAG_FLUSHED_DEPTH,
+ false);
if (r) {
return NULL;
}
@@ -627,7 +633,7 @@ struct pipe_resource *r600_texture_from_handle(struct
pipe_screen *screen,
else
array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
- r = r600_init_surface(rscreen, surface, templ, array_mode, false);
+ r = r600_init_surface(rscreen, surface, templ, array_mode, false,
true);
if (r) {
return NULL;
}
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Mesa (master): r600g: avoid shader needing too many gpr to lockup the gpu v2
Module: Mesa
Branch: master
Commit: 470952f751d1327831c638ee369b7f0f2e20e6fb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=470952f751d1327831c638ee369b7f0f2e20e6fb
Author: Jerome Glisse jgli...@redhat.com
Date: Fri Oct 26 18:59:05 2012 -0400
r600g: avoid shader needing too many gpr to lockup the gpu v2
On r6xx/r7xx shader resource management need to make sure that the
shader does not goes over the gpr register limit. Each specific
asic has a maxmimum register that can be split btw shader stage.
For each stage the shader must not use more register than the
limit programmed.
v2: Print an error message when discarding draw. Don't add another
boolean to context structure, but rather propagate the discard
boolean through the call chain.
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/r600_pipe.h |2 +-
src/gallium/drivers/r600/r600_state.c| 67 ++
src/gallium/drivers/r600/r600_state_common.c | 27 ++-
3 files changed, 62 insertions(+), 34 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index 238ab16..342ab87 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -620,7 +620,7 @@ void *r600_create_db_flush_dsa(struct r600_context *rctx);
void *r600_create_resolve_blend(struct r600_context *rctx);
void *r700_create_resolve_blend(struct r600_context *rctx);
void *r600_create_decompress_blend(struct r600_context *rctx);
-void r600_adjust_gprs(struct r600_context *rctx);
+bool r600_adjust_gprs(struct r600_context *rctx);
boolean r600_is_format_supported(struct pipe_screen *screen,
enum pipe_format format,
enum pipe_texture_target target,
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index f3af568..5c52f3d 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -2186,36 +2186,61 @@ void r600_init_state_functions(struct r600_context
*rctx)
}
/* Adjust GPR allocation on R6xx/R7xx */
-void r600_adjust_gprs(struct r600_context *rctx)
+bool r600_adjust_gprs(struct r600_context *rctx)
{
- unsigned num_ps_gprs = rctx-default_ps_gprs;
- unsigned num_vs_gprs = rctx-default_vs_gprs;
+ unsigned num_ps_gprs = rctx-ps_shader-current-shader.bc.ngpr;
+ unsigned num_vs_gprs = rctx-vs_shader-current-shader.bc.ngpr;
+ unsigned new_num_ps_gprs = num_ps_gprs;
+ unsigned new_num_vs_gprs = num_vs_gprs;
+ unsigned cur_num_ps_gprs =
G_008C04_NUM_PS_GPRS(rctx-config_state.sq_gpr_resource_mgmt_1);
+ unsigned cur_num_vs_gprs =
G_008C04_NUM_VS_GPRS(rctx-config_state.sq_gpr_resource_mgmt_1);
+ unsigned def_num_ps_gprs = rctx-default_ps_gprs;
+ unsigned def_num_vs_gprs = rctx-default_vs_gprs;
+ unsigned def_num_clause_temp_gprs = rctx-r6xx_num_clause_temp_gprs;
+ /* hardware will reserve twice num_clause_temp_gprs */
+ unsigned max_gprs = def_num_ps_gprs + def_num_vs_gprs +
def_num_clause_temp_gprs * 2;
unsigned tmp;
- int diff;
- if (rctx-ps_shader-current-shader.bc.ngpr rctx-default_ps_gprs) {
- diff = rctx-ps_shader-current-shader.bc.ngpr -
rctx-default_ps_gprs;
- num_vs_gprs -= diff;
- num_ps_gprs += diff;
- }
-
- if (rctx-vs_shader-current-shader.bc.ngpr rctx-default_vs_gprs)
- {
- diff = rctx-vs_shader-current-shader.bc.ngpr -
rctx-default_vs_gprs;
- num_ps_gprs -= diff;
- num_vs_gprs += diff;
+ /* the sum of all SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS must = to max_gprs
*/
+ if (new_num_ps_gprs cur_num_ps_gprs || new_num_vs_gprs
cur_num_vs_gprs) {
+ /* try to use switch back to default */
+ if (new_num_ps_gprs def_num_ps_gprs || new_num_vs_gprs
def_num_vs_gprs) {
+ /* always privilege vs stage so that at worst we have
the
+* pixel stage producing wrong output (not the vertex
+* stage) */
+ new_num_ps_gprs = max_gprs - (new_num_vs_gprs +
def_num_clause_temp_gprs * 2);
+ new_num_vs_gprs = num_vs_gprs;
+ } else {
+ new_num_ps_gprs = def_num_ps_gprs;
+ new_num_vs_gprs = def_num_vs_gprs;
+ }
+ } else {
+ return true;
}
- tmp = 0;
- tmp |= S_008C04_NUM_PS_GPRS(num_ps_gprs);
- tmp |= S_008C04_NUM_VS_GPRS(num_vs_gprs);
- tmp |= S_008C04_NUM_CLAUSE_TEMP_GPRS(rctx-r6xx_num_clause_temp_gprs);
-
- if (tmp != rctx-config_state.sq_gpr_resource_mgmt_1) {
+ /* SQ_PGM_RESOURCES_*.NUM_GPRS must always be program to a value =
+* SQ_GPR_RESOURCE_MGMT*.NUM_*_GPRS otherwise the GPU
Mesa (master): r600g: avoid GPU doing constant preload from random address
Module: Mesa Branch: master Commit: 841c1b5f5423d7994ff0f6773639934d75bd1fca URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=841c1b5f5423d7994ff0f6773639934d75bd1fca Author: Jerome Glisse jgli...@redhat.com Date: Fri Sep 7 15:00:20 2012 -0400 r600g: avoid GPU doing constant preload from random address Previous command stream might have set any of the constant buffer and the previous address might no longer be valid thus GPU might preload constant from random invalid address and possibly triggering lockup. Signed-off-by: Jerome Glisse jgli...@redhat.com --- src/gallium/drivers/r600/evergreen_state.c | 20 src/gallium/drivers/r600/r600_state.c | 20 2 files changed, 40 insertions(+), 0 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 9a5183e..405d1b0 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -2602,6 +2602,26 @@ void evergreen_init_common_regs(struct r600_command_buffer *cb, r600_store_context_reg(cb, R_028848_SQ_PGM_RESOURCES_2_PS, S_028848_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); r600_store_context_reg(cb, R_028864_SQ_PGM_RESOURCES_2_VS, S_028864_SINGLE_ROUND(V_SQ_ROUND_NEAREST_EVEN)); + /* to avoid GPU doing any preloading of constant from random address */ + r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8); + r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */ + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8); + r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */ + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC, S_028354_SURFACE_SYNC_MASK(0xf)); return; diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index ccafdc6..b363dc1 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -2381,6 +2381,26 @@ void r600_init_atom_start_cs(struct r600_context *rctx) r600_store_value(cb, 0); /* R_0288C4_SQ_REDUC_RING_ITEMSIZE */ r600_store_value(cb, 0); /* R_0288C8_SQ_GS_VERT_ITEMSIZE */ + /* to avoid GPU doing any preloading of constant from random address */ + r600_store_context_reg_seq(cb, R_028140_ALU_CONST_BUFFER_SIZE_PS_0, 8); + r600_store_value(cb, 0); /* R_028140_ALU_CONST_BUFFER_SIZE_PS_0 */ + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_context_reg_seq(cb, R_028180_ALU_CONST_BUFFER_SIZE_VS_0, 8); + r600_store_value(cb, 0); /* R_028180_ALU_CONST_BUFFER_SIZE_VS_0 */ + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_value(cb, 0); + r600_store_context_reg_seq(cb, R_028A10_VGT_OUTPUT_PATH_CNTL, 13); r600_store_value(cb, 0); /* R_028A10_VGT_OUTPUT_PATH_CNTL */ r600_store_value(cb, 0); /* R_028A14_VGT_HOS_CNTL */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: fix num of dwords needed for alphatest_state atom
Module: Mesa
Branch: master
Commit: 935a72944751e6bc0a5df779eef44766c7b52baa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=935a72944751e6bc0a5df779eef44766c7b52baa
Author: Jerome Glisse jgli...@redhat.com
Date: Thu Sep 6 15:09:21 2012 -0400
r600g: fix num of dwords needed for alphatest_state atom
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/r600_state_common.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index 68f53c6..26af6f6 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -108,7 +108,7 @@ void r600_init_common_atoms(struct r600_context *rctx)
{
r600_init_atom(rctx-surface_sync_cmd.atom,r600_emit_surface_sync,
5, EMIT_EARLY);
r600_init_atom(rctx-r6xx_flush_and_inv_cmd,
r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY);
- r600_init_atom(rctx-alphatest_state.atom,
r600_emit_alphatest_state, 3, 0);
+ r600_init_atom(rctx-alphatest_state.atom,
r600_emit_alphatest_state, 6, 0);
r600_atom_dirty(rctx, rctx-alphatest_state.atom);
}
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Mesa (master): r600g: order atom emission v3
Module: Mesa
Branch: master
Commit: 5ceb87286f2e1b5b8527ba18a844abf450903175
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ceb87286f2e1b5b8527ba18a844abf450903175
Author: Jerome Glisse jgli...@redhat.com
Date: Wed Sep 5 15:18:24 2012 -0400
r600g: order atom emission v3
To avoid GPU lockup registers must be emited in a specific order
(no kidding ...). This patch rework atom emission so order in which
atom are emited in respect to each other is always the same. We
don't have any informations on what is the correct order so order
will need to be infered from fglrx command stream.
v2: add comment warning that atom order should not be taken lightly
v3: rebase on top of alphatest atom fix
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_compute.c |2 +-
src/gallium/drivers/r600/evergreen_state.c | 63 +
src/gallium/drivers/r600/r600_hw_context.c | 10 +++--
src/gallium/drivers/r600/r600_pipe.c |1 -
src/gallium/drivers/r600/r600_pipe.h | 33 --
src/gallium/drivers/r600/r600_state.c| 53 +++---
src/gallium/drivers/r600/r600_state_common.c | 36 ---
7 files changed, 116 insertions(+), 82 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index acf91ba..3533312 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -583,7 +583,7 @@ void evergreen_init_atom_start_compute_cs(struct
r600_context *ctx)
/* since all required registers are initialised in the
* start_compute_cs_cmd atom, we can EMIT_EARLY here.
*/
- r600_init_command_buffer(cb, 256, EMIT_EARLY);
+ r600_init_command_buffer(ctx, cb, 1, 256);
cb-pkt_flags = RADEON_CP_PACKET3_COMPUTE_MODE;
switch (ctx-family) {
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index bda8ed5..9a5183e 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2161,27 +2161,50 @@ static void cayman_emit_sample_mask(struct r600_context
*rctx, struct r600_atom
void evergreen_init_state_functions(struct r600_context *rctx)
{
- r600_init_atom(rctx-cb_misc_state.atom, evergreen_emit_cb_misc_state,
0, 0);
- r600_atom_dirty(rctx, rctx-cb_misc_state.atom);
- r600_init_atom(rctx-db_misc_state.atom, evergreen_emit_db_misc_state,
7, 0);
- r600_atom_dirty(rctx, rctx-db_misc_state.atom);
- r600_init_atom(rctx-vertex_buffer_state.atom,
evergreen_fs_emit_vertex_buffers, 0, 0);
- r600_init_atom(rctx-cs_vertex_buffer_state.atom,
evergreen_cs_emit_vertex_buffers, 0, 0);
- r600_init_atom(rctx-vs_constbuf_state.atom,
evergreen_emit_vs_constant_buffers, 0, 0);
- r600_init_atom(rctx-ps_constbuf_state.atom,
evergreen_emit_ps_constant_buffers, 0, 0);
- r600_init_atom(rctx-vs_samplers.views.atom,
evergreen_emit_vs_sampler_views, 0, 0);
- r600_init_atom(rctx-ps_samplers.views.atom,
evergreen_emit_ps_sampler_views, 0, 0);
- r600_init_atom(rctx-cs_shader_state.atom, evergreen_emit_cs_shader,
0, 0);
- r600_init_atom(rctx-vs_samplers.atom_sampler,
evergreen_emit_vs_sampler, 0, 0);
- r600_init_atom(rctx-ps_samplers.atom_sampler,
evergreen_emit_ps_sampler, 0, 0);
-
- if (rctx-chip_class == EVERGREEN)
- r600_init_atom(rctx-sample_mask.atom,
evergreen_emit_sample_mask, 3, 0);
- else
- r600_init_atom(rctx-sample_mask.atom,
cayman_emit_sample_mask, 4, 0);
+ unsigned id = 4;
+
+ /* !!!
+* To avoid GPU lockup registers must be emited in a specific order
+* (no kidding ...). The order below is important and have been
+* partialy infered from analyzing fglrx command stream.
+*
+* Don't reorder atom without carefully checking the effect (GPU lockup
+* or piglit regression).
+* !!!
+*/
+
+ /* shader const */
+ r600_init_atom(rctx, rctx-vs_constbuf_state.atom, id++,
evergreen_emit_vs_constant_buffers, 0);
+ r600_init_atom(rctx, rctx-ps_constbuf_state.atom, id++,
evergreen_emit_ps_constant_buffers, 0);
+ /* shader program */
+ r600_init_atom(rctx, rctx-cs_shader_state.atom, id++,
evergreen_emit_cs_shader, 0);
+ /* sampler */
+ r600_init_atom(rctx, rctx-vs_samplers.atom_sampler, id++,
evergreen_emit_vs_sampler, 0);
+ r600_init_atom(rctx, rctx-ps_samplers.atom_sampler, id++,
evergreen_emit_ps_sampler, 0);
+ /* resources */
+ r600_init_atom(rctx, rctx-vertex_buffer_state.atom, id++,
evergreen_fs_emit_vertex_buffers, 0);
+ r600_init_atom(rctx, rctx-cs_vertex_buffer_state.atom, id++,
evergreen_cs_emit_vertex_buffers, 0);
+ r600_init_atom(rctx, rctx-vs_samplers.views.atom, id
Mesa (9.0): r600g: fix num of dwords needed for alphatest_state atom
Module: Mesa
Branch: 9.0
Commit: 41d14eaf193c6b1eb87fe1998808a887f1c6c698
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=41d14eaf193c6b1eb87fe1998808a887f1c6c698
Author: Jerome Glisse jgli...@redhat.com
Date: Thu Sep 6 15:09:21 2012 -0400
r600g: fix num of dwords needed for alphatest_state atom
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/r600_state_common.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index 68f53c6..26af6f6 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -108,7 +108,7 @@ void r600_init_common_atoms(struct r600_context *rctx)
{
r600_init_atom(rctx-surface_sync_cmd.atom,r600_emit_surface_sync,
5, EMIT_EARLY);
r600_init_atom(rctx-r6xx_flush_and_inv_cmd,
r600_emit_r6xx_flush_and_inv, 2, EMIT_EARLY);
- r600_init_atom(rctx-alphatest_state.atom,
r600_emit_alphatest_state, 3, 0);
+ r600_init_atom(rctx-alphatest_state.atom,
r600_emit_alphatest_state, 6, 0);
r600_atom_dirty(rctx, rctx-alphatest_state.atom);
}
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Mesa (master): r600g: atomize sampler state v2
Module: Mesa
Branch: master
Commit: 2df399c34bb39122a45bdd5b430b48346542e1cb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2df399c34bb39122a45bdd5b430b48346542e1cb
Author: Jerome Glisse jgli...@redhat.com
Date: Wed Aug 1 15:53:11 2012 -0400
r600g: atomize sampler state v2
Use atom for sampler state. Does not provide new functionality
or fix any bug. Just a step toward full atom base r600g.
v2: Split seamless on r6xx/r7xx into it's own atom. Make sure it's
emited after sampler and with a pipeline flush before otherwise
it does not take effect.
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_hw_context.c | 117
src/gallium/drivers/r600/evergreen_state.c | 136 ---
src/gallium/drivers/r600/r600.h |5 +-
src/gallium/drivers/r600/r600_hw_context.c | 149 +---
src/gallium/drivers/r600/r600_pipe.h| 24 ++-
src/gallium/drivers/r600/r600_state.c | 215 +++
src/gallium/drivers/r600/r600_state_common.c| 66 +++-
7 files changed, 261 insertions(+), 451 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c
b/src/gallium/drivers/r600/evergreen_hw_context.c
index 199033f..6494786 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -575,37 +575,6 @@ static const struct r600_reg cayman_context_reg_list[] = {
{R_028EAC_CB_COLOR11_DIM, 0, 0},
};
-/* SHADER SAMPLER BORDER EG/CM */
-static int evergreen_state_sampler_border_init(struct r600_context *ctx,
uint32_t offset, unsigned id)
-{
- struct r600_reg r600_shader_sampler_border[] = {
- {R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, 0, 0},
- {R_00A404_TD_PS_SAMPLER0_BORDER_RED, 0, 0},
- {R_00A408_TD_PS_SAMPLER0_BORDER_GREEN, 0, 0},
- {R_00A40C_TD_PS_SAMPLER0_BORDER_BLUE, 0, 0},
- {R_00A410_TD_PS_SAMPLER0_BORDER_ALPHA, 0, 0},
- };
- unsigned nreg = Elements(r600_shader_sampler_border);
- unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX)
* 0x100 + 0x4 + id * 0x1C;
- struct r600_range *range;
- struct r600_block *block;
- int r;
-
- for (int i = 0; i nreg; i++) {
- r600_shader_sampler_border[i].offset -=
R_00A400_TD_PS_SAMPLER0_BORDER_INDEX;
- r600_shader_sampler_border[i].offset += fake_offset;
- }
- r = r600_context_add_block(ctx, r600_shader_sampler_border, nreg,
PKT3_SET_CONFIG_REG, 0);
- if (r) {
- return r;
- }
- /* set proper offset */
- range = ctx-range[CTX_RANGE_ID(r600_shader_sampler_border[0].offset)];
- block =
range-blocks[CTX_BLOCK_ID(r600_shader_sampler_border[0].offset)];
- block-pm4[1] = (offset - EVERGREEN_CONFIG_REG_OFFSET) 2;
- return 0;
-}
-
static int evergreen_loop_const_init(struct r600_context *ctx, uint32_t offset)
{
unsigned nreg = 32;
@@ -646,32 +615,6 @@ int evergreen_context_init(struct r600_context *ctx)
if (r)
goto out_err;
-
- /* PS SAMPLER */
- for (int j = 0, offset = 0; j 18; j++, offset += 0xC) {
- r = r600_state_sampler_init(ctx, offset);
- if (r)
- goto out_err;
- }
- /* VS SAMPLER */
- for (int j = 0, offset = 0xD8; j 18; j++, offset += 0xC) {
- r = r600_state_sampler_init(ctx, offset);
- if (r)
- goto out_err;
- }
- /* PS SAMPLER BORDER */
- for (int j = 0; j 18; j++) {
- r = evergreen_state_sampler_border_init(ctx,
R_00A400_TD_PS_SAMPLER0_BORDER_INDEX, j);
- if (r)
- goto out_err;
- }
- /* VS SAMPLER BORDER */
- for (int j = 0; j 18; j++) {
- r = evergreen_state_sampler_border_init(ctx,
R_00A414_TD_VS_SAMPLER0_BORDER_INDEX, j);
- if (r)
- goto out_err;
- }
-
/* PS loop const */
evergreen_loop_const_init(ctx, 0);
/* VS loop const */
@@ -688,66 +631,6 @@ out_err:
return r;
}
-static inline void evergreen_context_pipe_state_set_sampler_border(struct
r600_context *ctx, struct r600_pipe_state *state, unsigned offset, unsigned id)
-{
- unsigned fake_offset = (offset - R_00A400_TD_PS_SAMPLER0_BORDER_INDEX)
* 0x100 + 0x4 + id * 0x1C;
- struct r600_range *range;
- struct r600_block *block;
- int i;
- int dirty;
-
- range = ctx-range[CTX_RANGE_ID(fake_offset)];
- block = range-blocks[CTX_BLOCK_ID(fake_offset)];
- if (state == NULL) {
- block-status = ~(R600_BLOCK_STATUS_ENABLED |
R600_BLOCK_STATUS_DIRTY);
- LIST_DELINIT(block-list);
- LIST_DELINIT(block-enable_list
Mesa (master): r600g: enable streamout only on 2.14 or latter kernel
Module: Mesa
Branch: master
Commit: 1ffac44e83a6fa6f486c6493e1d4eda259938ebb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1ffac44e83a6fa6f486c6493e1d4eda259938ebb
Author: Jerome Glisse jgli...@redhat.com
Date: Tue Jul 24 15:05:43 2012 -0400
r600g: enable streamout only on 2.14 or latter kernel
The kernel streamout support was supposed to get into 3.3 along
the tiling change and thus use the same kernel version bump of
2.13 to report userspace that streamout register were supported.
This is not what happen. So as streamout kernel support did not
bump the kernel driver version, rely on kernel 2.14 version bump
to know if streamout is enabled or not. Which means you need at
least 3.4 kernel.
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/r600_pipe.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index 52725fc..17cc8e9 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -902,7 +902,7 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys
*ws)
switch (rscreen-chip_class) {
case R600:
case EVERGREEN:
- rscreen-has_streamout = rscreen-info.drm_minor = 13;
+ rscreen-has_streamout = rscreen-info.drm_minor = 14;
break;
case R700:
rscreen-has_streamout = rscreen-info.drm_minor = 17;
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Mesa (master): r600g: don't emit forbidden register on old kernel
Module: Mesa
Branch: master
Commit: b7b5a77ec0fa715f09cef32083f818e745772f91
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7b5a77ec0fa715f09cef32083f818e745772f91
Author: Jerome Glisse jgli...@redhat.com
Date: Mon Jul 23 11:26:24 2012 -0400
r600g: don't emit forbidden register on old kernel
Fix https://bugs.freedesktop.org/show_bug.cgi?id=52313
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_state.c |4 +++-
src/gallium/drivers/r600/r600_state.c |4 +++-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 9313cb4..61d893b 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2107,7 +2107,9 @@ static void cayman_init_atom_start_cs(struct r600_context
*rctx)
r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC,
S_028354_SURFACE_SYNC_MASK(0xf));
r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
- r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
+ if (rctx-screen-has_streamout) {
+ r600_store_context_reg(cb,
R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
+ }
eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4),
0x01000FFF);
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 50a7bec..82f5ffb 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -2258,7 +2258,9 @@ void r600_init_atom_start_cs(struct r600_context *rctx)
if (rctx-chip_class == R700 rctx-screen-has_streamout)
r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC,
S_028354_SURFACE_SYNC_MASK(0xf));
r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
- r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
+ if (rctx-screen-has_streamout) {
+ r600_store_context_reg(cb,
R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
+ }
r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0, 0x1000FFF);
r600_store_loop_const(cb, R_03E200_SQ_LOOP_CONST_0 + (32 * 4),
0x1000FFF);
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Mesa (master): r600g: don't emit forbidden reg with old kernel on evergreen
Module: Mesa
Branch: master
Commit: cb149bf9e12aebd38bd0a6d009673e8400659110
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cb149bf9e12aebd38bd0a6d009673e8400659110
Author: Jerome Glisse jgli...@redhat.com
Date: Mon Jul 23 11:42:36 2012 -0400
r600g: don't emit forbidden reg with old kernel on evergreen
Fix https://bugs.freedesktop.org/show_bug.cgi?id=52313
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_state.c |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 61d893b..654aeff 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -2595,7 +2595,9 @@ void evergreen_init_atom_start_cs(struct r600_context
*rctx)
r600_store_context_reg(cb, R_028354_SX_SURFACE_SYNC,
S_028354_SURFACE_SYNC_MASK(0xf));
r600_store_context_reg(cb, R_028800_DB_DEPTH_CONTROL, 0);
- r600_store_context_reg(cb, R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
+ if (rctx-screen-has_streamout) {
+ r600_store_context_reg(cb,
R_028B28_VGT_STRMOUT_DRAW_OPAQUE_OFFSET, 0);
+ }
eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0, 0x01000FFF);
eg_store_loop_const(cb, R_03A200_SQ_LOOP_CONST_0 + (32 * 4),
0x01000FFF);
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Mesa (master): r600g: fix z/stencil texture creation v2
Module: Mesa
Branch: master
Commit: b4f0ab0b22625ac1bb3cf16342039557c086ebae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b4f0ab0b22625ac1bb3cf16342039557c086ebae
Author: Jerome Glisse jgli...@redhat.com
Date: Fri Jun 15 13:01:49 2012 -0400
r600g: fix z/stencil texture creation v2
z or stencil texture should not be created with the z/stencil
flags for surface creation as they are intended to be bound
as texture.
v2: remove broken code
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/r600_texture.c | 32 --
1 files changed, 17 insertions(+), 15 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_texture.c
b/src/gallium/drivers/r600/r600_texture.c
index 5b15990..fe9a923 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -237,7 +237,7 @@ static void r600_texture_set_array_mode(struct pipe_screen
*screen,
static int r600_init_surface(struct radeon_surface *surface,
const struct pipe_resource *ptex,
-unsigned array_mode)
+unsigned array_mode, bool is_transfer)
{
surface-npix_x = ptex-width0;
surface-npix_y = ptex-height0;
@@ -298,7 +298,7 @@ static int r600_init_surface(struct radeon_surface *surface,
if (ptex-bind PIPE_BIND_SCANOUT) {
surface-flags |= RADEON_SURF_SCANOUT;
}
- if (util_format_is_depth_and_stencil(ptex-format)) {
+ if (util_format_is_depth_and_stencil(ptex-format) !is_transfer) {
surface-flags |= RADEON_SURF_ZBUFFER;
surface-flags |= RADEON_SURF_SBUFFER;
}
@@ -316,11 +316,6 @@ static int r600_setup_surface(struct pipe_screen *screen,
unsigned i;
int r;
- if (util_format_is_depth_or_stencil(rtex-real_format)) {
- rtex-surface.flags |= RADEON_SURF_ZBUFFER;
- rtex-surface.flags |= RADEON_SURF_SBUFFER;
- }
-
r = rscreen-ws-surface_init(rscreen-ws, rtex-surface);
if (r) {
return r;
@@ -572,7 +567,8 @@ r600_texture_create_object(struct pipe_screen *screen,
r600_setup_miptree(screen, rtex, array_mode);
if (rscreen-use_surface_alloc) {
rtex-surface = *surface;
- r = r600_setup_surface(screen, rtex, array_mode,
pitch_in_bytes_override);
+ r = r600_setup_surface(screen, rtex, array_mode,
+ pitch_in_bytes_override);
if (r) {
FREE(rtex);
return NULL;
@@ -642,7 +638,8 @@ struct pipe_resource *r600_texture_create(struct
pipe_screen *screen,
}
}
- r = r600_init_surface(surface, templ, array_mode);
+ r = r600_init_surface(surface, templ, array_mode,
+ templ-flags R600_RESOURCE_FLAG_TRANSFER);
if (r) {
return NULL;
}
@@ -723,7 +720,7 @@ struct pipe_resource *r600_texture_from_handle(struct
pipe_screen *screen,
else
array_mode = 0;
- r = r600_init_surface(surface, templ, array_mode);
+ r = r600_init_surface(surface, templ, array_mode, 0);
if (r) {
return NULL;
}
@@ -796,8 +793,9 @@ struct pipe_transfer* r600_texture_get_transfer(struct
pipe_context *ctx,
* the CPU is much happier reading out of cached system memory
* than uncached VRAM.
*/
- if (R600_TEX_IS_TILED(rtex, level))
+ if (R600_TEX_IS_TILED(rtex, level)) {
use_staging_texture = TRUE;
+ }
if ((usage PIPE_TRANSFER_READ) u_box_volume(box) 1024)
use_staging_texture = TRUE;
@@ -805,15 +803,18 @@ struct pipe_transfer* r600_texture_get_transfer(struct
pipe_context *ctx,
/* Use a staging texture for uploads if the underlying BO is busy. */
if (!(usage PIPE_TRANSFER_READ)
(rctx-ws-cs_is_buffer_referenced(rctx-cs, rtex-resource.cs_buf,
RADEON_USAGE_READWRITE) ||
-rctx-ws-buffer_is_busy(rtex-resource.buf,
RADEON_USAGE_READWRITE)))
+rctx-ws-buffer_is_busy(rtex-resource.buf,
RADEON_USAGE_READWRITE))) {
use_staging_texture = TRUE;
+ }
if (!permit_hardware_blit(ctx-screen, texture) ||
- (texture-flags R600_RESOURCE_FLAG_TRANSFER))
+ (texture-flags R600_RESOURCE_FLAG_TRANSFER)) {
use_staging_texture = FALSE;
+ }
- if (use_staging_texture (usage PIPE_TRANSFER_MAP_DIRECTLY))
+ if (use_staging_texture (usage PIPE_TRANSFER_MAP_DIRECTLY)) {
return NULL;
+ }
trans = CALLOC_STRUCT(r600_transfer);
if (trans == NULL)
@@ -898,8 +899,9 @@ void r600_texture_transfer_destroy(struct pipe_context *ctx,
}
if (rtex-is_depth !rtex
Mesa (master): radeon/r600g: fix virtual address space allocation
Module: Mesa
Branch: master
Commit: e372e53ee0ed57072322003e508b3ca4c58076be
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e372e53ee0ed57072322003e508b3ca4c58076be
Author: Jerome Glisse jgli...@redhat.com
Date: Tue Feb 21 12:34:54 2012 -0500
radeon/r600g: fix virtual address space allocation
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/winsys/radeon/drm/radeon_drm_bo.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 8e73e6f..31a47c6 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -211,6 +211,9 @@ static uint64_t radeon_bomgr_find_va(struct radeon_bomgr
*mgr, uint64_t size, ui
waste = waste ? alignment - waste : 0;
}
offset += waste;
+if (offset = (hole-offset + hole-size)) {
+continue;
+}
if (!waste hole-size == size) {
offset = hole-offset;
list_del(hole-list);
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Mesa (master): r600g: fix tiling with cayman and virtual memory
Module: Mesa
Branch: master
Commit: 356eb0aadbb977b0732da077ad31cd66d1b53e23
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=356eb0aadbb977b0732da077ad31cd66d1b53e23
Author: Jerome Glisse jgli...@redhat.com
Date: Tue Feb 14 16:26:12 2012 -0500
r600g: fix tiling with cayman and virtual memory
The virtual address but follow the alignment requirement of the
tiled surface. The bo from handle case is not properly fix. Need
bigger change for a proper fix. Work around that by enforcing 1M
alignment for those bo.
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 38 ++--
1 files changed, 28 insertions(+), 10 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index adee7b2..8e73e6f 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -196,32 +196,50 @@ static boolean radeon_bo_is_busy(struct pb_buffer *_buf,
}
}
-static uint64_t radeon_bomgr_find_va(struct radeon_bomgr *mgr, uint64_t size)
+static uint64_t radeon_bomgr_find_va(struct radeon_bomgr *mgr, uint64_t size,
uint64_t alignment)
{
struct radeon_bo_va_hole *hole, *n;
-uint64_t offset = 0;
+uint64_t offset = 0, waste = 0;
pipe_mutex_lock(mgr-bo_va_mutex);
/* first look for a hole */
LIST_FOR_EACH_ENTRY_SAFE(hole, n, mgr-va_holes, list) {
-if (hole-size == size) {
+offset = hole-offset;
+waste = 0;
+if (alignment) {
+waste = offset % alignment;
+waste = waste ? alignment - waste : 0;
+}
+offset += waste;
+if (!waste hole-size == size) {
offset = hole-offset;
list_del(hole-list);
FREE(hole);
pipe_mutex_unlock(mgr-bo_va_mutex);
return offset;
}
-if (hole-size size) {
-offset = hole-offset;
-hole-size -= size;
-hole-offset += size;
+if ((hole-size - waste) = size) {
+if (waste) {
+n = CALLOC_STRUCT(radeon_bo_va_hole);
+n-size = waste;
+n-offset = hole-offset;
+list_add(n-list, mgr-va_holes);
+}
+hole-size -= (size + waste);
+hole-offset += size + waste;
pipe_mutex_unlock(mgr-bo_va_mutex);
return offset;
}
}
offset = mgr-va_offset;
-mgr-va_offset += size;
+waste = 0;
+if (alignment) {
+waste = offset % alignment;
+waste = waste ? alignment - waste : 0;
+}
+offset += waste;
+mgr-va_offset += size + waste;
pipe_mutex_unlock(mgr-bo_va_mutex);
return offset;
}
@@ -517,7 +535,7 @@ static struct pb_buffer *radeon_bomgr_create_bo(struct
pb_manager *_mgr,
struct drm_radeon_gem_va va;
bo-va_size = align(size, 4096);
-bo-va = radeon_bomgr_find_va(mgr, bo-va_size);
+bo-va = radeon_bomgr_find_va(mgr, bo-va_size, desc-alignment);
va.handle = bo-handle;
va.vm_id = 0;
@@ -818,7 +836,7 @@ done:
struct drm_radeon_gem_va va;
bo-va_size = ((bo-base.size + 4095) ~4095);
-bo-va = radeon_bomgr_find_va(mgr, bo-va_size);
+bo-va = radeon_bomgr_find_va(mgr, bo-va_size, 1 20);
va.handle = bo-handle;
va.operation = RADEON_VA_MAP;
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Mesa (master): r600g: add support for common surface allocator for tiling v13
Module: Mesa Branch: master Commit: c0c979eebc076b95cc8d18a013ce2968fe6311ad URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0c979eebc076b95cc8d18a013ce2968fe6311ad Author: Jerome Glisse jgli...@redhat.com Date: Mon Jan 30 17:22:13 2012 -0500 r600g: add support for common surface allocator for tiling v13 Tiled surface have all kind of alignment constraint that needs to be met. Instead of having all this code duplicated btw ddx and mesa use common code in libdrm_radeon this also ensure that both ddx and mesa compute those alignment in the same way. v2 fix evergreen v3 fix compressed texture and workaround cube texture issue by disabling 2D array mode for cubemap (need to check if r7xx and newer are also affected by the issue) v4 fix texture array v5 fix evergreen and newer, split surface values computation from mipmap tree generation so that we can get them directly from the ddx v6 final fix to evergreen tile split value v7 fix mipmap offset to avoid to use random value, use color view depth view to address different layer as hardware is doing some magic rotation depending on the layer v8 fix COLOR_VIEW on r6xx for linear array mode, use COLOR_VIEW on evergreen, align bytes per pixel to a multiple of a dword v9 fix handling of stencil on evergreen, half fix for compressed texture v10 fix evergreen compressed texture proper support for stencil tile split. Fix stencil issue when array mode was clear by the kernel, always program stencil bo. On evergreen depth buffer bo need to be big enough to hold depth buffer + stencil buffer as even with stencil disabled things get written there. v11 rebase on top of mesa, fix pitch issue with 1d surface on evergreen, old ddx overestimate those. Fix linear case when pitch*height 64. Fix r300g. v12 Fix linear case when pitch*height 64 for old path, adapt to libdrm API change v13 add libdrm check Signed-off-by: Jerome Glisse jgli...@redhat.com --- configure.ac |4 +- src/gallium/drivers/r300/r300_texture.c |2 +- src/gallium/drivers/r600/evergreen_state.c| 352 ++--- src/gallium/drivers/r600/evergreend.h | 22 ++ src/gallium/drivers/r600/r600_blit.c | 27 ++- src/gallium/drivers/r600/r600_hw_context.c|3 + src/gallium/drivers/r600/r600_pipe.h |1 + src/gallium/drivers/r600/r600_resource.h |1 + src/gallium/drivers/r600/r600_state.c | 256 src/gallium/drivers/r600/r600_texture.c | 198 +++- src/gallium/targets/dri-r300/Makefile |2 + src/gallium/targets/dri-r600/Makefile |2 +- src/gallium/targets/egl-static/Makefile |2 + src/gallium/targets/va-r300/Makefile |2 +- src/gallium/targets/va-r600/Makefile |2 +- src/gallium/targets/vdpau-r300/Makefile |2 +- src/gallium/targets/vdpau-r600/Makefile |2 +- src/gallium/targets/xorg-r300/Makefile|2 +- src/gallium/targets/xorg-r600/Makefile|2 +- src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 29 ++- src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 26 ++ src/gallium/winsys/radeon/drm/radeon_drm_winsys.h |1 + src/gallium/winsys/radeon/drm/radeon_winsys.h | 25 ++- 23 files changed, 832 insertions(+), 133 deletions(-) Diff: http://cgit.freedesktop.org/mesa/mesa/diff/?id=c0c979eebc076b95cc8d18a013ce2968fe6311ad ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: add support for virtual address space on cayman v11
Module: Mesa
Branch: master
Commit: bb1f0cf3508630a9a93512c79badf8c493c46743
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bb1f0cf3508630a9a93512c79badf8c493c46743
Author: Jerome Glisse jgli...@redhat.com
Date: Fri Dec 2 10:20:29 2011 -0500
r600g: add support for virtual address space on cayman v11
Virtual address space put the userspace in charge of their GPU
address space. It's up to userspace to bind bo into the virtual
address space. Command stream can them be executed using the
IB_VM chunck.
This patch add support for this configuration. It doesn't remove
the 64K ib size limit thought this limit can be extanded up to
1M for IB_VM chunk.
v2: fix rendering
v3: fix rendering when using index buffer
v4: make vm conditional on kernel support add basic va management
v5: catch the case when we already have va for a bo
v6: agd5f: update on top of ioctl changes
v7: agd5f: further ioctl updates
v8: indentation cleanup + fix non cayman
v9: rebase against lastest mesa + improvement from Marek Michel
v10: fix cut/paste bug
v11: don't rely on updated radeon_drm.h
Signed-off-by: Jerome Glisse jgli...@redhat.com
Signed-off-by: Alex Deucher alexander.deuc...@amd.com
---
src/gallium/drivers/r600/evergreen_hw_context.c |9 +-
src/gallium/drivers/r600/evergreen_state.c| 49 --
src/gallium/drivers/r600/r600_hw_context.c| 47 --
src/gallium/drivers/r600/r600_pipe.h |3 +-
src/gallium/drivers/r600/r600_resource.c | 11 +
src/gallium/drivers/r600/r600_resource.h |2 +
src/gallium/drivers/r600/r600_state_common.c | 14 +-
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 209 +
src/gallium/winsys/radeon/drm/radeon_drm_bo.h |2 +
src/gallium/winsys/radeon/drm/radeon_drm_cs.c | 34 +++-
src/gallium/winsys/radeon/drm/radeon_drm_cs.h |4 +-
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 23 +++
src/gallium/winsys/radeon/drm/radeon_winsys.h | 11 +
13 files changed, 370 insertions(+), 48 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_hw_context.c
b/src/gallium/drivers/r600/evergreen_hw_context.c
index bd1d969..e75eaf2 100644
--- a/src/gallium/drivers/r600/evergreen_hw_context.c
+++ b/src/gallium/drivers/r600/evergreen_hw_context.c
@@ -1135,6 +1135,7 @@ void evergreen_context_draw(struct r600_context *ctx,
const struct r600_draw *dr
struct r600_block *dirty_block = NULL;
struct r600_block *next_block;
uint32_t *pm4;
+ uint64_t va;
if (draw-indices) {
ndwords = 11;
@@ -1174,9 +1175,11 @@ void evergreen_context_draw(struct r600_context *ctx,
const struct r600_draw *dr
pm4[2] = PKT3(PKT3_NUM_INSTANCES, 0, ctx-predicate_drawing);
pm4[3] = draw-vgt_num_instances;
if (draw-indices) {
- pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx-predicate_drawing);
- pm4[5] = draw-indices_bo_offset;
- pm4[6] = 0;
+ va = r600_resource_va(ctx-screen-screen,
(void*)draw-indices);
+ va += draw-indices_bo_offset;
+ pm4[4] = PKT3(PKT3_DRAW_INDEX, 3, ctx-predicate_drawing);
+ pm4[5] = va;
+ pm4[6] = (va 32UL) 0xFF;
pm4[7] = draw-vgt_num_indices;
pm4[8] = draw-vgt_draw_initiator;
pm4[9] = PKT3(PKT3_NOP, 0, ctx-predicate_drawing);
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index f3aab69..df6ad28 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1105,8 +1105,8 @@ static struct pipe_sampler_view
*evergreen_create_sampler_view(struct pipe_conte
rstate-val[1] = (S_030004_TEX_HEIGHT(height - 1) |
S_030004_TEX_DEPTH(depth - 1) |
S_030004_ARRAY_MODE(array_mode));
- rstate-val[2] = tmp-offset[0] 8;
- rstate-val[3] = tmp-offset[1] 8;
+ rstate-val[2] = (tmp-offset[0] + r600_resource_va(ctx-screen,
texture)) 8;
+ rstate-val[3] = (tmp-offset[1] + r600_resource_va(ctx-screen,
texture)) 8;
rstate-val[4] = (word4 |
S_030010_SRF_MODE_ALL(V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE) |
S_030010_ENDIAN_SWAP(endian) |
@@ -1343,7 +1343,7 @@ static void evergreen_cb(struct r600_pipe_context *rctx,
struct r600_pipe_state
unsigned pitch, slice;
unsigned color_info;
unsigned format, swap, ntype, endian;
- unsigned offset;
+ uint64_t offset;
unsigned tile_type;
const struct util_format_description *desc;
int i;
@@ -1443,10 +1443,13 @@ static void evergreen_cb(struct r600_pipe_context
*rctx, struct r600_pipe_state
} else /* workaround for linear buffers */
tile_type = 1;
+ offset += r600_resource_va(rctx-context.screen
Mesa (master): radeon/winsys: fix get info ioctl error checking
Module: Mesa
Branch: master
Commit: b82a2a848c2f614be6186f411bc366ebe2f189bc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b82a2a848c2f614be6186f411bc366ebe2f189bc
Author: Jerome Glisse jgli...@redhat.com
Date: Mon Jan 9 14:59:56 2012 -0500
radeon/winsys: fix get info ioctl error checking
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c |8 +---
1 files changed, 5 insertions(+), 3 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index 442bd2a..f337411 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -138,9 +138,11 @@ static boolean radeon_get_drm_value(int fd, unsigned
request,
info.request = request;
retval = drmCommandWriteRead(fd, DRM_RADEON_INFO, info, sizeof(info));
-if (retval errname) {
-fprintf(stderr, radeon: Failed to get %s, error number %d\n,
-errname, retval);
+if (retval) {
+if (errname) {
+fprintf(stderr, radeon: Failed to get %s, error number %d\n,
+errname, retval);
+}
return FALSE;
}
return TRUE;
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Mesa (master): gallium/radeon: fix indentation
Module: Mesa
Branch: master
Commit: bbc320a94def6178028a4c46012c737839e1cf61
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bbc320a94def6178028a4c46012c737839e1cf61
Author: Jerome Glisse jgli...@redhat.com
Date: Mon Dec 5 18:40:53 2011 -0500
gallium/radeon: fix indentation
Indentation cleanup, to keep consistency.
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 44 ++--
src/gallium/winsys/radeon/drm/radeon_drm_cs.h |2 +-
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c |8 ++--
src/gallium/winsys/radeon/drm/radeon_winsys.h |2 +-
4 files changed, 28 insertions(+), 28 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index d3de6eb..ccf9c4f 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -44,15 +44,15 @@
#define RADEON_BO_FLAGS_MICRO_TILE_SQUARE 0x20
#ifndef DRM_RADEON_GEM_WAIT
-#define DRM_RADEON_GEM_WAIT0x2b
+#define DRM_RADEON_GEM_WAIT 0x2b
-#define RADEON_GEM_NO_WAIT 0x1
-#define RADEON_GEM_USAGE_READ 0x2
-#define RADEON_GEM_USAGE_WRITE 0x4
+#define RADEON_GEM_NO_WAIT 0x1
+#define RADEON_GEM_USAGE_READ 0x2
+#define RADEON_GEM_USAGE_WRITE 0x4
struct drm_radeon_gem_wait {
- uint32_thandle;
- uint32_tflags; /* one of RADEON_GEM_* */
+uint32_thandle;
+uint32_tflags; /* one of RADEON_GEM_* */
};
#endif
@@ -91,9 +91,9 @@ static struct radeon_bo *get_radeon_bo(struct pb_buffer *_buf)
if (_buf-vtbl == radeon_bo_vtbl) {
bo = radeon_bo(_buf);
} else {
- struct pb_buffer *base_buf;
- pb_size offset;
- pb_get_base_buffer(_buf, base_buf, offset);
+struct pb_buffer *base_buf;
+pb_size offset;
+pb_get_base_buffer(_buf, base_buf, offset);
if (base_buf-vtbl == radeon_bo_vtbl)
bo = radeon_bo(base_buf);
@@ -161,7 +161,7 @@ static void radeon_bo_destroy(struct pb_buffer *_buf)
if (bo-name) {
pipe_mutex_lock(bo-mgr-bo_handles_mutex);
util_hash_table_remove(bo-mgr-bo_handles,
- (void*)(uintptr_t)bo-name);
+ (void*)(uintptr_t)bo-name);
pipe_mutex_unlock(bo-mgr-bo_handles_mutex);
}
@@ -305,16 +305,16 @@ static void radeon_bo_unmap_internal(struct pb_buffer
*_buf)
}
static void radeon_bo_get_base_buffer(struct pb_buffer *buf,
- struct pb_buffer **base_buf,
- unsigned *offset)
+ struct pb_buffer **base_buf,
+ unsigned *offset)
{
*base_buf = buf;
*offset = 0;
}
static enum pipe_error radeon_bo_validate(struct pb_buffer *_buf,
- struct pb_validate *vl,
- unsigned flags)
+ struct pb_validate *vl,
+ unsigned flags)
{
/* Always pinned */
return PIPE_OK;
@@ -335,8 +335,8 @@ const struct pb_vtbl radeon_bo_vtbl = {
};
static struct pb_buffer *radeon_bomgr_create_bo(struct pb_manager *_mgr,
- pb_size size,
- const struct pb_desc *desc)
+pb_size size,
+const struct pb_desc *desc)
{
struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
struct radeon_drm_winsys *rws = mgr-rws;
@@ -367,7 +367,7 @@ static struct pb_buffer *radeon_bomgr_create_bo(struct
pb_manager *_mgr,
bo = CALLOC_STRUCT(radeon_bo);
if (!bo)
- return NULL;
+return NULL;
pipe_reference_init(bo-base.reference, 1);
bo-base.alignment = desc-alignment;
@@ -431,7 +431,7 @@ struct pb_manager *radeon_bomgr_create(struct
radeon_drm_winsys *rws)
mgr = CALLOC_STRUCT(radeon_bomgr);
if (!mgr)
- return NULL;
+return NULL;
mgr-base.destroy = radeon_bomgr_destroy;
mgr-base.create_buffer = radeon_bomgr_create_bo;
@@ -470,10 +470,10 @@ static void radeon_bo_get_tiling(struct pb_buffer *_buf,
*microtiled = RADEON_LAYOUT_LINEAR;
*macrotiled = RADEON_LAYOUT_LINEAR;
if (args.tiling_flags RADEON_BO_FLAGS_MICRO_TILE)
- *microtiled = RADEON_LAYOUT_TILED;
+*microtiled = RADEON_LAYOUT_TILED;
if (args.tiling_flags RADEON_BO_FLAGS_MACRO_TILE)
- *macrotiled = RADEON_LAYOUT_TILED;
+*macrotiled = RADEON_LAYOUT_TILED;
}
static void radeon_bo_set_tiling(struct pb_buffer *_buf,
@@ -565,13 +565,13 @@ radeon_winsys_bo_create(struct radeon_winsys *rws,
/* Assign a buffer manager. */
if (bind (PIPE_BIND_VERTEX_BUFFER
Mesa (master): r600g: fix error path and use util_slab_free
Module: Mesa
Branch: master
Commit: e368eefc6866d78e2a004db2fdb13e08e06e0839
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e368eefc6866d78e2a004db2fdb13e08e06e0839
Author: Jerome Glisse jgli...@redhat.com
Date: Mon Dec 5 18:42:38 2011 -0500
r600g: fix error path and use util_slab_free
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/r600_buffer.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_buffer.c
b/src/gallium/drivers/r600/r600_buffer.c
index f1b6956..f438886 100644
--- a/src/gallium/drivers/r600/r600_buffer.c
+++ b/src/gallium/drivers/r600/r600_buffer.c
@@ -177,7 +177,7 @@ struct pipe_resource *r600_buffer_create(struct pipe_screen
*screen,
rbuffer-b.user_ptr = NULL;
if (!r600_init_resource(rscreen, rbuffer, templ-width0, alignment,
templ-bind, templ-usage)) {
- FREE(rbuffer);
+ util_slab_free(rscreen-pool_buffers, rbuffer);
return NULL;
}
return rbuffer-b.b.b;
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Mesa (master): r600g: LIT: fix xy slots order
Module: Mesa Branch: master Commit: 8567e02dca6a944c703185f268a7a624fdd65482 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8567e02dca6a944c703185f268a7a624fdd65482 Author: Vadim Girlin vadimgir...@gmail.com Date: Fri Jun 24 20:29:11 2011 +0400 r600g: LIT: fix xy slots order Signed-off-by: Vadim Girlin vadimgir...@gmail.com --- src/gallium/drivers/r600/r600_shader.c | 22 +++--- 1 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index 86fdfbc..904cc69 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -1391,6 +1391,17 @@ static int tgsi_lit(struct r600_shader_ctx *ctx) } } + /* dst.x, - 1.0 */ + memset(alu, 0, sizeof(struct r600_bc_alu)); + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); + alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/ + alu.src[0].chan = 0; + tgsi_dst(ctx, inst-Dst[0], 0, alu.dst); + alu.dst.write = (inst-Dst[0].Register.WriteMask 0) 1; + r = r600_bc_add_alu(ctx-bc, alu); + if (r) + return r; + /* dst.y = max(src.x, 0.0) */ memset(alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MAX); @@ -1403,17 +1414,6 @@ static int tgsi_lit(struct r600_shader_ctx *ctx) if (r) return r; - /* dst.x, - 1.0 */ - memset(alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); - alu.src[0].sel = V_SQ_ALU_SRC_1; /*1.0*/ - alu.src[0].chan = 0; - tgsi_dst(ctx, inst-Dst[0], 0, alu.dst); - alu.dst.write = (inst-Dst[0].Register.WriteMask 0) 1; - r = r600_bc_add_alu(ctx-bc, alu); - if (r) - return r; - /* dst.w, - 1.0 */ memset(alu, 0, sizeof(struct r600_bc_alu)); alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: optimize spi update
Module: Mesa
Branch: master
Commit: d81126b714cd4de0ab036bb22bf4103f5fcec015
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d81126b714cd4de0ab036bb22bf4103f5fcec015
Author: Vadim Girlin vadimgir...@gmail.com
Date: Fri Jun 24 20:29:12 2011 +0400
r600g: optimize spi update
Signed-off-by: Vadim Girlin vadimgir...@gmail.com
---
src/gallium/drivers/r600/r600_pipe.h |1 +
src/gallium/drivers/r600/r600_state_common.c | 10 +++---
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index 9941bbf..63ddd39 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -202,6 +202,7 @@ struct r600_pipe_context {
struct pipe_query *saved_render_cond;
unsignedsaved_render_cond_mode;
/* shader information */
+ boolean spi_dirty;
unsignedsprite_coord_enable;
boolean flatshade;
boolean export_16bpc;
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index 30c6181..259f426 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -112,7 +112,7 @@ void r600_bind_rs_state(struct pipe_context *ctx, void
*state)
r600_polygon_offset_update(rctx);
}
if (rctx-ps_shader rctx-vs_shader)
- r600_spi_update(rctx);
+ rctx-spi_dirty = true;
}
void r600_delete_rs_state(struct pipe_context *ctx, void *state)
@@ -274,7 +274,7 @@ void r600_bind_ps_shader(struct pipe_context *ctx, void
*state)
r600_context_pipe_state_set(rctx-ctx,
rctx-ps_shader-rstate);
}
if (rctx-ps_shader rctx-vs_shader) {
- r600_spi_update(rctx);
+ rctx-spi_dirty = true;
r600_adjust_gprs(rctx);
}
}
@@ -289,7 +289,7 @@ void r600_bind_vs_shader(struct pipe_context *ctx, void
*state)
r600_context_pipe_state_set(rctx-ctx,
rctx-vs_shader-rstate);
}
if (rctx-ps_shader rctx-vs_shader) {
- r600_spi_update(rctx);
+ rctx-spi_dirty = true;
r600_adjust_gprs(rctx);
}
}
@@ -391,6 +391,7 @@ static void r600_spi_update(struct r600_pipe_context *rctx)
r600_pipe_state_mod_reg(rstate, tmp);
}
+ rctx-spi_dirty = false;
r600_context_pipe_state_set(rctx-ctx, rstate);
}
@@ -573,6 +574,9 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
if (r600_conv_pipe_prim(draw.info.mode, prim))
return;
+ if (rctx-spi_dirty)
+ r600_spi_update(rctx);
+
if (rctx-alpha_ref_dirty)
r600_update_alpha_ref(rctx);
___
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mesa-commit@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: implement fragment and vertex color clamp
Module: Mesa
Branch: master
Commit: eafd331cf3b024001abd3f64861f41cd33a9acb2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eafd331cf3b024001abd3f64861f41cd33a9acb2
Author: Vadim Girlin vadimgir...@gmail.com
Date: Fri Jun 24 20:29:13 2011 +0400
r600g: implement fragment and vertex color clamp
Fixes https://bugs.freedesktop.org/show_bug.cgi?id=38440
Signed-off-by: Vadim Girlin vadimgir...@gmail.com
---
src/gallium/drivers/r600/evergreen_state.c |2 +
src/gallium/drivers/r600/r600_pipe.c |2 +-
src/gallium/drivers/r600/r600_pipe.h |7 +++-
src/gallium/drivers/r600/r600_shader.c | 52 +++---
src/gallium/drivers/r600/r600_shader.h |1 +
src/gallium/drivers/r600/r600_state.c|2 +
src/gallium/drivers/r600/r600_state_common.c | 30 ++-
7 files changed, 87 insertions(+), 9 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index f86e4d4..dfe7896 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -256,6 +256,8 @@ static void *evergreen_create_rs_state(struct pipe_context
*ctx,
}
rstate = rs-rstate;
+ rs-clamp_vertex_color = state-clamp_vertex_color;
+ rs-clamp_fragment_color = state-clamp_fragment_color;
rs-flatshade = state-flatshade;
rs-sprite_coord_enable = state-sprite_coord_enable;
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index 38801d6..12599bf 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -377,6 +377,7 @@ static int r600_get_param(struct pipe_screen* pscreen, enum
pipe_cap param)
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
case PIPE_CAP_SM3:
case PIPE_CAP_SEAMLESS_CUBE_MAP:
+ case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
return 1;
/* Supported except the original R600. */
@@ -392,7 +393,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum
pipe_cap param)
/* Unsupported features. */
case PIPE_CAP_STREAM_OUTPUT:
case PIPE_CAP_PRIMITIVE_RESTART:
- case PIPE_CAP_FRAGMENT_COLOR_CLAMP_CONTROL:
case PIPE_CAP_TGSI_INSTANCEID:
case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index 63ddd39..dc9aad0 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -88,6 +88,8 @@ struct r600_pipe_sampler_view {
struct r600_pipe_rasterizer {
struct r600_pipe_state rstate;
+ boolean clamp_vertex_color;
+ boolean clamp_fragment_color;
boolean flatshade;
unsignedsprite_coord_enable;
float offset_units;
@@ -125,6 +127,7 @@ struct r600_pipe_shader {
struct r600_bo *bo;
struct r600_bo *bo_fetch;
struct r600_vertex_element vertex_elements;
+ struct tgsi_token *tokens;
};
struct r600_pipe_sampler_state {
@@ -202,6 +205,8 @@ struct r600_pipe_context {
struct pipe_query *saved_render_cond;
unsignedsaved_render_cond_mode;
/* shader information */
+ boolean clamp_vertex_color;
+ boolean clamp_fragment_color;
boolean spi_dirty;
unsignedsprite_coord_enable;
boolean flatshade;
@@ -265,7 +270,7 @@ void r600_init_query_functions(struct r600_pipe_context
*rctx);
void r600_init_context_resource_functions(struct r600_pipe_context *r600);
/* r600_shader.c */
-int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader
*shader, const struct tgsi_token *tokens);
+int r600_pipe_shader_create(struct pipe_context *ctx, struct r600_pipe_shader
*shader);
void r600_pipe_shader_destroy(struct pipe_context *ctx, struct
r600_pipe_shader *shader);
int r600_find_vs_semantic_index(struct r600_shader *vs,
struct r600_shader *ps, int id);
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 904cc69..2e5d4a6 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -118,9 +118,9 @@ static int r600_pipe_shader(struct pipe_context *ctx,
struct r600_pipe_shader *s
return 0;
}
-static int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct
r600_shader *shader);
+static int r600_shader_from_tgsi(struct r600_pipe_context * rctx, struct
Mesa (master): r600g: add support for anisotropic filtering
Module: Mesa
Branch: master
Commit: ad904cdf98be576ba652fe1c16ab722d52365782
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad904cdf98be576ba652fe1c16ab722d52365782
Author: Carl-Philip Haensch carli@carli-laptop.(none)
Date: Fri May 6 22:48:08 2011 +0200
r600g: add support for anisotropic filtering
---
src/gallium/drivers/r600/r600_state.c | 20 +---
src/gallium/drivers/r600/r600d.h |9 +
2 files changed, 26 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 3f979cf..aeffb9e 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -364,6 +364,17 @@ static void *r600_create_rs_state(struct pipe_context *ctx,
return rstate;
}
+
+
+static inline unsigned r600_tex_aniso_filter(unsigned filter)
+{
+ if (filter = 1) return 0;
+ if (filter = 2) return 1;
+ if (filter = 4) return 2;
+ if (filter = 8) return 3;
+/* else */return 4;
+}
+
static void *r600_create_sampler_state(struct pipe_context *ctx,
const struct pipe_sampler_state *state)
{
@@ -376,13 +387,15 @@ static void *r600_create_sampler_state(struct
pipe_context *ctx,
rstate-id = R600_PIPE_STATE_SAMPLER;
util_pack_color(state-border_color, PIPE_FORMAT_B8G8R8A8_UNORM, uc);
+ unsigned aniso_flag_offset = state-max_anisotropy 1 ? 4 : 0;
r600_pipe_state_add_reg(rstate, R_03C000_SQ_TEX_SAMPLER_WORD0_0,
S_03C000_CLAMP_X(r600_tex_wrap(state-wrap_s)) |
S_03C000_CLAMP_Y(r600_tex_wrap(state-wrap_t)) |
S_03C000_CLAMP_Z(r600_tex_wrap(state-wrap_r)) |
-
S_03C000_XY_MAG_FILTER(r600_tex_filter(state-mag_img_filter)) |
-
S_03C000_XY_MIN_FILTER(r600_tex_filter(state-min_img_filter)) |
+
S_03C000_XY_MAG_FILTER(r600_tex_filter(state-mag_img_filter) |
aniso_flag_offset) |
+
S_03C000_XY_MIN_FILTER(r600_tex_filter(state-min_img_filter) |
aniso_flag_offset) |
S_03C000_MIP_FILTER(r600_tex_mipfilter(state-min_mip_filter)) |
+
S_03C000_ANISO(r600_tex_aniso_filter(state-max_anisotropy)) |
S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state-compare_func)) |
S_03C000_BORDER_COLOR_TYPE(uc.ui ?
V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0x, NULL);
r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
@@ -492,7 +505,8 @@ static struct pipe_sampler_view
*r600_create_sampler_view(struct pipe_context *c
S_038014_BASE_ARRAY(state-u.tex.first_layer) |
S_038014_LAST_ARRAY(state-u.tex.last_layer),
0x, NULL);
r600_pipe_state_add_reg(rstate, R_038018_RESOURCE0_WORD6,
-
S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE), 0x, NULL);
+
S_038018_TYPE(V_038010_SQ_TEX_VTX_VALID_TEXTURE) |
+ S_038018_ANISO(4 /* max 16 samples */),
0x, NULL);
return resource-base;
}
diff --git a/src/gallium/drivers/r600/r600d.h b/src/gallium/drivers/r600/r600d.h
index 8296b52..c997462 100644
--- a/src/gallium/drivers/r600/r600d.h
+++ b/src/gallium/drivers/r600/r600d.h
@@ -1012,6 +1012,9 @@
#define S_038018_MPEG_CLAMP(x) (((x) 0x3) 0)
#define G_038018_MPEG_CLAMP(x) (((x) 0) 0x3)
#define C_038018_MPEG_CLAMP 0xFFFC
+#define S_038018_ANISO(x)(((x) 0x7) 2)
+#define G_038018_ANISO(x)(((x) 2) 0x7)
+#define C_038018_ANISO 0xFFE3
#define S_038018_PERF_MODULATION(x) (((x) 0x7) 5)
#define G_038018_PERF_MODULATION(x) (((x) 5) 0x7)
#define C_038018_PERF_MODULATION 0xFF1F
@@ -1090,6 +1093,9 @@
#define S_03C000_MIP_FILTER(x) (((x) 0x3) 17)
#define G_03C000_MIP_FILTER(x) (((x) 17) 0x3)
#define C_03C000_MIP_FILTER 0xFFF9
+#define S_03C000_ANISO(x)(((x) 0x7) 19)
+#define G_03C000_ANISO(x)(((x) 19) 0x7)
+#define C_03C000_ANISO 0xFFB7
#define S_03C000_BORDER_COLOR_TYPE(x)(((x) 0x3) 22)
#define G_03C000_BORDER_COLOR_TYPE(x)(((x) 22) 0x3)
#define C_03C000_BORDER_COLOR_TYPE 0xFF3F
@@ -1152,6 +1158,9 @@
#define S_03C008_PERF_Z(x) (((x) 0x3) 18)
#define G_03C008_PERF_Z(x) (((x) 18) 0x3)
#define
Mesa (master): r600g: anisotropic filtering support for evergreen hw
Module: Mesa
Branch: master
Commit: b9e8ea6a2717422ea71887beda093fe1dfbd1200
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9e8ea6a2717422ea71887beda093fe1dfbd1200
Author: Jerome Glisse jgli...@redhat.com
Date: Mon May 9 12:09:51 2011 -0400
r600g: anisotropic filtering support for evergreen hw
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_state.c | 10 +++---
src/gallium/drivers/r600/evergreend.h |6 ++
src/gallium/drivers/r600/r600_pipe.h |9 +
src/gallium/drivers/r600/r600_state.c | 17 +++--
src/gallium/drivers/r600/r600d.h | 12 ++--
5 files changed, 31 insertions(+), 23 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 502f266..654b04e 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -310,6 +310,7 @@ static void *evergreen_create_sampler_state(struct
pipe_context *ctx,
{
struct r600_pipe_state *rstate = CALLOC_STRUCT(r600_pipe_state);
union util_color uc;
+ unsigned aniso_flag_offset = state-max_anisotropy 1 ? 2 : 0;
if (rstate == NULL) {
return NULL;
@@ -321,9 +322,10 @@ static void *evergreen_create_sampler_state(struct
pipe_context *ctx,
S_03C000_CLAMP_X(r600_tex_wrap(state-wrap_s)) |
S_03C000_CLAMP_Y(r600_tex_wrap(state-wrap_t)) |
S_03C000_CLAMP_Z(r600_tex_wrap(state-wrap_r)) |
-
S_03C000_XY_MAG_FILTER(r600_tex_filter(state-mag_img_filter)) |
-
S_03C000_XY_MIN_FILTER(r600_tex_filter(state-min_img_filter)) |
+
S_03C000_XY_MAG_FILTER(r600_tex_filter(state-mag_img_filter) |
aniso_flag_offset) |
+
S_03C000_XY_MIN_FILTER(r600_tex_filter(state-min_img_filter) |
aniso_flag_offset) |
S_03C000_MIP_FILTER(r600_tex_mipfilter(state-min_mip_filter)) |
+
S_03C000_MAX_ANISO(r600_tex_aniso_filter(state-max_anisotropy)) |
S_03C000_DEPTH_COMPARE_FUNCTION(r600_tex_compare(state-compare_func)) |
S_03C000_BORDER_COLOR_TYPE(uc.ui ?
V_03C000_SQ_TEX_BORDER_COLOR_REGISTER : 0), 0x, NULL);
r600_pipe_state_add_reg(rstate, R_03C004_SQ_TEX_SAMPLER_WORD1_0,
@@ -429,7 +431,9 @@ static struct pipe_sampler_view
*evergreen_create_sampler_view(struct pipe_conte
S_030014_LAST_LEVEL(state-u.tex.last_level) |
S_030014_BASE_ARRAY(0) |
S_030014_LAST_ARRAY(0), 0x, NULL);
- r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x0,
0x, NULL);
+ r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6,
+ S_030018_MAX_ANISO(4 /* max 16 samples */),
+ 0x, NULL);
r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
S_03001C_DATA_FORMAT(format) |
S_03001C_TYPE(V_03001C_SQ_TEX_VTX_VALID_TEXTURE), 0x, NULL);
diff --git a/src/gallium/drivers/r600/evergreend.h
b/src/gallium/drivers/r600/evergreend.h
index 670606d..3e87810 100644
--- a/src/gallium/drivers/r600/evergreend.h
+++ b/src/gallium/drivers/r600/evergreend.h
@@ -1027,6 +1027,9 @@
#define G_030014_LAST_ARRAY(x) (((x) 17) 0x1FFF)
#define C_030014_LAST_ARRAY 0xC001
#define R_030018_SQ_TEX_RESOURCE_WORD6_0 0x030018
+#define S_030018_MAX_ANISO(x)(((x) 0x7) 0)
+#define G_030018_MAX_ANISO(x)(((x) 0) 0x7)
+#define C_030018_MAX_ANISO 0xFFF8
#define S_030018_PERF_MODULATION(x) (((x) 0x7) 3)
#define G_030018_PERF_MODULATION(x) (((x) 3) 0x7)
#define C_030018_PERF_MODULATION 0xFFC7
@@ -1141,6 +1144,9 @@
#define S_03C000_MIP_FILTER(x) (((x) 0x3) 15)
#define G_03C000_MIP_FILTER(x) (((x) 15) 0x3)
#define C_03C000_MIP_FILTER 0xFFFE7FFF
+#define S_03C000_MAX_ANISO(x)(((x) 0x7) 17)
+#define G_03C000_MAX_ANISO(x)(((x) 17) 0x7)
+#define C_03C000_MAX_ANISO 0xFFF1
#define S_03C000_BORDER_COLOR_TYPE(x)(((x) 0x3) 20)
#define G_03C000_BORDER_COLOR_TYPE(x)(((x) 20) 0x3)
#define C_03C000_BORDER_COLOR_TYPE 0xFFCF
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index aa5ef4e..0e4cfeb 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium
Mesa (master): r600g: implement the pipe_screen fence functions
Module: Mesa
Branch: master
Commit: 948e1eb8e9c166ad5b74abc630d0760768ce78c9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=948e1eb8e9c166ad5b74abc630d0760768ce78c9
Author: Fredrik Höglund fred...@kde.org
Date: Tue Mar 29 19:43:59 2011 +0200
r600g: implement the pipe_screen fence functions
v2: Allocate the fences from a single shared buffer object.
v3: Allocate the r600_fence structs in blocks of 16.
Spin a few times before calling sched_yield in r600_fence_finish().
---
src/gallium/drivers/r600/r600.h |2 +
src/gallium/drivers/r600/r600_pipe.c | 145 +
src/gallium/drivers/r600/r600_pipe.h | 27 +
src/gallium/winsys/r600/drm/r600_hw_context.c | 23
4 files changed, 197 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index 0b7d6f7..75b8b50 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -288,6 +288,8 @@ void r600_context_queries_suspend(struct r600_context *ctx);
void r600_context_queries_resume(struct r600_context *ctx);
void r600_query_predication(struct r600_context *ctx, struct r600_query
*query, int operation,
int flag_wait);
+void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence,
+ unsigned offset, unsigned value);
int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon);
void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw
*draw);
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index 0e28bda..c5fc2ba 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -37,6 +37,7 @@
#include util/u_memory.h
#include util/u_inlines.h
#include util/u_upload_mgr.h
+#include os/os_time.h
#include pipebuffer/pb_buffer.h
#include r600.h
#include r600d.h
@@ -48,15 +49,82 @@
/*
* pipe_context
*/
+static struct r600_fence *r600_create_fence(struct r600_pipe_context *ctx)
+{
+ struct r600_fence *fence = NULL;
+
+ if (!ctx-fences.bo) {
+ /* Create the shared buffer object */
+ ctx-fences.bo = r600_bo(ctx-radeon, 4096, 0, 0, 0);
+ if (!ctx-fences.bo) {
+ R600_ERR(r600: failed to create bo for fence
objects\n);
+ return NULL;
+ }
+ ctx-fences.data = r600_bo_map(ctx-radeon, ctx-fences.bo,
PB_USAGE_UNSYNCHRONIZED, NULL);
+ }
+
+ if (!LIST_IS_EMPTY(ctx-fences.pool)) {
+ struct r600_fence *entry;
+
+ /* Try to find a freed fence that has been signalled */
+ LIST_FOR_EACH_ENTRY(entry, ctx-fences.pool, head) {
+ if (ctx-fences.data[entry-index] != 0) {
+ LIST_DELINIT(entry-head);
+ fence = entry;
+ break;
+ }
+ }
+ }
+
+ if (!fence) {
+ /* Allocate a new fence */
+ struct r600_fence_block *block;
+ unsigned index;
+
+ if ((ctx-fences.next_index + 1) = 1024) {
+ R600_ERR(r600: too many concurrent fences\n);
+ return NULL;
+ }
+
+ index = ctx-fences.next_index++;
+
+ if (!(index % FENCE_BLOCK_SIZE)) {
+ /* Allocate a new block */
+ block = CALLOC_STRUCT(r600_fence_block);
+ if (block == NULL)
+ return NULL;
+
+ LIST_ADD(block-head, ctx-fences.blocks);
+ } else {
+ block = LIST_ENTRY(struct r600_fence_block,
ctx-fences.blocks.next, head);
+ }
+
+ fence = block-fences[index % FENCE_BLOCK_SIZE];
+ fence-ctx = ctx;
+ fence-index = index;
+ }
+
+ pipe_reference_init(fence-reference, 1);
+
+ ctx-fences.data[fence-index] = 0;
+ r600_context_emit_fence(ctx-ctx, ctx-fences.bo, fence-index, 1);
+ return fence;
+}
+
static void r600_flush(struct pipe_context *ctx,
struct pipe_fence_handle **fence)
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+ struct r600_fence **rfence = (struct r600_fence**)fence;
+
#if 0
static int dc = 0;
char dname[256];
#endif
+ if (rfence)
+ *rfence = r600_create_fence(rctx);
+
if (!rctx-ctx.pm4_cdwords)
return;
@@ -112,6 +180,18 @@ static void r600_destroy_context(struct pipe_context
*context)
u_vbuf_mgr_destroy(rctx-vbuf_mgr);
util_slab_destroy(rctx-pool_transfers);
+ if (rctx-fences.bo) {
+ struct r600_fence_block *entry, *tmp;
+
Mesa (master): r600g: implement texture barrier
Module: Mesa
Branch: master
Commit: d04ab396a54d29948363c3353efa5aaa888076a3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d04ab396a54d29948363c3353efa5aaa888076a3
Author: Fredrik Höglund fred...@kde.org
Date: Tue Mar 29 19:52:03 2011 +0200
r600g: implement texture barrier
---
src/gallium/drivers/r600/evergreen_state.c|1 +
src/gallium/drivers/r600/r600.h |1 +
src/gallium/drivers/r600/r600_pipe.h |2 ++
src/gallium/drivers/r600/r600_state.c |8
src/gallium/winsys/r600/drm/r600_hw_context.c | 17 +
5 files changed, 29 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 7743266..8f93eb8 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -920,6 +920,7 @@ void evergreen_init_state_functions(struct
r600_pipe_context *rctx)
rctx-context.set_viewport_state = evergreen_set_viewport_state;
rctx-context.sampler_view_destroy = r600_sampler_view_destroy;
rctx-context.redefine_user_buffer = u_default_redefine_user_buffer;
+ rctx-context.texture_barrier = r600_texture_barrier;
}
void evergreen_init_config(struct r600_pipe_context *rctx)
diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index 75b8b50..4256a7e 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -290,6 +290,7 @@ void r600_query_predication(struct r600_context *ctx,
struct r600_query *query,
int flag_wait);
void r600_context_emit_fence(struct r600_context *ctx, struct r600_bo *fence,
unsigned offset, unsigned value);
+void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags);
int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon);
void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw
*draw);
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index 88aff0e..5b26d1f 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -298,6 +298,8 @@ void r600_set_constant_buffer(struct pipe_context *ctx,
uint shader, uint index,
struct pipe_resource *buffer);
void r600_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info
*info);
+void r600_texture_barrier(struct pipe_context *ctx);
+
/*
* common helpers
*/
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index d3adf03..e202056 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -934,6 +934,13 @@ static void r600_set_framebuffer_state(struct pipe_context
*ctx,
}
}
+void r600_texture_barrier(struct pipe_context *ctx)
+{
+ struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
+
+ r600_context_flush_all(rctx-ctx, S_0085F0_TC_ACTION_ENA(1));
+}
+
void r600_init_state_functions(struct r600_pipe_context *rctx)
{
rctx-context.create_blend_state = r600_create_blend_state;
@@ -974,6 +981,7 @@ void r600_init_state_functions(struct r600_pipe_context
*rctx)
rctx-context.set_viewport_state = r600_set_viewport_state;
rctx-context.sampler_view_destroy = r600_sampler_view_destroy;
rctx-context.redefine_user_buffer = u_default_redefine_user_buffer;
+ rctx-context.texture_barrier = r600_texture_barrier;
}
void r600_init_config(struct r600_pipe_context *rctx)
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c
b/src/gallium/winsys/r600/drm/r600_hw_context.c
index 48bce81..7f8da12 100644
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -771,6 +771,23 @@ static void rv6xx_context_surface_base_update(struct
r600_context *ctx,
}
}
+/* Flushes all surfaces */
+void r600_context_flush_all(struct r600_context *ctx, unsigned flush_flags)
+{
+ unsigned ndwords = 5;
+
+ if ((ctx-pm4_dirty_cdwords + ndwords + ctx-pm4_cdwords)
ctx-pm4_ndwords) {
+ /* need to flush */
+ r600_context_flush(ctx);
+ }
+
+ ctx-pm4[ctx-pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3,
ctx-predicate_drawing);
+ ctx-pm4[ctx-pm4_cdwords++] = flush_flags; /* CP_COHER_CNTL */
+ ctx-pm4[ctx-pm4_cdwords++] = 0x; /* CP_COHER_SIZE */
+ ctx-pm4[ctx-pm4_cdwords++] = 0; /* CP_COHER_BASE */
+ ctx-pm4[ctx-pm4_cdwords++] = 0x000A; /* POLL_INTERVAL */
+}
+
void r600_context_bo_flush(struct r600_context *ctx, unsigned flush_flags,
unsigned flush_mask, struct r600_bo *rbo)
{
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Mesa (master): r600g: indentation fixes
Module: Mesa
Branch: master
Commit: c33e091d17b90df61f7b3873a2f124c4f26adf06
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c33e091d17b90df61f7b3873a2f124c4f26adf06
Author: Jerome Glisse jgli...@redhat.com
Date: Mon Feb 28 13:33:13 2011 -0500
r600g: indentation fixes
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/r600.h |6 ++--
src/gallium/drivers/r600/r600_asm.c | 48 +-
src/gallium/drivers/r600/r600_buffer.c | 16
src/gallium/drivers/r600/r600_pipe.c |3 +-
src/gallium/drivers/r600/r600_shader.c | 46
src/gallium/drivers/r600/r600_state_common.c | 12 +++---
6 files changed, 65 insertions(+), 66 deletions(-)
diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index 64c52bc..1b76f00 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -118,10 +118,10 @@ unsigned r600_get_clock_crystal_freq(struct radeon
*radeon);
/* r600_bo.c */
struct r600_bo;
struct r600_bo *r600_bo(struct radeon *radeon,
-unsigned size, unsigned alignment,
-unsigned binding, unsigned usage);
+ unsigned size, unsigned alignment,
+ unsigned binding, unsigned usage);
struct r600_bo *r600_bo_handle(struct radeon *radeon,
- unsigned handle, unsigned *array_mode);
+ unsigned handle, unsigned *array_mode);
void *r600_bo_map(struct radeon *radeon, struct r600_bo *bo, unsigned usage,
void *ctx);
void r600_bo_unmap(struct radeon *radeon, struct r600_bo *bo);
void r600_bo_reference(struct radeon *radeon, struct r600_bo **dst,
diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index 5d59356..a319747 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -2070,7 +2070,7 @@ int r600_vertex_elements_build_fetch_shader(struct
r600_pipe_context *rctx, stru
unsigned fetch_resource_start = rctx-family = CHIP_CEDAR ? 0 : 160;
unsigned format, num_format, format_comp;
u32 *bytecode;
-int i, r;
+ int i, r;
/* vertex elements offset need special handling, if offset is bigger
+ * than what we can put in fetch instruction then we need to alterate
@@ -2090,23 +2090,23 @@ int r600_vertex_elements_build_fetch_shader(struct
r600_pipe_context *rctx, stru
return r;
for (i = 0; i ve-count; i++) {
- if (elements[i].instance_divisor 1) {
+ if (elements[i].instance_divisor 1) {
struct r600_bc_alu alu;
memset(alu, 0, sizeof(alu));
-alu.inst = BC_INST(bc,
V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT);
-alu.src[0].sel = 0;
-alu.src[0].chan = 3;
+ alu.inst = BC_INST(bc,
V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_INT_TO_FLT);
+ alu.src[0].sel = 0;
+ alu.src[0].chan = 3;
alu.dst.sel = i + 1;
alu.dst.chan = 3;
alu.dst.write = 1;
alu.last = 1;
-if ((r = r600_bc_add_alu(bc, alu))) {
+ if ((r = r600_bc_add_alu(bc, alu))) {
r600_bc_clear(bc);
-return r;
-}
+ return r;
+ }
memset(alu, 0, sizeof(alu));
alu.inst = BC_INST(bc,
V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL);
@@ -2121,10 +2121,10 @@ int r600_vertex_elements_build_fetch_shader(struct
r600_pipe_context *rctx, stru
alu.dst.write = 1;
alu.last = 1;
-if ((r = r600_bc_add_alu(bc, alu))) {
+ if ((r = r600_bc_add_alu(bc, alu))) {
r600_bc_clear(bc);
-return r;
-}
+ return r;
+ }
memset(alu, 0, sizeof(alu));
alu.inst = BC_INST(bc,
V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_TRUNC);
@@ -2136,26 +2136,26 @@ int r600_vertex_elements_build_fetch_shader(struct
r600_pipe_context *rctx, stru
alu.dst.write = 1;
alu.last = 1;
-if ((r = r600_bc_add_alu(bc, alu))) {
+ if ((r = r600_bc_add_alu(bc, alu))) {
r600_bc_clear(bc);
-return r;
-}
+ return r
Mesa (master): gallium/st: place value check before value is use
Module: Mesa Branch: master Commit: 8e17adfdbd96ba1a11cda329ddfd2b997255ea20 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=8e17adfdbd96ba1a11cda329ddfd2b997255ea20 Author: Jerome Glisse jgli...@redhat.com Date: Fri Feb 25 11:49:23 2011 -0500 gallium/st: place value check before value is use 7.9 7.10 candidate Signed-off-by: Jerome Glisse jgli...@redhat.com --- src/mesa/state_tracker/st_mesa_to_tgsi.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/state_tracker/st_mesa_to_tgsi.c b/src/mesa/state_tracker/st_mesa_to_tgsi.c index 5c68fd7..c07739f 100644 --- a/src/mesa/state_tracker/st_mesa_to_tgsi.c +++ b/src/mesa/state_tracker/st_mesa_to_tgsi.c @@ -224,9 +224,9 @@ src_register( struct st_translate *t, case PROGRAM_TEMPORARY: assert(index = 0); + assert(index Elements(t-temps)); if (ureg_dst_is_undef(t-temps[index])) t-temps[index] = ureg_DECL_temporary( t-ureg ); - assert(index Elements(t-temps)); return ureg_src(t-temps[index]); case PROGRAM_NAMED_PARAM: ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): gallium/tgsi: shuffle ureg_src structure to work around gcc4 .6.0 issue
Module: Mesa
Branch: master
Commit: b0e8aec5ab7f0e81dc0ea6c79ac7db2cca4788ed
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0e8aec5ab7f0e81dc0ea6c79ac7db2cca4788ed
Author: Jerome Glisse jgli...@redhat.com
Date: Fri Feb 25 11:56:29 2011 -0500
gallium/tgsi: shuffle ureg_src structure to work around gcc4.6.0 issue
There is an issue with gcc 4.6.0 that leads to segfault/assert with mesa
due to ureg_src size, reshuffling the structure member to better better
alignment work around the issue.
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=47893
7.9 + 7.10 candidate
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/auxiliary/tgsi/tgsi_ureg.h | 28 ++--
1 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_ureg.h
b/src/gallium/auxiliary/tgsi/tgsi_ureg.h
index b8d193f..9d5553f 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_ureg.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_ureg.h
@@ -43,24 +43,24 @@ struct ureg_program;
*/
struct ureg_src
{
- unsigned File: 4; /* TGSI_FILE_ */
- unsigned SwizzleX: 2; /* TGSI_SWIZZLE_ */
- unsigned SwizzleY: 2; /* TGSI_SWIZZLE_ */
- unsigned SwizzleZ: 2; /* TGSI_SWIZZLE_ */
- unsigned SwizzleW: 2; /* TGSI_SWIZZLE_ */
- unsigned Indirect: 1; /* BOOL */
- unsigned DimIndirect : 1; /* BOOL */
- unsigned Dimension : 1; /* BOOL */
- unsigned Absolute: 1; /* BOOL */
- unsigned Negate : 1; /* BOOL */
- int Index : 16; /* SINT */
+ unsigned File : 4; /* TGSI_FILE_ */
+ unsigned SwizzleX : 2; /* TGSI_SWIZZLE_ */
+ unsigned SwizzleY : 2; /* TGSI_SWIZZLE_ */
+ unsigned SwizzleZ : 2; /* TGSI_SWIZZLE_ */
+ unsigned SwizzleW : 2; /* TGSI_SWIZZLE_ */
+ unsigned Indirect : 1; /* BOOL */
+ unsigned DimIndirect : 1; /* BOOL */
+ unsigned Dimension: 1; /* BOOL */
+ unsigned Absolute : 1; /* BOOL */
+ unsigned Negate : 1; /* BOOL */
unsigned IndirectFile : 4; /* TGSI_FILE_ */
- int IndirectIndex: 16; /* SINT */
unsigned IndirectSwizzle : 2; /* TGSI_SWIZZLE_ */
- int DimensionIndex : 16; /* SINT */
unsigned DimIndFile : 4; /* TGSI_FILE_ */
- int DimIndIndex : 16; /* SINT */
unsigned DimIndSwizzle: 2; /* TGSI_SWIZZLE_ */
+ int Index: 16; /* SINT */
+ int IndirectIndex: 16; /* SINT */
+ int DimensionIndex : 16; /* SINT */
+ int DimIndIndex : 16; /* SINT */
};
/* Very similar to a tgsi_dst_register, removing unsupported fields
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Demos (master): perf/glslstateschange: evaluate shader/ texture state change performance
Module: Demos
Branch: master
Commit: 014a0c44bd7656446df1b1f8f485bc14b7fd68eb
URL:
http://cgit.freedesktop.org/mesa/demos/commit/?id=014a0c44bd7656446df1b1f8f485bc14b7fd68eb
Author: Jerome Glisse jgli...@redhat.com
Date: Tue Jan 11 16:45:14 2011 -0500
perf/glslstateschange: evaluate shader/texture state change performance
Many GL applications change shader bound texture btw draw operation,
this test try to evaluate the speed of such change in the stack.
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/perf/Makefile.am|4 +-
src/perf/glslstateschange.c | 272 +++
src/perf/glslstateschange1.frag | 19 +++
src/perf/glslstateschange1.vert | 14 ++
src/perf/glslstateschange2.frag | 17 +++
src/perf/glslstateschange2.vert | 14 ++
6 files changed, 339 insertions(+), 1 deletions(-)
diff --git a/src/perf/Makefile.am b/src/perf/Makefile.am
index 789aeef..5b00c11 100644
--- a/src/perf/Makefile.am
+++ b/src/perf/Makefile.am
@@ -50,7 +50,8 @@ bin_PROGRAMS = \
swapbuffers \
teximage \
vbo \
- vertexrate
+ vertexrate \
+ glslstateschange
endif
copytex_LDADD = libperf.la
@@ -63,3 +64,4 @@ swapbuffers_LDADD = libperf.la
teximage_LDADD = libperf.la
vbo_LDADD = libperf.la
vertexrate_LDADD = libperf.la
+glslstateschange_LDADD = libperf.la ../util/libutil.la
diff --git a/src/perf/glslstateschange.c b/src/perf/glslstateschange.c
new file mode 100644
index 000..0ea8a7b
--- /dev/null
+++ b/src/perf/glslstateschange.c
@@ -0,0 +1,272 @@
+/**
+ * Test states change when using shaders textures.
+ *
+ * Copyright (C) 2008 Brian Paul All Rights Reserved.
+ * Copyright (C) 2011 Red Hat All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the Software),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * BRIAN PAUL BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN
+ * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+ */
+#include assert.h
+#include math.h
+#include stdio.h
+#include stdlib.h
+#include string.h
+#include GL/glew.h
+#include GL/glut.h
+#include readtex.h
+#include shaderutil.h
+#include glmain.h
+#include common.h
+
+static const char *VertFile1 = glslstateschange1.vert;
+static const char *FragFile1 = glslstateschange1.frag;
+static const char *VertFile2 = glslstateschange2.vert;
+static const char *FragFile2 = glslstateschange2.frag;
+static struct uniform_info Uniforms1[] = {
+ { tex1, 1, GL_SAMPLER_2D, { 0, 0, 0, 0 }, -1 },
+ { tex2, 1, GL_SAMPLER_2D, { 1, 0, 0, 0 }, -1 },
+ { UniV1, 1, GL_FLOAT_VEC4, { 0.8, 0.2, 0.2, 0 }, -1 },
+ { UniV2, 1, GL_FLOAT_VEC4, { 0.6, 0.6, 0.6, 0 }, -1 },
+ END_OF_UNIFORMS
+};
+static struct uniform_info Uniforms2[] = {
+ { tex1, 1, GL_SAMPLER_2D, { 0, 0, 0, 0 }, -1 },
+ { tex2, 1, GL_SAMPLER_2D, { 1, 0, 0, 0 }, -1 },
+ { UniV1, 1, GL_FLOAT_VEC4, { 0.8, 0.2, 0.2, 0 }, -1 },
+ { UniV2, 1, GL_FLOAT_VEC4, { 0.6, 0.6, 0.6, 0 }, -1 },
+ END_OF_UNIFORMS
+};
+static GLuint Program1;
+static GLuint Program2;
+static GLint P1VertCoord_attr = -1;
+static GLint P1TexCoord0_attr = -1, P1TexCoord1_attr = -1;
+static GLint P2VertCoord_attr = -1;
+static GLint P2TexCoord0_attr = -1, P2TexCoord1_attr = -1;
+
+static const char *TexFiles[4] =
+ {
+ ../images/tile.rgb,
+ ../images/tree2.rgba,
+ ../images/tile.rgb,
+ ../images/tree2.rgba
+ };
+GLuint texObj[4];
+
+
+int WinWidth = 500, WinHeight = 500;
+
+static GLfloat Xrot = 0.0, Yrot = .0, Zrot = 0.0;
+static GLfloat EyeDist = 10;
+
+
+
+static const GLfloat Tex0Coords[4][2] = {
+ { 0.0, 0.0 }, { 2.0, 0.0 }, { 2.0, 2.0 }, { 0.0, 2.0 }
+};
+
+static const GLfloat Tex1Coords[4][2] = {
+ { 0.0, 0.0 }, { 1.0, 0.0 }, { 1.0, 1.0 }, { 0.0, 1.0 }
+};
+
+static const GLfloat VertCoords[4][2] = {
+ { -3.0, -3.0 }, { 3.0, -3.0 }, { 3.0, 3.0 }, { -3.0, 3.0 }
+};
+
+static void
+DrawPolygonArray(GLint VertCoord_attr,
+ GLint TexCoord0_attr,
+ GLint TexCoord1_attr)
+{
+ void *vertPtr, *tex0Ptr, *tex1Ptr;
+
+ vertPtr = VertCoords;
+ tex0Ptr = Tex0Coords;
+ tex1Ptr = Tex1Coords
Mesa (master): r600g: move user fence into base radeon structure
Module: Mesa
Branch: master
Commit: 63b9790a55038c262b57c846a5f7067ea33fc60f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=63b9790a55038c262b57c846a5f7067ea33fc60f
Author: Jerome Glisse jgli...@redhat.com
Date: Tue Jan 11 14:29:33 2011 -0500
r600g: move user fence into base radeon structure
This avoid any issue when context is free and we still try to
access fence through radeon structure.
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/r600.h|3 -
src/gallium/winsys/r600/drm/evergreen_hw_context.c |5 +--
src/gallium/winsys/r600/drm/r600_drm.c | 22 +
src/gallium/winsys/r600/drm/r600_hw_context.c | 48 ++--
src/gallium/winsys/r600/drm/r600_priv.h|3 +
src/gallium/winsys/r600/drm/radeon_bo.c|4 +-
6 files changed, 42 insertions(+), 43 deletions(-)
diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index 335f282..a852bef 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -248,10 +248,7 @@ struct r600_context {
u32 *pm4;
struct list_headquery_list;
unsignednum_query_running;
- unsignedfence;
struct list_headfenced_bo;
- unsigned*cfence;
- struct r600_bo *fence_bo;
};
struct r600_draw {
diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index 47d73c2..3fdafc3 100644
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -621,10 +621,7 @@ int evergreen_context_init(struct r600_context *ctx,
struct radeon *radeon)
/* save 16dwords space for fence mecanism */
ctx-pm4_ndwords -= 16;
- r = r600_context_init_fence(ctx);
- if (r) {
- goto out_err;
- }
+ LIST_INITHEAD(ctx-fenced_bo);
/* init dirty list */
LIST_INITHEAD(ctx-dirty);
diff --git a/src/gallium/winsys/r600/drm/r600_drm.c
b/src/gallium/winsys/r600/drm/r600_drm.c
index 36ec583..ee262c3 100644
--- a/src/gallium/winsys/r600/drm/r600_drm.c
+++ b/src/gallium/winsys/r600/drm/r600_drm.c
@@ -30,6 +30,7 @@
#include sys/ioctl.h
#include util/u_inlines.h
#include util/u_debug.h
+#include pipebuffer/pb_bufmgr.h
#include r600.h
#include r600_priv.h
#include r600_drm_public.h
@@ -125,6 +126,18 @@ static int radeon_drm_get_tiling(struct radeon *radeon)
return 0;
}
+static int radeon_init_fence(struct radeon *radeon)
+{
+ radeon-fence = 1;
+ radeon-fence_bo = r600_bo(radeon, 4096, 0, 0, 0);
+ if (radeon-fence_bo == NULL) {
+ return -ENOMEM;
+ }
+ radeon-cfence = r600_bo_map(radeon, radeon-fence_bo,
PB_USAGE_UNSYNCHRONIZED, NULL);
+ *radeon-cfence = 0;
+ return 0;
+}
+
static struct radeon *radeon_new(int fd, unsigned device)
{
struct radeon *radeon;
@@ -198,6 +211,11 @@ static struct radeon *radeon_new(int fd, unsigned device)
if (radeon-bomgr == NULL) {
return NULL;
}
+ r = radeon_init_fence(radeon);
+ if (r) {
+ radeon_decref(radeon);
+ return NULL;
+ }
return radeon;
}
@@ -214,6 +232,10 @@ struct radeon *radeon_decref(struct radeon *radeon)
return NULL;
}
+ if (radeon-fence_bo) {
+ r600_bo_reference(radeon, radeon-fence_bo, NULL);
+ }
+
if (radeon-bomgr)
r600_bomgr_destroy(radeon-bomgr);
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c
b/src/gallium/winsys/r600/drm/r600_hw_context.c
index d01ec3e..f10e2fd 100644
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -40,27 +40,13 @@
#define GROUP_FORCE_NEW_BLOCK 0
-int r600_context_init_fence(struct r600_context *ctx)
-{
- ctx-fence = 1;
- ctx-fence_bo = r600_bo(ctx-radeon, 4096, 0, 0, 0);
- if (ctx-fence_bo == NULL) {
- return -ENOMEM;
- }
- ctx-cfence = r600_bo_map(ctx-radeon, ctx-fence_bo,
PB_USAGE_UNSYNCHRONIZED, NULL);
- *ctx-cfence = 0;
- ctx-radeon-cfence = ctx-cfence;
- LIST_INITHEAD(ctx-fenced_bo);
- return 0;
-}
-
static void INLINE r600_context_update_fenced_list(struct r600_context *ctx)
{
for (int i = 0; i ctx-creloc; i++) {
if (!LIST_IS_EMPTY(ctx-bo[i]-fencedlist))
LIST_DELINIT(ctx-bo[i]-fencedlist);
LIST_ADDTAIL(ctx-bo[i]-fencedlist, ctx-fenced_bo);
- ctx-bo[i]-fence = ctx-fence;
+ ctx-bo[i]-fence = ctx-radeon-fence;
ctx-bo[i]-ctx = ctx;
}
}
@@ -71,7 +57,7 @@ static void INLINE r600_context_fence_wraparound(struct
r600_context *ctx, unsig
Mesa (master): noop: remove dead dri target
Module: Mesa
Branch: master
Commit: 0865af4b42bc82816f751e3a96971375f2adbfb4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0865af4b42bc82816f751e3a96971375f2adbfb4
Author: Jerome Glisse jgli...@redhat.com
Date: Tue Jan 11 14:46:09 2011 -0500
noop: remove dead dri target
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
configure.ac | 13 -
src/gallium/targets/dri-noop/Makefile | 34 -
src/gallium/targets/dri-noop/SConscript | 31
src/gallium/targets/dri-noop/swrast_drm_api.c | 63 -
4 files changed, 0 insertions(+), 141 deletions(-)
diff --git a/configure.ac b/configure.ac
index b6f7d86..d9220c8 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1701,19 +1701,6 @@ if test x$enable_gallium_swrast = xyes || test
x$enable_gallium_swrast = xau
fi
fi
-dnl
-dnl Gallium noop configuration
-dnl
-AC_ARG_ENABLE([gallium-noop],
-[AS_HELP_STRING([--enable-gallium-noop],
-[build gallium radeon @:@default=disabled@:@])],
-[enable_gallium_noop=$enableval],
-[enable_gallium_noop=auto])
-if test x$enable_gallium_noop = xyes; then
-GALLIUM_DRIVERS_DIRS=$GALLIUM_DRIVERS_DIRS noop
-GALLIUM_TARGET_DIRS=$GALLIUM_TARGET_DIRS dri-noop
-fi
-
dnl prepend CORE_DIRS to SRC_DIRS
SRC_DIRS=$CORE_DIRS $SRC_DIRS
diff --git a/src/gallium/targets/dri-noop/Makefile
b/src/gallium/targets/dri-noop/Makefile
deleted file mode 100644
index 21c5f4f..000
--- a/src/gallium/targets/dri-noop/Makefile
+++ /dev/null
@@ -1,34 +0,0 @@
-TOP = ../../../..
-include $(TOP)/configs/current
-
-LIBNAME = noop_dri.so
-
-DRIVER_DEFINES = \
- -D__NOT_HAVE_DRM_H
-
-PIPE_DRIVERS = \
- $(TOP)/src/gallium/state_trackers/dri/sw/libdrisw.a \
- $(TOP)/src/gallium/winsys/sw/dri/libswdri.a \
- $(TOP)/src/gallium/drivers/softpipe/libsoftpipe.a \
- $(TOP)/src/gallium/drivers/trace/libtrace.a \
- $(TOP)/src/gallium/drivers/rbug/librbug.a \
- $(TOP)/src/gallium/drivers/noop/libnoop.a
-
-SWRAST_COMMON_GALLIUM_SOURCES = \
- $(TOP)/src/mesa/drivers/dri/common/utils.c \
- $(TOP)/src/mesa/drivers/dri/common/drisw_util.c \
- $(TOP)/src/mesa/drivers/dri/common/xmlconfig.c
-
-C_SOURCES = \
- swrast_drm_api.c \
- $(SWRAST_COMMON_GALLIUM_SOURCES) \
- $(DRIVER_SOURCES)
-
-ASM_SOURCES =
-
-include ../Makefile.dri
-
-INCLUDES += \
- -I$(TOP)/src/gallium/winsys/sw/dri
-
-symlinks:
diff --git a/src/gallium/targets/dri-noop/SConscript
b/src/gallium/targets/dri-noop/SConscript
deleted file mode 100644
index 9c04ee6..000
--- a/src/gallium/targets/dri-noop/SConscript
+++ /dev/null
@@ -1,31 +0,0 @@
-Import('*')
-
-env = drienv.Clone()
-
-env.Append(CPPPATH = [
-'#/src/gallium/winsys/sw/dri',
-])
-
-env.Prepend(LIBS = [
-st_drisw,
-ws_dri,
-noop,
-mesa,
-glsl,
-gallium,
-COMMON_DRI_SW_OBJECTS
-])
-
-env.Prepend(LIBS = [noop])
-
-swrastg_sources = [
-'swrast_drm_api.c'
-]
-
-module = env.LoadableModule(
-target ='noop_dri.so',
-source = swrastg_sources,
-SHLIBPREFIX = '',
-)
-
-env.Alias('dri-noop', module)
diff --git a/src/gallium/targets/dri-noop/swrast_drm_api.c
b/src/gallium/targets/dri-noop/swrast_drm_api.c
deleted file mode 100644
index a99779f..000
--- a/src/gallium/targets/dri-noop/swrast_drm_api.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/**
- *
- * Copyright 2009, VMware, Inc.
- * All Rights Reserved.
- * Copyright 2010 George Sapountzis gsapount...@gmail.com
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the
- * Software), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sub license, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice (including the
- * next paragraph) shall be included in all copies or substantial portions
- * of the Software.
- *
- * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
- * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
- * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- **/
-
-#include pipe/p_compiler.h
-#include util/u_memory.h
-#include dri_sw_winsys.h
-#include noop/noop_public.h
-
-#include target-helpers/inline_debug_helper.h
-#include target
Mesa (master): noop: make noop useable like trace or rbug
Module: Mesa
Branch: master
Commit: 3349517351059dcd70a81b31bdffe9835bd8f216
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3349517351059dcd70a81b31bdffe9835bd8f216
Author: Jerome Glisse jgli...@redhat.com
Date: Sun Jan 9 21:04:41 2011 -0500
noop: make noop useable like trace or rbug
If you want to enable noop set GALLIUM_NOOP=1 as an env variable.
You need first to enable noop wrapping for your driver see change
to src/gallium/targets/dri-r600/ in this commit as an example.
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
configs/default|2 +-
configure.ac |2 +-
.../auxiliary/target-helpers/inline_noop_helper.h | 51 +
src/gallium/drivers/noop/noop_pipe.c | 77 +---
src/gallium/drivers/noop/noop_public.h |5 +-
src/gallium/targets/dri-r600/Makefile |5 +-
src/gallium/targets/dri-r600/target.c |2 +-
7 files changed, 92 insertions(+), 52 deletions(-)
diff --git a/configs/default b/configs/default
index 3ce90ef..394dc17 100644
--- a/configs/default
+++ b/configs/default
@@ -107,7 +107,7 @@ EGL_DRIVERS_DIRS = glx
# Gallium directories and
GALLIUM_DIRS = auxiliary drivers state_trackers
GALLIUM_AUXILIARIES = $(TOP)/src/gallium/auxiliary/libgallium.a
-GALLIUM_DRIVERS_DIRS = softpipe trace rbug identity galahad i915 i965 svga
r300 nvfx nv50 failover
+GALLIUM_DRIVERS_DIRS = softpipe trace rbug noop identity galahad i915 i965
svga r300 nvfx nv50 failover
GALLIUM_DRIVERS = $(foreach
DIR,$(GALLIUM_DRIVERS_DIRS),$(TOP)/src/gallium/drivers/$(DIR)/lib$(DIR).a)
GALLIUM_WINSYS_DIRS = sw sw/xlib
GALLIUM_TARGET_DIRS = libgl-xlib
diff --git a/configure.ac b/configure.ac
index bcf7cd3..ca2a05c 100644
--- a/configure.ac
+++ b/configure.ac
@@ -588,7 +588,7 @@ GLU_DIRS=sgi
GALLIUM_DIRS=auxiliary drivers state_trackers
GALLIUM_TARGET_DIRS=
GALLIUM_WINSYS_DIRS=sw
-GALLIUM_DRIVERS_DIRS=softpipe failover galahad trace rbug identity
+GALLIUM_DRIVERS_DIRS=softpipe failover galahad trace rbug noop identity
GALLIUM_STATE_TRACKERS_DIRS=
# build glapi if OpenGL is enabled
diff --git a/src/gallium/auxiliary/target-helpers/inline_noop_helper.h
b/src/gallium/auxiliary/target-helpers/inline_noop_helper.h
new file mode 100644
index 000..77c7cfd
--- /dev/null
+++ b/src/gallium/auxiliary/target-helpers/inline_noop_helper.h
@@ -0,0 +1,51 @@
+
+#ifndef INLINE_DEBUG_HELPER_H
+#define INLINE_DEBUG_HELPER_H
+
+#include pipe/p_compiler.h
+#include util/u_debug.h
+
+
+/* Helper function to wrap a screen with
+ * one or more debug driver: rbug, trace.
+ */
+
+#ifdef GALLIUM_TRACE
+#include trace/tr_public.h
+#endif
+
+#ifdef GALLIUM_RBUG
+#include rbug/rbug_public.h
+#endif
+
+#ifdef GALLIUM_GALAHAD
+#include galahad/glhd_public.h
+#endif
+
+#ifdef GALLIUM_NOOP
+#include noop/noop_public.h
+#endif
+
+static INLINE struct pipe_screen *
+debug_screen_wrap(struct pipe_screen *screen)
+{
+#if defined(GALLIUM_RBUG)
+ screen = rbug_screen_create(screen);
+#endif
+
+#if defined(GALLIUM_TRACE)
+ screen = trace_screen_create(screen);
+#endif
+
+#if defined(GALLIUM_GALAHAD)
+ screen = galahad_screen_create(screen);
+#endif
+
+#if defined(GALLIUM_NOOP)
+ screen = noop_screen_create(screen);
+#endif
+
+ return screen;
+}
+
+#endif
diff --git a/src/gallium/drivers/noop/noop_pipe.c
b/src/gallium/drivers/noop/noop_pipe.c
index c9c463f..8c9efc2 100644
--- a/src/gallium/drivers/noop/noop_pipe.c
+++ b/src/gallium/drivers/noop/noop_pipe.c
@@ -30,10 +30,16 @@
#include util/u_inlines.h
#include util/u_format.h
#include noop_public.h
-#include state_tracker/sw_winsys.h
+
+DEBUG_GET_ONCE_BOOL_OPTION(noop, GALLIUM_NOOP, FALSE)
void noop_init_state_functions(struct pipe_context *ctx);
+struct noop_pipe_screen {
+ struct pipe_screen pscreen;
+ struct pipe_screen *oscreen;
+};
+
/*
* query
*/
@@ -108,52 +114,29 @@ static struct pipe_resource *noop_resource_create(struct
pipe_screen *screen,
FREE(nresource);
return NULL;
}
-#if 0
- if (nresource-base.bind (PIPE_BIND_DISPLAY_TARGET |
- PIPE_BIND_SCANOUT |
- PIPE_BIND_SHARED)) {
- struct sw_winsys *winsys = (struct sw_winsys *)screen-winsys;
- unsigned stride;
-
- nresource-dt = winsys-displaytarget_create(winsys,
nresource-base.bind,
-
nresource-base.format,
-
nresource-base.width0,
-
nresource-base.height0,
- 16, stride);
- }
-#endif
return nresource-base;
}
-static struct pipe_resource *noop_resource_from_handle(struct pipe_screen
Mesa (7.10): r600g: fix bo size when creating bo from handle
Module: Mesa Branch: 7.10 Commit: e7b12f2a0e88e754c68faf7c0e034f7bfc0775f1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=e7b12f2a0e88e754c68faf7c0e034f7bfc0775f1 Author: Jerome Glisse jgli...@redhat.com Date: Fri Dec 10 11:17:27 2010 -0500 r600g: fix bo size when creating bo from handle Spoted by Alex Diomin Signed-off-by: Jerome Glisse jgli...@redhat.com --- src/gallium/winsys/r600/drm/r600_bo.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/gallium/winsys/r600/drm/r600_bo.c b/src/gallium/winsys/r600/drm/r600_bo.c index 137402c..6a3737f 100644 --- a/src/gallium/winsys/r600/drm/r600_bo.c +++ b/src/gallium/winsys/r600/drm/r600_bo.c @@ -85,7 +85,7 @@ struct r600_bo *r600_bo_handle(struct radeon *radeon, free(bo); return NULL; } - bo-size = bo-size; + bo-size = rbo-size; bo-domains = (RADEON_GEM_DOMAIN_CPU | RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (7.10): r600g: properly unset vertex buffer
Module: Mesa
Branch: 7.10
Commit: ece71d605bdc2f1196599bd26ad00e06126fe2c3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ece71d605bdc2f1196599bd26ad00e06126fe2c3
Author: Jerome Glisse jgli...@redhat.com
Date: Mon Dec 20 15:30:42 2010 -0500
r600g: properly unset vertex buffer
Fix bug http://bugs.freedesktop.org/show_bug.cgi?id=32455
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_state.c | 10 +-
src/gallium/drivers/r600/r600_state.c| 10 +-
src/gallium/drivers/r600/r600_state_common.c | 14 --
3 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 07496eb..af19beb 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1327,16 +1327,16 @@ void evergreen_vertex_buffer_update(struct
r600_pipe_context *rctx)
vbuffer_index =
rctx-vertex_elements-elements[i].vertex_buffer_index;
vertex_buffer = rctx-vertex_buffer[vbuffer_index];
rbuffer = (struct r600_resource*)vertex_buffer-buffer;
- offset = rctx-vertex_elements-vbuffer_offset[i] +
- vertex_buffer-buffer_offset +
- r600_bo_offset(rbuffer-bo);
+ offset = rctx-vertex_elements-vbuffer_offset[i];
} else {
/* bind vertex buffer once */
vertex_buffer = rctx-vertex_buffer[i];
rbuffer = (struct r600_resource*)vertex_buffer-buffer;
- offset = vertex_buffer-buffer_offset +
- r600_bo_offset(rbuffer-bo);
+ offset = 0;
}
+ if (vertex_buffer == NULL)
+ continue;
+ offset += vertex_buffer-buffer_offset +
r600_bo_offset(rbuffer-bo);
r600_pipe_state_add_reg(rstate, R_03_RESOURCE0_WORD0,
offset, 0x, rbuffer-bo);
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index cd5f079..0d76afd 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -167,16 +167,16 @@ void r600_vertex_buffer_update(struct r600_pipe_context
*rctx)
vbuffer_index =
rctx-vertex_elements-elements[i].vertex_buffer_index;
vertex_buffer = rctx-vertex_buffer[vbuffer_index];
rbuffer = (struct r600_resource*)vertex_buffer-buffer;
- offset = rctx-vertex_elements-vbuffer_offset[i] +
- vertex_buffer-buffer_offset +
- r600_bo_offset(rbuffer-bo);
+ offset = rctx-vertex_elements-vbuffer_offset[i];
} else {
/* bind vertex buffer once */
vertex_buffer = rctx-vertex_buffer[i];
rbuffer = (struct r600_resource*)vertex_buffer-buffer;
- offset = vertex_buffer-buffer_offset +
- r600_bo_offset(rbuffer-bo);
+ offset = 0;
}
+ if (vertex_buffer == NULL)
+ continue;
+ offset += vertex_buffer-buffer_offset +
r600_bo_offset(rbuffer-bo);
r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
offset, 0x, rbuffer-bo);
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index 99b372c..f488cf7 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -179,8 +179,16 @@ void r600_set_vertex_buffers(struct pipe_context *ctx,
unsigned count,
struct pipe_vertex_buffer *vbo;
unsigned max_index = (unsigned)-1;
- for (int i = 0; i rctx-nvertex_buffer; i++) {
- pipe_resource_reference(rctx-vertex_buffer[i].buffer, NULL);
+ if (rctx-family = CHIP_CEDAR) {
+ for (int i = 0; i rctx-nvertex_buffer; i++) {
+ pipe_resource_reference(rctx-vertex_buffer[i].buffer,
NULL);
+ evergreen_fs_resource_set(rctx-ctx, NULL, i);
+ }
+ } else {
+ for (int i = 0; i rctx-nvertex_buffer; i++) {
+ pipe_resource_reference(rctx-vertex_buffer[i].buffer,
NULL);
+ r600_context_pipe_state_set_fs_resource(rctx-ctx,
NULL, i);
+ }
}
memcpy(rctx-vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer)
* count);
@@ -188,6 +196,8 @@ void r600_set_vertex_buffers(struct pipe_context *ctx
Mesa (7.10): r600g: fix segfault when translating vertex buffer
Module: Mesa
Branch: 7.10
Commit: 44346148446bc0cb89e3f003f249a98721bec6f4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=44346148446bc0cb89e3f003f249a98721bec6f4
Author: Jerome Glisse jgli...@redhat.com
Date: Tue Dec 14 13:50:46 2010 -0500
r600g: fix segfault when translating vertex buffer
Note the support for non float vertex draw likely regressed need to
find what we want to do there.
candidates for 7.10 branches
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_state.c |5 -
src/gallium/drivers/r600/r600_state.c|9 -
src/gallium/drivers/r600/r600_state_common.c |5 +
src/gallium/drivers/r600/r600_translate.c| 12 +---
4 files changed, 10 insertions(+), 21 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index a9d4a86..07496eb 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1295,11 +1295,6 @@ void evergreen_vertex_buffer_update(struct
r600_pipe_context *rctx)
if (rctx-vertex_elements == NULL || !rctx-nvertex_buffer)
return;
- /* delete previous translated vertex elements */
- if (rctx-tran.new_velems) {
- r600_end_vertex_translate(rctx);
- }
-
if (rctx-vertex_elements-incompatible_layout) {
/* translate rebind new vertex elements so
* return once translated
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 67ea217..cd5f079 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -135,11 +135,6 @@ void r600_vertex_buffer_update(struct r600_pipe_context
*rctx)
if (rctx-vertex_elements == NULL || !rctx-nvertex_buffer)
return;
- /* delete previous translated vertex elements */
- if (rctx-tran.new_velems) {
- r600_end_vertex_translate(rctx);
- }
-
if (rctx-vertex_elements-incompatible_layout) {
/* translate rebind new vertex elements so
* return once translated
@@ -280,7 +275,6 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_drawl draw;
- boolean translate = FALSE;
memset(draw, 0, sizeof(struct r600_drawl));
draw.ctx = ctx;
@@ -312,9 +306,6 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
}
r600_draw_common(draw);
- if (translate)
- r600_end_vertex_translate(rctx);
-
pipe_resource_reference(draw.index_buffer, NULL);
}
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index 1333808..99b372c 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -119,6 +119,11 @@ void r600_bind_vertex_elements(struct pipe_context *ctx,
void *state)
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_vertex_element *v = (struct r600_vertex_element*)state;
+ /* delete previous translated vertex elements */
+ if (rctx-tran.new_velems) {
+ r600_end_vertex_translate(rctx);
+ }
+
rctx-vertex_elements = v;
if (v) {
rctx-states[v-rstate.id] = v-rstate;
diff --git a/src/gallium/drivers/r600/r600_translate.c
b/src/gallium/drivers/r600/r600_translate.c
index 1c227d3..ba12eee 100644
--- a/src/gallium/drivers/r600/r600_translate.c
+++ b/src/gallium/drivers/r600/r600_translate.c
@@ -42,6 +42,7 @@ void r600_begin_vertex_translate(struct r600_pipe_context
*rctx)
struct pipe_resource *out_buffer;
unsigned i, num_verts;
struct pipe_vertex_element new_velems[PIPE_MAX_ATTRIBS];
+ void *tmp;
/* Initialize the translate key, i.e. the recipe how vertices should be
* translated. */
@@ -159,8 +160,9 @@ void r600_begin_vertex_translate(struct r600_pipe_context
*rctx)
}
}
- rctx-tran.new_velems = pipe-create_vertex_elements_state(pipe,
ve-count, new_velems);
- pipe-bind_vertex_elements_state(pipe, rctx-tran.new_velems);
+ tmp = pipe-create_vertex_elements_state(pipe, ve-count, new_velems);
+ pipe-bind_vertex_elements_state(pipe, tmp);
+ rctx-tran.new_velems = tmp;
pipe_resource_reference(out_buffer, NULL);
}
@@ -173,15 +175,11 @@ void r600_end_vertex_translate(struct r600_pipe_context
*rctx)
return;
}
/* Restore vertex elements. */
- if (rctx-vertex_elements == rctx-tran.new_velems) {
- pipe-bind_vertex_elements_state(pipe, NULL);
- }
pipe-delete_vertex_elements_state(pipe, rctx-tran.new_velems
Mesa (7.10): r600g: need to reference upload buffer as the might still live accross flush
Module: Mesa
Branch: 7.10
Commit: 0fc205152c0706cff0eb9835e6a249376581366d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0fc205152c0706cff0eb9835e6a249376581366d
Author: Jerome Glisse jgli...@redhat.com
Date: Wed Dec 15 12:07:09 2010 -0500
r600g: need to reference upload buffer as the might still live accross flush
Can't get away from referencing upload buffer as after flush a vertex buffer
using the upload buffer might still be active. Likely need to simplify the
pipe_refence a bit so we don't waste so much cpu time in it.
candidates for 7.10 branch
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/r600_buffer.c |2 +-
src/gallium/drivers/r600/r600_upload.c |4 +++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_buffer.c
b/src/gallium/drivers/r600/r600_buffer.c
index 7d29f76..a17c54d 100644
--- a/src/gallium/drivers/r600/r600_buffer.c
+++ b/src/gallium/drivers/r600/r600_buffer.c
@@ -103,7 +103,7 @@ static void r600_buffer_destroy(struct pipe_screen *screen,
{
struct r600_resource_buffer *rbuffer = r600_buffer(buf);
- if (!rbuffer-uploaded rbuffer-r.bo) {
+ if (rbuffer-r.bo) {
r600_bo_reference((struct radeon*)screen-winsys,
rbuffer-r.bo, NULL);
}
rbuffer-r.bo = NULL;
diff --git a/src/gallium/drivers/r600/r600_upload.c
b/src/gallium/drivers/r600/r600_upload.c
index ac72854..44102ff 100644
--- a/src/gallium/drivers/r600/r600_upload.c
+++ b/src/gallium/drivers/r600/r600_upload.c
@@ -69,6 +69,7 @@ void r600_upload_flush(struct r600_upload *upload)
upload-default_size = MAX2(upload-total_alloc_size,
upload-default_size);
upload-total_alloc_size = 0;
upload-size = 0;
+ upload-offset = 0;
upload-ptr = NULL;
upload-buffer = NULL;
}
@@ -105,7 +106,8 @@ int r600_upload_buffer(struct r600_upload *upload, unsigned
offset,
memcpy(upload-ptr + upload-offset, (uint8_t *) in_ptr + offset, size);
*out_offset = upload-offset;
*out_size = upload-size;
- *out_buffer = upload-buffer;
+ *out_buffer = NULL;
+ r600_bo_reference(upload-rctx-radeon, out_buffer, upload-buffer);
upload-offset += alloc_size;
return 0;
___
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Mesa (7.10): r600g: avoid segfault
Module: Mesa Branch: 7.10 Commit: 34c58f6d469242616579e95df9a5909a9e177988 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=34c58f6d469242616579e95df9a5909a9e177988 Author: Jerome Glisse jgli...@redhat.com Date: Tue Dec 21 10:49:53 2010 -0500 r600g: avoid segfault Candidates 7.10 Signed-off-by: Jerome Glisse jgli...@redhat.com --- src/gallium/drivers/r600/evergreen_state.c |2 +- src/gallium/drivers/r600/r600_state.c |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index af19beb..8a69a10 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -1334,7 +1334,7 @@ void evergreen_vertex_buffer_update(struct r600_pipe_context *rctx) rbuffer = (struct r600_resource*)vertex_buffer-buffer; offset = 0; } - if (vertex_buffer == NULL) + if (vertex_buffer == NULL || rbuffer == NULL) continue; offset += vertex_buffer-buffer_offset + r600_bo_offset(rbuffer-bo); diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 0d76afd..9b099df 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -174,7 +174,7 @@ void r600_vertex_buffer_update(struct r600_pipe_context *rctx) rbuffer = (struct r600_resource*)vertex_buffer-buffer; offset = 0; } - if (vertex_buffer == NULL) + if (vertex_buffer == NULL || rbuffer == NULL) continue; offset += vertex_buffer-buffer_offset + r600_bo_offset(rbuffer-bo); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (7.10): r600g: fix evergreen segfaults.
Module: Mesa
Branch: 7.10
Commit: 949c24862afcaf50b2c204f88582099c60fdbc51
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=949c24862afcaf50b2c204f88582099c60fdbc51
Author: Dave Airlie airl...@redhat.com
Date: Wed Dec 22 14:54:17 2010 +1000
r600g: fix evergreen segfaults.
evergreen was crashing running even gears here.
This is a 7.10 candidate if its broken the same.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/r600/r600_state_common.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index f488cf7..3603376 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -182,7 +182,7 @@ void r600_set_vertex_buffers(struct pipe_context *ctx,
unsigned count,
if (rctx-family = CHIP_CEDAR) {
for (int i = 0; i rctx-nvertex_buffer; i++) {
pipe_resource_reference(rctx-vertex_buffer[i].buffer,
NULL);
- evergreen_fs_resource_set(rctx-ctx, NULL, i);
+
evergreen_context_pipe_state_set_fs_resource(rctx-ctx, NULL, i);
}
} else {
for (int i = 0; i rctx-nvertex_buffer; i++) {
___
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Mesa (7.10): r600g: hack around property unknown issues.
Module: Mesa Branch: 7.10 Commit: 9ba827100a2d49ca839c7c8a1d0dec258b5c7ecd URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9ba827100a2d49ca839c7c8a1d0dec258b5c7ecd Author: Dave Airlie airl...@redhat.com Date: Fri Dec 24 17:33:41 2010 +1000 r600g: hack around property unknown issues. should fix https://bugs.freedesktop.org/show_bug.cgi?id=32619 Need to add proper support for properties later. Signed-off-by: Dave Airlie airl...@redhat.com --- src/gallium/drivers/r600/r600_shader.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index 9c7b7f0..bb5038c 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -589,6 +589,8 @@ int r600_shader_from_tgsi(const struct tgsi_token *tokens, struct r600_shader *s if (r) goto out_err; break; + case TGSI_TOKEN_TYPE_PROPERTY: + break; default: R600_ERR(unsupported token type %d\n, ctx.parse.FullToken.Token.Type); r = -EINVAL; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (7.10): r600g: remove useless switch statements
Module: Mesa
Branch: 7.10
Commit: 002ce07abe5581d98b72ea30dc5982fe6de0db3b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=002ce07abe5581d98b72ea30dc5982fe6de0db3b
Author: Alex Deucher alexdeuc...@gmail.com
Date: Wed Dec 22 01:30:41 2010 -0500
r600g: remove useless switch statements
Signed-off-by: Alex Deucher alexdeuc...@gmail.com
---
src/gallium/winsys/r600/drm/r600.c | 52 ---
src/gallium/winsys/r600/drm/r600_drm.c | 53
2 files changed, 0 insertions(+), 105 deletions(-)
diff --git a/src/gallium/winsys/r600/drm/r600.c
b/src/gallium/winsys/r600/drm/r600.c
index b88733f..82a55ac 100644
--- a/src/gallium/winsys/r600/drm/r600.c
+++ b/src/gallium/winsys/r600/drm/r600.c
@@ -79,58 +79,6 @@ struct radeon *r600_new(int fd, unsigned device)
r600_delete(r600);
return NULL;
}
- switch (r600-family) {
- case CHIP_R600:
- case CHIP_RV610:
- case CHIP_RV630:
- case CHIP_RV670:
- case CHIP_RV620:
- case CHIP_RV635:
- case CHIP_RS780:
- case CHIP_RS880:
- case CHIP_RV770:
- case CHIP_RV730:
- case CHIP_RV710:
- case CHIP_RV740:
- case CHIP_CEDAR:
- case CHIP_REDWOOD:
- case CHIP_JUNIPER:
- case CHIP_CYPRESS:
- case CHIP_HEMLOCK:
- case CHIP_PALM:
- break;
- case CHIP_R100:
- case CHIP_RV100:
- case CHIP_RS100:
- case CHIP_RV200:
- case CHIP_RS200:
- case CHIP_R200:
- case CHIP_RV250:
- case CHIP_RS300:
- case CHIP_RV280:
- case CHIP_R300:
- case CHIP_R350:
- case CHIP_RV350:
- case CHIP_RV380:
- case CHIP_R420:
- case CHIP_R423:
- case CHIP_RV410:
- case CHIP_RS400:
- case CHIP_RS480:
- case CHIP_RS600:
- case CHIP_RS690:
- case CHIP_RS740:
- case CHIP_RV515:
- case CHIP_R520:
- case CHIP_RV530:
- case CHIP_RV560:
- case CHIP_RV570:
- case CHIP_R580:
- default:
- R600_ERR(unknown or unsupported chipset 0x%04X\n,
r600-device);
- break;
- }
-
/* setup class */
switch (r600-family) {
case CHIP_R600:
diff --git a/src/gallium/winsys/r600/drm/r600_drm.c
b/src/gallium/winsys/r600/drm/r600_drm.c
index 3cbbf91..94ed3ed 100644
--- a/src/gallium/winsys/r600/drm/r600_drm.c
+++ b/src/gallium/winsys/r600/drm/r600_drm.c
@@ -134,59 +134,6 @@ static struct radeon *radeon_new(int fd, unsigned device)
fprintf(stderr, Unknown chipset 0x%04X\n, radeon-device);
return radeon_decref(radeon);
}
- switch (radeon-family) {
- case CHIP_R600:
- case CHIP_RV610:
- case CHIP_RV630:
- case CHIP_RV670:
- case CHIP_RV620:
- case CHIP_RV635:
- case CHIP_RS780:
- case CHIP_RS880:
- case CHIP_RV770:
- case CHIP_RV730:
- case CHIP_RV710:
- case CHIP_RV740:
- case CHIP_CEDAR:
- case CHIP_REDWOOD:
- case CHIP_JUNIPER:
- case CHIP_CYPRESS:
- case CHIP_HEMLOCK:
- case CHIP_PALM:
- break;
- case CHIP_R100:
- case CHIP_RV100:
- case CHIP_RS100:
- case CHIP_RV200:
- case CHIP_RS200:
- case CHIP_R200:
- case CHIP_RV250:
- case CHIP_RS300:
- case CHIP_RV280:
- case CHIP_R300:
- case CHIP_R350:
- case CHIP_RV350:
- case CHIP_RV380:
- case CHIP_R420:
- case CHIP_R423:
- case CHIP_RV410:
- case CHIP_RS400:
- case CHIP_RS480:
- case CHIP_RS600:
- case CHIP_RS690:
- case CHIP_RS740:
- case CHIP_RV515:
- case CHIP_R520:
- case CHIP_RV530:
- case CHIP_RV560:
- case CHIP_RV570:
- case CHIP_R580:
- default:
- fprintf(stderr, %s unknown or unsupported chipset 0x%04X\n,
- __func__, radeon-device);
- break;
- }
-
/* setup class */
switch (radeon-family) {
case CHIP_R600:
___
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Mesa (master): r600g: avoid segfault
Module: Mesa Branch: master Commit: fa62cf7450595b3d99259b5a212df301ca711d4b URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa62cf7450595b3d99259b5a212df301ca711d4b Author: Jerome Glisse jgli...@redhat.com Date: Tue Dec 21 10:49:53 2010 -0500 r600g: avoid segfault Candidates 7.10 Signed-off-by: Jerome Glisse jgli...@redhat.com --- src/gallium/drivers/r600/evergreen_state.c |2 +- src/gallium/drivers/r600/r600_state.c |2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index af19beb..8a69a10 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -1334,7 +1334,7 @@ void evergreen_vertex_buffer_update(struct r600_pipe_context *rctx) rbuffer = (struct r600_resource*)vertex_buffer-buffer; offset = 0; } - if (vertex_buffer == NULL) + if (vertex_buffer == NULL || rbuffer == NULL) continue; offset += vertex_buffer-buffer_offset + r600_bo_offset(rbuffer-bo); diff --git a/src/gallium/drivers/r600/r600_state.c b/src/gallium/drivers/r600/r600_state.c index 0d76afd..9b099df 100644 --- a/src/gallium/drivers/r600/r600_state.c +++ b/src/gallium/drivers/r600/r600_state.c @@ -174,7 +174,7 @@ void r600_vertex_buffer_update(struct r600_pipe_context *rctx) rbuffer = (struct r600_resource*)vertex_buffer-buffer; offset = 0; } - if (vertex_buffer == NULL) + if (vertex_buffer == NULL || rbuffer == NULL) continue; offset += vertex_buffer-buffer_offset + r600_bo_offset(rbuffer-bo); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: properly unset vertex buffer
Module: Mesa
Branch: master
Commit: abe9ffc25c8d65b48ae02cdc8445b212b9f61632
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=abe9ffc25c8d65b48ae02cdc8445b212b9f61632
Author: Jerome Glisse jgli...@redhat.com
Date: Mon Dec 20 15:30:42 2010 -0500
r600g: properly unset vertex buffer
Fix bug http://bugs.freedesktop.org/show_bug.cgi?id=32455
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_state.c | 10 +-
src/gallium/drivers/r600/r600_state.c| 10 +-
src/gallium/drivers/r600/r600_state_common.c | 14 --
3 files changed, 22 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 07496eb..af19beb 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1327,16 +1327,16 @@ void evergreen_vertex_buffer_update(struct
r600_pipe_context *rctx)
vbuffer_index =
rctx-vertex_elements-elements[i].vertex_buffer_index;
vertex_buffer = rctx-vertex_buffer[vbuffer_index];
rbuffer = (struct r600_resource*)vertex_buffer-buffer;
- offset = rctx-vertex_elements-vbuffer_offset[i] +
- vertex_buffer-buffer_offset +
- r600_bo_offset(rbuffer-bo);
+ offset = rctx-vertex_elements-vbuffer_offset[i];
} else {
/* bind vertex buffer once */
vertex_buffer = rctx-vertex_buffer[i];
rbuffer = (struct r600_resource*)vertex_buffer-buffer;
- offset = vertex_buffer-buffer_offset +
- r600_bo_offset(rbuffer-bo);
+ offset = 0;
}
+ if (vertex_buffer == NULL)
+ continue;
+ offset += vertex_buffer-buffer_offset +
r600_bo_offset(rbuffer-bo);
r600_pipe_state_add_reg(rstate, R_03_RESOURCE0_WORD0,
offset, 0x, rbuffer-bo);
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index cd5f079..0d76afd 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -167,16 +167,16 @@ void r600_vertex_buffer_update(struct r600_pipe_context
*rctx)
vbuffer_index =
rctx-vertex_elements-elements[i].vertex_buffer_index;
vertex_buffer = rctx-vertex_buffer[vbuffer_index];
rbuffer = (struct r600_resource*)vertex_buffer-buffer;
- offset = rctx-vertex_elements-vbuffer_offset[i] +
- vertex_buffer-buffer_offset +
- r600_bo_offset(rbuffer-bo);
+ offset = rctx-vertex_elements-vbuffer_offset[i];
} else {
/* bind vertex buffer once */
vertex_buffer = rctx-vertex_buffer[i];
rbuffer = (struct r600_resource*)vertex_buffer-buffer;
- offset = vertex_buffer-buffer_offset +
- r600_bo_offset(rbuffer-bo);
+ offset = 0;
}
+ if (vertex_buffer == NULL)
+ continue;
+ offset += vertex_buffer-buffer_offset +
r600_bo_offset(rbuffer-bo);
r600_pipe_state_add_reg(rstate, R_038000_RESOURCE0_WORD0,
offset, 0x, rbuffer-bo);
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index 99b372c..f488cf7 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -179,8 +179,16 @@ void r600_set_vertex_buffers(struct pipe_context *ctx,
unsigned count,
struct pipe_vertex_buffer *vbo;
unsigned max_index = (unsigned)-1;
- for (int i = 0; i rctx-nvertex_buffer; i++) {
- pipe_resource_reference(rctx-vertex_buffer[i].buffer, NULL);
+ if (rctx-family = CHIP_CEDAR) {
+ for (int i = 0; i rctx-nvertex_buffer; i++) {
+ pipe_resource_reference(rctx-vertex_buffer[i].buffer,
NULL);
+ evergreen_fs_resource_set(rctx-ctx, NULL, i);
+ }
+ } else {
+ for (int i = 0; i rctx-nvertex_buffer; i++) {
+ pipe_resource_reference(rctx-vertex_buffer[i].buffer,
NULL);
+ r600_context_pipe_state_set_fs_resource(rctx-ctx,
NULL, i);
+ }
}
memcpy(rctx-vertex_buffer, buffers, sizeof(struct pipe_vertex_buffer)
* count);
@@ -188,6 +196,8 @@ void r600_set_vertex_buffers(struct pipe_context *ctx
Mesa (master): r600g: need to reference upload buffer as the might still live accross flush
Module: Mesa
Branch: master
Commit: 3861a1001c5ad0dd0de3b0befabf3ed69da9dc5e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3861a1001c5ad0dd0de3b0befabf3ed69da9dc5e
Author: Jerome Glisse jgli...@redhat.com
Date: Wed Dec 15 12:07:09 2010 -0500
r600g: need to reference upload buffer as the might still live accross flush
Can't get away from referencing upload buffer as after flush a vertex buffer
using the upload buffer might still be active. Likely need to simplify the
pipe_refence a bit so we don't waste so much cpu time in it.
candidates for 7.10 branch
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/r600_buffer.c |2 +-
src/gallium/drivers/r600/r600_upload.c |4 +++-
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_buffer.c
b/src/gallium/drivers/r600/r600_buffer.c
index 7d29f76..a17c54d 100644
--- a/src/gallium/drivers/r600/r600_buffer.c
+++ b/src/gallium/drivers/r600/r600_buffer.c
@@ -103,7 +103,7 @@ static void r600_buffer_destroy(struct pipe_screen *screen,
{
struct r600_resource_buffer *rbuffer = r600_buffer(buf);
- if (!rbuffer-uploaded rbuffer-r.bo) {
+ if (rbuffer-r.bo) {
r600_bo_reference((struct radeon*)screen-winsys,
rbuffer-r.bo, NULL);
}
rbuffer-r.bo = NULL;
diff --git a/src/gallium/drivers/r600/r600_upload.c
b/src/gallium/drivers/r600/r600_upload.c
index ac72854..44102ff 100644
--- a/src/gallium/drivers/r600/r600_upload.c
+++ b/src/gallium/drivers/r600/r600_upload.c
@@ -69,6 +69,7 @@ void r600_upload_flush(struct r600_upload *upload)
upload-default_size = MAX2(upload-total_alloc_size,
upload-default_size);
upload-total_alloc_size = 0;
upload-size = 0;
+ upload-offset = 0;
upload-ptr = NULL;
upload-buffer = NULL;
}
@@ -105,7 +106,8 @@ int r600_upload_buffer(struct r600_upload *upload, unsigned
offset,
memcpy(upload-ptr + upload-offset, (uint8_t *) in_ptr + offset, size);
*out_offset = upload-offset;
*out_size = upload-size;
- *out_buffer = upload-buffer;
+ *out_buffer = NULL;
+ r600_bo_reference(upload-rctx-radeon, out_buffer, upload-buffer);
upload-offset += alloc_size;
return 0;
___
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Mesa (master): r600g: fix pow(0, 0) evaluating to NaN
Module: Mesa Branch: master Commit: 66f55de31e15f97ad1d16c573756738218c02109 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=66f55de31e15f97ad1d16c573756738218c02109 Author: Fredrik Höglund fred...@kde.org Date: Wed Dec 15 20:00:42 2010 +0100 r600g: fix pow(0, 0) evaluating to NaN We have to use the non-IEEE compliant version of MUL here, since log2(0) is -inf, and 0 * -inf is NaN in IEEE arithmetic. candidates for 7.10 branch --- src/gallium/drivers/r600/r600_shader.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/gallium/drivers/r600/r600_shader.c b/src/gallium/drivers/r600/r600_shader.c index d645502..9c7b7f0 100644 --- a/src/gallium/drivers/r600/r600_shader.c +++ b/src/gallium/drivers/r600/r600_shader.c @@ -1451,7 +1451,7 @@ static int tgsi_pow(struct r600_shader_ctx *ctx) return r; /* b * LOG2(a) */ memset(alu, 0, sizeof(struct r600_bc_alu)); - alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL_IEEE); + alu.inst = CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MUL); r = tgsi_src(ctx, inst-Src[1], alu.src[0]); if (r) return r; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): gallium: properly check for src-dst blit compatibilities
Module: Mesa
Branch: master
Commit: dbb679e51d7e91e98d1d48d0c93be69bfabbba23
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dbb679e51d7e91e98d1d48d0c93be69bfabbba23
Author: Jerome Glisse jgli...@redhat.com
Date: Wed Dec 15 15:27:16 2010 -0500
gallium: properly check for src-dst blit compatibilities
Spotted by Christoph Bumiller Jose Fonseca
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/auxiliary/util/u_blitter.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_blitter.c
b/src/gallium/auxiliary/util/u_blitter.c
index 4c986e3..545021d 100644
--- a/src/gallium/auxiliary/util/u_blitter.c
+++ b/src/gallium/auxiliary/util/u_blitter.c
@@ -738,8 +738,8 @@ void util_blitter_copy_region(struct blitter_context
*blitter,
assert(!is_overlap(srcbox-x, srcbox-x + width, srcbox-y, srcbox-y +
height,
dstx, dstx + width, dsty, dsty + height));
} else {
- assert(util_is_format_compatible(util_format_description(dst-format),
- util_format_description(src-format)));
+ assert(util_is_format_compatible(util_format_description(src-format),
+ util_format_description(dst-format)));
}
assert(src-target PIPE_MAX_TEXTURE_TYPES);
/* XXX should handle 3d regions */
___
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Mesa (master): r600g: fix segfault when translating vertex buffer
Module: Mesa
Branch: master
Commit: 54773415f407678eb9728ac347cc8302e2d76c74
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=54773415f407678eb9728ac347cc8302e2d76c74
Author: Jerome Glisse jgli...@redhat.com
Date: Tue Dec 14 13:50:46 2010 -0500
r600g: fix segfault when translating vertex buffer
Note the support for non float vertex draw likely regressed need to
find what we want to do there.
candidates for 7.10 branches
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_state.c |5 -
src/gallium/drivers/r600/r600_state.c|9 -
src/gallium/drivers/r600/r600_state_common.c |5 +
src/gallium/drivers/r600/r600_translate.c| 12 +---
4 files changed, 10 insertions(+), 21 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index a9d4a86..07496eb 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1295,11 +1295,6 @@ void evergreen_vertex_buffer_update(struct
r600_pipe_context *rctx)
if (rctx-vertex_elements == NULL || !rctx-nvertex_buffer)
return;
- /* delete previous translated vertex elements */
- if (rctx-tran.new_velems) {
- r600_end_vertex_translate(rctx);
- }
-
if (rctx-vertex_elements-incompatible_layout) {
/* translate rebind new vertex elements so
* return once translated
diff --git a/src/gallium/drivers/r600/r600_state.c
b/src/gallium/drivers/r600/r600_state.c
index 67ea217..cd5f079 100644
--- a/src/gallium/drivers/r600/r600_state.c
+++ b/src/gallium/drivers/r600/r600_state.c
@@ -135,11 +135,6 @@ void r600_vertex_buffer_update(struct r600_pipe_context
*rctx)
if (rctx-vertex_elements == NULL || !rctx-nvertex_buffer)
return;
- /* delete previous translated vertex elements */
- if (rctx-tran.new_velems) {
- r600_end_vertex_translate(rctx);
- }
-
if (rctx-vertex_elements-incompatible_layout) {
/* translate rebind new vertex elements so
* return once translated
@@ -280,7 +275,6 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_drawl draw;
- boolean translate = FALSE;
memset(draw, 0, sizeof(struct r600_drawl));
draw.ctx = ctx;
@@ -312,9 +306,6 @@ void r600_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
}
r600_draw_common(draw);
- if (translate)
- r600_end_vertex_translate(rctx);
-
pipe_resource_reference(draw.index_buffer, NULL);
}
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index 1333808..99b372c 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -119,6 +119,11 @@ void r600_bind_vertex_elements(struct pipe_context *ctx,
void *state)
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
struct r600_vertex_element *v = (struct r600_vertex_element*)state;
+ /* delete previous translated vertex elements */
+ if (rctx-tran.new_velems) {
+ r600_end_vertex_translate(rctx);
+ }
+
rctx-vertex_elements = v;
if (v) {
rctx-states[v-rstate.id] = v-rstate;
diff --git a/src/gallium/drivers/r600/r600_translate.c
b/src/gallium/drivers/r600/r600_translate.c
index 1c227d3..ba12eee 100644
--- a/src/gallium/drivers/r600/r600_translate.c
+++ b/src/gallium/drivers/r600/r600_translate.c
@@ -42,6 +42,7 @@ void r600_begin_vertex_translate(struct r600_pipe_context
*rctx)
struct pipe_resource *out_buffer;
unsigned i, num_verts;
struct pipe_vertex_element new_velems[PIPE_MAX_ATTRIBS];
+ void *tmp;
/* Initialize the translate key, i.e. the recipe how vertices should be
* translated. */
@@ -159,8 +160,9 @@ void r600_begin_vertex_translate(struct r600_pipe_context
*rctx)
}
}
- rctx-tran.new_velems = pipe-create_vertex_elements_state(pipe,
ve-count, new_velems);
- pipe-bind_vertex_elements_state(pipe, rctx-tran.new_velems);
+ tmp = pipe-create_vertex_elements_state(pipe, ve-count, new_velems);
+ pipe-bind_vertex_elements_state(pipe, tmp);
+ rctx-tran.new_velems = tmp;
pipe_resource_reference(out_buffer, NULL);
}
@@ -173,15 +175,11 @@ void r600_end_vertex_translate(struct r600_pipe_context
*rctx)
return;
}
/* Restore vertex elements. */
- if (rctx-vertex_elements == rctx-tran.new_velems) {
- pipe-bind_vertex_elements_state(pipe, NULL);
- }
pipe-delete_vertex_elements_state(pipe, rctx-tran.new_velems
Mesa (master): r600g: fix bo size when creating bo from handle
Module: Mesa Branch: master Commit: b22c8e8bbcdff7933b0354197c101738c99ea7d0 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b22c8e8bbcdff7933b0354197c101738c99ea7d0 Author: Jerome Glisse jgli...@redhat.com Date: Fri Dec 10 11:17:27 2010 -0500 r600g: fix bo size when creating bo from handle Spoted by Alex Diomin Signed-off-by: Jerome Glisse jgli...@redhat.com --- src/gallium/winsys/r600/drm/r600_bo.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/gallium/winsys/r600/drm/r600_bo.c b/src/gallium/winsys/r600/drm/r600_bo.c index 137402c..6a3737f 100644 --- a/src/gallium/winsys/r600/drm/r600_bo.c +++ b/src/gallium/winsys/r600/drm/r600_bo.c @@ -85,7 +85,7 @@ struct r600_bo *r600_bo_handle(struct radeon *radeon, free(bo); return NULL; } - bo-size = bo-size; + bo-size = rbo-size; bo-domains = (RADEON_GEM_DOMAIN_CPU | RADEON_GEM_DOMAIN_GTT | RADEON_GEM_DOMAIN_VRAM); ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: avoid using pb* helper we are loosing previous cpu cycle with it
Module: Mesa
Branch: master
Commit: 15753cf54d57b1ebb0cd41b7dbb8030d23213891
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=15753cf54d57b1ebb0cd41b7dbb8030d23213891
Author: Jerome Glisse jgli...@redhat.com
Date: Thu Dec 9 13:07:10 2010 -0500
r600g: avoid using pb* helper we are loosing previous cpu cycle with it
r600g is up to a point where all small CPU cycle matter and pb* turn
high on profile. It's mostly because pb try to be generic and thus
trigger unecessary check for r600g driver. To avoid having too much
abstraction too much depth in the call embedded everythings into
r600_bo. Make code simpler faster. The performance win highly depend
on the CPU application considered being more important on slower CPU
and marginal/unoticeable on faster one.
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/winsys/r600/drm/Makefile |4 +-
src/gallium/winsys/r600/drm/evergreen_hw_context.c |1 -
src/gallium/winsys/r600/drm/r600.c |1 -
src/gallium/winsys/r600/drm/r600_bo.c | 171 +++--
src/gallium/winsys/r600/drm/r600_bomgr.c | 161
src/gallium/winsys/r600/drm/r600_drm.c | 16 +-
src/gallium/winsys/r600/drm/r600_hw_context.c | 19 +-
src/gallium/winsys/r600/drm/r600_priv.h| 119 +++--
src/gallium/winsys/r600/drm/radeon_bo_pb.c | 260
9 files changed, 364 insertions(+), 388 deletions(-)
diff --git a/src/gallium/winsys/r600/drm/Makefile
b/src/gallium/winsys/r600/drm/Makefile
index a396205..91c6501 100644
--- a/src/gallium/winsys/r600/drm/Makefile
+++ b/src/gallium/winsys/r600/drm/Makefile
@@ -8,12 +8,12 @@ C_SOURCES = \
bof.c \
evergreen_hw_context.c \
radeon_bo.c \
- radeon_bo_pb.c \
radeon_pciid.c \
r600.c \
r600_bo.c \
r600_drm.c \
- r600_hw_context.c
+ r600_hw_context.c \
+ r600_bomgr.c
LIBRARY_INCLUDES = -I$(TOP)/src/gallium/drivers/r600 \
$(shell pkg-config libdrm --cflags-only-I)
diff --git a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
index e1f163e..2175d57 100644
--- a/src/gallium/winsys/r600/drm/evergreen_hw_context.c
+++ b/src/gallium/winsys/r600/drm/evergreen_hw_context.c
@@ -36,7 +36,6 @@
#include pipe/p_compiler.h
#include util/u_inlines.h
#include util/u_memory.h
-#include pipebuffer/pb_bufmgr.h
#include r600_priv.h
#define GROUP_FORCE_NEW_BLOCK 0
diff --git a/src/gallium/winsys/r600/drm/r600.c
b/src/gallium/winsys/r600/drm/r600.c
index f5e53e2..b88733f 100644
--- a/src/gallium/winsys/r600/drm/r600.c
+++ b/src/gallium/winsys/r600/drm/r600.c
@@ -27,7 +27,6 @@
#include radeon_drm.h
#include pipe/p_compiler.h
#include util/u_inlines.h
-#include pipebuffer/pb_bufmgr.h
#include r600_priv.h
enum radeon_family r600_get_family(struct radeon *r600)
diff --git a/src/gallium/winsys/r600/drm/r600_bo.c
b/src/gallium/winsys/r600/drm/r600_bo.c
index 251f009..933b169 100644
--- a/src/gallium/winsys/r600/drm/r600_bo.c
+++ b/src/gallium/winsys/r600/drm/r600_bo.c
@@ -36,142 +36,153 @@ struct r600_bo *r600_bo(struct radeon *radeon,
unsigned size, unsigned alignment,
unsigned binding, unsigned usage)
{
- struct r600_bo *ws_bo = calloc(1, sizeof(struct r600_bo));
- struct pb_desc desc;
- struct pb_manager *man;
+ struct r600_bo *bo;
+ struct radeon_bo *rbo;
- desc.alignment = alignment;
- desc.usage = (PB_USAGE_CPU_READ_WRITE | PB_USAGE_GPU_READ_WRITE);
- ws_bo-size = size;
+ if (binding (PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_VERTEX_BUFFER |
PIPE_BIND_INDEX_BUFFER)) {
+ bo = r600_bomgr_bo_create(radeon-bomgr, size, alignment,
*radeon-cfence);
+ if (bo) {
+ return bo;
+ }
+ }
- if (binding (PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_VERTEX_BUFFER |
PIPE_BIND_INDEX_BUFFER))
- man = radeon-cman;
- else
- man = radeon-kman;
+ rbo = radeon_bo(radeon, 0, size, alignment);
+ if (rbo == NULL) {
+ return NULL;
+ }
+
+ bo = calloc(1, sizeof(struct r600_bo));
+ bo-size = size;
+ bo-alignment = alignment;
+ bo-bo = rbo;
+ if (binding (PIPE_BIND_CONSTANT_BUFFER | PIPE_BIND_VERTEX_BUFFER |
PIPE_BIND_INDEX_BUFFER)) {
+ r600_bomgr_bo_init(radeon-bomgr, bo);
+ }
/* Staging resources particpate in transfers and blits only
* and are used for uploads and downloads from regular
* resources. We generate them internally for some transfers.
*/
if (usage == PIPE_USAGE_STAGING)
-ws_bo-domains = RADEON_GEM_DOMAIN_CPU | RADEON_GEM_DOMAIN_GTT;
-else
-ws_bo-domains = (RADEON_GEM_DOMAIN_CPU
Mesa (master): r600g: specialized upload manager
Module: Mesa
Branch: master
Commit: 7055068eeae7f64166cca513282829d5a3e9b9d3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7055068eeae7f64166cca513282829d5a3e9b9d3
Author: Jerome Glisse jgli...@redhat.com
Date: Wed Dec 8 13:41:25 2010 -0500
r600g: specialized upload manager
Allow important performance increase by doing hw specific implementation
of the upload manager helper. Drop the range flushing that is not hit with
this code (and wasn't with previous neither). Performance improvement are
mostly visible on slow CPU.
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/Makefile |3 +-
src/gallium/drivers/r600/evergreen_state.c |2 +-
src/gallium/drivers/r600/r600_buffer.c | 114 +---
src/gallium/drivers/r600/r600_pipe.c | 21 +
src/gallium/drivers/r600/r600_pipe.h |5 +-
src/gallium/drivers/r600/r600_resource.h | 25 --
src/gallium/drivers/r600/r600_state.c |3 +-
src/gallium/drivers/r600/r600_upload.c | 112 +++
8 files changed, 176 insertions(+), 109 deletions(-)
diff --git a/src/gallium/drivers/r600/Makefile
b/src/gallium/drivers/r600/Makefile
index a484f38..b476b9a 100644
--- a/src/gallium/drivers/r600/Makefile
+++ b/src/gallium/drivers/r600/Makefile
@@ -21,6 +21,7 @@ C_SOURCES = \
evergreen_state.c \
eg_asm.c \
r600_translate.c \
- r600_state_common.c
+ r600_state_common.c \
+ r600_upload.c
include ../../Makefile.template
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 9e1a5e1..a9d4a86 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1346,7 +1346,7 @@ void evergreen_vertex_buffer_update(struct
r600_pipe_context *rctx)
r600_pipe_state_add_reg(rstate, R_03_RESOURCE0_WORD0,
offset, 0x, rbuffer-bo);
r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
- rbuffer-size - offset - 1, 0x,
NULL);
+ rbuffer-bo_size - offset - 1,
0x, NULL);
r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
S_030008_STRIDE(vertex_buffer-stride),
0x, NULL);
diff --git a/src/gallium/drivers/r600/r600_buffer.c
b/src/gallium/drivers/r600/r600_buffer.c
index 03a61a3..7d29f76 100644
--- a/src/gallium/drivers/r600/r600_buffer.c
+++ b/src/gallium/drivers/r600/r600_buffer.c
@@ -29,7 +29,6 @@
#include util/u_math.h
#include util/u_inlines.h
#include util/u_memory.h
-#include util/u_upload_mgr.h
#include state_tracker/drm_driver.h
#include xf86drm.h
#include radeon_drm.h
@@ -53,12 +52,13 @@ struct pipe_resource *r600_buffer_create(struct pipe_screen
*screen,
rbuffer-magic = R600_BUFFER_MAGIC;
rbuffer-user_buffer = NULL;
- rbuffer-num_ranges = 0;
rbuffer-r.base.b = *templ;
pipe_reference_init(rbuffer-r.base.b.reference, 1);
rbuffer-r.base.b.screen = screen;
rbuffer-r.base.vtbl = r600_buffer_vtbl;
rbuffer-r.size = rbuffer-r.base.b.width0;
+ rbuffer-r.bo_size = rbuffer-r.size;
+ rbuffer-uploaded = FALSE;
bo = r600_bo((struct radeon*)screen-winsys, rbuffer-r.base.b.width0,
alignment, rbuffer-r.base.b.bind, rbuffer-r.base.b.usage);
if (bo == NULL) {
FREE(rbuffer);
@@ -91,9 +91,10 @@ struct pipe_resource *r600_user_buffer_create(struct
pipe_screen *screen,
rbuffer-r.base.b.depth0 = 1;
rbuffer-r.base.b.array_size = 1;
rbuffer-r.base.b.flags = 0;
- rbuffer-num_ranges = 0;
rbuffer-r.bo = NULL;
+ rbuffer-r.bo_size = 0;
rbuffer-user_buffer = ptr;
+ rbuffer-uploaded = FALSE;
return rbuffer-r.base.b;
}
@@ -102,9 +103,10 @@ static void r600_buffer_destroy(struct pipe_screen *screen,
{
struct r600_resource_buffer *rbuffer = r600_buffer(buf);
- if (rbuffer-r.bo) {
+ if (!rbuffer-uploaded rbuffer-r.bo) {
r600_bo_reference((struct radeon*)screen-winsys,
rbuffer-r.bo, NULL);
}
+ rbuffer-r.bo = NULL;
FREE(rbuffer);
}
@@ -114,29 +116,10 @@ static void *r600_buffer_transfer_map(struct pipe_context
*pipe,
struct r600_resource_buffer *rbuffer = r600_buffer(transfer-resource);
int write = 0;
uint8_t *data;
- int i;
- boolean flush = FALSE;
if (rbuffer-user_buffer)
return (uint8_t*)rbuffer-user_buffer + transfer-box.x;
- if (transfer-usage PIPE_TRANSFER_DISCARD) {
- for (i = 0; i rbuffer-num_ranges; i++) {
- if ((transfer-box.x = rbuffer-ranges[i].start)
- (transfer-box.x
Mesa (master): r600g: indentation cleanup
Module: Mesa
Branch: master
Commit: 121079bd679ea0729834cca79ab3c424e006feed
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=121079bd679ea0729834cca79ab3c424e006feed
Author: Jerome Glisse jgli...@redhat.com
Date: Thu Dec 9 16:16:22 2010 -0500
r600g: indentation cleanup
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/r600_pipe.h |4 +-
src/gallium/drivers/r600/r600_resource.h | 40 ++---
2 files changed, 21 insertions(+), 23 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index f7f6f63..43dbee9 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -111,7 +111,7 @@ struct r600_pipe_shader {
#define NUM_TEX_UNITS 16
struct r600_textures_info {
- struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
+ struct r600_pipe_sampler_view *views[NUM_TEX_UNITS];
unsignedn_views;
void*samplers[NUM_TEX_UNITS];
unsignedn_samplers;
@@ -271,13 +271,13 @@ void r600_sampler_view_destroy(struct pipe_context *ctx,
void r600_bind_state(struct pipe_context *ctx, void *state);
void r600_delete_state(struct pipe_context *ctx, void *state);
void r600_bind_vertex_elements(struct pipe_context *ctx, void *state);
-
void *r600_create_shader_state(struct pipe_context *ctx,
const struct pipe_shader_state *state);
void r600_bind_ps_shader(struct pipe_context *ctx, void *state);
void r600_bind_vs_shader(struct pipe_context *ctx, void *state);
void r600_delete_ps_shader(struct pipe_context *ctx, void *state);
void r600_delete_vs_shader(struct pipe_context *ctx, void *state);
+
/*
* common helpers
*/
diff --git a/src/gallium/drivers/r600/r600_resource.h
b/src/gallium/drivers/r600/r600_resource.h
index e21916f..8ca2769 100644
--- a/src/gallium/drivers/r600/r600_resource.h
+++ b/src/gallium/drivers/r600/r600_resource.h
@@ -62,7 +62,21 @@ struct r600_resource_texture {
unsignedtile_type;
unsigneddepth;
unsigneddirty;
- struct r600_resource_texture*flushed_depth_texture;
+ struct r600_resource_texture*flushed_depth_texture;
+};
+
+#define R600_BUFFER_MAGIC 0xabcd1600
+
+struct r600_resource_buffer {
+ struct r600_resourcer;
+ uint32_tmagic;
+ void*user_buffer;
+ booluploaded;
+};
+
+struct r600_surface {
+ struct pipe_surface base;
+ unsignedaligned_height;
};
void r600_init_screen_resource_functions(struct pipe_screen *screen);
@@ -74,23 +88,14 @@ struct pipe_resource *r600_texture_from_handle(struct
pipe_screen *screen,
const struct pipe_resource
*base,
struct winsys_handle *whandle);
-#define R600_BUFFER_MAGIC 0xabcd1600
-
-struct r600_resource_buffer {
- struct r600_resource r;
- uint32_t magic;
- void *user_buffer;
- bool uploaded;
-};
-
/* r600_buffer */
static INLINE struct r600_resource_buffer *r600_buffer(struct pipe_resource
*buffer)
{
if (buffer) {
assert(((struct r600_resource_buffer *)buffer)-magic ==
R600_BUFFER_MAGIC);
return (struct r600_resource_buffer *)buffer;
-}
-return NULL;
+ }
+ return NULL;
}
static INLINE boolean r600_buffer_is_user_buffer(struct pipe_resource *buffer)
@@ -100,10 +105,8 @@ static INLINE boolean r600_buffer_is_user_buffer(struct
pipe_resource *buffer)
return r600_buffer(buffer)-user_buffer ? TRUE : FALSE;
}
-int r600_texture_depth_flush(struct pipe_context *ctx,
-struct pipe_resource *texture);
-
-extern int (*r600_blit_uncompress_depth_ptr)(struct pipe_context *ctx, struct
r600_resource_texture *texture);
+int r600_texture_depth_flush(struct pipe_context *ctx, struct pipe_resource
*texture);
+int (*r600_blit_uncompress_depth_ptr)(struct pipe_context *ctx, struct
r600_resource_texture *texture);
/* r600_texture.c texture transfer functions. */
struct pipe_transfer* r600_texture_get_transfer(struct pipe_context *ctx,
@@ -118,11 +121,6 @@ void* r600_texture_transfer_map(struct pipe_context *ctx,
void r600_texture_transfer_unmap(struct pipe_context *ctx,
struct pipe_transfer* transfer);
-struct r600_surface {
- struct pipe_surface base;
- unsigned aligned_height;
-};
-
struct r600_pipe_context;
struct r600_upload *r600_upload_create(struct r600_pipe_context *rctx,
unsigned default_size,
___
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mesa
Mesa (master): r600g: remove dead code
Module: Mesa
Branch: master
Commit: 69251fc4cd5f71be403e08398bc43d19052a640d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=69251fc4cd5f71be403e08398bc43d19052a640d
Author: Jerome Glisse jgli...@redhat.com
Date: Tue Dec 7 16:11:51 2010 -0500
r600g: remove dead code
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_state.c | 77 +---
src/gallium/drivers/r600/r600_asm.c|2 +-
src/gallium/drivers/r600/r600_pipe.h |2 +-
src/gallium/drivers/r600/r600_shader.c | 140 +---
src/gallium/drivers/r600/r600_shader.h |1 -
src/gallium/drivers/r600/r600_state.c | 54 +---
6 files changed, 8 insertions(+), 268 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index feb30f3..9e1a5e1 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1372,27 +1372,12 @@ int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info
*info)
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
- struct r600_pipe_state *rstate;
struct r600_resource *rbuffer;
- unsigned i, j, offset, prim;
u32 vgt_dma_index_type, vgt_draw_initiator, mask;
- struct pipe_vertex_buffer *vertex_buffer;
struct r600_draw rdraw;
struct r600_pipe_state vgt;
struct r600_drawl draw;
- boolean translate = FALSE;
-
-#if 0
- if (rctx-vertex_elements-incompatible_layout) {
- r600_begin_vertex_translate(rctx);
- translate = TRUE;
- }
-
- if (rctx-any_user_vbs) {
- r600_upload_user_buffers(rctx);
- rctx-any_user_vbs = FALSE;
- }
-#endif
+ unsigned prim;
memset(draw, 0, sizeof(struct r600_drawl));
draw.ctx = ctx;
@@ -1457,53 +1442,8 @@ void evergreen_draw(struct pipe_context *ctx, const
struct pipe_draw_info *info)
return;
}
-#if 0
- /* rebuild vertex shader if input format changed */
- if (r600_pipe_shader_update(rctx-context, rctx-vs_shader))
- return;
- if (r600_pipe_shader_update(rctx-context, rctx-ps_shader))
- return;
-#endif
-
evergreen_spi_update(rctx);
-#if 0
- for (i = 0 ; i rctx-vertex_elements-count; i++) {
- uint32_t word3, word2;
- uint32_t format;
- rstate = rctx-vs_resource[i];
-
- rstate-id = R600_PIPE_STATE_RESOURCE;
- rstate-nregs = 0;
-
- j = rctx-vertex_elements-elements[i].vertex_buffer_index;
- vertex_buffer = rctx-vertex_buffer[j];
- rbuffer = (struct r600_resource*)vertex_buffer-buffer;
- offset = rctx-vertex_elements-elements[i].src_offset +
- vertex_buffer-buffer_offset +
- r600_bo_offset(rbuffer-bo);
-
- format =
r600_translate_vertex_data_type(rctx-vertex_elements-hw_format[i]);
-
- word2 = format | S_030008_STRIDE(vertex_buffer-stride);
-
- word3 = S_03000C_DST_SEL_X(V_03000C_SQ_SEL_X) |
- S_03000C_DST_SEL_Y(V_03000C_SQ_SEL_Y) |
- S_03000C_DST_SEL_Z(V_03000C_SQ_SEL_Z) |
- S_03000C_DST_SEL_W(V_03000C_SQ_SEL_W);
-
- r600_pipe_state_add_reg(rstate, R_03_RESOURCE0_WORD0,
offset, 0x, rbuffer-bo);
- r600_pipe_state_add_reg(rstate, R_030004_RESOURCE0_WORD1,
rbuffer-size - offset - 1, 0x, NULL);
- r600_pipe_state_add_reg(rstate, R_030008_RESOURCE0_WORD2,
word2, 0x, NULL);
- r600_pipe_state_add_reg(rstate, R_03000C_RESOURCE0_WORD3,
word3, 0x, NULL);
- r600_pipe_state_add_reg(rstate, R_030010_RESOURCE0_WORD4,
0x, 0x, NULL);
- r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5,
0x, 0x, NULL);
- r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6,
0x, 0x, NULL);
- r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7,
0xC000, 0x, NULL);
- evergreen_fs_resource_set(rctx-ctx, rstate, i);
- }
-#endif
-
mask = 0;
for (int i = 0; i rctx-framebuffer.nr_cbufs; i++) {
mask |= (0xF (i * 4));
@@ -1532,18 +1472,14 @@ void evergreen_draw(struct pipe_context *ctx, const
struct pipe_draw_info *info)
}
evergreen_context_draw(rctx-ctx, rdraw);
- if (translate)
- r600_end_vertex_translate(rctx);
-
pipe_resource_reference(draw.index_buffer, NULL);
}
void evergreen_pipe_shader_ps(struct pipe_context *ctx, struct
r600_pipe_shader *shader)
{
- struct
Mesa (master): r600g: fix userspace fence against lastest kernel
Module: Mesa Branch: master Commit: b7617346dcff50a66a10c61b95c33682cf629c9e URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b7617346dcff50a66a10c61b95c33682cf629c9e Author: Jerome Glisse jgli...@redhat.com Date: Tue Dec 7 15:15:58 2010 -0500 r600g: fix userspace fence against lastest kernel R6XX GPU doesn't like to have two partial flush writting back to memory in row without a prior flush of the pipeline. Add PS_PARTIAL_FLUSH to flush all work between the CP and the ES, GS, VS, PS shaders. Thanks a lot to Alban Browaeys (prahal on irc) for investigating this issue. Signed-off-by: Alban Browaeys pra...@yahoo.com Signed-off-by: Jerome Glisse jgli...@redhat.com --- src/gallium/winsys/r600/drm/r600_hw_context.c |2 ++ src/gallium/winsys/r600/drm/r600d.h |1 + 2 files changed, 3 insertions(+), 0 deletions(-) diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c b/src/gallium/winsys/r600/drm/r600_hw_context.c index b2da7bf..0f2724f 100644 --- a/src/gallium/winsys/r600/drm/r600_hw_context.c +++ b/src/gallium/winsys/r600/drm/r600_hw_context.c @@ -1112,6 +1112,8 @@ void r600_context_flush(struct r600_context *ctx) r600_context_queries_suspend(ctx); /* emit fence */ + ctx-pm4[ctx-pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 0); + ctx-pm4[ctx-pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_PS_PARTIAL_FLUSH) | EVENT_INDEX(4); ctx-pm4[ctx-pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4); ctx-pm4[ctx-pm4_cdwords++] = EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5); ctx-pm4[ctx-pm4_cdwords++] = 0; diff --git a/src/gallium/winsys/r600/drm/r600d.h b/src/gallium/winsys/r600/drm/r600d.h index 4a08d50..1c1ac76 100644 --- a/src/gallium/winsys/r600/drm/r600d.h +++ b/src/gallium/winsys/r600/drm/r600d.h @@ -91,6 +91,7 @@ #define PKT3_SET_CTL_CONST 0x6F #define PKT3_SURFACE_BASE_UPDATE 0x73 +#define EVENT_TYPE_PS_PARTIAL_FLUSH0x10 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14 #define EVENT_TYPE_ZPASS_DONE 0x15 #define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16 ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): r600g: build fetch shader from vertex elements
Module: Mesa
Branch: master
Commit: fa86fc564aea4e40c89f6fc889e6a5bf817634b3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa86fc564aea4e40c89f6fc889e6a5bf817634b3
Author: Jerome Glisse jgli...@redhat.com
Date: Fri Dec 3 20:47:02 2010 -0500
r600g: build fetch shader from vertex elements
Vertex elements change are less frequent than draw call, those to
avoid rebuilding fetch shader to often build the fetch shader along
vertex elements. This also allow to move vertex buffer setup out
of draw path and make update to it less frequent.
Shader update can still be improved to only update SPI regs (based
on some rasterizer state like flat shading or point sprite ...).
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/eg_asm.c| 35 +++
src/gallium/drivers/r600/evergreen_state.c | 97 -
src/gallium/drivers/r600/r600_asm.c | 317 ++
src/gallium/drivers/r600/r600_asm.h |8 +
src/gallium/drivers/r600/r600_buffer.c |5 +-
src/gallium/drivers/r600/r600_pipe.c |2 +
src/gallium/drivers/r600/r600_pipe.h | 20 ++-
src/gallium/drivers/r600/r600_shader.c | 18 +-
src/gallium/drivers/r600/r600_state.c| 83 +++
src/gallium/drivers/r600/r600_state_common.c | 35 +++-
src/gallium/drivers/r600/r600_translate.c| 43 ++--
11 files changed, 619 insertions(+), 44 deletions(-)
diff --git a/src/gallium/drivers/r600/eg_asm.c
b/src/gallium/drivers/r600/eg_asm.c
index 21d66fa..b79875c 100644
--- a/src/gallium/drivers/r600/eg_asm.c
+++ b/src/gallium/drivers/r600/eg_asm.c
@@ -27,6 +27,7 @@
#include r600_asm.h
#include eg_sq.h
#include r600_opcodes.h
+#include evergreend.h
int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
{
@@ -89,3 +90,37 @@ int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf)
}
return 0;
}
+
+void eg_cf_vtx(struct r600_vertex_element *ve, u32 *bytecode, unsigned count)
+{
+ struct r600_pipe_state *rstate;
+ unsigned i = 0;
+
+ if (count 8) {
+ bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 1);
+ bytecode[i++] =
S_SQ_CF_WORD1_CF_INST(EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
+ S_SQ_CF_WORD1_BARRIER(1) |
+ S_SQ_CF_WORD1_COUNT(8 - 1);
+ bytecode[i++] = S_SQ_CF_WORD0_ADDR(40 1);
+ bytecode[i++] =
S_SQ_CF_WORD1_CF_INST(EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
+ S_SQ_CF_WORD1_BARRIER(1) |
+ S_SQ_CF_WORD1_COUNT(count - 8 - 1);
+ } else {
+ bytecode[i++] = S_SQ_CF_WORD0_ADDR(8 1);
+ bytecode[i++] =
S_SQ_CF_WORD1_CF_INST(EG_V_SQ_CF_WORD1_SQ_CF_INST_VTX) |
+ S_SQ_CF_WORD1_BARRIER(1) |
+ S_SQ_CF_WORD1_COUNT(count - 1);
+ }
+ bytecode[i++] = S_SQ_CF_WORD0_ADDR(0);
+ bytecode[i++] =
S_SQ_CF_WORD1_CF_INST(EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN) |
+ S_SQ_CF_WORD1_BARRIER(1);
+
+ rstate = ve-rstate;
+ rstate-id = R600_PIPE_STATE_FETCH_SHADER;
+ rstate-nregs = 0;
+ r600_pipe_state_add_reg(rstate, R_0288A8_SQ_PGM_RESOURCES_FS,
+ 0x, 0x, NULL);
+ r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS,
+ (r600_bo_offset(ve-fetch_shader)) 8,
+ 0x, ve-fetch_shader);
+}
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index ebd541d..b313d52 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1259,6 +1259,90 @@ void evergreen_polygon_offset_update(struct
r600_pipe_context *rctx)
}
}
+void evergreen_vertex_buffer_update(struct r600_pipe_context *rctx)
+{
+ struct r600_pipe_state *rstate;
+ struct r600_resource *rbuffer;
+ struct pipe_vertex_buffer *vertex_buffer;
+ unsigned i, offset;
+
+ /* we don't update until we know vertex elements */
+ if (rctx-vertex_elements == NULL || !rctx-nvertex_buffer)
+ return;
+
+ /* delete previous translated vertex elements */
+ if (rctx-tran.new_velems) {
+ r600_end_vertex_translate(rctx);
+ }
+
+ if (rctx-vertex_elements-incompatible_layout) {
+ /* translate rebind new vertex elements so
+* return once translated
+*/
+ r600_begin_vertex_translate(rctx);
+ return;
+ }
+
+ if (rctx-any_user_vbs) {
+ r600_upload_user_buffers(rctx);
+ rctx-any_user_vbs = FALSE;
+ }
+
+ if (rctx-vertex_elements-vbuffer_need_offset) {
+ /* one resource per vertex elements */
+ rctx-nvs_resource = rctx
Mesa (master): r600g: avoid useless shader rebuild at draw call
Module: Mesa
Branch: master
Commit: afc56b1861c1dae4137493af4c0e6dacc6ee41f9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=afc56b1861c1dae4137493af4c0e6dacc6ee41f9
Author: Jerome Glisse jgli...@redhat.com
Date: Sun Dec 5 19:24:03 2010 -0500
r600g: avoid useless shader rebuild at draw call
Avoid rebuilding constant shader state at each draw call,
factor out spi update that might change at each draw call.
Best would be to update spi only when revealent states
change (likely only flat shading sprite point).
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_state.c | 55 --
src/gallium/drivers/r600/r600_pipe.c |4 +-
src/gallium/drivers/r600/r600_shader.c | 36 ++--
src/gallium/drivers/r600/r600_shader.h |1 -
src/gallium/drivers/r600/r600_state.c| 50 +++-
src/gallium/drivers/r600/r600_state_common.c |6 +++
src/gallium/drivers/r600/r600_translate.c|3 +
7 files changed, 108 insertions(+), 47 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index b313d52..feb30f3 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1239,6 +1239,7 @@ void evergreen_polygon_offset_update(struct
r600_pipe_context *rctx)
default:
return;
}
+ /* FIXME some of those reg can be computed with cso */
offset_db_fmt_cntl |=
S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
r600_pipe_state_add_reg(state,
R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
@@ -1259,6 +1260,30 @@ void evergreen_polygon_offset_update(struct
r600_pipe_context *rctx)
}
}
+static void evergreen_spi_update(struct r600_pipe_context *rctx)
+{
+ struct r600_pipe_shader *shader = rctx-ps_shader;
+ struct r600_pipe_state rstate;
+ struct r600_shader *rshader = shader-shader;
+ unsigned i, tmp;
+
+ rstate.nregs = 0;
+ for (i = 0; i rshader-ninput; i++) {
+ tmp =
S_028644_SEMANTIC(r600_find_vs_semantic_index(rctx-vs_shader-shader,
rshader, i));
+ if (rshader-input[i].name == TGSI_SEMANTIC_COLOR ||
+ rshader-input[i].name == TGSI_SEMANTIC_BCOLOR
||
+ rshader-input[i].name ==
TGSI_SEMANTIC_POSITION) {
+ tmp |= S_028644_FLAT_SHADE(rctx-flatshade);
+ }
+ if (rshader-input[i].name == TGSI_SEMANTIC_GENERIC
+ rctx-sprite_coord_enable (1
rshader-input[i].sid)) {
+ tmp |= S_028644_PT_SPRITE_TEX(1);
+ }
+ r600_pipe_state_add_reg(rstate, R_028644_SPI_PS_INPUT_CNTL_0 +
i * 4, tmp, 0x, NULL);
+ }
+ r600_context_pipe_state_set(rctx-ctx, rstate);
+}
+
void evergreen_vertex_buffer_update(struct r600_pipe_context *rctx)
{
struct r600_pipe_state *rstate;
@@ -1417,12 +1442,30 @@ void evergreen_draw(struct pipe_context *ctx, const
struct pipe_draw_info *info)
}
if (r600_conv_pipe_prim(draw.mode, prim))
return;
+ if (unlikely(rctx-ps_shader == NULL)) {
+ R600_ERR(missing vertex shader\n);
+ return;
+ }
+ if (unlikely(rctx-vs_shader == NULL)) {
+ R600_ERR(missing vertex shader\n);
+ return;
+ }
+ /* there should be enough input */
+ if (rctx-vertex_elements-count
rctx-vs_shader-shader.bc.nresource) {
+ R600_ERR(%d resources provided, expecting %d\n,
+ rctx-vertex_elements-count,
rctx-vs_shader-shader.bc.nresource);
+ return;
+ }
+#if 0
/* rebuild vertex shader if input format changed */
if (r600_pipe_shader_update(rctx-context, rctx-vs_shader))
return;
if (r600_pipe_shader_update(rctx-context, rctx-ps_shader))
return;
+#endif
+
+ evergreen_spi_update(rctx);
#if 0
for (i = 0 ; i rctx-vertex_elements-count; i++) {
@@ -1506,11 +1549,9 @@ void evergreen_pipe_shader_ps(struct pipe_context *ctx,
struct r600_pipe_shader
boolean have_linear = FALSE, have_centroid = FALSE, have_perspective =
FALSE;
unsigned spi_baryc_cntl;
- /* clear previous register */
rstate-nregs = 0;
for (i = 0; i rshader-ninput; i++) {
- tmp =
S_028644_SEMANTIC(r600_find_vs_semantic_index(rctx-vs_shader-shader,
rshader, i));
/* evergreen NUM_INTERP only contains values interpolated into
the LDS,
POSITION goes via GPRs from the SC so isn't counted */
if (rshader-input[i].name == TGSI_SEMANTIC_POSITION)
@@ -1528,16 +1569,6 @@ void evergreen_pipe_shader_ps(struct
Mesa (master): r600g: remove useless flush map
Module: Mesa
Branch: master
Commit: e0d554ab787c6f356d51df4d6266d4deb1199565
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e0d554ab787c6f356d51df4d6266d4deb1199565
Author: Jerome Glisse jgli...@redhat.com
Date: Mon Dec 6 09:49:16 2010 -0500
r600g: remove useless flush map
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/winsys/r600/drm/r600_hw_context.c |2 -
src/gallium/winsys/r600/drm/radeon_bo_pb.c| 29 +
2 files changed, 1 insertions(+), 30 deletions(-)
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c
b/src/gallium/winsys/r600/drm/r600_hw_context.c
index 50b7e6d..b2da7bf 100644
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -,8 +,6 @@ void r600_context_flush(struct r600_context *ctx)
/* suspend queries */
r600_context_queries_suspend(ctx);
- radeon_bo_pbmgr_flush_maps(ctx-radeon-kman);
-
/* emit fence */
ctx-pm4[ctx-pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE_EOP, 4);
ctx-pm4[ctx-pm4_cdwords++] =
EVENT_TYPE(EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT) | EVENT_INDEX(5);
diff --git a/src/gallium/winsys/r600/drm/radeon_bo_pb.c
b/src/gallium/winsys/r600/drm/radeon_bo_pb.c
index 312552f..4bd3ae3 100644
--- a/src/gallium/winsys/r600/drm/radeon_bo_pb.c
+++ b/src/gallium/winsys/r600/drm/radeon_bo_pb.c
@@ -35,7 +35,6 @@ struct radeon_bo_pb {
struct radeon_bo *bo;
struct radeon_bo_pbmgr *mgr;
- struct list_head maplist;
};
extern const struct pb_vtbl radeon_bo_pb_vtbl;
@@ -50,7 +49,6 @@ static INLINE struct radeon_bo_pb *radeon_bo_pb(struct
pb_buffer *buf)
struct radeon_bo_pbmgr {
struct pb_manager b;
struct radeon *radeon;
- struct list_head buffer_map_list;
};
static INLINE struct radeon_bo_pbmgr *radeon_bo_pbmgr(struct pb_manager *mgr)
@@ -66,10 +64,7 @@ static void radeon_bo_pb_destroy(struct pb_buffer *_buf)
/* If this buffer is on the list of buffers to unmap,
* do the unmapping now.
*/
- if (!LIST_IS_EMPTY(buf-maplist))
- radeon_bo_unmap(buf-mgr-radeon, buf-bo);
-
- LIST_DEL(buf-maplist);
+ radeon_bo_unmap(buf-mgr-radeon, buf-bo);
radeon_bo_reference(buf-mgr-radeon, buf-bo, NULL);
FREE(buf);
}
@@ -85,7 +80,6 @@ radeon_bo_pb_map_internal(struct pb_buffer *_buf,
if (radeon_bo_map(buf-mgr-radeon, buf-bo)) {
return NULL;
}
- LIST_DELINIT(buf-maplist);
return buf-bo-data;
}
@@ -116,14 +110,11 @@ radeon_bo_pb_map_internal(struct pb_buffer *_buf,
return NULL;
}
out:
- LIST_DELINIT(buf-maplist);
return buf-bo-data;
}
static void radeon_bo_pb_unmap_internal(struct pb_buffer *_buf)
{
- struct radeon_bo_pb *buf = radeon_bo_pb(_buf);
- LIST_ADDTAIL(buf-maplist, buf-mgr-buffer_map_list);
}
static void
@@ -178,7 +169,6 @@ radeon_bo_pb_create_buffer_from_handle(struct pb_manager
*_mgr,
return NULL;
}
- LIST_INITHEAD(bo-maplist);
pipe_reference_init(bo-b.base.reference, 1);
bo-b.base.alignment = 0;
bo-b.base.usage = PB_USAGE_GPU_WRITE | PB_USAGE_GPU_READ;
@@ -211,8 +201,6 @@ radeon_bo_pb_create_buffer(struct pb_manager *_mgr,
bo-b.vtbl = radeon_bo_pb_vtbl;
bo-mgr = mgr;
- LIST_INITHEAD(bo-maplist);
-
bo-bo = radeon_bo(radeon, 0, size, desc-alignment);
if (bo-bo == NULL)
goto error2;
@@ -250,24 +238,9 @@ struct pb_manager *radeon_bo_pbmgr_create(struct radeon
*radeon)
mgr-b.flush = radeon_bo_pbmgr_flush;
mgr-radeon = radeon;
- LIST_INITHEAD(mgr-buffer_map_list);
return mgr-b;
}
-void radeon_bo_pbmgr_flush_maps(struct pb_manager *_mgr)
-{
- struct radeon_bo_pbmgr *mgr = radeon_bo_pbmgr(_mgr);
- struct radeon_bo_pb *rpb = NULL;
- struct radeon_bo_pb *t_rpb;
-
- LIST_FOR_EACH_ENTRY_SAFE(rpb, t_rpb, mgr-buffer_map_list, maplist) {
- radeon_bo_unmap(mgr-radeon, rpb-bo);
- LIST_DELINIT(rpb-maplist);
- }
-
- LIST_INITHEAD(mgr-buffer_map_list);
-}
-
struct radeon_bo *radeon_bo_pb_get_bo(struct pb_buffer *_buf)
{
struct radeon_bo_pb *buf;
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Mesa (master): r600g: dump raw shader output for debugging
Module: Mesa
Branch: master
Commit: 833f3a488a7ba0fa59e25f1e518f6b4616270143
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=833f3a488a7ba0fa59e25f1e518f6b4616270143
Author: Jerome Glisse jgli...@redhat.com
Date: Fri Dec 3 11:34:47 2010 -0500
r600g: dump raw shader output for debugging
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/r600_asm.c| 25 +
src/gallium/drivers/r600/r600_asm.h|1 +
src/gallium/drivers/r600/r600_shader.c |1 +
3 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index edadedf..73daa00 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -947,3 +947,28 @@ void r600_bc_clear(struct r600_bc *bc)
LIST_INITHEAD(cf-list);
}
+
+void r600_bc_dump(struct r600_bc *bc)
+{
+ unsigned i;
+ char chip = '6';
+
+ switch (bc-chiprev) {
+ case 1:
+ chip = '7';
+ break;
+ case 2:
+ chip = 'E';
+ break;
+ case 0:
+ default:
+ chip = '6';
+ break;
+ }
+ fprintf(stderr, bytecode %d dw ---\n, bc-ndw);
+ fprintf(stderr, %c\n, chip);
+ for (i = 0; i bc-ndw; i++) {
+ fprintf(stderr, 0x%08X\n, bc-bytecode[i]);
+ }
+ fprintf(stderr, --\n);
+}
diff --git a/src/gallium/drivers/r600/r600_asm.h
b/src/gallium/drivers/r600/r600_asm.h
index f2016af..1be5e4a 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -200,6 +200,7 @@ int r600_bc_add_output(struct r600_bc *bc, const struct
r600_bc_output *output);
int r600_bc_build(struct r600_bc *bc);
int r600_bc_add_cfinst(struct r600_bc *bc, int inst);
int r600_bc_add_alu_type(struct r600_bc *bc, const struct r600_bc_alu *alu,
int type);
+void r600_bc_dump(struct r600_bc *bc);
/* r700_asm.c */
int r700_bc_alu_build(struct r600_bc *bc, struct r600_bc_alu *alu, unsigned
id);
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index 77b1809..b6d815f 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -351,6 +351,7 @@ int r600_pipe_shader_create(struct pipe_context *ctx,
struct r600_pipe_shader *s
return r;
}
}
+//r600_bc_dump(shader-shader.bc);
//fprintf(stderr,
__\n);
return 0;
}
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Mesa (master): r600g: set address of pop instructions to next instruction
Module: Mesa
Branch: master
Commit: cd431a12bf1f0c47dac6bf10c2d9edb5726fe6fe
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd431a12bf1f0c47dac6bf10c2d9edb5726fe6fe
Author: Fabian Bieler der.f...@gmx.net
Date: Fri Dec 3 03:39:48 2010 +0100
r600g: set address of pop instructions to next instruction
---
src/gallium/drivers/r600/r600_shader.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_shader.c
b/src/gallium/drivers/r600/r600_shader.c
index b6d815f..60e6794 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -2805,6 +2805,7 @@ static int pops(struct r600_shader_ctx *ctx, int pops)
{
r600_bc_add_cfinst(ctx-bc, CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_POP));
ctx-bc-cf_last-pop_count = pops;
+ ctx-bc-cf_last-cf_addr = ctx-bc-cf_last-id + 2;
return 0;
}
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Mesa (master): r600g: update polygon offset only when rasterizer or zbuffer change
Module: Mesa
Branch: master
Commit: 0b841b0349d7aca218eac4e9d9b7b1406ad71944
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b841b0349d7aca218eac4e9d9b7b1406ad71944
Author: Jerome Glisse jgli...@redhat.com
Date: Fri Dec 3 12:20:40 2010 -0500
r600g: update polygon offset only when rasterizer or zbuffer change
Aim is to build as little state as possible in draw functions.
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_state.c | 92 +++---
src/gallium/drivers/r600/r600_pipe.h |4 +
src/gallium/drivers/r600/r600_state.c| 92 +++---
src/gallium/drivers/r600/r600_state_common.c |6 ++
4 files changed, 114 insertions(+), 80 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index bee6752..9f44645 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -833,6 +833,10 @@ static void evergreen_set_framebuffer_state(struct
pipe_context *ctx,
free(rctx-states[R600_PIPE_STATE_FRAMEBUFFER]);
rctx-states[R600_PIPE_STATE_FRAMEBUFFER] = rstate;
r600_context_pipe_state_set(rctx-ctx, rstate);
+
+ if (state-zsbuf) {
+ evergreen_polygon_offset_update(rctx);
+ }
}
static void evergreen_set_constant_buffer(struct pipe_context *ctx, uint
shader, uint index,
@@ -1208,6 +1212,54 @@ r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
r600_context_pipe_state_set(rctx-ctx, rstate);
}
+void evergreen_polygon_offset_update(struct r600_pipe_context *rctx)
+{
+ struct r600_pipe_state state;
+
+ state.id = R600_PIPE_STATE_POLYGON_OFFSET;
+ state.nregs = 0;
+ if (rctx-rasterizer rctx-framebuffer.zsbuf) {
+ float offset_units = rctx-rasterizer-offset_units;
+ unsigned offset_db_fmt_cntl = 0, depth;
+
+ switch (rctx-framebuffer.zsbuf-texture-format) {
+ case PIPE_FORMAT_Z24X8_UNORM:
+ case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
+ depth = -24;
+ offset_units *= 2.0f;
+ break;
+ case PIPE_FORMAT_Z32_FLOAT:
+ depth = -23;
+ offset_units *= 1.0f;
+ offset_db_fmt_cntl |=
S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
+ break;
+ case PIPE_FORMAT_Z16_UNORM:
+ depth = -16;
+ offset_units *= 4.0f;
+ break;
+ default:
+ return;
+ }
+ offset_db_fmt_cntl |=
S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(depth);
+ r600_pipe_state_add_reg(state,
+ R_028B80_PA_SU_POLY_OFFSET_FRONT_SCALE,
+ fui(rctx-rasterizer-offset_scale),
0x, NULL);
+ r600_pipe_state_add_reg(state,
+ R_028B84_PA_SU_POLY_OFFSET_FRONT_OFFSET,
+ fui(offset_units), 0x, NULL);
+ r600_pipe_state_add_reg(state,
+ R_028B88_PA_SU_POLY_OFFSET_BACK_SCALE,
+ fui(rctx-rasterizer-offset_scale),
0x, NULL);
+ r600_pipe_state_add_reg(state,
+ R_028B8C_PA_SU_POLY_OFFSET_BACK_OFFSET,
+ fui(offset_units), 0x, NULL);
+ r600_pipe_state_add_reg(state,
+ R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,
+ offset_db_fmt_cntl, 0x, NULL);
+ r600_context_pipe_state_set(rctx-ctx, state);
+ }
+}
+
int r600_conv_pipe_prim(unsigned pprim, unsigned *prim);
void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info
*info)
{
@@ -1336,46 +1388,6 @@ void evergreen_draw(struct pipe_context *ctx, const
struct pipe_draw_info *info)
r600_pipe_state_add_reg(vgt, R_028404_VGT_MIN_VTX_INDX,
draw.min_index, 0x, NULL);
r600_pipe_state_add_reg(vgt, R_03CFF0_SQ_VTX_BASE_VTX_LOC, 0,
0x, NULL);
r600_pipe_state_add_reg(vgt, R_03CFF4_SQ_VTX_START_INST_LOC, 0,
0x, NULL);
-
- if (rctx-rasterizer rctx-framebuffer.zsbuf) {
- float offset_units = rctx-rasterizer-offset_units;
- unsigned offset_db_fmt_cntl = 0, depth;
-
- switch (rctx-framebuffer.zsbuf-texture-format) {
- case PIPE_FORMAT_Z24X8_UNORM:
- case PIPE_FORMAT_Z24_UNORM_S8_USCALED:
- depth = -24;
- offset_units *= 2.0f;
- break;
- case PIPE_FORMAT_Z32_FLOAT:
- depth = -23;
- offset_units *= 1.0f
Mesa (master): r600g: indentation fix
Module: Mesa
Branch: master
Commit: 119f00659c03c48cfab0f2770dd6b6fb89af31e4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=119f00659c03c48cfab0f2770dd6b6fb89af31e4
Author: Jerome Glisse jgli...@redhat.com
Date: Fri Dec 3 12:56:51 2010 -0500
r600g: indentation fix
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_state.c |3 +-
src/gallium/drivers/r600/r600_blit.c | 12 +-
src/gallium/drivers/r600/r600_buffer.c |6 +-
src/gallium/drivers/r600/r600_pipe.c |6 +-
src/gallium/drivers/r600/r600_pipe.h | 19 ++--
src/gallium/drivers/r600/r600_shader.c |4 +-
src/gallium/drivers/r600/r600_texture.c| 156 ++--
7 files changed, 101 insertions(+), 105 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 9f44645..ebd541d 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -1206,8 +1206,7 @@ void evergreen_init_config(struct r600_pipe_context *rctx)
r600_pipe_state_add_reg(rstate, R_0283F8_SQ_VTX_SEMANTIC_30, 0x0,
0x, NULL);
r600_pipe_state_add_reg(rstate, R_0283FC_SQ_VTX_SEMANTIC_31, 0x0,
0x, NULL);
-r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL,
- 0x0, 0x, NULL);
+ r600_pipe_state_add_reg(rstate, R_028810_PA_CL_CLIP_CNTL, 0x0,
0x, NULL);
r600_context_pipe_state_set(rctx-ctx, rstate);
}
diff --git a/src/gallium/drivers/r600/r600_blit.c
b/src/gallium/drivers/r600/r600_blit.c
index f35eacd..0f04136 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++ b/src/gallium/drivers/r600/r600_blit.c
@@ -159,12 +159,12 @@ static void r600_clear_depth_stencil(struct pipe_context
*ctx,
/* Copy a block of pixels from one surface to another using HW. */
static void r600_hw_copy_region(struct pipe_context *ctx,
-struct pipe_resource *dst,
-unsigned dst_level,
-unsigned dstx, unsigned dsty, unsigned dstz,
-struct pipe_resource *src,
-unsigned src_level,
-const struct pipe_box *src_box)
+ struct pipe_resource *dst,
+ unsigned dst_level,
+ unsigned dstx, unsigned dsty, unsigned dstz,
+ struct pipe_resource *src,
+ unsigned src_level,
+ const struct pipe_box *src_box)
{
struct r600_pipe_context *rctx = (struct r600_pipe_context *)ctx;
diff --git a/src/gallium/drivers/r600/r600_buffer.c
b/src/gallium/drivers/r600/r600_buffer.c
index 76f9d88..51b8aba 100644
--- a/src/gallium/drivers/r600/r600_buffer.c
+++ b/src/gallium/drivers/r600/r600_buffer.c
@@ -130,9 +130,9 @@ static void *r600_buffer_transfer_map(struct pipe_context
*pipe,
r600_bo_reference((struct radeon*)pipe-winsys,
rbuffer-r.bo, NULL);
rbuffer-num_ranges = 0;
rbuffer-r.bo = r600_bo((struct
radeon*)pipe-winsys,
-
rbuffer-r.base.b.width0, 0,
-rbuffer-r.base.b.bind,
-
rbuffer-r.base.b.usage);
+
rbuffer-r.base.b.width0, 0,
+ rbuffer-r.base.b.bind,
+
rbuffer-r.base.b.usage);
break;
}
}
diff --git a/src/gallium/drivers/r600/r600_pipe.c
b/src/gallium/drivers/r600/r600_pipe.c
index 4592cbc..fa0b635 100644
--- a/src/gallium/drivers/r600/r600_pipe.c
+++ b/src/gallium/drivers/r600/r600_pipe.c
@@ -420,9 +420,9 @@ static boolean r600_is_format_supported(struct pipe_screen*
screen,
}
if ((usage (PIPE_BIND_RENDER_TARGET |
- PIPE_BIND_DISPLAY_TARGET |
- PIPE_BIND_SCANOUT |
- PIPE_BIND_SHARED))
+ PIPE_BIND_DISPLAY_TARGET |
+ PIPE_BIND_SCANOUT |
+ PIPE_BIND_SHARED))
r600_is_colorbuffer_format_supported(format)) {
retval |= usage
(PIPE_BIND_RENDER_TARGET |
diff --git a/src/gallium/drivers/r600/r600_pipe.h
b/src/gallium/drivers/r600/r600_pipe.h
index e4d5dd4..deec946 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -103,19 +103,20 @@ struct r600_pipe_shader {
struct r600_textures_info {
struct
Mesa (master): r600g: more indentation fix + warning silencing + dead code removal
Module: Mesa
Branch: master
Commit: edda44e0dc72302afa04a767772d5d97ab9d9aa6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=edda44e0dc72302afa04a767772d5d97ab9d9aa6
Author: Jerome Glisse jgli...@redhat.com
Date: Fri Dec 3 13:06:53 2010 -0500
r600g: more indentation fix + warning silencing + dead code removal
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/r600.h|2 +
src/gallium/drivers/r600/r600_texture.c|2 -
src/gallium/winsys/r600/drm/r600_drm.c | 17 ---
src/gallium/winsys/r600/drm/r600_priv.h|5 +--
src/gallium/winsys/r600/drm/radeon_pciid.c | 79 +---
5 files changed, 14 insertions(+), 91 deletions(-)
diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h
index 2ab60f3..aa456d4 100644
--- a/src/gallium/drivers/r600/r600.h
+++ b/src/gallium/drivers/r600/r600.h
@@ -294,4 +294,6 @@ void evergreen_context_pipe_state_set_fs_resource(struct
r600_context *ctx, stru
void evergreen_context_pipe_state_set_ps_sampler(struct r600_context *ctx,
struct r600_pipe_state *state, unsigned id);
void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx,
struct r600_pipe_state *state, unsigned id);
+struct radeon *radeon_decref(struct radeon *radeon);
+
#endif
diff --git a/src/gallium/drivers/r600/r600_texture.c
b/src/gallium/drivers/r600/r600_texture.c
index 1a2fd4e..d4d9b07 100644
--- a/src/gallium/drivers/r600/r600_texture.c
+++ b/src/gallium/drivers/r600/r600_texture.c
@@ -170,8 +170,6 @@ static unsigned r600_texture_get_stride(struct pipe_screen
*screen,
unsigned level)
{
struct pipe_resource *ptex = rtex-resource.base.b;
- struct radeon *radeon = (struct radeon *)screen-winsys;
- enum chip_class chipc = r600_get_family_class(radeon);
unsigned width, stride, tile_width;
if (rtex-pitch_override)
diff --git a/src/gallium/winsys/r600/drm/r600_drm.c
b/src/gallium/winsys/r600/drm/r600_drm.c
index e83cc44..8c84712 100644
--- a/src/gallium/winsys/r600/drm/r600_drm.c
+++ b/src/gallium/winsys/r600/drm/r600_drm.c
@@ -40,6 +40,9 @@
#ifndef RADEON_INFO_TILING_CONFIG
#define RADEON_INFO_TILING_CONFIG 0x6
#endif
+
+static struct radeon *radeon_new(int fd, unsigned device);
+
static int radeon_get_device(struct radeon *radeon)
{
struct drm_radeon_info info;
@@ -108,7 +111,7 @@ static int radeon_drm_get_tiling(struct radeon *radeon)
return 0;
}
-struct radeon *radeon_new(int fd, unsigned device)
+static struct radeon *radeon_new(int fd, unsigned device)
{
struct radeon *radeon;
int r;
@@ -249,14 +252,14 @@ struct radeon *radeon_decref(struct radeon *radeon)
return NULL;
}
-if (radeon-cman)
- radeon-cman-destroy(radeon-cman);
+ if (radeon-cman)
+ radeon-cman-destroy(radeon-cman);
-if (radeon-kman)
- radeon-kman-destroy(radeon-kman);
+ if (radeon-kman)
+ radeon-kman-destroy(radeon-kman);
-if (radeon-fd = 0)
- drmClose(radeon-fd);
+ if (radeon-fd = 0)
+ drmClose(radeon-fd);
free(radeon);
return NULL;
diff --git a/src/gallium/winsys/r600/drm/r600_priv.h
b/src/gallium/winsys/r600/drm/r600_priv.h
index 9fd77b7..193af98 100644
--- a/src/gallium/winsys/r600/drm/r600_priv.h
+++ b/src/gallium/winsys/r600/drm/r600_priv.h
@@ -78,7 +78,7 @@ struct r600_bo {
struct pb_buffer*pb;
unsignedsize;
unsignedtiling_flags;
- unsignedkernel_pitch;
+ unsignedkernel_pitch;
unsigneddomains;
};
@@ -86,9 +86,6 @@ struct r600_bo {
/* radeon_pciid.c */
unsigned radeon_family_from_device(unsigned device);
-/* r600_drm.c */
-struct radeon *radeon_decref(struct radeon *radeon);
-
/* radeon_bo.c */
struct radeon_bo *radeon_bo(struct radeon *radeon, unsigned handle,
unsigned size, unsigned alignment);
diff --git a/src/gallium/winsys/r600/drm/radeon_pciid.c
b/src/gallium/winsys/r600/drm/radeon_pciid.c
index 18bddc1..92560a4 100644
--- a/src/gallium/winsys/r600/drm/radeon_pciid.c
+++ b/src/gallium/winsys/r600/drm/radeon_pciid.c
@@ -24,7 +24,7 @@
* Jerome Glisse
*/
#include stdlib.h
-#include r600.h
+#include r600_priv.h
struct pci_id {
unsignedvendor;
@@ -460,80 +460,3 @@ unsigned radeon_family_from_device(unsigned device)
}
return CHIP_UNKNOWN;
}
-
-int radeon_is_family_compatible(unsigned family1, unsigned family2)
-{
- switch (family1) {
- case CHIP_R600:
- case CHIP_RV610:
- case CHIP_RV630:
- case CHIP_RV670:
- case CHIP_RV620:
- case CHIP_RV635:
- case CHIP_RS780:
- case CHIP_RS880:
- case CHIP_RV770
Mesa (master): r600g: fix occlusion query on evergreen (avoid lockup)
Module: Mesa
Branch: master
Commit: fab804bdfeb0b8080b7ee52d4d79f0ef0e548d1f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fab804bdfeb0b8080b7ee52d4d79f0ef0e548d1f
Author: Jerome Glisse jgli...@redhat.com
Date: Fri Nov 19 11:51:37 2010 -0500
r600g: fix occlusion query on evergreen (avoid lockup)
Occlusion query on evergreen need the event index field to be
set otherwise we endup locking up the GPU.
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/winsys/r600/drm/r600_hw_context.c | 12 ++--
src/gallium/winsys/r600/drm/r600d.h |1 +
2 files changed, 11 insertions(+), 2 deletions(-)
diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c
b/src/gallium/winsys/r600/drm/r600_hw_context.c
index b2a1125..b70dffa 100644
--- a/src/gallium/winsys/r600/drm/r600_hw_context.c
+++ b/src/gallium/winsys/r600/drm/r600_hw_context.c
@@ -1279,7 +1279,11 @@ void r600_query_begin(struct r600_context *ctx, struct
r600_query *query)
/* emit begin query */
ctx-pm4[ctx-pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2);
- ctx-pm4[ctx-pm4_cdwords++] = EVENT_TYPE_ZPASS_DONE;
+ if (ctx-radeon-chip_class == EVERGREEN) {
+ ctx-pm4[ctx-pm4_cdwords++] = EVENT_TYPE_ZPASS_DONE |
EG_EVENT_INDEX(1);
+ } else {
+ ctx-pm4[ctx-pm4_cdwords++] = EVENT_TYPE_ZPASS_DONE;
+ }
ctx-pm4[ctx-pm4_cdwords++] = query-num_results +
r600_bo_offset(query-buffer);
ctx-pm4[ctx-pm4_cdwords++] = 0;
ctx-pm4[ctx-pm4_cdwords++] = PKT3(PKT3_NOP, 0);
@@ -1295,7 +1299,11 @@ void r600_query_end(struct r600_context *ctx, struct
r600_query *query)
{
/* emit begin query */
ctx-pm4[ctx-pm4_cdwords++] = PKT3(PKT3_EVENT_WRITE, 2);
- ctx-pm4[ctx-pm4_cdwords++] = EVENT_TYPE_ZPASS_DONE;
+ if (ctx-radeon-chip_class == EVERGREEN) {
+ ctx-pm4[ctx-pm4_cdwords++] = EVENT_TYPE_ZPASS_DONE |
EG_EVENT_INDEX(1);
+ } else {
+ ctx-pm4[ctx-pm4_cdwords++] = EVENT_TYPE_ZPASS_DONE;
+ }
ctx-pm4[ctx-pm4_cdwords++] = query-num_results + 8 +
r600_bo_offset(query-buffer);
ctx-pm4[ctx-pm4_cdwords++] = 0;
ctx-pm4[ctx-pm4_cdwords++] = PKT3(PKT3_NOP, 0);
diff --git a/src/gallium/winsys/r600/drm/r600d.h
b/src/gallium/winsys/r600/drm/r600d.h
index 5ca7456..3c39b3f 100644
--- a/src/gallium/winsys/r600/drm/r600d.h
+++ b/src/gallium/winsys/r600/drm/r600d.h
@@ -94,6 +94,7 @@
#define EVENT_TYPE_CACHE_FLUSH_AND_INV_TS_EVENT 0x14
#define EVENT_TYPE_ZPASS_DONE 0x15
#define EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT 0x16
+#define EG_EVENT_INDEX(x) ((x) 8)
#define PKT_TYPE_S(x) (((x) 0x3) 30)
#define PKT_TYPE_G(x) (((x) 30) 0x3)
___
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Mesa (master): r600g: add fetch shader capabilities
Module: Mesa Branch: master Commit: f609b2ab0342d77a8beca9efb5fbc5b66ff98295 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f609b2ab0342d77a8beca9efb5fbc5b66ff98295 Author: Jerome Glisse jgli...@redhat.com Date: Thu Nov 18 14:29:16 2010 -0500 r600g: add fetch shader capabilities Use fetch shader instead of having fetch instruction in the vertex shader. Allow to restrict shader update to a smaller part when vertex buffer input layout changes. Signed-off-by: Jerome Glisse jgli...@redhat.com --- src/gallium/drivers/r600/eg_asm.c |2 + src/gallium/drivers/r600/evergreen_state.c |4 +- src/gallium/drivers/r600/r600.h|3 + src/gallium/drivers/r600/r600_asm.c| 42 +++-- src/gallium/drivers/r600/r600_asm.h|1 + src/gallium/drivers/r600/r600_pipe.h |1 + src/gallium/drivers/r600/r600_shader.c | 48 +-- src/gallium/drivers/r600/r600_shader.h |1 + src/gallium/drivers/r600/r600_state.c |2 +- src/gallium/winsys/r600/drm/evergreen_hw_context.c | 20 src/gallium/winsys/r600/drm/r600_hw_context.c | 13 + 11 files changed, 125 insertions(+), 12 deletions(-) diff --git a/src/gallium/drivers/r600/eg_asm.c b/src/gallium/drivers/r600/eg_asm.c index c30f09c..21d66fa 100644 --- a/src/gallium/drivers/r600/eg_asm.c +++ b/src/gallium/drivers/r600/eg_asm.c @@ -74,6 +74,8 @@ int eg_bc_cf_build(struct r600_bc *bc, struct r600_bc_cf *cf) case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_END: case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_CONTINUE: case EG_V_SQ_CF_WORD1_SQ_CF_INST_LOOP_BREAK: + case EG_V_SQ_CF_WORD1_SQ_CF_INST_CALL_FS: + case EG_V_SQ_CF_WORD1_SQ_CF_INST_RETURN: bc-bytecode[id++] = S_SQ_CF_WORD0_ADDR(cf-cf_addr 1); bc-bytecode[id++] = S_SQ_CF_WORD1_CF_INST(cf-inst) | S_SQ_CF_WORD1_BARRIER(1) | diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 7609025..669eef4 100644 --- a/src/gallium/drivers/r600/evergreen_state.c +++ b/src/gallium/drivers/r600/evergreen_state.c @@ -1289,7 +1289,7 @@ void evergreen_draw(struct pipe_context *ctx, const struct pipe_draw_info *info) r600_pipe_state_add_reg(rstate, R_030014_RESOURCE0_WORD5, 0x, 0x, NULL); r600_pipe_state_add_reg(rstate, R_030018_RESOURCE0_WORD6, 0x, 0x, NULL); r600_pipe_state_add_reg(rstate, R_03001C_RESOURCE0_WORD7, 0xC000, 0x, NULL); - evergreen_vs_resource_set(rctx-ctx, rstate, i); + evergreen_fs_resource_set(rctx-ctx, rstate, i); } mask = 0; @@ -1554,7 +1554,7 @@ void evergreen_pipe_shader_vs(struct pipe_context *ctx, struct r600_pipe_shader (r600_bo_offset(shader-bo)) 8, 0x, shader-bo); r600_pipe_state_add_reg(rstate, R_0288A4_SQ_PGM_START_FS, - (r600_bo_offset(shader-bo)) 8, 0x, shader-bo); + (r600_bo_offset(shader-bo)) 8, 0x, shader-bo_fetch); r600_pipe_state_add_reg(rstate, R_03A200_SQ_LOOP_CONST_0 + (32 * 4), 0x01000FFF, diff --git a/src/gallium/drivers/r600/r600.h b/src/gallium/drivers/r600/r600.h index 17858b2..a617a5b 100644 --- a/src/gallium/drivers/r600/r600.h +++ b/src/gallium/drivers/r600/r600.h @@ -264,6 +264,7 @@ void r600_context_fini(struct r600_context *ctx); void r600_context_pipe_state_set(struct r600_context *ctx, struct r600_pipe_state *state); void r600_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid); void r600_context_pipe_state_set_vs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid); +void r600_context_pipe_state_set_fs_resource(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid); void r600_context_pipe_state_set_ps_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); void r600_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struct r600_pipe_state *state, unsigned id); void r600_context_flush(struct r600_context *ctx); @@ -284,9 +285,11 @@ int evergreen_context_init(struct r600_context *ctx, struct radeon *radeon); void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw); void evergreen_ps_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid); void evergreen_vs_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid); +void evergreen_fs_resource_set(struct r600_context *ctx, struct r600_pipe_state *state, unsigned rid); void evergreen_context_pipe_state_set_ps_resource(struct r600_context *ctx, struct
Mesa (master): r600g: code cleanup (indent, trailing space, empty line ...)
Module: Mesa
Branch: master
Commit: 7ffd4e976fd11b8c083c2927effd25a2f79ac841
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ffd4e976fd11b8c083c2927effd25a2f79ac841
Author: Jerome Glisse jgli...@redhat.com
Date: Wed Nov 17 17:20:59 2010 -0500
r600g: code cleanup (indent, trailing space, empty line ...)
Signed-off-by: Jerome Glisse jgli...@redhat.com
---
src/gallium/drivers/r600/evergreen_state.c |6 +-
src/gallium/drivers/r600/r600_asm.c | 16 +++---
src/gallium/drivers/r600/r600_asm.h | 14 +++---
src/gallium/drivers/r600/r600_blit.c |7 +--
src/gallium/drivers/r600/r600_buffer.c |4 +-
src/gallium/drivers/r600/r600_pipe.c |4 +-
src/gallium/drivers/r600/r600_shader.c | 73 +-
src/gallium/drivers/r600/r600_state.c|8 ++--
src/gallium/drivers/r600/r600_state_common.c | 11 ++--
9 files changed, 70 insertions(+), 73 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_state.c
b/src/gallium/drivers/r600/evergreen_state.c
index 1535b9a..7609025 100644
--- a/src/gallium/drivers/r600/evergreen_state.c
+++ b/src/gallium/drivers/r600/evergreen_state.c
@@ -660,7 +660,7 @@ static void evergreen_cb(struct r600_pipe_context *rctx,
struct r600_pipe_state
S_028C70_COMP_SWAP(swap) |
S_028C70_BLEND_CLAMP(1) |
S_028C70_NUMBER_TYPE(ntype);
- if (desc-colorspace != UTIL_FORMAT_COLORSPACE_ZS)
+ if (desc-colorspace != UTIL_FORMAT_COLORSPACE_ZS)
color_info |= S_028C70_SOURCE_FORMAT(1);
/* FIXME handle enabling of CB beyond BASE8 which has different offset
*/
@@ -1467,8 +1467,8 @@ void evergreen_pipe_shader_ps(struct pipe_context *ctx,
struct r600_pipe_shader
S_0286E0_PERSP_CENTROID_ENA(have_centroid);
if (have_linear)
spi_baryc_cntl |= S_0286E0_LINEAR_CENTER_ENA(1) |
- S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
-
+ S_0286E0_LINEAR_CENTROID_ENA(have_centroid);
+
r600_pipe_state_add_reg(rstate, R_0286CC_SPI_PS_IN_CONTROL_0,
spi_ps_in_control_0, 0x, NULL);
r600_pipe_state_add_reg(rstate, R_0286D0_SPI_PS_IN_CONTROL_1,
diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index 8a7f3ce..eed40d2 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -55,8 +55,8 @@ static inline unsigned int r600_bc_get_num_operands(struct
r600_bc_alu *alu)
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_DOT4_IEEE:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_CUBE:
- return 2;
-
+ return 2;
+
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOV:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_MOVA_FLOOR:
case V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_FRACT:
@@ -74,7 +74,7 @@ static inline unsigned int r600_bc_get_num_operands(struct
r600_bc_alu *alu)
default: R600_ERR(
Need instruction operand number for 0x%x.\n, alu-inst);
};
-
+
return 3;
}
@@ -199,9 +199,9 @@ const unsigned bank_swizzle_vec[8] = {SQ_ALU_VEC_210, //000
SQ_ALU_VEC_012}; //111
const unsigned bank_swizzle_scl[8] = {SQ_ALU_SCL_210, //000
- SQ_ALU_SCL_122, //001
+ SQ_ALU_SCL_122, //001
SQ_ALU_SCL_122, //010
-
+
SQ_ALU_SCL_221, //011
SQ_ALU_SCL_212, //100
SQ_ALU_SCL_122, //101
@@ -678,8 +678,8 @@ static int r600_bc_alu_build(struct r600_bc *bc, struct
r600_bc_alu *alu, unsign
S_SQ_ALU_WORD1_OP2_WRITE_MASK(alu-dst.write) |
S_SQ_ALU_WORD1_OP2_ALU_INST(alu-inst) |
S_SQ_ALU_WORD1_BANK_SWIZZLE(alu-bank_swizzle) |
-
S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu-predicate) |
-
S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu-predicate);
+
S_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(alu-predicate) |
+
S_SQ_ALU_WORD1_OP2_UPDATE_PRED(alu-predicate);
}
if (alu-last) {
if (alu-nliteral !alu-literal_added) {
@@ -766,7 +766,7 @@ int r600_bc_build(struct r600_bc *bc)
int r;
if (bc-callstack[0].max 0)
- bc-nstack = ((bc-callstack[0].max + 3) 2) + 2;
+ bc-nstack = ((bc-callstack[0].max + 3) 2) + 2;
/* first path compute addr
