Mesa (master): amd/common: use the dimension-aware image intrinsics on LLVM 7+
Module: Mesa
Branch: master
Commit: a9a79934412abedfb8eaf74aac2dbf52604509e0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a9a79934412abedfb8eaf74aac2dbf52604509e0
Author: Nicolai Hähnle
Date: Fri Feb 16 18:44:25 2018 +0100
amd/common: use the dimension-aware image intrinsics on LLVM 7+
Requires LLVM trunk r329166.
Acked-by: Marek Olšák
---
src/amd/common/ac_llvm_build.c | 189 +++--
1 file changed, 165 insertions(+), 24 deletions(-)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 4eebbbd4d9..a686b72287 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -1473,8 +1473,26 @@ static unsigned ac_num_derivs(enum ac_image_dim dim)
}
}
-LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
- struct ac_image_args *a)
+static const char *get_atomic_name(enum ac_atomic_op op)
+{
+ switch (op) {
+ case ac_atomic_swap: return "swap";
+ case ac_atomic_add: return "add";
+ case ac_atomic_sub: return "sub";
+ case ac_atomic_smin: return "smin";
+ case ac_atomic_umin: return "umin";
+ case ac_atomic_smax: return "smax";
+ case ac_atomic_umax: return "umax";
+ case ac_atomic_and: return "and";
+ case ac_atomic_or: return "or";
+ case ac_atomic_xor: return "xor";
+ }
+ unreachable("bad atomic op");
+}
+
+/* LLVM 6 and older */
+static LLVMValueRef ac_build_image_opcode_llvm6(struct ac_llvm_context *ctx,
+ struct ac_image_args *a)
{
LLVMValueRef args[16];
LLVMTypeRef retty = ctx->v4f32;
@@ -1482,16 +1500,6 @@ LLVMValueRef ac_build_image_opcode(struct
ac_llvm_context *ctx,
const char *atomic_subop = "";
char intr_name[128], coords_type[64];
- assert(!a->lod || a->lod == ctx->i32_0 || a->lod == ctx->f32_0 ||
- !a->level_zero);
- assert((a->opcode != ac_image_get_resinfo && a->opcode !=
ac_image_load_mip &&
- a->opcode != ac_image_store_mip) ||
- a->lod);
- assert((a->bias ? 1 : 0) +
- (a->lod ? 1 : 0) +
- (a->level_zero ? 1 : 0) +
- (a->derivs[0] ? 1 : 0) <= 1);
-
bool sample = a->opcode == ac_image_sample ||
a->opcode == ac_image_gather4 ||
a->opcode == ac_image_get_lod;
@@ -1603,18 +1611,7 @@ LLVMValueRef ac_build_image_opcode(struct
ac_llvm_context *ctx,
if (a->opcode == ac_image_atomic_cmpswap) {
atomic_subop = "cmpswap";
} else {
- switch (a->atomic) {
- case ac_atomic_swap: atomic_subop = "swap"; break;
- case ac_atomic_add: atomic_subop = "add"; break;
- case ac_atomic_sub: atomic_subop = "sub"; break;
- case ac_atomic_smin: atomic_subop = "smin"; break;
- case ac_atomic_umin: atomic_subop = "umin"; break;
- case ac_atomic_smax: atomic_subop = "smax"; break;
- case ac_atomic_umax: atomic_subop = "umax"; break;
- case ac_atomic_and: atomic_subop = "and"; break;
- case ac_atomic_or: atomic_subop = "or"; break;
- case ac_atomic_xor: atomic_subop = "xor"; break;
- }
+ atomic_subop = get_atomic_name(a->atomic);
}
break;
case ac_image_get_lod:
@@ -1658,6 +1655,150 @@ LLVMValueRef ac_build_image_opcode(struct
ac_llvm_context *ctx,
return result;
}
+LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
+ struct ac_image_args *a)
+{
+ const char *overload[3] = { "", "", "" };
+ unsigned num_overloads = 0;
+ LLVMValueRef args[18];
+ unsigned num_args = 0;
+
+ assert(!a->lod || a->lod == ctx->i32_0 || a->lod == ctx->f32_0 ||
+ !a->level_zero);
+ assert((a->opcode != ac_image_get_resinfo && a->opcode !=
ac_image_load_mip &&
+ a->opcode != ac_image_store_mip) ||
+ a->lod);
+ assert(a->opcode == ac_image_sample || a->opcode == ac_image_gather4 ||
+ (!a->compare && !a->offset));
+ assert((a->opcode == ac_image_sample || a->opcode == ac_image_gather4 ||
+ a->opcode == ac_image_get_lod) ||
Mesa (master): amd/common: use llvm.amdgcn.wqm for explicit derivatives
Module: Mesa
Branch: master
Commit: c0acb596f45624e2bc9ba7285e20bc744a532dbe
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0acb596f45624e2bc9ba7285e20bc744a532dbe
Author: Nicolai Hähnle
Date: Tue May 1 11:06:18 2018 +0200
amd/common: use llvm.amdgcn.wqm for explicit derivatives
To comply with an upcoming change in LLVM, see
https://reviews.llvm.org/D46051
Reviewed-by: Bas Nieuwenhuizen
---
src/amd/common/ac_llvm_build.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index f21a5d2623..c9b2e36b63 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -1248,6 +1248,13 @@ ac_build_ddxy(struct ac_llvm_context *ctx,
tl = LLVMBuildBitCast(ctx->builder, tl, ctx->f32, "");
trbl = LLVMBuildBitCast(ctx->builder, trbl, ctx->f32, "");
result = LLVMBuildFSub(ctx->builder, trbl, tl, "");
+
+ if (HAVE_LLVM >= 0x0700) {
+ result = ac_build_intrinsic(ctx,
+ "llvm.amdgcn.wqm.f32", ctx->f32,
+ &result, 1, 0);
+ }
+
return result;
}
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Mesa (master): glsl: prevent spurious Valgrind errors when serializing NIR
Module: Mesa
Branch: master
Commit: 68ee1d57962c81172841459f5eaeefbe5506425e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=68ee1d57962c81172841459f5eaeefbe5506425e
Author: Nicolai Hähnle
Date: Fri Mar 23 15:43:58 2018 +0100
glsl: prevent spurious Valgrind errors when serializing NIR
It looks as if the structure fields array is fully initialized below,
but in fact at least gcc in debug builds will not actually overwrite
the unused bits of bit fields.
Reviewed-by: Timothy Arceri
---
src/compiler/glsl_types.cpp | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/compiler/glsl_types.cpp b/src/compiler/glsl_types.cpp
index 11947c917a..d11c365e19 100644
--- a/src/compiler/glsl_types.cpp
+++ b/src/compiler/glsl_types.cpp
@@ -105,8 +105,10 @@ glsl_type::glsl_type(const glsl_struct_field *fields,
unsigned num_fields,
assert(name != NULL);
this->name = ralloc_strdup(this->mem_ctx, name);
- this->fields.structure = ralloc_array(this->mem_ctx,
- glsl_struct_field, length);
+ /* Zero-fill to prevent spurious Valgrind errors when serializing NIR
+* due to uninitialized unused bits in bit fields. */
+ this->fields.structure = rzalloc_array(this->mem_ctx,
+ glsl_struct_field, length);
for (i = 0; i < length; i++) {
this->fields.structure[i] = fields[i];
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Mesa (master): amd/common: pass new enum ac_image_dim to ac_build_image_opcode
Module: Mesa
Branch: master
Commit: f931583828f0ca9a3b135da0f2cda6a36ebbc877
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f931583828f0ca9a3b135da0f2cda6a36ebbc877
Author: Nicolai Hähnle
Date: Fri Feb 16 14:21:56 2018 +0100
amd/common: pass new enum ac_image_dim to ac_build_image_opcode
This is in preparation for the new, dimension-aware LLVM image
intrinsics.
Acked-by: Marek Olšák
---
src/amd/common/ac_llvm_build.c| 10 -
src/amd/common/ac_llvm_build.h| 13 +-
src/amd/common/ac_nir_to_llvm.c | 54 +++
src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c | 50 -
4 files changed, 114 insertions(+), 13 deletions(-)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 9a00bb1114..77b0798943 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -1456,6 +1456,12 @@ LLVMValueRef ac_build_image_opcode(struct
ac_llvm_context *ctx,
bool sample = a->opcode == ac_image_sample ||
a->opcode == ac_image_gather4 ||
a->opcode == ac_image_get_lod;
+ bool da = a->dim == ac_image_cube ||
+ a->dim == ac_image_1darray ||
+ a->dim == ac_image_2darray ||
+ a->dim == ac_image_2darraymsaa;
+ if (a->opcode == ac_image_get_lod)
+ da = false;
if (sample)
args[num_args++] = ac_to_float(ctx, a->addr);
@@ -1471,7 +1477,7 @@ LLVMValueRef ac_build_image_opcode(struct ac_llvm_context
*ctx,
args[num_args++] = ctx->i1false; /* glc */
args[num_args++] = ctx->i1false; /* slc */
args[num_args++] = ctx->i1false; /* lwe */
- args[num_args++] = LLVMConstInt(ctx->i1, a->da, 0);
+ args[num_args++] = LLVMConstInt(ctx->i1, da, 0);
switch (a->opcode) {
case ac_image_sample:
@@ -2473,7 +2479,7 @@ void ac_apply_fmask_to_sample(struct ac_llvm_context *ac,
LLVMValueRef fmask,
fmask_load.opcode = ac_image_load;
fmask_load.resource = fmask;
fmask_load.dmask = 0xf;
- fmask_load.da = is_array_tex;
+ fmask_load.dim = is_array_tex ? ac_image_2darray : ac_image_2d;
LLVMValueRef fmask_addr[4];
memcpy(fmask_addr, addr, sizeof(fmask_addr[0]) * 3);
diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index c583240e14..328eddc9a7 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -317,8 +317,20 @@ enum ac_image_opcode {
ac_image_get_resinfo,
};
+enum ac_image_dim {
+ ac_image_1d,
+ ac_image_2d,
+ ac_image_3d,
+ ac_image_cube, // includes cube arrays
+ ac_image_1darray,
+ ac_image_2darray,
+ ac_image_2dmsaa,
+ ac_image_2darraymsaa,
+};
+
struct ac_image_args {
enum ac_image_opcode opcode;
+ enum ac_image_dim dim;
bool level_zero;
bool bias;
bool lod;
@@ -331,7 +343,6 @@ struct ac_image_args {
LLVMValueRef addr;
unsigned dmask;
bool unorm;
- bool da;
};
LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 6b519f78e0..de3754d72b 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -76,6 +76,45 @@ build_store_values_extended(struct ac_llvm_context *ac,
}
}
+static enum ac_image_dim
+get_ac_sampler_dim(const struct ac_llvm_context *ctx, enum glsl_sampler_dim
dim,
+ bool is_array)
+{
+ switch (dim) {
+ case GLSL_SAMPLER_DIM_1D:
+ if (ctx->chip_class >= GFX9)
+ return is_array ? ac_image_2darray : ac_image_2d;
+ return is_array ? ac_image_1darray : ac_image_1d;
+ case GLSL_SAMPLER_DIM_2D:
+ case GLSL_SAMPLER_DIM_RECT:
+ case GLSL_SAMPLER_DIM_SUBPASS:
+ case GLSL_SAMPLER_DIM_EXTERNAL:
+ return is_array ? ac_image_2darray : ac_image_2d;
+ case GLSL_SAMPLER_DIM_3D:
+ return ac_image_3d;
+ case GLSL_SAMPLER_DIM_CUBE:
+ return ac_image_cube;
+ case GLSL_SAMPLER_DIM_MS:
+ case GLSL_SAMPLER_DIM_SUBPASS_MS:
+ return is_array ? ac_image_2darraymsaa : ac_image_2dmsaa;
+ default:
+ unreachable("bad sampler dim");
+ }
+}
+
+static enum ac_image_dim
+get_ac_image_dim(const struct ac_llvm_context *ctx, enum glsl_sampler_dim sdim,
+bool is_array)
+{
+ enum ac_image_dim dim = get_ac_sampler_dim(ctx, sdim, is_array);
+
+ if (dim == ac_image_cube ||
+ (ctx->chip_class <= VI && dim == ac_image_3d))
+ dim = ac_image_2darray;
+
+ return dim;
+}
+
static LLVMTypeRef get_def_type(struc
Mesa (master): radeonsi/nir: fix crash in test involving the sample mask
Module: Mesa
Branch: master
Commit: 9cb52d470a0db8b733bb344168308a6e7766626d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9cb52d470a0db8b733bb344168308a6e7766626d
Author: Nicolai Hähnle
Date: Wed Apr 4 21:14:13 2018 +0200
radeonsi/nir: fix crash in test involving the sample mask
Reviewed-by: Timothy Arceri
---
src/gallium/drivers/radeonsi/si_shader.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index b4970f14e3..4eff4f57b9 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2016,7 +2016,8 @@ static LLVMValueRef load_sample_position(struct
ac_shader_abi *abi, LLVMValueRef
static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
{
- return abi->sample_coverage;
+ struct si_shader_context *ctx = si_shader_context_from_abi(abi);
+ return ac_to_integer(&ctx->ac, abi->sample_coverage);
}
static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi)
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Mesa (master): radeonsi: generate image load/store/atomic ops using ac_build_image_opcode
Module: Mesa
Branch: master
Commit: 74063431f125df450029ec9202d376b4a77f30c6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=74063431f125df450029ec9202d376b4a77f30c6
Author: Nicolai Hähnle
Date: Fri Apr 20 09:29:57 2018 +0200
radeonsi: generate image load/store/atomic ops using ac_build_image_opcode
In preparation of dimension-aware LLVM image intrinsics.
Acked-by: Marek Olšák
---
src/amd/common/ac_llvm_build.c | 105 +++---
src/amd/common/ac_llvm_build.h | 37 +++-
src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.h | 2 +-
src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c | 230 +
4 files changed, 210 insertions(+), 164 deletions(-)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 22aac7cbdb..64b47e7343 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -1489,12 +1489,15 @@ LLVMValueRef ac_build_image_opcode(struct
ac_llvm_context *ctx,
struct ac_image_args *a)
{
LLVMValueRef args[16];
+ LLVMTypeRef retty = ctx->v4f32;
const char *name = NULL;
- char intr_name[128], type[64];
+ const char *atomic_subop = "";
+ char intr_name[128], coords_type[64];
assert(!a->lod || a->lod == ctx->i32_0 || a->lod == ctx->f32_0 ||
!a->level_zero);
- assert((a->opcode != ac_image_get_resinfo && a->opcode !=
ac_image_load_mip) ||
+ assert((a->opcode != ac_image_get_resinfo && a->opcode !=
ac_image_load_mip &&
+ a->opcode != ac_image_store_mip) ||
a->lod);
assert((a->bias ? 1 : 0) +
(a->lod ? 1 : 0) +
@@ -1504,6 +1507,8 @@ LLVMValueRef ac_build_image_opcode(struct ac_llvm_context
*ctx,
bool sample = a->opcode == ac_image_sample ||
a->opcode == ac_image_gather4 ||
a->opcode == ac_image_get_lod;
+ bool atomic = a->opcode == ac_image_atomic ||
+ a->opcode == ac_image_atomic_cmpswap;
bool da = a->dim == ac_image_cube ||
a->dim == ac_image_1darray ||
a->dim == ac_image_2darray ||
@@ -1539,6 +1544,13 @@ LLVMValueRef ac_build_image_opcode(struct
ac_llvm_context *ctx,
addr = ac_build_gather_values(ctx, args, num_addr);
unsigned num_args = 0;
+ if (atomic || a->opcode == ac_image_store || a->opcode ==
ac_image_store_mip) {
+ args[num_args++] = a->data[0];
+ if (a->opcode == ac_image_atomic_cmpswap)
+ args[num_args++] = a->data[1];
+ }
+
+ unsigned coords_arg = num_args;
if (sample)
args[num_args++] = ac_to_float(ctx, addr);
else
@@ -1547,13 +1559,19 @@ LLVMValueRef ac_build_image_opcode(struct
ac_llvm_context *ctx,
args[num_args++] = a->resource;
if (sample)
args[num_args++] = a->sampler;
- args[num_args++] = LLVMConstInt(ctx->i32, a->dmask, 0);
- if (sample)
- args[num_args++] = LLVMConstInt(ctx->i1, a->unorm, 0);
- args[num_args++] = ctx->i1false; /* glc */
- args[num_args++] = ctx->i1false; /* slc */
- args[num_args++] = ctx->i1false; /* lwe */
- args[num_args++] = LLVMConstInt(ctx->i1, da, 0);
+ if (!atomic) {
+ args[num_args++] = LLVMConstInt(ctx->i32, a->dmask, 0);
+ if (sample)
+ args[num_args++] = LLVMConstInt(ctx->i1, a->unorm, 0);
+ args[num_args++] = a->cache_policy & ac_glc ? ctx->i1true :
ctx->i1false;
+ args[num_args++] = a->cache_policy & ac_slc ? ctx->i1true :
ctx->i1false;
+ args[num_args++] = ctx->i1false; /* lwe */
+ args[num_args++] = LLVMConstInt(ctx->i1, da, 0);
+ } else {
+ args[num_args++] = ctx->i1false; /* r128 */
+ args[num_args++] = LLVMConstInt(ctx->i1, da, 0);
+ args[num_args++] = a->cache_policy & ac_slc ? ctx->i1true :
ctx->i1false;
+ }
switch (a->opcode) {
case ac_image_sample:
@@ -1568,6 +1586,35 @@ LLVMValueRef ac_build_image_opcode(struct
ac_llvm_context *ctx,
case ac_image_load_mip:
name = "llvm.amdgcn.image.load.mip";
break;
+ case ac_image_store:
+ name = "llvm.amdgcn.image.store";
+ retty = ctx->voidt;
+ break;
+ case ac_image_store_mip:
+ name = "llvm.amdgcn.image.store.mip";
+ retty = ctx->voidt;
+ break;
+ case ac_image_atomic:
+ case ac_image_atomic_cmpswap:
+
Mesa (master): radeonsi: fix error paths of si_texture_transfer_map
Module: Mesa
Branch: master
Commit: e788b987d866c12af25cee641209a3a5b2d2c107
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e788b987d866c12af25cee641209a3a5b2d2c107
Author: Nicolai Hähnle
Date: Tue Jan 16 14:38:00 2018 +0100
radeonsi: fix error paths of si_texture_transfer_map
trans is zero-initialized, but trans->resource is setup immediately so
needs to be dereferenced.
Reviewed-by: Timothy Arceri
---
src/gallium/drivers/radeonsi/si_texture.c | 25 -
1 file changed, 12 insertions(+), 13 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_texture.c
b/src/gallium/drivers/radeonsi/si_texture.c
index b41a0d1b92..0a2939bdd1 100644
--- a/src/gallium/drivers/radeonsi/si_texture.c
+++ b/src/gallium/drivers/radeonsi/si_texture.c
@@ -1740,16 +1740,14 @@ static void *si_texture_transfer_map(struct
pipe_context *ctx,
if (!si_init_flushed_depth_texture(ctx, &resource,
&staging_depth)) {
PRINT_ERR("failed to create temporary texture
to hold untiled copy\n");
- FREE(trans);
- return NULL;
+ goto fail_trans;
}
if (usage & PIPE_TRANSFER_READ) {
struct pipe_resource *temp =
ctx->screen->resource_create(ctx->screen, &resource);
if (!temp) {
PRINT_ERR("failed to create a temporary
depth texture\n");
- FREE(trans);
- return NULL;
+ goto fail_trans;
}
si_copy_region_with_blit(ctx, temp, 0, 0, 0, 0,
texture, level, box);
@@ -1767,8 +1765,7 @@ static void *si_texture_transfer_map(struct pipe_context
*ctx,
/* XXX: when discard is true, no need to read back from
depth texture */
if (!si_init_flushed_depth_texture(ctx, texture,
&staging_depth)) {
PRINT_ERR("failed to create temporary texture
to hold untiled copy\n");
- FREE(trans);
- return NULL;
+ goto fail_trans;
}
si_blit_decompress_depth(ctx, rtex, staging_depth,
@@ -1797,8 +1794,7 @@ static void *si_texture_transfer_map(struct pipe_context
*ctx,
staging = (struct
r600_texture*)ctx->screen->resource_create(ctx->screen, &resource);
if (!staging) {
PRINT_ERR("failed to create temporary texture to hold
untiled copy\n");
- FREE(trans);
- return NULL;
+ goto fail_trans;
}
trans->staging = &staging->resource;
@@ -1821,14 +1817,17 @@ static void *si_texture_transfer_map(struct
pipe_context *ctx,
buf = &rtex->resource;
}
- if (!(map = si_buffer_map_sync_with_rings(sctx, buf, usage))) {
- r600_resource_reference(&trans->staging, NULL);
- FREE(trans);
- return NULL;
- }
+ if (!(map = si_buffer_map_sync_with_rings(sctx, buf, usage)))
+ goto fail_trans;
*ptransfer = &trans->b.b;
return map + offset;
+
+fail_trans:
+ r600_resource_reference(&trans->staging, NULL);
+ pipe_resource_reference(&trans->b.b.resource, NULL);
+ FREE(trans);
+ return NULL;
}
static void si_texture_transfer_unmap(struct pipe_context *ctx,
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Mesa (master): ac/nir: fix atomic compare-and-swap
Module: Mesa
Branch: master
Commit: a807a9b215d1a6db7fc51478a6bf8fa873f51f58
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a807a9b215d1a6db7fc51478a6bf8fa873f51f58
Author: Nicolai Hähnle
Date: Mon Apr 2 14:12:50 2018 +0200
ac/nir: fix atomic compare-and-swap
The LLVM instruction returns { i32, i1 }, where the i1 indicates success.
We're only interested in the first part, which is the loaded value.
Fixes dEQP-GLES31.functional.compute.shared_var.atomic.compswap.*
Reviewed-by: Timothy Arceri
---
src/amd/common/ac_nir_to_llvm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 45405d30fe..6b519f78e0 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2631,6 +2631,7 @@ static LLVMValueRef visit_var_atomic(struct
ac_nir_context *ctx,
LLVMAtomicOrderingSequentiallyConsistent,
LLVMAtomicOrderingSequentiallyConsistent,
false);
+ result = LLVMBuildExtractValue(ctx->ac.builder, result, 0, "");
} else {
LLVMAtomicRMWBinOp op;
switch (instr->intrinsic) {
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Mesa (master): amd/common: pass address components individually to ac_build_image_intrinsic
Module: Mesa
Branch: master
Commit: 625dcbbc45665459737c9d028f268fd6782472f3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=625dcbbc45665459737c9d028f268fd6782472f3
Author: Nicolai Hähnle
Date: Fri Mar 23 11:20:24 2018 +0100
amd/common: pass address components individually to ac_build_image_intrinsic
This is in preparation for the new image intrinsics.
Acked-by: Marek Olšák
---
src/amd/common/ac_llvm_build.c | 101 +-
src/amd/common/ac_llvm_build.h | 14 +-
src/amd/common/ac_nir_to_llvm.c| 365 +++--
src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.h | 2 +-
src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c | 222 +
5 files changed, 295 insertions(+), 409 deletions(-)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 77b0798943..22aac7cbdb 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -37,6 +37,7 @@
#include "util/bitscan.h"
#include "util/macros.h"
#include "util/u_atomic.h"
+#include "util/u_math.h"
#include "sid.h"
#include "shader_enums.h"
@@ -1445,14 +1446,61 @@ void ac_build_export_null(struct ac_llvm_context *ctx)
ac_build_export(ctx, &args);
}
+static unsigned ac_num_coords(enum ac_image_dim dim)
+{
+ switch (dim) {
+ case ac_image_1d:
+ return 1;
+ case ac_image_2d:
+ case ac_image_1darray:
+return 2;
+ case ac_image_3d:
+ case ac_image_cube:
+ case ac_image_2darray:
+ case ac_image_2dmsaa:
+ return 3;
+ case ac_image_2darraymsaa:
+ return 4;
+ default:
+ unreachable("ac_num_coords: bad dim");
+ }
+}
+
+static unsigned ac_num_derivs(enum ac_image_dim dim)
+{
+ switch (dim) {
+ case ac_image_1d:
+ case ac_image_1darray:
+ return 2;
+ case ac_image_2d:
+ case ac_image_2darray:
+ case ac_image_cube:
+ return 4;
+ case ac_image_3d:
+ return 6;
+ case ac_image_2dmsaa:
+ case ac_image_2darraymsaa:
+ default:
+ unreachable("derivatives not supported");
+ }
+}
+
LLVMValueRef ac_build_image_opcode(struct ac_llvm_context *ctx,
struct ac_image_args *a)
{
- LLVMValueRef args[11];
- unsigned num_args = 0;
+ LLVMValueRef args[16];
const char *name = NULL;
char intr_name[128], type[64];
+ assert(!a->lod || a->lod == ctx->i32_0 || a->lod == ctx->f32_0 ||
+ !a->level_zero);
+ assert((a->opcode != ac_image_get_resinfo && a->opcode !=
ac_image_load_mip) ||
+ a->lod);
+ assert((a->bias ? 1 : 0) +
+ (a->lod ? 1 : 0) +
+ (a->level_zero ? 1 : 0) +
+ (a->derivs[0] ? 1 : 0) <= 1);
+
bool sample = a->opcode == ac_image_sample ||
a->opcode == ac_image_gather4 ||
a->opcode == ac_image_get_lod;
@@ -1463,10 +1511,38 @@ LLVMValueRef ac_build_image_opcode(struct
ac_llvm_context *ctx,
if (a->opcode == ac_image_get_lod)
da = false;
+ unsigned num_coords =
+ a->opcode != ac_image_get_resinfo ? ac_num_coords(a->dim) : 0;
+ LLVMValueRef addr;
+ unsigned num_addr = 0;
+
+ if (a->offset)
+ args[num_addr++] = ac_to_integer(ctx, a->offset);
+ if (a->bias)
+ args[num_addr++] = ac_to_integer(ctx, a->bias);
+ if (a->compare)
+ args[num_addr++] = ac_to_integer(ctx, a->compare);
+ if (a->derivs[0]) {
+ unsigned num_derivs = ac_num_derivs(a->dim);
+ for (unsigned i = 0; i < num_derivs; ++i)
+ args[num_addr++] = ac_to_integer(ctx, a->derivs[i]);
+ }
+ for (unsigned i = 0; i < num_coords; ++i)
+ args[num_addr++] = ac_to_integer(ctx, a->coords[i]);
+ if (a->lod)
+ args[num_addr++] = ac_to_integer(ctx, a->lod);
+
+ unsigned pad_goal = util_next_power_of_two(num_addr);
+ while (num_addr < pad_goal)
+ args[num_addr++] = LLVMGetUndef(ctx->i32);
+
+ addr = ac_build_gather_values(ctx, args, num_addr);
+
+ unsigned num_args = 0;
if (sample)
- args[num_args++] = ac_to_float(ctx, a->addr);
+ args[num_args++] = ac_to_float(ctx, addr);
else
- args[num_args++] = a->addr;
+ args[num_args++] = ac_to_integer(ctx, addr);
args[num_args++] = a->resource;
if (sample)
@@ -1505,12 +1581,15 @@ LLVMValueRef ac_build_image_opcode(struct
ac_llvm_context
Mesa (master): ac/nir: use ac_build_image_opcode for image intrinsics
Module: Mesa
Branch: master
Commit: 24fb3e6aa166b3afe906eb2845077766075189ed
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=24fb3e6aa166b3afe906eb2845077766075189ed
Author: Nicolai Hähnle
Date: Fri Apr 20 09:30:07 2018 +0200
ac/nir: use ac_build_image_opcode for image intrinsics
So that we'll use the dimension-aware intrinsics in the future.
Acked-by: Marek Olšák
---
src/amd/common/ac_llvm_build.c | 22 -
src/amd/common/ac_llvm_build.h | 6 --
src/amd/common/ac_nir_to_llvm.c | 190 +---
3 files changed, 78 insertions(+), 140 deletions(-)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 64b47e7343..02739f9da9 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -1948,28 +1948,6 @@ LLVMValueRef ac_build_fsign(struct ac_llvm_context *ctx,
LLVMValueRef src0,
return val;
}
-void ac_get_image_intr_name(const char *base_name,
- LLVMTypeRef data_type,
- LLVMTypeRef coords_type,
- LLVMTypeRef rsrc_type,
- char *out_name, unsigned out_len)
-{
-char coords_type_name[8];
-
-ac_build_type_name_for_intr(coords_type, coords_type_name,
-sizeof(coords_type_name));
-
- char data_type_name[8];
- char rsrc_type_name[8];
-
- ac_build_type_name_for_intr(data_type, data_type_name,
- sizeof(data_type_name));
- ac_build_type_name_for_intr(rsrc_type, rsrc_type_name,
- sizeof(rsrc_type_name));
- snprintf(out_name, out_len, "%s.%s.%s.%s", base_name,
-data_type_name, coords_type_name, rsrc_type_name);
-}
-
#define AC_EXP_TARGET (HAVE_LLVM >= 0x0500 ? 0 : 3)
#define AC_EXP_ENABLED_CHANNELS (HAVE_LLVM >= 0x0500 ? 1 : 0)
#define AC_EXP_OUT0 (HAVE_LLVM >= 0x0500 ? 2 : 5)
diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index b676adba65..026955a555 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -401,12 +401,6 @@ LLVMValueRef ac_build_isign(struct ac_llvm_context *ctx,
LLVMValueRef src0,
LLVMValueRef ac_build_fsign(struct ac_llvm_context *ctx, LLVMValueRef src0,
unsigned bitsize);
-void ac_get_image_intr_name(const char *base_name,
- LLVMTypeRef data_type,
- LLVMTypeRef coords_type,
- LLVMTypeRef rsrc_type,
- char *out_name, unsigned out_len);
-
void ac_optimize_vs_outputs(struct ac_llvm_context *ac,
LLVMValueRef main_fn,
uint8_t *vs_output_param_offset,
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index a0e1837999..f00091e825 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1130,23 +1130,6 @@ get_buffer_size(struct ac_nir_context *ctx, LLVMValueRef
descriptor, bool in_ele
return size;
}
-/**
- * Given the i32 or vNi32 \p type, generate the textual name (e.g. for use with
- * intrinsic names).
- */
-static void build_int_type_name(
- LLVMTypeRef type,
- char *buf, unsigned bufsize)
-{
- assert(bufsize >= 6);
-
- if (LLVMGetTypeKind(type) == LLVMVectorTypeKind)
- snprintf(buf, bufsize, "v%ui32",
-LLVMGetVectorSize(type));
- else
- strcpy(buf, "i32");
-}
-
static LLVMValueRef lower_gather4_integer(struct ac_llvm_context *ctx,
struct ac_image_args *args,
const nir_tex_instr *instr)
@@ -1165,6 +1148,7 @@ static LLVMValueRef lower_gather4_integer(struct
ac_llvm_context *ctx,
txq_args.dmask = 0xf;
txq_args.lod = ctx->i32_0;
txq_args.resource = args->resource;
+ txq_args.attributes = AC_FUNC_ATTR_READNONE;
LLVMValueRef size = ac_build_image_opcode(ctx, &txq_args);
for (unsigned c = 0; c < 2; c++) {
@@ -1233,6 +1217,8 @@ static LLVMValueRef lower_gather4_integer(struct
ac_llvm_context *ctx,
ctx->builder, compare_cube_wa,
orig_coords[c], args->coords[c], "");
}
+
+ args->attributes = AC_FUNC_ATTR_READNONE;
result = ac_build_image_opcode(ctx, args);
if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
@@ -1320,6 +1306,8 @@ static LLVMValueRef build_tex_intrinsic(struct
ac_nir_context *ctx,
return lower_gather4_integer(&ctx->ac, args, instr);
}
}
+
+ args->attributes = AC_FUNC_ATTR_READNONE;
Mesa (master): radeonsi/nir: set FS properties only when scanning a fragment shader
Module: Mesa
Branch: master
Commit: 552bc37c6f6314e3d644d0dbd7ce6891e7f8dea8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=552bc37c6f6314e3d644d0dbd7ce6891e7f8dea8
Author: Nicolai Hähnle
Date: Mon Apr 2 13:20:02 2018 +0200
radeonsi/nir: set FS properties only when scanning a fragment shader
Reviewed-by: Timothy Arceri
---
src/gallium/drivers/radeonsi/si_shader_nir.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index c0e08c79a5..b4fba8b881 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -607,7 +607,8 @@ void si_nir_scan_shader(const struct nir_shader *nir,
}
unsigned loc = variable->data.location;
- if (loc == FRAG_RESULT_COLOR &&
+ if (nir->info.stage == MESA_SHADER_FRAGMENT &&
+ loc == FRAG_RESULT_COLOR &&
nir->info.outputs_written & (1ull << loc)) {
assert(attrib_count == 1);
info->properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] = true;
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Mesa (master): radeonsi: correctly parse disassembly with labels
Module: Mesa
Branch: master
Commit: 41e6ffee49832c57b3821e4b63e0245db7b115f9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=41e6ffee49832c57b3821e4b63e0245db7b115f9
Author: Nicolai Hähnle
Date: Thu Jan 18 16:05:21 2018 +0100
radeonsi: correctly parse disassembly with labels
LLVM now emits labels as part of the disassembly string, which is very
useful but breaks the old parsing approach.
Use the semicolon to detect the boundary of instructions instead of going
by line breaks.
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeonsi/si_debug.c | 63 +
1 file changed, 32 insertions(+), 31 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_debug.c
b/src/gallium/drivers/radeonsi/si_debug.c
index 69d20c1efe..817a6d5ee9 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -31,6 +31,7 @@
#include "util/u_dump.h"
#include "util/u_log.h"
#include "util/u_memory.h"
+#include "util/u_string.h"
#include "ac_debug.h"
static void si_dump_bo_list(struct si_context *sctx,
@@ -859,42 +860,40 @@ static void si_dump_compute_descriptors(struct si_context
*sctx,
}
struct si_shader_inst {
- char text[160]; /* one disasm line */
- unsigned offset; /* instruction offset */
+ const char *text; /* start of disassembly for this instruction */
+ unsigned textlen;
unsigned size; /* instruction size = 4 or 8 */
+ uint64_t addr; /* instruction address */
};
-/* Split a disassembly string into lines and add them to the array pointed
- * to by "instructions". */
+/**
+ * Split a disassembly string into instructions and add them to the array
+ * pointed to by \p instructions.
+ *
+ * Labels are considered to be part of the following instruction.
+ */
static void si_add_split_disasm(const char *disasm,
- uint64_t start_addr,
+ uint64_t *addr,
unsigned *num,
struct si_shader_inst *instructions)
{
- struct si_shader_inst *last_inst = *num ? &instructions[*num - 1] :
NULL;
- char *next;
+ const char *semicolon;
- while ((next = strchr(disasm, '\n'))) {
- struct si_shader_inst *inst = &instructions[*num];
- unsigned len = next - disasm;
+ while ((semicolon = strchr(disasm, ';'))) {
+ struct si_shader_inst *inst = &instructions[(*num)++];
+ const char *end = util_strchrnul(semicolon, '\n');
- assert(len < ARRAY_SIZE(inst->text));
- memcpy(inst->text, disasm, len);
- inst->text[len] = 0;
- inst->offset = last_inst ? last_inst->offset + last_inst->size
: 0;
+ inst->text = disasm;
+ inst->textlen = end - disasm;
- const char *semicolon = strchr(disasm, ';');
- assert(semicolon);
+ inst->addr = *addr;
/* More than 16 chars after ";" means the instruction is 8
bytes long. */
- inst->size = next - semicolon > 16 ? 8 : 4;
-
- snprintf(inst->text + len, ARRAY_SIZE(inst->text) - len,
- " [PC=0x%"PRIx64", off=%u, size=%u]",
- start_addr + inst->offset, inst->offset, inst->size);
+ inst->size = end - semicolon > 16 ? 8 : 4;
+ *addr += inst->size;
- last_inst = inst;
- (*num)++;
- disasm = next + 1;
+ if (!(*end))
+ break;
+ disasm = end + 1;
}
}
@@ -930,26 +929,27 @@ static void si_print_annotated_shader(struct si_shader
*shader,
* Buffer size / 4 is the upper bound of the instruction count.
*/
unsigned num_inst = 0;
+ uint64_t inst_addr = start_addr;
struct si_shader_inst *instructions =
calloc(shader->bo->b.b.width0 / 4, sizeof(struct
si_shader_inst));
if (shader->prolog) {
si_add_split_disasm(shader->prolog->binary.disasm_string,
- start_addr, &num_inst, instructions);
+ &inst_addr, &num_inst, instructions);
}
if (shader->previous_stage) {
si_add_split_disasm(shader->previous_stage->binary.disasm_string,
- start_addr, &num_inst, instructions);
+ &inst_addr, &num_inst, instructions);
}
if (shader->prolog2) {
si_add_split_disasm(shader->prolog2->binary.disasm_string,
-
Mesa (master): radeonsi: pass -O halt_waves to umr for hang debugging
Module: Mesa
Branch: master
Commit: 0630e52c9eba4af9b1e96705248bad03a0cb951e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0630e52c9eba4af9b1e96705248bad03a0cb951e
Author: Nicolai Hähnle
Date: Thu Jan 18 16:04:15 2018 +0100
radeonsi: pass -O halt_waves to umr for hang debugging
This will give us meaningful wave information in the case of a hang where
shaders are still running in an infinite loop.
Note that we call umr multiple times for different sections of the ddebug
hang dump, and so the wave information will not necessarily match up
between sections.
Reviewed-by: Marek Olšák
---
src/amd/common/ac_debug.c | 2 +-
src/gallium/drivers/radeonsi/si_debug.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/amd/common/ac_debug.c b/src/amd/common/ac_debug.c
index 7f43437aa9..3b15398a2a 100644
--- a/src/amd/common/ac_debug.c
+++ b/src/amd/common/ac_debug.c
@@ -761,7 +761,7 @@ unsigned ac_get_wave_info(struct ac_wave_info
waves[AC_MAX_WAVES_PER_CHIP])
char line[2000];
unsigned num_waves = 0;
- FILE *p = popen("umr -wa", "r");
+ FILE *p = popen("umr -O halt_waves -wa", "r");
if (!p)
return 0;
diff --git a/src/gallium/drivers/radeonsi/si_debug.c
b/src/gallium/drivers/radeonsi/si_debug.c
index 00e0722c82..69d20c1efe 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -1051,8 +1051,8 @@ static void si_dump_debug_state(struct pipe_context *ctx,
FILE *f,
si_dump_debug_registers(sctx, f);
si_dump_annotated_shaders(sctx, f);
- si_dump_command("Active waves (raw data)", "umr -wa | column
-t", f);
- si_dump_command("Wave information", "umr -O bits -wa", f);
+ si_dump_command("Active waves (raw data)", "umr -O halt_waves
-wa | column -t", f);
+ si_dump_command("Wave information", "umr -O halt_waves,bits
-wa", f);
}
}
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Mesa (master): radeonsi: fix the R600_RESOURCE_FLAG_UNMAPPABLE check
Module: Mesa
Branch: master
Commit: 5e2962c9492e6a948516f6360f973e2e92034b01
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e2962c9492e6a948516f6360f973e2e92034b01
Author: Nicolai Hähnle
Date: Thu Nov 23 10:25:34 2017 +0100
radeonsi: fix the R600_RESOURCE_FLAG_UNMAPPABLE check
The flag is on the pipe_resource, not the r600_resource.
I don't see an obvious bug related to this, but it could potentially lead
to suboptimal placement of some resources.
Fixes: a41587433c4d ("gallium/radeon: add R600_RESOURCE_FLAG_UNMAPPABLE")
Reviewed-by: Marek Olšák
Tested-by: Dieter Nützel
---
src/gallium/drivers/radeon/r600_buffer_common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c
b/src/gallium/drivers/radeon/r600_buffer_common.c
index ec282d55aa..f1c4780dfe 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -159,7 +159,7 @@ void si_init_resource_fields(struct si_screen *sscreen,
/* Tiled textures are unmappable. Always put them in VRAM. */
if ((res->b.b.target != PIPE_BUFFER && !rtex->surface.is_linear) ||
- res->flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
+ res->b.b.flags & R600_RESOURCE_FLAG_UNMAPPABLE) {
res->domains = RADEON_DOMAIN_VRAM;
res->flags |= RADEON_FLAG_NO_CPU_ACCESS |
RADEON_FLAG_GTT_WC;
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Mesa (master): radeonsi: always place sparse buffers in VRAM
Module: Mesa
Branch: master
Commit: 20ccb51ffcc46a68ab0eb82a43ed55a1e1952850
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=20ccb51ffcc46a68ab0eb82a43ed55a1e1952850
Author: Nicolai Hähnle
Date: Thu Nov 23 10:29:49 2017 +0100
radeonsi: always place sparse buffers in VRAM
Together with "radeonsi: fix the R600_RESOURCE_FLAG_UNMAPPABLE check",
this ensures that sparse buffers are placed in VRAM.
Noticed by an assertion that started triggering with commit d4fac1e1d7
("gallium/radeon: enable suballocations for VRAM with no CPU access")
Fixes KHR-GL45.sparse_buffer_tests.BufferStorageTest in debug builds.
Reviewed-by: Marek Olšák
Tested-by: Dieter Nützel
---
src/gallium/drivers/radeon/r600_buffer_common.c | 3 +++
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 5 +++--
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c
b/src/gallium/drivers/radeon/r600_buffer_common.c
index f1c4780dfe..09075f3ea2 100644
--- a/src/gallium/drivers/radeon/r600_buffer_common.c
+++ b/src/gallium/drivers/radeon/r600_buffer_common.c
@@ -610,6 +610,9 @@ static struct pipe_resource *si_buffer_create(struct
pipe_screen *screen,
struct si_screen *sscreen = (struct si_screen*)screen;
struct r600_resource *rbuffer = r600_alloc_buffer_struct(screen, templ);
+ if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
+ rbuffer->b.b.flags |= R600_RESOURCE_FLAG_UNMAPPABLE;
+
si_init_resource_fields(sscreen, rbuffer, templ->width0, alignment);
if (templ->flags & PIPE_RESOURCE_FLAG_SPARSE)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
index d3b3674f12..0d824025ce 100644
--- a/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
+++ b/src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
@@ -1169,6 +1169,9 @@ amdgpu_bo_create(struct radeon_winsys *rws,
/* NO_CPU_ACCESS is valid with VRAM only. */
assert(domain == RADEON_DOMAIN_VRAM || !(flags &
RADEON_FLAG_NO_CPU_ACCESS));
+ /* Sparse buffers must have NO_CPU_ACCESS set. */
+ assert(!(flags & RADEON_FLAG_SPARSE) || flags & RADEON_FLAG_NO_CPU_ACCESS);
+
/* Sub-allocate small buffers from slabs. */
if (!(flags & (RADEON_FLAG_NO_SUBALLOC | RADEON_FLAG_SPARSE)) &&
size <= (1 << AMDGPU_SLAB_MAX_SIZE_LOG2) &&
@@ -1201,8 +1204,6 @@ no_slab:
if (flags & RADEON_FLAG_SPARSE) {
assert(RADEON_SPARSE_PAGE_SIZE % alignment == 0);
- flags |= RADEON_FLAG_NO_CPU_ACCESS;
-
return amdgpu_bo_sparse_create(ws, size, domain, flags);
}
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Mesa (master): radeonsi: cleanup si_initialize_color_surface
Module: Mesa
Branch: master
Commit: 1c2d19d84d74a3cac2d8c534f9447c105f36c705
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c2d19d84d74a3cac2d8c534f9447c105f36c705
Author: Nicolai Hähnle
Date: Thu Nov 16 07:33:34 2017 +0100
radeonsi: cleanup si_initialize_color_surface
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeonsi/si_state.c | 24
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 0b82429b03..dea4d466eb 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2327,15 +2327,12 @@ static void si_initialize_color_surface(struct
si_context *sctx,
struct r600_surface *surf)
{
struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
- unsigned color_info, color_attrib, color_view;
+ unsigned color_info, color_attrib;
unsigned format, swap, ntype, endian;
const struct util_format_description *desc;
int firstchan;
unsigned blend_clamp = 0, blend_bypass = 0;
- color_view = S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
-S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
-
desc = util_format_description(surf->base.format);
for (firstchan = 0; firstchan < 4; firstchan++) {
if (desc->channel[firstchan].type != UTIL_FORMAT_TYPE_VOID) {
@@ -2432,10 +2429,6 @@ static void si_initialize_color_surface(struct
si_context *sctx,
}
}
- surf->cb_color_view = color_view;
- surf->cb_color_info = color_info;
- surf->cb_color_attrib = color_attrib;
-
if (sctx->b.chip_class >= VI) {
unsigned max_uncompressed_block_size = 2;
@@ -2453,20 +2446,27 @@ static void si_initialize_color_surface(struct
si_context *sctx,
/* This must be set for fast clear to work without FMASK. */
if (!rtex->fmask.size && sctx->b.chip_class == SI) {
unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
- surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
+ color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
}
+ unsigned color_view =
S_028C6C_SLICE_START(surf->base.u.tex.first_layer) |
+ S_028C6C_SLICE_MAX(surf->base.u.tex.last_layer);
+
if (sctx->b.chip_class >= GFX9) {
unsigned mip0_depth = util_max_layer(&rtex->resource.b.b, 0);
- surf->cb_color_view |=
S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
- surf->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
-
S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
+ color_view |= S_028C6C_MIP_LEVEL(surf->base.u.tex.level);
+ color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
+
S_028C74_RESOURCE_TYPE(rtex->surface.u.gfx9.resource_type);
surf->cb_color_attrib2 = S_028C68_MIP0_WIDTH(surf->width0 - 1) |
S_028C68_MIP0_HEIGHT(surf->height0 -
1) |
S_028C68_MAX_MIP(rtex->resource.b.b.last_level);
}
+ surf->cb_color_view = color_view;
+ surf->cb_color_info = color_info;
+ surf->cb_color_attrib = color_attrib;
+
/* Determine pixel shader export format */
si_choose_spi_color_formats(surf, format, swap, ntype, rtex->is_depth);
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Mesa (master): radeonsi/gfx9: simplify condition for on-chip ESGS
Module: Mesa Branch: master Commit: dd078689041077eb9d90888a3cb0166fdc093b93 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=dd078689041077eb9d90888a3cb0166fdc093b93 Author: Nicolai Hähnle Date: Thu Nov 16 17:23:43 2017 +0100 radeonsi/gfx9: simplify condition for on-chip ESGS Reviewed-by: Marek Olšák --- src/gallium/drivers/radeonsi/si_shader.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_shader.c b/src/gallium/drivers/radeonsi/si_shader.c index a997ab0103..fc4bab8c9c 100644 --- a/src/gallium/drivers/radeonsi/si_shader.c +++ b/src/gallium/drivers/radeonsi/si_shader.c @@ -4739,9 +4739,7 @@ static void create_function(struct si_shader_context *ctx) if (shader->key.as_ls || ctx->type == PIPE_SHADER_TESS_CTRL || /* GFX9 has the ESGS ring buffer in LDS. */ - (ctx->screen->b.chip_class >= GFX9 && -(shader->key.as_es || - ctx->type == PIPE_SHADER_GEOMETRY))) + type == SI_SHADER_MERGED_VERTEX_OR_TESSEVAL_GEOMETRY) ac_declare_lds_as_pointer(&ctx->ac); } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): amd/common: sid.h cleanups
Module: Mesa Branch: master Commit: 97f42d11df8268ab3303cefd5b35bd43ae065f46 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=97f42d11df8268ab3303cefd5b35bd43ae065f46 Author: Nicolai Hähnle Date: Thu Nov 9 10:59:22 2017 +0100 amd/common: sid.h cleanups Fix a bunch of labels indicating when registers were added/removed and normalize the SI-class GRBM_GFX_INDEX. Reviewed-by: Marek Olšák --- src/amd/common/sid.h| 42 +++-- src/amd/vulkan/si_cmd_buffer.c | 14 ++- src/gallium/drivers/radeonsi/si_state.c | 2 +- 3 files changed, 38 insertions(+), 20 deletions(-) diff --git a/src/amd/common/sid.h b/src/amd/common/sid.h index 15ebd9b267..59a7e2a06e 100644 --- a/src/amd/common/sid.h +++ b/src/amd/common/sid.h @@ -698,13 +698,14 @@ #define S_008010_GUI_ACTIVE(x) (((unsigned)(x) & 0x1) << 31) #define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 0x1) #define C_008010_GUI_ACTIVE 0x7FFF -#define GRBM_GFX_INDEX 0x802C -#define INSTANCE_INDEX(x) ((x) << 0) -#define SH_INDEX(x) ((x) << 8) -#define SE_INDEX(x) ((x) << 16) -#define SH_BROADCAST_WRITES (1 << 29) -#define INSTANCE_BROADCAST_WRITES (1 << 30) -#define SE_BROADCAST_WRITES (1 << 31) +/* not on CIK -- moved to uconfig space */ +#define R_00802C_GRBM_GFX_INDEX 0x802C +#define S_00802C_INSTANCE_INDEX(x) (((unsigned)(x) & 0xFF) << 0) +#define S_00802C_SH_INDEX(x) (((unsigned)(x) & 0xFF) << 8) +#define S_00802C_SE_INDEX(x) (((unsigned)(x) & 0xFF) << 16) +#define S_00802C_SH_BROADCAST_WRITES(x) (((unsigned)(x) & 0x1) << 29) +#define S_00802C_INSTANCE_BROADCAST_WRITES(x) (((unsigned)(x) & 0x1) << 30) +#define S_00802C_SE_BROADCAST_WRITES(x) (((unsigned)(x) & 0x1) << 31) #define R_0084FC_CP_STRMOUT_CNTL 0x0084FC #define S_0084FC_OFFSET_UPDATE_DONE(x) (((unsigned)(x) & 0x1) << 0) #define R_0085F0_CP_COHER_CNTL 0x0085F0 @@ -767,6 +768,7 @@ #define C_0085F0_SH_ICACHE_ACTION_ENA 0xDFFF #define R_0085F4_CP_COHER_SIZE 0x0085F4 #define R_0085F8_CP_COHER_BASE 0x0085F8 +/* */ #define R_008014_GRBM_STATUS_SE0 0x008014 #define S_008014_DB_CLEAN(x) (((unsigned)(x) & 0x1) << 1) #define G_008014_DB_CLEAN(x)(((x) >> 1) & 0x1) @@ -1001,7 +1003,7 @@ #define S_0301F0_SH_SD_ACTION_ENA(x) (((unsigned)(x) & 0x1) << 31) #define G_0301F0_SH_SD_ACTION_ENA(x)(((x) >> 31) & 0x1) #define C_0301F0_SH_SD_ACTION_ENA 0x7FFF -/**/ +/* CIK */ #define R_0301F4_CP_COHER_SIZE 0x0301F4 #define R_0301F8_CP_COHER_BASE 0x0301F8 #define R_0301FC_CP_COHER_STATUS 0x0301FC @@ -1017,6 +1019,7 @@ #define S_0301FC_STATUS(x) (((unsigned)(x) & 0x1) << 31) #define G_0301FC_STATUS(x) (((x) >> 31) & 0x1) #define C_0301FC_STATUS 0x7FFF +/**/ #define R_008210_CP_CPC_STATUS 0x008210 #define S_008210_MEC1_BUSY(x) (((unsigned)(x) & 0x1) << 0) #define G_008210_MEC1_BUSY(x) (((x) >> 0) & 0x1) @@ -1396,12 +1399,15 @@ #define S_0088C4_ES_LIMIT(x) (((unsigned)(x) & 0x1F) << 16) #define G_0088C4_ES_LIMIT(x)(((x) >> 16) & 0x1F) #define C_0088C4_ES_LIMIT 0xFFE0 +/* not on CIK -- moved to uconfig space */ #define R_0088C8_VGT_ESGS_RING_SIZE
Mesa (master): ac/surface: fix indentation
Module: Mesa
Branch: master
Commit: 377a0623215d052a04cfdd0967d082fb27399421
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=377a0623215d052a04cfdd0967d082fb27399421
Author: Nicolai Hähnle
Date: Sun Nov 19 16:09:28 2017 +0100
ac/surface: fix indentation
Reviewed-by: Marek Olšák
---
src/amd/common/ac_surface.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index 2b6c3fb013..4db48cf33b 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -861,7 +861,7 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
ret = Addr2ComputeSurfaceInfo(addrlib, in, &out);
if (ret != ADDR_OK)
- return ret;
+ return ret;
if (in->flags.stencil) {
surf->u.gfx9.stencil.swizzle_mode = in->swizzleMode;
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Mesa (master): radeonsi: check that we don't leak fine.buf references
Module: Mesa
Branch: master
Commit: e52e8326d9131670880d4b6fa285d49c7e1d7fee
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e52e8326d9131670880d4b6fa285d49c7e1d7fee
Author: Nicolai Hähnle
Date: Tue Nov 14 09:37:38 2017 +0100
radeonsi: check that we don't leak fine.buf references
Just as an added precaution.
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeonsi/si_fence.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_fence.c
b/src/gallium/drivers/radeonsi/si_fence.c
index b835ed649e..61105217ca 100644
--- a/src/gallium/drivers/radeonsi/si_fence.c
+++ b/src/gallium/drivers/radeonsi/si_fence.c
@@ -445,12 +445,14 @@ static void si_flush_from_st(struct pipe_context *ctx,
}
multi_fence->fine = fine;
+ fine.buf = NULL;
if (flags & TC_FLUSH_ASYNC) {
util_queue_fence_signal(&multi_fence->ready);
tc_unflushed_batch_token_reference(&multi_fence->tc_token, NULL);
}
}
+ assert(!fine.buf);
finish:
if (!(flags & PIPE_FLUSH_DEFERRED)) {
if (rctx->dma.cs)
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Mesa (master): radeonsi: avoid attempting to create CMASK if the tiling mode doesn't have it
Module: Mesa Branch: master Commit: 08f6b4dd7bce06389b38c0ef40ccc2babc5920f1 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=08f6b4dd7bce06389b38c0ef40ccc2babc5920f1 Author: Nicolai Hähnle Date: Sun Nov 19 17:26:45 2017 +0100 radeonsi: avoid attempting to create CMASK if the tiling mode doesn't have it Reviewed-by: Marek Olšák --- src/gallium/drivers/radeon/r600_texture.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/gallium/drivers/radeon/r600_texture.c b/src/gallium/drivers/radeon/r600_texture.c index eb63cdefd1..3fa5f5eaa9 100644 --- a/src/gallium/drivers/radeon/r600_texture.c +++ b/src/gallium/drivers/radeon/r600_texture.c @@ -848,6 +848,8 @@ static void r600_texture_alloc_cmask_separate(struct r600_common_screen *rscreen assert(rtex->cmask.size == 0); si_texture_get_cmask_info(rscreen, rtex, &rtex->cmask); + if (!rtex->cmask.size) + return; rtex->cmask_buffer = (struct r600_resource *) si_aligned_buffer_create(&rscreen->b, ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: use si_shader_context instead of lp_build_context in more places
Module: Mesa
Branch: master
Commit: 26da5d0317a607783b5a52fc3dfabfebac68ebdb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=26da5d0317a607783b5a52fc3dfabfebac68ebdb
Author: Nicolai Hähnle
Date: Thu Nov 16 16:56:21 2017 +0100
radeonsi: use si_shader_context instead of lp_build_context in more places
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader.c | 50 +++-
1 file changed, 23 insertions(+), 27 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index 74cea7ad59..a997ab0103 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -2083,13 +2083,12 @@ static LLVMValueRef
si_llvm_pack_two_int32_as_int16(struct si_shader_context *ct
}
/* Initialize arguments for the shader export intrinsic */
-static void si_llvm_init_export_args(struct lp_build_tgsi_context *bld_base,
+static void si_llvm_init_export_args(struct si_shader_context *ctx,
LLVMValueRef *values,
unsigned target,
struct ac_export_args *args)
{
- struct si_shader_context *ctx = si_shader_context(bld_base);
- struct lp_build_context *base = &bld_base->base;
+ LLVMValueRef f32undef = LLVMGetUndef(ctx->ac.f32);
LLVMBuilderRef builder = ctx->ac.builder;
LLVMValueRef val[4];
unsigned spi_shader_col_format = V_028714_SPI_SHADER_32_ABGR;
@@ -2120,10 +2119,10 @@ static void si_llvm_init_export_args(struct
lp_build_tgsi_context *bld_base,
}
args->compr = false;
- args->out[0] = base->undef;
- args->out[1] = base->undef;
- args->out[2] = base->undef;
- args->out[3] = base->undef;
+ args->out[0] = f32undef;
+ args->out[1] = f32undef;
+ args->out[2] = f32undef;
+ args->out[3] = f32undef;
switch (spi_shader_col_format) {
case V_028714_SPI_SHADER_ZERO:
@@ -2182,10 +2181,10 @@ static void si_llvm_init_export_args(struct
lp_build_tgsi_context *bld_base,
case V_028714_SPI_SHADER_SNORM16_ABGR:
for (chan = 0; chan < 4; chan++) {
/* Clamp between [-1, 1]. */
- val[chan] = lp_build_emit_llvm_binary(bld_base,
TGSI_OPCODE_MIN,
+ val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base,
TGSI_OPCODE_MIN,
values[chan],
LLVMConstReal(ctx->f32, 1));
- val[chan] = lp_build_emit_llvm_binary(bld_base,
TGSI_OPCODE_MAX,
+ val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base,
TGSI_OPCODE_MAX,
val[chan],
LLVMConstReal(ctx->f32, -1));
/* Convert to a signed integer in [-32767, 32767]. */
@@ -2215,7 +2214,7 @@ static void si_llvm_init_export_args(struct
lp_build_tgsi_context *bld_base,
/* Clamp. */
for (chan = 0; chan < 4; chan++) {
val[chan] = ac_to_integer(&ctx->ac, values[chan]);
- val[chan] = lp_build_emit_llvm_binary(bld_base,
TGSI_OPCODE_UMIN,
+ val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base,
TGSI_OPCODE_UMIN,
val[chan],
chan == 3 ? max_alpha : max_rgb);
}
@@ -2239,10 +2238,10 @@ static void si_llvm_init_export_args(struct
lp_build_tgsi_context *bld_base,
/* Clamp. */
for (chan = 0; chan < 4; chan++) {
val[chan] = ac_to_integer(&ctx->ac, values[chan]);
- val[chan] = lp_build_emit_llvm_binary(bld_base,
+ val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base,
TGSI_OPCODE_IMIN,
val[chan], chan == 3 ? max_alpha :
max_rgb);
- val[chan] = lp_build_emit_llvm_binary(bld_base,
+ val[chan] = lp_build_emit_llvm_binary(&ctx->bld_base,
TGSI_OPCODE_IMAX,
val[chan], chan == 3 ? min_alpha :
min_rgb);
}
@@ -2312,11 +2311,9 @@ static LLVMValueRef si_scale_alpha_by_sample_mask(struct
lp_build_tgsi_context *
return LLVMBuildFMul(ctx->ac.builder, alpha, coverage, "");
}
-static void si_llvm_emit_clipvertex(struct lp_build_tgsi_context *bld_base,
+static void si_llvm_emit_clipvertex(struct si_shader_context *ctx,
Mesa (master): radeonsi: clarify that si_shader_selector:: esgs_itemsize is set for the ES part
Module: Mesa
Branch: master
Commit: 239d2b5809ccfd207a7c3f3a98c1620ec40e1e1c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=239d2b5809ccfd207a7c3f3a98c1620ec40e1e1c
Author: Nicolai Hähnle
Date: Sat Nov 18 14:33:34 2017 +0100
radeonsi: clarify that si_shader_selector::esgs_itemsize is set for the ES part
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader.h | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.h
b/src/gallium/drivers/radeonsi/si_shader.h
index 148356b87f..bcb5c9da4c 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -341,8 +341,10 @@ struct si_shader_selector {
ubyte clipdist_mask;
ubyte culldist_mask;
- /* GS parameters. */
+ /* ES parameters. */
unsignedesgs_itemsize;
+
+ /* GS parameters. */
unsignedgs_input_verts_per_prim;
unsignedgs_output_prim;
unsignedgs_max_out_vertices;
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Mesa (master): st_glsl_to_tgsi: check for the tail sentinel in merge_two_dsts
Module: Mesa
Branch: master
Commit: 7e35bdad1c67d7df2832ac4b39bff471e83812e5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e35bdad1c67d7df2832ac4b39bff471e83812e5
Author: Nicolai Hähnle
Date: Fri Nov 17 20:01:50 2017 +0100
st_glsl_to_tgsi: check for the tail sentinel in merge_two_dsts
This fixes yet another case where DFRACEXP has only one destination. Found
by address sanitizer.
Fixes
tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-frexp-dvec4-only-mantissa.shader_test
Fixes: 3b666aa74795 ("st/glsl_to_tgsi: fix DFRACEXP with only one destination")
Acked-by: Marek Olšák
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 0772b73627..fa51fef343 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -5252,7 +5252,7 @@ glsl_to_tgsi_visitor::merge_two_dsts(void)
defined = 0;
inst2 = (glsl_to_tgsi_instruction *) inst->next;
- do {
+ while (!inst2->is_tail_sentinel()) {
if (inst->op == inst2->op &&
inst2->dst[defined].file == PROGRAM_UNDEFINED &&
inst->src[0].file == inst2->src[0].file &&
@@ -5261,9 +5261,9 @@ glsl_to_tgsi_visitor::merge_two_dsts(void)
inst->src[0].swizzle == inst2->src[0].swizzle)
break;
inst2 = (glsl_to_tgsi_instruction *) inst2->next;
- } while (inst2);
+ }
- if (!inst2) {
+ if (inst2->is_tail_sentinel()) {
/* Undefined destinations are not allowed, substitute with an unused
* temporary register.
*/
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Mesa (master): u_threaded_gallium: remove synchronization in fence_server_sync
Module: Mesa
Branch: master
Commit: ce470af0b1bcb276c22dd04e627ab665e10619f7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ce470af0b1bcb276c22dd04e627ab665e10619f7
Author: Nicolai Hähnle
Date: Mon Nov 6 11:56:54 2017 +0100
u_threaded_gallium: remove synchronization in fence_server_sync
The whole point of fence_server_sync is that it can be used to
avoid waiting in the application thread.
Reviewed-by: Andres Rodriguez
Reviewed-by: Marek Olšák
---
src/gallium/auxiliary/util/u_threaded_context.c | 14 +++---
src/gallium/auxiliary/util/u_threaded_context.h | 1 +
src/gallium/auxiliary/util/u_threaded_context_calls.h | 1 +
3 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_threaded_context.c
b/src/gallium/auxiliary/util/u_threaded_context.c
index b212393a5b..d0a8ffbd11 100644
--- a/src/gallium/auxiliary/util/u_threaded_context.c
+++ b/src/gallium/auxiliary/util/u_threaded_context.c
@@ -1835,14 +1835,22 @@ tc_create_fence_fd(struct pipe_context *_pipe,
}
static void
+tc_call_fence_server_sync(struct pipe_context *pipe, union tc_payload *payload)
+{
+ pipe->fence_server_sync(pipe, payload->fence);
+ pipe->screen->fence_reference(pipe->screen, &payload->fence, NULL);
+}
+
+static void
tc_fence_server_sync(struct pipe_context *_pipe,
struct pipe_fence_handle *fence)
{
struct threaded_context *tc = threaded_context(_pipe);
- struct pipe_context *pipe = tc->pipe;
+ struct pipe_screen *screen = tc->pipe->screen;
+ union tc_payload *payload = tc_add_small_call(tc,
TC_CALL_fence_server_sync);
- tc_sync(tc);
- pipe->fence_server_sync(pipe, fence);
+ payload->fence = NULL;
+ screen->fence_reference(screen, &payload->fence, fence);
}
static struct pipe_video_codec *
diff --git a/src/gallium/auxiliary/util/u_threaded_context.h
b/src/gallium/auxiliary/util/u_threaded_context.h
index ea815ed5e0..b2d904569e 100644
--- a/src/gallium/auxiliary/util/u_threaded_context.h
+++ b/src/gallium/auxiliary/util/u_threaded_context.h
@@ -309,6 +309,7 @@ union tc_payload {
struct pipe_query *query;
struct pipe_resource *resource;
struct pipe_transfer *transfer;
+ struct pipe_fence_handle *fence;
uint64_t handle;
};
diff --git a/src/gallium/auxiliary/util/u_threaded_context_calls.h
b/src/gallium/auxiliary/util/u_threaded_context_calls.h
index 0d2fd18368..675deaabd9 100644
--- a/src/gallium/auxiliary/util/u_threaded_context_calls.h
+++ b/src/gallium/auxiliary/util/u_threaded_context_calls.h
@@ -1,5 +1,6 @@
CALL(flush)
CALL(callback)
+CALL(fence_server_sync)
CALL(destroy_query)
CALL(begin_query)
CALL(end_query)
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Mesa (master): ddebug: fix use-after-free of streamout targets
Module: Mesa
Branch: master
Commit: 16f8da299700e714fd5aff265b8f28fe2badfa95
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=16f8da299700e714fd5aff265b8f28fe2badfa95
Author: Nicolai Hähnle
Date: Fri Nov 10 13:11:53 2017 +0100
ddebug: fix use-after-free of streamout targets
Fixes: b47727a83ad6 ("ddebug: implement pipelined hang detection mode")
Reviewed-by: Marek Olšák
---
src/gallium/drivers/ddebug/dd_draw.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/ddebug/dd_draw.c
b/src/gallium/drivers/ddebug/dd_draw.c
index a25017114d..e908410a33 100644
--- a/src/gallium/drivers/ddebug/dd_draw.c
+++ b/src/gallium/drivers/ddebug/dd_draw.c
@@ -767,7 +767,7 @@ dd_copy_draw_state(struct dd_draw_state *dst, struct
dd_draw_state *src)
}
dst->num_so_targets = src->num_so_targets;
- for (i = 0; i < ARRAY_SIZE(src->so_targets); i++)
+ for (i = 0; i < src->num_so_targets; i++)
pipe_so_target_reference(&dst->so_targets[i], src->so_targets[i]);
memcpy(dst->so_offsets, src->so_offsets, sizeof(src->so_offsets));
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Mesa (master): gallium/u_threaded: properly initialize fence unflushed tokens
Module: Mesa
Branch: master
Commit: aaebf49ebaf34e92e99608507f42f5f42335a118
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aaebf49ebaf34e92e99608507f42f5f42335a118
Author: Nicolai Hähnle
Date: Fri Nov 10 11:28:28 2017 +0100
gallium/u_threaded: properly initialize fence unflushed tokens
This got lost in a rebase but never hurt anything because we happened
to always sync in fence_finish anyway...
Reviewed-by: Marek Olšák
---
src/gallium/auxiliary/util/u_threaded_context.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_threaded_context.c
b/src/gallium/auxiliary/util/u_threaded_context.c
index d0a8ffbd11..84fbb22453 100644
--- a/src/gallium/auxiliary/util/u_threaded_context.c
+++ b/src/gallium/auxiliary/util/u_threaded_context.c
@@ -1931,7 +1931,6 @@ tc_flush(struct pipe_context *_pipe, struct
pipe_fence_handle **fence,
if (async && tc->create_fence) {
if (fence) {
- struct tc_unflushed_batch_token *token = NULL;
struct tc_batch *next = &tc->batch_slots[tc->next];
if (!next->token) {
@@ -1943,7 +1942,7 @@ tc_flush(struct pipe_context *_pipe, struct
pipe_fence_handle **fence,
next->token->tc = tc;
}
- screen->fence_reference(screen, fence, tc->create_fence(pipe, token));
+ screen->fence_reference(screen, fence, tc->create_fence(pipe,
next->token));
if (!*fence)
goto out_of_memory;
}
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Mesa (master): ddebug: fix the hang detection timeout calculation
Module: Mesa
Branch: master
Commit: f5ea8d18ff8b60dbd8864aad7128140e2085862d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f5ea8d18ff8b60dbd8864aad7128140e2085862d
Author: Nicolai Hähnle
Date: Fri Nov 10 17:13:27 2017 +0100
ddebug: fix the hang detection timeout calculation
Fixes: c9fefa062b36 ("ddebug: rewrite to always use a threaded approach")
Reviewed-by: Marek Olšák
---
src/gallium/drivers/ddebug/dd_draw.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/ddebug/dd_draw.c
b/src/gallium/drivers/ddebug/dd_draw.c
index e908410a33..c404ea0607 100644
--- a/src/gallium/drivers/ddebug/dd_draw.c
+++ b/src/gallium/drivers/ddebug/dd_draw.c
@@ -1034,10 +1034,10 @@ dd_thread_main(void *input)
/* Fences can be NULL legitimately when timeout detection is disabled. */
if ((fence &&
!screen->fence_finish(screen, NULL, fence,
- dscreen->timeout_ms * 1000*1000)) ||
+ (uint64_t)dscreen->timeout_ms * 1000*1000)) ||
(fence2 &&
!screen->fence_finish(screen, NULL, fence2,
- dscreen->timeout_ms * 1000*1000))) {
+ (uint64_t)dscreen->timeout_ms * 1000*1000))) {
mtx_lock(&dctx->mutex);
list_splice(&records, &dctx->records);
dd_report_hang(dctx);
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Mesa (master): st/mesa: use asynchronous flushes in st_finish
Module: Mesa
Branch: master
Commit: 764bd6ef96d5a3247f18c0016d57c95edd9d4102
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=764bd6ef96d5a3247f18c0016d57c95edd9d4102
Author: Nicolai Hähnle
Date: Thu Nov 9 14:34:20 2017 +0100
st/mesa: use asynchronous flushes in st_finish
With threaded gallium, the driver may currently be running in another
thread. In that case, we will execute all remaining commands in that
thread instead of syncing, which should be better for cache locality.
Reviewed-by: Andres Rodriguez
Reviewed-by: Marek Olšák
---
src/mesa/state_tracker/st_cb_flush.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/state_tracker/st_cb_flush.c
b/src/mesa/state_tracker/st_cb_flush.c
index c8452d0e6f..14bfd5a468 100644
--- a/src/mesa/state_tracker/st_cb_flush.c
+++ b/src/mesa/state_tracker/st_cb_flush.c
@@ -63,7 +63,7 @@ void st_finish( struct st_context *st )
{
struct pipe_fence_handle *fence = NULL;
- st_flush(st, &fence, 0);
+ st_flush(st, &fence, PIPE_FLUSH_ASYNC | PIPE_FLUSH_HINT_FINISH);
if(fence) {
st->pipe->screen->fence_finish(st->pipe->screen, NULL, fence,
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Mesa (master): gallium/u_threaded: avoid syncing in threaded_context_flush
Module: Mesa
Branch: master
Commit: 3f17d3c01753020ff01e8d30a25edff6ca453971
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3f17d3c01753020ff01e8d30a25edff6ca453971
Author: Nicolai Hähnle
Date: Fri Nov 10 11:15:44 2017 +0100
gallium/u_threaded: avoid syncing in threaded_context_flush
We could always do the flush asynchronously, but if we're going to wait
for a fence anyway and the driver thread is currently idle, the additional
communication overhead isn't worth it.
Reviewed-by: Marek Olšák
---
src/gallium/auxiliary/util/u_threaded_context.c | 16 +---
src/gallium/auxiliary/util/u_threaded_context.h | 3 ++-
src/gallium/drivers/radeonsi/si_fence.c | 3 ++-
3 files changed, 17 insertions(+), 5 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_threaded_context.c
b/src/gallium/auxiliary/util/u_threaded_context.c
index 84fbb22453..ffa824744e 100644
--- a/src/gallium/auxiliary/util/u_threaded_context.c
+++ b/src/gallium/auxiliary/util/u_threaded_context.c
@@ -231,13 +231,23 @@ _tc_sync(struct threaded_context *tc, MAYBE_UNUSED const
char *info, MAYBE_UNUSE
*/
void
threaded_context_flush(struct pipe_context *_pipe,
- struct tc_unflushed_batch_token *token)
+ struct tc_unflushed_batch_token *token,
+ bool prefer_async)
{
struct threaded_context *tc = threaded_context(_pipe);
/* This is called from the state-tracker / application thread. */
- if (token->tc && token->tc == tc)
- tc_sync(token->tc);
+ if (token->tc && token->tc == tc) {
+ struct tc_batch *last = &tc->batch_slots[tc->last];
+
+ /* Prefer to do the flush in the driver thread if it is already
+ * running. That should be better for cache locality.
+ */
+ if (prefer_async || !util_queue_fence_is_signalled(&last->fence))
+ tc_batch_flush(tc);
+ else
+ tc_sync(token->tc);
+ }
}
static void
diff --git a/src/gallium/auxiliary/util/u_threaded_context.h
b/src/gallium/auxiliary/util/u_threaded_context.h
index 34089561f3..53c5a7e8c4 100644
--- a/src/gallium/auxiliary/util/u_threaded_context.h
+++ b/src/gallium/auxiliary/util/u_threaded_context.h
@@ -381,7 +381,8 @@ threaded_context_create(struct pipe_context *pipe,
void
threaded_context_flush(struct pipe_context *_pipe,
- struct tc_unflushed_batch_token *token);
+ struct tc_unflushed_batch_token *token,
+ bool prefer_async);
static inline struct threaded_context *
threaded_context(struct pipe_context *pipe)
diff --git a/src/gallium/drivers/radeonsi/si_fence.c
b/src/gallium/drivers/radeonsi/si_fence.c
index 5163d652c8..9d6bcfe102 100644
--- a/src/gallium/drivers/radeonsi/si_fence.c
+++ b/src/gallium/drivers/radeonsi/si_fence.c
@@ -203,7 +203,8 @@ static boolean si_fence_finish(struct pipe_screen *screen,
* be in flight in the driver thread, so the fence
* may not be ready yet when this call returns.
*/
- threaded_context_flush(ctx, rfence->tc_token);
+ threaded_context_flush(ctx, rfence->tc_token,
+ timeout == 0);
}
if (timeout == PIPE_TIMEOUT_INFINITE) {
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Mesa (master): radeonsi: avoid syncing the driver thread in si_fence_finish
Module: Mesa
Branch: master
Commit: bc65dcab3bc48673ff6180afb036561a4b8b1119
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bc65dcab3bc48673ff6180afb036561a4b8b1119
Author: Nicolai Hähnle
Date: Fri Nov 10 10:58:10 2017 +0100
radeonsi: avoid syncing the driver thread in si_fence_finish
It is really only required when we need to flush for deferred fences.
Reviewed-by: Marek Olšák
---
src/gallium/auxiliary/util/u_threaded_context.h | 8 +++
src/gallium/drivers/radeonsi/si_fence.c | 75 +
src/gallium/drivers/radeonsi/si_hw_context.c| 3 +
3 files changed, 49 insertions(+), 37 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_threaded_context.h
b/src/gallium/auxiliary/util/u_threaded_context.h
index b2d904569e..34089561f3 100644
--- a/src/gallium/auxiliary/util/u_threaded_context.h
+++ b/src/gallium/auxiliary/util/u_threaded_context.h
@@ -407,6 +407,14 @@ threaded_transfer(struct pipe_transfer *transfer)
return (struct threaded_transfer*)transfer;
}
+static inline struct pipe_context *
+threaded_context_unwrap_unsync(struct pipe_context *pipe)
+{
+ if (!pipe || !pipe->priv)
+ return pipe;
+ return (struct pipe_context*)pipe->priv;
+}
+
static inline void
tc_unflushed_batch_token_reference(struct tc_unflushed_batch_token **dst,
struct tc_unflushed_batch_token *src)
diff --git a/src/gallium/drivers/radeonsi/si_fence.c
b/src/gallium/drivers/radeonsi/si_fence.c
index ff1800ce78..5163d652c8 100644
--- a/src/gallium/drivers/radeonsi/si_fence.c
+++ b/src/gallium/drivers/radeonsi/si_fence.c
@@ -188,12 +188,8 @@ static boolean si_fence_finish(struct pipe_screen *screen,
{
struct radeon_winsys *rws = ((struct r600_common_screen*)screen)->ws;
struct si_multi_fence *rfence = (struct si_multi_fence *)fence;
- struct r600_common_context *rctx;
int64_t abs_timeout = os_time_get_absolute_timeout(timeout);
- ctx = threaded_context_unwrap_sync(ctx);
- rctx = ctx ? (struct r600_common_context*)ctx : NULL;
-
if (!util_queue_fence_is_signalled(&rfence->ready)) {
if (!timeout)
return false;
@@ -245,41 +241,46 @@ static boolean si_fence_finish(struct pipe_screen *screen,
}
/* Flush the gfx IB if it hasn't been flushed yet. */
- if (rctx &&
- rfence->gfx_unflushed.ctx == rctx &&
- rfence->gfx_unflushed.ib_index == rctx->num_gfx_cs_flushes) {
- /* Section 4.1.2 (Signaling) of the OpenGL 4.6 (Core profile)
-* spec says:
-*
-*"If the sync object being blocked upon will not be
-* signaled in finite time (for example, by an associated
-* fence command issued previously, but not yet flushed to
-* the graphics pipeline), then ClientWaitSync may hang
-* forever. To help prevent this behavior, if
-* ClientWaitSync is called and all of the following are
-* true:
-*
-* * the SYNC_FLUSH_COMMANDS_BIT bit is set in flags,
-* * sync is unsignaled when ClientWaitSync is called,
-* * and the calls to ClientWaitSync and FenceSync were
-* issued from the same context,
-*
-* then the GL will behave as if the equivalent of Flush
-* were inserted immediately after the creation of sync."
-*
-* This means we need to flush for such fences even when we're
-* not going to wait.
-*/
- rctx->gfx.flush(rctx, timeout ? 0 : RADEON_FLUSH_ASYNC, NULL);
- rfence->gfx_unflushed.ctx = NULL;
+ if (ctx && rfence->gfx_unflushed.ctx) {
+ struct si_context *sctx;
+
+ sctx = (struct si_context *)threaded_context_unwrap_unsync(ctx);
+ if (rfence->gfx_unflushed.ctx == &sctx->b &&
+ rfence->gfx_unflushed.ib_index ==
sctx->b.num_gfx_cs_flushes) {
+ /* Section 4.1.2 (Signaling) of the OpenGL 4.6 (Core
profile)
+* spec says:
+*
+*"If the sync object being blocked upon will not be
+* signaled in finite time (for example, by an
associated
+* fence command issued previously, but not yet
flushed to
+* the graphics pipeline), then ClientWaitSync may
hang
+* forever. To help prevent this behavior, if
+* ClientWaitSync is called and all of the
following are
+* true:
+
Mesa (master): util/u_queue: really use futex-based fences
Module: Mesa
Branch: master
Commit: 81aabb20f38449973dbd9c003628986f947a9efb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=81aabb20f38449973dbd9c003628986f947a9efb
Author: Nicolai Hähnle
Date: Fri Nov 10 12:32:44 2017 +0100
util/u_queue: really use futex-based fences
The relevant define changed in the final revision of the simple mutex
patch.
Reviewed-by: Marek Olšák
---
src/util/u_queue.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/util/u_queue.h b/src/util/u_queue.h
index 57753bd31b..d49f713e6a 100644
--- a/src/util/u_queue.h
+++ b/src/util/u_queue.h
@@ -49,7 +49,7 @@ extern "C" {
#define UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY (1 << 0)
#define UTIL_QUEUE_INIT_RESIZE_IF_FULL(1 << 1)
-#if defined(__GNUC__) && defined(HAVE_FUTEX)
+#if defined(__GNUC__) && defined(HAVE_LINUX_FUTEX_H)
#define UTIL_QUEUE_FENCE_FUTEX
#else
#define UTIL_QUEUE_FENCE_STANDARD
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Mesa (master): util/u_queue: fix timeout handling in util_queue_fence_wait_timeout
Module: Mesa
Branch: master
Commit: a6e831172314f3f76d1b795209f6623e251483b8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a6e831172314f3f76d1b795209f6623e251483b8
Author: Nicolai Hähnle
Date: Mon Nov 13 14:35:50 2017 +0100
util/u_queue: fix timeout handling in util_queue_fence_wait_timeout
Fixes: e3a8013de8ca ("util/u_queue: add util_queue_fence_wait_timeout")
Reviewed-by: Marek Olšák
---
src/util/u_queue.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/util/u_queue.c b/src/util/u_queue.c
index 43c28ac6ef..dba23f9645 100644
--- a/src/util/u_queue.c
+++ b/src/util/u_queue.c
@@ -113,7 +113,7 @@ do_futex_fence_wait(struct util_queue_fence *fence,
int r = futex_wait(&fence->val, 2, timeout ? &ts : NULL);
if (timeout && r < 0) {
- if (errno == -ETIMEDOUT)
+ if (errno == ETIMEDOUT)
return false;
}
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Mesa (master): st/mesa: implement st_server_wait_sync properly
Module: Mesa
Branch: master
Commit: 2d8b82baaad43a41d076a5273ac0de3c03cc5a55
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d8b82baaad43a41d076a5273ac0de3c03cc5a55
Author: Nicolai Hähnle
Date: Thu Nov 9 14:34:19 2017 +0100
st/mesa: implement st_server_wait_sync properly
Asynchronous flushes require a proper implementation of
st_server_wait_sync, because we could have the following with
threaded Gallium:
Context 1 app Context 1 driver Context 2
- -
f = glFenceSync
glFlush
<-- app sync --> <-- app sync -->
glWaitSync(f)
.. draw calls ..
pipe_context::flush
for glFenceSync
pipe_context::flush
for glFlush
Reviewed-by: Andres Rodriguez
Reviewed-by: Marek Olšák
---
src/mesa/state_tracker/st_cb_syncobj.c | 26 --
1 file changed, 24 insertions(+), 2 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_syncobj.c
b/src/mesa/state_tracker/st_cb_syncobj.c
index 637fbe3b73..44323b4750 100644
--- a/src/mesa/state_tracker/st_cb_syncobj.c
+++ b/src/mesa/state_tracker/st_cb_syncobj.c
@@ -130,8 +130,30 @@ static void st_server_wait_sync(struct gl_context *ctx,
struct gl_sync_object *obj,
GLbitfield flags, GLuint64 timeout)
{
- /* NO-OP.
-* Neither Gallium nor DRM interfaces support blocking on the GPU. */
+ struct pipe_context *pipe = st_context(ctx)->pipe;
+ struct pipe_screen *screen = pipe->screen;
+ struct st_sync_object *so = (struct st_sync_object*)obj;
+ struct pipe_fence_handle *fence = NULL;
+
+ /* Nothing needs to be done here if the driver does not support async
+* flushes. */
+ if (!pipe->fence_server_sync)
+ return;
+
+ /* If the fence doesn't exist, assume it's signalled. */
+ mtx_lock(&so->mutex);
+ if (!so->fence) {
+ mtx_unlock(&so->mutex);
+ so->b.StatusFlag = GL_TRUE;
+ return;
+ }
+
+ /* We need a local copy of the fence pointer. */
+ screen->fence_reference(screen, &fence, so->fence);
+ mtx_unlock(&so->mutex);
+
+ pipe->fence_server_sync(pipe, fence);
+ screen->fence_reference(screen, &fence, NULL);
}
void st_init_syncobj_functions(struct dd_function_table *functions)
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Mesa (master): radeonsi: recompute the relative timeout after waiting for ready fence
Module: Mesa
Branch: master
Commit: 3db1ce01b1f33aaeceda4038487a4ce0ceb77267
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3db1ce01b1f33aaeceda4038487a4ce0ceb77267
Author: Nicolai Hähnle
Date: Mon Nov 13 14:50:17 2017 +0100
radeonsi: recompute the relative timeout after waiting for ready fence
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeonsi/si_fence.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_fence.c
b/src/gallium/drivers/radeonsi/si_fence.c
index fa80f4fd87..ff1800ce78 100644
--- a/src/gallium/drivers/radeonsi/si_fence.c
+++ b/src/gallium/drivers/radeonsi/si_fence.c
@@ -216,6 +216,11 @@ static boolean si_fence_finish(struct pipe_screen *screen,
if (!util_queue_fence_wait_timeout(&rfence->ready,
abs_timeout))
return false;
}
+
+ if (timeout && timeout != PIPE_TIMEOUT_INFINITE) {
+ int64_t time = os_time_get_nano();
+ timeout = abs_timeout > time ? abs_timeout - time : 0;
+ }
}
if (rfence->sdma) {
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Mesa (master): amd: build addrlib with C++11
Module: Mesa
Branch: master
Commit: abeded1cacb5a17a422cb3788153814ed2e01ecb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=abeded1cacb5a17a422cb3788153814ed2e01ecb
Author: Nicolai Hähnle
Date: Wed Nov 15 12:51:23 2017 +0100
amd: build addrlib with C++11
It is required for LLVM anyway.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103658
Fixes: 7f33e94e43a6 ("amd/addrlib: update to latest version")
Tested-by: Vinson Lee
Reviewed-by: Marek Olšák
---
src/amd/Makefile.addrlib.am | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/Makefile.addrlib.am b/src/amd/Makefile.addrlib.am
index 46689637f9..90dfe96344 100644
--- a/src/amd/Makefile.addrlib.am
+++ b/src/amd/Makefile.addrlib.am
@@ -33,7 +33,7 @@ addrlib_libamdgpu_addrlib_la_CPPFLAGS = \
-DBRAHMA_BUILD=1
addrlib_libamdgpu_addrlib_la_CXXFLAGS = \
- $(VISIBILITY_CXXFLAGS)
+ $(VISIBILITY_CXXFLAGS) $(CXX11_CXXFLAGS)
noinst_LTLIBRARIES += $(ADDRLIB_LIBS)
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Mesa (master): radeonsi/gfx9: fix VM fault with fetched instance divisors
Module: Mesa
Branch: master
Commit: df5ebe0c261e8d13683f2515be9ce263f5437bcd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=df5ebe0c261e8d13683f2515be9ce263f5437bcd
Author: Nicolai Hähnle
Date: Wed Nov 15 11:22:26 2017 +0100
radeonsi/gfx9: fix VM fault with fetched instance divisors
We need to account for SGPR locations in merged shaders.
This case is exercised by KHR-GL45.enhanced_layouts.vertex_attrib_locations
Fixes: 79c2e7388c7f ("radeonsi/gfx9: use SPI_SHADER_USER_DATA_COMMON")
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader.c | 13 +++--
src/gallium/drivers/radeonsi/si_shader.h | 4 +---
2 files changed, 12 insertions(+), 5 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index c1a310275c..e6b14f9205 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -5883,11 +5883,13 @@ static void si_get_vs_prolog_key(const struct
tgsi_shader_info *info,
key->vs_prolog.num_input_sgprs = num_input_sgprs;
key->vs_prolog.last_input = MAX2(1, info->num_inputs) - 1;
key->vs_prolog.as_ls = shader_out->key.as_ls;
+ key->vs_prolog.as_es = shader_out->key.as_es;
if (shader_out->selector->type == PIPE_SHADER_TESS_CTRL) {
key->vs_prolog.as_ls = 1;
key->vs_prolog.num_merged_next_stage_vgprs = 2;
} else if (shader_out->selector->type == PIPE_SHADER_GEOMETRY) {
+ key->vs_prolog.as_es = 1;
key->vs_prolog.num_merged_next_stage_vgprs = 5;
}
@@ -6768,6 +6770,8 @@ si_get_shader_part(struct si_screen *sscreen,
switch (type) {
case PIPE_SHADER_VERTEX:
+ shader.key.as_ls = key->vs_prolog.as_ls;
+ shader.key.as_es = key->vs_prolog.as_es;
break;
case PIPE_SHADER_TESS_CTRL:
assert(!prolog);
@@ -6810,10 +6814,15 @@ out:
static LLVMValueRef si_prolog_get_rw_buffers(struct si_shader_context *ctx)
{
LLVMValueRef ptr[2], list;
+ bool is_merged_shader =
+ ctx->screen->b.chip_class >= GFX9 &&
+ (ctx->type == PIPE_SHADER_TESS_CTRL ||
+ctx->type == PIPE_SHADER_GEOMETRY ||
+ctx->shader->key.as_ls || ctx->shader->key.as_es);
/* Get the pointer to rw buffers. */
- ptr[0] = LLVMGetParam(ctx->main_fn, SI_SGPR_RW_BUFFERS);
- ptr[1] = LLVMGetParam(ctx->main_fn, SI_SGPR_RW_BUFFERS_HI);
+ ptr[0] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) +
SI_SGPR_RW_BUFFERS);
+ ptr[1] = LLVMGetParam(ctx->main_fn, (is_merged_shader ? 8 : 0) +
SI_SGPR_RW_BUFFERS_HI);
list = lp_build_gather_values(&ctx->gallivm, ptr, 2);
list = LLVMBuildBitCast(ctx->ac.builder, list, ctx->i64, "");
list = LLVMBuildIntToPtr(ctx->ac.builder, list,
diff --git a/src/gallium/drivers/radeonsi/si_shader.h
b/src/gallium/drivers/radeonsi/si_shader.h
index 41851627a8..148356b87f 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -149,9 +149,6 @@ struct nir_shader;
/* SGPR user data indices */
enum {
- /* GFX9 merged shaders have RW_BUFFERS among the first 8 system SGPRs,
-* and these two are used for other purposes.
-*/
SI_SGPR_RW_BUFFERS, /* rings (& stream-out, VS only) */
SI_SGPR_RW_BUFFERS_HI,
SI_SGPR_BINDLESS_SAMPLERS_AND_IMAGES,
@@ -455,6 +452,7 @@ union si_shader_part_key {
unsignednum_merged_next_stage_vgprs:3;
unsignedlast_input:4;
unsignedas_ls:1;
+ unsignedas_es:1;
/* Prologs for monolithic shaders shouldn't set EXEC. */
unsignedis_monolithic:1;
} vs_prolog;
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Mesa (master): tgsi/exec: fix LDEXP in softpipe
Module: Mesa
Branch: master
Commit: f3fa3b0d95c712c00318ca5601433bce1b82432d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f3fa3b0d95c712c00318ca5601433bce1b82432d
Author: Nicolai Hähnle
Date: Wed Nov 15 19:34:00 2017 +0100
tgsi/exec: fix LDEXP in softpipe
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103128
Fixes: cad959d90145 ("gallium: add LDEXP TGSI instruction and corresponding
cap")
Reviewed-by: Brian Paul
---
src/gallium/auxiliary/tgsi/tgsi_exec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_exec.c
b/src/gallium/auxiliary/tgsi/tgsi_exec.c
index afed96c9b1..793c0da39a 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_exec.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_exec.c
@@ -5130,7 +5130,7 @@ exec_instruction(
break;
case TGSI_OPCODE_LDEXP:
- exec_scalar_binary(mach, inst, micro_ldexp, TGSI_EXEC_DATA_FLOAT,
TGSI_EXEC_DATA_INT);
+ exec_vector_binary(mach, inst, micro_ldexp, TGSI_EXEC_DATA_FLOAT,
TGSI_EXEC_DATA_FLOAT);
break;
case TGSI_OPCODE_COS:
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Mesa (master): threads,configure.ac,meson.build: define and use HAVE_TIMESPEC_GET
Module: Mesa
Branch: master
Commit: 2e3d0dd6c8f405f27d68b1ac35e928233bf8b89c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e3d0dd6c8f405f27d68b1ac35e928233bf8b89c
Author: Nicolai Hähnle
Date: Wed Nov 15 12:41:58 2017 +0100
threads,configure.ac,meson.build: define and use HAVE_TIMESPEC_GET
Tested with Travis and Appveyor.
v2: add HAVE_TIMESPEC_GET for non-Windows Scons builds
v3: use check_functions in Scons (Eric)
Cc: Rob Herring
Cc: Alexander von Gluck IV
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103674
Fixes: f1a364878431 ("threads: update for late C11 changes")
Reviewed-by: Eric Engestrom
Reviewed-by: Dylan Baker
Reviewed-by: Jon Turney (v2)
---
configure.ac| 1 +
include/c11/threads_posix.h | 2 +-
meson.build | 2 +-
scons/gallium.py| 3 +++
4 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/configure.ac b/configure.ac
index 411c4f6b3e..a7ae920ab9 100644
--- a/configure.ac
+++ b/configure.ac
@@ -848,6 +848,7 @@ AC_CHECK_HEADER([xlocale.h], [DEFINES="$DEFINES
-DHAVE_XLOCALE_H"])
AC_CHECK_HEADER([sys/sysctl.h], [DEFINES="$DEFINES -DHAVE_SYS_SYSCTL_H"])
AC_CHECK_FUNC([strtof], [DEFINES="$DEFINES -DHAVE_STRTOF"])
AC_CHECK_FUNC([mkostemp], [DEFINES="$DEFINES -DHAVE_MKOSTEMP"])
+AC_CHECK_FUNC([timespec_get], [DEFINES="$DEFINES -DHAVE_TIMESPEC_GET"])
AC_MSG_CHECKING([whether strtod has locale support])
AC_LINK_IFELSE([AC_LANG_SOURCE([[
diff --git a/include/c11/threads_posix.h b/include/c11/threads_posix.h
index 2d7ac1326d..45cb6075e6 100644
--- a/include/c11/threads_posix.h
+++ b/include/c11/threads_posix.h
@@ -382,7 +382,7 @@ tss_set(tss_t key, void *val)
/* 7.25.7 Time functions */
// 7.25.6.1
-#ifdef __HAIKU__
+#ifndef HAVE_TIMESPEC_GET
static inline int
timespec_get(struct timespec *ts, int base)
{
diff --git a/meson.build b/meson.build
index 1c4200705f..7fdc3c280e 100644
--- a/meson.build
+++ b/meson.build
@@ -578,7 +578,7 @@ foreach h : ['xlocale.h', 'sys/sysctl.h', 'linux/futex.h']
endif
endforeach
-foreach f : ['strtof', 'mkostemp', 'posix_memalign']
+foreach f : ['strtof', 'mkostemp', 'posix_memalign', 'timespec_get']
if cc.has_function(f)
pre_args += '-DHAVE_@0@'.format(f.to_upper())
endif
diff --git a/scons/gallium.py b/scons/gallium.py
index 94022df180..ef3b2ee81a 100755
--- a/scons/gallium.py
+++ b/scons/gallium.py
@@ -355,6 +355,9 @@ def generate(env):
if check_functions(env, ['strtod_l', 'strtof_l']):
cppdefines += ['HAVE_STRTOD_L']
+if check_functions(env, ['timespec_get']):
+cppdefines += ['HAVE_TIMESPEC_GET']
+
if platform == 'windows':
cppdefines += [
'WIN32',
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Mesa (master): util/u_queue: handle OS_TIMEOUT_INFINITE in util_queue_fence_wait_timeout
Module: Mesa
Branch: master
Commit: f53570a7a6155c42a9cc536948f26cb18dd9f32e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f53570a7a6155c42a9cc536948f26cb18dd9f32e
Author: Nicolai Hähnle
Date: Fri Nov 10 10:40:41 2017 +0100
util/u_queue: handle OS_TIMEOUT_INFINITE in util_queue_fence_wait_timeout
Fixes e.g. piglit/bin/bufferstorage-persistent read -auto
Fixes: e6dbc804a87a ("winsys/amdgpu: handle cs_add_fence_dependency for
deferred/unsubmitted fences")
Reviewed-by: Marek Olšák
---
src/util/u_queue.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/util/u_queue.h b/src/util/u_queue.h
index ec02815748..57753bd31b 100644
--- a/src/util/u_queue.h
+++ b/src/util/u_queue.h
@@ -38,6 +38,7 @@
#include "util/futex.h"
#include "util/list.h"
#include "util/macros.h"
+#include "util/os_time.h"
#include "util/u_atomic.h"
#include "util/u_thread.h"
@@ -179,6 +180,11 @@ util_queue_fence_wait_timeout(struct util_queue_fence
*fence,
if (util_queue_fence_is_signalled(fence))
return true;
+ if (abs_timeout == (int64_t)OS_TIMEOUT_INFINITE) {
+ _util_queue_fence_wait(fence);
+ return true;
+ }
+
return _util_queue_fence_wait_timeout(fence, abs_timeout);
}
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Mesa (master): gallium/u_threaded: fix end_query regression
Module: Mesa
Branch: master
Commit: ee880e91ccf06fbf7cdea35c75b7dfd83bbc02b5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ee880e91ccf06fbf7cdea35c75b7dfd83bbc02b5
Author: Nicolai Hähnle
Date: Fri Nov 10 09:59:08 2017 +0100
gallium/u_threaded: fix end_query regression
Ouch...
Fixes: 244536d3d6b4 ("gallium/u_threaded: avoid syncs for get_query_result")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103653
Reviewed-by: Marek Olšák
---
src/gallium/auxiliary/util/u_threaded_context.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_threaded_context.c
b/src/gallium/auxiliary/util/u_threaded_context.c
index e1ec47e4e0..b05cffd754 100644
--- a/src/gallium/auxiliary/util/u_threaded_context.c
+++ b/src/gallium/auxiliary/util/u_threaded_context.c
@@ -395,8 +395,6 @@ tc_end_query(struct pipe_context *_pipe, struct pipe_query
*query)
struct tc_end_query_payload *payload =
tc_add_struct_typed_call(tc, TC_CALL_end_query, tc_end_query_payload);
- tc_add_small_call(tc, TC_CALL_end_query);
-
payload->tc = tc;
payload->query = query;
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Mesa (master): util/u_thread: fix compilation on Mac OS
Module: Mesa
Branch: master
Commit: e7972b89432600ebe38e6eb67b9b65c1f34dfdc1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e7972b89432600ebe38e6eb67b9b65c1f34dfdc1
Author: Nicolai Hähnle
Date: Fri Nov 10 12:36:16 2017 +0100
util/u_thread: fix compilation on Mac OS
Apparently, it doesn't have pthread barriers.
p_config.h (which was originally used to guard this code) uses the
__APPLE__ macro to detect Mac OS.
Fixes: f0d3a4de75 ("util: move pipe_barrier into src/util and rename to
util_barrier")
Cc: Roland Scheidegger
Reviewed-by: Marek Olšák
Reviewed-by: Brian Paul
---
src/util/u_thread.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/util/u_thread.h b/src/util/u_thread.h
index e484d8aa74..26cc0b0934 100644
--- a/src/util/u_thread.h
+++ b/src/util/u_thread.h
@@ -104,7 +104,7 @@ static inline bool u_thread_is_self(thrd_t thread)
* util_barrier
*/
-#if defined(HAVE_PTHREAD)
+#if defined(HAVE_PTHREAD) && !defined(__APPLE__)
typedef pthread_barrier_t util_barrier;
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Mesa (master): anv: fix build failure
Module: Mesa
Branch: master
Commit: ffc20606165fc0287214356089830d72a50d5d73
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ffc20606165fc0287214356089830d72a50d5d73
Author: Nicolai Hähnle
Date: Thu Nov 9 14:49:19 2017 +0100
anv: fix build failure
Fixes: e3a8013de8ca ("util/u_queue: add util_queue_fence_wait_timeout")
---
src/intel/vulkan/anv_allocator.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/vulkan/anv_allocator.c b/src/intel/vulkan/anv_allocator.c
index 4d8eea641a..ce37ccb488 100644
--- a/src/intel/vulkan/anv_allocator.c
+++ b/src/intel/vulkan/anv_allocator.c
@@ -565,7 +565,7 @@ anv_block_pool_alloc_new(struct anv_block_pool *pool,
futex_wake(&pool_state->end, INT_MAX);
return state.next;
} else {
- futex_wait(&pool_state->end, state.end);
+ futex_wait(&pool_state->end, state.end, NULL);
continue;
}
}
@@ -662,7 +662,7 @@ anv_fixed_size_state_pool_alloc_new(struct
anv_fixed_size_state_pool *pool,
futex_wake(&pool->block.end, INT_MAX);
return offset;
} else {
- futex_wait(&pool->block.end, block.end);
+ futex_wait(&pool->block.end, block.end, NULL);
goto restart;
}
}
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Mesa (master): mesa: flush and wait after creating a fallback texture
Module: Mesa Branch: master Commit: cc78d770439cfc1ae8ec0c802e5fcb5eae25979f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc78d770439cfc1ae8ec0c802e5fcb5eae25979f Author: Nicolai Hähnle Date: Sun Oct 22 17:39:04 2017 +0200 mesa: flush and wait after creating a fallback texture Fixes non-deterministic failures in dEQP-EGL.functional.sharing.gles2.multithread.simple_egl_sync.images.texture_source.teximage2d_render and others in dEQP-EGL.functional.sharing.gles2.multithread.* Reviewed-by: Marek Olšák --- src/mesa/main/texobj.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/mesa/main/texobj.c b/src/mesa/main/texobj.c index 71c6f81323..02c4767788 100644 --- a/src/mesa/main/texobj.c +++ b/src/mesa/main/texobj.c @@ -1051,6 +1051,11 @@ _mesa_get_fallback_texture(struct gl_context *ctx, gl_texture_index tex) assert(texObj->_MipmapComplete); ctx->Shared->FallbackTex[tex] = texObj; + + /* Complete the driver's operation in case another context will also + * use the same fallback texture. */ + if (ctx->Driver.Finish) + ctx->Driver.Finish(ctx); } return ctx->Shared->FallbackTex[tex]; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): st/mesa: remove redundant flushes from st_flush
Module: Mesa
Branch: master
Commit: fbda7958ff21ab8595ca7d601df6cf033a7eabf7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fbda7958ff21ab8595ca7d601df6cf033a7eabf7
Author: Nicolai Hähnle
Date: Sun Oct 22 17:39:02 2017 +0200
st/mesa: remove redundant flushes from st_flush
st_flush should flush state tracker-internal state and the pipe, but
not mesa/main state. Of the four callers:
- glFlush/glFinish already call FLUSH_{VERTICES,STATE}.
- st_vdpau doesn't need to call them.
- st_manager will now call them explicitly.
Reviewed-by: Marek Olšák
---
src/mesa/state_tracker/st_cb_flush.c | 3 ---
src/mesa/state_tracker/st_manager.c | 3 +++
src/mesa/state_tracker/st_vdpau.c| 3 +++
3 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_flush.c
b/src/mesa/state_tracker/st_cb_flush.c
index d9ec0a846a..c8452d0e6f 100644
--- a/src/mesa/state_tracker/st_cb_flush.c
+++ b/src/mesa/state_tracker/st_cb_flush.c
@@ -50,9 +50,6 @@ void st_flush(struct st_context *st,
struct pipe_fence_handle **fence,
unsigned flags)
{
- FLUSH_VERTICES(st->ctx, 0);
- FLUSH_CURRENT(st->ctx, 0);
-
st_flush_bitmap_cache(st);
st->pipe->flush(st->pipe, fence, flags);
diff --git a/src/mesa/state_tracker/st_manager.c
b/src/mesa/state_tracker/st_manager.c
index d27727ae8f..953f7156c9 100644
--- a/src/mesa/state_tracker/st_manager.c
+++ b/src/mesa/state_tracker/st_manager.c
@@ -45,6 +45,7 @@
#include "st_debug.h"
#include "st_extensions.h"
#include "st_format.h"
+#include "st_cb_bitmap.h"
#include "st_cb_fbo.h"
#include "st_cb_flush.h"
#include "st_manager.h"
@@ -635,6 +636,8 @@ st_context_flush(struct st_context_iface *stctxi, unsigned
flags,
pipe_flags |= PIPE_FLUSH_END_OF_FRAME;
}
+ FLUSH_VERTICES(st->ctx, 0);
+ FLUSH_CURRENT(st->ctx, 0);
st_flush(st, fence, pipe_flags);
if ((flags & ST_FLUSH_WAIT) && fence && *fence) {
diff --git a/src/mesa/state_tracker/st_vdpau.c
b/src/mesa/state_tracker/st_vdpau.c
index 19611e719a..e0126cc03d 100644
--- a/src/mesa/state_tracker/st_vdpau.c
+++ b/src/mesa/state_tracker/st_vdpau.c
@@ -262,6 +262,9 @@ st_vdpau_unmap_surface(struct gl_context *ctx, GLenum
target, GLenum access,
_mesa_dirty_texobj(ctx, texObj);
+ /* NV_vdpau_interop does not specify an explicit synchronization mechanism
+* between the GL and VDPAU contexts. Provide automatic synchronization
here.
+*/
st_flush(st, NULL, 0);
}
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Mesa (master): mesa: increase MaxServerWaitTimeout
Module: Mesa Branch: master Commit: 46444613cfc46e71f3b875b9a202e0f60ba79cfd URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=46444613cfc46e71f3b875b9a202e0f60ba79cfd Author: Nicolai Hähnle Date: Sun Oct 22 17:39:03 2017 +0200 mesa: increase MaxServerWaitTimeout The current value was introduced in commit a27180d0d8666, which claims that it represents ~1.11 years. However, it is interpreted in nanoseconds, so it actually only represents ~9.8 hours. That seems a bit short. Use the largest value consistent with both int32 and int64. It corresponds to ~292 years in nanoseconds. Reviewed-by: Kenneth Graunke Reviewed-by: Marek Olšák --- src/mesa/main/context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c index 6d24b93c19..61099eb39f 100644 --- a/src/mesa/main/context.c +++ b/src/mesa/main/context.c @@ -654,7 +654,7 @@ _mesa_init_constants(struct gl_constants *consts, gl_api api) consts->UniformBooleanTrue = FLOAT_AS_UNION(1.0f).u; /* GL_ARB_sync */ - consts->MaxServerWaitTimeout = 0x1fff7fffULL; + consts->MaxServerWaitTimeout = 0x7fff7fffULL; /* GL_EXT_provoking_vertex */ consts->QuadsFollowProvokingVertexConvention = GL_TRUE; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): st/dri: use stapi flush instead of pipe flush when creating fences
Module: Mesa
Branch: master
Commit: 884a0b2a9e55d4c1ca39475b50d9af598d7d7280
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=884a0b2a9e55d4c1ca39475b50d9af598d7d7280
Author: Nicolai Hähnle
Date: Sun Oct 22 17:38:37 2017 +0200
st/dri: use stapi flush instead of pipe flush when creating fences
There may be pending operations (e.g. vertices) that need to be flushed
by the state tracker.
Found by inspection.
Reviewed-by: Marek Olšák
---
src/gallium/state_trackers/dri/dri_helpers.c | 11 ++-
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/src/gallium/state_trackers/dri/dri_helpers.c
b/src/gallium/state_trackers/dri/dri_helpers.c
index 06309d8f0c..a9213eca19 100644
--- a/src/gallium/state_trackers/dri/dri_helpers.c
+++ b/src/gallium/state_trackers/dri/dri_helpers.c
@@ -90,13 +90,13 @@ static unsigned dri2_fence_get_caps(__DRIscreen *_screen)
static void *
dri2_create_fence(__DRIcontext *_ctx)
{
- struct pipe_context *ctx = dri_context(_ctx)->st->pipe;
+ struct st_context_iface *stapi = dri_context(_ctx)->st;
struct dri2_fence *fence = CALLOC_STRUCT(dri2_fence);
if (!fence)
return NULL;
- ctx->flush(ctx, &fence->pipe_fence, 0);
+ stapi->flush(stapi, 0, &fence->pipe_fence);
if (!fence->pipe_fence) {
FREE(fence);
@@ -110,13 +110,14 @@ dri2_create_fence(__DRIcontext *_ctx)
static void *
dri2_create_fence_fd(__DRIcontext *_ctx, int fd)
{
- struct pipe_context *ctx = dri_context(_ctx)->st->pipe;
+ struct st_context_iface *stapi = dri_context(_ctx)->st;
+ struct pipe_context *ctx = stapi->pipe;
struct dri2_fence *fence = CALLOC_STRUCT(dri2_fence);
if (fd == -1) {
/* exporting driver created fence, flush: */
- ctx->flush(ctx, &fence->pipe_fence,
- PIPE_FLUSH_DEFERRED | PIPE_FLUSH_FENCE_FD);
+ stapi->flush(stapi, PIPE_FLUSH_DEFERRED | PIPE_FLUSH_FENCE_FD,
+ &fence->pipe_fence);
} else {
/* importing a foreign fence fd: */
ctx->create_fence_fd(ctx, &fence->pipe_fence, fd);
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Mesa (master): 43 new commits
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b921da3b74d71598c47da2bc46e445e3813d7933
Author: Nicolai Hähnle
Date: Sun Oct 22 17:39:05 2017 +0200
radeonsi: use a threaded context even for debug contexts
Reviewed-by: Marek Olšák
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a6d9e087a2171ae4d0f2ac2697ba4042fbad4c1
Author: Nicolai Hähnle
Date: Sun Oct 22 17:39:05 2017 +0200
radeonsi: record and dump time of flush
Reviewed-by: Marek Olšák
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b07569ad8b7bbe6ea33c984013a2f2607cd7ddaf
Author: Nicolai Hähnle
Date: Sun Oct 22 17:39:01 2017 +0200
ddebug: optionally handle transfer commands like draws
Transfer commands can have associated GPU operations.
Enabled by passing GALLIUM_DDEBUG=transfers.
Reviewed-by: Marek Olšák
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=18fd2a859de51353187f993ea2852bebe1ea5734
Author: Nicolai Hähnle
Date: Sun Oct 22 17:39:01 2017 +0200
ddebug: dump context and before/after times of draws
Reviewed-by: Marek Olšák
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ba2f2b6f2aa05dab01389cf27a5001d0d43adcb4
Author: Nicolai Hähnle
Date: Sun Oct 22 17:39:00 2017 +0200
ddebug: generalize print_named_xxx via a PRINT_NAMED macro
Reviewed-by: Marek Olšák
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c9fefa062b369056eb4c3ef82b529b0acc4cc88a
Author: Nicolai Hähnle
Date: Sun Oct 22 17:38:59 2017 +0200
ddebug: rewrite to always use a threaded approach
This patch has multiple goals:
1. Off-load the writing of records in 'always' mode to another thread
for performance.
2. Allow using ddebug with threaded contexts. This really forces us to
move some of the "after_draw" handling into another thread.
3. Simplify the different modes of ddebug, both in the code and in
the user interface, i.e. GALLIUM_DDEBUG. In particular, there's
no 'pipelined' anymore, since we're always pipelined; and 'noflush'
is replaced by 'flush', since we no longer flush by default.
4. Fix the fences in pipelining mode. They previously relied on writes
via pipe_context::clear_buffer. However, on radeonsi, those could
(quite reasonably) end up in the SDMA buffer. So we use the newly
added PIPE_FLUSH_{TOP,BOTTOM}_OF_PIPE fences instead.
5. Improve pipelined mode overall, using the finer grained information
provided by the new fences.
Overall, the result is that pipelined mode should be more useful, and
using ddebug in default mode is much less invasive, in the sense that
it changes the overall driver behavior less (which is kind of crucial
for a driver debugging tool).
An example of the new hang debug output:
Gallium debugger active.
Hang detection timeout is 1000ms.
GPU hang detected, collecting information...
Draw # driver prev BOP TOP BOP dump file
-
2 YES YESYES NO
/home/nha/ddebug_dumps/shader_runner_19919_
3 YES NO YES NO
/home/nha/ddebug_dumps/shader_runner_19919_0001
4 YES NO YES NO
/home/nha/ddebug_dumps/shader_runner_19919_0002
5 YES NO YES NO
/home/nha/ddebug_dumps/shader_runner_19919_0003
Done.
We can see that there were almost certainly 4 draws in flight when
the hang happened: the top-of-pipe fence was signaled for all 4 draws,
the bottom-of-pipe fence for none of them. In virtually all cases,
we'd expect the first draw in the list to be at fault, but due to the
GPU parallelism, it's possible (though highly unlikely) that one of
the later draws causes a component to get stuck in a way that prevents
the earlier draws from making progress as well.
(In the above example, there were actually only 3 draws truly in flight:
the last draw is a blit that waits for the earlier draws; however, its
top-of-pipe fence is emitted before the cache flush and wait, and so
the fact that the draw hasn't truly started yet can only be seen from a
closer inspection of GPU state.)
Acked-by: Marek Olšák
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e8bb8758ddfa884b55abf8648af9cb7239bc1f66
Author: Nicolai Hähnle
Date: Sun Oct 22 17:38:58 2017 +0200
ddebug: use an atomic increment when numbering files
Reviewed-by: Marek Olšák
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6710fe874cce4c01d48279e25210279a06c7543
Author: Nicolai Hähnle
Date: Sun Oct 22 17:38:58 2017 +0200
dd/util: extract dd_get_debug_filename_and_mkdir
Reviewed-
Mesa (master): glsl: allow any l-value of an input variable as interpolant in interpolateAt*
Module: Mesa
Branch: master
Commit: 4f42450b86ea30f9228309e02ca68755c389866f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f42450b86ea30f9228309e02ca68755c389866f
Author: Nicolai Hähnle
Date: Wed Jun 14 12:43:10 2017 +0200
glsl: allow any l-value of an input variable as interpolant in interpolateAt*
The intended rule has been clarified in GLSL 4.60, Section 8.13.2
(Interpolation Functions):
"For all of the interpolation functions, interpolant must be an l-value
from an in declaration; this can include a variable, a block or
structure member, an array element, or some combination of these.
Component selection operators (e.g., .xy) may be used when specifying
interpolant."
For members of interface blocks, var->data.must_be_shader_input must be
determined on-the-fly after lowering interface blocks, since we don't want
to disable varying packing for an entire block just because one input in it
is used in interpolateAt*.
v2: keep setting must_be_shader_input in ast_function (Ian)
v3: follow the relaxed rule of GLSL 4.60
v4: only apply the relaxed rules to desktop GL
(the ES WG decided that the relaxed rules may apply in a future version
but not retroactively; see also
dEQP-GLES31.functional.shaders.multisample_interpolation.interpolate_at_centroid.negative.*)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101378
Reviewed-by: Ian Romanick (v1)
Reviewed-by: Timothy Arceri
---
src/compiler/glsl/ast_function.cpp | 19 ++-
src/compiler/glsl/lower_named_interface_blocks.cpp | 18 ++
2 files changed, 32 insertions(+), 5 deletions(-)
diff --git a/src/compiler/glsl/ast_function.cpp
b/src/compiler/glsl/ast_function.cpp
index 46a61e46fd..d1596c272e 100644
--- a/src/compiler/glsl/ast_function.cpp
+++ b/src/compiler/glsl/ast_function.cpp
@@ -227,19 +227,28 @@ verify_parameter_modes(_mesa_glsl_parse_state *state,
val = ((ir_swizzle *)val)->val;
}
- while (val->ir_type == ir_type_dereference_array) {
-val = ((ir_dereference_array *)val)->array;
+ for (;;) {
+if (val->ir_type == ir_type_dereference_array) {
+ val = ((ir_dereference_array *)val)->array;
+} else if (val->ir_type == ir_type_dereference_record &&
+ !state->es_shader) {
+ val = ((ir_dereference_record *)val)->record;
+} else
+ break;
}
- if (!val->as_dereference_variable() ||
- val->variable_referenced()->data.mode != ir_var_shader_in) {
+ ir_variable *var = NULL;
+ if (const ir_dereference_variable *deref_var =
val->as_dereference_variable())
+var = deref_var->variable_referenced();
+
+ if (!var || var->data.mode != ir_var_shader_in) {
_mesa_glsl_error(&loc, state,
"parameter `%s` must be a shader input",
formal->name);
return false;
}
- val->variable_referenced()->data.must_be_shader_input = 1;
+ var->data.must_be_shader_input = 1;
}
/* Verify that 'out' and 'inout' actual parameters are lvalues. */
diff --git a/src/compiler/glsl/lower_named_interface_blocks.cpp
b/src/compiler/glsl/lower_named_interface_blocks.cpp
index 064694128b..136352a131 100644
--- a/src/compiler/glsl/lower_named_interface_blocks.cpp
+++ b/src/compiler/glsl/lower_named_interface_blocks.cpp
@@ -115,6 +115,7 @@ public:
void run(exec_list *instructions);
virtual ir_visitor_status visit_leave(ir_assignment *);
+ virtual ir_visitor_status visit_leave(ir_expression *);
virtual void handle_rvalue(ir_rvalue **rvalue);
};
@@ -238,6 +239,23 @@
flatten_named_interface_blocks_declarations::visit_leave(ir_assignment *ir)
return rvalue_visit(ir);
}
+ir_visitor_status
+flatten_named_interface_blocks_declarations::visit_leave(ir_expression *ir)
+{
+ ir_visitor_status status = rvalue_visit(ir);
+
+ if (ir->operation == ir_unop_interpolate_at_centroid ||
+ ir->operation == ir_binop_interpolate_at_offset ||
+ ir->operation == ir_binop_interpolate_at_sample) {
+ const ir_rvalue *val = ir->operands[0];
+
+ /* This disables varying packing for this input. */
+ val->variable_referenced()->data.must_be_shader_input = 1;
+ }
+
+ return status;
+}
+
void
flatten_named_interface_blocks_declarations::handle_rvalue(ir_rvalue **rvalue)
{
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Mesa (master): glsl: fix interpolateAtXxx(some_vec[idx], ...) with dynamic idx
Module: Mesa
Branch: master
Commit: ca63a5ed3e9efb2bd645b425f7393089f4e132a6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ca63a5ed3e9efb2bd645b425f7393089f4e132a6
Author: Nicolai Hähnle
Date: Tue Aug 1 12:44:34 2017 +0200
glsl: fix interpolateAtXxx(some_vec[idx], ...) with dynamic idx
The dynamic index of a vector (not array!) is lowered to a sequence of
conditional assignments. However, the interpolate_at_* expressions
require that the interpolant is an l-value of a shader input.
So instead of doing conditional assignments of parts of the shader input
and then interpolating that (which is nonsensical), we interpolate the
entire shader input and then do conditional assignments of the interpolated
result.
Reviewed-by: Timothy Arceri
---
.../glsl/lower_vec_index_to_cond_assign.cpp| 31 +-
1 file changed, 30 insertions(+), 1 deletion(-)
diff --git a/src/compiler/glsl/lower_vec_index_to_cond_assign.cpp
b/src/compiler/glsl/lower_vec_index_to_cond_assign.cpp
index a26253998e..8924426660 100644
--- a/src/compiler/glsl/lower_vec_index_to_cond_assign.cpp
+++ b/src/compiler/glsl/lower_vec_index_to_cond_assign.cpp
@@ -128,7 +128,36 @@
ir_vec_index_to_cond_assign_visitor::convert_vector_extract_to_cond_assign(ir_rv
{
ir_expression *const expr = ir->as_expression();
- if (expr == NULL || expr->operation != ir_binop_vector_extract)
+ if (expr == NULL)
+ return ir;
+
+ if (expr->operation == ir_unop_interpolate_at_centroid ||
+ expr->operation == ir_binop_interpolate_at_offset ||
+ expr->operation == ir_binop_interpolate_at_sample) {
+ /* Lower interpolateAtXxx(some_vec[idx], ...) to
+ * interpolateAtXxx(some_vec, ...)[idx] before lowering to conditional
+ * assignments, to maintain the rule that the interpolant is an l-value
+ * referring to a (part of a) shader input.
+ *
+ * This is required when idx is dynamic (otherwise it gets lowered to
+ * a swizzle).
+ */
+ ir_expression *const interpolant = expr->operands[0]->as_expression();
+ if (!interpolant || interpolant->operation != ir_binop_vector_extract)
+ return ir;
+
+ ir_rvalue *vec_input = interpolant->operands[0];
+ ir_expression *const vec_interpolate =
+ new(base_ir) ir_expression(expr->operation, vec_input->type,
+vec_input, expr->operands[1]);
+
+ return convert_vec_index_to_cond_assign(ralloc_parent(ir),
+ vec_interpolate,
+ interpolant->operands[1],
+ ir->type);
+ }
+
+ if (expr->operation != ir_binop_vector_extract)
return ir;
return convert_vec_index_to_cond_assign(ralloc_parent(ir),
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Mesa (master): amd/common/gfx9: workaround DCC corruption more conservatively
Module: Mesa
Branch: master
Commit: f9ccfda9bc8166f833fdb64adf1eca5b8ee69251
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9ccfda9bc8166f833fdb64adf1eca5b8ee69251
Author: Nicolai Hähnle
Date: Thu Oct 12 11:21:26 2017 +0200
amd/common/gfx9: workaround DCC corruption more conservatively
Fixes KHR-GL45.texture_swizzle.smoke and others on Vega.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102809
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Marek Olšák
---
src/amd/common/ac_surface.c | 32 +---
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index f956c14a10..ec37d37698 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -927,9 +927,11 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
in->numSamples == 1) {
ADDR2_COMPUTE_DCCINFO_INPUT din = {0};
ADDR2_COMPUTE_DCCINFO_OUTPUT dout = {0};
+ ADDR2_META_MIP_INFO
meta_mip_info[RADEON_SURF_MAX_LEVELS] = {};
din.size = sizeof(ADDR2_COMPUTE_DCCINFO_INPUT);
dout.size = sizeof(ADDR2_COMPUTE_DCCINFO_OUTPUT);
+ dout.pMipInfo = meta_mip_info;
din.dccKeyFlags.pipeAligned = 1;
din.dccKeyFlags.rbAligned = 1;
@@ -955,21 +957,37 @@ static int gfx9_compute_miptree(ADDR_HANDLE addrlib,
surf->dcc_alignment = dout.dccRamBaseAlign;
surf->num_dcc_levels = in->numMipLevels;
- /* Disable DCC for the smallest levels. It seems to be
-* required for DCC readability between CB and shaders
-* when TC L2 isn't flushed. This was guessed.
+ /* Disable DCC for levels that are in the mip tail.
+*
+* There are two issues that this is intended to
+* address:
+*
+* 1. Multiple mip levels may share a cache line. This
+*can lead to corruption when switching between
+*rendering to different mip levels because the
+*RBs don't maintain coherency.
+*
+* 2. Texturing with metadata after rendering sometimes
+*fails with corruption, probably for a similar
+*reason.
+*
+* Working around these issues for all levels in the
+* mip tail may be overly conservative, but it's what
+* Vulkan does.
*
* Alternative solutions that also work but are worse:
-* - Disable DCC.
+* - Disable DCC entirely.
* - Flush TC L2 after rendering.
*/
- for (unsigned i = 1; i < in->numMipLevels; i++) {
- if (mip_info[i].pitch *
- mip_info[i].height * surf->bpe < 1024) {
+ for (unsigned i = 0; i < in->numMipLevels; i++) {
+ if (meta_mip_info[i].inMiptail) {
surf->num_dcc_levels = i;
break;
}
}
+
+ if (!surf->num_dcc_levels)
+ surf->dcc_size = 0;
}
/* FMASK */
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Mesa (master): radeonsi: add support for PIPE_FORMAT_{X1, A1}R5G5B5_UNORM
Module: Mesa
Branch: master
Commit: bc2d87410169c0f0eee19070ea8167d481861eb4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bc2d87410169c0f0eee19070ea8167d481861eb4
Author: Nicolai Hähnle
Date: Tue Oct 3 15:02:22 2017 +0200
radeonsi: add support for PIPE_FORMAT_{X1,A1}R5G5B5_UNORM
Fixes dEQP-EGL.functional.image.modify.tex_rgb5_a1_tex_subimage_rgba8
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeonsi/si_state.c | 8
1 file changed, 8 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 4bfd5272db..ae45e1a6b2 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1506,6 +1506,8 @@ static uint32_t si_translate_colorformat(enum pipe_format
format)
}
} else if (HAS_SIZE(5,5,5,1)) {
return V_028C70_COLOR_1_5_5_5;
+ } else if (HAS_SIZE(1,5,5,5)) {
+ return V_028C70_COLOR_5_5_5_1;
} else if (HAS_SIZE(10,10,10,2)) {
return V_028C70_COLOR_2_10_10_10;
}
@@ -1764,6 +1766,12 @@ static uint32_t si_translate_texformat(struct
pipe_screen *screen,
desc->channel[3].size == 1) {
return V_008F14_IMG_DATA_FORMAT_1_5_5_5;
}
+ if (desc->channel[0].size == 1 &&
+ desc->channel[1].size == 5 &&
+ desc->channel[2].size == 5 &&
+ desc->channel[3].size == 5) {
+ return V_008F14_IMG_DATA_FORMAT_5_5_5_1;
+ }
if (desc->channel[0].size == 10 &&
desc->channel[1].size == 10 &&
desc->channel[2].size == 10 &&
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Mesa (master): gallium: add tests for PIPE_FORMAT_{X1, A1}B5G5R5_UNORM formats
Module: Mesa
Branch: master
Commit: 9f55da130e8aedb507edbf0674d1e5b4e1c101ad
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f55da130e8aedb507edbf0674d1e5b4e1c101ad
Author: Nicolai Hähnle
Date: Tue Oct 3 15:00:24 2017 +0200
gallium: add tests for PIPE_FORMAT_{X1,A1}B5G5R5_UNORM formats
This is a left-over from my version of adding the new format
after rebasing on Eric's version.
Reviewed-by: Marek Olšák
---
src/gallium/auxiliary/util/u_format_tests.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/gallium/auxiliary/util/u_format_tests.c
b/src/gallium/auxiliary/util/u_format_tests.c
index dbf072a01e..9c9a5838d1 100644
--- a/src/gallium/auxiliary/util/u_format_tests.c
+++ b/src/gallium/auxiliary/util/u_format_tests.c
@@ -170,6 +170,19 @@ util_format_test_cases[] =
{PIPE_FORMAT_B5G5R5A1_UNORM, PACKED_1x16(0x), PACKED_1x16(0x8000),
UNPACKED_1x1(0.0, 0.0, 0.0, 1.0)},
{PIPE_FORMAT_B5G5R5A1_UNORM, PACKED_1x16(0x), PACKED_1x16(0x),
UNPACKED_1x1(1.0, 1.0, 1.0, 1.0)},
+ {PIPE_FORMAT_X1B5G5R5_UNORM, PACKED_1x16(0xfffe), PACKED_1x16(0x),
UNPACKED_1x1(0.0, 0.0, 0.0, 1.0)},
+ {PIPE_FORMAT_X1B5G5R5_UNORM, PACKED_1x16(0xfffe), PACKED_1x16(0x003e),
UNPACKED_1x1(0.0, 0.0, 1.0, 1.0)},
+ {PIPE_FORMAT_X1B5G5R5_UNORM, PACKED_1x16(0xfffe), PACKED_1x16(0x07c0),
UNPACKED_1x1(0.0, 1.0, 0.0, 1.0)},
+ {PIPE_FORMAT_X1B5G5R5_UNORM, PACKED_1x16(0xfffe), PACKED_1x16(0xf800),
UNPACKED_1x1(1.0, 0.0, 0.0, 1.0)},
+ {PIPE_FORMAT_X1B5G5R5_UNORM, PACKED_1x16(0xfffe), PACKED_1x16(0xfffe),
UNPACKED_1x1(1.0, 1.0, 1.0, 1.0)},
+
+ {PIPE_FORMAT_A1B5G5R5_UNORM, PACKED_1x16(0x), PACKED_1x16(0x),
UNPACKED_1x1(0.0, 0.0, 0.0, 0.0)},
+ {PIPE_FORMAT_A1B5G5R5_UNORM, PACKED_1x16(0x), PACKED_1x16(0x003e),
UNPACKED_1x1(0.0, 0.0, 1.0, 0.0)},
+ {PIPE_FORMAT_A1B5G5R5_UNORM, PACKED_1x16(0x), PACKED_1x16(0x07c0),
UNPACKED_1x1(0.0, 1.0, 0.0, 0.0)},
+ {PIPE_FORMAT_A1B5G5R5_UNORM, PACKED_1x16(0x), PACKED_1x16(0xf800),
UNPACKED_1x1(1.0, 0.0, 0.0, 0.0)},
+ {PIPE_FORMAT_A1B5G5R5_UNORM, PACKED_1x16(0x), PACKED_1x16(0x0001),
UNPACKED_1x1(0.0, 0.0, 0.0, 1.0)},
+ {PIPE_FORMAT_A1B5G5R5_UNORM, PACKED_1x16(0x), PACKED_1x16(0x),
UNPACKED_1x1(1.0, 1.0, 1.0, 1.0)},
+
{PIPE_FORMAT_B4G4R4X4_UNORM, PACKED_1x16(0x0fff), PACKED_1x16(0x),
UNPACKED_1x1(0.0, 0.0, 0.0, 1.0)},
{PIPE_FORMAT_B4G4R4X4_UNORM, PACKED_1x16(0x0fff), PACKED_1x16(0x000f),
UNPACKED_1x1(0.0, 0.0, 1.0, 1.0)},
{PIPE_FORMAT_B4G4R4X4_UNORM, PACKED_1x16(0x0fff), PACKED_1x16(0x00f0),
UNPACKED_1x1(0.0, 1.0, 0.0, 1.0)},
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Mesa (master): st/mesa: store state that affects sampler views per context
Module: Mesa
Branch: master
Commit: bce3055c69b9fddf951fa1d80fc5894570fc00a3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bce3055c69b9fddf951fa1d80fc5894570fc00a3
Author: Nicolai Hähnle
Date: Thu Oct 5 14:08:04 2017 +0200
st/mesa: store state that affects sampler views per context
This fixes sequences like:
1. Context 1 samples from texture with sRGB decode enabled
2. Context 2 samples from texture with sRGB decode disabled
3. Context 1 samples from texture with sRGB decode disabled
Previously, step 3 would see the prev_sRGBDecode value from context 2
and would incorrectly use the old sampler view with sRGB decode enabled.
Reviewed-by: Marek Olšák
---
src/mesa/state_tracker/st_atom_sampler.c | 4 +--
src/mesa/state_tracker/st_atom_texture.c | 12
src/mesa/state_tracker/st_sampler_view.c | 49 ++--
src/mesa/state_tracker/st_texture.h | 20 +
4 files changed, 44 insertions(+), 41 deletions(-)
diff --git a/src/mesa/state_tracker/st_atom_sampler.c
b/src/mesa/state_tracker/st_atom_sampler.c
index d9e8de3c9e..ff3f49fa4e 100644
--- a/src/mesa/state_tracker/st_atom_sampler.c
+++ b/src/mesa/state_tracker/st_atom_sampler.c
@@ -170,8 +170,8 @@ st_convert_sampler(const struct st_context *st,
swizzle is per-texture, not per context. */
/* XXX: clean that up to not use the sampler view at all */
for (unsigned i = 0; i < stobj->num_sampler_views; ++i) {
-if (stobj->sampler_views[i]) {
- sv = stobj->sampler_views[i];
+if (stobj->sampler_views[i].view) {
+ sv = stobj->sampler_views[i].view;
break;
}
}
diff --git a/src/mesa/state_tracker/st_atom_texture.c
b/src/mesa/state_tracker/st_atom_texture.c
index 81bf62908f..90828bb4cf 100644
--- a/src/mesa/state_tracker/st_atom_texture.c
+++ b/src/mesa/state_tracker/st_atom_texture.c
@@ -84,18 +84,6 @@ st_update_single_texture(struct st_context *st,
return;
}
- /* Check a few pieces of state outside the texture object to see if we
-* need to force revalidation.
-*/
- if (stObj->prev_glsl130_or_later != glsl130_or_later ||
- stObj->prev_sRGBDecode != samp->sRGBDecode) {
-
- st_texture_release_all_sampler_views(st, stObj);
-
- stObj->prev_glsl130_or_later = glsl130_or_later;
- stObj->prev_sRGBDecode = samp->sRGBDecode;
- }
-
if (texObj->TargetIndex == TEXTURE_EXTERNAL_INDEX &&
stObj->pt->screen->resource_changed)
stObj->pt->screen->resource_changed(stObj->pt->screen, stObj->pt);
diff --git a/src/mesa/state_tracker/st_sampler_view.c
b/src/mesa/state_tracker/st_sampler_view.c
index 014b4d2678..99c4f74ae0 100644
--- a/src/mesa/state_tracker/st_sampler_view.c
+++ b/src/mesa/state_tracker/st_sampler_view.c
@@ -47,19 +47,19 @@
* If none is found an empty slot is initialized with a
* template and returned instead.
*/
-static struct pipe_sampler_view **
+static struct st_sampler_view *
st_texture_get_sampler_view(struct st_context *st,
struct st_texture_object *stObj)
{
- struct pipe_sampler_view **free = NULL;
+ struct st_sampler_view *free = NULL;
GLuint i;
for (i = 0; i < stObj->num_sampler_views; ++i) {
- struct pipe_sampler_view **sv = &stObj->sampler_views[i];
+ struct st_sampler_view *sv = &stObj->sampler_views[i];
/* Is the array entry used ? */
- if (*sv) {
+ if (sv->view) {
/* check if the context matches */
- if ((*sv)->context == st->pipe) {
+ if (sv->view->context == st->pipe) {
return sv;
}
} else {
@@ -73,13 +73,13 @@ st_texture_get_sampler_view(struct st_context *st,
if (!free) {
/* Haven't even found a free one, resize the array */
unsigned new_size = (stObj->num_sampler_views + 1) *
- sizeof(struct pipe_sampler_view *);
+ sizeof(struct st_sampler_view);
stObj->sampler_views = realloc(stObj->sampler_views, new_size);
free = &stObj->sampler_views[stObj->num_sampler_views++];
- *free = NULL;
+ free->view = NULL;
}
- assert(*free == NULL);
+ assert(free->view == NULL);
return free;
}
@@ -96,7 +96,7 @@ st_texture_release_sampler_view(struct st_context *st,
GLuint i;
for (i = 0; i < stObj->num_sampler_views; ++i) {
- struct pipe_sampler_view **sv = &stObj->sampler_views[i];
+ struct pipe_sampler_view **sv = &stObj->sampler_views[i].view;
if (*sv && (*sv)->context == st->pipe) {
pipe_sampler_view_reference(sv, NULL);
@@ -118,7 +118,7 @@ st_texture_release_all_sampler_views(struct st_context *st,
/* XXX This should use sampler_views[i]->pipe, not st->pipe */
for (i
Mesa (master): st/glsl_to_tgsi: fix DFRACEXP with only one destination
Module: Mesa
Branch: master
Commit: 3b666aa747955526f9200674a3f52539a07df5f6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b666aa747955526f9200674a3f52539a07df5f6
Author: Nicolai Hähnle
Date: Fri Oct 6 20:27:40 2017 +0200
st/glsl_to_tgsi: fix DFRACEXP with only one destination
Replace the undefined destination by a new temporary register.
Cleanup merge_two_dsts while we're at it.
Reviewed-by: Marek Olšák
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 38 ++
1 file changed, 23 insertions(+), 15 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 6a66317a21..7b81e18000 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -5206,7 +5206,8 @@ glsl_to_tgsi_visitor::merge_two_dsts(void)
/* We never delete inst, but we may delete its successor. */
foreach_in_list(glsl_to_tgsi_instruction, inst, &this->instructions) {
glsl_to_tgsi_instruction *inst2;
- bool merged;
+ unsigned defined;
+
if (num_inst_dst_regs(inst) != 2)
continue;
@@ -5214,10 +5215,19 @@ glsl_to_tgsi_visitor::merge_two_dsts(void)
inst->dst[1].file != PROGRAM_UNDEFINED)
continue;
+ assert(inst->dst[0].file != PROGRAM_UNDEFINED ||
+ inst->dst[1].file != PROGRAM_UNDEFINED);
+
+ if (inst->dst[0].file == PROGRAM_UNDEFINED)
+ defined = 1;
+ else
+ defined = 0;
+
inst2 = (glsl_to_tgsi_instruction *) inst->next;
do {
-
- if (inst->src[0].file == inst2->src[0].file &&
+ if (inst->op == inst2->op &&
+ inst2->dst[defined].file == PROGRAM_UNDEFINED &&
+ inst->src[0].file == inst2->src[0].file &&
inst->src[0].index == inst2->src[0].index &&
inst->src[0].type == inst2->src[0].type &&
inst->src[0].swizzle == inst2->src[0].swizzle)
@@ -5225,21 +5235,19 @@ glsl_to_tgsi_visitor::merge_two_dsts(void)
inst2 = (glsl_to_tgsi_instruction *) inst2->next;
} while (inst2);
- if (!inst2)
+ if (!inst2) {
+ /* Undefined destinations are not allowed, substitute with an unused
+ * temporary register.
+ */
+ st_src_reg tmp = get_temp(glsl_type::vec4_type);
+ inst->dst[defined ^ 1] = st_dst_reg(tmp);
+ inst->dst[defined ^ 1].writemask = 0;
continue;
- merged = false;
- if (inst->dst[0].file == PROGRAM_UNDEFINED) {
- merged = true;
- inst->dst[0] = inst2->dst[0];
- } else if (inst->dst[1].file == PROGRAM_UNDEFINED) {
- inst->dst[1] = inst2->dst[1];
- merged = true;
}
- if (merged) {
- inst2->remove();
- delete inst2;
- }
+ inst->dst[defined ^ 1] = inst2->dst[defined ^ 1];
+ inst2->remove();
+ delete inst2;
}
}
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Mesa (master): st/glsl_to_tgsi: the second destination doesn' t support relative addressing
Module: Mesa
Branch: master
Commit: cf3dd91969bd85f3c18d9f56d9fade70ea425a29
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cf3dd91969bd85f3c18d9f56d9fade70ea425a29
Author: Nicolai Hähnle
Date: Fri Oct 6 20:28:43 2017 +0200
st/glsl_to_tgsi: the second destination doesn't support relative addressing
It's not used -- DFRACEXP gets array indexes of its exponent out-parameter
lowered earlier -- and it wouldn't have worked correctly anyway when both
dst and dst1 use relative addressing.
Reviewed-by: Marek Olšák
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 7b81e18000..573ce69d8f 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -389,7 +389,7 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned
op,
* sources into temps.
*/
num_reladdr += dst.reladdr != NULL || dst.reladdr2;
- num_reladdr += dst1.reladdr != NULL || dst1.reladdr2;
+ assert(!dst1.reladdr); /* should be lowered in earlier passes */
num_reladdr += src0.reladdr != NULL || src0.reladdr2 != NULL;
num_reladdr += src1.reladdr != NULL || src1.reladdr2 != NULL;
num_reladdr += src2.reladdr != NULL || src2.reladdr2 != NULL;
@@ -407,10 +407,7 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir,
unsigned op,
emit_arl(ir, address_reg2, *dst.reladdr2);
num_reladdr--;
}
- if (dst1.reladdr) {
- emit_arl(ir, address_reg, *dst1.reladdr);
- num_reladdr--;
- }
+
assert(num_reladdr == 0);
/* inst->op has only 8 bits. */
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Mesa (master): st/mesa: don't assign prog->ShadowSamplers
Module: Mesa
Branch: master
Commit: 2991c0d7df898c6c3b5f5fdb66be07e63f8313e8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2991c0d7df898c6c3b5f5fdb66be07e63f8313e8
Author: Nicolai Hähnle
Date: Thu Oct 5 19:25:48 2017 +0200
st/mesa: don't assign prog->ShadowSamplers
It's not used, and the assignment for the TGSI case was incorrect
for sampler arrays.
Reviewed-by: Kenneth Graunke
Reviewed-by: Marek Olšák
---
src/mesa/state_tracker/st_glsl_to_nir.cpp | 1 -
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 4
2 files changed, 5 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 06a8ee8c61..5a439aaf92 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -435,7 +435,6 @@ st_nir_get_mesa_program(struct gl_context *ctx,
_mesa_log("\n\n");
}
- prog->ShadowSamplers = shader->shadow_samplers;
prog->ExternalSamplersUsed = gl_external_samplers(prog);
_mesa_update_shader_textures_used(shader_program, prog);
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 4b365c8481..1cfc9d963d 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -4475,10 +4475,6 @@ count_resources(glsl_to_tgsi_visitor *v, gl_program
*prog)
v->sampler_targets[idx] =
st_translate_texture_target(inst->tex_target, inst->tex_shadow);
-if (inst->tex_shadow) {
- prog->ShadowSamplers |= 1 << (inst->resource.index + i);
-}
-
if (inst->op == TGSI_OPCODE_TXF || inst->op == TGSI_OPCODE_TXF_LZ)
{
prog->TexelFetchSamplers |= 1u << idx;
}
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Mesa (master): st/glsl_to_tgsi: ignore GL_TEXTURE_SRGB_DECODE_EXT for samplers used with texelFetch*()
Module: Mesa
Branch: master
Commit: 0e26e767d2f13397d862b9a8fb921610a721cf19
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0e26e767d2f13397d862b9a8fb921610a721cf19
Author: Nicolai Hähnle
Date: Thu Oct 5 19:39:33 2017 +0200
st/glsl_to_tgsi: ignore GL_TEXTURE_SRGB_DECODE_EXT for samplers used with
texelFetch*()
See the comment for the relevant spec quote.
Fixes dEQP-GLES31.functional.srgb_texture_decode.skip_decode.srgba8.texel_fetch
v2: note the interaction between ARB_bindless_texture and
EXT_texture_sRGB_decode
as a TODO
Reviewed-by: Kenneth Graunke
Reviewed-by: Marek Olšák
---
src/mesa/main/mtypes.h | 1 +
src/mesa/state_tracker/st_atom_texture.c | 39 +++---
src/mesa/state_tracker/st_cb_texture.c | 4 ++-
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 4 +++
src/mesa/state_tracker/st_sampler_view.c | 19 +--
src/mesa/state_tracker/st_sampler_view.h | 3 ++-
src/mesa/state_tracker/st_texture.c| 3 ++-
src/mesa/state_tracker/st_texture.h| 7 +++---
8 files changed, 63 insertions(+), 17 deletions(-)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 2802a0e360..8206793de9 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2088,6 +2088,7 @@ struct gl_program
GLbitfield TexturesUsed[MAX_COMBINED_TEXTURE_IMAGE_UNITS]; /**<
TEXTURE_x_BIT bitmask */
GLbitfield SamplersUsed; /**< Bitfield of which samplers are used */
GLbitfield ShadowSamplers; /**< Texture units used for shadow sampling. */
+ GLbitfield TexelFetchSamplers; /**< Texture units used for texelFetch*(). */
GLbitfield ExternalSamplersUsed; /**< Texture units used for
samplerExternalOES */
/* Fragement shader only fields */
diff --git a/src/mesa/state_tracker/st_atom_texture.c
b/src/mesa/state_tracker/st_atom_texture.c
index 90828bb4cf..c350a09809 100644
--- a/src/mesa/state_tracker/st_atom_texture.c
+++ b/src/mesa/state_tracker/st_atom_texture.c
@@ -58,7 +58,8 @@
void
st_update_single_texture(struct st_context *st,
struct pipe_sampler_view **sampler_view,
- GLuint texUnit, bool glsl130_or_later)
+ GLuint texUnit, bool glsl130_or_later,
+ bool ignore_srgb_decode)
{
struct gl_context *ctx = st->ctx;
const struct gl_sampler_object *samp;
@@ -90,7 +91,8 @@ st_update_single_texture(struct st_context *st,
*sampler_view =
st_get_texture_sampler_view_from_stobj(st, stObj, samp,
- glsl130_or_later);
+ glsl130_or_later,
+ ignore_srgb_decode);
}
@@ -104,6 +106,7 @@ update_textures(struct st_context *st,
{
const GLuint old_max = *out_num_textures;
GLbitfield samplers_used = prog->SamplersUsed;
+ GLbitfield texel_fetch_samplers = prog->TexelFetchSamplers;
GLbitfield free_slots = ~prog->SamplersUsed;
GLbitfield external_samplers_used = prog->ExternalSamplersUsed;
GLuint unit;
@@ -118,13 +121,41 @@ update_textures(struct st_context *st,
/* loop over sampler units (aka tex image units) */
for (unit = 0; samplers_used || unit < old_max;
-unit++, samplers_used >>= 1) {
+unit++, samplers_used >>= 1, texel_fetch_samplers >>= 1) {
struct pipe_sampler_view *sampler_view = NULL;
if (samplers_used & 1) {
const GLuint texUnit = prog->SamplerUnits[unit];
- st_update_single_texture(st, &sampler_view, texUnit, glsl130);
+ /* The EXT_texture_sRGB_decode extension says:
+ *
+ *"The conversion of sRGB color space components to linear color
+ * space is always performed if the texel lookup function is one
+ * of the texelFetch builtin functions.
+ *
+ * Otherwise, if the texel lookup function is one of the texture
+ * builtin functions or one of the texture gather functions, the
+ * conversion of sRGB color space components to linear color space
+ * is controlled by the TEXTURE_SRGB_DECODE_EXT parameter.
+ *
+ * If the TEXTURE_SRGB_DECODE_EXT parameter is DECODE_EXT, the
+ * conversion of sRGB color space components to linear color space
+ * is performed.
+ *
+ * If the TEXTURE_SRGB_DECODE_EXT parameter is SKIP_DECODE_EXT,
+ * the value is returned without decoding. However, if the texture
+ * is also [statically] accessed with a texelFetch function, then
+ * the result of texture builtin functions and/or texture gather
+ * functions may be returned with decoding or without decoding."
+ *
+ * Note: the "statically" wil
Mesa (master): st/glsl_to_tgsi: fix indirect access to 64-bit integer
Module: Mesa
Branch: master
Commit: 541208cf138deb59204b28c56b3d37fec399778b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=541208cf138deb59204b28c56b3d37fec399778b
Author: Nicolai Hähnle
Date: Fri Oct 6 17:14:46 2017 +0200
st/glsl_to_tgsi: fix indirect access to 64-bit integer
Make sure we actually allocate two adjacent TGSI temporaries. The
current code fails e.g. when an arithmetic operation has two
operands with indirect accesses.
I will send out a new piglit test
(arb_gpu_shader_int64/execution/indirect-array-two-accesses.shader_test)
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Marek Olšák
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 1cfc9d963d..6a66317a21 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -1269,7 +1269,7 @@ glsl_to_tgsi_visitor::reladdr_to_temp(ir_instruction *ir,
if (reg->reladdr2) emit_arl(ir, address_reg2, *reg->reladdr2);
if (*num_reladdr != 1) {
- st_src_reg temp = get_temp(reg->type == GLSL_TYPE_DOUBLE ?
glsl_type::dvec4_type : glsl_type::vec4_type);
+ st_src_reg temp = get_temp(glsl_type::get_instance(reg->type, 4, 1));
emit_asm(ir, TGSI_OPCODE_MOV, st_dst_reg(temp), *reg);
*reg = temp;
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Mesa (master): st_api: remove unused get_resource_for_egl_image
Module: Mesa
Branch: master
Commit: fbcae1897be19203c95f3633dd38e3436768e3a8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fbcae1897be19203c95f3633dd38e3436768e3a8
Author: Nicolai Hähnle
Date: Tue Oct 10 13:58:48 2017 +0200
st_api: remove unused get_resource_for_egl_image
Reviewed-by: Eric Engestrom
---
src/gallium/include/state_tracker/st_api.h | 37 --
1 file changed, 37 deletions(-)
diff --git a/src/gallium/include/state_tracker/st_api.h
b/src/gallium/include/state_tracker/st_api.h
index 4d27dad5c5..2232c3efa1 100644
--- a/src/gallium/include/state_tracker/st_api.h
+++ b/src/gallium/include/state_tracker/st_api.h
@@ -141,22 +141,6 @@ enum st_attachment_type {
#define ST_ATTACHMENT_SAMPLE_MASK (1 << ST_ATTACHMENT_SAMPLE)
/**
- * Enumerations of state tracker context resources.
- */
-enum st_context_resource_type {
- ST_CONTEXT_RESOURCE_OPENGL_TEXTURE_2D,
- ST_CONTEXT_RESOURCE_OPENGL_TEXTURE_3D,
- ST_CONTEXT_RESOURCE_OPENGL_TEXTURE_CUBE_MAP_POSITIVE_X,
- ST_CONTEXT_RESOURCE_OPENGL_TEXTURE_CUBE_MAP_NEGATIVE_X,
- ST_CONTEXT_RESOURCE_OPENGL_TEXTURE_CUBE_MAP_POSITIVE_Y,
- ST_CONTEXT_RESOURCE_OPENGL_TEXTURE_CUBE_MAP_NEGATIVE_Y,
- ST_CONTEXT_RESOURCE_OPENGL_TEXTURE_CUBE_MAP_POSITIVE_Z,
- ST_CONTEXT_RESOURCE_OPENGL_TEXTURE_CUBE_MAP_NEGATIVE_Z,
- ST_CONTEXT_RESOURCE_OPENGL_RENDERBUFFER,
- ST_CONTEXT_RESOURCE_OPENVG_PARENT_IMAGE
-};
-
-/**
* Flush flags.
*/
#define ST_FLUSH_FRONT(1 << 0)
@@ -183,19 +167,6 @@ struct pipe_fence_handle;
struct util_queue_monitoring;
/**
- * Used in st_context_iface->get_resource_for_egl_image.
- */
-struct st_context_resource
-{
- /* these fields are filled in by the caller */
- enum st_context_resource_type type;
- void *resource;
-
- /* this is owned by the caller */
- struct pipe_resource *texture;
-};
-
-/**
* Used in st_manager_iface->get_egl_image.
*/
struct st_egl_image
@@ -432,14 +403,6 @@ struct st_context_iface
struct st_context_iface *stsrci);
/**
-* Look up and return the info of a resource for EGLImage.
-*
-* This function is optional.
-*/
- boolean (*get_resource_for_egl_image)(struct st_context_iface *stctxi,
- struct st_context_resource *stres);
-
- /**
* Start the thread if the API has a worker thread.
* Called after the context has been created and fully initialized on both
* sides (e.g. st/mesa and st/dri).
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Mesa (master): st/mesa: fix switching from surface-based to non-surface-based textures
Module: Mesa
Branch: master
Commit: d245724399b7ac9e2ddf99d381f7fe092204006a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d245724399b7ac9e2ddf99d381f7fe092204006a
Author: Nicolai Hähnle
Date: Tue Oct 10 13:58:44 2017 +0200
st/mesa: fix switching from surface-based to non-surface-based textures
This can happen with surface-based texture objects derived from EGL
images, since those aren't immutable.
Fixes tests in
dEQP-EGL.functional.sharing.gles2.multithread.random.images.teximage2d.* and
others
Reviewed-by: Marek Olšák
---
src/mesa/main/texobj.c | 11 +++
src/mesa/main/texobj.h | 3 ++-
src/mesa/state_tracker/st_cb_eglimage.c | 2 +-
src/mesa/state_tracker/st_cb_texture.c | 3 ++-
src/mesa/state_tracker/st_manager.c | 2 +-
src/mesa/state_tracker/st_vdpau.c | 2 +-
6 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/src/mesa/main/texobj.c b/src/mesa/main/texobj.c
index b703da01be..1978898b8b 100644
--- a/src/mesa/main/texobj.c
+++ b/src/mesa/main/texobj.c
@@ -471,16 +471,19 @@ _mesa_copy_texture_object( struct gl_texture_object *dest,
/**
- * Free all texture images of the given texture object.
+ * Free all texture images of the given texture objectm, except for
+ * \p retainTexImage.
*
* \param ctx GL context.
- * \param t texture object.
+ * \param texObj texture object.
+ * \param retainTexImage a texture image that will \em not be freed.
*
* \sa _mesa_clear_texture_image().
*/
void
_mesa_clear_texture_object(struct gl_context *ctx,
- struct gl_texture_object *texObj)
+ struct gl_texture_object *texObj,
+ struct gl_texture_image *retainTexImage)
{
GLuint i, j;
@@ -490,7 +493,7 @@ _mesa_clear_texture_object(struct gl_context *ctx,
for (i = 0; i < MAX_FACES; i++) {
for (j = 0; j < MAX_TEXTURE_LEVELS; j++) {
struct gl_texture_image *texImage = texObj->Image[i][j];
- if (texImage)
+ if (texImage && texImage != retainTexImage)
_mesa_clear_texture_image(ctx, texImage);
}
}
diff --git a/src/mesa/main/texobj.h b/src/mesa/main/texobj.h
index 71cc8ffba2..e67ce3ff9d 100644
--- a/src/mesa/main/texobj.h
+++ b/src/mesa/main/texobj.h
@@ -81,7 +81,8 @@ _mesa_copy_texture_object( struct gl_texture_object *dest,
extern void
_mesa_clear_texture_object(struct gl_context *ctx,
- struct gl_texture_object *obj);
+ struct gl_texture_object *obj,
+ struct gl_texture_image *retainTexImage);
extern void
_mesa_reference_texobj_(struct gl_texture_object **ptr,
diff --git a/src/mesa/state_tracker/st_cb_eglimage.c
b/src/mesa/state_tracker/st_cb_eglimage.c
index cca2c02609..e15b32ff19 100644
--- a/src/mesa/state_tracker/st_cb_eglimage.c
+++ b/src/mesa/state_tracker/st_cb_eglimage.c
@@ -198,7 +198,7 @@ st_bind_egl_image(struct gl_context *ctx,
/* switch to surface based */
if (!stObj->surface_based) {
- _mesa_clear_texture_object(ctx, texObj);
+ _mesa_clear_texture_object(ctx, texObj, NULL);
stObj->surface_based = GL_TRUE;
}
diff --git a/src/mesa/state_tracker/st_cb_texture.c
b/src/mesa/state_tracker/st_cb_texture.c
index b5006b05a7..b0a95ecbc7 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -693,7 +693,8 @@ prep_teximage(struct gl_context *ctx, struct
gl_texture_image *texImage,
const GLuint level = texImage->Level;
mesa_format texFormat;
- _mesa_clear_texture_object(ctx, texObj);
+ assert(!st_texture_image(texImage)->pt);
+ _mesa_clear_texture_object(ctx, texObj, texImage);
pipe_resource_reference(&stObj->pt, NULL);
/* oops, need to init this image again */
diff --git a/src/mesa/state_tracker/st_manager.c
b/src/mesa/state_tracker/st_manager.c
index 50bc3c33c6..aef87ea8b7 100644
--- a/src/mesa/state_tracker/st_manager.c
+++ b/src/mesa/state_tracker/st_manager.c
@@ -694,7 +694,7 @@ st_context_teximage(struct st_context_iface *stctxi,
stObj = st_texture_object(texObj);
/* switch to surface based */
if (!stObj->surface_based) {
- _mesa_clear_texture_object(ctx, texObj);
+ _mesa_clear_texture_object(ctx, texObj, NULL);
stObj->surface_based = GL_TRUE;
}
diff --git a/src/mesa/state_tracker/st_vdpau.c
b/src/mesa/state_tracker/st_vdpau.c
index 0273815308..bb4070eec3 100644
--- a/src/mesa/state_tracker/st_vdpau.c
+++ b/src/mesa/state_tracker/st_vdpau.c
@@ -221,7 +221,7 @@ st_vdpau_map_surface(struct gl_context *ctx, GLenum target,
GLenum access,
/* switch to surface based */
if (!stObj->surface_based) {
- _mesa_clear_texture_object(ctx, texObj);
+ _mesa_clear_texture_object(ctx, texObj, NULL);
stObj->surface_based = GL_TRUE;
}
___
Mesa (master): u_threaded_context: fix a memory leak
Module: Mesa
Branch: master
Commit: 1b592d30c51696eeeadca7a55b603c543dfdc3cf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1b592d30c51696eeeadca7a55b603c543dfdc3cf
Author: Nicolai Hähnle
Date: Tue Oct 10 13:58:46 2017 +0200
u_threaded_context: fix a memory leak
The uploaders can own transfers which need to be unmapped. Destroy them
before the final sync (they're not used from the driver thread anyway)
so that the transfer_unmap call is processed by the driver.
Reviewed-by: Marek Olšák
---
src/gallium/auxiliary/util/u_threaded_context.c | 15 ---
1 file changed, 8 insertions(+), 7 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_threaded_context.c
b/src/gallium/auxiliary/util/u_threaded_context.c
index 043d4e67df..7e28b87a7f 100644
--- a/src/gallium/auxiliary/util/u_threaded_context.c
+++ b/src/gallium/auxiliary/util/u_threaded_context.c
@@ -2233,6 +2233,13 @@ tc_destroy(struct pipe_context *_pipe)
struct threaded_context *tc = threaded_context(_pipe);
struct pipe_context *pipe = tc->pipe;
+ if (tc->base.const_uploader &&
+ tc->base.stream_uploader != tc->base.const_uploader)
+ u_upload_destroy(tc->base.const_uploader);
+
+ if (tc->base.stream_uploader)
+ u_upload_destroy(tc->base.stream_uploader);
+
tc_sync(tc);
if (util_queue_is_initialized(&tc->queue)) {
@@ -2242,14 +2249,8 @@ tc_destroy(struct pipe_context *_pipe)
util_queue_fence_destroy(&tc->batch_slots[i].fence);
}
- if (tc->base.const_uploader &&
- tc->base.stream_uploader != tc->base.const_uploader)
- u_upload_destroy(tc->base.const_uploader);
-
- if (tc->base.stream_uploader)
- u_upload_destroy(tc->base.stream_uploader);
-
slab_destroy_child(&tc->pool_transfers);
+ assert(tc->batch_slots[tc->next].num_total_call_slots == 0);
pipe->destroy(pipe);
os_free_aligned(tc);
}
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Mesa (master): egl/dri: factor out egl_error_from_dri_image_error
Module: Mesa
Branch: master
Commit: d0d6efcc64d5d088f130fbaec5d47f5e8817fae2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d0d6efcc64d5d088f130fbaec5d47f5e8817fae2
Author: Nicolai Hähnle
Date: Tue Oct 10 13:58:47 2017 +0200
egl/dri: factor out egl_error_from_dri_image_error
Reviewed-by: Eric Engestrom
---
src/egl/drivers/dri2/egl_dri2.c | 54 -
1 file changed, 26 insertions(+), 28 deletions(-)
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index 0db80a091f..1407c96352 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -1847,6 +1847,29 @@ dri2_create_image_from_dri(_EGLDisplay *disp, __DRIimage
*dri_image)
return &dri2_img->base;
}
+/**
+ * Translate a DRI Image extension error code into an EGL error code.
+ */
+static EGLint
+egl_error_from_dri_image_error(int dri_error)
+{
+ switch (dri_error) {
+ case __DRI_IMAGE_ERROR_SUCCESS:
+ return EGL_SUCCESS;
+ case __DRI_IMAGE_ERROR_BAD_ALLOC:
+ return EGL_BAD_ALLOC;
+ case __DRI_IMAGE_ERROR_BAD_MATCH:
+ return EGL_BAD_MATCH;
+ case __DRI_IMAGE_ERROR_BAD_PARAMETER:
+ return EGL_BAD_PARAMETER;
+ case __DRI_IMAGE_ERROR_BAD_ACCESS:
+ return EGL_BAD_ACCESS;
+ default:
+ assert(0);
+ return EGL_BAD_ALLOC;
+ }
+}
+
static _EGLImage *
dri2_create_image_khr_renderbuffer(_EGLDisplay *disp, _EGLContext *ctx,
EGLClientBuffer buffer,
@@ -1949,35 +1972,10 @@ dri2_get_sync_values_chromium(_EGLDisplay *dpy,
_EGLSurface *surf,
static void
dri2_create_image_khr_texture_error(int dri_error)
{
- EGLint egl_error;
-
- switch (dri_error) {
- case __DRI_IMAGE_ERROR_SUCCESS:
- return;
-
- case __DRI_IMAGE_ERROR_BAD_ALLOC:
- egl_error = EGL_BAD_ALLOC;
- break;
-
- case __DRI_IMAGE_ERROR_BAD_MATCH:
- egl_error = EGL_BAD_MATCH;
- break;
-
- case __DRI_IMAGE_ERROR_BAD_PARAMETER:
- egl_error = EGL_BAD_PARAMETER;
- break;
-
- case __DRI_IMAGE_ERROR_BAD_ACCESS:
- egl_error = EGL_BAD_ACCESS;
- break;
-
- default:
- assert(0);
- egl_error = EGL_BAD_MATCH;
- break;
- }
+ EGLint egl_error = egl_error_from_dri_image_error(dri_error);
- _eglError(egl_error, "dri2_create_image_khr_texture");
+ if (egl_error != EGL_SUCCESS)
+ _eglError(egl_error, "dri2_create_image_khr_texture");
}
static _EGLImage *
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Mesa (master): disk_cache: remove unnecessary NULL-pointer guards
Module: Mesa Branch: master Commit: 76fcede3f44d5f6eaf9b99ef80914c326387a3e5 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=76fcede3f44d5f6eaf9b99ef80914c326387a3e5 Author: Nicolai Hähnle Date: Tue Oct 10 13:58:45 2017 +0200 disk_cache: remove unnecessary NULL-pointer guards Reviewed-by: Marek Olšák --- src/util/disk_cache.c | 6 ++ 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/util/disk_cache.c b/src/util/disk_cache.c index 63fd8e1f93..e38cacb259 100644 --- a/src/util/disk_cache.c +++ b/src/util/disk_cache.c @@ -987,10 +987,8 @@ cache_put(void *job, int thread_index) */ if (fd != -1) close(fd); - if (filename_tmp) - free(filename_tmp); - if (filename) - free(filename); + free(filename_tmp); + free(filename); } void ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): egl/dri: use createImageFromRenderbuffer2 when available
Module: Mesa
Branch: master
Commit: bad24395d91737ce2b07cfe567c449271e31988c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bad24395d91737ce2b07cfe567c449271e31988c
Author: Nicolai Hähnle
Date: Tue Oct 10 13:58:47 2017 +0200
egl/dri: use createImageFromRenderbuffer2 when available
Reviewed-by: Eric Engestrom
---
src/egl/drivers/dri2/egl_dri2.c | 23 ---
1 file changed, 20 insertions(+), 3 deletions(-)
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index 1407c96352..171858bbcd 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -1890,9 +1890,26 @@ dri2_create_image_khr_renderbuffer(_EGLDisplay *disp,
_EGLContext *ctx,
return EGL_NO_IMAGE_KHR;
}
- dri_image =
- dri2_dpy->image->createImageFromRenderbuffer(dri2_ctx->dri_context,
- renderbuffer, NULL);
+ if (dri2_dpy->image->base.version >= 17) {
+ unsigned error = ~0;
+
+ dri_image = dri2_dpy->image->createImageFromRenderbuffer2(
+ dri2_ctx->dri_context, renderbuffer, NULL, &error);
+
+ assert(!!dri_image == (error == __DRI_IMAGE_ERROR_SUCCESS));
+
+ if (!dri_image) {
+ _eglError(egl_error_from_dri_image_error(error),
"dri2_create_image_khr");
+ return EGL_NO_IMAGE_KHR;
+ }
+ } else {
+ dri_image = dri2_dpy->image->createImageFromRenderbuffer(
+ dri2_ctx->dri_context, renderbuffer, NULL);
+ if (!dri_image) {
+ _eglError(EGL_BAD_ALLOC, "dri2_create_image_khr");
+ return EGL_NO_IMAGE_KHR;
+ }
+ }
return dri2_create_image_from_dri(disp, dri_image);
}
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Mesa (master): st/mesa: whitespace fix
Module: Mesa Branch: master Commit: 83c54a1402cfe495d79d151d94277996608197bf URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=83c54a1402cfe495d79d151d94277996608197bf Author: Nicolai Hähnle Date: Tue Oct 10 13:58:44 2017 +0200 st/mesa: whitespace fix Reviewed-by: Marek Olšák --- src/mesa/state_tracker/st_texture.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/state_tracker/st_texture.h b/src/mesa/state_tracker/st_texture.h index 0cde0c1f40..ea459bf6e2 100644 --- a/src/mesa/state_tracker/st_texture.h +++ b/src/mesa/state_tracker/st_texture.h @@ -70,7 +70,7 @@ struct st_texture_image * mapping/unmapping, as well as image copies. */ GLubyte *etc_data; - }; +}; /** ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): st/mesa: fix import of EGL images with non-zero level or layer
Module: Mesa
Branch: master
Commit: 288dea076e331153021453884a6d920b590a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=288dea076e331153021453884a6d920b590a
Author: Nicolai Hähnle
Date: Tue Oct 10 13:58:44 2017 +0200
st/mesa: fix import of EGL images with non-zero level or layer
In GL state, textures created from EGL images look like plain 2D textures
with a single level, so we use the existing layer_override facility and
add an analogous level_override one.
Fixes
dEQP-EGL.functional.image.create.gles2_cubemap_{positive,negative}_{x,y,z}_rgba_texture
Reviewed-by: Marek Olšák
---
src/mesa/state_tracker/st_cb_eglimage.c | 3 ++-
src/mesa/state_tracker/st_cb_texture.c | 2 ++
src/mesa/state_tracker/st_sampler_view.c | 16 ++--
src/mesa/state_tracker/st_texture.h | 15 ---
src/mesa/state_tracker/st_vdpau.c| 2 ++
5 files changed, 28 insertions(+), 10 deletions(-)
diff --git a/src/mesa/state_tracker/st_cb_eglimage.c
b/src/mesa/state_tracker/st_cb_eglimage.c
index e15b32ff19..bb092a2f6e 100644
--- a/src/mesa/state_tracker/st_cb_eglimage.c
+++ b/src/mesa/state_tracker/st_cb_eglimage.c
@@ -226,12 +226,13 @@ st_bind_egl_image(struct gl_context *ctx,
stimg->texture->width0, stimg->texture->height0,
1, 0, internalFormat, texFormat);
- /* FIXME create a non-default sampler view from the stimg? */
pipe_resource_reference(&stObj->pt, stimg->texture);
st_texture_release_all_sampler_views(st, stObj);
pipe_resource_reference(&stImage->pt, stObj->pt);
stObj->surface_format = stimg->format;
+ stObj->level_override = stimg->level;
+ stObj->layer_override = stimg->layer;
_mesa_dirty_texobj(ctx, texObj);
}
diff --git a/src/mesa/state_tracker/st_cb_texture.c
b/src/mesa/state_tracker/st_cb_texture.c
index b0a95ecbc7..25ea52924d 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -695,6 +695,8 @@ prep_teximage(struct gl_context *ctx, struct
gl_texture_image *texImage,
assert(!st_texture_image(texImage)->pt);
_mesa_clear_texture_object(ctx, texObj, texImage);
+ stObj->layer_override = 0;
+ stObj->level_override = 0;
pipe_resource_reference(&stObj->pt, NULL);
/* oops, need to init this image again */
diff --git a/src/mesa/state_tracker/st_sampler_view.c
b/src/mesa/state_tracker/st_sampler_view.c
index fbf0aaeb03..014b4d2678 100644
--- a/src/mesa/state_tracker/st_sampler_view.c
+++ b/src/mesa/state_tracker/st_sampler_view.c
@@ -379,9 +379,12 @@ st_create_texture_sampler_view_from_stobj(struct
st_context *st,
templ.format = format;
- templ.u.tex.first_level = stObj->base.MinLevel + stObj->base.BaseLevel;
- templ.u.tex.last_level = last_level(stObj);
- assert(templ.u.tex.first_level <= templ.u.tex.last_level);
+ if (stObj->level_override) {
+ templ.u.tex.first_level = templ.u.tex.last_level = stObj->level_override;
+ } else {
+ templ.u.tex.first_level = stObj->base.MinLevel + stObj->base.BaseLevel;
+ templ.u.tex.last_level = last_level(stObj);
+ }
if (stObj->layer_override) {
templ.u.tex.first_layer = templ.u.tex.last_layer = stObj->layer_override;
} else {
@@ -389,6 +392,7 @@ st_create_texture_sampler_view_from_stobj(struct st_context
*st,
templ.u.tex.last_layer = last_layer(stObj);
}
assert(templ.u.tex.first_layer <= templ.u.tex.last_layer);
+ assert(templ.u.tex.first_level <= templ.u.tex.last_level);
templ.target = gl_target_to_pipe(stObj->base.Target);
templ.swizzle_r = GET_SWZ(swizzle, 0);
@@ -419,9 +423,9 @@ st_get_texture_sampler_view_from_stobj(struct st_context
*st,
assert(!check_sampler_swizzle(st, stObj, view, glsl130_or_later));
assert(get_sampler_view_format(st, stObj, samp) == view->format);
assert(gl_target_to_pipe(stObj->base.Target) == view->target);
- assert(stObj->base.MinLevel + stObj->base.BaseLevel ==
- view->u.tex.first_level);
- assert(last_level(stObj) == view->u.tex.last_level);
+ assert(stObj->level_override ||
+ stObj->base.MinLevel + stObj->base.BaseLevel ==
view->u.tex.first_level);
+ assert(stObj->level_override || last_level(stObj) ==
view->u.tex.last_level);
assert(stObj->layer_override || stObj->base.MinLayer ==
view->u.tex.first_layer);
assert(stObj->layer_override || last_layer(stObj) ==
view->u.tex.last_layer);
assert(!stObj->layer_override ||
diff --git a/src/mesa/state_tracker/st_texture.h
b/src/mesa/state_tracker/st_texture.h
index 8448f4c6f0..0cde0c1f40 100644
--- a/src/mesa/state_tracker/st_texture.h
+++ b/src/mesa/state_tracker/st_texture.h
@@ -111,12 +111,21 @@ struct st_texture_object
*/
enum pip
Mesa (master): dri_interface: add an error-returning version of createImageFromRenderbuffer
Module: Mesa
Branch: master
Commit: f12e1c558614156fa1650abe4dc6b4ccec63bada
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f12e1c558614156fa1650abe4dc6b4ccec63bada
Author: Nicolai Hähnle
Date: Tue Oct 10 13:58:46 2017 +0200
dri_interface: add an error-returning version of createImageFromRenderbuffer
We ought to be able to distinguish between allocation errors and bad
parameters (non-existent renderbuffer object).
Bumps the version of the DRI Image extension to 17.
Reviewed-by: Eric Engestrom
---
include/GL/internal/dri_interface.h | 19 ++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/include/GL/internal/dri_interface.h
b/include/GL/internal/dri_interface.h
index 783ff1c70d..aefba92c02 100644
--- a/include/GL/internal/dri_interface.h
+++ b/include/GL/internal/dri_interface.h
@@ -1180,7 +1180,7 @@ struct __DRIdri2ExtensionRec {
* extensions.
*/
#define __DRI_IMAGE "DRI_IMAGE"
-#define __DRI_IMAGE_VERSION 16
+#define __DRI_IMAGE_VERSION 17
/**
* These formats correspond to the similarly named MESA_FORMAT_*
@@ -1377,6 +1377,7 @@ struct __DRIimageExtensionRec {
int name, int pitch,
void *loaderPrivate);
+/* Deprecated since version 17; see createImageFromRenderbuffer2 */
__DRIimage *(*createImageFromRenderbuffer)(__DRIcontext *context,
int renderbuffer,
void *loaderPrivate);
@@ -1625,6 +1626,22 @@ struct __DRIimageExtensionRec {
GLboolean (*queryDmaBufFormatModifierAttribs)(__DRIscreen *screen,
uint32_t fourcc, uint64_t
modifier,
int attrib, uint64_t *value);
+
+ /**
+* Create a DRI image from the given renderbuffer.
+*
+* \param context the current DRI context
+* \param renderbuffer the GL name of the renderbuffer
+* \param loaderPrivate for callbacks into the loader related to the image
+* \param error will be set to one of __DRI_IMAGE_ERROR_xxx
+* \return the newly created image on success, or NULL otherwise
+*
+* \since 17
+*/
+__DRIimage *(*createImageFromRenderbuffer2)(__DRIcontext *context,
+int renderbuffer,
+void *loaderPrivate,
+unsigned *error);
};
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Mesa (master): egl/dri: remove old left-overs
Module: Mesa
Branch: master
Commit: 4ec2ac11bd277a7eaa7cc506fd88228d05a22cd9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4ec2ac11bd277a7eaa7cc506fd88228d05a22cd9
Author: Nicolai Hähnle
Date: Tue Oct 10 13:58:47 2017 +0200
egl/dri: remove old left-overs
Reviewed-by: Eric Engestrom
---
src/egl/drivers/dri2/platform_x11_dri3.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/src/egl/drivers/dri2/platform_x11_dri3.c
b/src/egl/drivers/dri2/platform_x11_dri3.c
index 45bb56ca17..eadd37141e 100644
--- a/src/egl/drivers/dri2/platform_x11_dri3.c
+++ b/src/egl/drivers/dri2/platform_x11_dri3.c
@@ -304,8 +304,6 @@ dri3_create_image_khr(_EGLDriver *drv, _EGLDisplay *disp,
_EGLContext *ctx, EGLenum target,
EGLClientBuffer buffer, const EGLint *attr_list)
{
- (void) drv;
-
switch (target) {
case EGL_NATIVE_PIXMAP_KHR:
return dri3_create_image_khr_pixmap(disp, ctx, buffer, attr_list);
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Mesa (master): glsl/linker: add check for compute shared memory size
Module: Mesa
Branch: master
Commit: a2c8812f919c59933605c5942d6613e14ec8b3d1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a2c8812f919c59933605c5942d6613e14ec8b3d1
Author: Nicolai Hähnle
Date: Tue Oct 10 13:58:43 2017 +0200
glsl/linker: add check for compute shared memory size
Unlike uniforms, the limit on shared memory size is not called out
explicitly in the list of things that cause linker errors, but presumably
that's just an oversight in the spec.
Fixes
dEQP-GLES31.functional.debug.negative_coverage.{callbacks,get_error,log}.compute.exceed_shared_memory_size_limit
Reviewed-by: Timothy Arceri
---
src/compiler/glsl/ir_optimization.h | 5 +++--
src/compiler/glsl/linker.cpp | 3 +--
src/compiler/glsl/lower_shared_reference.cpp | 21 +++--
3 files changed, 23 insertions(+), 6 deletions(-)
diff --git a/src/compiler/glsl/ir_optimization.h
b/src/compiler/glsl/ir_optimization.h
index 38fb54990e..eb3ec3b0c7 100644
--- a/src/compiler/glsl/ir_optimization.h
+++ b/src/compiler/glsl/ir_optimization.h
@@ -143,8 +143,9 @@ bool lower_clip_cull_distance(struct gl_shader_program
*prog,
gl_linked_shader *shader);
void lower_output_reads(unsigned stage, exec_list *instructions);
bool lower_packing_builtins(exec_list *instructions, int op_mask);
-void lower_shared_reference(struct gl_linked_shader *shader,
-unsigned *shared_size);
+void lower_shared_reference(struct gl_context *ctx,
+struct gl_shader_program *prog,
+struct gl_linked_shader *shader);
void lower_ubo_reference(struct gl_linked_shader *shader,
bool clamp_block_indices, bool use_std430_as_default);
void lower_packed_varyings(void *mem_ctx,
diff --git a/src/compiler/glsl/linker.cpp b/src/compiler/glsl/linker.cpp
index f352c5385c..03eb05bf63 100644
--- a/src/compiler/glsl/linker.cpp
+++ b/src/compiler/glsl/linker.cpp
@@ -4657,8 +4657,7 @@ link_varyings_and_uniforms(unsigned first, unsigned last,
ctx->Const.UseSTD430AsDefaultPacking);
if (i == MESA_SHADER_COMPUTE)
- lower_shared_reference(prog->_LinkedShaders[i],
-&prog->Comp.SharedSize);
+ lower_shared_reference(ctx, prog, prog->_LinkedShaders[i]);
lower_vector_derefs(prog->_LinkedShaders[i]);
do_vec_index_to_swizzle(prog->_LinkedShaders[i]->ir);
diff --git a/src/compiler/glsl/lower_shared_reference.cpp
b/src/compiler/glsl/lower_shared_reference.cpp
index b9098913af..a1b3f7df47 100644
--- a/src/compiler/glsl/lower_shared_reference.cpp
+++ b/src/compiler/glsl/lower_shared_reference.cpp
@@ -33,6 +33,7 @@
#include "lower_buffer_access.h"
#include "ir_builder.h"
+#include "linker.h"
#include "main/macros.h"
#include "util/list.h"
#include "glsl_parser_extras.h"
@@ -478,7 +479,9 @@ lower_shared_reference_visitor::visit_enter(ir_call *ir)
} /* unnamed namespace */
void
-lower_shared_reference(struct gl_linked_shader *shader, unsigned *shared_size)
+lower_shared_reference(struct gl_context *ctx,
+ struct gl_shader_program *prog,
+ struct gl_linked_shader *shader)
{
if (shader->Stage != MESA_SHADER_COMPUTE)
return;
@@ -495,5 +498,19 @@ lower_shared_reference(struct gl_linked_shader *shader,
unsigned *shared_size)
visit_list_elements(&v, shader->ir);
} while (v.progress);
- *shared_size = v.shared_size;
+ prog->Comp.SharedSize = v.shared_size;
+
+ /* Section 19.1 (Compute Shader Variables) of the OpenGL 4.5 (Core Profile)
+* specification says:
+*
+* "There is a limit to the total size of all variables declared as
+*shared in a single program object. This limit, expressed in units of
+*basic machine units, may be queried as the value of
+*MAX_COMPUTE_SHARED_MEMORY_SIZE."
+*/
+ if (prog->Comp.SharedSize > ctx->Const.MaxComputeSharedMemorySize) {
+ linker_error(prog, "Too much shared memory used (%u/%u)\n",
+ prog->Comp.SharedSize,
+ ctx->Const.MaxComputeSharedMemorySize);
+ }
}
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Mesa (master): st/dri: implement createImageFromRenderbuffer(2)
Module: Mesa
Branch: master
Commit: e14fe41e0bf5d82c0b22eda2f8dcea058ac6e610
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e14fe41e0bf5d82c0b22eda2f8dcea058ac6e610
Author: Nicolai Hähnle
Date: Tue Oct 10 13:58:48 2017 +0200
st/dri: implement createImageFromRenderbuffer(2)
Tested with dEQP-EGL.functional.image.*renderbuffer* tests.
Reviewed-by: Eric Anholt
---
src/gallium/state_trackers/dri/dri2.c| 8 +++-
src/gallium/state_trackers/dri/dri_helpers.c | 65 +---
src/gallium/state_trackers/dri/dri_helpers.h | 5 +++
src/mesa/state_tracker/st_cb_fbo.h | 5 +++
4 files changed, 76 insertions(+), 7 deletions(-)
diff --git a/src/gallium/state_trackers/dri/dri2.c
b/src/gallium/state_trackers/dri/dri2.c
index 8672174787..324e357c35 100644
--- a/src/gallium/state_trackers/dri/dri2.c
+++ b/src/gallium/state_trackers/dri/dri2.c
@@ -1561,7 +1561,7 @@ dri2_get_capabilities(__DRIscreen *_screen)
/* The extension is modified during runtime if DRI_PRIME is detected */
static __DRIimageExtension dri2ImageExtension = {
-.base = { __DRI_IMAGE, 15 },
+.base = { __DRI_IMAGE, 17 },
.createImageFromName = dri2_create_image_from_name,
.createImageFromRenderbuffer = dri2_create_image_from_renderbuffer,
@@ -1579,6 +1579,12 @@ static __DRIimageExtension dri2ImageExtension = {
.getCapabilities = dri2_get_capabilities,
.mapImage = dri2_map_image,
.unmapImage = dri2_unmap_image,
+.createImageWithModifiers = NULL,
+.createImageFromDmaBufs2 = NULL,
+.queryDmaBufFormats = NULL,
+.queryDmaBufModifiers = NULL,
+.queryDmaBufFormatModifierAttribs = NULL,
+.createImageFromRenderbuffer2 = dri2_create_image_from_renderbuffer2,
};
static const __DRIrobustnessExtension dri2Robustness = {
diff --git a/src/gallium/state_trackers/dri/dri_helpers.c
b/src/gallium/state_trackers/dri/dri_helpers.c
index 07c4086310..06309d8f0c 100644
--- a/src/gallium/state_trackers/dri/dri_helpers.c
+++ b/src/gallium/state_trackers/dri/dri_helpers.c
@@ -25,6 +25,7 @@
#include "pipe/p_screen.h"
#include "state_tracker/st_texture.h"
#include "state_tracker/st_context.h"
+#include "state_tracker/st_cb_fbo.h"
#include "main/texobj.h"
#include "dri_helpers.h"
@@ -246,16 +247,68 @@ dri2_lookup_egl_image(struct dri_screen *screen, void
*handle)
}
__DRIimage *
-dri2_create_image_from_renderbuffer(__DRIcontext *context,
- int renderbuffer, void *loaderPrivate)
+dri2_create_image_from_renderbuffer2(__DRIcontext *context,
+int renderbuffer, void *loaderPrivate,
+ unsigned *error)
{
- struct dri_context *ctx = dri_context(context);
+ struct gl_context *ctx = ((struct st_context
*)dri_context(context)->st)->ctx;
+ struct gl_renderbuffer *rb;
+ struct pipe_resource *tex;
+ __DRIimage *img;
+
+ /* Section 3.9 (EGLImage Specification and Management) of the EGL 1.5
+* specification says:
+*
+* "If target is EGL_GL_RENDERBUFFER and buffer is not the name of a
+*renderbuffer object, or if buffer is the name of a multisampled
+*renderbuffer object, the error EGL_BAD_PARAMETER is generated."
+*
+* "If target is EGL_GL_TEXTURE_2D , EGL_GL_TEXTURE_CUBE_MAP_*,
+*EGL_GL_RENDERBUFFER or EGL_GL_TEXTURE_3D and buffer refers to the
+*default GL texture object (0) for the corresponding GL target, the
+*error EGL_BAD_PARAMETER is generated."
+* (rely on _mesa_lookup_renderbuffer returning NULL in this case)
+*/
+ rb = _mesa_lookup_renderbuffer(ctx, renderbuffer);
+ if (!rb || rb->NumSamples > 0) {
+ *error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
+ return NULL;
+ }
+
+ tex = st_get_renderbuffer_resource(rb);
+ if (!tex) {
+ *error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
+ return NULL;
+ }
+
+ img = CALLOC_STRUCT(__DRIimageRec);
+ if (!img) {
+ *error = __DRI_IMAGE_ERROR_BAD_ALLOC;
+ return NULL;
+ }
- if (!ctx->st->get_resource_for_egl_image)
+ img->dri_format = driGLFormatToImageFormat(rb->Format);
+ img->loader_private = loaderPrivate;
+
+ if (img->dri_format == __DRI_IMAGE_FORMAT_NONE) {
+ *error = __DRI_IMAGE_ERROR_BAD_PARAMETER;
+ free(img);
return NULL;
+ }
+
+ pipe_resource_reference(&img->texture, tex);
+
+ *error = __DRI_IMAGE_ERROR_SUCCESS;
+ return img;
+}
- /* TODO */
- return NULL;
+__DRIimage *
+dri2_create_image_from_renderbuffer(__DRIcontext *context,
+ int renderbuffer, void *loaderPrivate)
+{
+ unsigned error;
+ return dri2_create_image_from_renderbuffer2(context, renderbuffer,
+ loade
Mesa (master): st/mesa: don' t clobber glGetInternalformat* buffer for GL_NUM_SAMPLE_COUNTS
Module: Mesa
Branch: master
Commit: 9a8f13a33b2d08b34c78de67ce90e0198bfdf0b3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a8f13a33b2d08b34c78de67ce90e0198bfdf0b3
Author: Nicolai Hähnle
Date: Tue Oct 10 13:58:46 2017 +0200
st/mesa: don't clobber glGetInternalformat* buffer for GL_NUM_SAMPLE_COUNTS
Applications might pass in a buffer that is sized too large and rely
on the extra space of the buffer not being overwritten.
Fixes
dEQP-GLES31.functional.state_query.internal_format.partial_query.num_sample_counts
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Marek Olšák
---
src/mesa/state_tracker/st_format.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/state_tracker/st_format.c
b/src/mesa/state_tracker/st_format.c
index 5e38fe5689..65be09cbde 100644
--- a/src/mesa/state_tracker/st_format.c
+++ b/src/mesa/state_tracker/st_format.c
@@ -2378,9 +2378,10 @@ st_QueryInternalFormat(struct gl_context *ctx, GLenum
target,
break;
case GL_NUM_SAMPLE_COUNTS: {
+ int samples[16];
size_t num_samples;
num_samples = st_QuerySamplesForFormat(ctx, target, internalFormat,
- params);
+ samples);
params[0] = (GLint) num_samples;
break;
}
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Mesa (master): disk_cache: fix a memory leak
Module: Mesa Branch: master Commit: b041bf9f4b7b3ea5c787937d5f0cba14ab7dd532 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=b041bf9f4b7b3ea5c787937d5f0cba14ab7dd532 Author: Nicolai Hähnle Date: Tue Oct 10 13:58:45 2017 +0200 disk_cache: fix a memory leak Reviewed-by: Marek Olšák --- src/util/disk_cache.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/util/disk_cache.c b/src/util/disk_cache.c index 17913a913b..63fd8e1f93 100644 --- a/src/util/disk_cache.c +++ b/src/util/disk_cache.c @@ -1145,6 +1145,7 @@ disk_cache_get(struct disk_cache *cache, const cache_key key, size_t *size) free(data); free(filename); + free(file_header); close(fd); if (size) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: deduce rast_prim correctly for tessellation point mode
Module: Mesa
Branch: master
Commit: a3fa3b2e025f2a7d1eed45b332a89bc0d66ee0e4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a3fa3b2e025f2a7d1eed45b332a89bc0d66ee0e4
Author: Nicolai Hähnle
Date: Sun Sep 17 11:28:21 2017 +0200
radeonsi: deduce rast_prim correctly for tessellation point mode
Together with the previous patches, this fixes
dEQP-GLES31.functional.primitive_bounding_box.wide_points.*
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeonsi/si_state_draw.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index fb91d936c9..42807c0309 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1249,9 +1249,12 @@ void si_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
* current_rast_prim for this draw_vbo call. */
if (sctx->gs_shader.cso)
rast_prim = sctx->gs_shader.cso->gs_output_prim;
- else if (sctx->tes_shader.cso)
- rast_prim =
sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
- else
+ else if (sctx->tes_shader.cso) {
+ if
(sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
+ rast_prim = PIPE_PRIM_POINTS;
+ else
+ rast_prim =
sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
+ } else
rast_prim = info->mode;
if (rast_prim != sctx->b.current_rast_prim) {
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Mesa (master): radeonsi: move r600_viewport.c to si_viewport.c
Module: Mesa
Branch: master
Commit: c955f4594654eab28e342f72b42d8746c83843d5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c955f4594654eab28e342f72b42d8746c83843d5
Author: Nicolai Hähnle
Date: Tue Sep 26 17:17:55 2017 +0200
radeonsi: move r600_viewport.c to si_viewport.c
This is purely a file-move + #include fixup + build system changes.
Other cleanups will follow in subsequent commits.
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeon/Makefile.sources | 1 -
src/gallium/drivers/radeonsi/Makefile.sources | 1 +
.../drivers/{radeon/r600_viewport.c => radeonsi/si_state_viewport.c}| 2 +-
3 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/Makefile.sources
b/src/gallium/drivers/radeon/Makefile.sources
index f4e817e56e..5d38bb36b4 100644
--- a/src/gallium/drivers/radeon/Makefile.sources
+++ b/src/gallium/drivers/radeon/Makefile.sources
@@ -11,7 +11,6 @@ C_SOURCES := \
r600_streamout.c \
r600_test_dma.c \
r600_texture.c \
- r600_viewport.c \
radeon_uvd.c \
radeon_uvd.h \
radeon_vcn_dec.c \
diff --git a/src/gallium/drivers/radeonsi/Makefile.sources
b/src/gallium/drivers/radeonsi/Makefile.sources
index 3795bedb6b..ed3e52046c 100644
--- a/src/gallium/drivers/radeonsi/Makefile.sources
+++ b/src/gallium/drivers/radeonsi/Makefile.sources
@@ -30,5 +30,6 @@ C_SOURCES := \
si_state_binning.c \
si_state_draw.c \
si_state_shaders.c \
+ si_state_viewport.c \
si_state.h \
si_uvd.c
diff --git a/src/gallium/drivers/radeon/r600_viewport.c
b/src/gallium/drivers/radeonsi/si_state_viewport.c
similarity index 99%
rename from src/gallium/drivers/radeon/r600_viewport.c
rename to src/gallium/drivers/radeonsi/si_state_viewport.c
index 6e4fc9d751..00fa4c0d02 100644
--- a/src/gallium/drivers/radeon/r600_viewport.c
+++ b/src/gallium/drivers/radeonsi/si_state_viewport.c
@@ -21,7 +21,7 @@
* USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
-#include "r600_cs.h"
+#include "radeon/r600_cs.h"
#include "util/u_viewport.h"
#include "tgsi/tgsi_scan.h"
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Mesa (master): st/mesa: use R10G10B10X2 format where applicable
Module: Mesa
Branch: master
Commit: 6f83085ec08a5fab78bf385ef425493eaefebc1a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f83085ec08a5fab78bf385ef425493eaefebc1a
Author: Nicolai Hähnle
Date: Wed Sep 27 17:05:07 2017 +0200
st/mesa: use R10G10B10X2 format where applicable
This is the last step of fixing
dEQP-GLES3.functional.fbo.completeness.renderable.texture.color0.rgb_unsigned_int_2_10_10_10_rev
for radeonsi.
Reviewed-by: Marek Olšák
---
src/mesa/state_tracker/st_format.c | 11 ---
1 file changed, 8 insertions(+), 3 deletions(-)
diff --git a/src/mesa/state_tracker/st_format.c
b/src/mesa/state_tracker/st_format.c
index 348853affd..84b744e3df 100644
--- a/src/mesa/state_tracker/st_format.c
+++ b/src/mesa/state_tracker/st_format.c
@@ -89,6 +89,8 @@ st_mesa_format_to_pipe_format(const struct st_context *st,
mesa_format mesaForma
return PIPE_FORMAT_B10G10R10A2_UNORM;
case MESA_FORMAT_R10G10B10A2_UNORM:
return PIPE_FORMAT_R10G10B10A2_UNORM;
+ case MESA_FORMAT_R10G10B10X2_UNORM:
+ return PIPE_FORMAT_R10G10B10X2_UNORM;
case MESA_FORMAT_L4A4_UNORM:
return PIPE_FORMAT_L4A4_UNORM;
case MESA_FORMAT_L8A8_UNORM:
@@ -566,6 +568,8 @@ st_pipe_format_to_mesa_format(enum pipe_format format)
return MESA_FORMAT_B10G10R10A2_UNORM;
case PIPE_FORMAT_R10G10B10A2_UNORM:
return MESA_FORMAT_R10G10B10A2_UNORM;
+ case PIPE_FORMAT_R10G10B10X2_UNORM:
+ return MESA_FORMAT_R10G10B10X2_UNORM;
case PIPE_FORMAT_L4A4_UNORM:
return MESA_FORMAT_L4A4_UNORM;
case PIPE_FORMAT_LA88_UNORM:
@@ -1058,7 +1062,7 @@ test_format_conversion(struct st_context *st)
struct format_mapping
{
GLenum glFormats[18]; /**< list of GLenum formats, 0-terminated */
- enum pipe_format pipeFormats[13]; /**< list of pipe formats, 0-terminated */
+ enum pipe_format pipeFormats[14]; /**< list of pipe formats, 0-terminated */
};
@@ -1110,8 +1114,9 @@ static const struct format_mapping format_map[] = {
/* Basic RGB, RGBA formats */
{
{ GL_RGB10, 0 },
- { PIPE_FORMAT_B10G10R10X2_UNORM, PIPE_FORMAT_B10G10R10A2_UNORM,
-PIPE_FORMAT_R10G10B10A2_UNORM, DEFAULT_RGB_FORMATS }
+ { PIPE_FORMAT_R10G10B10X2_UNORM, PIPE_FORMAT_B10G10R10X2_UNORM,
+PIPE_FORMAT_R10G10B10A2_UNORM, PIPE_FORMAT_B10G10R10A2_UNORM,
+DEFAULT_RGB_FORMATS }
},
{
{ GL_RGB10_A2, 0 },
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Mesa (master): radeonsi: remove si_context::{scissor_enabled, clip_halfz}
Module: Mesa
Branch: master
Commit: 63680471f9f3e7047a2b074e824e449e59e4c8e9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=63680471f9f3e7047a2b074e824e449e59e4c8e9
Author: Nicolai Hähnle
Date: Tue Sep 26 18:10:58 2017 +0200
radeonsi: remove si_context::{scissor_enabled,clip_halfz}
They are just copies of the rasterizer state.
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeonsi/si_pipe.h | 4 ---
src/gallium/drivers/radeonsi/si_state.c | 14 +--
src/gallium/drivers/radeonsi/si_state_viewport.c | 32 +---
3 files changed, 24 insertions(+), 26 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index 4fe158fb9a..ed88aa0521 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -462,8 +462,6 @@ struct si_context {
bool need_check_render_feedback;
booldecompression_enabled;
- boolscissor_enabled;
- boolclip_halfz;
boolvs_writes_viewport_index;
boolvs_disables_clipping_viewport;
@@ -567,8 +565,6 @@ struct pipe_video_buffer *si_video_buffer_create(struct
pipe_context *pipe,
const struct pipe_video_buffer
*tmpl);
/* si_viewport.c */
-void si_viewport_set_rast_deps(struct si_context *rctx,
- bool scissor_enable, bool clip_halfz);
void si_update_vs_writes_viewport_index(struct si_context *ctx);
void si_init_viewport_functions(struct si_context *ctx);
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 2dbe7c6e27..78a3fbd086 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -1003,12 +1003,22 @@ static void si_bind_rs_state(struct pipe_context *ctx,
void *state)
sctx->current_vs_state &= C_VS_STATE_CLAMP_VERTEX_COLOR;
sctx->current_vs_state |=
S_VS_STATE_CLAMP_VERTEX_COLOR(rs->clamp_vertex_color);
- si_viewport_set_rast_deps(sctx, rs->scissor_enable, rs->clip_halfz);
-
si_pm4_bind_state(sctx, rasterizer, rs);
si_update_poly_offset_state(sctx);
if (!old_rs ||
+ old_rs->scissor_enable != rs->scissor_enable) {
+ sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
+ si_mark_atom_dirty(sctx, &sctx->scissors.atom);
+ }
+
+ if (!old_rs ||
+ old_rs->clip_halfz != rs->clip_halfz) {
+ sctx->viewports.depth_range_dirty_mask = (1 <<
SI_MAX_VIEWPORTS) - 1;
+ si_mark_atom_dirty(sctx, &sctx->viewports.atom);
+ }
+
+ if (!old_rs ||
old_rs->clip_plane_enable != rs->clip_plane_enable ||
old_rs->pa_cl_clip_cntl != rs->pa_cl_clip_cntl)
si_mark_atom_dirty(sctx, &sctx->clip_regs);
diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c
b/src/gallium/drivers/radeonsi/si_state_viewport.c
index 8e08a61f2f..1201be8779 100644
--- a/src/gallium/drivers/radeonsi/si_state_viewport.c
+++ b/src/gallium/drivers/radeonsi/si_state_viewport.c
@@ -40,7 +40,8 @@ static void si_set_scissor_states(struct pipe_context *pctx,
for (i = 0; i < num_scissors; i++)
ctx->scissors.states[start_slot + i] = state[i];
- if (!ctx->scissor_enabled)
+ if (!ctx->queued.named.rasterizer ||
+ !ctx->queued.named.rasterizer->scissor_enable)
return;
ctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
@@ -214,10 +215,13 @@ static void si_emit_scissors(struct r600_common_context
*rctx, struct r600_atom
struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
struct pipe_scissor_state *states = ctx->scissors.states;
unsigned mask = ctx->scissors.dirty_mask;
- bool scissor_enabled = ctx->scissor_enabled;
+ bool scissor_enabled = false;
struct si_signed_scissor max_vp_scissor;
int i;
+ if (ctx->queued.named.rasterizer)
+ scissor_enabled = ctx->queued.named.rasterizer->scissor_enable;
+
/* The simple case: Only 1 viewport is active. */
if (!ctx->vs_writes_viewport_index) {
struct si_signed_scissor *vp = &ctx->viewports.as_scissor[0];
@@ -327,14 +331,18 @@ static void si_emit_depth_ranges(struct si_context *ctx)
struct radeon_winsys_cs *cs = ctx->b.gfx.cs;
struct pipe_viewport_state *states = ctx->viewports.states;
unsigned mask = ctx->viewports.depth_range_dirty_mask;
+ bool clip_halfz = false;
float zmin, zmax;
+ if (ctx->queued.named.rasterizer)
+ clip_halfz = ctx->queued.n
Mesa (master): radeonsi: simplify the signature of si_update_vs_writes_viewport_index
Module: Mesa
Branch: master
Commit: 12f3155e28f335911d10aadabda03ec4f9bcbf16
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=12f3155e28f335911d10aadabda03ec4f9bcbf16
Author: Nicolai Hähnle
Date: Tue Sep 26 18:00:21 2017 +0200
radeonsi: simplify the signature of si_update_vs_writes_viewport_index
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeonsi/si_pipe.h | 3 +--
src/gallium/drivers/radeonsi/si_state_shaders.c | 6 +++---
src/gallium/drivers/radeonsi/si_state_viewport.c | 4 ++--
3 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index e0759eddb2..4fe158fb9a 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -569,8 +569,7 @@ struct pipe_video_buffer *si_video_buffer_create(struct
pipe_context *pipe,
/* si_viewport.c */
void si_viewport_set_rast_deps(struct si_context *rctx,
bool scissor_enable, bool clip_halfz);
-void si_update_vs_writes_viewport_index(struct si_context *ctx,
- struct tgsi_shader_info *info);
+void si_update_vs_writes_viewport_index(struct si_context *ctx);
void si_init_viewport_functions(struct si_context *ctx);
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 7619e2f04a..1fadc7ec5d 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -2301,7 +2301,7 @@ static void si_bind_vs_shader(struct pipe_context *ctx,
void *state)
sctx->vs_shader.current = sel ? sel->first_variant : NULL;
si_update_common_shader_state(sctx);
- si_update_vs_writes_viewport_index(sctx, si_get_vs_info(sctx));
+ si_update_vs_writes_viewport_index(sctx);
si_set_active_descriptors_for_shader(sctx, sel);
si_update_streamout_state(sctx);
si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
@@ -2344,7 +2344,7 @@ static void si_bind_gs_shader(struct pipe_context *ctx,
void *state)
if (sctx->ia_multi_vgt_param_key.u.uses_tess)
si_update_tess_uses_prim_id(sctx);
}
- si_update_vs_writes_viewport_index(sctx, si_get_vs_info(sctx));
+ si_update_vs_writes_viewport_index(sctx);
si_set_active_descriptors_for_shader(sctx, sel);
si_update_streamout_state(sctx);
si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
@@ -2395,7 +2395,7 @@ static void si_bind_tes_shader(struct pipe_context *ctx,
void *state)
si_shader_change_notify(sctx);
sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
}
- si_update_vs_writes_viewport_index(sctx, si_get_vs_info(sctx));
+ si_update_vs_writes_viewport_index(sctx);
si_set_active_descriptors_for_shader(sctx, sel);
si_update_streamout_state(sctx);
si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c
b/src/gallium/drivers/radeonsi/si_state_viewport.c
index eb4c00a24d..8e08a61f2f 100644
--- a/src/gallium/drivers/radeonsi/si_state_viewport.c
+++ b/src/gallium/drivers/radeonsi/si_state_viewport.c
@@ -389,9 +389,9 @@ void si_viewport_set_rast_deps(struct si_context *ctx,
* is delayed. When a shader with VIEWPORT_INDEX appears, this should be
* called to emit the rest.
*/
-void si_update_vs_writes_viewport_index(struct si_context *ctx,
- struct tgsi_shader_info *info)
+void si_update_vs_writes_viewport_index(struct si_context *ctx)
{
+ struct tgsi_shader_info *info = si_get_vs_info(ctx);
bool vs_window_space;
if (!info)
___
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Mesa (master): radeonsi: don't discard points and lines
Module: Mesa
Branch: master
Commit: 4d74432dd3b64814aca7d31fa133d5ee8bce9026
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4d74432dd3b64814aca7d31fa133d5ee8bce9026
Author: Nicolai Hähnle
Date: Sun Sep 17 11:26:53 2017 +0200
radeonsi: don't discard points and lines
This is a bit conservative, but a more precise solution requires access
to the rasterizer state. This is something to tackle after the fork between
r600 and radeonsi.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeon/r600_viewport.c | 21 +++--
src/gallium/drivers/radeonsi/si_state_draw.c | 7 +++
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_viewport.c
b/src/gallium/drivers/radeon/r600_viewport.c
index cf6d5f28ac..6e4fc9d751 100644
--- a/src/gallium/drivers/radeon/r600_viewport.c
+++ b/src/gallium/drivers/radeon/r600_viewport.c
@@ -165,6 +165,7 @@ static void r600_emit_guardband(struct r600_common_context
*rctx,
struct radeon_winsys_cs *cs = rctx->gfx.cs;
struct pipe_viewport_state vp;
float left, top, right, bottom, max_range, guardband_x, guardband_y;
+ float discard_x, discard_y;
/* Reconstruct the viewport transformation from the scissor. */
vp.translate[0] = (vp_as_scissor->minx + vp_as_scissor->maxx) / 2.0;
@@ -198,6 +199,22 @@ static void r600_emit_guardband(struct r600_common_context
*rctx,
guardband_x = MIN2(-left, right);
guardband_y = MIN2(-top, bottom);
+ discard_x = 1.0;
+ discard_y = 1.0;
+
+ if (rctx->current_rast_prim < PIPE_PRIM_TRIANGLES) {
+ /* When rendering wide points or lines, we need to be more
+* conservative about when to discard them entirely. Since
+* point size can be determined by the VS output, we basically
+* disable discard completely completely here.
+*
+* TODO: This can hurt performance when rendering lines and
+* points with fixed size, and could be improved.
+*/
+ discard_x = guardband_x;
+ discard_y = guardband_y;
+ }
+
/* If any of the GB registers is updated, all of them must be updated.
*/
if (rctx->chip_class >= CAYMAN)
radeon_set_context_reg_seq(cs,
CM_R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, 4);
@@ -205,9 +222,9 @@ static void r600_emit_guardband(struct r600_common_context
*rctx,
radeon_set_context_reg_seq(cs,
R600_R_028C0C_PA_CL_GB_VERT_CLIP_ADJ, 4);
radeon_emit(cs, fui(guardband_y)); /* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ */
- radeon_emit(cs, fui(1.0)); /* R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
+ radeon_emit(cs, fui(discard_y)); /* R_028BEC_PA_CL_GB_VERT_DISC_ADJ */
radeon_emit(cs, fui(guardband_x)); /* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ */
- radeon_emit(cs, fui(1.0)); /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
+ radeon_emit(cs, fui(discard_x)); /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
}
static void r600_emit_scissors(struct r600_common_context *rctx, struct
r600_atom *atom)
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index e4f592c384..fb91d936c9 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -1255,6 +1255,13 @@ void si_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
rast_prim = info->mode;
if (rast_prim != sctx->b.current_rast_prim) {
+ bool old_is_poly = sctx->b.current_rast_prim >=
PIPE_PRIM_TRIANGLES;
+ bool new_is_poly = rast_prim >= PIPE_PRIM_TRIANGLES;
+ if (old_is_poly != new_is_poly) {
+ sctx->b.scissors.dirty_mask = (1 << R600_MAX_VIEWPORTS)
- 1;
+ si_set_atom_dirty(sctx, &sctx->b.scissors.atom, true);
+ }
+
sctx->b.current_rast_prim = rast_prim;
sctx->do_update_shaders = true;
}
___
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Mesa (master): radeonsi: move current_rast_prim to r600_common_context
Module: Mesa
Branch: master
Commit: f86a112b07f01e267828fc255ffd63f223d2d5bb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f86a112b07f01e267828fc255ffd63f223d2d5bb
Author: Nicolai Hähnle
Date: Sun Sep 17 11:10:04 2017 +0200
radeonsi: move current_rast_prim to r600_common_context
We'll use it in the scissors / clip / guardband state.
v2: avoid a performance regression on r600 when applied to
(pre-fork) stable branches
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeon/r600_pipe_common.c | 4
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
src/gallium/drivers/radeonsi/si_pipe.h | 1 -
src/gallium/drivers/radeonsi/si_state_draw.c| 8
src/gallium/drivers/radeonsi/si_state_shaders.c | 8
5 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 62bd5f6a98..b327fd106a 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -724,6 +724,10 @@ bool si_common_context_init(struct r600_common_context
*rctx,
rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
rctx->b.buffer_subdata = si_buffer_subdata;
+ /* Set a reasonable default to avoid a performance regression in r600
+* on stable branches. */
+ rctx->current_rast_prim = PIPE_PRIM_TRIANGLES;
+
if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
rctx->b.get_device_reset_status = r600_get_reset_status;
rctx->gpu_reset_counter =
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index debedd402b..f6ded92dc5 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -599,6 +599,7 @@ struct r600_common_context {
/* Additional context states. */
unsigned flags; /* flush flags */
+ enum pipe_prim_type current_rast_prim; /* primitive type
after TES, GS */
/* Queries. */
/* Maintain the list of active queries for pausing between IBs. */
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index 46c89e2f38..08d47ea414 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -409,7 +409,6 @@ struct si_context {
unsignedlast_sc_line_stipple;
unsignedcurrent_vs_state;
unsignedlast_vs_state;
- enum pipe_prim_type current_rast_prim; /* primitive type after TES,
GS */
/* Scratch buffer */
struct r600_atomscratch_state;
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 0a672c503f..e4f592c384 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -531,7 +531,7 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context
*sctx,
static void si_emit_rasterizer_prim_state(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
- enum pipe_prim_type rast_prim = sctx->current_rast_prim;
+ enum pipe_prim_type rast_prim = sctx->b.current_rast_prim;
struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
/* Skip this if not rendering lines. */
@@ -581,7 +581,7 @@ static void si_emit_draw_registers(struct si_context *sctx,
{
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
unsigned prim = si_conv_pipe_prim(info->mode);
- unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
+ unsigned gs_out_prim =
si_conv_prim_to_gs_out(sctx->b.current_rast_prim);
unsigned ia_multi_vgt_param;
ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
@@ -1254,8 +1254,8 @@ void si_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
else
rast_prim = info->mode;
- if (rast_prim != sctx->current_rast_prim) {
- sctx->current_rast_prim = rast_prim;
+ if (rast_prim != sctx->b.current_rast_prim) {
+ sctx->b.current_rast_prim = rast_prim;
sctx->do_update_shaders = true;
}
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 889cd8e724..1146e5e394 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -1408,10 +1408,10 @@ static inline void si_shader_selector_key(struct
pipe_context *ctx,
}
if (rs) {
- bool is_poly = (sctx->current_rast_prim >=
P
Mesa (master): radeonsi: adjust clip discard based on line width / point size
Module: Mesa
Branch: master
Commit: 146c2b7c28ad62e837a9ca8123c2829bd07ca77a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=146c2b7c28ad62e837a9ca8123c2829bd07ca77a
Author: Nicolai Hähnle
Date: Tue Sep 26 20:36:10 2017 +0200
radeonsi: adjust clip discard based on line width / point size
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeonsi/si_state.c | 7 +-
src/gallium/drivers/radeonsi/si_state.h | 2 ++
src/gallium/drivers/radeonsi/si_state_viewport.c | 29
3 files changed, 27 insertions(+), 11 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index 78a3fbd086..4965a8374f 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -858,6 +858,7 @@ static void *si_create_rs_state(struct pipe_context *ctx,
rs->line_stipple_enable = state->line_stipple_enable;
rs->poly_stipple_enable = state->poly_stipple_enable;
rs->line_smooth = state->line_smooth;
+ rs->line_width = state->line_width;
rs->poly_smooth = state->poly_smooth;
rs->uses_poly_offset = state->offset_point || state->offset_line ||
state->offset_tri;
@@ -897,6 +898,8 @@ static void *si_create_rs_state(struct pipe_context *ctx,
psize_min = state->point_size;
psize_max = state->point_size;
}
+ rs->max_point_size = psize_max;
+
/* Divide by two, because 0.5 = 1 pixel. */
si_pm4_set_reg(pm4, R_028A04_PA_SU_POINT_MINMAX,
S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
@@ -1007,7 +1010,9 @@ static void si_bind_rs_state(struct pipe_context *ctx,
void *state)
si_update_poly_offset_state(sctx);
if (!old_rs ||
- old_rs->scissor_enable != rs->scissor_enable) {
+ (old_rs->scissor_enable != rs->scissor_enable ||
+old_rs->line_width != rs->line_width ||
+old_rs->max_point_size != rs->max_point_size)) {
sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
si_mark_atom_dirty(sctx, &sctx->scissors.atom);
}
diff --git a/src/gallium/drivers/radeonsi/si_state.h
b/src/gallium/drivers/radeonsi/si_state.h
index 4388ea99da..8e414a0817 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -68,6 +68,8 @@ struct si_state_rasterizer {
struct si_pm4_state *pm4_poly_offset;
unsignedpa_sc_line_stipple;
unsignedpa_cl_clip_cntl;
+ float line_width;
+ float max_point_size;
unsignedsprite_coord_enable:8;
unsignedclip_plane_enable:8;
unsignedflatshade:1;
diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c
b/src/gallium/drivers/radeonsi/si_state_viewport.c
index 1201be8779..a96eb8adc1 100644
--- a/src/gallium/drivers/radeonsi/si_state_viewport.c
+++ b/src/gallium/drivers/radeonsi/si_state_viewport.c
@@ -187,17 +187,26 @@ static void si_emit_guardband(struct si_context *ctx,
discard_x = 1.0;
discard_y = 1.0;
- if (ctx->current_rast_prim < PIPE_PRIM_TRIANGLES) {
+ if (unlikely(ctx->current_rast_prim < PIPE_PRIM_TRIANGLES) &&
+ ctx->queued.named.rasterizer) {
/* When rendering wide points or lines, we need to be more
-* conservative about when to discard them entirely. Since
-* point size can be determined by the VS output, we basically
-* disable discard completely completely here.
-*
-* TODO: This can hurt performance when rendering lines and
-* points with fixed size, and could be improved.
-*/
- discard_x = guardband_x;
- discard_y = guardband_y;
+* conservative about when to discard them entirely. */
+ const struct si_state_rasterizer *rs =
ctx->queued.named.rasterizer;
+ float pixels;
+
+ if (ctx->current_rast_prim == PIPE_PRIM_POINTS)
+ pixels = rs->max_point_size;
+ else
+ pixels = rs->line_width;
+
+ /* Add half the point size / line width */
+ discard_x += pixels / (2.0 * vp.scale[0]);
+ discard_y += pixels / (2.0 * vp.scale[1]);
+
+ /* Discard primitives that would lie entirely outside the clip
+* region. */
+ discard_x = MIN2(discard_x, guardband_x);
+ discard_y = MIN2(discard_y, guardband_y);
}
/* If any of the GB registers is u
Mesa (master): mesa/main: select the R10G10B10X2_UNORM internal format based on data type
Module: Mesa Branch: master Commit: f38b94285db7c0630b16cf6b8abc80e973e2e09f URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f38b94285db7c0630b16cf6b8abc80e973e2e09f Author: Nicolai Hähnle Date: Wed Sep 27 15:24:31 2017 +0200 mesa/main: select the R10G10B10X2_UNORM internal format based on data type ES requires it. This is a partial fix for dEQP-GLES3.functional.fbo.completeness.renderable.texture.color0.rgb_unsigned_int_2_10_10_10_rev Reviewed-by: Marek Olšák --- src/mesa/main/formats.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mesa/main/formats.c b/src/mesa/main/formats.c index 5c29d37bb4..ecdfd56103 100644 --- a/src/mesa/main/formats.c +++ b/src/mesa/main/formats.c @@ -2005,7 +2005,6 @@ _mesa_format_matches_format_and_type(mesa_format mesa_format, case MESA_FORMAT_RGBX_UINT8: case MESA_FORMAT_RGBX_SINT8: case MESA_FORMAT_B10G10R10X2_UNORM: - case MESA_FORMAT_R10G10B10X2_UNORM: case MESA_FORMAT_RGBX_UNORM16: case MESA_FORMAT_RGBX_SNORM16: case MESA_FORMAT_RGBX_FLOAT16: @@ -2016,6 +2015,9 @@ _mesa_format_matches_format_and_type(mesa_format mesa_format, case MESA_FORMAT_RGBX_SINT32: return GL_FALSE; + case MESA_FORMAT_R10G10B10X2_UNORM: + return format == GL_RGB && type == GL_UNSIGNED_INT_2_10_10_10_REV && + !swapBytes; case MESA_FORMAT_R10G10B10A2_UNORM: return format == GL_RGBA && type == GL_UNSIGNED_INT_2_10_10_10_REV && !swapBytes; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: move current_rast_prim into si_context
Module: Mesa
Branch: master
Commit: 7bbcb6ac6cf3e09da4387bf9c658c3aa1270db9a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7bbcb6ac6cf3e09da4387bf9c658c3aa1270db9a
Author: Nicolai Hähnle
Date: Tue Sep 26 17:57:59 2017 +0200
radeonsi: move current_rast_prim into si_context
v2: rebase fixes
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeon/r600_pipe_common.c| 4
src/gallium/drivers/radeon/r600_pipe_common.h| 1 -
src/gallium/drivers/radeonsi/si_pipe.h | 1 +
src/gallium/drivers/radeonsi/si_state_draw.c | 10 +-
src/gallium/drivers/radeonsi/si_state_shaders.c | 8
src/gallium/drivers/radeonsi/si_state_viewport.c | 2 +-
6 files changed, 11 insertions(+), 15 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index d50982b863..1aceb5b755 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -724,10 +724,6 @@ bool si_common_context_init(struct r600_common_context
*rctx,
rctx->dma_clear_buffer = r600_dma_clear_buffer_fallback;
rctx->b.buffer_subdata = si_buffer_subdata;
- /* Set a reasonable default to avoid a performance regression in r600
-* on stable branches. */
- rctx->current_rast_prim = PIPE_PRIM_TRIANGLES;
-
if (rscreen->info.drm_major == 2 && rscreen->info.drm_minor >= 43) {
rctx->b.get_device_reset_status = r600_get_reset_status;
rctx->gpu_reset_counter =
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 1558943bfe..597ff0280e 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -571,7 +571,6 @@ struct r600_common_context {
/* Additional context states. */
unsigned flags; /* flush flags */
- enum pipe_prim_type current_rast_prim; /* primitive type
after TES, GS */
/* Queries. */
/* Maintain the list of active queries for pausing between IBs. */
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h
b/src/gallium/drivers/radeonsi/si_pipe.h
index b3d5b18645..e0759eddb2 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -433,6 +433,7 @@ struct si_context {
unsignedlast_sc_line_stipple;
unsignedcurrent_vs_state;
unsignedlast_vs_state;
+ enum pipe_prim_type current_rast_prim; /* primitive type after TES,
GS */
/* Scratch buffer */
struct r600_atomscratch_state;
diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c
b/src/gallium/drivers/radeonsi/si_state_draw.c
index 9a6c9c8f84..2d4c9c5b9f 100644
--- a/src/gallium/drivers/radeonsi/si_state_draw.c
+++ b/src/gallium/drivers/radeonsi/si_state_draw.c
@@ -531,7 +531,7 @@ static unsigned si_get_ia_multi_vgt_param(struct si_context
*sctx,
static void si_emit_rasterizer_prim_state(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
- enum pipe_prim_type rast_prim = sctx->b.current_rast_prim;
+ enum pipe_prim_type rast_prim = sctx->current_rast_prim;
struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
/* Skip this if not rendering lines. */
@@ -581,7 +581,7 @@ static void si_emit_draw_registers(struct si_context *sctx,
{
struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
unsigned prim = si_conv_pipe_prim(info->mode);
- unsigned gs_out_prim =
si_conv_prim_to_gs_out(sctx->b.current_rast_prim);
+ unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
unsigned ia_multi_vgt_param;
ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
@@ -1257,15 +1257,15 @@ void si_draw_vbo(struct pipe_context *ctx, const struct
pipe_draw_info *info)
} else
rast_prim = info->mode;
- if (rast_prim != sctx->b.current_rast_prim) {
- bool old_is_poly = sctx->b.current_rast_prim >=
PIPE_PRIM_TRIANGLES;
+ if (rast_prim != sctx->current_rast_prim) {
+ bool old_is_poly = sctx->current_rast_prim >=
PIPE_PRIM_TRIANGLES;
bool new_is_poly = rast_prim >= PIPE_PRIM_TRIANGLES;
if (old_is_poly != new_is_poly) {
sctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
si_mark_atom_dirty(sctx, &sctx->scissors.atom);
}
- sctx->b.current_rast_prim = rast_prim;
+ sctx->current_rast_prim = rast_prim;
sctx->do_update_shaders = true;
}
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c
b/src/gallium/d
Mesa (master): mesa/main: R10G10B10_(A2) formats are not color renderable in ES
Module: Mesa
Branch: master
Commit: d2b60e433e50032e398fb92181f22a78601a5538
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2b60e433e50032e398fb92181f22a78601a5538
Author: Nicolai Hähnle
Date: Wed Sep 27 15:25:10 2017 +0200
mesa/main: R10G10B10_(A2) formats are not color renderable in ES
The EXT_texture_type_2_10_10_10_REV (ES only) states the following issue:
"1. Should textures specified with this type be renderable?
UNRESOLVED: No. A separate extension could provide this functionality."
This partially fixes
dEQP-GLES3.functional.fbo.completeness.renderable.texture.color0.{rgb,rgba}_unsigned_int_2_10_10_10_rev
Reviewed-by: Marek Olšák
---
src/mesa/main/fbobject.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index 4d6fdfcd6b..0867ff70fa 100644
--- a/src/mesa/main/fbobject.c
+++ b/src/mesa/main/fbobject.c
@@ -737,8 +737,11 @@ is_format_color_renderable(const struct gl_context *ctx,
mesa_format format,
break;
}
- if (format == MESA_FORMAT_B10G10R10A2_UNORM &&
- internalFormat != GL_RGB10_A2) {
+ if (internalFormat != GL_RGB10_A2 &&
+ (format == MESA_FORMAT_B10G10R10A2_UNORM ||
+format == MESA_FORMAT_B10G10R10X2_UNORM ||
+format == MESA_FORMAT_R10G10B10A2_UNORM ||
+format == MESA_FORMAT_R10G10B10X2_UNORM)) {
return GL_FALSE;
}
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Mesa (master): glsl: do not set the 'smooth' qualifier by default on ES shaders
Module: Mesa
Branch: master
Commit: fcae1a64ec0ef96bf90e473893849213ab9c14dd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fcae1a64ec0ef96bf90e473893849213ab9c14dd
Author: Nicolai Hähnle
Date: Mon Sep 11 16:40:37 2017 +0200
glsl: do not set the 'smooth' qualifier by default on ES shaders
It leads to surprising states with integer inputs and outputs on
vertex processing stages (e.g. geometry stages). Instead, rely on the
driver to choose smooth interpolation by default.
We still allow varyings to match when one stage declares it as smooth
and the other declares it without interpolation qualifiers.
Reviewed-by: Marek Olšák
Tested-by: Dieter Nützel
---
src/compiler/glsl/ast_to_hir.cpp| 11 ---
src/compiler/glsl/link_varyings.cpp | 17 -
src/mesa/main/shader_query.cpp | 8 +++-
3 files changed, 23 insertions(+), 13 deletions(-)
diff --git a/src/compiler/glsl/ast_to_hir.cpp b/src/compiler/glsl/ast_to_hir.cpp
index c46454956d..1999e68158 100644
--- a/src/compiler/glsl/ast_to_hir.cpp
+++ b/src/compiler/glsl/ast_to_hir.cpp
@@ -3126,17 +3126,6 @@ interpret_interpolation_qualifier(const struct
ast_type_qualifier *qual,
interpolation = INTERP_MODE_NOPERSPECTIVE;
else if (qual->flags.q.smooth)
interpolation = INTERP_MODE_SMOOTH;
- else if (state->es_shader &&
-((mode == ir_var_shader_in &&
- state->stage != MESA_SHADER_VERTEX) ||
- (mode == ir_var_shader_out &&
- state->stage != MESA_SHADER_FRAGMENT)))
- /* Section 4.3.9 (Interpolation) of the GLSL ES 3.00 spec says:
- *
- *"When no interpolation qualifier is present, smooth interpolation
- *is used."
- */
- interpolation = INTERP_MODE_SMOOTH;
else
interpolation = INTERP_MODE_NONE;
diff --git a/src/compiler/glsl/link_varyings.cpp
b/src/compiler/glsl/link_varyings.cpp
index 656bf79ca9..ed3bf41687 100644
--- a/src/compiler/glsl/link_varyings.cpp
+++ b/src/compiler/glsl/link_varyings.cpp
@@ -325,8 +325,23 @@ cross_validate_types_and_qualifiers(struct
gl_shader_program *prog,
* "It is a link-time error if, within the same stage, the interpolation
* qualifiers of variables of the same name do not match.
*
+* Section 4.3.9 (Interpolation) of the GLSL ES 3.00 spec says:
+*
+*"When no interpolation qualifier is present, smooth interpolation
+*is used."
+*
+* So we match variables where one is smooth and the other has no explicit
+* qualifier.
*/
- if (input->data.interpolation != output->data.interpolation &&
+ unsigned input_interpolation = input->data.interpolation;
+ unsigned output_interpolation = output->data.interpolation;
+ if (prog->IsES) {
+ if (input_interpolation == INTERP_MODE_NONE)
+ input_interpolation = INTERP_MODE_SMOOTH;
+ if (output_interpolation == INTERP_MODE_NONE)
+ output_interpolation = INTERP_MODE_SMOOTH;
+ }
+ if (input_interpolation != output_interpolation &&
prog->data->Version < 440) {
linker_error(prog,
"%s shader output `%s' specifies %s "
diff --git a/src/mesa/main/shader_query.cpp b/src/mesa/main/shader_query.cpp
index 64e68b4a26..6712bb45fb 100644
--- a/src/mesa/main/shader_query.cpp
+++ b/src/mesa/main/shader_query.cpp
@@ -1634,7 +1634,13 @@ validate_io(struct gl_program *producer, struct
gl_program *consumer)
* Note that location mismatches are detected by the loops above that
* find the producer variable that goes with the consumer variable.
*/
- if (producer_var->interpolation != consumer_var->interpolation) {
+ unsigned producer_interpolation = producer_var->interpolation;
+ unsigned consumer_interpolation = consumer_var->interpolation;
+ if (producer_interpolation == INTERP_MODE_NONE)
+ producer_interpolation = INTERP_MODE_SMOOTH;
+ if (consumer_interpolation == INTERP_MODE_NONE)
+ consumer_interpolation = INTERP_MODE_SMOOTH;
+ if (producer_interpolation != consumer_interpolation) {
valid = false;
goto out;
}
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Mesa (master): radeonsi: fix maximum advertised point size / line width
Module: Mesa
Branch: master
Commit: 30e37289ea754302f970705f6f94b8c51c952f30
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=30e37289ea754302f970705f6f94b8c51c952f30
Author: Nicolai Hähnle
Date: Sun Sep 17 11:59:37 2017 +0200
radeonsi: fix maximum advertised point size / line width
The hardware registers store the half-size/width in 12.4 fixed point
format, so 8192 is the maximum.
Fixes dEQP-GLES3.functional.rasterization.*
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeon/r600_pipe_common.c | 7 +--
src/gallium/drivers/radeonsi/si_state.c | 4 ++--
2 files changed, 3 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index b327fd106a..949d313bb5 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -1004,17 +1004,12 @@ static const char* r600_get_name(struct pipe_screen*
pscreen)
static float r600_get_paramf(struct pipe_screen* pscreen,
enum pipe_capf param)
{
- struct r600_common_screen *rscreen = (struct r600_common_screen
*)pscreen;
-
switch (param) {
case PIPE_CAPF_MAX_LINE_WIDTH:
case PIPE_CAPF_MAX_LINE_WIDTH_AA:
case PIPE_CAPF_MAX_POINT_WIDTH:
case PIPE_CAPF_MAX_POINT_WIDTH_AA:
- if (rscreen->family >= CHIP_CEDAR)
- return 16384.0f;
- else
- return 8192.0f;
+ return 8192.0f;
case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
return 16.0f;
case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
diff --git a/src/gallium/drivers/radeonsi/si_state.c
b/src/gallium/drivers/radeonsi/si_state.c
index e82ca6a694..3fbacec566 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -902,8 +902,8 @@ static void *si_create_rs_state(struct pipe_context *ctx,
S_028A04_MIN_SIZE(si_pack_float_12p4(psize_min/2)) |
S_028A04_MAX_SIZE(si_pack_float_12p4(psize_max/2)));
- tmp = (unsigned)state->line_width * 8;
- si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL, S_028A08_WIDTH(tmp));
+ si_pm4_set_reg(pm4, R_028A08_PA_SU_LINE_CNTL,
+ S_028A08_WIDTH(si_pack_float_12p4(state->line_width/2)));
si_pm4_set_reg(pm4, R_028A48_PA_SC_MODE_CNTL_0,
S_028A48_LINE_STIPPLE_ENABLE(state->line_stipple_enable)
|
S_028A48_MSAA_ENABLE(state->multisample ||
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Mesa (master): radeonsi: remove si_apply_scissor_bug_workaround
Module: Mesa
Branch: master
Commit: 449ac258d1b1d14fbb003b0140d4e4692777b05e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=449ac258d1b1d14fbb003b0140d4e4692777b05e
Author: Nicolai Hähnle
Date: Tue Sep 26 17:24:19 2017 +0200
radeonsi: remove si_apply_scissor_bug_workaround
It only affects pre-SI chips.
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeon/r600_pipe_common.h| 2 --
src/gallium/drivers/radeonsi/si_state_viewport.c | 17 -
2 files changed, 19 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index f6ded92dc5..4508a76876 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -880,8 +880,6 @@ void si_init_screen_texture_functions(struct
r600_common_screen *rscreen);
void si_init_context_texture_functions(struct r600_common_context *rctx);
/* r600_viewport.c */
-void si_apply_scissor_bug_workaround(struct r600_common_context *rctx,
-struct pipe_scissor_state *scissor);
void si_viewport_set_rast_deps(struct r600_common_context *rctx,
bool scissor_enable, bool clip_halfz);
void si_update_vs_writes_viewport_index(struct r600_common_context *rctx,
diff --git a/src/gallium/drivers/radeonsi/si_state_viewport.c
b/src/gallium/drivers/radeonsi/si_state_viewport.c
index 00fa4c0d02..54f31c4694 100644
--- a/src/gallium/drivers/radeonsi/si_state_viewport.c
+++ b/src/gallium/drivers/radeonsi/si_state_viewport.c
@@ -115,21 +115,6 @@ static void r600_scissor_make_union(struct
r600_signed_scissor *out,
out->maxy = MAX2(out->maxy, in->maxy);
}
-void si_apply_scissor_bug_workaround(struct r600_common_context *rctx,
-struct pipe_scissor_state *scissor)
-{
- if (rctx->chip_class == EVERGREEN || rctx->chip_class == CAYMAN) {
- if (scissor->maxx == 0)
- scissor->minx = 1;
- if (scissor->maxy == 0)
- scissor->miny = 1;
-
- if (rctx->chip_class == CAYMAN &&
- scissor->maxx == 1 && scissor->maxy == 1)
- scissor->maxx = 2;
- }
-}
-
static void r600_emit_one_scissor(struct r600_common_context *rctx,
struct radeon_winsys_cs *cs,
struct r600_signed_scissor *vp_scissor,
@@ -147,8 +132,6 @@ static void r600_emit_one_scissor(struct
r600_common_context *rctx,
if (scissor)
r600_clip_scissor(&final, scissor);
- si_apply_scissor_bug_workaround(rctx, &final);
-
radeon_emit(cs, S_028250_TL_X(final.minx) |
S_028250_TL_Y(final.miny) |
S_028250_WINDOW_OFFSET_DISABLE(1));
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Mesa (master): gallium: add PIPE_FORMAT_R10G10B10X2_UNORM
Module: Mesa
Branch: master
Commit: 85a3e1cae0f7e8751ec7ed284f50c323d000e7c1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=85a3e1cae0f7e8751ec7ed284f50c323d000e7c1
Author: Nicolai Hähnle
Date: Wed Sep 27 15:25:35 2017 +0200
gallium: add PIPE_FORMAT_R10G10B10X2_UNORM
Reviewed-by: Marek Olšák
---
src/gallium/auxiliary/util/u_format.csv | 1 +
src/gallium/auxiliary/util/u_format_tests.c | 6 ++
src/gallium/drivers/svga/svga_format.c | 1 +
src/gallium/include/pipe/p_format.h | 2 ++
4 files changed, 10 insertions(+)
diff --git a/src/gallium/auxiliary/util/u_format.csv
b/src/gallium/auxiliary/util/u_format.csv
index cef530aae7..be86acca9b 100644
--- a/src/gallium/auxiliary/util/u_format.csv
+++ b/src/gallium/auxiliary/util/u_format.csv
@@ -78,6 +78,7 @@ PIPE_FORMAT_B4G4R4A4_UNORM, plain, 1, 1, un4 , un4 ,
un4 , un4 , zyxw, r
PIPE_FORMAT_B4G4R4X4_UNORM, plain, 1, 1, un4 , un4 , un4 , x4 , zyx1,
rgb, x4 , un4 , un4 , un4 , yzw1
PIPE_FORMAT_B5G6R5_UNORM , plain, 1, 1, un5 , un6 , un5 , , zyx1,
rgb, un5 , un6 , un5 , , xyz1
PIPE_FORMAT_R10G10B10A2_UNORM , plain, 1, 1, un10, un10, un10, un2 , xyzw,
rgb, un2 , un10, un10, un10, wzyx
+PIPE_FORMAT_R10G10B10X2_UNORM , plain, 1, 1, un10, un10, un10, x2, xyz1,
rgb, x2 , un10, un10, un10, wzy1
PIPE_FORMAT_B10G10R10A2_UNORM , plain, 1, 1, un10, un10, un10, un2 , zyxw,
rgb, un2 , un10, un10, un10, yzwx
PIPE_FORMAT_B2G3R3_UNORM , plain, 1, 1, un2 , un3 , un3 , , zyx1,
rgb, un3 , un3 , un2 , , xyz1
diff --git a/src/gallium/auxiliary/util/u_format_tests.c
b/src/gallium/auxiliary/util/u_format_tests.c
index 3075ea0abe..dbf072a01e 100644
--- a/src/gallium/auxiliary/util/u_format_tests.c
+++ b/src/gallium/auxiliary/util/u_format_tests.c
@@ -140,6 +140,12 @@ util_format_test_cases[] =
{PIPE_FORMAT_R10G10B10A2_UNORM, PACKED_1x32(0x),
PACKED_1x32(0xc000), UNPACKED_1x1(0.0, 0.0, 0.0, 1.0)},
{PIPE_FORMAT_R10G10B10A2_UNORM, PACKED_1x32(0x),
PACKED_1x32(0x), UNPACKED_1x1(1.0, 1.0, 1.0, 1.0)},
+ {PIPE_FORMAT_R10G10B10X2_UNORM, PACKED_1x32(0x3fff),
PACKED_1x32(0x), UNPACKED_1x1(0.0, 0.0, 0.0, 1.0)},
+ {PIPE_FORMAT_R10G10B10X2_UNORM, PACKED_1x32(0x3fff),
PACKED_1x32(0x03ff), UNPACKED_1x1(1.0, 0.0, 0.0, 1.0)},
+ {PIPE_FORMAT_R10G10B10X2_UNORM, PACKED_1x32(0x3fff),
PACKED_1x32(0x000ffc00), UNPACKED_1x1(0.0, 1.0, 0.0, 1.0)},
+ {PIPE_FORMAT_R10G10B10X2_UNORM, PACKED_1x32(0x3fff),
PACKED_1x32(0x3ff0), UNPACKED_1x1(0.0, 0.0, 1.0, 1.0)},
+ {PIPE_FORMAT_R10G10B10X2_UNORM, PACKED_1x32(0x3fff),
PACKED_1x32(0x3fff), UNPACKED_1x1(1.0, 1.0, 1.0, 1.0)},
+
{PIPE_FORMAT_B10G10R10A2_UNORM, PACKED_1x32(0x),
PACKED_1x32(0x), UNPACKED_1x1(0.0, 0.0, 0.0, 0.0)},
{PIPE_FORMAT_B10G10R10A2_UNORM, PACKED_1x32(0x),
PACKED_1x32(0x03ff), UNPACKED_1x1(0.0, 0.0, 1.0, 0.0)},
{PIPE_FORMAT_B10G10R10A2_UNORM, PACKED_1x32(0x),
PACKED_1x32(0x000ffc00), UNPACKED_1x1(0.0, 1.0, 0.0, 0.0)},
diff --git a/src/gallium/drivers/svga/svga_format.c
b/src/gallium/drivers/svga/svga_format.c
index 95dd04d8ab..2f74240b6a 100644
--- a/src/gallium/drivers/svga/svga_format.c
+++ b/src/gallium/drivers/svga/svga_format.c
@@ -360,6 +360,7 @@ static const struct vgpu10_format_entry
format_conversion_table[] =
{ PIPE_FORMAT_ASTC_12x10_SRGB, SVGA3D_FORMAT_INVALID,
SVGA3D_FORMAT_INVALID, 0 },
{ PIPE_FORMAT_ASTC_12x12_SRGB, SVGA3D_FORMAT_INVALID,
SVGA3D_FORMAT_INVALID, 0 },
{ PIPE_FORMAT_P016, SVGA3D_FORMAT_INVALID,
SVGA3D_FORMAT_INVALID, 0 },
+ { PIPE_FORMAT_R10G10B10X2_UNORM, SVGA3D_FORMAT_INVALID,
SVGA3D_FORMAT_INVALID, 0 },
};
diff --git a/src/gallium/include/pipe/p_format.h
b/src/gallium/include/pipe/p_format.h
index e4e09d8b43..25e6548bb3 100644
--- a/src/gallium/include/pipe/p_format.h
+++ b/src/gallium/include/pipe/p_format.h
@@ -391,6 +391,8 @@ enum pipe_format {
PIPE_FORMAT_P016= 307,
+ PIPE_FORMAT_R10G10B10X2_UNORM = 308,
+
PIPE_FORMAT_COUNT
};
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Mesa (master): radeonsi: move and rename scissor and viewport state and functions
Module: Mesa
Branch: master
Commit: 6b416ec3d665fb1e10fafad44fbd8f9cec661a68
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6b416ec3d665fb1e10fafad44fbd8f9cec661a68
Author: Nicolai Hähnle
Date: Tue Sep 26 17:56:15 2017 +0200
radeonsi: move and rename scissor and viewport state and functions
v2: change GET_MAX_SCISSOR to SI_MAX_SCISSOR
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeon/r600_pipe_common.c| 1 -
src/gallium/drivers/radeon/r600_pipe_common.h| 35 ---
src/gallium/drivers/radeonsi/si_blit.c | 4 +-
src/gallium/drivers/radeonsi/si_hw_context.c | 10 +-
src/gallium/drivers/radeonsi/si_pipe.c | 3 +-
src/gallium/drivers/radeonsi/si_pipe.h | 37
src/gallium/drivers/radeonsi/si_state.c | 6 +-
src/gallium/drivers/radeonsi/si_state_draw.c | 6 +-
src/gallium/drivers/radeonsi/si_state_shaders.c | 6 +-
src/gallium/drivers/radeonsi/si_state_viewport.c | 258 +++
10 files changed, 184 insertions(+), 182 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c
b/src/gallium/drivers/radeon/r600_pipe_common.c
index 949d313bb5..d50982b863 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -738,7 +738,6 @@ bool si_common_context_init(struct r600_common_context
*rctx,
rctx->b.set_device_reset_callback = r600_set_device_reset_callback;
si_init_context_texture_functions(rctx);
- si_init_viewport_functions(rctx);
si_streamout_init(rctx);
si_init_query_functions(rctx);
si_init_msaa(&rctx->b);
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 4508a76876..1558943bfe 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -120,7 +120,6 @@ struct u_log_context;
#define DBG_NO_DFSM(1ull << 55)
#define R600_MAP_BUFFER_ALIGNMENT 64
-#define R600_MAX_VIEWPORTS16
#define SI_MAX_VARIABLE_THREADS_PER_BLOCK 1024
@@ -523,27 +522,6 @@ struct r600_streamout {
int num_prims_gen_queries;
};
-struct r600_signed_scissor {
- int minx;
- int miny;
- int maxx;
- int maxy;
-};
-
-struct r600_scissors {
- struct r600_atomatom;
- unsigneddirty_mask;
- struct pipe_scissor_state states[R600_MAX_VIEWPORTS];
-};
-
-struct r600_viewports {
- struct r600_atomatom;
- unsigneddirty_mask;
- unsigneddepth_range_dirty_mask;
- struct pipe_viewport_state states[R600_MAX_VIEWPORTS];
- struct r600_signed_scissor as_scissor[R600_MAX_VIEWPORTS];
-};
-
struct r600_ring {
struct radeon_winsys_cs *cs;
void (*flush)(void *ctx, unsigned flags,
@@ -590,12 +568,6 @@ struct r600_common_context {
/* States. */
struct r600_streamout streamout;
- struct r600_scissorsscissors;
- struct r600_viewports viewports;
- boolscissor_enabled;
- boolclip_halfz;
- boolvs_writes_viewport_index;
- boolvs_disables_clipping_viewport;
/* Additional context states. */
unsigned flags; /* flush flags */
@@ -879,13 +851,6 @@ bool si_texture_disable_dcc(struct r600_common_context
*rctx,
void si_init_screen_texture_functions(struct r600_common_screen *rscreen);
void si_init_context_texture_functions(struct r600_common_context *rctx);
-/* r600_viewport.c */
-void si_viewport_set_rast_deps(struct r600_common_context *rctx,
- bool scissor_enable, bool clip_halfz);
-void si_update_vs_writes_viewport_index(struct r600_common_context *rctx,
- struct tgsi_shader_info *info);
-void si_init_viewport_functions(struct r600_common_context *rctx);
-
/* cayman_msaa.c */
void si_get_sample_position(struct pipe_context *ctx, unsigned sample_count,
unsigned sample_index, float *out_value);
diff --git a/src/gallium/drivers/radeonsi/si_blit.c
b/src/gallium/drivers/radeonsi/si_blit.c
index f5ae072f4f..b8ff67d5ab 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -70,8 +70,8 @@ static void si_blitter_begin(struct pipe_context *ctx, enum
si_blitter_op op)
util_blitter_save_stencil_ref(sctx->blitter,
&sctx->stencil_ref.state);
util_blitter_save_fragment_shader(sctx->blitter,
sctx->ps_shader.cso);
util_blitter_save_sample_mask(sctx->blitter,
sctx->sample_mask.sample_mask);
- util_blitt
Mesa (master): amd/common: move ac_build_phi from radeonsi
Module: Mesa
Branch: master
Commit: 052b974fed3586f3b2f61d2d2c050c1807ec43c5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=052b974fed3586f3b2f61d2d2c050c1807ec43c5
Author: Nicolai Hähnle
Date: Fri Sep 29 11:17:03 2017 +0200
amd/common: move ac_build_phi from radeonsi
Reviewed-by: Marek Olšák
---
src/amd/common/ac_llvm_build.c | 14 ++
src/amd/common/ac_llvm_build.h | 5 +
src/gallium/drivers/radeonsi/si_shader.c | 20 +++-
3 files changed, 22 insertions(+), 17 deletions(-)
diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 71468df2db..51fb009be8 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -252,6 +252,20 @@ void ac_build_type_name_for_intr(LLVMTypeRef type, char
*buf, unsigned bufsize)
}
}
+/**
+ * Helper function that builds an LLVM IR PHI node and immediately adds
+ * incoming edges.
+ */
+LLVMValueRef
+ac_build_phi(struct ac_llvm_context *ctx, LLVMTypeRef type,
+unsigned count_incoming, LLVMValueRef *values,
+LLVMBasicBlockRef *blocks)
+{
+ LLVMValueRef phi = LLVMBuildPhi(ctx->builder, type, "");
+ LLVMAddIncoming(phi, values, blocks, count_incoming);
+ return phi;
+}
+
/* Prevent optimizations (at least of memory accesses) across the current
* point in the program by emitting empty inline assembly that is marked as
* having side effects.
diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index 3f93551330..1d6dc0ab2f 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -85,6 +85,11 @@ ac_build_intrinsic(struct ac_llvm_context *ctx, const char
*name,
void ac_build_type_name_for_intr(LLVMTypeRef type, char *buf, unsigned
bufsize);
+LLVMValueRef
+ac_build_phi(struct ac_llvm_context *ctx, LLVMTypeRef type,
+unsigned count_incoming, LLVMValueRef *values,
+LLVMBasicBlockRef *blocks);
+
void ac_build_optimization_barrier(struct ac_llvm_context *ctx,
LLVMValueRef *pvgpr);
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index d012c19a58..c11a4ebead 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -234,20 +234,6 @@ unsigned si_shader_io_get_unique_index(unsigned
semantic_name, unsigned index)
}
/**
- * Helper function that builds an LLVM IR PHI node and immediately adds
- * incoming edges.
- */
-static LLVMValueRef
-build_phi(struct ac_llvm_context *ctx, LLVMTypeRef type,
- unsigned count_incoming, LLVMValueRef *values,
- LLVMBasicBlockRef *blocks)
-{
- LLVMValueRef phi = LLVMBuildPhi(ctx->builder, type, "");
- LLVMAddIncoming(phi, values, blocks, count_incoming);
- return phi;
-}
-
-/**
* Get the value of a shader input parameter and extract a bitfield.
*/
static LLVMValueRef unpack_param(struct si_shader_context *ctx,
@@ -2922,15 +2908,15 @@ static void si_llvm_emit_tcs_epilogue(struct
lp_build_tgsi_context *bld_base)
values[0] = rel_patch_id;
values[1] = LLVMGetUndef(ctx->i32);
- rel_patch_id = build_phi(&ctx->ac, ctx->i32, 2, values, blocks);
+ rel_patch_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values,
blocks);
values[0] = tf_lds_offset;
values[1] = LLVMGetUndef(ctx->i32);
- tf_lds_offset = build_phi(&ctx->ac, ctx->i32, 2, values,
blocks);
+ tf_lds_offset = ac_build_phi(&ctx->ac, ctx->i32, 2, values,
blocks);
values[0] = invocation_id;
values[1] = ctx->i32_1; /* cause the epilog to skip threads */
- invocation_id = build_phi(&ctx->ac, ctx->i32, 2, values,
blocks);
+ invocation_id = ac_build_phi(&ctx->ac, ctx->i32, 2, values,
blocks);
}
/* Return epilog parameters from this function. */
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Mesa (master): radeonsi: fix a regression in integer cube map handling
Module: Mesa
Branch: master
Commit: 6d23f7c65d6a3e6117b7b383bc811f01dd5b5c40
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6d23f7c65d6a3e6117b7b383bc811f01dd5b5c40
Author: Nicolai Hähnle
Date: Fri Sep 29 11:21:01 2017 +0200
radeonsi: fix a regression in integer cube map handling
A recent commit fixed the case of integer cube maps, which need the
workaround of replacing the data format with USCALED/SSCALED. However,
this broke the case of non- integer cube maps; those still need the
fix of shifting the texture coordinates.
Fixes KHR-GL45.texture_gather.plain-gather-int-cube-array and similar.
Fixes: 6fb0c1013b35 ("radeonsi: workaround for gather4 on integer cube maps")
Reviewed-by: Marek Olšák
---
src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c | 34 +--
1 file changed, 26 insertions(+), 8 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
index be92044750..0863876ed8 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_mem.c
@@ -1722,6 +1722,7 @@ si_lower_gather4_integer(struct si_shader_context *ctx,
enum tgsi_return_type return_type)
{
LLVMBuilderRef builder = ctx->gallivm.builder;
+ LLVMValueRef wa_ = NULL;
LLVMValueRef coord = args->addr;
LLVMValueRef half_texel[2];
/* Texture coordinates start after:
@@ -1739,7 +1740,6 @@ si_lower_gather4_integer(struct si_shader_context *ctx,
LLVMValueRef formats;
LLVMValueRef data_format;
LLVMValueRef wa_formats;
- LLVMValueRef wa;
formats = LLVMBuildExtractElement(builder, args->resource,
ctx->i32_1, "");
@@ -1747,9 +1747,10 @@ si_lower_gather4_integer(struct si_shader_context *ctx,
LLVMConstInt(ctx->i32, 20, false),
"");
data_format = LLVMBuildAnd(builder, data_format,
LLVMConstInt(ctx->i32, (1u << 6) -
1, false), "");
- wa = LLVMBuildICmp(builder, LLVMIntEQ, data_format,
- LLVMConstInt(ctx->i32,
V_008F14_IMG_DATA_FORMAT_8_8_8_8, false),
- "");
+ wa_ = LLVMBuildICmp(
+ builder, LLVMIntEQ, data_format,
+ LLVMConstInt(ctx->i32,
V_008F14_IMG_DATA_FORMAT_8_8_8_8, false),
+ "");
uint32_t wa_num_format =
return_type == TGSI_RETURN_TYPE_UINT ?
@@ -1761,19 +1762,24 @@ si_lower_gather4_integer(struct si_shader_context *ctx,
wa_formats = LLVMBuildOr(builder, wa_formats,
LLVMConstInt(ctx->i32, wa_num_format,
false), "");
- formats = LLVMBuildSelect(builder, wa, wa_formats, formats, "");
+ formats = LLVMBuildSelect(builder, wa_, wa_formats,
formats, "");
args->resource = LLVMBuildInsertElement(
builder, args->resource, formats, ctx->i32_1, "");
-
- return wa;
}
if (target == TGSI_TEXTURE_RECT ||
target == TGSI_TEXTURE_SHADOWRECT) {
+ assert(!wa_);
half_texel[0] = half_texel[1] = LLVMConstReal(ctx->f32, -0.5);
} else {
struct tgsi_full_instruction txq_inst = {};
struct lp_build_emit_data txq_emit_data = {};
+ struct lp_build_if_state if_ctx;
+
+ if (wa_) {
+ /* Skip the texture size query entirely if we don't
need it. */
+ lp_build_if(&if_ctx, &ctx->gallivm,
LLVMBuildNot(builder, wa_, ""));
+ }
/* Query the texture size. */
txq_inst.Texture.Texture = target;
@@ -1796,6 +1802,18 @@ si_lower_gather4_integer(struct si_shader_context *ctx,
half_texel[c] = LLVMBuildFMul(builder, half_texel[c],
LLVMConstReal(ctx->f32,
-0.5), "");
}
+
+ if (wa_) {
+ lp_build_endif(&if_ctx);
+
+ LLVMBasicBlockRef bb[2] = { if_ctx.true_block,
if_ctx.entry_block };
+
+ for (c = 0; c < 2; c++) {
+ LLVMValueRef values[2] = { half_texel[c],
ctx->ac.f32_0 };
+ half_texel[c] = ac_build_phi(&ctx->ac,
ctx->f32, 2,
+values, bb);
+ }
+ }
}
for
Mesa (master): tgsi: fix the documentation of DLDEXP
Module: Mesa
Branch: master
Commit: dbe7fc00d5715bcc08acc3141414da037938bbdd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dbe7fc00d5715bcc08acc3141414da037938bbdd
Author: Nicolai Hähnle
Date: Fri Sep 15 17:47:27 2017 +0200
tgsi: fix the documentation of DLDEXP
Sourcing the exponent for the zw destination pair from Z is consistent
with both tgsi_exec and gallivm. In practice, st_glsl_to_tgsi always
generates per-channel instructions anyway.
Reviewed-by: Marek Olšák
Tested-by: Dieter Nützel
---
src/gallium/docs/source/tgsi.rst | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/docs/source/tgsi.rst b/src/gallium/docs/source/tgsi.rst
index 0bd9964a98..8633c929b9 100644
--- a/src/gallium/docs/source/tgsi.rst
+++ b/src/gallium/docs/source/tgsi.rst
@@ -1859,7 +1859,7 @@ source is an integer.
dst.xy = src0.xy \times 2^{src1.x}
- dst.zw = src0.zw \times 2^{src1.y}
+ dst.zw = src0.zw \times 2^{src1.z}
.. opcode:: DMIN - Minimum
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Mesa (master): st/glsl_to_tgsi: use LDEXP when available
Module: Mesa
Branch: master
Commit: 6de5147d2024a282f064d3bcf6103240d283da72
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6de5147d2024a282f064d3bcf6103240d283da72
Author: Nicolai Hähnle
Date: Fri Sep 15 16:52:23 2017 +0200
st/glsl_to_tgsi: use LDEXP when available
Reviewed-by: Marek Olšák
Tested-by: Dieter Nützel
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 0daf5a1428..50a71e461f 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -584,10 +584,10 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir,
unsigned op,
} else {
/* some opcodes are special case in what they use as sources
- - [FUI]2D/[UI]2I64 is a float/[u]int src0, DLDEXP is integer
src1 */
+ - [FUI]2D/[UI]2I64 is a float/[u]int src0, (D)LDEXP is
integer src1 */
if (op == TGSI_OPCODE_F2D || op == TGSI_OPCODE_U2D || op ==
TGSI_OPCODE_I2D ||
op == TGSI_OPCODE_I2I64 || op == TGSI_OPCODE_U2I64 ||
- op == TGSI_OPCODE_DLDEXP ||
+ op == TGSI_OPCODE_DLDEXP || op == TGSI_OPCODE_LDEXP ||
(op == TGSI_OPCODE_UCMP && dst_is_64bit[0])) {
dinst->src[j].swizzle = MAKE_SWIZZLE4(swz, swz, swz, swz);
}
@@ -2107,6 +2107,8 @@ glsl_to_tgsi_visitor::visit_expression(ir_expression* ir,
st_src_reg *op)
case ir_binop_ldexp:
if (ir->operands[0]->type->is_double()) {
emit_asm(ir, TGSI_OPCODE_DLDEXP, result_dst, op[0], op[1]);
+ } else if (ir->operands[0]->type->is_float()) {
+ emit_asm(ir, TGSI_OPCODE_LDEXP, result_dst, op[0], op[1]);
} else {
assert(!"Invalid ldexp for non-double opcode in
glsl_to_tgsi_visitor::visit()");
}
@@ -6783,6 +6785,8 @@ st_link_shader(struct gl_context *ctx, struct
gl_shader_program *prog)
PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED);
bool have_dfrexp = pscreen->get_shader_param(pscreen, ptarget,
PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED);
+ bool have_ldexp = pscreen->get_shader_param(pscreen, ptarget,
+
PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED);
unsigned if_threshold = pscreen->get_shader_param(pscreen, ptarget,
PIPE_SHADER_CAP_LOWER_IF_THRESHOLD);
@@ -6833,7 +6837,7 @@ st_link_shader(struct gl_context *ctx, struct
gl_shader_program *prog)
FDIV_TO_MUL_RCP |
EXP_TO_EXP2 |
LOG_TO_LOG2 |
- LDEXP_TO_ARITH |
+ (have_ldexp ? 0 : LDEXP_TO_ARITH) |
(have_dfrexp ? 0 : DFREXP_DLDEXP_TO_ARITH) |
CARRY_TO_ARITH |
BORROW_TO_ARITH |
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Mesa (master): util/queue: fix a race condition in the fence code
Module: Mesa
Branch: master
Commit: a208cd7ae4c1613dfd9acafa6046c1cd0be4911f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a208cd7ae4c1613dfd9acafa6046c1cd0be4911f
Author: Nicolai Hähnle
Date: Thu Sep 28 17:52:42 2017 +0200
util/queue: fix a race condition in the fence code
A tempting alternative fix would be adding a lock/unlock pair in
util_queue_fence_is_signalled. However, that wouldn't actually
improve anything in the semantics of util_queue_fence_is_signalled,
while making that test much more heavy-weight. So this lock/unlock
pair in util_queue_fence_destroy for "flushing out" other threads
that may still be in util_queue_fence_signal looks like the better
fix.
v2: rephrase the comment
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Marek Olšák
Reviewed-by: Gustaw Smolarczyk
---
src/util/u_queue.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/util/u_queue.c b/src/util/u_queue.c
index 449da7dc9a..3b05110e9f 100644
--- a/src/util/u_queue.c
+++ b/src/util/u_queue.c
@@ -120,6 +120,19 @@ void
util_queue_fence_destroy(struct util_queue_fence *fence)
{
assert(fence->signalled);
+
+ /* Ensure that another thread is not in the middle of
+* util_queue_fence_signal (having set the fence to signalled but still
+* holding the fence mutex).
+*
+* A common contract between threads is that as soon as a fence is signalled
+* by thread A, thread B is allowed to destroy it. Since
+* util_queue_fence_is_signalled does not lock the fence mutex (for
+* performance reasons), we must do so here.
+*/
+ mtx_lock(&fence->mutex);
+ mtx_unlock(&fence->mutex);
+
cnd_destroy(&fence->cond);
mtx_destroy(&fence->mutex);
}
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Mesa (master): tgsi: infer that DLDEXP's second source has an integer type
Module: Mesa
Branch: master
Commit: d713af711d3fdf63358f627b3f318f8b88519e46
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d713af711d3fdf63358f627b3f318f8b88519e46
Author: Nicolai Hähnle
Date: Fri Sep 15 17:40:05 2017 +0200
tgsi: infer that DLDEXP's second source has an integer type
Reviewed-by: Marek Olšák
Tested-by: Dieter Nützel
---
src/gallium/auxiliary/gallivm/lp_bld_tgsi.c | 4 ++--
src/gallium/auxiliary/nir/tgsi_to_nir.c | 7 ---
src/gallium/auxiliary/tgsi/tgsi_info.c | 5 -
src/gallium/auxiliary/tgsi/tgsi_info.h | 2 +-
4 files changed, 11 insertions(+), 7 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
index c6b1dcbad3..e450092a82 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
@@ -202,7 +202,7 @@ static int get_src_chan_idx(unsigned opcode,
int dst_chan_index)
{
enum tgsi_opcode_type dtype = tgsi_opcode_infer_dst_type(opcode);
- enum tgsi_opcode_type stype = tgsi_opcode_infer_src_type(opcode);
+ enum tgsi_opcode_type stype = tgsi_opcode_infer_src_type(opcode, 0);
if (!tgsi_type_is_64bit(dtype) && !tgsi_type_is_64bit(stype))
return dst_chan_index;
@@ -420,7 +420,7 @@ lp_build_emit_fetch(
{
const struct tgsi_full_src_register *reg = &inst->Src[src_op];
enum tgsi_opcode_type stype =
- tgsi_opcode_infer_src_type(inst->Instruction.Opcode);
+ tgsi_opcode_infer_src_type(inst->Instruction.Opcode, src_op);
return lp_build_emit_fetch_src(bld_base, reg, stype, chan_index);
}
diff --git a/src/gallium/auxiliary/nir/tgsi_to_nir.c
b/src/gallium/auxiliary/nir/tgsi_to_nir.c
index 1b630096ff..a317552311 100644
--- a/src/gallium/auxiliary/nir/tgsi_to_nir.c
+++ b/src/gallium/auxiliary/nir/tgsi_to_nir.c
@@ -767,12 +767,13 @@ ttn_get_var(struct ttn_compile *c, struct
tgsi_full_dst_register *tgsi_fdst)
}
static nir_ssa_def *
-ttn_get_src(struct ttn_compile *c, struct tgsi_full_src_register *tgsi_fsrc)
+ttn_get_src(struct ttn_compile *c, struct tgsi_full_src_register *tgsi_fsrc,
+int src_idx)
{
nir_builder *b = &c->build;
struct tgsi_src_register *tgsi_src = &tgsi_fsrc->Register;
unsigned tgsi_opcode = c->token->FullInstruction.Instruction.Opcode;
- unsigned tgsi_src_type = tgsi_opcode_infer_src_type(tgsi_opcode);
+ unsigned tgsi_src_type = tgsi_opcode_infer_src_type(tgsi_opcode, src_idx);
bool src_is_float = !(tgsi_src_type == TGSI_TYPE_SIGNED ||
tgsi_src_type == TGSI_TYPE_UNSIGNED);
nir_alu_src src;
@@ -1644,7 +1645,7 @@ ttn_emit_instruction(struct ttn_compile *c)
nir_ssa_def *src[TGSI_FULL_MAX_SRC_REGISTERS];
for (i = 0; i < tgsi_inst->Instruction.NumSrcRegs; i++) {
- src[i] = ttn_get_src(c, &tgsi_inst->Src[i]);
+ src[i] = ttn_get_src(c, &tgsi_inst->Src[i], i);
}
nir_alu_dest dest = ttn_get_dest(c, tgsi_dst);
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c
b/src/gallium/auxiliary/tgsi/tgsi_info.c
index 08bce6380c..36be463dc8 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
@@ -242,8 +242,11 @@ tgsi_opcode_infer_type( uint opcode )
* infer the source type of a TGSI opcode.
*/
enum tgsi_opcode_type
-tgsi_opcode_infer_src_type( uint opcode )
+tgsi_opcode_infer_src_type(uint opcode, uint src_idx)
{
+ if (src_idx == 1 && opcode == TGSI_OPCODE_DLDEXP)
+ return TGSI_TYPE_SIGNED;
+
switch (opcode) {
case TGSI_OPCODE_UIF:
case TGSI_OPCODE_TXF:
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.h
b/src/gallium/auxiliary/tgsi/tgsi_info.h
index 74bff18692..f3ef46fb4a 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.h
@@ -111,7 +111,7 @@ static inline bool tgsi_type_is_64bit(enum tgsi_opcode_type
type)
}
enum tgsi_opcode_type
-tgsi_opcode_infer_src_type( uint opcode );
+tgsi_opcode_infer_src_type( uint opcode, uint src_idx );
enum tgsi_opcode_type
tgsi_opcode_infer_dst_type( uint opcode );
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Mesa (master): radeonsi: emit DLDEXP and DFRACEXP TGSI opcodes
Module: Mesa
Branch: master
Commit: d190bfc1ad1a90f6d231c0c840a8153c22c06423
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d190bfc1ad1a90f6d231c0c840a8153c22c06423
Author: Nicolai Hähnle
Date: Sat Sep 16 12:52:21 2017 +0200
radeonsi: emit DLDEXP and DFRACEXP TGSI opcodes
Note: this causes spurious regressions in some current piglit tests,
because the tests incorrectly assume that there is no denorm support for
doubles. I'm going to send out a fix for those tests as well.
Reviewed-by: Marek Olšák
Tested-by: Dieter Nützel
---
src/gallium/drivers/radeonsi/si_pipe.c| 2 +-
src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c | 25 +++
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index 9a5b789a2c..954f9ff063 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -749,6 +749,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
+ case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
return 1;
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
@@ -768,7 +769,6 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
/* Unsupported boolean features. */
case PIPE_SHADER_CAP_SUBROUTINES:
case PIPE_SHADER_CAP_SUPPORTED_IRS:
- case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
return 0;
}
return 0;
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
index ba7ec4f410..818ca499d9 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c
@@ -734,6 +734,27 @@ static void emit_rsq(const struct lp_build_tgsi_action
*action,
bld_base->base.one, sqrt);
}
+static void dfracexp_fetch_args(struct lp_build_tgsi_context *bld_base,
+ struct lp_build_emit_data *emit_data)
+{
+ emit_data->args[0] = lp_build_emit_fetch(bld_base, emit_data->inst, 0,
TGSI_CHAN_X);
+ emit_data->arg_count = 1;
+}
+
+static void dfracexp_emit(const struct lp_build_tgsi_action *action,
+ struct lp_build_tgsi_context *bld_base,
+ struct lp_build_emit_data *emit_data)
+{
+ struct si_shader_context *ctx = si_shader_context(bld_base);
+
+ emit_data->output[emit_data->chan] =
+ lp_build_intrinsic(ctx->ac.builder,
"llvm.amdgcn.frexp.mant.f64",
+ ctx->ac.f64, &emit_data->args[0], 1, 0);
+ emit_data->output1[emit_data->chan] =
+ lp_build_intrinsic(ctx->ac.builder,
"llvm.amdgcn.frexp.exp.i32.f64",
+ ctx->ac.i32, &emit_data->args[0], 1, 0);
+}
+
void si_shader_context_init_alu(struct lp_build_tgsi_context *bld_base)
{
lp_set_default_actions(bld_base);
@@ -772,6 +793,10 @@ void si_shader_context_init_alu(struct
lp_build_tgsi_context *bld_base)
bld_base->op_actions[TGSI_OPCODE_DSQRT].intr_name = "llvm.sqrt.f64";
bld_base->op_actions[TGSI_OPCODE_DTRUNC].emit =
build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_DTRUNC].intr_name = "llvm.trunc.f64";
+ bld_base->op_actions[TGSI_OPCODE_DFRACEXP].fetch_args =
dfracexp_fetch_args;
+ bld_base->op_actions[TGSI_OPCODE_DFRACEXP].emit = dfracexp_emit;
+ bld_base->op_actions[TGSI_OPCODE_DLDEXP].emit =
build_tgsi_intrinsic_nomem;
+ bld_base->op_actions[TGSI_OPCODE_DLDEXP].intr_name =
"llvm.amdgcn.ldexp.f64";
bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.exp2.f32";
bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_nomem;
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Mesa (master): r600: cleanup set_occlusion_query_state
Module: Mesa
Branch: master
Commit: c49400a03bbea1319aa2b78fd3abb56e22a8b31d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c49400a03bbea1319aa2b78fd3abb56e22a8b31d
Author: Nicolai Hähnle
Date: Thu Sep 28 21:46:30 2017 +0200
r600: cleanup set_occlusion_query_state
This fixes a warning caused by the fork (note the change in the function
signature):
../../../../../mesa-src/src/gallium/drivers/r600/r600_state_common.c: In
function ‘r600_init_common_state_functions’:
../../../../../mesa-src/src/gallium/drivers/r600/r600_state_common.c:2974:36:
warning: assignment from incompatible pointer type
[-Wincompatible-pointer-types]
rctx->b.set_occlusion_query_state = r600_set_occlusion_query_state;
Reviewed-by: Marek Olšák
---
src/gallium/drivers/r600/r600_pipe_common.h | 3 ---
src/gallium/drivers/r600/r600_query.c| 4 +++-
src/gallium/drivers/r600/r600_state_common.c | 10 --
3 files changed, 3 insertions(+), 14 deletions(-)
diff --git a/src/gallium/drivers/r600/r600_pipe_common.h
b/src/gallium/drivers/r600/r600_pipe_common.h
index 39dd45aace..719efb9bba 100644
--- a/src/gallium/drivers/r600/r600_pipe_common.h
+++ b/src/gallium/drivers/r600/r600_pipe_common.h
@@ -703,9 +703,6 @@ struct r600_common_context {
void (*rebind_buffer)(struct pipe_context *ctx, struct pipe_resource
*buf,
uint64_t old_gpu_address);
- /* Enable or disable occlusion queries. */
- void (*set_occlusion_query_state)(struct pipe_context *ctx, bool
enable);
-
void (*save_qbo_state)(struct pipe_context *ctx, struct r600_qbo_state
*st);
/* This ensures there is enough space in the command stream. */
diff --git a/src/gallium/drivers/r600/r600_query.c
b/src/gallium/drivers/r600/r600_query.c
index 03ff1018a7..4c6311c79e 100644
--- a/src/gallium/drivers/r600/r600_query.c
+++ b/src/gallium/drivers/r600/r600_query.c
@@ -23,6 +23,7 @@
*/
#include "r600_query.h"
+#include "r600_pipe.h"
#include "r600_cs.h"
#include "util/u_memory.h"
#include "util/u_upload_mgr.h"
@@ -710,7 +711,8 @@ static void r600_update_occlusion_query_state(struct
r600_common_context *rctx,
perfect_enable = rctx->num_perfect_occlusion_queries != 0;
if (enable != old_enable || perfect_enable !=
old_perfect_enable) {
- rctx->set_occlusion_query_state(&rctx->b, enable);
+ struct r600_context *ctx = (struct r600_context*)rctx;
+ r600_mark_atom_dirty(ctx, &ctx->db_misc_state.atom);
}
}
}
diff --git a/src/gallium/drivers/r600/r600_state_common.c
b/src/gallium/drivers/r600/r600_state_common.c
index 38f4ca0fc4..7e2b34bf79 100644
--- a/src/gallium/drivers/r600/r600_state_common.c
+++ b/src/gallium/drivers/r600/r600_state_common.c
@@ -2914,15 +2914,6 @@ static void r600_set_active_query_state(struct
pipe_context *ctx, boolean enable
}
}
-static void r600_set_occlusion_query_state(struct pipe_context *ctx,
- bool old_enable,
- bool old_perfect_enable)
-{
- struct r600_context *rctx = (struct r600_context*)ctx;
-
- r600_mark_atom_dirty(rctx, &rctx->db_misc_state.atom);
-}
-
static void r600_need_gfx_cs_space(struct pipe_context *ctx, unsigned num_dw,
bool include_draw_vbo)
{
@@ -2971,6 +2962,5 @@ void r600_init_common_state_functions(struct r600_context
*rctx)
rctx->b.b.set_active_query_state = r600_set_active_query_state;
rctx->b.b.draw_vbo = r600_draw_vbo;
rctx->b.invalidate_buffer = r600_invalidate_buffer;
- rctx->b.set_occlusion_query_state = r600_set_occlusion_query_state;
rctx->b.need_gfx_cs_space = r600_need_gfx_cs_space;
}
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Mesa (master): radeonsi: emit LDEXP opcode
Module: Mesa Branch: master Commit: 061303e4fd17961f52b3cbb0822376d9a586f617 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=061303e4fd17961f52b3cbb0822376d9a586f617 Author: Nicolai Hähnle Date: Fri Sep 15 16:59:09 2017 +0200 radeonsi: emit LDEXP opcode The LLVM intrinsic has existed for a long time. The current name was established in LLVM 3.9. Reviewed-by: Marek Olšák Tested-by: Dieter Nützel --- src/gallium/drivers/radeonsi/si_pipe.c| 2 +- src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c | 2 ++ 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/gallium/drivers/radeonsi/si_pipe.c b/src/gallium/drivers/radeonsi/si_pipe.c index c82aff23b5..9a5b789a2c 100644 --- a/src/gallium/drivers/radeonsi/si_pipe.c +++ b/src/gallium/drivers/radeonsi/si_pipe.c @@ -748,6 +748,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen, case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE: case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS: case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED: + case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: return 1; case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR: @@ -768,7 +769,6 @@ static int si_get_shader_param(struct pipe_screen* pscreen, case PIPE_SHADER_CAP_SUBROUTINES: case PIPE_SHADER_CAP_SUPPORTED_IRS: case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED: - case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED: return 0; } return 0; diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c index 234fd7f23c..ba7ec4f410 100644 --- a/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c +++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_alu.c @@ -800,6 +800,8 @@ void si_shader_context_init_alu(struct lp_build_tgsi_context *bld_base) bld_base->op_actions[TGSI_OPCODE_KILL_IF].fetch_args = kill_if_fetch_args; bld_base->op_actions[TGSI_OPCODE_KILL_IF].emit = kil_emit; bld_base->op_actions[TGSI_OPCODE_KILL].emit = kil_emit; + bld_base->op_actions[TGSI_OPCODE_LDEXP].emit = build_tgsi_intrinsic_nomem; + bld_base->op_actions[TGSI_OPCODE_LDEXP].intr_name = "llvm.amdgcn.ldexp.f32"; bld_base->op_actions[TGSI_OPCODE_LSB].emit = emit_lsb; bld_base->op_actions[TGSI_OPCODE_LG2].emit = build_tgsi_intrinsic_nomem; bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32"; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): glsl/lower_instruction: handle denorms and overflow in ldexp correctly
Module: Mesa
Branch: master
Commit: 93bf9c114b7c54e4faf342810bd848527b7d0a80
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=93bf9c114b7c54e4faf342810bd848527b7d0a80
Author: Nicolai Hähnle
Date: Fri Sep 15 16:39:31 2017 +0200
glsl/lower_instruction: handle denorms and overflow in ldexp correctly
GLSL ES requires both, and while GLSL explicitly doesn't require correct
overflow handling, it does appear to require handling input inf/denorms
correctly.
Fixes dEQP-GLES31.functional.shaders.builtin_functions.precision.ldexp.*
Cc: mesa-sta...@lists.freedesktop.org
Acked-by: Matt Turner
Acked-by: Marek Olšák
Tested-by: Dieter Nützel
---
src/compiler/glsl/lower_instructions.cpp | 171 +++
1 file changed, 107 insertions(+), 64 deletions(-)
diff --git a/src/compiler/glsl/lower_instructions.cpp
b/src/compiler/glsl/lower_instructions.cpp
index 0c1408911d..362562a4af 100644
--- a/src/compiler/glsl/lower_instructions.cpp
+++ b/src/compiler/glsl/lower_instructions.cpp
@@ -365,13 +365,21 @@ lower_instructions_visitor::ldexp_to_arith(ir_expression
*ir)
* into
*
*extracted_biased_exp = rshift(bitcast_f2i(abs(x)), exp_shift);
-*resulting_biased_exp = extracted_biased_exp + exp;
+*resulting_biased_exp = min(extracted_biased_exp + exp, 255);
*
-*if (resulting_biased_exp < 1 || x == 0.0f) {
-* return copysign(0.0, x);
+*if (extracted_biased_exp >= 255)
+* return x; // +/-inf, NaN
+*
+*sign_mantissa = bitcast_f2u(x) & sign_mantissa_mask;
+*
+*if (min(resulting_biased_exp, extracted_biased_exp) < 1)
+* resulting_biased_exp = 0;
+*if (resulting_biased_exp >= 255 ||
+*min(resulting_biased_exp, extracted_biased_exp) < 1) {
+* sign_mantissa &= sign_mask;
*}
*
-*return bitcast_u2f((bitcast_f2u(x) & sign_mantissa_mask) |
+*return bitcast_u2f(sign_mantissa |
* lshift(i2u(resulting_biased_exp), exp_shift));
*
* which we can't actually implement as such, since the GLSL IR doesn't
@@ -379,45 +387,58 @@ lower_instructions_visitor::ldexp_to_arith(ir_expression
*ir)
* using conditional-select:
*
*extracted_biased_exp = rshift(bitcast_f2i(abs(x)), exp_shift);
-*resulting_biased_exp = extracted_biased_exp + exp;
+*resulting_biased_exp = min(extracted_biased_exp + exp, 255);
*
-*is_not_zero_or_underflow = logic_and(nequal(x, 0.0f),
-* gequal(resulting_biased_exp, 1);
-*x = csel(is_not_zero_or_underflow, x, copysign(0.0f, x));
-*resulting_biased_exp = csel(is_not_zero_or_underflow,
-*resulting_biased_exp, 0);
+*sign_mantissa = bitcast_f2u(x) & sign_mantissa_mask;
*
-*return bitcast_u2f((bitcast_f2u(x) & sign_mantissa_mask) |
-* lshift(i2u(resulting_biased_exp), exp_shift));
+*flush_to_zero = lequal(min(resulting_biased_exp,
extracted_biased_exp), 0);
+*resulting_biased_exp = csel(flush_to_zero, 0, resulting_biased_exp)
+*zero_mantissa = logic_or(flush_to_zero,
+* gequal(resulting_biased_exp, 255));
+*sign_mantissa = csel(zero_mantissa, sign_mantissa & sign_mask,
sign_mantissa);
+*
+*result = sign_mantissa |
+* lshift(i2u(resulting_biased_exp), exp_shift));
+*
+*return csel(extracted_biased_exp >= 255, x, bitcast_u2f(result));
+*
+* The definition of ldexp in the GLSL spec says:
+*
+*"If this product is too large to be represented in the
+* floating-point type, the result is undefined."
+*
+* However, the definition of ldexp in the GLSL ES spec does not contain
+* this sentence, so we do need to handle overflow correctly.
+*
+* There is additional language limiting the defined range of exp, but this
+* is merely to allow implementations that store 2^exp in a temporary
+* variable.
*/
const unsigned vec_elem = ir->type->vector_elements;
/* Types */
const glsl_type *ivec = glsl_type::get_instance(GLSL_TYPE_INT, vec_elem, 1);
+ const glsl_type *uvec = glsl_type::get_instance(GLSL_TYPE_UINT, vec_elem,
1);
const glsl_type *bvec = glsl_type::get_instance(GLSL_TYPE_BOOL, vec_elem,
1);
- /* Constants */
- ir_constant *zeroi = ir_constant::zero(ir, ivec);
-
- ir_constant *sign_mask = new(ir) ir_constant(0x8000u, vec_elem);
-
- ir_constant *exp_shift = new(ir) ir_constant(23, vec_elem);
-
/* Temporary variables */
ir_variable *x = new(ir) ir_variable(ir->type, "x", ir_var_temporary);
ir_variable *exp = new(ir) ir_variable(ivec, "exp", ir_var_temporary);
-
- ir_variable *zero_sign_x = new(ir) ir_varia
Mesa (master): tgsi: infer that dst[1] of DFRACEXP is an integer
Module: Mesa
Branch: master
Commit: 2b0bfc51de148147b7a822bb022a7ee2a1c2a28f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b0bfc51de148147b7a822bb022a7ee2a1c2a28f
Author: Nicolai Hähnle
Date: Fri Sep 15 18:47:52 2017 +0200
tgsi: infer that dst[1] of DFRACEXP is an integer
Reviewed-by: Marek Olšák
Tested-by: Dieter Nützel
---
src/gallium/auxiliary/gallivm/lp_bld_tgsi.c | 2 +-
src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c | 4 ++--
src/gallium/auxiliary/tgsi/tgsi_info.c | 5 -
src/gallium/auxiliary/tgsi/tgsi_info.h | 2 +-
src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c | 2 +-
5 files changed, 9 insertions(+), 6 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
index b33976bb64..079a6eed49 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi.c
@@ -201,7 +201,7 @@ void lp_build_fetch_args(
static int get_src_chan_idx(unsigned opcode,
int dst_chan_index)
{
- enum tgsi_opcode_type dtype = tgsi_opcode_infer_dst_type(opcode);
+ enum tgsi_opcode_type dtype = tgsi_opcode_infer_dst_type(opcode, 0);
enum tgsi_opcode_type stype = tgsi_opcode_infer_src_type(opcode, 0);
if (!tgsi_type_is_64bit(dtype) && !tgsi_type_is_64bit(stype))
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
index 435d1075aa..e5d0293b8f 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
@@ -1751,7 +1751,7 @@ emit_store_chan(
struct lp_build_context *float_bld = &bld_base->base;
struct lp_build_context *int_bld = &bld_base->int_bld;
LLVMValueRef indirect_index = NULL;
- enum tgsi_opcode_type dtype =
tgsi_opcode_infer_dst_type(inst->Instruction.Opcode);
+ enum tgsi_opcode_type dtype =
tgsi_opcode_infer_dst_type(inst->Instruction.Opcode, index);
/*
* Apply saturation.
@@ -1917,7 +1917,7 @@ emit_store(
LLVMValueRef dst[4])
{
- enum tgsi_opcode_type dtype =
tgsi_opcode_infer_dst_type(inst->Instruction.Opcode);
+ enum tgsi_opcode_type dtype =
tgsi_opcode_infer_dst_type(inst->Instruction.Opcode, index);
unsigned writemask = inst->Dst[index].Register.WriteMask;
while (writemask) {
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.c
b/src/gallium/auxiliary/tgsi/tgsi_info.c
index 36be463dc8..62b41c031b 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.c
@@ -312,7 +312,10 @@ tgsi_opcode_infer_src_type(uint opcode, uint src_idx)
* infer the destination type of a TGSI opcode.
*/
enum tgsi_opcode_type
-tgsi_opcode_infer_dst_type( uint opcode )
+tgsi_opcode_infer_dst_type( uint opcode, uint dst_idx )
{
+ if (dst_idx == 1 && opcode == TGSI_OPCODE_DFRACEXP)
+ return TGSI_TYPE_SIGNED;
+
return tgsi_opcode_infer_type(opcode);
}
diff --git a/src/gallium/auxiliary/tgsi/tgsi_info.h
b/src/gallium/auxiliary/tgsi/tgsi_info.h
index f3ef46fb4a..8d32f4774b 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_info.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_info.h
@@ -114,7 +114,7 @@ enum tgsi_opcode_type
tgsi_opcode_infer_src_type( uint opcode, uint src_idx );
enum tgsi_opcode_type
-tgsi_opcode_infer_dst_type( uint opcode );
+tgsi_opcode_infer_dst_type( uint opcode, uint dst_idx );
#if defined __cplusplus
}
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
index f0c7803c99..109ec1b5a3 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
@@ -890,7 +890,7 @@ void si_llvm_emit_store(struct lp_build_tgsi_context
*bld_base,
LLVMBuilderRef builder = ctx->gallivm.builder;
LLVMValueRef temp_ptr, temp_ptr2 = NULL;
bool is_vec_store = false;
- enum tgsi_opcode_type dtype =
tgsi_opcode_infer_dst_type(inst->Instruction.Opcode);
+ enum tgsi_opcode_type dtype =
tgsi_opcode_infer_dst_type(inst->Instruction.Opcode, index);
if (dst[0]) {
LLVMTypeKind k = LLVMGetTypeKind(LLVMTypeOf(dst[0]));
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