Mesa (master): radeonsi/nir: fix fs output index

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 6bf1c93fe07603b3bcc9de88ce92cec61954bb4a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6bf1c93fe07603b3bcc9de88ce92cec61954bb4a

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Mon Jan 22 14:41:25 2018 +1100

radeonsi/nir: fix fs output index

Fixes the following piglit tests:

arb_blend_func_extended-fbo-extended-blend
arb_blend_func_extended-fbo-extended-blend-explicit
arb_blend_func_extended-fbo-extended-blend-explicit_gles3
arb_blend_func_extended-fbo-extended-blend-pattern
arb_blend_func_extended-fbo-extended-blend-pattern_gles2
arb_blend_func_extended-fbo-extended-blend-pattern_gles3
arb_blend_func_extended-fbo-extended-blend_gles3
ext_framebuffer_multisample/alpha-to-coverage-dual-src-blend
ext_framebuffer_multisample/alpha-to-one-dual-src-blend

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader_nir.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 97b647434b..8784117833 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -317,6 +317,11 @@ void si_nir_scan_shader(const struct nir_shader *nir,
if (nir->info.stage == MESA_SHADER_FRAGMENT) {

tgsi_get_gl_frag_result_semantic(variable->data.location,
_name, _index);
+
+   /* Adjust for dual source blending */
+   if (variable->data.index > 0) {
+   semantic_index++;
+   }
} else {
tgsi_get_gl_varying_semantic(variable->data.location, 
true,
 _name, 
_index);

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Mesa (master): ac/nir/radeonsi: add ARB_shader_ballot support

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 882af004d886a08c95622a16f98e17f1b28f85db
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=882af004d886a08c95622a16f98e17f1b28f85db

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Mon Jan 22 12:53:45 2018 +1100

ac/nir/radeonsi: add ARB_shader_ballot support

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/amd/common/ac_nir_to_llvm.c  | 37 
 src/gallium/drivers/radeonsi/si_shader_nir.c |  9 +++
 2 files changed, 46 insertions(+)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 53940e2c9e..82f29c0588 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4247,6 +4247,43 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
LLVMValueRef result = NULL;
 
switch (instr->intrinsic) {
+   case nir_intrinsic_ballot:
+   result = ac_build_ballot(>ac, get_src(ctx, instr->src[0]));
+   break;
+   case nir_intrinsic_read_invocation:
+   case nir_intrinsic_read_first_invocation: {
+   LLVMValueRef args[2];
+
+   /* Value */
+   args[0] = get_src(ctx, instr->src[0]);
+
+   unsigned num_args;
+   const char *intr_name;
+   if (instr->intrinsic == nir_intrinsic_read_invocation) {
+   num_args = 2;
+   intr_name = "llvm.amdgcn.readlane";
+
+   /* Invocation */
+   args[1] = get_src(ctx, instr->src[1]);
+   } else {
+   num_args = 1;
+   intr_name = "llvm.amdgcn.readfirstlane";
+   }
+
+   /* We currently have no other way to prevent LLVM from lifting 
the icmp
+* calls to a dominating basic block.
+*/
+   ac_build_optimization_barrier(>ac, [0]);
+
+   result = ac_build_intrinsic(>ac, intr_name,
+   ctx->ac.i32, args, num_args,
+   AC_FUNC_ATTR_READNONE |
+   AC_FUNC_ATTR_CONVERGENT);
+   break;
+   }
+   case nir_intrinsic_load_subgroup_invocation:
+   result = ac_get_thread_id(>ac);
+   break;
case nir_intrinsic_load_work_group_id: {
LLVMValueRef values[3];
 
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index e26994c06b..97b647434b 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -505,6 +505,15 @@ si_lower_nir(struct si_shader_selector* sel)
};
NIR_PASS_V(sel->nir, nir_lower_tex, _tex_options);
 
+   const nir_lower_subgroups_options subgroups_options = {
+   .subgroup_size = 64,
+   .ballot_bit_size = 32,
+   .lower_to_scalar = true,
+   .lower_subgroup_masks = true,
+   .lower_vote_trivial = false,
+   };
+   NIR_PASS_V(sel->nir, nir_lower_subgroups, _options);
+
bool progress;
do {
progress = false;

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Mesa (master): radeonsi/nir: add nir_intrinsic_load_sample_mask_in to ir scan

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: c6a0ce7e5479f9bb8ed6135df685b0e34681c189
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c6a0ce7e5479f9bb8ed6135df685b0e34681c189

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Fri Jan 19 21:52:24 2018 +1100

radeonsi/nir: add nir_intrinsic_load_sample_mask_in to ir scan

Fixes a bunch of ARB_sample_shading piglit tests.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader_nir.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 9a15271bb0..56594fcd0e 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -98,6 +98,9 @@ static void scan_instruction(struct tgsi_shader_info *info,
case nir_intrinsic_load_primitive_id:
info->uses_primid = 1;
break;
+   case nir_intrinsic_load_sample_mask_in:
+   info->reads_samplemask = true;
+   break;
case nir_intrinsic_load_tess_level_inner:
case nir_intrinsic_load_tess_level_outer:
info->reads_tess_factors = true;

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Mesa (master): ac: fix visit_ssa_undef() for doubles

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 3bccb5dba9415f98f7a3dbb7c43a5eace64b4ec6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3bccb5dba9415f98f7a3dbb7c43a5eace64b4ec6

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Thu Jan 18 12:01:33 2018 +1100

ac: fix visit_ssa_undef() for doubles

V2: use LLVMIntTypeInContext()

Fixes: f4e499ec7914 "radv: add initial non-conformant radv vulkan driver"

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>

---

 src/amd/common/ac_nir_to_llvm.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 02a46dab4d..cd400376a0 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -5055,12 +5055,13 @@ static void visit_ssa_undef(struct ac_nir_context *ctx,
const nir_ssa_undef_instr *instr)
 {
unsigned num_components = instr->def.num_components;
+   LLVMTypeRef type = LLVMIntTypeInContext(ctx->ac.context, 
instr->def.bit_size);
LLVMValueRef undef;
 
if (num_components == 1)
-   undef = LLVMGetUndef(ctx->ac.i32);
+   undef = LLVMGetUndef(type);
else {
-   undef = LLVMGetUndef(LLVMVectorType(ctx->ac.i32, 
num_components));
+   undef = LLVMGetUndef(LLVMVectorType(type, num_components));
}
_mesa_hash_table_insert(ctx->defs, >def, undef);
 }

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Mesa (master): ac: fix nir_intrinsic_get_buffer_size for radeonsi

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 409e15f26fd245dfa6645214c433cfe4e7b9a988
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=409e15f26fd245dfa6645214c433cfe4e7b9a988

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Jan 16 18:02:37 2018 +1100

ac: fix nir_intrinsic_get_buffer_size for radeonsi

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/amd/common/ac_nir_to_llvm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 25ce06138b..1dc64f87cc 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2404,9 +2404,9 @@ static LLVMValueRef visit_load_push_constant(struct 
nir_to_llvm_context *ctx,
 static LLVMValueRef visit_get_buffer_size(struct ac_nir_context *ctx,
   const nir_intrinsic_instr *instr)
 {
-   LLVMValueRef ptr = get_src(ctx, instr->src[0]);
+   LLVMValueRef index = get_src(ctx, instr->src[0]);
 
-   return get_buffer_size(ctx, LLVMBuildLoad(ctx->ac.builder, ptr, ""), 
false);
+   return get_buffer_size(ctx, ctx->abi->load_ssbo(ctx->abi, index, 
false), false);
 }
 static void visit_store_ssbo(struct ac_nir_context *ctx,
  nir_intrinsic_instr *instr)

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Mesa (master): mesa/st: translate SO info in glsl_to_nir() case

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 4c69961daf45a6a64970e5831bd362307dca0cb2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c69961daf45a6a64970e5831bd362307dca0cb2

Author: Rob Clark <robdcl...@gmail.com>
Date:   Wed Jan 10 03:54:14 2018 +0100

mesa/st: translate SO info in glsl_to_nir() case

This was handled for VS, but not for GS.

Fixes for gallium drivers using nir:
spec@arb_gpu_shader5@arb_gpu_shader5-xfb-streams-without-invocations
spec@arb_gpu_shader5@arb_gpu_shader5-xfb-streams*
spec@arb_transform_feedback3@arb_transform_feedback3-ext_interleaved_two_bufs_gs*
spec@ext_transform_feedback@geometry-shaders-basic
spec@ext_transform_feedback@* use_gs
spec@glsl-1.50@execution@geometry@primitive-id*
spec@glsl-1.50@execution@geometry@tri-strip-ordering-with-prim-restart 
gl_triangle_strip *
spec@glsl-1.50@transform-feedback-builtins
spec@glsl-1.50@transform-feedback-type-and-size

v2: don't call st_translate_program_stream_output) for TCS

v3: drop scanning patch outputs as TCS can't output xfb

Signed-off-by: Rob Clark <robdcl...@gmail.com>
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>
Tested-by: Karol Herbst <kher...@redhat.com>

---

 src/mesa/state_tracker/st_program.c | 47 +
 1 file changed, 43 insertions(+), 4 deletions(-)

diff --git a/src/mesa/state_tracker/st_program.c 
b/src/mesa/state_tracker/st_program.c
index 77136edbb9..883813d6c0 100644
--- a/src/mesa/state_tracker/st_program.c
+++ b/src/mesa/state_tracker/st_program.c
@@ -1425,6 +1425,40 @@ st_translate_program_common(struct st_context *st,
}
 }
 
+/**
+ * Update stream-output info for GS/TCS/TES.  Normally this is done in
+ * st_translate_program_common() but that is not called for glsl_to_nir
+ * case.
+ */
+static void
+st_translate_program_stream_output(struct gl_program *prog,
+   struct pipe_stream_output_info 
*stream_output)
+{
+   if (!prog->sh.LinkedTransformFeedback)
+  return;
+
+   ubyte outputMapping[VARYING_SLOT_TESS_MAX];
+   GLuint attr;
+   uint num_outputs = 0;
+
+   memset(outputMapping, 0, sizeof(outputMapping));
+
+   /*
+* Determine number of outputs, the (default) output register
+* mapping and the semantic information for each output.
+*/
+   for (attr = 0; attr < VARYING_SLOT_MAX; attr++) {
+  if (prog->info.outputs_written & BITFIELD64_BIT(attr)) {
+ GLuint slot = num_outputs++;
+
+ outputMapping[attr] = slot;
+  }
+   }
+
+   st_translate_stream_output_info2(prog->sh.LinkedTransformFeedback,
+outputMapping,
+stream_output);
+}
 
 /**
  * Translate a geometry program to create a new variant.
@@ -1436,8 +1470,10 @@ st_translate_geometry_program(struct st_context *st,
struct ureg_program *ureg;
 
/* We have already compiled to NIR so just return */
-   if (stgp->shader_program)
+   if (stgp->shader_program) {
+  st_translate_program_stream_output(>Base, 
>tgsi.stream_output);
   return true;
+   }
 
ureg = ureg_create_with_screen(PIPE_SHADER_GEOMETRY, st->pipe->screen);
if (ureg == NULL)
@@ -1493,6 +1529,7 @@ st_get_basic_variant(struct st_context *st,
tgsi.ir.nir = nir_shader_clone(NULL, prog->tgsi.ir.nir);
st_finalize_nir(st, >Base, prog->shader_program,
 tgsi.ir.nir);
+tgsi.stream_output = prog->tgsi.stream_output;
 } else
tgsi = prog->tgsi;
  /* fill in new variant */
@@ -1533,7 +1570,7 @@ st_translate_tessctrl_program(struct st_context *st,
 {
struct ureg_program *ureg;
 
-   /* We have already compiler to NIR so just return */
+   /* We have already compiled to NIR so just return */
if (sttcp->shader_program)
   return true;
 
@@ -1562,9 +1599,11 @@ st_translate_tesseval_program(struct st_context *st,
 {
struct ureg_program *ureg;
 
-   /* We have already compiler to NIR so just return */
-   if (sttep->shader_program)
+   /* We have already compiled to NIR so just return */
+   if (sttep->shader_program) {
+  st_translate_program_stream_output(>Base, 
>tgsi.stream_output);
   return true;
+   }
 
ureg = ureg_create_with_screen(PIPE_SHADER_TESS_EVAL, st->pipe->screen);
if (ureg == NULL)

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Mesa (master): ac: fix buffer overflow bug in 64bit SSBO loads

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: e2b9296146746635cd631c5212ae56f0cd270820
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e2b9296146746635cd631c5212ae56f0cd270820

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Jan 16 17:45:30 2018 +1100

ac: fix buffer overflow bug in 64bit SSBO loads

Fixes: 441ee1e65b04 "radv/ac: Implement Float64 SSBO loads"

Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/amd/common/ac_nir_to_llvm.c | 5 -
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 1dc64f87cc..e07330ca5c 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2588,8 +2588,11 @@ static LLVMValueRef visit_load_buffer(struct 
ac_nir_context *ctx,
ctx->ac.i1false,
};
 
-   results[i] = ac_build_intrinsic(>ac, load_name, data_type, 
params, 5, 0);
+   int idx = i;
+   if (instr->dest.ssa.bit_size == 64)
+   idx = i > 1 ? 1 : 0;
 
+   results[idx] = ac_build_intrinsic(>ac, load_name, 
data_type, params, 5, 0);
}
 
assume(results[0]);

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Mesa (master): ac: tidy up array indexing logic

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 9248f72c4e8513fdf4ac4cac4b78c9f06621046a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9248f72c4e8513fdf4ac4cac4b78c9f06621046a

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Thu Jan 18 15:46:35 2018 +1100

ac: tidy up array indexing logic

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>

---

 src/amd/common/ac_nir_to_llvm.c | 6 +-
 1 file changed, 1 insertion(+), 5 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index e07330ca5c..c53fb5cb1c 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2588,11 +2588,7 @@ static LLVMValueRef visit_load_buffer(struct 
ac_nir_context *ctx,
ctx->ac.i1false,
};
 
-   int idx = i;
-   if (instr->dest.ssa.bit_size == 64)
-   idx = i > 1 ? 1 : 0;
-
-   results[idx] = ac_build_intrinsic(>ac, load_name, 
data_type, params, 5, 0);
+   results[i > 0 ? 1 : 0] = ac_build_intrinsic(>ac, 
load_name, data_type, params, 5, 0);
}
 
assume(results[0]);

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Mesa (master): ac/radeonsi: add tcs load outputs support

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 9622b445c87e6099a3cafe5b868fa5820dfdfd3f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9622b445c87e6099a3cafe5b868fa5820dfdfd3f

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Jan  9 12:12:45 2018 +1100

ac/radeonsi: add tcs load outputs support

The code to load outputs is essentially the same as load inputs
so we make the interface more generic to maximise code sharing.

We will make use of the new support in the following patch.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/amd/common/ac_nir_to_llvm.c   | 20 ++-
 src/amd/common/ac_shader_abi.h| 21 ++--
 src/gallium/drivers/radeonsi/si_shader.c  | 42 +++
 src/gallium/drivers/radeonsi/si_shader_internal.h |  3 +-
 4 files changed, 51 insertions(+), 35 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 5a8ddf13d7..d94a010ca3 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2850,7 +2850,8 @@ load_tcs_input(struct ac_shader_abi *abi,
   unsigned component,
   unsigned num_components,
   bool is_patch,
-  bool is_compact)
+  bool is_compact,
+  bool load_input)
 {
struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
LLVMValueRef dw_addr, stride;
@@ -2999,7 +3000,8 @@ load_tes_input(struct ac_shader_abi *abi,
   unsigned component,
   unsigned num_components,
   bool is_patch,
-  bool is_compact)
+  bool is_compact,
+  bool load_input)
 {
struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
LLVMValueRef buf_addr;
@@ -3149,11 +3151,11 @@ static LLVMValueRef visit_load_var(struct 
ac_nir_context *ctx,
 false, NULL, is_patch ? NULL : 
_index,
 _index, _index);
 
-   result = ctx->abi->load_tess_inputs(ctx->abi, 
vertex_index, indir_index,
-   const_index, 
location, driver_location,
-   
instr->variables[0]->var->data.location_frac,
-   
instr->num_components,
-   is_patch, 
is_compact);
+   result = ctx->abi->load_tess_varyings(ctx->abi, 
vertex_index, indir_index,
+ const_index, 
location, driver_location,
+ 
instr->variables[0]->var->data.location_frac,
+ 
instr->num_components,
+ is_patch, 
is_compact, true);
return LLVMBuildBitCast(ctx->ac.builder, result, 
get_def_type(ctx, >dest.ssa), "");
}
 
@@ -6742,12 +6744,12 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
ctx.tcs_patch_outputs_read = 
shaders[i]->info.patch_outputs_read;
-   ctx.abi.load_tess_inputs = load_tcs_input;
+   ctx.abi.load_tess_varyings = load_tcs_input;
ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
ctx.abi.store_tcs_outputs = store_tcs_output;
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
ctx.tes_primitive_mode = 
shaders[i]->info.tess.primitive_mode;
-   ctx.abi.load_tess_inputs = load_tes_input;
+   ctx.abi.load_tess_varyings = load_tes_input;
ctx.abi.load_tess_coord = load_tess_coord;
ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index 06e61207ec..3e9e7a4786 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -76,16 +76,17 @@ struct ac_shader_abi {
unsigned const_index,
LLVMTypeRef type);
 
-   LLVMValueRef (*load_tess_inputs)(struct ac_shader_abi *abi,
-LLVMValueRef vertex_index,
-LLVMValueRef param_index,
-

Mesa (master): radeonsi/nir: add some missing tcs bits to the nir scan pass

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: b282207c323d32deb23037463ac9d6886f15f6cf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b282207c323d32deb23037463ac9d6886f15f6cf

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Jan 10 13:52:29 2018 +1100

radeonsi/nir: add some missing tcs bits to the nir scan pass

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader_nir.c | 14 ++
 1 file changed, 14 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index d5b8f835b9..9a15271bb0 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -399,6 +399,20 @@ void si_nir_scan_shader(const struct nir_shader *nir,
info->writes_position = true;
break;
}
+
+   if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
+   switch (semantic_name) {
+   case TGSI_SEMANTIC_PATCH:
+   info->reads_perpatch_outputs = true;
+   break;
+   case TGSI_SEMANTIC_TESSINNER:
+   case TGSI_SEMANTIC_TESSOUTER:
+   info->reads_tessfactor_outputs = true;
+   break;
+   default:
+   info->reads_pervertex_outputs = true;
+   }
+   }
}
 
info->num_outputs = num_outputs;

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Mesa (master): ac: rework load_tcs_{inputs,outputs}

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 7898eb9a60c1ad4fb03a2fc3453c6778604e8742
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7898eb9a60c1ad4fb03a2fc3453c6778604e8742

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Jan  9 13:50:08 2018 +1100

ac: rework load_tcs_{inputs,outputs}

This shares more code and calls the new shared load_tess_varyings()
abi so that the radeonsi nir path now supports tcs output loads.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/amd/common/ac_nir_to_llvm.c | 126 +---
 1 file changed, 53 insertions(+), 73 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index d94a010ca3..25ce06138b 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2841,73 +2841,45 @@ get_dw_address(struct nir_to_llvm_context *ctx,
 }
 
 static LLVMValueRef
-load_tcs_input(struct ac_shader_abi *abi,
-  LLVMValueRef vertex_index,
-  LLVMValueRef indir_index,
-  unsigned const_index,
-  unsigned location,
-  unsigned driver_location,
-  unsigned component,
-  unsigned num_components,
-  bool is_patch,
-  bool is_compact,
-  bool load_input)
+load_tcs_varyings(struct ac_shader_abi *abi,
+ LLVMValueRef vertex_index,
+ LLVMValueRef indir_index,
+ unsigned const_index,
+ unsigned location,
+ unsigned driver_location,
+ unsigned component,
+ unsigned num_components,
+ bool is_patch,
+ bool is_compact,
+ bool load_input)
 {
struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
LLVMValueRef dw_addr, stride;
LLVMValueRef value[4], result;
unsigned param = shader_io_get_unique_index(location);
 
-   stride = unpack_param(>ac, ctx->tcs_in_layout, 13, 8);
-   dw_addr = get_tcs_in_current_patch_offset(ctx);
-   dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, 
vertex_index, stride,
-indir_index);
-
-   for (unsigned i = 0; i < num_components + component; i++) {
-   value[i] = ac_lds_load(>ac, dw_addr);
-   dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
-  ctx->ac.i32_1, "");
-   }
-   result = ac_build_varying_gather_values(>ac, value, 
num_components, component);
-   return result;
-}
-
-static LLVMValueRef
-load_tcs_output(struct nir_to_llvm_context *ctx,
-  nir_intrinsic_instr *instr)
-{
-   LLVMValueRef dw_addr;
-   LLVMValueRef stride = NULL;
-   LLVMValueRef value[4], result;
-   LLVMValueRef vertex_index = NULL;
-   LLVMValueRef indir_index = NULL;
-   unsigned const_index = 0;
-   unsigned param;
-   const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, 
ctx->stage);
-   const bool is_compact = instr->variables[0]->var->data.compact;
-   param = 
shader_io_get_unique_index(instr->variables[0]->var->data.location);
-   get_deref_offset(ctx->nir, instr->variables[0],
-false, NULL, per_vertex ? _index : NULL,
-_index, _index);
-
-   if (!instr->variables[0]->var->data.patch) {
-   stride = unpack_param(>ac, ctx->tcs_out_layout, 13, 8);
-   dw_addr = get_tcs_out_current_patch_offset(ctx);
+   if (load_input) {
+   stride = unpack_param(>ac, ctx->tcs_in_layout, 13, 8);
+   dw_addr = get_tcs_in_current_patch_offset(ctx);
} else {
-   dw_addr = get_tcs_out_current_patch_data_offset(ctx);
+   if (!is_patch) {
+   stride = unpack_param(>ac, ctx->tcs_out_layout, 
13, 8);
+   dw_addr = get_tcs_out_current_patch_offset(ctx);
+   } else {
+   dw_addr = get_tcs_out_current_patch_data_offset(ctx);
+   stride = NULL;
+   }
}
 
dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, 
vertex_index, stride,
 indir_index);
 
-   unsigned comp = instr->variables[0]->var->data.location_frac;
-   for (unsigned i = comp; i < instr->num_components + comp; i++) {
+   for (unsigned i = 0; i < num_components + component; i++) {
value[i] = ac_lds_load(>ac, dw_addr);
dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
   ctx->ac.i32_1, "");
}
-   result = ac_build_varying_gather_values(>ac, value, 
instr->num_components, comp);
-   r

Mesa (master): radeonsi: bump glsl version to 450 for nir backend

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 1256ab18c12955497e0564b606232473c8feec34
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1256ab18c12955497e0564b606232473c8feec34

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Fri Jan 12 12:38:13 2018 +1100

radeonsi: bump glsl version to 450 for nir backend

We still have more work to do but piglit results are looking
pretty good.

At GLSL 1.50 we have 30647/31118 piglit tests passing.
At GLSL 4.50 we have 37927/38551 piglit tests passing.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/gallium/drivers/radeonsi/si_get.c | 7 +--
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c
index caf6e9d19f..7072cfc1f5 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -226,8 +226,6 @@ static int si_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
return 4;
 
case PIPE_CAP_GLSL_FEATURE_LEVEL:
-   if (sscreen->debug_flags & DBG(NIR))
-   return 150; /* no tessellation shaders yet */
if (si_have_tgsi_compute(sscreen))
return 450;
return 420;
@@ -451,10 +449,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
return 32;
case PIPE_SHADER_CAP_PREFERRED_IR:
-   if (sscreen->debug_flags & DBG(NIR) &&
-   (shader == PIPE_SHADER_VERTEX ||
-shader == PIPE_SHADER_GEOMETRY ||
-shader == PIPE_SHADER_FRAGMENT))
+   if (sscreen->debug_flags & DBG(NIR))
return PIPE_SHADER_IR_NIR;
return PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:

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Mesa (master): st/glsl_to_tgsi: store num_tgsi_tokens in st_*_program

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: c69b0dd6817b3321d0d9ccfd1c3d44b44277c736
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c69b0dd6817b3321d0d9ccfd1c3d44b44277c736

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Nov 28 21:43:12 2017 +1100

st/glsl_to_tgsi: store num_tgsi_tokens in st_*_program

We will need this for ARB_get_program_binary binary support.

Tested-by: Dieter Nützel <die...@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/mesa/state_tracker/st_program.c  | 21 -
 src/mesa/state_tracker/st_program.h  | 12 
 src/mesa/state_tracker/st_shader_cache.c | 15 +--
 src/mesa/state_tracker/st_shader_cache.h |  3 +--
 4 files changed, 34 insertions(+), 17 deletions(-)

diff --git a/src/mesa/state_tracker/st_program.c 
b/src/mesa/state_tracker/st_program.c
index 05e6042f42..9f8bf5f76f 100644
--- a/src/mesa/state_tracker/st_program.c
+++ b/src/mesa/state_tracker/st_program.c
@@ -534,13 +534,12 @@ st_translate_vertex_program(struct st_context *st,
   return false;
}
 
-   unsigned num_tokens;
-   stvp->tgsi.tokens = ureg_get_tokens(ureg, _tokens);
+   stvp->tgsi.tokens = ureg_get_tokens(ureg, >num_tgsi_tokens);
ureg_destroy(ureg);
 
if (stvp->glsl_to_tgsi) {
   stvp->glsl_to_tgsi = NULL;
-  st_store_tgsi_in_disk_cache(st, >Base, NULL, num_tokens);
+  st_store_tgsi_in_disk_cache(st, >Base, NULL);
}
 
return stvp->tgsi.tokens != NULL;
@@ -992,13 +991,12 @@ st_translate_fragment_program(struct st_context *st,
 fs_output_semantic_name,
 fs_output_semantic_index);
 
-   unsigned num_tokens;
-   stfp->tgsi.tokens = ureg_get_tokens(ureg, _tokens);
+   stfp->tgsi.tokens = ureg_get_tokens(ureg, >num_tgsi_tokens);
ureg_destroy(ureg);
 
if (stfp->glsl_to_tgsi) {
   stfp->glsl_to_tgsi = NULL;
-  st_store_tgsi_in_disk_cache(st, >Base, NULL, num_tokens);
+  st_store_tgsi_in_disk_cache(st, >Base, NULL);
}
 
return stfp->tgsi.tokens != NULL;
@@ -1400,15 +1398,20 @@ st_translate_program_common(struct st_context *st,
 output_semantic_name,
 output_semantic_index);
 
-   unsigned num_tokens;
-   out_state->tokens = ureg_get_tokens(ureg, _tokens);
+   if (tgsi_processor == PIPE_SHADER_COMPUTE) {
+  struct st_compute_program *stcp = (struct st_compute_program *) prog;
+  out_state->tokens = ureg_get_tokens(ureg, >num_tgsi_tokens);
+   } else {
+  struct st_common_program *stcp = (struct st_common_program *) prog;
+  out_state->tokens = ureg_get_tokens(ureg, >num_tgsi_tokens);
+   }
ureg_destroy(ureg);
 
st_translate_stream_output_info(glsl_to_tgsi,
outputMapping,
_state->stream_output);
 
-   st_store_tgsi_in_disk_cache(st, prog, out_state, num_tokens);
+   st_store_tgsi_in_disk_cache(st, prog, out_state);
 
if ((ST_DEBUG & DEBUG_TGSI) && (ST_DEBUG & DEBUG_MESA)) {
   _mesa_print_program(prog);
diff --git a/src/mesa/state_tracker/st_program.h 
b/src/mesa/state_tracker/st_program.h
index 0e6c8e00c6..a520ffbecb 100644
--- a/src/mesa/state_tracker/st_program.h
+++ b/src/mesa/state_tracker/st_program.h
@@ -150,6 +150,9 @@ struct st_fragment_program
struct gl_shader_program *shader_program;
 
struct st_fp_variant *variants;
+
+   /* Used by the shader cache and ARB_get_program_binary */
+   unsigned num_tgsi_tokens;
 };
 
 
@@ -222,6 +225,9 @@ struct st_vertex_program
 
/** SHA1 hash of linked tgsi shader program, used for on-disk cache */
unsigned char sha1[20];
+
+   /* Used by the shader cache and ARB_get_program_binary */
+   unsigned num_tgsi_tokens;
 };
 
 
@@ -264,6 +270,9 @@ struct st_common_program
 
/** SHA1 hash of linked tgsi shader program, used for on-disk cache */
unsigned char sha1[20];
+
+   /* Used by the shader cache and ARB_get_program_binary */
+   unsigned num_tgsi_tokens;
 };
 
 
@@ -284,6 +293,9 @@ struct st_compute_program
 
/** SHA1 hash of linked tgsi shader program, used for on-disk cache */
unsigned char sha1[20];
+
+   /* Used by the shader cache and ARB_get_program_binary */
+   unsigned num_tgsi_tokens;
 };
 
 
diff --git a/src/mesa/state_tracker/st_shader_cache.c 
b/src/mesa/state_tracker/st_shader_cache.c
index a5e33133b3..a9413fb053 100644
--- a/src/mesa/state_tracker/st_shader_cache.c
+++ b/src/mesa/state_tracker/st_shader_cache.c
@@ -56,8 +56,7 @@ write_tgsi_to_cache(struct blob *blob, struct 
pipe_shader_state *tgsi,
  */
 void
 st_store_tgsi_in_disk_cache(struct st_context *st, struct gl_program *prog,
-struct pipe_shader_state *out_state,
-unsigned num_tokens)
+struct pipe_shader_state *out_stat

Mesa (master): st/glsl_to_tgsi: add (de)serialise program helpers

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 9eebc55cc206d7400cc33e5faa52b51a1b4b5b8b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9eebc55cc206d7400cc33e5faa52b51a1b4b5b8b

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Nov 28 16:00:50 2017 +1100

st/glsl_to_tgsi: add (de)serialise program helpers

These will be shared between the on-disk shader cache and
ARB_get_program_binary.

Tested-by: Dieter Nützel <die...@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/mesa/state_tracker/st_shader_cache.c | 265 ---
 src/mesa/state_tracker/st_shader_cache.h |   8 +
 2 files changed, 146 insertions(+), 127 deletions(-)

diff --git a/src/mesa/state_tracker/st_shader_cache.c 
b/src/mesa/state_tracker/st_shader_cache.c
index 1d9b172755..62d62f7611 100644
--- a/src/mesa/state_tracker/st_shader_cache.c
+++ b/src/mesa/state_tracker/st_shader_cache.c
@@ -50,22 +50,9 @@ write_tgsi_to_cache(struct blob *blob, const struct 
tgsi_token *tokens,
prog->driver_cache_blob_size = blob->size;
 }
 
-/**
- * Store tgsi and any other required state in on-disk shader cache.
- */
 void
-st_store_tgsi_in_disk_cache(struct st_context *st, struct gl_program *prog)
+st_serialise_tgsi_program(struct gl_context *ctx, struct gl_program *prog)
 {
-   if (!st->ctx->Cache)
-  return;
-
-   /* Exit early when we are dealing with a ff shader with no source file to
-* generate a source from.
-*/
-   static const char zero[sizeof(prog->sh.data->sha1)] = {0};
-   if (memcmp(prog->sh.data->sha1, zero, sizeof(prog->sh.data->sha1)) == 0)
-  return;
-
struct blob blob;
blob_init();
 
@@ -112,12 +99,31 @@ st_store_tgsi_in_disk_cache(struct st_context *st, struct 
gl_program *prog)
   unreachable("Unsupported stage");
}
 
+   blob_finish();
+}
+
+/**
+ * Store tgsi and any other required state in on-disk shader cache.
+ */
+void
+st_store_tgsi_in_disk_cache(struct st_context *st, struct gl_program *prog)
+{
+   if (!st->ctx->Cache)
+  return;
+
+   /* Exit early when we are dealing with a ff shader with no source file to
+* generate a source from.
+*/
+   static const char zero[sizeof(prog->sh.data->sha1)] = {0};
+   if (memcmp(prog->sh.data->sha1, zero, sizeof(prog->sh.data->sha1)) == 0)
+  return;
+
+   st_serialise_tgsi_program(st->ctx, prog);
+
if (st->ctx->_Shader->Flags & GLSL_CACHE_INFO) {
   fprintf(stderr, "putting %s tgsi_tokens in cache\n",
   _mesa_shader_stage_to_string(prog->info.stage));
}
-
-   blob_finish();
 }
 
 static void
@@ -138,159 +144,164 @@ read_tgsi_from_cache(struct blob_reader *blob_reader,
blob_copy_bytes(blob_reader, (uint8_t *) *tokens, tokens_size);
 }
 
-bool
-st_load_tgsi_from_disk_cache(struct gl_context *ctx,
- struct gl_shader_program *prog)
+void
+st_deserialise_tgsi_program(struct gl_context *ctx,
+struct gl_shader_program *shProg,
+struct gl_program *prog)
 {
-   if (!ctx->Cache)
-  return false;
-
-   /* If we didn't load the GLSL metadata from cache then we could not have
-* loaded the tgsi either.
-*/
-   if (prog->data->LinkStatus != linking_skipped)
-  return false;
-
struct st_context *st = st_context(ctx);
-   for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
-  if (prog->_LinkedShaders[i] == NULL)
- continue;
+   size_t size = prog->driver_cache_blob_size;
+   uint8_t *buffer = (uint8_t *) prog->driver_cache_blob;
 
-  struct gl_program *glprog = prog->_LinkedShaders[i]->Program;
+   struct blob_reader blob_reader;
+   blob_reader_init(_reader, buffer, size);
 
-  size_t size = glprog->driver_cache_blob_size;
-  uint8_t *buffer = (uint8_t *) glprog->driver_cache_blob;
+   switch (prog->info.stage) {
+   case MESA_SHADER_VERTEX: {
+  struct st_vertex_program *stvp = (struct st_vertex_program *) prog;
 
-  struct blob_reader blob_reader;
-  blob_reader_init(_reader, buffer, size);
+  st_release_vp_variants(st, stvp);
 
-  switch (glprog->info.stage) {
-  case MESA_SHADER_VERTEX: {
- struct st_vertex_program *stvp = (struct st_vertex_program *) glprog;
+  stvp->num_inputs = blob_read_uint32(_reader);
+  blob_copy_bytes(_reader, (uint8_t *) stvp->index_to_input,
+  sizeof(stvp->index_to_input));
+  blob_copy_bytes(_reader, (uint8_t *) stvp->result_to_output,
+  sizeof(stvp->result_to_output));
 
- st_release_vp_variants(st, stvp);
+  read_stream_out_from_cache(_reader, >tgsi);
+  read_tgsi_from_cache(_reader, >tgsi.tokens);
 
- stvp->num_inputs = blob_read_uint32(_reader);
- blob_copy_bytes(_reader, (uint8_t *) stvp->index_to_input,
- 

Mesa (master): st/glsl_to_tgsi: add st_get_program_binary_driver_sha1() helper

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: a34262aed77dc358c29b492139796a9847dd37d1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a34262aed77dc358c29b492139796a9847dd37d1

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Nov 28 22:28:31 2017 +1100

st/glsl_to_tgsi: add st_get_program_binary_driver_sha1() helper

This will be used by ARB_get_program_binary.

Tested-by: Dieter Nützel <die...@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/mesa/state_tracker/st_shader_cache.c | 6 ++
 src/mesa/state_tracker/st_shader_cache.h | 3 +++
 2 files changed, 9 insertions(+)

diff --git a/src/mesa/state_tracker/st_shader_cache.c 
b/src/mesa/state_tracker/st_shader_cache.c
index 62d62f7611..a971b0d7ee 100644
--- a/src/mesa/state_tracker/st_shader_cache.c
+++ b/src/mesa/state_tracker/st_shader_cache.c
@@ -30,6 +30,12 @@
 #include "program/ir_to_mesa.h"
 #include "util/u_memory.h"
 
+void
+st_get_program_binary_driver_sha1(struct gl_context *ctx, uint8_t *sha1)
+{
+   disk_cache_compute_key(ctx->Cache, NULL, 0, sha1);
+}
+
 static void
 write_stream_out_to_cache(struct blob *blob,
   struct pipe_shader_state *tgsi)
diff --git a/src/mesa/state_tracker/st_shader_cache.h 
b/src/mesa/state_tracker/st_shader_cache.h
index 358c6ecef8..488035c7ed 100644
--- a/src/mesa/state_tracker/st_shader_cache.h
+++ b/src/mesa/state_tracker/st_shader_cache.h
@@ -33,6 +33,9 @@ extern "C" {
 #endif
 
 void
+st_get_program_binary_driver_sha1(struct gl_context *ctx, uint8_t *sha1);
+
+void
 st_serialise_tgsi_program(struct gl_context *ctx, struct gl_program *prog);
 
 void

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Mesa (master): st/glsl_to_tgsi: stop passing pipe_shader_state to st_store_tgsi_in_disk_cache()

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: dbf7e483b4b289fa39154597846df6a2ce10b094
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dbf7e483b4b289fa39154597846df6a2ce10b094

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Nov 28 22:02:17 2017 +1100

st/glsl_to_tgsi: stop passing pipe_shader_state to st_store_tgsi_in_disk_cache()

We can instead just get this from st_*_program.

V2: store tokens to to st_compute_program before attempting to
write to cache (fixes crash).

Tested-by: Dieter Nützel <die...@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/mesa/state_tracker/st_program.c  |  8 
 src/mesa/state_tracker/st_shader_cache.c | 22 --
 src/mesa/state_tracker/st_shader_cache.h |  3 +--
 3 files changed, 17 insertions(+), 16 deletions(-)

diff --git a/src/mesa/state_tracker/st_program.c 
b/src/mesa/state_tracker/st_program.c
index 9f8bf5f76f..77136edbb9 100644
--- a/src/mesa/state_tracker/st_program.c
+++ b/src/mesa/state_tracker/st_program.c
@@ -539,7 +539,7 @@ st_translate_vertex_program(struct st_context *st,
 
if (stvp->glsl_to_tgsi) {
   stvp->glsl_to_tgsi = NULL;
-  st_store_tgsi_in_disk_cache(st, >Base, NULL);
+  st_store_tgsi_in_disk_cache(st, >Base);
}
 
return stvp->tgsi.tokens != NULL;
@@ -996,7 +996,7 @@ st_translate_fragment_program(struct st_context *st,
 
if (stfp->glsl_to_tgsi) {
   stfp->glsl_to_tgsi = NULL;
-  st_store_tgsi_in_disk_cache(st, >Base, NULL);
+  st_store_tgsi_in_disk_cache(st, >Base);
}
 
return stfp->tgsi.tokens != NULL;
@@ -1401,6 +1401,7 @@ st_translate_program_common(struct st_context *st,
if (tgsi_processor == PIPE_SHADER_COMPUTE) {
   struct st_compute_program *stcp = (struct st_compute_program *) prog;
   out_state->tokens = ureg_get_tokens(ureg, >num_tgsi_tokens);
+  stcp->tgsi.prog = out_state->tokens;
} else {
   struct st_common_program *stcp = (struct st_common_program *) prog;
   out_state->tokens = ureg_get_tokens(ureg, >num_tgsi_tokens);
@@ -1411,7 +1412,7 @@ st_translate_program_common(struct st_context *st,
outputMapping,
_state->stream_output);
 
-   st_store_tgsi_in_disk_cache(st, prog, out_state);
+   st_store_tgsi_in_disk_cache(st, prog);
 
if ((ST_DEBUG & DEBUG_TGSI) && (ST_DEBUG & DEBUG_MESA)) {
   _mesa_print_program(prog);
@@ -1624,7 +1625,6 @@ st_translate_compute_program(struct st_context *st,
PIPE_SHADER_COMPUTE, );
 
stcp->tgsi.ir_type = PIPE_SHADER_IR_TGSI;
-   stcp->tgsi.prog = prog.tokens;
stcp->tgsi.req_local_mem = stcp->Base.info.cs.shared_size;
stcp->tgsi.req_private_mem = 0;
stcp->tgsi.req_input_mem = 0;
diff --git a/src/mesa/state_tracker/st_shader_cache.c 
b/src/mesa/state_tracker/st_shader_cache.c
index a9413fb053..1d9b172755 100644
--- a/src/mesa/state_tracker/st_shader_cache.c
+++ b/src/mesa/state_tracker/st_shader_cache.c
@@ -39,12 +39,11 @@ write_stream_out_to_cache(struct blob *blob,
 }
 
 static void
-write_tgsi_to_cache(struct blob *blob, struct pipe_shader_state *tgsi,
+write_tgsi_to_cache(struct blob *blob, const struct tgsi_token *tokens,
 struct gl_program *prog, unsigned num_tokens)
 {
blob_write_uint32(blob, num_tokens);
-   blob_write_bytes(blob, tgsi->tokens,
-num_tokens * sizeof(struct tgsi_token));
+   blob_write_bytes(blob, tokens, num_tokens * sizeof(struct tgsi_token));
 
prog->driver_cache_blob = ralloc_size(NULL, blob->size);
memcpy(prog->driver_cache_blob, blob->data, blob->size);
@@ -55,8 +54,7 @@ write_tgsi_to_cache(struct blob *blob, struct 
pipe_shader_state *tgsi,
  * Store tgsi and any other required state in on-disk shader cache.
  */
 void
-st_store_tgsi_in_disk_cache(struct st_context *st, struct gl_program *prog,
-struct pipe_shader_state *out_state)
+st_store_tgsi_in_disk_cache(struct st_context *st, struct gl_program *prog)
 {
if (!st->ctx->Cache)
   return;
@@ -82,7 +80,8 @@ st_store_tgsi_in_disk_cache(struct st_context *st, struct 
gl_program *prog,
sizeof(stvp->result_to_output));
 
   write_stream_out_to_cache(, >tgsi);
-  write_tgsi_to_cache(, >tgsi, prog, stvp->num_tgsi_tokens);
+  write_tgsi_to_cache(, stvp->tgsi.tokens, prog,
+  stvp->num_tgsi_tokens);
   break;
}
case MESA_SHADER_TESS_CTRL:
@@ -90,20 +89,23 @@ st_store_tgsi_in_disk_cache(struct st_context *st, struct 
gl_program *prog,
case MESA_SHADER_GEOMETRY: {
   struct st_common_program *stcp = (struct st_common_program *) prog;
 
-  write_stream_out_to_cache(, out_state);
-  write_tgsi_to_cache(, out_state, prog, stcp->num_tgsi_tokens

Mesa (master): st/glsl_to_tgsi: add ARB_get_program_binary support using TGSI

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: a20016d8277f9cd68620784417a57ae227783a04
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a20016d8277f9cd68620784417a57ae227783a04

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Mon Nov 27 17:01:01 2017 +1100

st/glsl_to_tgsi: add ARB_get_program_binary support using TGSI

This resolves a game bug in Dead Island. The game doesn't properly
handle ARB_get_program_binary with 0 supported formats, and ends up
crashing.

This will enable ARB_get_program_binary binary support for any
driver that currently enables the on-disk shader cache.

Tested-by: Dieter Nützel <die...@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85564

---

 src/mesa/state_tracker/st_context.c| 6 ++
 src/mesa/state_tracker/st_extensions.c | 4 
 2 files changed, 10 insertions(+)

diff --git a/src/mesa/state_tracker/st_context.c 
b/src/mesa/state_tracker/st_context.c
index 7564a53035..a7b2cfc12b 100644
--- a/src/mesa/state_tracker/st_context.c
+++ b/src/mesa/state_tracker/st_context.c
@@ -74,6 +74,7 @@
 #include "st_pbo.h"
 #include "st_program.h"
 #include "st_sampler_view.h"
+#include "st_shader_cache.h"
 #include "st_vdpau.h"
 #include "st_texture.h"
 #include "pipe/p_context.h"
@@ -760,4 +761,9 @@ st_init_driver_functions(struct pipe_screen *screen,
functions->SetBackgroundContext = st_set_background_context;
functions->GetDriverUuid = st_get_device_uuid;
functions->GetDeviceUuid = st_get_driver_uuid;
+
+   /* GL_ARB_get_program_binary */
+   functions->GetProgramBinaryDriverSHA1 = st_get_program_binary_driver_sha1;
+   functions->ProgramBinarySerializeDriverBlob = st_serialise_tgsi_program;
+   functions->ProgramBinaryDeserializeDriverBlob = st_deserialise_tgsi_program;
 }
diff --git a/src/mesa/state_tracker/st_extensions.c 
b/src/mesa/state_tracker/st_extensions.c
index c8411a6995..370d1a7e06 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -417,6 +417,10 @@ void st_init_limits(struct pipe_screen *screen,
c->GLSLFrontFacingIsSysVal =
   screen->get_param(screen, PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL);
 
+   /* GL_ARB_get_program_binary */
+   if (screen->get_disk_shader_cache && screen->get_disk_shader_cache(screen))
+  c->NumProgramBinaryFormats = 1;
+
c->MaxAtomicBufferBindings =
   c->Program[MESA_SHADER_FRAGMENT].MaxAtomicBuffers;
 

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Mesa (master): st/glsl_to_nir: disable io lowering to temps for tess

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: f69cbb2b53ac3edf7b201ba77430a61471edfa6e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f69cbb2b53ac3edf7b201ba77430a61471edfa6e

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Thu Jan 11 12:47:31 2018 +1100

st/glsl_to_nir: disable io lowering to temps for tess

Lowering these to temps makes a big mess, and results in some
piglit test failures. Also the radeonsi backend (the only backend
to support tess) has support for indirects so there is no need to
lower them anyway.

Fixes the following piglit tests on radeonsi:

tests/spec/arb_tessellation_shader/execution/variable-indexing/tes-input-array-vec3-index-rd.shader_test
tests/spec/arb_tessellation_shader/execution/variable-indexing/tes-input-array-vec4-index-rd.shader_test

Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/mesa/state_tracker/st_glsl_to_nir.cpp | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 1c5de3d5de..bd6d588a98 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -490,9 +490,12 @@ st_nir_get_mesa_program(struct gl_context *ctx,
set_st_program(prog, shader_program, nir);
prog->nir = nir;
 
-   NIR_PASS_V(nir, nir_lower_io_to_temporaries,
-  nir_shader_get_entrypoint(nir),
-  true, true);
+   if (nir->info.stage != MESA_SHADER_TESS_CTRL &&
+   nir->info.stage != MESA_SHADER_TESS_EVAL) {
+  NIR_PASS_V(nir, nir_lower_io_to_temporaries,
+ nir_shader_get_entrypoint(nir),
+ true, true);
+   }
NIR_PASS_V(nir, nir_lower_global_vars_to_local);
NIR_PASS_V(nir, nir_split_var_copies);
NIR_PASS_V(nir, nir_lower_var_copies);
@@ -665,7 +668,8 @@ st_finalize_nir(struct st_context *st, struct gl_program 
*prog,
 
NIR_PASS_V(nir, nir_split_var_copies);
NIR_PASS_V(nir, nir_lower_var_copies);
-   if (nir->info.stage != MESA_SHADER_TESS_CTRL)
+   if (nir->info.stage != MESA_SHADER_TESS_CTRL &&
+   nir->info.stage != MESA_SHADER_TESS_EVAL)
   NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects);
 
if (nir->info.stage == MESA_SHADER_VERTEX) {

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Mesa (master): st/mesa: enable ARB_enhanced_layouts on nir drivers

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: dc520dafdcfccd20071dc560b39e3d93ffdbafe4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=dc520dafdcfccd20071dc560b39e3d93ffdbafe4

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Fri Jan 12 16:42:47 2018 +1100

st/mesa: enable ARB_enhanced_layouts on nir drivers

I'm guessing this may have been disable because of missing
component packing support. However recent nir linking changes
required nir based gallium drivers to support component packing
so this should now be ok to enable.

Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/mesa/state_tracker/st_extensions.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/src/mesa/state_tracker/st_extensions.c 
b/src/mesa/state_tracker/st_extensions.c
index 9ef0df1e92..c8411a6995 100644
--- a/src/mesa/state_tracker/st_extensions.c
+++ b/src/mesa/state_tracker/st_extensions.c
@@ -956,9 +956,7 @@ void st_init_extensions(struct pipe_screen *screen,
}
 
if (consts->GLSLVersion >= 140) {
-  if (screen->get_param(screen, PIPE_CAP_TGSI_ARRAY_COMPONENTS) &&
- screen->get_shader_param(screen, PIPE_SHADER_FRAGMENT,
-   PIPE_SHADER_CAP_PREFERRED_IR) == 
PIPE_SHADER_IR_TGSI)
+  if (screen->get_param(screen, PIPE_CAP_TGSI_ARRAY_COMPONENTS))
  extensions->ARB_enhanced_layouts = GL_TRUE;
}
 

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Mesa (master): ac: add doubles support to isign

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: e6378962ce43727056756a373f5001da041b160e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6378962ce43727056756a373f5001da041b160e

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Sun Jan 14 10:07:58 2018 +1100

ac: add doubles support to isign

Fixes a number of int64 piglit tests, for example:

generated_tests/spec/arb_gpu_shader_int64/execution/built-in-functions/fs-sign-i64vec2.shader_test

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>

---

 src/amd/common/ac_nir_to_llvm.c | 25 ++---
 1 file changed, 18 insertions(+), 7 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 0a0b577735..6467ed66ae 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1362,14 +1362,25 @@ static LLVMValueRef emit_fsign(struct ac_llvm_context 
*ctx,
 }
 
 static LLVMValueRef emit_isign(struct ac_llvm_context *ctx,
-  LLVMValueRef src0)
+  LLVMValueRef src0, unsigned bitsize)
 {
-   LLVMValueRef cmp, val;
+   LLVMValueRef cmp, val, zero, one;
+   LLVMTypeRef type;
+
+   if (bitsize == 32) {
+   type = ctx->i32;
+   zero = ctx->i32_0;
+   one = ctx->i32_1;
+   } else {
+   type = ctx->i64;
+   zero = ctx->i64_0;
+   one = ctx->i64_1;
+   }
 
-   cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, ctx->i32_0, "");
-   val = LLVMBuildSelect(ctx->builder, cmp, ctx->i32_1, src0, "");
-   cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, ctx->i32_0, "");
-   val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(ctx->i32, 
-1, true), "");
+   cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGT, src0, zero, "");
+   val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
+   cmp = LLVMBuildICmp(ctx->builder, LLVMIntSGE, val, zero, "");
+   val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstInt(type, -1, 
true), "");
return val;
 }
 
@@ -1813,7 +1824,7 @@ static void visit_alu(struct ac_nir_context *ctx, const 
nir_alu_instr *instr)
result = emit_minmax_int(>ac, LLVMIntULT, src[0], src[1]);
break;
case nir_op_isign:
-   result = emit_isign(>ac, src[0]);
+   result = emit_isign(>ac, src[0], 
instr->dest.dest.ssa.bit_size);
break;
case nir_op_fsign:
src[0] = ac_to_float(>ac, src[0]);

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Mesa (master): ac/nir: fix translation of nir_op_b2i for doubles

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 741b21b713f0e9fd7f8df802164120e0d8486d7b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=741b21b713f0e9fd7f8df802164120e0d8486d7b

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Fri Jan 12 12:31:00 2018 +1100

ac/nir: fix translation of nir_op_b2i for doubles

V2: just zero-extend the 32-bit value.

Fixes a number of int64 piglet tests, for example:

generated_tests/spec/arb_gpu_shader_int64/execution/conversion/frag-conversion-explicit-bool-int64_t.shader_test

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>

---

 src/amd/common/ac_nir_to_llvm.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 0e1fefede5..0a0b577735 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1422,9 +1422,15 @@ static LLVMValueRef emit_f2b(struct ac_llvm_context *ctx,
 }
 
 static LLVMValueRef emit_b2i(struct ac_llvm_context *ctx,
-LLVMValueRef src0)
+LLVMValueRef src0,
+unsigned bitsize)
 {
-   return LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
+   LLVMValueRef result = LLVMBuildAnd(ctx->builder, src0, ctx->i32_1, "");
+
+   if (bitsize == 32)
+   return result;
+
+   return LLVMBuildZExt(ctx->builder, result, ctx->i64, "");
 }
 
 static LLVMValueRef emit_i2b(struct ac_llvm_context *ctx,
@@ -1979,7 +1985,7 @@ static void visit_alu(struct ac_nir_context *ctx, const 
nir_alu_instr *instr)
result = emit_f2b(>ac, src[0]);
break;
case nir_op_b2i:
-   result = emit_b2i(>ac, src[0]);
+   result = emit_b2i(>ac, src[0], 
instr->dest.dest.ssa.bit_size);
break;
case nir_op_i2b:
src[0] = ac_to_integer(>ac, src[0]);

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Mesa (master): ac: add i64_0 and i64_1 to llvm build context

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 38876c88d1e61d9ec489547dc51ac2026aabddc1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=38876c88d1e61d9ec489547dc51ac2026aabddc1

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Sun Jan 14 10:06:36 2018 +1100

ac: add i64_0 and i64_1 to llvm build context

These will be used in the following patch.

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>

---

 src/amd/common/ac_llvm_build.c | 2 ++
 src/amd/common/ac_llvm_build.h | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index f0a1788eaf..3467bba693 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -76,6 +76,8 @@ ac_llvm_context_init(struct ac_llvm_context *ctx, 
LLVMContextRef context,
 
ctx->i32_0 = LLVMConstInt(ctx->i32, 0, false);
ctx->i32_1 = LLVMConstInt(ctx->i32, 1, false);
+   ctx->i64_0 = LLVMConstInt(ctx->i64, 0, false);
+   ctx->i64_1 = LLVMConstInt(ctx->i64, 1, false);
ctx->f32_0 = LLVMConstReal(ctx->f32, 0.0);
ctx->f32_1 = LLVMConstReal(ctx->f32, 1.0);
ctx->f64_0 = LLVMConstReal(ctx->f64, 0.0);
diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index 78322bbf01..f87889daf6 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -61,6 +61,8 @@ struct ac_llvm_context {
 
LLVMValueRef i32_0;
LLVMValueRef i32_1;
+   LLVMValueRef i64_0;
+   LLVMValueRef i64_1;
LLVMValueRef f32_0;
LLVMValueRef f32_1;
LLVMValueRef f64_0;

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Mesa (master): ac: fix build error in si_shader

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 4d61eb80187cd8e5984eed94f2ae3c7d6c3b3aa0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4d61eb80187cd8e5984eed94f2ae3c7d6c3b3aa0

Author: Mauro Rossi <issor.or...@gmail.com>
Date:   Fri Jan 12 15:47:34 2018 +0100

ac: fix build error in si_shader

assert() is replaced by unreachable(), to avoid following building error:

external/mesa/src/gallium/drivers/radeonsi/si_shader.c:1967:1:
error: control may reach end of non-void function [-Werror,-Wreturn-type]
}
^
1 error generated.

Fixes: c797cd6 ("ac: add load_patch_vertices_in() to the abi")

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>

---

 src/gallium/drivers/radeonsi/si_shader.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index dd635ae203..35f82d8d63 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1963,7 +1963,7 @@ static LLVMValueRef si_load_patch_vertices_in(struct 
ac_shader_abi *abi)
else if (ctx->type == PIPE_SHADER_TESS_EVAL)
return get_num_tcs_out_vertices(ctx);
else
-   assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
+   unreachable("invalid shader stage for 
TGSI_SEMANTIC_VERTICESIN");
 }
 
 void si_load_system_value(struct si_shader_context *ctx,

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Mesa (master): radv/radeonsi/nir: lower 64bit flrp

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: f0d74ecce8d3353ed2696cb4b1e707fd6ddf0a40
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0d74ecce8d3353ed2696cb4b1e707fd6ddf0a40

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Fri Jan 12 11:12:09 2018 +1100

radv/radeonsi/nir: lower 64bit flrp

Fixes a bunch of arb_gpu_shader_fp64 piglit tests for example:

generated_tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-mix-double-double-double.shader_test

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>

---

 src/amd/vulkan/radv_shader.c  | 1 +
 src/gallium/drivers/radeonsi/si_get.c | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 6f622dd996..9819a522d7 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -52,6 +52,7 @@ static const struct nir_shader_compiler_options nir_options = 
{
.vertex_id_zero_based = true,
.lower_scmp = true,
.lower_flrp32 = true,
+   .lower_flrp64 = true,
.lower_fsat = true,
.lower_fdiv = true,
.lower_sub = true,
diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c
index 9b5a03edaf..caf6e9d19f 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -504,6 +504,7 @@ static const struct nir_shader_compiler_options nir_options 
= {
.vertex_id_zero_based = true,
.lower_scmp = true,
.lower_flrp32 = true,
+   .lower_flrp64 = true,
.lower_fsat = true,
.lower_fdiv = true,
.lower_sub = true,

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Mesa (master): ac: add f64_0 to the llvm build context

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: d7b6b8ba52894488b3234bc5fb09c0caebcc202b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d7b6b8ba52894488b3234bc5fb09c0caebcc202b

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Thu Jan 11 22:09:35 2018 +1100

ac: add f64_0 to the llvm build context

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

---

 src/amd/common/ac_llvm_build.c | 1 +
 src/amd/common/ac_llvm_build.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 75cc0dc63c..f0a1788eaf 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -78,6 +78,7 @@ ac_llvm_context_init(struct ac_llvm_context *ctx, 
LLVMContextRef context,
ctx->i32_1 = LLVMConstInt(ctx->i32, 1, false);
ctx->f32_0 = LLVMConstReal(ctx->f32, 0.0);
ctx->f32_1 = LLVMConstReal(ctx->f32, 1.0);
+   ctx->f64_0 = LLVMConstReal(ctx->f64, 0.0);
ctx->f64_1 = LLVMConstReal(ctx->f64, 1.0);
 
ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index a5279294bc..78322bbf01 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -63,6 +63,7 @@ struct ac_llvm_context {
LLVMValueRef i32_1;
LLVMValueRef f32_0;
LLVMValueRef f32_1;
+   LLVMValueRef f64_0;
LLVMValueRef f64_1;
LLVMValueRef i1true;
LLVMValueRef i1false;

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Mesa (master): ac/nir: fix translation of nir_op_fsign for doubles

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 30c1a93f6de66f0b9f86e11b517b62f57f330d95
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=30c1a93f6de66f0b9f86e11b517b62f57f330d95

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Thu Jan 11 22:10:47 2018 +1100

ac/nir: fix translation of nir_op_fsign for doubles

Without this we end up with the llvm error message:

"Both operands to a binary operator are not of the same type!"

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

---

 src/amd/common/ac_nir_to_llvm.c | 26 +++---
 1 file changed, 19 insertions(+), 7 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 7b348d97f0..6ab93b3678 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1338,14 +1338,26 @@ static LLVMValueRef emit_iabs(struct ac_llvm_context 
*ctx,
 }
 
 static LLVMValueRef emit_fsign(struct ac_llvm_context *ctx,
-  LLVMValueRef src0)
+  LLVMValueRef src0,
+  unsigned bitsize)
 {
-   LLVMValueRef cmp, val;
+   LLVMValueRef cmp, val, zero, one;
+   LLVMTypeRef type;
+
+   if (bitsize == 32) {
+   type = ctx->f32;
+   zero = ctx->f32_0;
+   one = ctx->f32_1;
+   } else {
+   type = ctx->f64;
+   zero = ctx->f64_0;
+   one = ctx->f64_1;
+   }
 
-   cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, ctx->f32_0, "");
-   val = LLVMBuildSelect(ctx->builder, cmp, ctx->f32_1, src0, "");
-   cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, ctx->f32_0, "");
-   val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(ctx->f32, 
-1.0), "");
+   cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGT, src0, zero, "");
+   val = LLVMBuildSelect(ctx->builder, cmp, one, src0, "");
+   cmp = LLVMBuildFCmp(ctx->builder, LLVMRealOGE, val, zero, "");
+   val = LLVMBuildSelect(ctx->builder, cmp, val, LLVMConstReal(type, 
-1.0), "");
return val;
 }
 
@@ -1799,7 +1811,7 @@ static void visit_alu(struct ac_nir_context *ctx, const 
nir_alu_instr *instr)
break;
case nir_op_fsign:
src[0] = ac_to_float(>ac, src[0]);
-   result = emit_fsign(>ac, src[0]);
+   result = emit_fsign(>ac, src[0], 
instr->dest.dest.ssa.bit_size);
break;
case nir_op_ffloor:
result = emit_intrin_1f_param(>ac, "llvm.floor",

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Mesa (master): ac/nir: fix translation of nir_op_frcp for doubles

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 7b971c828a7aaa507e9cea139f3ed932bbfc890a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b971c828a7aaa507e9cea139f3ed932bbfc890a

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Thu Jan 11 21:11:00 2018 +1100

ac/nir: fix translation of nir_op_frcp for doubles

Without this we end up with the llvm error message:

"Both operands to a binary operator are not of the same type!"

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

---

 src/amd/common/ac_nir_to_llvm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 372a424ce5..7b348d97f0 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1715,7 +1715,8 @@ static void visit_alu(struct ac_nir_context *ctx, const 
nir_alu_instr *instr)
break;
case nir_op_frcp:
src[0] = ac_to_float(>ac, src[0]);
-   result = ac_build_fdiv(>ac, ctx->ac.f32_1, src[0]);
+   result = ac_build_fdiv(>ac, instr->dest.dest.ssa.bit_size 
== 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
+  src[0]);
break;
case nir_op_iand:
result = LLVMBuildAnd(ctx->ac.builder, src[0], src[1], "");

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Mesa (master): ac/nir: fix translation of nir_op_frsq for doubles

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 24575c815c3a8bf3457b54077b93baa5fd73c7f2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=24575c815c3a8bf3457b54077b93baa5fd73c7f2

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Thu Jan 11 17:04:22 2018 +1100

ac/nir: fix translation of nir_op_frsq for doubles

Without this we end up with the llvm error message:

"Both operands to a binary operator are not of the same type!"

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

---

 src/amd/common/ac_nir_to_llvm.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 7153c9708d..372a424ce5 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1842,7 +1842,8 @@ static void visit_alu(struct ac_nir_context *ctx, const 
nir_alu_instr *instr)
case nir_op_frsq:
result = emit_intrin_1f_param(>ac, "llvm.sqrt",
  ac_to_float_type(>ac, 
def_type), src[0]);
-   result = ac_build_fdiv(>ac, ctx->ac.f32_1, result);
+   result = ac_build_fdiv(>ac, instr->dest.dest.ssa.bit_size 
== 32 ? ctx->ac.f32_1 : ctx->ac.f64_1,
+  result);
break;
case nir_op_fpow:
result = emit_intrin_2f_param(>ac, "llvm.pow",

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Mesa (master): ac: add f64_1 to the llvm build context

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: c0eb304acd7a803e3161bb9cf76cfa03bfc29050
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c0eb304acd7a803e3161bb9cf76cfa03bfc29050

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Thu Jan 11 17:03:36 2018 +1100

ac: add f64_1 to the llvm build context

Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

---

 src/amd/common/ac_llvm_build.c | 1 +
 src/amd/common/ac_llvm_build.h | 1 +
 2 files changed, 2 insertions(+)

diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 07044142b0..75cc0dc63c 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -78,6 +78,7 @@ ac_llvm_context_init(struct ac_llvm_context *ctx, 
LLVMContextRef context,
ctx->i32_1 = LLVMConstInt(ctx->i32, 1, false);
ctx->f32_0 = LLVMConstReal(ctx->f32, 0.0);
ctx->f32_1 = LLVMConstReal(ctx->f32, 1.0);
+   ctx->f64_1 = LLVMConstReal(ctx->f64, 1.0);
 
ctx->i1false = LLVMConstInt(ctx->i1, 0, false);
ctx->i1true = LLVMConstInt(ctx->i1, 1, false);
diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index e0fe0a58a4..a5279294bc 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -63,6 +63,7 @@ struct ac_llvm_context {
LLVMValueRef i32_1;
LLVMValueRef f32_0;
LLVMValueRef f32_1;
+   LLVMValueRef f64_1;
LLVMValueRef i1true;
LLVMValueRef i1false;
 

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Mesa (master): ac: add load_patch_vertices_in() to the abi

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: c797cd605ac9cb42795a40b1967b6dd10184b763
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c797cd605ac9cb42795a40b1967b6dd10184b763

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Jan 10 17:01:10 2018 +1100

ac: add load_patch_vertices_in() to the abi

Fixes the follow test for radeonsi nir:

tests/spec/arb_tessellation_shader/execution/quads.shader_test

Also stops 8 other tests from crashing, they now just fail e.g.

tcs-output-array-float-index-rd-after-barrier.shader_test

Reviewed-by: Marek Olšák <marek.ol...@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

---

 src/amd/common/ac_nir_to_llvm.c  | 11 ++-
 src/amd/common/ac_shader_abi.h   |  2 ++
 src/gallium/drivers/radeonsi/si_shader.c | 20 ++--
 3 files changed, 26 insertions(+), 7 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 8301b16057..7153c9708d 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4166,6 +4166,13 @@ load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef 
type,
return LLVMBuildBitCast(ctx->builder, result, type, "");
 }
 
+static LLVMValueRef
+load_patch_vertices_in(struct ac_shader_abi *abi)
+{
+   struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+   return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, 
false);
+}
+
 static void visit_intrinsic(struct ac_nir_context *ctx,
 nir_intrinsic_instr *instr)
 {
@@ -4366,7 +4373,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
result = ctx->abi->load_tess_level(ctx->abi, 
VARYING_SLOT_TESS_LEVEL_INNER);
break;
case nir_intrinsic_load_patch_vertices_in:
-   result = LLVMConstInt(ctx->ac.i32, 
ctx->nctx->options->key.tcs.input_vertices, false);
+   result = ctx->abi->load_patch_vertices_in(ctx->abi);
break;
default:
fprintf(stderr, "Unknown intrinsic: ");
@@ -6698,11 +6705,13 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
ctx.tcs_patch_outputs_read = 
shaders[i]->info.patch_outputs_read;
ctx.abi.load_tess_inputs = load_tcs_input;
+   ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
ctx.abi.store_tcs_outputs = store_tcs_output;
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
ctx.tes_primitive_mode = 
shaders[i]->info.tess.primitive_mode;
ctx.abi.load_tess_inputs = load_tes_input;
ctx.abi.load_tess_coord = load_tess_coord;
+   ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
if (shader_info->info.vs.needs_instance_id) {
if (ctx.ac.chip_class == GFX9 &&
diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index e3a47089a5..06e61207ec 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -103,6 +103,8 @@ struct ac_shader_abi {
LLVMTypeRef type,
unsigned num_components);
 
+   LLVMValueRef (*load_patch_vertices_in)(struct ac_shader_abi *abi);
+
LLVMValueRef (*load_tess_level)(struct ac_shader_abi *abi,
unsigned varying_id);
 
diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 86f3f7a8ba..dd635ae203 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1955,6 +1955,17 @@ static LLVMValueRef si_load_tess_level(struct 
ac_shader_abi *abi,
 
 }
 
+static LLVMValueRef si_load_patch_vertices_in(struct ac_shader_abi *abi)
+{
+   struct si_shader_context *ctx = si_shader_context_from_abi(abi);
+   if (ctx->type == PIPE_SHADER_TESS_CTRL)
+   return unpack_param(ctx, ctx->param_tcs_out_lds_layout, 26, 6);
+   else if (ctx->type == PIPE_SHADER_TESS_EVAL)
+   return get_num_tcs_out_vertices(ctx);
+   else
+   assert(!"invalid shader stage for TGSI_SEMANTIC_VERTICESIN");
+}
+
 void si_load_system_value(struct si_shader_context *ctx,
  unsigned index,
  const struct tgsi_full_declaration *decl)
@@ -2063,12 +2074,7 @@ void si_load_system_value(struct si_shader_context *ctx,
break;
 
case TGSI_SEMANTIC_VERTICESIN:
-   if

Mesa (master): ac: rework emit_barrier() to not segfault on radeonsi

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: f04d2ca0d979101dd8bfcdc6cad30461ff73a7cc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f04d2ca0d979101dd8bfcdc6cad30461ff73a7cc

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Mon Jan  8 17:41:24 2018 +1100

ac: rework emit_barrier() to not segfault on radeonsi

nir_to_llvm_context will always be NULL for radeonsi so we need
work around this.

Reviewed-by: Dave Airlie <airl...@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>

---

 src/amd/common/ac_nir_to_llvm.c | 17 -
 1 file changed, 8 insertions(+), 9 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index cad4adfa03..70876cfc69 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3831,19 +3831,18 @@ static void emit_membar(struct nir_to_llvm_context *ctx,
ac_build_waitcnt(>ac, waitcnt);
 }
 
-static void emit_barrier(struct nir_to_llvm_context *ctx)
+static void emit_barrier(struct ac_llvm_context *ac, gl_shader_stage stage)
 {
/* SI only (thanks to a hw bug workaround):
 * The real barrier instruction isn’t needed, because an entire patch
 * always fits into a single wave.
 */
-   if (ctx->options->chip_class == SI &&
-   ctx->stage == MESA_SHADER_TESS_CTRL) {
-   ac_build_waitcnt(>ac, LGKM_CNT & VM_CNT);
+   if (ac->chip_class == SI && stage == MESA_SHADER_TESS_CTRL) {
+   ac_build_waitcnt(ac, LGKM_CNT & VM_CNT);
return;
}
-   ac_build_intrinsic(>ac, "llvm.amdgcn.s.barrier",
-  ctx->ac.voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
+   ac_build_intrinsic(ac, "llvm.amdgcn.s.barrier",
+  ac->voidt, NULL, 0, AC_FUNC_ATTR_CONVERGENT);
 }
 
 static void emit_discard_if(struct ac_nir_context *ctx,
@@ -4336,7 +4335,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
emit_membar(ctx->nctx, instr);
break;
case nir_intrinsic_barrier:
-   emit_barrier(ctx->nctx);
+   emit_barrier(>ac, ctx->stage);
break;
case nir_intrinsic_var_atomic_add:
case nir_intrinsic_var_atomic_imin:
@@ -6179,7 +6178,7 @@ write_tess_factors(struct nir_to_llvm_context *ctx)
LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
int i;
-   emit_barrier(ctx);
+   emit_barrier(>ac, ctx->stage);
 
switch (ctx->options->key.tcs.primitive_mode) {
case GL_ISOLINES:
@@ -6728,7 +6727,7 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
}
 
if (i)
-   emit_barrier();
+   emit_barrier(, ctx.stage);
 
ac_setup_rings();
 

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Mesa (master): ac: add load_tess_level() to the abi

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 19f3141e6ab34dc7389b5e1fa9f3dca5e23b2191
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=19f3141e6ab34dc7389b5e1fa9f3dca5e23b2191

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Mon Dec 11 16:16:30 2017 +1100

ac: add load_tess_level() to the abi

Fixes the following piglit tests in radeonsi:

vs-tcs-tes-tessinner-tessouter-inputs-quads.shader_test
vs-tcs-tes-tessinner-tessouter-inputs-tris.shader_test
vs-tes-tessinner-tessouter-inputs-quads.shader_test
vs-tes-tessinner-tessouter-inputs-tris.shader_test

v2: make use of si_shader_io_get_unique_index_patch()
via the helper in the previous patch rather than
shader_io_get_unique_index()

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> (v1)
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/amd/common/ac_nir_to_llvm.c  |  6 ++
 src/amd/common/ac_shader_abi.h   |  4 
 src/gallium/drivers/radeonsi/si_shader.c | 22 ++
 3 files changed, 32 insertions(+)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 42ddebbeef..cad4adfa03 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4369,6 +4369,12 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
result = ctx->abi->load_tess_coord(ctx->abi, type, 
instr->num_components);
break;
}
+   case nir_intrinsic_load_tess_level_outer:
+   result = ctx->abi->load_tess_level(ctx->abi, 
VARYING_SLOT_TESS_LEVEL_OUTER);
+   break;
+   case nir_intrinsic_load_tess_level_inner:
+   result = ctx->abi->load_tess_level(ctx->abi, 
VARYING_SLOT_TESS_LEVEL_INNER);
+   break;
case nir_intrinsic_load_patch_vertices_in:
result = LLVMConstInt(ctx->ac.i32, 
ctx->nctx->options->key.tcs.input_vertices, false);
break;
diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index 277e4efe47..e3a47089a5 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -103,6 +103,10 @@ struct ac_shader_abi {
LLVMTypeRef type,
unsigned num_components);
 
+   LLVMValueRef (*load_tess_level)(struct ac_shader_abi *abi,
+   unsigned varying_id);
+
+
LLVMValueRef (*load_ubo)(struct ac_shader_abi *abi, LLVMValueRef index);
 
/**
diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index e579916359..86f3f7a8ba 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1934,6 +1934,27 @@ static LLVMValueRef load_tess_level(struct 
si_shader_context *ctx,
 
 }
 
+static LLVMValueRef si_load_tess_level(struct ac_shader_abi *abi,
+  unsigned varying_id)
+{
+   struct si_shader_context *ctx = si_shader_context_from_abi(abi);
+   unsigned semantic_name;
+
+   switch (varying_id) {
+   case VARYING_SLOT_TESS_LEVEL_INNER:
+   semantic_name = TGSI_SEMANTIC_TESSINNER;
+   break;
+   case VARYING_SLOT_TESS_LEVEL_OUTER:
+   semantic_name = TGSI_SEMANTIC_TESSOUTER;
+   break;
+   default:
+   unreachable("unknown tess level");
+   }
+
+   return load_tess_level(ctx, semantic_name);
+
+}
+
 void si_load_system_value(struct si_shader_context *ctx,
  unsigned index,
  const struct tgsi_full_declaration *decl)
@@ -5971,6 +5992,7 @@ static bool si_compile_tgsi_main(struct si_shader_context 
*ctx,
bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
ctx->abi.load_tess_inputs = si_nir_load_input_tes;
ctx->abi.load_tess_coord = si_load_tess_coord;
+   ctx->abi.load_tess_level = si_load_tess_level;
if (shader->key.as_es)
ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
else

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Mesa (master): radeonsi: add load_tess_level() helper

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 2bd7ab32cfe8ad2ee7469ecb83d9077cd520c537
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2bd7ab32cfe8ad2ee7469ecb83d9077cd520c537

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Mon Dec 11 14:48:41 2017 +1100

radeonsi: add load_tess_level() helper

This will be shared by the tgsi and nir backends.

v2: move si_shader_io_get_unique_index_patch() call inside
the helper.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> (v1)
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader.c | 33 ++--
 1 file changed, 19 insertions(+), 14 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index f6e3083e4c..e579916359 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1916,6 +1916,24 @@ static LLVMValueRef si_load_tess_coord(struct 
ac_shader_abi *abi,
return lp_build_gather_values(>gallivm, coord, 4);
 }
 
+static LLVMValueRef load_tess_level(struct si_shader_context *ctx,
+   unsigned semantic_name)
+{
+   LLVMValueRef buffer, base, addr;
+
+   int param = si_shader_io_get_unique_index_patch(semantic_name, 0);
+
+   buffer = desc_from_addr_base64k(ctx, 
ctx->param_tcs_offchip_addr_base64k);
+
+   base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
+   addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), NULL,
+ LLVMConstInt(ctx->i32, param, 0));
+
+   return buffer_load(>bld_base, ctx->f32,
+  ~0, buffer, base, addr, true);
+
+}
+
 void si_load_system_value(struct si_shader_context *ctx,
  unsigned index,
  const struct tgsi_full_declaration *decl)
@@ -2034,21 +2052,8 @@ void si_load_system_value(struct si_shader_context *ctx,
 
case TGSI_SEMANTIC_TESSINNER:
case TGSI_SEMANTIC_TESSOUTER:
-   {
-   LLVMValueRef buffer, base, addr;
-   int param = 
si_shader_io_get_unique_index_patch(decl->Semantic.Name, 0);
-
-   buffer = desc_from_addr_base64k(ctx, 
ctx->param_tcs_offchip_addr_base64k);
-
-   base = LLVMGetParam(ctx->main_fn, 
ctx->param_tcs_offchip_offset);
-   addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), 
NULL,
- LLVMConstInt(ctx->i32, param, 0));
-
-   value = buffer_load(>bld_base, ctx->f32,
-   ~0, buffer, base, addr, true);
-
+   value = load_tess_level(ctx, decl->Semantic.Name);
break;
-   }
 
case TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI:
case TGSI_SEMANTIC_DEFAULT_TESSINNER_SI:

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Mesa (master): glsl: Respect std430 layout in lower_buffer_access

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 7e025def6d7d3d6bf94facd6ec6d956f40cbb31e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e025def6d7d3d6bf94facd6ec6d956f40cbb31e

Author: Florian Will <florian.w...@gmail.com>
Date:   Fri Jan  5 15:33:31 2018 +0100

glsl: Respect std430 layout in lower_buffer_access

Respect the std430 rules for determining offset and size of struct
members when using a std430 buffer. std140 rules lead to wrong buffer
offsets in that case.

Fixes my test case attached in Bugzilla. No piglit changes.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104492
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>

---

 src/compiler/glsl/lower_buffer_access.cpp | 14 ++
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/src/compiler/glsl/lower_buffer_access.cpp 
b/src/compiler/glsl/lower_buffer_access.cpp
index db6e8e367b..ff6f9c1fcf 100644
--- a/src/compiler/glsl/lower_buffer_access.cpp
+++ b/src/compiler/glsl/lower_buffer_access.cpp
@@ -73,16 +73,22 @@ lower_buffer_access::emit_access(void *mem_ctx,
 new(mem_ctx) ir_dereference_record(deref->clone(mem_ctx, NULL),
field->name);
 
- field_offset =
-glsl_align(field_offset,
-   field->type->std140_base_alignment(row_major));
+ unsigned field_align;
+ if (packing == GLSL_INTERFACE_PACKING_STD430)
+field_align = field->type->std430_base_alignment(row_major);
+ else
+field_align = field->type->std140_base_alignment(row_major);
+ field_offset = glsl_align(field_offset, field_align);
 
  emit_access(mem_ctx, is_write, field_deref, base_offset,
  deref_offset + field_offset,
  row_major, NULL, packing,
  writemask_for_size(field_deref->type->vector_elements));
 
- field_offset += field->type->std140_size(row_major);
+ if (packing == GLSL_INTERFACE_PACKING_STD430)
+field_offset += field->type->std430_size(row_major);
+ else
+field_offset += field->type->std140_size(row_major);
   }
   return;
}

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Mesa (master): nir: fix st_nir_assign_var_locations for patch variables

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: efd2169c1a40f552b3a6a0b03bb787255b8febf6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=efd2169c1a40f552b3a6a0b03bb787255b8febf6

Author: Karol Herbst <kher...@redhat.com>
Date:   Sun Jan  7 21:42:19 2018 +0100

nir: fix st_nir_assign_var_locations for patch variables

Signed-off-by: Karol Herbst <kher...@redhat.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>

---

 src/mesa/state_tracker/st_glsl_to_nir.cpp | 8 ++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 5683df..1c5de3d5de 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -139,8 +139,12 @@ st_nir_assign_var_locations(struct exec_list *var_list, 
unsigned *size,
   }
 
   bool processed = false;
-  if (var->data.patch) {
- unsigned patch_loc = var->data.location - VARYING_SLOT_VAR0;
+  if (var->data.patch &&
+  var->data.location != VARYING_SLOT_TESS_LEVEL_INNER &&
+  var->data.location != VARYING_SLOT_TESS_LEVEL_OUTER &&
+  var->data.location != VARYING_SLOT_BOUNDING_BOX0 &&
+  var->data.location != VARYING_SLOT_BOUNDING_BOX1) {
+ unsigned patch_loc = var->data.location - VARYING_SLOT_PATCH0;
  if (processed_patch_locs & (1 << patch_loc))
 processed = true;
 

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Mesa (master): ac: rework ac_llvm_extract_elem()

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 4a0c24f2dd97c670259a7ab0ced701dbf9bb5dd7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a0c24f2dd97c670259a7ab0ced701dbf9bb5dd7

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Dec 13 18:46:56 2017 +1100

ac: rework ac_llvm_extract_elem()

Simplifies the logic a little and asserts index is 0.

Suggested-by: Nicolai Hähnle <nhaeh...@gmail.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/amd/common/ac_llvm_build.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 0ea5e7f4ca..8a3a2abf17 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -114,10 +114,10 @@ ac_llvm_extract_elem(struct ac_llvm_context *ac,
 LLVMValueRef value,
 int index)
 {
-   int count = ac_get_llvm_num_components(value);
-
-   if (count == 1)
+   if (LLVMGetTypeKind(LLVMTypeOf(value)) != LLVMVectorTypeKind) {
+   assert(index == 0);
return value;
+   }
 
return LLVMBuildExtractElement(ac->builder, value,
   LLVMConstInt(ac->i32, index, false), "");

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Mesa (master): ac/radeonsi: add load_tess_coord() to the abi

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 14adf7853a569b966bca80cd3429a9eb24ddebd4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=14adf7853a569b966bca80cd3429a9eb24ddebd4

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Dec  6 17:34:32 2017 +1100

ac/radeonsi: add load_tess_coord() to the abi

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/amd/common/ac_nir_to_llvm.c  | 20 +--
 src/amd/common/ac_shader_abi.h   |  4 +++
 src/gallium/drivers/radeonsi/si_shader.c | 42 +++-
 3 files changed, 42 insertions(+), 24 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index bdbe6f82e2..e9f997c7a4 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -4147,9 +4147,11 @@ visit_end_primitive(struct nir_to_llvm_context *ctx,
 }
 
 static LLVMValueRef
-visit_load_tess_coord(struct nir_to_llvm_context *ctx,
- const nir_intrinsic_instr *instr)
+load_tess_coord(struct ac_shader_abi *abi, LLVMTypeRef type,
+   unsigned num_components)
 {
+   struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+
LLVMValueRef coord[4] = {
ctx->tes_u,
ctx->tes_v,
@@ -4161,9 +4163,8 @@ visit_load_tess_coord(struct nir_to_llvm_context *ctx,
coord[2] = LLVMBuildFSub(ctx->builder, ctx->ac.f32_1,
LLVMBuildFAdd(ctx->builder, coord[0], 
coord[1], ""), "");
 
-   LLVMValueRef result = ac_build_gather_values(>ac, coord, 
instr->num_components);
-   return LLVMBuildBitCast(ctx->builder, result,
-   get_def_type(ctx->nir, >dest.ssa), "");
+   LLVMValueRef result = ac_build_gather_values(>ac, coord, 
num_components);
+   return LLVMBuildBitCast(ctx->builder, result, type, "");
 }
 
 static void visit_intrinsic(struct ac_nir_context *ctx,
@@ -4352,9 +4353,13 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
case nir_intrinsic_end_primitive:
visit_end_primitive(ctx->nctx, instr);
break;
-   case nir_intrinsic_load_tess_coord:
-   result = visit_load_tess_coord(ctx->nctx, instr);
+   case nir_intrinsic_load_tess_coord: {
+   LLVMTypeRef type = ctx->nctx ?
+   get_def_type(ctx->nctx->nir, >dest.ssa) :
+   NULL;
+   result = ctx->abi->load_tess_coord(ctx->abi, type, 
instr->num_components);
break;
+   }
case nir_intrinsic_load_patch_vertices_in:
result = LLVMConstInt(ctx->ac.i32, 
ctx->nctx->options->key.tcs.input_vertices, false);
break;
@@ -6686,6 +6691,7 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
ctx.tes_primitive_mode = 
shaders[i]->info.tess.primitive_mode;
ctx.abi.load_tess_inputs = load_tes_input;
+   ctx.abi.load_tess_coord = load_tess_coord;
} else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
if (shader_info->info.vs.needs_instance_id) {
ctx.shader_info->vs.vgpr_comp_cnt =
diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index d5d7c9c327..277e4efe47 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -99,6 +99,10 @@ struct ac_shader_abi {
  bool is_compact,
  unsigned writemask);
 
+   LLVMValueRef (*load_tess_coord)(struct ac_shader_abi *abi,
+   LLVMTypeRef type,
+   unsigned num_components);
+
LLVMValueRef (*load_ubo)(struct ac_shader_abi *abi, LLVMValueRef index);
 
/**
diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 45c4720d35..f6e3083e4c 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1893,11 +1893,33 @@ static LLVMValueRef load_sample_position(struct 
si_shader_context *ctx, LLVMValu
return lp_build_gather_values(>gallivm, pos, 4);
 }
 
+static LLVMValueRef si_load_tess_coord(struct ac_shader_abi *abi,
+  LLVMTypeRef type,
+  unsigned num_components)
+{
+   struct si_shader_context *ctx = si_shader_context_from_abi(abi);
+   struct lp_build_context *bld = >bld_base.base;
+
+   LLVMValueRef coord[4] = {
+   LLVMGetPara

Mesa (master): radeonsi: add get_dw_address_from_generic_indices() helper

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 234507b3cf2d3439289055c32038896724955e7b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=234507b3cf2d3439289055c32038896724955e7b

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Mon Dec 11 13:14:49 2017 +1100

radeonsi: add get_dw_address_from_generic_indices() helper

This will be used by both the tgsi and nir backends.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader.c | 76 +++-
 1 file changed, 46 insertions(+), 30 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 647a5a4d40..0696020c41 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -827,6 +827,38 @@ LLVMValueRef si_get_bounded_indirect_index(struct 
si_shader_context *ctx,
return si_llvm_bound_index(ctx, result, num);
 }
 
+static LLVMValueRef get_dw_address_from_generic_indices(struct 
si_shader_context *ctx,
+   LLVMValueRef 
vertex_dw_stride,
+   LLVMValueRef base_addr,
+   LLVMValueRef 
vertex_index,
+   LLVMValueRef 
param_index,
+   unsigned input_index,
+   ubyte *name,
+   ubyte *index,
+   bool is_patch)
+{
+   if (vertex_dw_stride) {
+   base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
+LLVMBuildMul(ctx->ac.builder, 
vertex_index,
+ vertex_dw_stride, ""), 
"");
+   }
+
+   if (param_index) {
+   base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
+LLVMBuildMul(ctx->ac.builder, 
param_index,
+ LLVMConstInt(ctx->i32, 4, 
0), ""), "");
+   }
+
+   int param = is_patch ?
+   si_shader_io_get_unique_index_patch(name[input_index],
+   index[input_index]) :
+   si_shader_io_get_unique_index(name[input_index],
+ index[input_index]);
+
+   /* Add the base address of the element. */
+   return LLVMBuildAdd(ctx->ac.builder, base_addr,
+   LLVMConstInt(ctx->i32, param * 4, 0), "");
+}
 
 /**
  * Calculate a dword address given an input or output register and a stride.
@@ -839,8 +871,10 @@ static LLVMValueRef get_dw_address(struct 
si_shader_context *ctx,
 {
struct tgsi_shader_info *info = >shader->selector->info;
ubyte *name, *index, *array_first;
-   int first, param;
+   int input_index;
struct tgsi_full_dst_register reg;
+   LLVMValueRef vertex_index = NULL;
+   LLVMValueRef ind_index = NULL;
 
/* Set the register description. The address computation is the same
 * for sources and destinations. */
@@ -858,17 +892,11 @@ static LLVMValueRef get_dw_address(struct 
si_shader_context *ctx,
/* If the register is 2-dimensional (e.g. an array of vertices
 * in a primitive), calculate the base address of the vertex. */
if (reg.Register.Dimension) {
-   LLVMValueRef index;
-
if (reg.Dimension.Indirect)
-   index = si_get_indirect_index(ctx, ,
+   vertex_index = si_get_indirect_index(ctx, 
,
  1, reg.Dimension.Index);
else
-   index = LLVMConstInt(ctx->i32, reg.Dimension.Index, 0);
-
-   base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
-LLVMBuildMul(ctx->ac.builder, index,
- vertex_dw_stride, ""), 
"");
+   vertex_index = LLVMConstInt(ctx->i32, 
reg.Dimension.Index, 0);
}
 
/* Get information about the register. */
@@ -887,34 +915,22 @@ static LLVMValueRef get_dw_address(struct 
si_shader_context *ctx,
 
if (reg.Register.Indirect) {
/* Add the relative address of the element. */
-   LLVMValueRef ind_index;
-
if (reg.Indirect.ArrayID)
-   first = array_first[reg.Indirect.ArrayID];
+   input_index = array_first[reg.Indirect.ArrayID];
else
-  

Mesa (master): radeonsi: add unpack_llvm_param() helper

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 9c2f877830b25744d2fdd930a12959723c6c42f3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9c2f877830b25744d2fdd930a12959723c6c42f3

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Dec  6 14:18:34 2017 +1100

radeonsi: add unpack_llvm_param() helper

This allows us to pass the llvm param directly rather than looking
it up.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader.c | 18 --
 1 file changed, 12 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 87719e0fdb..dc7f12ce6a 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -241,13 +241,10 @@ unsigned si_shader_io_get_unique_index(unsigned 
semantic_name, unsigned index)
 /**
  * Get the value of a shader input parameter and extract a bitfield.
  */
-static LLVMValueRef unpack_param(struct si_shader_context *ctx,
-unsigned param, unsigned rshift,
-unsigned bitwidth)
+static LLVMValueRef unpack_llvm_param(struct si_shader_context *ctx,
+ LLVMValueRef value, unsigned rshift,
+ unsigned bitwidth)
 {
-   LLVMValueRef value = LLVMGetParam(ctx->main_fn,
- param);
-
if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMFloatTypeKind)
value = ac_to_integer(>ac, value);
 
@@ -264,6 +261,15 @@ static LLVMValueRef unpack_param(struct si_shader_context 
*ctx,
return value;
 }
 
+static LLVMValueRef unpack_param(struct si_shader_context *ctx,
+unsigned param, unsigned rshift,
+unsigned bitwidth)
+{
+   LLVMValueRef value = LLVMGetParam(ctx->main_fn, param);
+
+   return unpack_llvm_param(ctx, value, rshift, bitwidth);
+}
+
 static LLVMValueRef get_rel_patch_id(struct si_shader_context *ctx)
 {
switch (ctx->type) {

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Mesa (master): ac: add {tcs,tes}_patch_id to the abi

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: f93740efc1c75e26a7cb4bb7b41a60fcfdd4fed3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f93740efc1c75e26a7cb4bb7b41a60fcfdd4fed3

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Dec  6 13:30:33 2017 +1100

ac: add {tcs,tes}_patch_id to the abi

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/amd/common/ac_nir_to_llvm.c   | 14 ++
 src/amd/common/ac_shader_abi.h|  2 ++
 src/gallium/drivers/radeonsi/si_shader.c  | 17 -
 src/gallium/drivers/radeonsi/si_shader_internal.h |  2 --
 4 files changed, 16 insertions(+), 19 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index f8a63eab82..8dc1d903e0 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -111,10 +111,8 @@ struct nir_to_llvm_context {
LLVMValueRef oc_lds;
LLVMValueRef merged_wave_info;
LLVMValueRef tess_factor_offset;
-   LLVMValueRef tcs_patch_id;
LLVMValueRef tcs_rel_ids;
LLVMValueRef tes_rel_patch_id;
-   LLVMValueRef tes_patch_id;
LLVMValueRef tes_u;
LLVMValueRef tes_v;
 
@@ -684,7 +682,7 @@ declare_tes_input_vgprs(struct nir_to_llvm_context *ctx, 
struct arg_info *args)
add_arg(args, ARG_VGPR, ctx->ac.f32, >tes_u);
add_arg(args, ARG_VGPR, ctx->ac.f32, >tes_v);
add_arg(args, ARG_VGPR, ctx->ac.i32, >tes_rel_patch_id);
-   add_arg(args, ARG_VGPR, ctx->ac.i32, >tes_patch_id);
+   add_arg(args, ARG_VGPR, ctx->ac.i32, >abi.tes_patch_id);
 }
 
 static void
@@ -850,7 +848,7 @@ static void create_function(struct nir_to_llvm_context *ctx,
>view_index);
 
add_arg(, ARG_VGPR, ctx->ac.i32,
-   >tcs_patch_id);
+   >abi.tcs_patch_id);
add_arg(, ARG_VGPR, ctx->ac.i32,
>tcs_rel_ids);
 
@@ -878,7 +876,7 @@ static void create_function(struct nir_to_llvm_context *ctx,
add_arg(, ARG_SGPR, ctx->ac.i32,
>tess_factor_offset);
add_arg(, ARG_VGPR, ctx->ac.i32,
-   >tcs_patch_id);
+   >abi.tcs_patch_id);
add_arg(, ARG_VGPR, ctx->ac.i32,
>tcs_rel_ids);
}
@@ -4217,9 +4215,9 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
if (ctx->stage == MESA_SHADER_GEOMETRY) {
result = ctx->abi->gs_prim_id;
} else if (ctx->stage == MESA_SHADER_TESS_CTRL) {
-   result = ctx->nctx->tcs_patch_id;
+   result = ctx->abi->tcs_patch_id;
} else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
-   result = ctx->nctx->tes_patch_id;
+   result = ctx->abi->tes_patch_id;
} else
fprintf(stderr, "Unknown primitive id intrinsic: %d", 
ctx->stage);
break;
@@ -6542,7 +6540,7 @@ static void ac_nir_fixup_ls_hs_input_vgprs(struct 
nir_to_llvm_context *ctx)
ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, 
ctx->rel_auto_id, ctx->abi.instance_id, "");
ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, 
ctx->abi.vertex_id, ctx->vs_prim_id, "");
ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, 
ctx->tcs_rel_ids, ctx->rel_auto_id, "");
-   ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, 
ctx->tcs_patch_id, ctx->abi.vertex_id, "");
+   ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, 
ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
 }
 
 static void prepare_gs_input_vgprs(struct nir_to_llvm_context *ctx)
diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index fd2ec06fb1..6f526d9f25 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -42,6 +42,8 @@ struct ac_shader_abi {
LLVMValueRef draw_id;
LLVMValueRef vertex_id;
LLVMValueRef instance_id;
+   LLVMValueRef tcs_patch_id;
+   LLVMValueRef tes_patch_id;
LLVMValueRef gs_prim_id;
LLVMValueRef gs_invocation_id;
LLVMValueRef frag_pos[4];
diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 39a8906312..87719e0fdb 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -763,1

Mesa (master): ac/radeonsi: add tcs_rel_ids to the abi

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 9e1a3caf323a383364e7d29e96d7fa2035bf914d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9e1a3caf323a383364e7d29e96d7fa2035bf914d

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Dec  6 14:36:11 2017 +1100

ac/radeonsi: add tcs_rel_ids to the abi

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/amd/common/ac_nir_to_llvm.c   | 15 +++
 src/amd/common/ac_shader_abi.h|  1 +
 src/gallium/drivers/radeonsi/si_shader.c  | 19 ++-
 src/gallium/drivers/radeonsi/si_shader_internal.h |  1 -
 4 files changed, 18 insertions(+), 18 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 8dc1d903e0..bdbe6f82e2 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -111,7 +111,6 @@ struct nir_to_llvm_context {
LLVMValueRef oc_lds;
LLVMValueRef merged_wave_info;
LLVMValueRef tess_factor_offset;
-   LLVMValueRef tcs_rel_ids;
LLVMValueRef tes_rel_patch_id;
LLVMValueRef tes_u;
LLVMValueRef tes_v;
@@ -402,7 +401,7 @@ static LLVMValueRef get_rel_patch_id(struct 
nir_to_llvm_context *ctx)
 {
switch (ctx->stage) {
case MESA_SHADER_TESS_CTRL:
-   return unpack_param(>ac, ctx->tcs_rel_ids, 0, 8);
+   return unpack_param(>ac, ctx->abi.tcs_rel_ids, 0, 8);
case MESA_SHADER_TESS_EVAL:
return ctx->tes_rel_patch_id;
break;
@@ -850,7 +849,7 @@ static void create_function(struct nir_to_llvm_context *ctx,
add_arg(, ARG_VGPR, ctx->ac.i32,
>abi.tcs_patch_id);
add_arg(, ARG_VGPR, ctx->ac.i32,
-   >tcs_rel_ids);
+   >abi.tcs_rel_ids);
 
declare_vs_input_vgprs(ctx, );
} else {
@@ -878,7 +877,7 @@ static void create_function(struct nir_to_llvm_context *ctx,
add_arg(, ARG_VGPR, ctx->ac.i32,
>abi.tcs_patch_id);
add_arg(, ARG_VGPR, ctx->ac.i32,
-   >tcs_rel_ids);
+   >abi.tcs_rel_ids);
}
break;
case MESA_SHADER_TESS_EVAL:
@@ -4207,7 +4206,7 @@ static void visit_intrinsic(struct ac_nir_context *ctx,
break;
case nir_intrinsic_load_invocation_id:
if (ctx->stage == MESA_SHADER_TESS_CTRL)
-   result = unpack_param(>ac, ctx->nctx->tcs_rel_ids, 
8, 5);
+   result = unpack_param(>ac, ctx->abi->tcs_rel_ids, 
8, 5);
else
result = ctx->abi->gs_invocation_id;
break;
@@ -6149,8 +6148,8 @@ write_tess_factors(struct nir_to_llvm_context *ctx)
 {
unsigned stride, outer_comps, inner_comps;
struct ac_build_if_state if_ctx, inner_if_ctx;
-   LLVMValueRef invocation_id = unpack_param(>ac, ctx->tcs_rel_ids, 
8, 5);
-   LLVMValueRef rel_patch_id = unpack_param(>ac, ctx->tcs_rel_ids, 0, 
8);
+   LLVMValueRef invocation_id = unpack_param(>ac, 
ctx->abi.tcs_rel_ids, 8, 5);
+   LLVMValueRef rel_patch_id = unpack_param(>ac, 
ctx->abi.tcs_rel_ids, 0, 8);
unsigned tess_inner_index, tess_outer_index;
LLVMValueRef lds_base, lds_inner, lds_outer, byteoffset, buffer;
LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
@@ -6539,7 +6538,7 @@ static void ac_nir_fixup_ls_hs_input_vgprs(struct 
nir_to_llvm_context *ctx)
  ctx->ac.i32_0, "");
ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, 
ctx->rel_auto_id, ctx->abi.instance_id, "");
ctx->vs_prim_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, 
ctx->abi.vertex_id, ctx->vs_prim_id, "");
-   ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, 
ctx->tcs_rel_ids, ctx->rel_auto_id, "");
+   ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, 
ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, 
ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
 }
 
diff --git a/src/amd/common/ac_shader_abi.h b/src/amd/common/ac_shader_abi.h
index 6f526d9f25..d5d7c9c327 100644
--- a/src/amd/common/ac_shader_abi.h
+++ b/src/amd/common/ac_shader_abi.h
@@ -43,6 +43,7 @@ struct ac_shader_abi {
LLVMValueRef vertex_id;
LLVMValueRef instance_id;
LLVMValueRef tcs_patch_id;
+   LLVMValueRef tcs_rel_ids;

Mesa (master): ac: call load_tcs_input() via the abi

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: b104e7e1727120a546fc022f3165ad6c3f9dd2fc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b104e7e1727120a546fc022f3165ad6c3f9dd2fc

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Dec  5 12:04:05 2017 +1100

ac: call load_tcs_input() via the abi

This also enables some code sharing with tes.

V2: drop type param and just use ctx->i32

Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/amd/common/ac_nir_to_llvm.c | 36 +---
 1 file changed, 17 insertions(+), 19 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 7a99461477..8c6a276da6 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2832,35 +2832,33 @@ get_dw_address(struct nir_to_llvm_context *ctx,
 }
 
 static LLVMValueRef
-load_tcs_input(struct nir_to_llvm_context *ctx,
-  nir_intrinsic_instr *instr)
+load_tcs_input(struct ac_shader_abi *abi,
+  LLVMValueRef vertex_index,
+  LLVMValueRef indir_index,
+  unsigned const_index,
+  unsigned location,
+  unsigned driver_location,
+  unsigned component,
+  unsigned num_components,
+  bool is_patch,
+  bool is_compact)
 {
+   struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
LLVMValueRef dw_addr, stride;
-   unsigned const_index;
-   LLVMValueRef vertex_index;
-   LLVMValueRef indir_index;
-   unsigned param;
LLVMValueRef value[4], result;
-   const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, 
ctx->stage);
-   const bool is_compact = instr->variables[0]->var->data.compact;
-   param = 
shader_io_get_unique_index(instr->variables[0]->var->data.location);
-   get_deref_offset(ctx->nir, instr->variables[0],
-false, NULL, per_vertex ? _index : NULL,
-_index, _index);
+   unsigned param = shader_io_get_unique_index(location);
 
stride = unpack_param(>ac, ctx->tcs_in_layout, 13, 8);
dw_addr = get_tcs_in_current_patch_offset(ctx);
dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, 
vertex_index, stride,
 indir_index);
 
-   unsigned comp = instr->variables[0]->var->data.location_frac;
-   for (unsigned i = 0; i < instr->num_components + comp; i++) {
+   for (unsigned i = 0; i < num_components + component; i++) {
value[i] = ac_lds_load(>ac, dw_addr);
dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
   ctx->ac.i32_1, "");
}
-   result = ac_build_varying_gather_values(>ac, value, 
instr->num_components, comp);
-   result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, 
>dest.ssa), "");
+   result = ac_build_varying_gather_values(>ac, value, 
num_components, component);
return result;
 }
 
@@ -3128,9 +3126,8 @@ static LLVMValueRef visit_load_var(struct ac_nir_context 
*ctx,
 
switch (instr->variables[0]->var->data.mode) {
case nir_var_shader_in:
-   if (ctx->stage == MESA_SHADER_TESS_CTRL)
-   return load_tcs_input(ctx->nctx, instr);
-   if (ctx->stage == MESA_SHADER_TESS_EVAL) {
+   if (ctx->stage == MESA_SHADER_TESS_CTRL ||
+   ctx->stage == MESA_SHADER_TESS_EVAL) {
LLVMValueRef result;
LLVMValueRef vertex_index = NULL;
LLVMValueRef indir_index = NULL;
@@ -6695,6 +6692,7 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
ctx.tcs_outputs_read = shaders[i]->info.outputs_read;
ctx.tcs_patch_outputs_read = 
shaders[i]->info.patch_outputs_read;
+   ctx.abi.load_tess_inputs = load_tcs_input;
} else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
ctx.tes_primitive_mode = 
shaders[i]->info.tess.primitive_mode;
ctx.abi.load_tess_inputs = load_tes_input;

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Mesa (master): ac: add store_tcs_outputs() to the abi

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 2deb82207572d47ab1b35fc47768536ad34a875e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2deb82207572d47ab1b35fc47768536ad34a875e

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Dec  6 11:51:51 2017 +1100

ac: add store_tcs_outputs() to the abi

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/amd/common/ac_nir_to_llvm.c | 63 +
 src/amd/common/ac_shader_abi.h  | 12 
 2 files changed, 51 insertions(+), 24 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 8c6a276da6..5bd2f28ca0 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2902,65 +2902,64 @@ load_tcs_output(struct nir_to_llvm_context *ctx,
 }
 
 static void
-store_tcs_output(struct nir_to_llvm_context *ctx,
-nir_intrinsic_instr *instr,
+store_tcs_output(struct ac_shader_abi *abi,
+LLVMValueRef vertex_index,
+LLVMValueRef param_index,
+unsigned const_index,
+unsigned location,
+unsigned driver_location,
 LLVMValueRef src,
+unsigned component,
+bool is_patch,
+bool is_compact,
 unsigned writemask)
 {
+   struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
LLVMValueRef dw_addr;
LLVMValueRef stride = NULL;
LLVMValueRef buf_addr = NULL;
-   LLVMValueRef vertex_index = NULL;
-   LLVMValueRef indir_index = NULL;
-   unsigned const_index = 0;
unsigned param;
-   const unsigned comp = instr->variables[0]->var->data.location_frac;
-   const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, 
ctx->stage);
-   const bool is_compact = instr->variables[0]->var->data.compact;
bool store_lds = true;
 
-   if (instr->variables[0]->var->data.patch) {
-   if (!(ctx->tcs_patch_outputs_read & (1U << 
(instr->variables[0]->var->data.location - VARYING_SLOT_PATCH0
+   if (is_patch) {
+   if (!(ctx->tcs_patch_outputs_read & (1U << (location - 
VARYING_SLOT_PATCH0
store_lds = false;
} else {
-   if (!(ctx->tcs_outputs_read & (1ULL << 
instr->variables[0]->var->data.location)))
+   if (!(ctx->tcs_outputs_read & (1ULL << location)))
store_lds = false;
}
-   get_deref_offset(ctx->nir, instr->variables[0],
-false, NULL, per_vertex ? _index : NULL,
-_index, _index);
 
-   param = 
shader_io_get_unique_index(instr->variables[0]->var->data.location);
-   if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 
&&
+   param = shader_io_get_unique_index(location);
+   if (location == VARYING_SLOT_CLIP_DIST0 &&
is_compact && const_index > 3) {
const_index -= 3;
param++;
}
 
-   if (!instr->variables[0]->var->data.patch) {
+   if (!is_patch) {
stride = unpack_param(>ac, ctx->tcs_out_layout, 13, 8);
dw_addr = get_tcs_out_current_patch_offset(ctx);
} else {
dw_addr = get_tcs_out_current_patch_data_offset(ctx);
}
 
-   mark_tess_output(ctx, instr->variables[0]->var->data.patch, param);
+   mark_tess_output(ctx, is_patch, param);
 
dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, 
vertex_index, stride,
-indir_index);
+param_index);
buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, 
is_compact,
-vertex_index, indir_index);
+vertex_index, param_index);
 
bool is_tess_factor = false;
-   if (instr->variables[0]->var->data.location == 
VARYING_SLOT_TESS_LEVEL_INNER ||
-   instr->variables[0]->var->data.location == 
VARYING_SLOT_TESS_LEVEL_OUTER)
+   if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
+   location == VARYING_SLOT_TESS_LEVEL_OUTER)
is_tess_factor = true;
 
unsigned base = is_compact ? const_index : 0;
for (unsigned chan = 0; chan < 8; chan++) {
if (!(writemask & (1 << chan)))
continue;
-   LLVMValueRef value = llvm_extract_elem(>ac, src, chan - 
comp);
+   LLVMValueRef value = llvm_extract_elem(>ac, src, chan - 
component);
 

Mesa (master): radeonsi: make si_llvm_emit_tcs_epilogue compatible with emit_outputs abi

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: eb1e555cfdac76696c71ffa93a686f7c5d54f9fa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eb1e555cfdac76696c71ffa93a686f7c5d54f9fa

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Dec  6 17:02:30 2017 +1100

radeonsi: make si_llvm_emit_tcs_epilogue compatible with emit_outputs abi

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader.c | 10 +++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 5945c3e506..45c4720d35 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -3239,9 +3239,12 @@ si_insert_input_ptr_as_2xi32(struct si_shader_context 
*ctx, LLVMValueRef ret,
 }
 
 /* This only writes the tessellation factor levels. */
-static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
+static void si_llvm_emit_tcs_epilogue(struct ac_shader_abi *abi,
+ unsigned max_outputs,
+ LLVMValueRef *addrs)
 {
-   struct si_shader_context *ctx = si_shader_context(bld_base);
+   struct si_shader_context *ctx = si_shader_context_from_abi(abi);
+   struct lp_build_tgsi_context *bld_base = >bld_base;
LLVMBuilderRef builder = ctx->ac.builder;
LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
 
@@ -5949,7 +5952,8 @@ static bool si_compile_tgsi_main(struct si_shader_context 
*ctx,
bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
bld_base->emit_store = store_output_tcs;
ctx->abi.store_tcs_outputs = si_nir_store_output_tcs;
-   bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;
+   ctx->abi.emit_outputs = si_llvm_emit_tcs_epilogue;
+   bld_base->emit_epilogue = si_tgsi_emit_epilogue;
break;
case PIPE_SHADER_TESS_EVAL:
bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;

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Mesa (master): radeonsi: add si_nir_load_input_tcs()

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 8be0135082c303515d83b825a3dd0b0182908d4e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8be0135082c303515d83b825a3dd0b0182908d4e

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Dec  5 12:56:12 2017 +1100

radeonsi: add si_nir_load_input_tcs()

V2: drop type param and just use ctx->i32

Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader.c | 45 
 1 file changed, 45 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 0696020c41..816396bf86 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1208,6 +1208,50 @@ static LLVMValueRef fetch_input_tcs(
return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, 
dw_addr);
 }
 
+static LLVMValueRef si_nir_load_input_tcs(struct ac_shader_abi *abi,
+ LLVMValueRef vertex_index,
+ LLVMValueRef param_index,
+ unsigned const_index,
+ unsigned location,
+ unsigned driver_location,
+ unsigned component,
+ unsigned num_components,
+ bool is_patch,
+ bool is_compact)
+{
+   struct si_shader_context *ctx = si_shader_context_from_abi(abi);
+   struct tgsi_shader_info *info = >shader->selector->info;
+   struct lp_build_tgsi_context *bld_base = >bld_base;
+   LLVMValueRef dw_addr, stride;
+
+   driver_location = driver_location / 4;
+
+   stride = get_tcs_in_vertex_dw_stride(ctx);
+   dw_addr = get_tcs_in_current_patch_offset(ctx);
+
+   if (param_index) {
+   /* Add the constant index to the indirect index */
+   param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
+  LLVMConstInt(ctx->i32, const_index, 
0), "");
+   } else {
+   param_index = LLVMConstInt(ctx->i32, const_index, 0);
+   }
+
+   dw_addr = get_dw_address_from_generic_indices(ctx, stride, dw_addr,
+ vertex_index, param_index,
+ driver_location,
+ info->input_semantic_name,
+ 
info->input_semantic_index,
+ is_patch);
+
+   LLVMValueRef value[4];
+   for (unsigned i = 0; i < num_components + component; i++) {
+   value[i] = lds_load(bld_base, ctx->i32, i, dw_addr);
+   }
+
+   return ac_build_varying_gather_values(>ac, value, num_components, 
component);
+}
+
 static LLVMValueRef fetch_output_tcs(
struct lp_build_tgsi_context *bld_base,
const struct tgsi_full_src_register *reg,
@@ -5778,6 +5822,7 @@ static bool si_compile_tgsi_main(struct si_shader_context 
*ctx,
break;
case PIPE_SHADER_TESS_CTRL:
bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
+   ctx->abi.load_tess_inputs = si_nir_load_input_tcs;
bld_base->emit_fetch_funcs[TGSI_FILE_OUTPUT] = fetch_output_tcs;
bld_base->emit_store = store_output_tcs;
bld_base->emit_epilogue = si_llvm_emit_tcs_epilogue;

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Mesa (master): ac: add load_tes_inputs() to the abi

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: b09a3196e038b521c6fd31d007e564be036d1144
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b09a3196e038b521c6fd31d007e564be036d1144

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Dec  5 10:31:49 2017 +1100

ac: add load_tes_inputs() to the abi

V2: drop type param and just use ctx->i32

Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/amd/common/ac_nir_to_llvm.c  | 62 
 src/amd/common/ac_shader_abi.h   | 11 ++
 src/gallium/drivers/radeonsi/si_shader.c |  1 +
 3 files changed, 52 insertions(+), 22 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index f1db730a25..7a99461477 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2984,39 +2984,36 @@ store_tcs_output(struct nir_to_llvm_context *ctx,
 }
 
 static LLVMValueRef
-load_tes_input(struct nir_to_llvm_context *ctx,
-  const nir_intrinsic_instr *instr)
+load_tes_input(struct ac_shader_abi *abi,
+  LLVMValueRef vertex_index,
+  LLVMValueRef param_index,
+  unsigned const_index,
+  unsigned location,
+  unsigned driver_location,
+  unsigned component,
+  unsigned num_components,
+  bool is_patch,
+  bool is_compact)
 {
+   struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
LLVMValueRef buf_addr;
LLVMValueRef result;
-   LLVMValueRef vertex_index = NULL;
-   LLVMValueRef indir_index = NULL;
-   unsigned const_index = 0;
-   unsigned param;
-   const bool per_vertex = nir_is_per_vertex_io(instr->variables[0]->var, 
ctx->stage);
-   const bool is_compact = instr->variables[0]->var->data.compact;
+   unsigned param = shader_io_get_unique_index(location);
 
-   get_deref_offset(ctx->nir, instr->variables[0],
-false, NULL, per_vertex ? _index : NULL,
-_index, _index);
-   param = 
shader_io_get_unique_index(instr->variables[0]->var->data.location);
-   if (instr->variables[0]->var->data.location == VARYING_SLOT_CLIP_DIST0 
&&
-   is_compact && const_index > 3) {
+   if (location == VARYING_SLOT_CLIP_DIST0 && is_compact && const_index > 
3) {
const_index -= 3;
param++;
}
 
-   unsigned comp = instr->variables[0]->var->data.location_frac;
buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
-is_compact, vertex_index, 
indir_index);
+is_compact, vertex_index, 
param_index);
 
-   LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, comp * 4, false);
+   LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, 
false);
buf_addr = LLVMBuildAdd(ctx->builder, buf_addr, comp_offset, "");
 
-   result = ac_build_buffer_load(>ac, ctx->hs_ring_tess_offchip, 
instr->num_components, NULL,
+   result = ac_build_buffer_load(>ac, ctx->hs_ring_tess_offchip, 
num_components, NULL,
  buf_addr, ctx->oc_lds, is_compact ? (4 * 
const_index) : 0, 1, 0, true, false);
-   result = trim_vector(>ac, result, instr->num_components);
-   result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, 
>dest.ssa), "");
+   result = trim_vector(>ac, result, num_components);
return result;
 }
 
@@ -3133,8 +3130,28 @@ static LLVMValueRef visit_load_var(struct ac_nir_context 
*ctx,
case nir_var_shader_in:
if (ctx->stage == MESA_SHADER_TESS_CTRL)
return load_tcs_input(ctx->nctx, instr);
-   if (ctx->stage == MESA_SHADER_TESS_EVAL)
-   return load_tes_input(ctx->nctx, instr);
+   if (ctx->stage == MESA_SHADER_TESS_EVAL) {
+   LLVMValueRef result;
+   LLVMValueRef vertex_index = NULL;
+   LLVMValueRef indir_index = NULL;
+   unsigned const_index = 0;
+   unsigned location = 
instr->variables[0]->var->data.location;
+   unsigned driver_location = 
instr->variables[0]->var->data.driver_location;
+   const bool is_patch =  
instr->variables[0]->var->data.patch;
+   const bool is_compact = 
instr->variables[0]->var->data.compact;
+
+   get_deref_offset(ctx, instr->variables[0],
+false, NULL, is_patch ? NULL : 
_index,
+ 

Mesa (master): st/glsl_to_nir/radeonsi: enable tessellation shaders

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 71f82dc9a3d9823f91e4cf9d5ab9d54047ba8ce4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=71f82dc9a3d9823f91e4cf9d5ab9d54047ba8ce4

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Dec  6 13:32:17 2017 +1100

st/glsl_to_nir/radeonsi: enable tessellation shaders

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader_nir.c | 2 ++
 src/mesa/state_tracker/st_glsl_to_nir.cpp| 4 +++-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index d331dfeaaa..d5b8f835b9 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -157,6 +157,8 @@ void si_nir_scan_shader(const struct nir_shader *nir,
 
assert(nir->info.stage == MESA_SHADER_VERTEX ||
   nir->info.stage == MESA_SHADER_GEOMETRY ||
+  nir->info.stage == MESA_SHADER_TESS_CTRL ||
+  nir->info.stage == MESA_SHADER_TESS_EVAL ||
   nir->info.stage == MESA_SHADER_FRAGMENT);
 
info->processor = pipe_shader_type_from_mesa(nir->info.stage);
diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 276450a64a..5683df 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -675,7 +675,9 @@ st_finalize_nir(struct st_context *st, struct gl_program 
*prog,
   >num_outputs,
   nir->info.stage);
   st_nir_fixup_varying_slots(st, >outputs);
-   } else if (nir->info.stage == MESA_SHADER_GEOMETRY) {
+   } else if (nir->info.stage == MESA_SHADER_GEOMETRY ||
+  nir->info.stage == MESA_SHADER_TESS_CTRL ||
+  nir->info.stage == MESA_SHADER_TESS_EVAL) {
   sort_varyings(>inputs);
   st_nir_assign_var_locations(>inputs,
   >num_inputs,

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Mesa (master): gallium/tgsi: add patch support to tgsi_get_gl_varying_semantic()

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 9755eeb15a1396e36afc068d31aa109adbdd3082
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9755eeb15a1396e36afc068d31aa109adbdd3082

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Mon Dec 11 11:45:09 2017 +1100

gallium/tgsi: add patch support to tgsi_get_gl_varying_semantic()

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/gallium/auxiliary/tgsi/tgsi_from_mesa.c | 11 ---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_from_mesa.c 
b/src/gallium/auxiliary/tgsi/tgsi_from_mesa.c
index c014115918..659156b519 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_from_mesa.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_from_mesa.c
@@ -154,9 +154,14 @@ tgsi_get_gl_varying_semantic(gl_varying_slot attr,
default:
   assert(attr >= VARYING_SLOT_VAR0 ||
  (attr >= VARYING_SLOT_TEX0 && attr <= VARYING_SLOT_TEX7));
-  *semantic_name = TGSI_SEMANTIC_GENERIC;
-  *semantic_index =
- tgsi_get_generic_gl_varying_index(attr, needs_texcoord_semantic);
+  if (attr >= VARYING_SLOT_PATCH0) {
+ *semantic_name = TGSI_SEMANTIC_PATCH;
+ *semantic_index = attr - VARYING_SLOT_PATCH0;
+  } else {
+ *semantic_name = TGSI_SEMANTIC_GENERIC;
+ *semantic_index =
+tgsi_get_generic_gl_varying_index(attr, needs_texcoord_semantic);
+  }
   break;
}
 }

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Mesa (master): radeonsi: add nir support for tcs outputs

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 15c6f3fdd5e507574097d1ec231ffb194a1a287b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=15c6f3fdd5e507574097d1ec231ffb194a1a287b

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Dec  6 12:04:02 2017 +1100

radeonsi: add nir support for tcs outputs

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader.c | 118 +++
 1 file changed, 118 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 816396bf86..39a8906312 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1434,6 +1434,123 @@ static void store_output_tcs(struct 
lp_build_tgsi_context *bld_base,
}
 }
 
+static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
+   LLVMValueRef vertex_index,
+   LLVMValueRef param_index,
+   unsigned const_index,
+   unsigned location,
+   unsigned driver_location,
+   LLVMValueRef src,
+   unsigned component,
+   bool is_patch,
+   bool is_compact,
+   unsigned writemask)
+{
+   struct si_shader_context *ctx = si_shader_context_from_abi(abi);
+   struct tgsi_shader_info *info = >shader->selector->info;
+   LLVMValueRef dw_addr, stride;
+   LLVMValueRef buffer, base, addr;
+   LLVMValueRef values[4];
+   bool skip_lds_store;
+   bool is_tess_factor = false, is_tess_inner = false;
+
+   driver_location = driver_location / 4;
+
+   if (param_index) {
+   /* Add the constant index to the indirect index */
+   param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
+  LLVMConstInt(ctx->i32, const_index, 
0), "");
+   } else {
+   if (const_index != 0)
+   param_index = LLVMConstInt(ctx->i32, const_index, 0);
+   }
+
+   if (!is_patch) {
+   stride = get_tcs_out_vertex_dw_stride(ctx);
+   dw_addr = get_tcs_out_current_patch_offset(ctx);
+   dw_addr = get_dw_address_from_generic_indices(ctx, stride, 
dw_addr,
+ vertex_index, 
param_index,
+ driver_location,
+ 
info->output_semantic_name,
+ 
info->output_semantic_index,
+ is_patch);
+
+   skip_lds_store = !info->reads_pervertex_outputs;
+   } else {
+   dw_addr = get_tcs_out_current_patch_data_offset(ctx);
+   dw_addr = get_dw_address_from_generic_indices(ctx, NULL, 
dw_addr,
+ vertex_index, 
param_index,
+ driver_location,
+ 
info->output_semantic_name,
+ 
info->output_semantic_index,
+ is_patch);
+
+   skip_lds_store = !info->reads_perpatch_outputs;
+
+   if (!param_index) {
+   int name = info->output_semantic_name[driver_location];
+
+   /* Always write tess factors into LDS for the TCS 
epilog. */
+   if (name == TGSI_SEMANTIC_TESSINNER ||
+   name == TGSI_SEMANTIC_TESSOUTER) {
+   /* The epilog doesn't read LDS if invocation 0 
defines tess factors. */
+   skip_lds_store = 
!info->reads_tessfactor_outputs &&
+
ctx->shader->selector->tcs_info.tessfactors_are_def_in_all_invocs;
+   is_tess_factor = true;
+   is_tess_inner = name == TGSI_SEMANTIC_TESSINNER;
+   }
+   }
+   }
+
+   buffer = desc_from_addr_base64k(ctx, 
ctx->param_tcs_offchip_addr_base64k);
+
+   base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
+
+   addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, 
vertex_index,
+  param_index, 
driver_loca

Mesa (master): ac: move some helpers to ac_llvm_build.c

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: b99ebaa4fd7ab1f4b1f3ff5b965d422f67a8cb40
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b99ebaa4fd7ab1f4b1f3ff5b965d422f67a8cb40

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Mon Dec 11 12:54:47 2017 +1100

ac: move some helpers to ac_llvm_build.c

We will call these from the radeonsi NIR backend.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/amd/common/ac_llvm_build.c  | 24 +
 src/amd/common/ac_llvm_build.h  |  8 ++
 src/amd/common/ac_nir_to_llvm.c | 58 +
 3 files changed, 50 insertions(+), 40 deletions(-)

diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index c74a47a799..0ea5e7f4ca 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -99,6 +99,30 @@ ac_llvm_context_init(struct ac_llvm_context *ctx, 
LLVMContextRef context,
ctx->empty_md = LLVMMDNodeInContext(ctx->context, NULL, 0);
 }
 
+int
+ac_get_llvm_num_components(LLVMValueRef value)
+{
+   LLVMTypeRef type = LLVMTypeOf(value);
+   unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
+ ? LLVMGetVectorSize(type)
+ : 1;
+   return num_components;
+}
+
+LLVMValueRef
+ac_llvm_extract_elem(struct ac_llvm_context *ac,
+LLVMValueRef value,
+int index)
+{
+   int count = ac_get_llvm_num_components(value);
+
+   if (count == 1)
+   return value;
+
+   return LLVMBuildExtractElement(ac->builder, value,
+  LLVMConstInt(ac->i32, index, false), "");
+}
+
 unsigned
 ac_get_type_size(LLVMTypeRef type)
 {
diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index 6427d5315a..3c81e2d43d 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -83,6 +83,14 @@ void
 ac_llvm_context_init(struct ac_llvm_context *ctx, LLVMContextRef context,
 enum chip_class chip_class, enum radeon_family family);
 
+int
+ac_get_llvm_num_components(LLVMValueRef value);
+
+LLVMValueRef
+ac_llvm_extract_elem(struct ac_llvm_context *ac,
+LLVMValueRef value,
+int index);
+
 unsigned ac_get_type_size(LLVMTypeRef type);
 
 LLVMTypeRef ac_to_integer_type(struct ac_llvm_context *ctx, LLVMTypeRef t);
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 5bd2f28ca0..f8a63eab82 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1127,32 +1127,10 @@ static void create_function(struct nir_to_llvm_context 
*ctx,
ctx->shader_info->num_user_sgprs = user_sgpr_idx;
 }
 
-static int get_llvm_num_components(LLVMValueRef value)
-{
-   LLVMTypeRef type = LLVMTypeOf(value);
-   unsigned num_components = LLVMGetTypeKind(type) == LLVMVectorTypeKind
- ? LLVMGetVectorSize(type)
- : 1;
-   return num_components;
-}
-
-static LLVMValueRef llvm_extract_elem(struct ac_llvm_context *ac,
- LLVMValueRef value,
- int index)
-{
-   int count = get_llvm_num_components(value);
-
-   if (count == 1)
-   return value;
-
-   return LLVMBuildExtractElement(ac->builder, value,
-  LLVMConstInt(ac->i32, index, false), "");
-}
-
 static LLVMValueRef trim_vector(struct ac_llvm_context *ctx,
 LLVMValueRef value, unsigned count)
 {
-   unsigned num_components = get_llvm_num_components(value);
+   unsigned num_components = ac_get_llvm_num_components(value);
if (count == num_components)
return value;
 
@@ -2453,7 +2431,7 @@ static void visit_store_ssbo(struct ac_nir_context *ctx,
 
} else {
assert(count == 1);
-   if (get_llvm_num_components(base_data) > 1)
+   if (ac_get_llvm_num_components(base_data) > 1)
data = LLVMBuildExtractElement(ctx->ac.builder, 
base_data,
   
LLVMConstInt(ctx->ac.i32, start, false), "");
else
@@ -2480,9 +2458,9 @@ static LLVMValueRef visit_atomic_ssbo(struct 
ac_nir_context *ctx,
int arg_count = 0;
 
if (instr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap) {
-   params[arg_count++] = llvm_extract_elem(>ac, get_src(ctx, 
instr->src[3]), 0);
+   params[arg_count++] = ac_llvm_extract_elem(>ac, 
get_src(ctx, instr->src[3]), 0);
}
-   params[arg_count++] = llvm_extract

Mesa (master): radeonsi: add si_nir_load_input_tes()

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: e04bf8a61915c4a41171dec584679df42b50712d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e04bf8a61915c4a41171dec584679df42b50712d

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Thu Nov 23 13:04:46 2017 +1100

radeonsi: add si_nir_load_input_tes()

V2: drop type param and just use ctx->i32

Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader.c  | 48 +++
 src/gallium/drivers/radeonsi/si_shader_internal.h | 11 ++
 2 files changed, 59 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index ef1b460f45..bb251986ff 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1229,6 +1229,54 @@ static LLVMValueRef fetch_input_tes(
   buffer, base, addr, true);
 }
 
+LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
+  LLVMValueRef vertex_index,
+  LLVMValueRef param_index,
+  unsigned const_index,
+  unsigned location,
+  unsigned driver_location,
+  unsigned component,
+  unsigned num_components,
+  bool is_patch,
+  bool is_compact)
+{
+   struct si_shader_context *ctx = si_shader_context_from_abi(abi);
+   struct tgsi_shader_info *info = >shader->selector->info;
+   LLVMValueRef buffer, base, addr;
+
+   driver_location = driver_location / 4;
+
+   buffer = desc_from_addr_base64k(ctx, 
ctx->param_tcs_offchip_addr_base64k);
+
+   base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
+
+   if (param_index) {
+   /* Add the constant index to the indirect index */
+   param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
+  LLVMConstInt(ctx->i32, const_index, 
0), "");
+   } else {
+   param_index = LLVMConstInt(ctx->i32, const_index, 0);
+   }
+
+   addr = get_tcs_tes_buffer_address_from_generic_indices(ctx, 
vertex_index,
+  param_index, 
driver_location,
+  
info->input_semantic_name,
+  
info->input_semantic_index,
+  is_patch);
+
+   /* TODO: This will generate rather ordinary llvm code, although it
+* should be easy for the optimiser to fix up. In future we might want
+* to refactor buffer_load(), but for now this maximises code sharing
+* between the NIR and TGSI backends.
+*/
+   LLVMValueRef value[4];
+   for (unsigned i = component; i < num_components + component; i++) {
+   value[i] = buffer_load(>bld_base, ctx->i32, i, buffer, 
base, addr, true);
+   }
+
+   return ac_build_varying_gather_values(>ac, value, num_components, 
component);
+}
+
 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
 const struct tgsi_full_instruction *inst,
 const struct tgsi_opcode_info *info,
diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h 
b/src/gallium/drivers/radeonsi/si_shader_internal.h
index e05927c7fd..378bfc1a7a 100644
--- a/src/gallium/drivers/radeonsi/si_shader_internal.h
+++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
@@ -277,6 +277,17 @@ LLVMValueRef si_llvm_emit_fetch(struct 
lp_build_tgsi_context *bld_base,
enum tgsi_opcode_type type,
unsigned swizzle);
 
+LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
+  LLVMValueRef vertex_index,
+  LLVMValueRef param_index,
+  unsigned const_index,
+  unsigned location,
+  unsigned driver_location,
+  unsigned component,
+  unsigned num_components,
+  bool is_patch,
+  bool is_compact);
+
 LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
   unsigned input_index,
   unsigned vtx_offset_param,

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Mesa (master): radeonsi/nir: gather tess properties

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 91f3c4ec1bfe527c15c7f1983f409b7ff6cc3790
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=91f3c4ec1bfe527c15c7f1983f409b7ff6cc3790

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Dec  6 16:02:34 2017 +1100

radeonsi/nir: gather tess properties

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader_nir.c | 29 
 1 file changed, 29 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 4138e04dcb..2757d4e411 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -83,6 +83,9 @@ static void scan_instruction(struct tgsi_shader_info *info,
case nir_intrinsic_load_instance_id:
info->uses_instanceid = 1;
break;
+   case nir_intrinsic_load_invocation_id:
+   info->uses_invocationid = true;
+   break;
case nir_intrinsic_load_vertex_id:
info->uses_vertexid = 1;
break;
@@ -95,6 +98,10 @@ static void scan_instruction(struct tgsi_shader_info *info,
case nir_intrinsic_load_primitive_id:
info->uses_primid = 1;
break;
+   case nir_intrinsic_load_tess_level_inner:
+   case nir_intrinsic_load_tess_level_outer:
+   info->reads_tess_factors = true;
+   break;
case nir_intrinsic_image_store:
case nir_intrinsic_image_atomic_add:
case nir_intrinsic_image_atomic_min:
@@ -137,6 +144,28 @@ void si_nir_scan_shader(const struct nir_shader *nir,
info->num_tokens = 2; /* indicate that the shader is non-empty */
info->num_instructions = 2;
 
+   if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
+   info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT] =
+   nir->info.tess.tcs_vertices_out;
+   }
+
+   if (nir->info.stage == MESA_SHADER_TESS_EVAL) {
+   if (nir->info.tess.primitive_mode == GL_ISOLINES)
+   info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = 
PIPE_PRIM_LINES;
+   else
+   info->properties[TGSI_PROPERTY_TES_PRIM_MODE] = 
nir->info.tess.primitive_mode;
+
+   STATIC_ASSERT((TESS_SPACING_EQUAL + 1) % 3 == 
PIPE_TESS_SPACING_EQUAL);
+   STATIC_ASSERT((TESS_SPACING_FRACTIONAL_ODD + 1) % 3 ==
+ PIPE_TESS_SPACING_FRACTIONAL_ODD);
+   STATIC_ASSERT((TESS_SPACING_FRACTIONAL_EVEN + 1) % 3 ==
+ PIPE_TESS_SPACING_FRACTIONAL_EVEN);
+
+   info->properties[TGSI_PROPERTY_TES_SPACING] = 
(nir->info.tess.spacing + 1) % 3;
+   info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW] = 
!nir->info.tess.ccw;
+   info->properties[TGSI_PROPERTY_TES_POINT_MODE] = 
nir->info.tess.point_mode;
+   }
+
if (nir->info.stage == MESA_SHADER_GEOMETRY) {
info->properties[TGSI_PROPERTY_GS_INPUT_PRIM] = 
nir->info.gs.input_primitive;
info->properties[TGSI_PROPERTY_GS_OUTPUT_PRIM] = 
nir->info.gs.output_primitive;

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Mesa (master): radeonsi: add dummy implementation of si_nir_scan_tess_ctrl ()

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 452586b56ab4cc787cd5843f6fd89e682e24ec79
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=452586b56ab4cc787cd5843f6fd89e682e24ec79

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Thu Dec  7 13:11:32 2017 +1100

radeonsi: add dummy implementation of si_nir_scan_tess_ctrl()

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader.h|  3 +++
 src/gallium/drivers/radeonsi/si_shader_nir.c| 19 +++
 src/gallium/drivers/radeonsi/si_state_shaders.c |  1 +
 3 files changed, 23 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader.h 
b/src/gallium/drivers/radeonsi/si_shader.h
index c981d3562e..c449aa9684 100644
--- a/src/gallium/drivers/radeonsi/si_shader.h
+++ b/src/gallium/drivers/radeonsi/si_shader.h
@@ -652,6 +652,9 @@ const char *si_get_shader_name(const struct si_shader 
*shader, unsigned processo
 /* si_shader_nir.c */
 void si_nir_scan_shader(const struct nir_shader *nir,
struct tgsi_shader_info *info);
+void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
+  const struct tgsi_shader_info *info,
+  struct tgsi_tessctrl_info *out);
 void si_lower_nir(struct si_shader_selector *sel);
 
 /* Inline helpers. */
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 2757d4e411..d331dfeaaa 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -130,6 +130,25 @@ static void scan_instruction(struct tgsi_shader_info *info,
}
 }
 
+void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
+  const struct tgsi_shader_info *info,
+  struct tgsi_tessctrl_info *out)
+{
+   memset(out, 0, sizeof(*out));
+
+   if (nir->info.stage != MESA_SHADER_TESS_CTRL)
+   return;
+
+   /* Initial value = true. Here the pass will accumulate results from
+* multiple segments surrounded by barriers. If tess factors aren't
+* written at all, it's a shader bug and we don't care if this will be
+* true.
+*/
+   out->tessfactors_are_def_in_all_invocs = true;
+
+   /* TODO: Implement scanning of tess factors, see tgsi backend. */
+}
+
 void si_nir_scan_shader(const struct nir_shader *nir,
struct tgsi_shader_info *info)
 {
diff --git a/src/gallium/drivers/radeonsi/si_state_shaders.c 
b/src/gallium/drivers/radeonsi/si_state_shaders.c
index 6fe6855ecc..ecb8a0dad8 100644
--- a/src/gallium/drivers/radeonsi/si_state_shaders.c
+++ b/src/gallium/drivers/radeonsi/si_state_shaders.c
@@ -2005,6 +2005,7 @@ static void *si_create_shader_selector(struct 
pipe_context *ctx,
sel->nir = state->ir.nir;
 
si_nir_scan_shader(sel->nir, >info);
+   si_nir_scan_tess_ctrl(sel->nir, >info, >tcs_info);
 
si_lower_nir(sel);
}

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Mesa (master): st/st_glsl_to_nir: call nir_lower_64bit_pack

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: ddc0e7941f688346b5ef4aa5ac630b904f28dcf6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ddc0e7941f688346b5ef4aa5ac630b904f28dcf6

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Thu Dec 14 16:02:45 2017 +1100

st/st_glsl_to_nir: call nir_lower_64bit_pack

Fixes 56 crashes in the radeonsi nir backend.

Tested-by: Dieter Nützel <die...@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/mesa/state_tracker/st_glsl_to_nir.cpp | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 7357eebae0..0ff8dcd68c 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -262,6 +262,7 @@ st_nir_opts(nir_shader *nir)
do {
   progress = false;
 
+  NIR_PASS_V(nir, nir_lower_64bit_pack);
   NIR_PASS(progress, nir, nir_copy_prop);
   NIR_PASS(progress, nir, nir_opt_remove_phis);
   NIR_PASS(progress, nir, nir_opt_dce);

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Mesa (master): st/glsl_to_nir: add patch support to st_nir_assign_var_locations()

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: a88532c612c49681b7622ce8a4afc7417c88694c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a88532c612c49681b7622ce8a4afc7417c88694c

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Thu Dec 14 10:14:34 2017 +1100

st/glsl_to_nir: add patch support to st_nir_assign_var_locations()

Tested-by: Dieter Nützel <die...@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/mesa/state_tracker/st_glsl_to_nir.cpp | 22 +-
 1 file changed, 17 insertions(+), 5 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index b411621ab2..276450a64a 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -126,8 +126,9 @@ st_nir_assign_var_locations(struct exec_list *var_list, 
unsigned *size,
 gl_shader_stage stage)
 {
unsigned location = 0;
-   unsigned assigned_locations[VARYING_SLOT_MAX];
+   unsigned assigned_locations[VARYING_SLOT_TESS_MAX];
uint64_t processed_locs = 0;
+   uint32_t processed_patch_locs = 0;
 
nir_foreach_variable(var, var_list) {
 
@@ -137,11 +138,24 @@ st_nir_assign_var_locations(struct exec_list *var_list, 
unsigned *size,
  type = glsl_get_array_element(type);
   }
 
+  bool processed = false;
+  if (var->data.patch) {
+ unsigned patch_loc = var->data.location - VARYING_SLOT_VAR0;
+ if (processed_patch_locs & (1 << patch_loc))
+processed = true;
+
+ processed_patch_locs |= (1 << patch_loc);
+  } else {
+ if (processed_locs & ((uint64_t)1 << var->data.location))
+processed = true;
+
+ processed_locs |= ((uint64_t)1 << var->data.location);
+  }
+
   /* Because component packing allows varyings to share the same location
* we may have already have processed this location.
*/
-  if (var->data.location >= VARYING_SLOT_VAR0 &&
-  processed_locs & ((uint64_t)1 << var->data.location)) {
+  if (processed && var->data.location >= VARYING_SLOT_VAR0) {
  var->data.driver_location = assigned_locations[var->data.location];
  *size += type_size(type);
  continue;
@@ -150,8 +164,6 @@ st_nir_assign_var_locations(struct exec_list *var_list, 
unsigned *size,
   assigned_locations[var->data.location] = location;
   var->data.driver_location = location;
   location += type_size(type);
-
-  processed_locs |= ((uint64_t)1 << var->data.location);
}
 
*size += location;

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Mesa (master): st/glsl_to_nir: call post opt functions after opts have finished

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 351eee05d346a8d226ecb6a5ab0a0e7d5b49aa66
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=351eee05d346a8d226ecb6a5ab0a0e7d5b49aa66

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Thu Dec 14 14:48:49 2017 +1100

st/glsl_to_nir: call post opt functions after opts have finished

We need to move this to a separate loop because
nir_compact_varyings() can alter the IR of a previous stage.

Fixes: 6648bd68fd27 "st/glsl_to_nir: enable NIR link time opts"

Tested-by: Dieter Nützel <die...@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/mesa/state_tracker/st_glsl_to_nir.cpp | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 0ff8dcd68c..b411621ab2 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -617,6 +617,12 @@ st_link_nir(struct gl_context *ctx,
   nir, ctx->API != API_OPENGL_COMPAT);
   }
   prev = i;
+   }
+
+   for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
+  struct gl_linked_shader *shader = shader_program->_LinkedShaders[i];
+  if (shader == NULL)
+ continue;
 
   st_glsl_to_nir_post_opts(st, shader->Program, shader_program);
 

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Mesa (master): radeonsi: create get_tcs_tes_buffer_address helper

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 3308f4b81a14ce14aa0efdd3d6a2383c4925fea3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3308f4b81a14ce14aa0efdd3d6a2383c4925fea3

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Thu Nov 23 12:59:01 2017 +1100

radeonsi: create get_tcs_tes_buffer_address helper

This will be shared between the NIR and TGSI backends.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader.c | 44 +++-
 1 file changed, 32 insertions(+), 12 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 5da9ec0bf5..0077054749 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -977,6 +977,34 @@ static LLVMValueRef get_tcs_tes_buffer_address(struct 
si_shader_context *ctx,
return base_addr;
 }
 
+/* This is a generic helper that can be shared by the NIR and TGSI backends */
+static LLVMValueRef get_tcs_tes_buffer_address_from_generic_indices(
+   struct si_shader_context *ctx,
+   LLVMValueRef vertex_index,
+   LLVMValueRef param_index,
+   unsigned param_base,
+   ubyte *name,
+   ubyte *index,
+   bool is_patch)
+{
+   unsigned param_index_base;
+
+   param_index_base = is_patch ?
+   si_shader_io_get_unique_index_patch(name[param_base], 
index[param_base]) :
+   si_shader_io_get_unique_index(name[param_base], 
index[param_base]);
+
+   if (param_index) {
+   param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
+  LLVMConstInt(ctx->i32, 
param_index_base, 0),
+  "");
+   } else {
+   param_index = LLVMConstInt(ctx->i32, param_index_base, 0);
+   }
+
+   return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
+ vertex_index, param_index);
+}
+
 static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
struct si_shader_context *ctx,
const struct tgsi_full_dst_register 
*dst,
@@ -987,7 +1015,7 @@ static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
struct tgsi_full_src_register reg;
LLVMValueRef vertex_index = NULL;
LLVMValueRef param_index = NULL;
-   unsigned param_index_base, param_base;
+   unsigned param_base;
 
reg = src ? *src : tgsi_full_src_register_from_dst(dst);
 
@@ -1025,19 +1053,11 @@ static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
 
} else {
param_base = reg.Register.Index;
-   param_index = ctx->i32_0;
}
 
-   param_index_base = reg.Register.Dimension ?
-   si_shader_io_get_unique_index(name[param_base], 
index[param_base]) :
-   si_shader_io_get_unique_index_patch(name[param_base], 
index[param_base]);
-
-   param_index = LLVMBuildAdd(ctx->ac.builder, param_index,
-  LLVMConstInt(ctx->i32, param_index_base, 0),
-  "");
-
-   return get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx),
- vertex_index, param_index);
+   return get_tcs_tes_buffer_address_from_generic_indices(ctx, 
vertex_index,
+  param_index, 
param_base,
+  name, index, 
!reg.Register.Dimension);
 }
 
 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,

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Mesa (master): ac: fix nir_op_f2f64

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: a5f9ac29282a39bad3cf1324557b1caaff37b4fb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a5f9ac29282a39bad3cf1324557b1caaff37b4fb

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Dec 12 16:10:24 2017 +1100

ac: fix nir_op_f2f64

Without this we get the error "FPExt only operates on FP" when
converting the following:

   vec1 32 ssa_5 = b2f ssa_4
   vec1 64 ssa_6 = f2f64 ssa_5

Which results in:

   %44 = and i32 %43, 1065353216
   %45 = fpext i32 %44 to double

With this patch we now get:

   %44 = and i32 %43, 1065353216
   %45 = bitcast i32 %44 to float
   %46 = fpext float %45 to double

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>

---

 src/amd/common/ac_nir_to_llvm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 3d26dd3752..f3602a267d 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1802,6 +1802,7 @@ static void visit_alu(struct ac_nir_context *ctx, const 
nir_alu_instr *instr)
result = LLVMBuildUIToFP(ctx->ac.builder, src[0], 
ac_to_float_type(>ac, def_type), "");
break;
case nir_op_f2f64:
+   src[0] = ac_to_float(>ac, src[0]);
result = LLVMBuildFPExt(ctx->ac.builder, src[0], 
ac_to_float_type(>ac, def_type), "");
break;
case nir_op_f2f32:

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Mesa (master): nir: fix shift for uint64_t

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: cab5513b4705a7f29fefe52fefb88952a9a19f4d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cab5513b4705a7f29fefe52fefb88952a9a19f4d

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Dec 12 13:52:50 2017 +1100

nir: fix shift for uint64_t

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/compiler/nir/nir_lower_io_arrays_to_elements.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/compiler/nir/nir_lower_io_arrays_to_elements.c 
b/src/compiler/nir/nir_lower_io_arrays_to_elements.c
index dca5719f11..cdf9a76a88 100644
--- a/src/compiler/nir/nir_lower_io_arrays_to_elements.c
+++ b/src/compiler/nir/nir_lower_io_arrays_to_elements.c
@@ -247,7 +247,7 @@ create_indirects_mask(nir_shader *shader, uint64_t 
*indirects,
if (var->data.mode != mode)
   continue;
 
-   uint64_t loc_mask = 1 << var->data.location;
+   uint64_t loc_mask = ((uint64_t)1) << var->data.location;
if (var->data.patch) {
   if (deref_has_indirect(, var, intr->variables[0]))
  patch_indirects[var->data.location_frac] |= loc_mask;
@@ -289,7 +289,7 @@ lower_io_arrays_to_elements(nir_shader *shader, 
nir_variable_mode mask,
nir_variable *var = intr->variables[0]->var;
 
/* Skip indirects */
-   uint64_t loc_mask = 1 << var->data.location;
+   uint64_t loc_mask = ((uint64_t)1) << var->data.location;
if (var->data.patch) {
   if (patch_indirects[var->data.location_frac] & loc_mask)
  continue;

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Mesa (master): i965: Fix memory leak when serializing nir

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 2e28494af2cbeb555856e984a1ff5ef2ac96411c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e28494af2cbeb555856e984a1ff5ef2ac96411c

Author: Jordan Justen <jordan.l.jus...@intel.com>
Date:   Fri Nov  3 17:18:32 2017 -0700

i965: Fix memory leak when serializing nir

Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>

---

 src/mesa/drivers/dri/i965/brw_program.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c
index be839ab38a..6aa41009e7 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -796,6 +796,7 @@ brw_program_serialize_nir(struct gl_context *ctx, struct 
gl_program *prog)
prog->driver_cache_blob = ralloc_size(NULL, writer.size);
memcpy(prog->driver_cache_blob, writer.data, writer.size);
prog->driver_cache_blob_size = writer.size;
+   blob_finish();
 }
 
 void

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Mesa (master): main: Clear shader program data whenever ProgramBinary is called

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: c1ff99fd70cd2ceb2cac4723e4fd5efc93834746
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c1ff99fd70cd2ceb2cac4723e4fd5efc93834746

Author: Jordan Justen 
Date:   Tue Nov  7 02:11:28 2017 -0800

main: Clear shader program data whenever ProgramBinary is called

The GL_ARB_get_program_binary extension spec says:

 "If ProgramBinary fails to load a binary, no error is generated, but
  any information about a previous link or load of that program object
  is lost."

v2:
 * Re-initialize shProg->data after clear. (Jordan)
   (Required after 6a72eba755fea15a0d97abb913a6315d9d32e274)

Signed-off-by: Jordan Justen 
Reviewed-by: Nicolai Hähnle 

---

 src/mesa/main/shaderapi.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index 51031e12ec..4607cbb99b 100644
--- a/src/mesa/main/shaderapi.c
+++ b/src/mesa/main/shaderapi.c
@@ -2221,6 +2221,9 @@ _mesa_ProgramBinary(GLuint program, GLenum binaryFormat,
if (!shProg)
   return;
 
+   _mesa_clear_shader_program_data(ctx, shProg);
+   shProg->data = _mesa_create_shader_program_data();
+
/* Section 2.3.1 (Errors) of the OpenGL 4.5 spec says:
 *
 * "If a negative number is provided where an argument of type sizei or

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Mesa (master): main: Support getting GL_PROGRAM_BINARY_LENGTH

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: e30ed18215c2b59b2b4de355b96fe553b5a8ce17
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e30ed18215c2b59b2b4de355b96fe553b5a8ce17

Author: Jordan Justen <jordan.l.jus...@intel.com>
Date:   Sat Nov  4 16:43:21 2017 -0700

main: Support getting GL_PROGRAM_BINARY_LENGTH

V2: call generic _mesa_get_program_binary_length() helper
rather than driver function directly to allow greater
code sharing.

Signed-off-by: Timothy Arceri <tarc...@itsqueeze.com>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> (v1)
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>i (v1)
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>

---

 src/mesa/main/shaderapi.c | 7 ++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index 7282435583..82a7fde697 100644
--- a/src/mesa/main/shaderapi.c
+++ b/src/mesa/main/shaderapi.c
@@ -45,6 +45,7 @@
 #include "main/hash.h"
 #include "main/mtypes.h"
 #include "main/pipelineobj.h"
+#include "main/program_binary.h"
 #include "main/shaderapi.h"
 #include "main/shaderobj.h"
 #include "main/transformfeedback.h"
@@ -834,7 +835,11 @@ get_programiv(struct gl_context *ctx, GLuint program, 
GLenum pname,
   *params = shProg->BinaryRetreivableHint;
   return;
case GL_PROGRAM_BINARY_LENGTH:
-  *params = 0;
+  if (ctx->Const.NumProgramBinaryFormats == 0) {
+ *params = 0;
+  } else {
+ _mesa_get_program_binary_length(ctx, shProg, params);
+  }
   return;
case GL_ACTIVE_ATOMIC_COUNTER_BUFFERS:
   if (!ctx->Extensions.ARB_shader_atomic_counters)

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Mesa (master): i965: Free serialized nir after deserializing

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: b3f1b765e964f2d4b6be38e7fbbe78b817aec100
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b3f1b765e964f2d4b6be38e7fbbe78b817aec100

Author: Jordan Justen <jordan.l.jus...@intel.com>
Date:   Fri Nov  3 16:45:46 2017 -0700

i965: Free serialized nir after deserializing

Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>

---

 src/mesa/drivers/dri/i965/brw_program.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c
index 2a647cdd73..30cc14e88a 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -800,4 +800,10 @@ brw_program_deserialize_nir(struct gl_context *ctx, struct 
gl_program *prog,
prog->driver_cache_blob_size);
   prog->nir = nir_deserialize(NULL, options, );
}
+
+   if (prog->driver_cache_blob) {
+  ralloc_free(prog->driver_cache_blob);
+  prog->driver_cache_blob = NULL;
+  prog->driver_cache_blob_size = 0;
+   }
 }

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Mesa (master): i965: Add brw_program_serialize_nir

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 25b3ce6e3ba4b2da2d278712b95f883807363070
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=25b3ce6e3ba4b2da2d278712b95f883807363070

Author: Jordan Justen <jordan.l.jus...@intel.com>
Date:   Fri Nov  3 16:57:42 2017 -0700

i965: Add brw_program_serialize_nir

Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>

---

 src/mesa/drivers/dri/i965/brw_link.cpp  |  7 +--
 src/mesa/drivers/dri/i965/brw_program.c | 11 +++
 src/mesa/drivers/dri/i965/brw_program.h |  2 ++
 3 files changed, 14 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_link.cpp 
b/src/mesa/drivers/dri/i965/brw_link.cpp
index 6177c8f5eb..64267671c0 100644
--- a/src/mesa/drivers/dri/i965/brw_link.cpp
+++ b/src/mesa/drivers/dri/i965/brw_link.cpp
@@ -355,12 +355,7 @@ brw_link_shader(struct gl_context *ctx, struct 
gl_shader_program *shProg)
 continue;
 
  struct gl_program *prog = shader->Program;
- struct blob writer;
- blob_init();
- nir_serialize(, prog->nir);
- prog->driver_cache_blob = ralloc_size(NULL, writer.size);
- memcpy(prog->driver_cache_blob, writer.data, writer.size);
- prog->driver_cache_blob_size = writer.size;
+ brw_program_serialize_nir(ctx, prog);
   }
}
 
diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c
index 30cc14e88a..be839ab38a 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -788,6 +788,17 @@ brw_assign_common_binding_table_offsets(const struct 
gen_device_info *devinfo,
 }
 
 void
+brw_program_serialize_nir(struct gl_context *ctx, struct gl_program *prog)
+{
+   struct blob writer;
+   blob_init();
+   nir_serialize(, prog->nir);
+   prog->driver_cache_blob = ralloc_size(NULL, writer.size);
+   memcpy(prog->driver_cache_blob, writer.data, writer.size);
+   prog->driver_cache_blob_size = writer.size;
+}
+
+void
 brw_program_deserialize_nir(struct gl_context *ctx, struct gl_program *prog,
 gl_shader_stage stage)
 {
diff --git a/src/mesa/drivers/dri/i965/brw_program.h 
b/src/mesa/drivers/dri/i965/brw_program.h
index bd9b4ad168..c89614d5c9 100644
--- a/src/mesa/drivers/dri/i965/brw_program.h
+++ b/src/mesa/drivers/dri/i965/brw_program.h
@@ -82,6 +82,8 @@ brw_assign_common_binding_table_offsets(const struct 
gen_device_info *devinfo,
 uint32_t next_binding_table_offset);
 
 void
+brw_program_serialize_nir(struct gl_context *ctx, struct gl_program *prog);
+void
 brw_program_deserialize_nir(struct gl_context *ctx, struct gl_program *prog,
 gl_shader_stage stage);
 

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Mesa (master): i965: Add ARB_get_program_binary support using nir_serialization

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: b4c37ce2140c0195005d865b7a4de903ef50a097
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b4c37ce2140c0195005d865b7a4de903ef50a097

Author: Jordan Justen <jordan.l.jus...@intel.com>
Date:   Sat Nov  4 16:53:15 2017 -0700

i965: Add ARB_get_program_binary support using nir_serialization

This resolves an apparent game bug described in 85564. The game
doesn't properly handle ARB_get_program_binary with 0 supported
formats.

V2 (Timothy Arceri):
 - less driver code as more has been moved into the common helpers.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=85564
Signed-off-by: Timothy Arceri <tarc...@itsqueeze.com>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> (v1)
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>

---

 src/mesa/drivers/dri/i965/Makefile.sources |  1 +
 src/mesa/drivers/dri/i965/brw_context.c| 10 
 src/mesa/drivers/dri/i965/brw_context.h| 15 ++
 src/mesa/drivers/dri/i965/brw_program.h|  6 ---
 src/mesa/drivers/dri/i965/brw_program_binary.c | 72 ++
 src/mesa/drivers/dri/i965/meson.build  |  1 +
 6 files changed, 99 insertions(+), 6 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/Makefile.sources 
b/src/mesa/drivers/dri/i965/Makefile.sources
index 5599f0a4b1..d928f71b43 100644
--- a/src/mesa/drivers/dri/i965/Makefile.sources
+++ b/src/mesa/drivers/dri/i965/Makefile.sources
@@ -38,6 +38,7 @@ i965_FILES = \
brw_performance_query.c \
brw_program.c \
brw_program.h \
+   brw_program_binary.c \
brw_program_cache.c \
brw_primitive_restart.c \
brw_queryobj.c \
diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
b/src/mesa/drivers/dri/i965/brw_context.c
index b62852d90c..126c187f62 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++ b/src/mesa/drivers/dri/i965/brw_context.c
@@ -329,6 +329,13 @@ brw_init_driver_functions(struct brw_context *brw,
 
if (devinfo->gen >= 6)
   functions->GetSamplePosition = gen6_get_sample_position;
+
+   /* GL_ARB_get_program_binary */
+   brw_program_binary_init(brw->screen->deviceID);
+   functions->GetProgramBinaryDriverSHA1 = brw_get_program_binary_driver_sha1;
+   functions->ProgramBinarySerializeDriverBlob = brw_program_serialize_nir;
+   functions->ProgramBinaryDeserializeDriverBlob =
+  brw_deserialize_program_binary;
 }
 
 static void
@@ -696,6 +703,9 @@ brw_initialize_context_constants(struct brw_context *brw)
 
if (!(ctx->Const.ContextFlags & GL_CONTEXT_FLAG_DEBUG_BIT))
   ctx->Const.AllowMappedBuffersDuringExecution = true;
+
+   /* GL_ARB_get_program_binary */
+   ctx->Const.NumProgramBinaryFormats = 1;
 }
 
 static void
diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
b/src/mesa/drivers/dri/i965/brw_context.h
index aa91380b96..0f0aad8534 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -1579,6 +1579,21 @@ brw_check_for_reset(struct brw_context *brw);
 extern void
 brw_init_compute_functions(struct dd_function_table *functions);
 
+/* brw_program_binary.c */
+extern void
+brw_program_binary_init(unsigned device_id);
+extern void
+brw_get_program_binary_driver_sha1(struct gl_context *ctx, uint8_t *sha1);
+extern void
+brw_deserialize_program_binary(struct gl_context *ctx,
+   struct gl_shader_program *shProg,
+   struct gl_program *prog);
+void
+brw_program_serialize_nir(struct gl_context *ctx, struct gl_program *prog);
+void
+brw_program_deserialize_nir(struct gl_context *ctx, struct gl_program *prog,
+gl_shader_stage stage);
+
 /*==
  * Inline conversion functions.  These are better-typed than the
  * macros used previously:
diff --git a/src/mesa/drivers/dri/i965/brw_program.h 
b/src/mesa/drivers/dri/i965/brw_program.h
index c89614d5c9..701b8da482 100644
--- a/src/mesa/drivers/dri/i965/brw_program.h
+++ b/src/mesa/drivers/dri/i965/brw_program.h
@@ -82,12 +82,6 @@ brw_assign_common_binding_table_offsets(const struct 
gen_device_info *devinfo,
 uint32_t next_binding_table_offset);
 
 void
-brw_program_serialize_nir(struct gl_context *ctx, struct gl_program *prog);
-void
-brw_program_deserialize_nir(struct gl_context *ctx, struct gl_program *prog,
-gl_shader_stage stage);
-
-void
 brw_stage_prog_data_free(const void *prog_data);
 
 void
diff --git a/src/mesa/drivers/dri/i965/brw_program_binary.c 
b/src/mesa/drivers/dri/i965/brw_program_binary.c
new file mode 100644
index 00..f1b327de4b
--- /dev/null
+++ b/src/mesa/drivers/dri/i965/brw_program_binary.c
@@ -0,0 +1,72 @@
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of th

Mesa (master): main, glsl: Add UniformDataDefaults which stores uniform defaults

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 7cf1037d5af015912e84cd52a992be80f4f6092c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7cf1037d5af015912e84cd52a992be80f4f6092c

Author: Jordan Justen <jordan.l.jus...@intel.com>
Date:   Mon Oct 30 11:16:48 2017 -0700

main, glsl: Add UniformDataDefaults which stores uniform defaults

The ARB_get_program_binary extension requires that uniform values in a
program be restored to their initial value just after linking.

This patch saves off the initial values just after linking. When the
program is restored by glProgramBinary, we can use this to copy the
initial value of uniforms into UniformDataSlots.

V2 (Timothy Arceri):
 - Store UniformDataDefaults only when serializing GLSL as this
   is what we want for both disk cache and ARB_get_program_binary.
   This saves us having to come back later and reset the Uniforms
   on program binary restores.

Signed-off-by: Timothy Arceri <tarc...@itsqueeze.com>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> (v1)
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>

---

 src/compiler/glsl/link_uniform_initializers.cpp |  2 ++
 src/compiler/glsl/link_uniforms.cpp |  3 +++
 src/compiler/glsl/serialize.cpp | 16 ++--
 src/mesa/main/mtypes.h  | 11 +++
 4 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/src/compiler/glsl/link_uniform_initializers.cpp 
b/src/compiler/glsl/link_uniform_initializers.cpp
index be3715cc1a..97796e721b 100644
--- a/src/compiler/glsl/link_uniform_initializers.cpp
+++ b/src/compiler/glsl/link_uniform_initializers.cpp
@@ -357,5 +357,7 @@ link_set_uniform_initializers(struct gl_shader_program 
*prog,
   }
}
 
+   memcpy(prog->data->UniformDataDefaults, prog->data->UniformDataSlots,
+  sizeof(union gl_constant_value) * prog->data->NumUniformDataSlots);
ralloc_free(mem_ctx);
 }
diff --git a/src/compiler/glsl/link_uniforms.cpp 
b/src/compiler/glsl/link_uniforms.cpp
index 46c746bc70..15813cb0ae 100644
--- a/src/compiler/glsl/link_uniforms.cpp
+++ b/src/compiler/glsl/link_uniforms.cpp
@@ -1365,6 +1365,9 @@ link_assign_uniform_storage(struct gl_context *ctx,
  
prog->data->NumUniformStorage);
   data = rzalloc_array(prog->data->UniformStorage,
union gl_constant_value, num_data_slots);
+  prog->data->UniformDataDefaults =
+ rzalloc_array(prog->data->UniformStorage,
+   union gl_constant_value, num_data_slots);
} else {
   data = prog->data->UniformDataSlots;
}
diff --git a/src/compiler/glsl/serialize.cpp b/src/compiler/glsl/serialize.cpp
index b5f68f907f..57c91d90bb 100644
--- a/src/compiler/glsl/serialize.cpp
+++ b/src/compiler/glsl/serialize.cpp
@@ -449,7 +449,10 @@ write_uniforms(struct blob *metadata, struct 
gl_shader_program *prog)
  unsigned vec_size =
 prog->data->UniformStorage[i].type->component_slots() *
 MAX2(prog->data->UniformStorage[i].array_elements, 1);
- blob_write_bytes(metadata, prog->data->UniformStorage[i].storage,
+ unsigned slot =
+prog->data->UniformStorage[i].storage -
+prog->data->UniformDataSlots;
+ blob_write_bytes(metadata, >data->UniformDataDefaults[slot],
   sizeof(union gl_constant_value) * vec_size);
   }
}
@@ -472,6 +475,9 @@ read_uniforms(struct blob_reader *metadata, struct 
gl_shader_program *prog)
data = rzalloc_array(uniforms, union gl_constant_value,
 prog->data->NumUniformDataSlots);
prog->data->UniformDataSlots = data;
+   prog->data->UniformDataDefaults =
+  rzalloc_array(uniforms, union gl_constant_value,
+prog->data->NumUniformDataSlots);
 
prog->UniformHash = new string_to_uint_map;
 
@@ -512,14 +518,20 @@ read_uniforms(struct blob_reader *metadata, struct 
gl_shader_program *prog)
  unsigned vec_size =
 prog->data->UniformStorage[i].type->component_slots() *
 MAX2(prog->data->UniformStorage[i].array_elements, 1);
+ unsigned slot =
+prog->data->UniformStorage[i].storage -
+prog->data->UniformDataSlots;
  blob_copy_bytes(metadata,
- (uint8_t *) prog->data->UniformStorage[i].storage,
+ (uint8_t *) >data->UniformDataSlots[slot],
  sizeof(union gl_constant_value) * vec_size);
 
 assert(vec_size + prog->data->UniformStorage[i].storage <=
data +  prog->data->NumUniformDataSlots);
   }
}
+
+   memcpy(prog->data->UniformDataDefaults, prog->data->UniformDataSlots,
+  sizeof(union gl_constant_

Mesa (master): i965: Add brw_program_deserialize_nir

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: cdc7ac23b9ada9133fbacb28cf3b52dcadc51fac
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cdc7ac23b9ada9133fbacb28cf3b52dcadc51fac

Author: Jordan Justen <jordan.l.jus...@intel.com>
Date:   Fri Nov  3 16:40:17 2017 -0700

i965: Add brw_program_deserialize_nir

Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>

---

 src/mesa/drivers/dri/i965/brw_disk_cache.c | 31 --
 src/mesa/drivers/dri/i965/brw_program.c| 16 +++
 src/mesa/drivers/dri/i965/brw_program.h|  4 
 3 files changed, 28 insertions(+), 23 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_disk_cache.c 
b/src/mesa/drivers/dri/i965/brw_disk_cache.c
index 853ea98af0..65bb52726e 100644
--- a/src/mesa/drivers/dri/i965/brw_disk_cache.c
+++ b/src/mesa/drivers/dri/i965/brw_disk_cache.c
@@ -24,7 +24,6 @@
 #include "compiler/blob.h"
 #include "compiler/glsl/ir_uniform.h"
 #include "compiler/glsl/shader_cache.h"
-#include "compiler/nir/nir_serialize.h"
 #include "main/mtypes.h"
 #include "util/build_id.h"
 #include "util/debug.h"
@@ -62,27 +61,6 @@ gen_shader_sha1(struct brw_context *brw, struct gl_program 
*prog,
 }
 
 static void
-restore_serialized_nir_shader(struct brw_context *brw, struct gl_program *prog,
-  gl_shader_stage stage)
-{
-   prog->program_written_to_cache = false;
-   if (brw->ctx._Shader->Flags & GLSL_CACHE_INFO) {
-  fprintf(stderr, "falling back to nir %s.\n",
-  _mesa_shader_stage_to_abbrev(prog->info.stage));
-   }
-
-   if (!prog->nir) {
-  assert(prog->driver_cache_blob && prog->driver_cache_blob_size > 0);
-  const struct nir_shader_compiler_options *options =
- brw->ctx.Const.ShaderCompilerOptions[stage].NirOptions;
-  struct blob_reader reader;
-  blob_reader_init(, prog->driver_cache_blob,
-   prog->driver_cache_blob_size);
-  prog->nir = nir_deserialize(NULL, options, );
-   }
-}
-
-static void
 write_blob_program_data(struct blob *binary, gl_shader_stage stage,
 const void *program,
 struct brw_stage_prog_data *prog_data)
@@ -298,7 +276,14 @@ brw_disk_cache_upload_program(struct brw_context *brw, 
gl_shader_stage stage)
return true;
 
 fail:
-   restore_serialized_nir_shader(brw, prog, stage);
+   prog->program_written_to_cache = false;
+   if (brw->ctx._Shader->Flags & GLSL_CACHE_INFO) {
+  fprintf(stderr, "falling back to nir %s.\n",
+  _mesa_shader_stage_to_abbrev(prog->info.stage));
+   }
+
+   brw_program_deserialize_nir(>ctx, prog, stage);
+
return false;
 }
 
diff --git a/src/mesa/drivers/dri/i965/brw_program.c 
b/src/mesa/drivers/dri/i965/brw_program.c
index 755d4973cc..2a647cdd73 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++ b/src/mesa/drivers/dri/i965/brw_program.c
@@ -40,6 +40,7 @@
 #include "util/ralloc.h"
 #include "compiler/glsl/ir.h"
 #include "compiler/glsl/glsl_to_nir.h"
+#include "compiler/nir/nir_serialize.h"
 
 #include "brw_program.h"
 #include "brw_context.h"
@@ -785,3 +786,18 @@ brw_assign_common_binding_table_offsets(const struct 
gen_device_info *devinfo,
assert(next_binding_table_offset <= BRW_MAX_SURFACES);
return next_binding_table_offset;
 }
+
+void
+brw_program_deserialize_nir(struct gl_context *ctx, struct gl_program *prog,
+gl_shader_stage stage)
+{
+   if (!prog->nir) {
+  assert(prog->driver_cache_blob && prog->driver_cache_blob_size > 0);
+  const struct nir_shader_compiler_options *options =
+ ctx->Const.ShaderCompilerOptions[stage].NirOptions;
+  struct blob_reader reader;
+  blob_reader_init(, prog->driver_cache_blob,
+   prog->driver_cache_blob_size);
+  prog->nir = nir_deserialize(NULL, options, );
+   }
+}
diff --git a/src/mesa/drivers/dri/i965/brw_program.h 
b/src/mesa/drivers/dri/i965/brw_program.h
index 701b8da482..bd9b4ad168 100644
--- a/src/mesa/drivers/dri/i965/brw_program.h
+++ b/src/mesa/drivers/dri/i965/brw_program.h
@@ -82,6 +82,10 @@ brw_assign_common_binding_table_offsets(const struct 
gen_device_info *devinfo,
 uint32_t next_binding_table_offset);
 
 void
+brw_program_deserialize_nir(struct gl_context *ctx, struct gl_program *prog,
+gl_shader_stage stage);
+
+void
 brw_stage_prog_data_free(const void *prog_data);
 
 void

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Mesa (master): main: add binary support to GetProgramBinary

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 7ee54ad057f05881d650443de13a6bf8099e7922
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ee54ad057f05881d650443de13a6bf8099e7922

Author: Jordan Justen <jordan.l.jus...@intel.com>
Date:   Sat Nov  4 16:47:25 2017 -0700

main: add binary support to GetProgramBinary

V2: call generic _mesa_get_program_binary() helper rather than driver
function directly to allow greater code sharing.

Signed-off-by: Timothy Arceri <tarc...@itsqueeze.com>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> (v1)
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> (v1)
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>

---

 src/mesa/main/shaderapi.c | 15 +--
 1 file changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index 82a7fde697..b728b320ac 100644
--- a/src/mesa/main/shaderapi.c
+++ b/src/mesa/main/shaderapi.c
@@ -2199,12 +2199,15 @@ _mesa_GetProgramBinary(GLuint program, GLsizei bufSize, 
GLsizei *length,
   return;
}
 
-   *length = 0;
-   _mesa_error(ctx, GL_INVALID_OPERATION,
-   "glGetProgramBinary(driver supports zero binary formats)");
-
-   (void) binaryFormat;
-   (void) binary;
+   if (ctx->Const.NumProgramBinaryFormats == 0) {
+  *length = 0;
+  _mesa_error(ctx, GL_INVALID_OPERATION,
+  "glGetProgramBinary(driver supports zero binary formats)");
+   } else {
+  _mesa_get_program_binary(ctx, shProg, bufSize, length, binaryFormat,
+   binary);
+  assert(*length == 0 || *binaryFormat == GL_PROGRAM_BINARY_FORMAT_MESA);
+   }
 }
 
 void GLAPIENTRY

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Mesa (master): docs: Update GL_ARB_get_program_binary docs to support 1 format

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 4d81c8e43e2b235684e480da02eab2c647e6de6b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4d81c8e43e2b235684e480da02eab2c647e6de6b

Author: Jordan Justen <jordan.l.jus...@intel.com>
Date:   Mon Nov 20 13:42:33 2017 -0800

docs: Update GL_ARB_get_program_binary docs to support 1 format

Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>
Acked-by: Tapani Pälli <tapani.pa...@intel.com>

---

 docs/features.txt | 2 +-
 docs/relnotes/17.4.0.html | 1 +
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/docs/features.txt b/docs/features.txt
index 5d65d4fdf0..f5541d0342 100644
--- a/docs/features.txt
+++ b/docs/features.txt
@@ -139,7 +139,7 @@ GL 4.0, GLSL 4.00 --- all DONE: i965/gen7+, nvc0, r600, 
radeonsi
 GL 4.1, GLSL 4.10 --- all DONE: i965/gen7+, nvc0, r600, radeonsi
 
   GL_ARB_ES2_compatibility  DONE (freedreno, i965, 
nv50, llvmpipe, softpipe, swr)
-  GL_ARB_get_program_binary DONE (0 binary formats)
+  GL_ARB_get_program_binary DONE (0 or 1 binary 
formats)
   GL_ARB_separate_shader_objectsDONE (all drivers)
   GL_ARB_shader_precision   DONE (i965/gen7+, all 
drivers that support GLSL 4.10)
   GL_ARB_vertex_attrib_64bitDONE (i965/gen7+, 
llvmpipe, softpipe)
diff --git a/docs/relnotes/17.4.0.html b/docs/relnotes/17.4.0.html
index 8b32c4e6bd..5474e044d3 100644
--- a/docs/relnotes/17.4.0.html
+++ b/docs/relnotes/17.4.0.html
@@ -50,6 +50,7 @@ Note: some of the new features are only available with 
certain drivers.
 GL_ARB_shader_storage_buffer_object on r600/evergreen+
 GL_ARB_cull_distance on r600/evergreen+
 OpenGL 4.2 on r600/evergreen with hw fp64 support
+Support 1 binary format for GL_ARB_get_program_binary on i965
 
 
 Bug fixes

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Mesa (master): glsl: Split out shader program serialization

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: ebd9e789c40190862b28bbde8852c0b8b09df5ba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ebd9e789c40190862b28bbde8852c0b8b09df5ba

Author: Jordan Justen <jordan.l.jus...@intel.com>
Date:   Fri Oct 27 01:04:53 2017 -0700

glsl: Split out shader program serialization

This will allow us to use the program serialization to implement
ARB_get_program_binary.

Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>

---

 src/compiler/Makefile.sources  |2 +
 src/compiler/glsl/meson.build  |2 +
 src/compiler/glsl/serialize.cpp| 1238 
 src/compiler/glsl/serialize.h  |   50 ++
 src/compiler/glsl/shader_cache.cpp | 1185 +-
 src/compiler/shader_info.h |1 +
 6 files changed, 1297 insertions(+), 1181 deletions(-)

Diff:   
http://cgit.freedesktop.org/mesa/mesa/diff/?id=ebd9e789c40190862b28bbde8852c0b8b09df5ba
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Mesa (master): include: Add GL_MESA_program_binary_formats to GL/ GLES2 ext.h files

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 219628c1180069cd92e4d01a3e527d2df9f4851c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=219628c1180069cd92e4d01a3e527d2df9f4851c

Author: Jordan Justen 
Date:   Tue Nov  7 00:16:47 2017 -0800

include: Add GL_MESA_program_binary_formats to GL/GLES2 ext.h files

Thus was merged into the OpenGL Registry in version
667c5a253781834b40a6ae9eb19d05af4542cfe1.

Ref: https://github.com/KhronosGroup/OpenGL-Registry/pull/127
Signed-off-by: Jordan Justen 
Reviewed-by: Nicolai Hähnle 

---

 include/GL/glext.h | 5 +
 include/GLES2/gl2ext.h | 5 +
 2 files changed, 10 insertions(+)

diff --git a/include/GL/glext.h b/include/GL/glext.h
index 0ae78920e1..75fd1f6118 100644
--- a/include/GL/glext.h
+++ b/include/GL/glext.h
@@ -9212,6 +9212,11 @@ GLAPI void APIENTRY glGetPerfQueryInfoINTEL (GLuint 
queryId, GLuint queryNameLen
 #define GL_PACK_INVERT_MESA   0x8758
 #endif /* GL_MESA_pack_invert */
 
+#ifndef GL_MESA_program_binary_formats
+#define GL_MESA_program_binary_formats 1
+#define GL_PROGRAM_BINARY_FORMAT_MESA 0x875F
+#endif /* GL_MESA_program_binary_formats */
+
 #ifndef GL_MESA_resize_buffers
 #define GL_MESA_resize_buffers 1
 typedef void (APIENTRYP PFNGLRESIZEBUFFERSMESAPROC) (void);
diff --git a/include/GLES2/gl2ext.h b/include/GLES2/gl2ext.h
index cc90a6cf5d..a7d19a1fc8 100644
--- a/include/GLES2/gl2ext.h
+++ b/include/GLES2/gl2ext.h
@@ -2334,6 +2334,11 @@ GL_APICALL void GL_APIENTRY glGetPerfQueryInfoINTEL 
(GLuint queryId, GLuint quer
 #endif
 #endif /* GL_INTEL_performance_query */
 
+#ifndef GL_MESA_program_binary_formats
+#define GL_MESA_program_binary_formats 1
+#define GL_PROGRAM_BINARY_FORMAT_MESA 0x875F
+#endif /* GL_MESA_program_binary_formats */
+
 #ifndef GL_MESA_shader_integer_functions
 #define GL_MESA_shader_integer_functions 1
 #endif /* GL_MESA_shader_integer_functions */

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Mesa (master): main: Support 1 Mesa format with get for GL_PROGRAM_BINARY_FORMATS

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 64ad804e596075c06f5a1f2bdc0d45b5d2f2ead2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=64ad804e596075c06f5a1f2bdc0d45b5d2f2ead2

Author: Jordan Justen 
Date:   Tue Nov  7 00:21:33 2017 -0800

main: Support 1 Mesa format with get for GL_PROGRAM_BINARY_FORMATS

Mesa supports either 0 or 1 formats. If 1 format is supported, it is
GL_PROGRAM_BINARY_FORMAT_MESA as defined in the
GL_MESA_program_binary_formats extension spec.

Signed-off-by: Jordan Justen 
Reviewed-by: Nicolai Hähnle 

---

 src/mesa/main/get.c  | 9 +
 src/mesa/main/get_hash_params.py | 2 +-
 2 files changed, 10 insertions(+), 1 deletion(-)

diff --git a/src/mesa/main/get.c b/src/mesa/main/get.c
index ea8d932b18..c1b1a89ee0 100644
--- a/src/mesa/main/get.c
+++ b/src/mesa/main/get.c
@@ -1151,6 +1151,15 @@ find_custom_value(struct gl_context *ctx, const struct 
value_desc *d, union valu
  }
   }
   break;
+
+   /* GL_ARB_get_program_binary */
+   case GL_PROGRAM_BINARY_FORMATS:
+  assert(ctx->Const.NumProgramBinaryFormats <= 1);
+  v->value_int_n.n = MIN2(ctx->Const.NumProgramBinaryFormats, 1);
+  if (ctx->Const.NumProgramBinaryFormats > 0) {
+ v->value_int_n.ints[0] = GL_PROGRAM_BINARY_FORMAT_MESA;
+  }
+  break;
}
 }
 
diff --git a/src/mesa/main/get_hash_params.py b/src/mesa/main/get_hash_params.py
index 6d99a029ed..eac250a1ec 100644
--- a/src/mesa/main/get_hash_params.py
+++ b/src/mesa/main/get_hash_params.py
@@ -325,7 +325,7 @@ descriptor=[
 
 # GL_ARB_get_program_binary / GL_OES_get_program_binary
   [ "NUM_PROGRAM_BINARY_FORMATS", 
"CONTEXT_UINT(Const.NumProgramBinaryFormats), NO_EXTRA" ],
-  [ "PROGRAM_BINARY_FORMATS", "LOC_CUSTOM, TYPE_INVALID, 0, NO_EXTRA" ],
+  [ "PROGRAM_BINARY_FORMATS", "LOC_CUSTOM, TYPE_INT_N, 0, NO_EXTRA" ],
 
 # GL_INTEL_performance_query
   [ "PERFQUERY_QUERY_NAME_LENGTH_MAX_INTEL", 
"CONST(MAX_PERFQUERY_QUERY_NAME_LENGTH), extra_INTEL_performance_query" ],

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Mesa (master): main: add binary support to ProgramBinary

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 50c09a648f6d389cdc1657a0ccf54cf263aa8aa6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=50c09a648f6d389cdc1657a0ccf54cf263aa8aa6

Author: Jordan Justen <jordan.l.jus...@intel.com>
Date:   Sat Nov  4 16:47:54 2017 -0700

main: add binary support to ProgramBinary

V2: call generic mesa_program_binary() helper rather than driver
function directly to allow greater code sharing.

Signed-off-by: Timothy Arceri <tarc...@itsqueeze.com>
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com> (v1)
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> (v1)
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>

---

 src/mesa/main/shaderapi.c | 36 +++-
 1 file changed, 19 insertions(+), 17 deletions(-)

diff --git a/src/mesa/main/shaderapi.c b/src/mesa/main/shaderapi.c
index b728b320ac..51031e12ec 100644
--- a/src/mesa/main/shaderapi.c
+++ b/src/mesa/main/shaderapi.c
@@ -2221,9 +2221,6 @@ _mesa_ProgramBinary(GLuint program, GLenum binaryFormat,
if (!shProg)
   return;
 
-   (void) binaryFormat;
-   (void) binary;
-
/* Section 2.3.1 (Errors) of the OpenGL 4.5 spec says:
 *
 * "If a negative number is provided where an argument of type sizei or
@@ -2234,20 +2231,25 @@ _mesa_ProgramBinary(GLuint program, GLenum binaryFormat,
   return;
}
 
-   /* The ARB_get_program_binary spec says:
-*
-* " and  must be those returned by a previous
-* call to GetProgramBinary, and  must be the length of the
-* program binary as returned by GetProgramBinary or GetProgramiv with
-*  PROGRAM_BINARY_LENGTH. Loading the program binary will fail,
-* setting the LINK_STATUS of  to FALSE, if these conditions
-* are not met."
-*
-* Since any value of binaryFormat passed "is not one of those specified as
-* allowable for [this] command, an INVALID_ENUM error is generated."
-*/
-   shProg->data->LinkStatus = linking_failure;
-   _mesa_error(ctx, GL_INVALID_ENUM, "glProgramBinary");
+   if (ctx->Const.NumProgramBinaryFormats == 0 ||
+   binaryFormat != GL_PROGRAM_BINARY_FORMAT_MESA) {
+  /* The ARB_get_program_binary spec says:
+   *
+   * " and  must be those returned by a previous
+   * call to GetProgramBinary, and  must be the length of the
+   * program binary as returned by GetProgramBinary or GetProgramiv 
with
+   *  PROGRAM_BINARY_LENGTH. Loading the program binary will 
fail,
+   * setting the LINK_STATUS of  to FALSE, if these conditions
+   * are not met."
+   *
+   * Since any value of binaryFormat passed "is not one of those specified 
as
+   * allowable for [this] command, an INVALID_ENUM error is generated."
+   */
+  shProg->data->LinkStatus = linking_failure;
+  _mesa_error(ctx, GL_INVALID_ENUM, "glProgramBinary");
+   } else {
+  _mesa_program_binary(ctx, shProg, binaryFormat, binary, length);
+   }
 }
 
 

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Mesa (master): mesa: add driver callbacks for serialising ProgramBinary blobs

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 90d4abdd872b62943b33d62c9368fe7855b1c4fc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=90d4abdd872b62943b33d62c9368fe7855b1c4fc

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Nov 28 14:27:51 2017 +1100

mesa: add driver callbacks for serialising ProgramBinary blobs

Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>

---

 src/mesa/main/dd.h | 17 +
 1 file changed, 17 insertions(+)

diff --git a/src/mesa/main/dd.h b/src/mesa/main/dd.h
index da03b2e8b9..4e4d2a6f37 100644
--- a/src/mesa/main/dd.h
+++ b/src/mesa/main/dd.h
@@ -1126,6 +1126,23 @@ struct dd_function_table {
 GLuint64 size,
 int fd);
/*@}*/
+
+   /**
+* \name GL_ARB_get_program_binary
+*/
+   /*@{*/
+   /**
+* Calls to retrieve/store a binary serialized copy of the current program.
+*/
+   void (*GetProgramBinaryDriverSHA1)(struct gl_context *ctx, uint8_t *sha1);
+
+   void (*ProgramBinarySerializeDriverBlob)(struct gl_context *ctx,
+struct gl_program *prog);
+
+   void (*ProgramBinaryDeserializeDriverBlob)(struct gl_context *ctx,
+  struct gl_shader_program *shProg,
+  struct gl_program *prog);
+   /*@}*/
 };
 
 

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Mesa (master): mesa: add GL_PROGRAM_BINARY_FORMAT_MESA enum

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 0c484878933dcf79be5c8592d89d72773643832b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0c484878933dcf79be5c8592d89d72773643832b

Author: Jordan Justen <jordan.l.jus...@intel.com>
Date:   Tue Nov 28 11:15:07 2017 +1100

mesa: add GL_PROGRAM_BINARY_FORMAT_MESA enum

Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Timothy Arceri <tarc...@itsqueeze.com>

---

 docs/specs/enums.txt   | 3 +++
 src/mapi/glapi/registry/gl.xml | 7 ++-
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/docs/specs/enums.txt b/docs/specs/enums.txt
index eb4aa396c5..bf3ca9c176 100644
--- a/docs/specs/enums.txt
+++ b/docs/specs/enums.txt
@@ -63,6 +63,9 @@ GL_MESAX_texture_stack:
GL_TEXTURE_1D_STACK_BINDING_MESAX0x875D
GL_TEXTURE_2D_STACK_BINDING_MESAX0x875E
 
+GL_MESA_program_binary_formats:
+GL_PROGRAM_BINARY_FORMAT_MESA   0x875F
+
 GL_MESA_tile_raster_order
GL_TILE_RASTER_ORDER_FIXED_MESA 0x8BB8
GL_TILE_RASTER_ORDER_INCREASING_X_MESA  0x8BB9
diff --git a/src/mapi/glapi/registry/gl.xml b/src/mapi/glapi/registry/gl.xml
index cbabe11b39..833478aa51 100644
--- a/src/mapi/glapi/registry/gl.xml
+++ b/src/mapi/glapi/registry/gl.xml
@@ -5505,7 +5505,7 @@ typedef unsigned int GLhandleARB;
 
 
 
-
+
 
 
 
@@ -44361,6 +44361,11 @@ typedef unsigned int GLhandleARB;
 
 
 
+
+
+
+
+
 
 
 

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Mesa (master): main: Allow non-zero NUM_PROGRAM_BINARY_FORMATS

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: fb077d603bcc46ad915e9863ebf53b75f4662f16
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb077d603bcc46ad915e9863ebf53b75f4662f16

Author: Jordan Justen 
Date:   Sat Nov  4 16:39:08 2017 -0700

main: Allow non-zero NUM_PROGRAM_BINARY_FORMATS

Signed-off-by: Jordan Justen 
Reviewed-by: Nicolai Hähnle 

---

 src/mesa/main/get_hash_params.py | 2 +-
 src/mesa/main/mtypes.h   | 3 +++
 2 files changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/mesa/main/get_hash_params.py b/src/mesa/main/get_hash_params.py
index 20ef6e4977..6d99a029ed 100644
--- a/src/mesa/main/get_hash_params.py
+++ b/src/mesa/main/get_hash_params.py
@@ -324,7 +324,7 @@ descriptor=[
   [ "SHADER_BINARY_FORMATS", "LOC_CUSTOM, TYPE_INVALID, 0, 
extra_ARB_ES2_compatibility_api_es2" ],
 
 # GL_ARB_get_program_binary / GL_OES_get_program_binary
-  [ "NUM_PROGRAM_BINARY_FORMATS", "CONST(0), NO_EXTRA" ],
+  [ "NUM_PROGRAM_BINARY_FORMATS", 
"CONTEXT_UINT(Const.NumProgramBinaryFormats), NO_EXTRA" ],
   [ "PROGRAM_BINARY_FORMATS", "LOC_CUSTOM, TYPE_INVALID, 0, NO_EXTRA" ],
 
 # GL_INTEL_performance_query
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 40f70b067e..d7e9f148f3 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -4022,6 +4022,9 @@ struct gl_constants
 
/** When drivers are OK with mapped buffers during draw and other calls. */
bool AllowMappedBuffersDuringExecution;
+
+   /** GL_ARB_get_program_binary */
+   GLuint NumProgramBinaryFormats;
 };
 
 

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Mesa (master): mesa: Add Mesa ARB_get_program_binary helper functions

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: c20fd744fef1ffb938f74dbafbe375c863fecc65
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c20fd744fef1ffb938f74dbafbe375c863fecc65

Author: Jordan Justen <jordan.l.jus...@intel.com>
Date:   Sat Nov  4 16:52:14 2017 -0700

mesa: Add Mesa ARB_get_program_binary helper functions

V2 (Timothy Arceri):
 - add extra code comment
 - stop passing around void *binary and just pass
   program_binary_header *hdr instead.
 - move to src/mesa/main rather than src/util

V3 (Timothy Arceri):
 - Move more code out of the backend and into the common
   helpers.

Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>

---

 src/mesa/Makefile.sources  |   2 +
 src/mesa/main/program_binary.c | 291 +
 src/mesa/main/program_binary.h |  56 
 src/mesa/meson.build   |   2 +
 4 files changed, 351 insertions(+)

diff --git a/src/mesa/Makefile.sources b/src/mesa/Makefile.sources
index 6da1e3fef9..d8b1eb1f99 100644
--- a/src/mesa/Makefile.sources
+++ b/src/mesa/Makefile.sources
@@ -173,6 +173,8 @@ MAIN_FILES = \
main/points.h \
main/polygon.c \
main/polygon.h \
+   main/program_binary.c \
+   main/program_binary.h \
main/program_resource.c \
main/program_resource.h \
main/querymatrix.c \
diff --git a/src/mesa/main/program_binary.c b/src/mesa/main/program_binary.c
new file mode 100644
index 00..2786487362
--- /dev/null
+++ b/src/mesa/main/program_binary.c
@@ -0,0 +1,291 @@
+/*
+ * Mesa 3-D graphics library
+ *
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included
+ * in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/**
+ * \file program_binary.c
+ *
+ * Helper functions for serializing a binary program.
+ */
+
+
+#include "compiler/blob.h"
+#include "compiler/glsl/serialize.h"
+#include "main/errors.h"
+#include "main/mtypes.h"
+#include "util/crc32.h"
+#include "program_binary.h"
+#include "program/prog_parameter.h"
+
+/**
+ * Mesa supports one binary format, but it must differentiate between formats
+ * produced by different drivers and different Mesa versions.
+ *
+ * Mesa uses a uint32_t value to specify an internal format. The only format
+ * defined has one uint32_t value of 0, followed by 20 bytes specifying a sha1
+ * that uniquely identifies the Mesa driver type and version.
+ */
+
+struct program_binary_header {
+   /* If internal_format is 0, it must be followed by the 20 byte sha1 that
+* identifies the Mesa driver and version supported. If we want to support
+* something besides a sha1, then a new internal_format value can be added.
+*/
+   uint32_t internal_format;
+   uint8_t sha1[20];
+   /* Fields following sha1 can be changed since the sha1 will guarantee that
+* the binary only works with the same Mesa version.
+*/
+   uint32_t size;
+   uint32_t crc32;
+};
+
+/**
+ * Returns the header size needed for a binary
+ */
+static unsigned
+get_program_binary_header_size(void)
+{
+   return sizeof(struct program_binary_header);
+}
+
+static bool
+write_program_binary(const void *payload, unsigned payload_size,
+ const void *sha1, void *binary, unsigned binary_size,
+ GLenum *binary_format)
+{
+   struct program_binary_header *hdr = binary;
+
+   if (binary_size < sizeof(*hdr))
+  return false;
+
+   /* binary_size is the size of the buffer provided by the application.
+* Make sure our program (payload) will fit in the buffer.
+*/
+   if (payload_size > binary_size - sizeof(*hdr))
+  return false;
+
+   hdr->internal_format = 0;
+   memcpy(hdr->sha1, sha1, sizeof(hdr->sha1));
+   memcpy(hdr + 1, payload, payload_size);
+   hdr->size = payload_size;
+
+   hdr->crc32 = util_hash_crc32(hdr +

Mesa (master): glsl: get correct member type when processing xfb ifc arrays

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 9d53b251d21f9291abaa3a28a41d06ce8c91
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d53b251d21f9291abaa3a28a41d06ce8c91

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Thu Dec  7 10:16:55 2017 +1100

glsl: get correct member type when processing xfb ifc arrays

This fixes a crash in:

KHR-GL45.enhanced_layouts.xfb_block_stride

Fixes: 0822517936d4 "glsl: add helper to process xfb qualifiers during linking"
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>

---

 src/compiler/glsl/link_varyings.cpp | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/compiler/glsl/link_varyings.cpp 
b/src/compiler/glsl/link_varyings.cpp
index 0f53cd4aa9..2be81b3f93 100644
--- a/src/compiler/glsl/link_varyings.cpp
+++ b/src/compiler/glsl/link_varyings.cpp
@@ -165,10 +165,12 @@ process_xfb_layout_qualifiers(void *mem_ctx, const 
gl_linked_shader *sh,
 
  if (var->data.from_named_ifc_block) {
 type = var->get_interface_type();
+
 /* Find the member type before it was altered by lowering */
+const glsl_type *type_wa = type->without_array();
 member_type =
-   type->fields.structure[type->field_index(var->name)].type;
-name = ralloc_strdup(NULL, type->without_array()->name);
+   type_wa->fields.structure[type_wa->field_index(var->name)].type;
+name = ralloc_strdup(NULL, type_wa->name);
  } else {
 type = var->type;
 member_type = NULL;

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Mesa (master): radeonsi: pass llvm type directly to buffer_load()

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: e9e6476ae5a53665faa0806c14458de957309205
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9e6476ae5a53665faa0806c14458de957309205

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Thu Nov 23 11:29:59 2017 +1100

radeonsi: pass llvm type directly to buffer_load()

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader.c | 15 +++
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index a94c2af870..6a1293b99d 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1041,14 +1041,13 @@ static LLVMValueRef get_tcs_tes_buffer_address_from_reg(
 }
 
 static LLVMValueRef buffer_load(struct lp_build_tgsi_context *bld_base,
-enum tgsi_opcode_type type, unsigned swizzle,
+LLVMTypeRef type, unsigned swizzle,
 LLVMValueRef buffer, LLVMValueRef offset,
 LLVMValueRef base, bool can_speculate)
 {
struct si_shader_context *ctx = si_shader_context(bld_base);
LLVMValueRef value, value2;
-   LLVMTypeRef llvm_type = tgsi2llvmtype(bld_base, type);
-   LLVMTypeRef vec_type = LLVMVectorType(llvm_type, 4);
+   LLVMTypeRef vec_type = LLVMVectorType(type, 4);
 
if (swizzle == ~0) {
value = ac_build_buffer_load(>ac, buffer, 4, NULL, base, 
offset,
@@ -1057,7 +1056,7 @@ static LLVMValueRef buffer_load(struct 
lp_build_tgsi_context *bld_base,
return LLVMBuildBitCast(ctx->ac.builder, value, vec_type, "");
}
 
-   if (!tgsi_type_is_64bit(type)) {
+   if (!llvm_type_is_64bit(ctx, type)) {
value = ac_build_buffer_load(>ac, buffer, 4, NULL, base, 
offset,
 0, 1, 0, can_speculate, false);
 
@@ -1072,8 +1071,7 @@ static LLVMValueRef buffer_load(struct 
lp_build_tgsi_context *bld_base,
value2 = ac_build_buffer_load(>ac, buffer, 1, NULL, base, offset,
   swizzle * 4 + 4, 1, 0, can_speculate, false);
 
-   return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
-   value, value2);
+   return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
 }
 
 /**
@@ -1206,7 +1204,8 @@ static LLVMValueRef fetch_input_tes(
base = LLVMGetParam(ctx->main_fn, ctx->param_tcs_offchip_offset);
addr = get_tcs_tes_buffer_address_from_reg(ctx, NULL, reg);
 
-   return buffer_load(bld_base, type, swizzle, buffer, base, addr, true);
+   return buffer_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle,
+  buffer, base, addr, true);
 }
 
 static void store_output_tcs(struct lp_build_tgsi_context *bld_base,
@@ -1788,7 +1787,7 @@ void si_load_system_value(struct si_shader_context *ctx,
addr = get_tcs_tes_buffer_address(ctx, get_rel_patch_id(ctx), 
NULL,
  LLVMConstInt(ctx->i32, param, 0));
 
-   value = buffer_load(>bld_base, TGSI_TYPE_FLOAT,
+   value = buffer_load(>bld_base, ctx->f32,
~0, buffer, base, addr, true);
 
break;

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Mesa (master): nir: allow builin arrays to be lowered

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: d99c7e0ff17208f82f254ef331e60a4005f4f6fa
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d99c7e0ff17208f82f254ef331e60a4005f4f6fa

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Nov 15 14:30:22 2017 +1100

nir: allow builin arrays to be lowered

Galliums nir drivers expect this to be done.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/compiler/nir/nir_lower_io_arrays_to_elements.c | 17 ++---
 1 file changed, 10 insertions(+), 7 deletions(-)

diff --git a/src/compiler/nir/nir_lower_io_arrays_to_elements.c 
b/src/compiler/nir/nir_lower_io_arrays_to_elements.c
index c785e22b0e..dca5719f11 100644
--- a/src/compiler/nir/nir_lower_io_arrays_to_elements.c
+++ b/src/compiler/nir/nir_lower_io_arrays_to_elements.c
@@ -264,7 +264,8 @@ create_indirects_mask(nir_shader *shader, uint64_t 
*indirects,
 static void
 lower_io_arrays_to_elements(nir_shader *shader, nir_variable_mode mask,
 uint64_t *indirects, uint64_t *patch_indirects,
-struct hash_table *varyings)
+struct hash_table *varyings,
+bool after_cross_stage_opts)
 {
nir_foreach_function(function, shader) {
   if (function->impl) {
@@ -313,14 +314,16 @@ lower_io_arrays_to_elements(nir_shader *shader, 
nir_variable_mode mask,
glsl_type_is_struct(glsl_without_array(type)))
   continue;
 
-   if (var->data.location < VARYING_SLOT_VAR0 &&
+   /* Skip builtins */
+   if (!after_cross_stage_opts &&
+   var->data.location < VARYING_SLOT_VAR0 &&
var->data.location >= 0)
   continue;
 
/* Don't bother splitting if we can't opt away any unused
 * elements.
 */
-   if (var->data.always_active_io)
+   if (!after_cross_stage_opts && var->data.always_active_io)
   continue;
 
switch (intr->intrinsic) {
@@ -355,10 +358,10 @@ nir_lower_io_arrays_to_elements_no_indirects(nir_shader 
*shader)
uint64_t indirects[4] = {0}, patch_indirects[4] = {0};
 
lower_io_arrays_to_elements(shader, nir_var_shader_out, indirects,
-   patch_indirects, split_outputs);
+   patch_indirects, split_outputs, true);
 
lower_io_arrays_to_elements(shader, nir_var_shader_in, indirects,
-   patch_indirects, split_inputs);
+   patch_indirects, split_inputs, true);
 
/* Remove old input from the shaders inputs list */
struct hash_entry *entry;
@@ -398,10 +401,10 @@ nir_lower_io_arrays_to_elements(nir_shader *producer, 
nir_shader *consumer)
  nir_var_shader_in);
 
lower_io_arrays_to_elements(producer, nir_var_shader_out, indirects,
-   patch_indirects, split_outputs);
+   patch_indirects, split_outputs, false);
 
lower_io_arrays_to_elements(consumer, nir_var_shader_in, indirects,
-   patch_indirects, split_inputs);
+   patch_indirects, split_inputs, false);
 
/* Remove old input from the shaders inputs list */
struct hash_entry *entry;

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Mesa (master): st/glsl_to_nir/radeonsi: enable gs support for nir backend

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 27888977c1f1104d52caac8f023eeeaad7fabbec
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=27888977c1f1104d52caac8f023eeeaad7fabbec

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Fri Nov 10 21:33:37 2017 +1100

st/glsl_to_nir/radeonsi: enable gs support for nir backend

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/gallium/drivers/radeonsi/si_get.c|  3 +-
 src/gallium/drivers/radeonsi/si_shader_nir.c | 61 +++-
 src/mesa/state_tracker/st_glsl_to_nir.cpp| 12 ++
 3 files changed, 47 insertions(+), 29 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_get.c 
b/src/gallium/drivers/radeonsi/si_get.c
index 7646ea8255..1c84a252ef 100644
--- a/src/gallium/drivers/radeonsi/si_get.c
+++ b/src/gallium/drivers/radeonsi/si_get.c
@@ -227,7 +227,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum 
pipe_cap param)
 
case PIPE_CAP_GLSL_FEATURE_LEVEL:
if (sscreen->debug_flags & DBG(NIR))
-   return 140; /* no geometry and tessellation shaders yet 
*/
+   return 150; /* no tessellation shaders yet */
if (si_have_tgsi_compute(sscreen))
return 450;
return 420;
@@ -452,6 +452,7 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
case PIPE_SHADER_CAP_PREFERRED_IR:
if (sscreen->debug_flags & DBG(NIR) &&
(shader == PIPE_SHADER_VERTEX ||
+shader == PIPE_SHADER_GEOMETRY ||
 shader == PIPE_SHADER_FRAGMENT))
return PIPE_SHADER_IR_NIR;
return PIPE_SHADER_IR_TGSI;
diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index 1b502b33e9..4138e04dcb 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -130,6 +130,7 @@ void si_nir_scan_shader(const struct nir_shader *nir,
unsigned i;
 
assert(nir->info.stage == MESA_SHADER_VERTEX ||
+  nir->info.stage == MESA_SHADER_GEOMETRY ||
   nir->info.stage == MESA_SHADER_FRAGMENT);
 
info->processor = pipe_shader_type_from_mesa(nir->info.stage);
@@ -151,8 +152,6 @@ void si_nir_scan_shader(const struct nir_shader *nir,
unsigned attrib_count = 
glsl_count_attribute_slots(variable->type,
   
nir->info.stage == MESA_SHADER_VERTEX);
 
-   assert(attrib_count == 1 && "not implemented");
-
/* Vertex shader inputs don't have semantics. The state
 * tracker has already mapped them to attributes via
 * variable->data.driver_location.
@@ -160,6 +159,9 @@ void si_nir_scan_shader(const struct nir_shader *nir,
if (nir->info.stage == MESA_SHADER_VERTEX)
continue;
 
+   assert(nir->info.stage != MESA_SHADER_FRAGMENT ||
+  (attrib_count == 1 && "not implemented"));
+
/* Fragment shader position is a system value. */
if (nir->info.stage == MESA_SHADER_FRAGMENT &&
variable->data.location == VARYING_SLOT_POS) {
@@ -559,33 +561,36 @@ bool si_nir_build_llvm(struct si_shader_context *ctx, 
struct nir_shader *nir)
 {
struct tgsi_shader_info *info = >shader->selector->info;
 
-   uint64_t processed_inputs = 0;
-   nir_foreach_variable(variable, >inputs) {
-   unsigned attrib_count = 
glsl_count_attribute_slots(variable->type,
-  
nir->info.stage == MESA_SHADER_VERTEX);
-   unsigned input_idx = variable->data.driver_location;
-
-   assert(attrib_count == 1);
-
-   LLVMValueRef data[4];
-   unsigned loc = variable->data.location;
-
-   /* Packed components share the same location so skip
-* them if we have already processed the location.
-*/
-   if (processed_inputs & ((uint64_t)1 << loc))
-   continue;
-
-   if (nir->info.stage == MESA_SHADER_VERTEX)
-   declare_nir_input_vs(ctx, variable, data);
-   else if (nir->info.stage == MESA_SHADER_FRAGMENT)
-   declare_nir_input_fs(ctx, variable, input_idx / 4, 
data);
-
-   for (unsigned chan = 0; chan < 4; chan++) {
-   ctx->inputs[input_idx + chan] =
-   LLVMBuildBitCast(ctx->ac.builder, data[chan], 
ctx->ac.i32, "");
+   i

Mesa (master): st/glsl_to_nir: add gs support to st_nir_assign_var_locations()

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 164b6d4aeb3a807b6ea6ce96543aad0ff65cf92d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=164b6d4aeb3a807b6ea6ce96543aad0ff65cf92d

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Nov 22 17:37:32 2017 +1100

st/glsl_to_nir: add gs support to st_nir_assign_var_locations()

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/mesa/state_tracker/st_glsl_to_nir.cpp | 23 +--
 1 file changed, 17 insertions(+), 6 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index f76e453d49..e1f47d88dd 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -122,26 +122,34 @@ st_nir_assign_vs_in_locations(struct gl_program *prog, 
nir_shader *nir)
 }
 
 static void
-st_nir_assign_var_locations(struct exec_list *var_list, unsigned *size)
+st_nir_assign_var_locations(struct exec_list *var_list, unsigned *size,
+gl_shader_stage stage)
 {
unsigned location = 0;
unsigned assigned_locations[VARYING_SLOT_MAX];
uint64_t processed_locs = 0;
 
nir_foreach_variable(var, var_list) {
+
+  const struct glsl_type *type = var->type;
+  if (nir_is_per_vertex_io(var, stage)) {
+ assert(glsl_type_is_array(type));
+ type = glsl_get_array_element(type);
+  }
+
   /* Because component packing allows varyings to share the same location
* we may have already have processed this location.
*/
   if (var->data.location >= VARYING_SLOT_VAR0 &&
   processed_locs & ((uint64_t)1 << var->data.location)) {
  var->data.driver_location = assigned_locations[var->data.location];
- *size += type_size(var->type);
+ *size += type_size(type);
  continue;
   }
 
   assigned_locations[var->data.location] = location;
   var->data.driver_location = location;
-  location += type_size(var->type);
+  location += type_size(type);
 
   processed_locs |= ((uint64_t)1 << var->data.location);
}
@@ -644,15 +652,18 @@ st_finalize_nir(struct st_context *st, struct gl_program 
*prog,
 
   sort_varyings(>outputs);
   st_nir_assign_var_locations(>outputs,
-  >num_outputs);
+  >num_outputs,
+  nir->info.stage);
   st_nir_fixup_varying_slots(st, >outputs);
} else if (nir->info.stage == MESA_SHADER_FRAGMENT) {
   sort_varyings(>inputs);
   st_nir_assign_var_locations(>inputs,
-  >num_inputs);
+  >num_inputs,
+  nir->info.stage);
   st_nir_fixup_varying_slots(st, >inputs);
   st_nir_assign_var_locations(>outputs,
-  >num_outputs);
+  >num_outputs,
+  nir->info.stage);
} else if (nir->info.stage == MESA_SHADER_COMPUTE) {
/* TODO? */
} else {

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Mesa (master): radeonsi: add nir support for ls epilogue

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 204f547852896bf6f4e5b41ce9f86597a3bcc3d0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=204f547852896bf6f4e5b41ce9f86597a3bcc3d0

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Thu Nov  2 15:02:55 2017 +1100

radeonsi: add nir support for ls epilogue

v2: make use of existing si_tgsi_emit_epilogue()

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader.c | 29 ++---
 1 file changed, 14 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index d3e5e9734e..81b6c38678 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1114,13 +1114,11 @@ static LLVMValueRef lds_load(struct 
lp_build_tgsi_context *bld_base,
  * \param dw_addr  address in dwords
  * \param valuevalue to store
  */
-static void lds_store(struct lp_build_tgsi_context *bld_base,
+static void lds_store(struct si_shader_context *ctx,
  unsigned dw_offset_imm, LLVMValueRef dw_addr,
  LLVMValueRef value)
 {
-   struct si_shader_context *ctx = si_shader_context(bld_base);
-
-   dw_addr = lp_build_add(_base->uint_bld, dw_addr,
+   dw_addr = lp_build_add(>bld_base.uint_bld, dw_addr,
LLVMConstInt(ctx->i32, dw_offset_imm, 0));
 
ac_lds_store(>ac, dw_addr, value);
@@ -1266,7 +1264,7 @@ static void store_output_tcs(struct lp_build_tgsi_context 
*bld_base,
 
/* Skip LDS stores if there is no LDS read of this output. */
if (!skip_lds_store)
-   lds_store(bld_base, chan_index, dw_addr, value);
+   lds_store(ctx, chan_index, dw_addr, value);
 
value = ac_to_integer(>ac, value);
values[chan_index] = value;
@@ -3129,9 +3127,11 @@ static void si_set_es_return_value_for_gs(struct 
si_shader_context *ctx)
ctx->return_value = ret;
 }
 
-static void si_llvm_emit_ls_epilogue(struct lp_build_tgsi_context *bld_base)
+static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
+unsigned max_outputs,
+LLVMValueRef *addrs)
 {
-   struct si_shader_context *ctx = si_shader_context(bld_base);
+   struct si_shader_context *ctx = si_shader_context_from_abi(abi);
struct si_shader *shader = ctx->shader;
struct tgsi_shader_info *info = >selector->info;
unsigned i, chan;
@@ -3144,7 +3144,6 @@ static void si_llvm_emit_ls_epilogue(struct 
lp_build_tgsi_context *bld_base)
/* Write outputs to LDS. The next shader (TCS aka HS) will read
 * its inputs from it. */
for (i = 0; i < info->num_outputs; i++) {
-   LLVMValueRef *out_ptr = ctx->outputs[i];
unsigned name = info->output_semantic_name[i];
unsigned index = info->output_semantic_index[i];
 
@@ -3175,8 +3174,8 @@ static void si_llvm_emit_ls_epilogue(struct 
lp_build_tgsi_context *bld_base)
if (!(info->output_usagemask[i] & (1 << chan)))
continue;
 
-   lds_store(bld_base, chan, dw_addr,
- LLVMBuildLoad(ctx->ac.builder, out_ptr[chan], 
""));
+   lds_store(ctx, chan, dw_addr,
+ LLVMBuildLoad(ctx->ac.builder, addrs[4 * i + 
chan], ""));
}
}
 
@@ -3223,7 +3222,7 @@ static void si_llvm_emit_es_epilogue(struct 
lp_build_tgsi_context *bld_base)
 
/* GFX9 has the ESGS ring in LDS. */
if (ctx->screen->info.chip_class >= GFX9) {
-   lds_store(bld_base, param * 4 + chan, lds_base, 
out_val);
+   lds_store(ctx, param * 4 + chan, lds_base, 
out_val);
continue;
}
 
@@ -4432,7 +4431,6 @@ static void create_function(struct si_shader_context *ctx)
assert(!shader->selector->nir);
ctx->param_es2gs_offset = add_arg(, ARG_SGPR, 
ctx->i32);
} else if (shader->key.as_ls) {
-   assert(!shader->selector->nir);
/* no extra parameters */
} else {
if (shader->is_gs_copy_shader) {
@@ -5735,9 +5733,10 @@ static bool si_compile_tgsi_main(struct 
si_shader_context *ctx,
switch (ctx->type) {
case PIPE_SHADER_VERTEX:
ctx->load_input = declare_input_vs;
-   if (shader->key.as_ls)
-   

Mesa (master): radeonsi: add llvm_type_is_64bit() helper

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 650126f3e02ede482fbb11b9dc069eae200378ae
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=650126f3e02ede482fbb11b9dc069eae200378ae

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Nov  7 21:41:27 2017 +1100

radeonsi: add llvm_type_is_64bit() helper

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index c3b5f58cd2..58cba2c5a4 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -103,6 +103,15 @@ enum {
LOCAL_ADDR_SPACE = 3,
 };
 
+static bool llvm_type_is_64bit(struct si_shader_context *ctx,
+  LLVMTypeRef type)
+{
+   if (type == ctx->ac.i64 || type == ctx->ac.f64)
+   return true;
+
+   return false;
+}
+
 static bool is_merged_shader(struct si_shader *shader)
 {
if (shader->selector->screen->info.chip_class <= VI)

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Mesa (master): radeonsi: add nir support for gs epilogue

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: e51ecbe980b56a312b43afd668b3990c8799a348
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e51ecbe980b56a312b43afd668b3990c8799a348

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Thu Nov  9 13:34:37 2017 +1100

radeonsi: add nir support for gs epilogue

v2: add emit_gs_epilogue() helper function to reduce duplication.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader.c | 25 +
 1 file changed, 21 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index aa9af1541d..e8b4ec7b98 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -3247,10 +3247,8 @@ static LLVMValueRef si_get_gs_wave_id(struct 
si_shader_context *ctx)
return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
 }
 
-static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
+static void emit_gs_epilogue(struct si_shader_context *ctx)
 {
-   struct si_shader_context *ctx = si_shader_context(bld_base);
-
ac_build_sendmsg(>ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
 si_get_gs_wave_id(ctx));
 
@@ -3258,6 +3256,24 @@ static void si_llvm_emit_gs_epilogue(struct 
lp_build_tgsi_context *bld_base)
lp_build_endif(>merged_wrap_if_state);
 }
 
+static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
+unsigned max_outputs,
+LLVMValueRef *addrs)
+{
+   struct si_shader_context *ctx = si_shader_context_from_abi(abi);
+   struct tgsi_shader_info UNUSED *info = >shader->selector->info;
+
+   assert(info->num_outputs <= max_outputs);
+
+   emit_gs_epilogue(ctx);
+}
+
+static void si_tgsi_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
+{
+   struct si_shader_context *ctx = si_shader_context(bld_base);
+   emit_gs_epilogue(ctx);
+}
+
 static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
 unsigned max_outputs,
 LLVMValueRef *addrs)
@@ -5758,7 +5774,8 @@ static bool si_compile_tgsi_main(struct si_shader_context 
*ctx,
case PIPE_SHADER_GEOMETRY:
bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;
ctx->abi.emit_vertex = si_llvm_emit_vertex;
-   bld_base->emit_epilogue = si_llvm_emit_gs_epilogue;
+   ctx->abi.emit_outputs = si_llvm_emit_gs_epilogue;
+   bld_base->emit_epilogue = si_tgsi_emit_gs_epilogue;
break;
case PIPE_SHADER_FRAGMENT:
ctx->load_input = declare_input_fs;

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Mesa (master): radeonsi: pass llvm type to si_llvm_emit_fetch_64bit()

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 7ef1e42c14fb23592e8e003f7a80db9a43cb9bc9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ef1e42c14fb23592e8e003f7a80db9a43cb9bc9

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Nov  7 21:27:18 2017 +1100

radeonsi: pass llvm type to si_llvm_emit_fetch_64bit()

v2: use LLVMBuildBitCast() directly

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader.c| 11 +++
 src/gallium/drivers/radeonsi/si_shader_internal.h   |  2 +-
 src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c | 17 ++---
 3 files changed, 18 insertions(+), 12 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index e8b4ec7b98..c3b5f58cd2 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1063,7 +1063,8 @@ static LLVMValueRef buffer_load(struct 
lp_build_tgsi_context *bld_base,
value2 = ac_build_buffer_load(>ac, buffer, 1, NULL, base, offset,
   swizzle * 4 + 4, 1, 0, can_speculate, false);
 
-   return si_llvm_emit_fetch_64bit(bld_base, type, value, value2);
+   return si_llvm_emit_fetch_64bit(bld_base, tgsi2llvmtype(bld_base, type),
+   value, value2);
 }
 
 /**
@@ -1096,7 +1097,8 @@ static LLVMValueRef lds_load(struct lp_build_tgsi_context 
*bld_base,
 
lo = lds_load(bld_base, TGSI_TYPE_UNSIGNED, swizzle, dw_addr);
hi = lds_load(bld_base, TGSI_TYPE_UNSIGNED, swizzle + 1, 
dw_addr);
-   return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
+   return si_llvm_emit_fetch_64bit(bld_base, 
tgsi2llvmtype(bld_base, type),
+   lo, hi);
}
 
dw_addr = lp_build_add(_base->uint_bld, dw_addr,
@@ -1375,7 +1377,7 @@ static LLVMValueRef fetch_input_gs(
value2 = ac_build_buffer_load(>ac, ctx->esgs_ring, 1,
  ctx->i32_0, vtx_offset, soffset,
  0, 1, 0, true, false);
-   return si_llvm_emit_fetch_64bit(bld_base, type,
+   return si_llvm_emit_fetch_64bit(bld_base, 
tgsi2llvmtype(bld_base, type),
value, value2);
}
return bitcast(bld_base, type, value);
@@ -1978,7 +1980,8 @@ static LLVMValueRef fetch_constant(
 
lo = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle);
hi = fetch_constant(bld_base, reg, TGSI_TYPE_UNSIGNED, swizzle 
+ 1);
-   return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
+   return si_llvm_emit_fetch_64bit(bld_base, 
tgsi2llvmtype(bld_base, type),
+   lo, hi);
}
 
idx = reg->Register.Index * 4 + swizzle;
diff --git a/src/gallium/drivers/radeonsi/si_shader_internal.h 
b/src/gallium/drivers/radeonsi/si_shader_internal.h
index 4bd128ef56..e7c097c5fc 100644
--- a/src/gallium/drivers/radeonsi/si_shader_internal.h
+++ b/src/gallium/drivers/radeonsi/si_shader_internal.h
@@ -268,7 +268,7 @@ void si_llvm_dispose(struct si_shader_context *ctx);
 void si_llvm_optimize_module(struct si_shader_context *ctx);
 
 LLVMValueRef si_llvm_emit_fetch_64bit(struct lp_build_tgsi_context *bld_base,
- enum tgsi_opcode_type type,
+ LLVMTypeRef type,
  LLVMValueRef ptr,
  LLVMValueRef ptr2);
 
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c 
b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
index e965fa7c41..0843b3c63c 100644
--- a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
+++ b/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
@@ -399,7 +399,7 @@ get_pointer_into_array(struct si_shader_context *ctx,
 
 LLVMValueRef
 si_llvm_emit_fetch_64bit(struct lp_build_tgsi_context *bld_base,
-enum tgsi_opcode_type type,
+LLVMTypeRef type,
 LLVMValueRef ptr,
 LLVMValueRef ptr2)
 {
@@ -416,7 +416,7 @@ si_llvm_emit_fetch_64bit(struct lp_build_tgsi_context 
*bld_base,
result,
ac_to_integer(>ac, ptr2),
ctx->i32_1, "");
-   return bitcast(bld_base, type, result);
+   return LLVMBuildBitCast(ctx->ac.builder, result, type, "");
 }
 
 static LLVMValueRef
@@ -461,7 +461,8 @@ load_value_from_array(struct lp_build_tgsi_context 
*bld_base,
LLVMValueRef ptr_hi, val_hi;

Mesa (master): st/glsl_to_nir: use nir_lower_io_arrays_to_elements() to lower arrays

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: c86baf71fbb19fa0ae8f05faba86aec023cde9bc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c86baf71fbb19fa0ae8f05faba86aec023cde9bc

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Nov 15 14:36:22 2017 +1100

st/glsl_to_nir: use nir_lower_io_arrays_to_elements() to lower arrays

This pass is more fully featured, it supports geom and tess shaders.
It also supports interpolation intrinsics.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/mesa/state_tracker/st_glsl_to_nir.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 9672ffbe64..f76e453d49 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -634,7 +634,7 @@ st_finalize_nir(struct st_context *st, struct gl_program 
*prog,
 
NIR_PASS_V(nir, nir_split_var_copies);
NIR_PASS_V(nir, nir_lower_var_copies);
-   NIR_PASS_V(nir, nir_lower_io_types);
+   NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects);
 
if (nir->info.stage == MESA_SHADER_VERTEX) {
   /* Needs special handling so drvloc matches the vbo state: */

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Mesa (master): ac: add basic nir -> llvm type helper

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 6fd6cb6616dfb04cb383cace550c2100e54daaa5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6fd6cb6616dfb04cb383cace550c2100e54daaa5

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Fri Nov 10 13:47:50 2017 +1100

ac: add basic nir -> llvm type helper

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/amd/common/ac_nir_to_llvm.c | 22 ++
 1 file changed, 22 insertions(+)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index b58bae90c5..8610e36715 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -161,6 +161,28 @@ nir_to_llvm_context_from_abi(struct ac_shader_abi *abi)
return container_of(abi, ctx, abi);
 }
 
+static LLVMTypeRef
+nir2llvmtype(struct ac_nir_context *ctx,
+const struct glsl_type *type)
+{
+   switch (glsl_get_base_type(glsl_without_array(type))) {
+   case GLSL_TYPE_UINT:
+   case GLSL_TYPE_INT:
+   return ctx->ac.i32;
+   case GLSL_TYPE_UINT64:
+   case GLSL_TYPE_INT64:
+   return ctx->ac.i64;
+   case GLSL_TYPE_DOUBLE:
+   return ctx->ac.f64;
+   case GLSL_TYPE_FLOAT:
+   return ctx->ac.f32;
+   default:
+   assert(!"Unsupported type in nir2llvmtype()");
+   break;
+   }
+   return 0;
+}
+
 static LLVMValueRef get_sampler_desc(struct ac_nir_context *ctx,
 const nir_deref_var *deref,
 enum ac_descriptor_type desc_type,

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Mesa (master): radv: enable nir varying array splitting

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: f13790c92ff1433a0fbff35788761b75df567c44
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f13790c92ff1433a0fbff35788761b75df567c44

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Mon Oct 30 11:58:52 2017 +1100

radv: enable nir varying array splitting

Acked-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_pipeline.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 6490b04863..0146d6935e 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1682,6 +1682,9 @@ radv_link_shaders(struct radv_pipeline *pipeline, 
nir_shader **shaders)
}
 
for (int i = 1; i < shader_count; ++i)  {
+   nir_lower_io_arrays_to_elements(ordered_shaders[i],
+   ordered_shaders[i - 1]);
+
nir_remove_dead_variables(ordered_shaders[i],
  nir_var_shader_out);
nir_remove_dead_variables(ordered_shaders[i - 1],

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Mesa (master): radeonsi: pass llvm type to lds_load()

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: c4c8df94bd77b987143caa43ca6609bff1ab2908
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c4c8df94bd77b987143caa43ca6609bff1ab2908

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Nov  7 21:42:10 2017 +1100

radeonsi: pass llvm type to lds_load()

v2: use LLVMBuildBitCast() directly

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader.c | 26 +-
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 58cba2c5a4..012e79ada6 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1084,7 +1084,7 @@ static LLVMValueRef buffer_load(struct 
lp_build_tgsi_context *bld_base,
  * \param dw_addr  address in dwords
  */
 static LLVMValueRef lds_load(struct lp_build_tgsi_context *bld_base,
-enum tgsi_opcode_type type, unsigned swizzle,
+LLVMTypeRef type, unsigned swizzle,
 LLVMValueRef dw_addr)
 {
struct si_shader_context *ctx = si_shader_context(bld_base);
@@ -1101,13 +1101,12 @@ static LLVMValueRef lds_load(struct 
lp_build_tgsi_context *bld_base,
}
 
/* Split 64-bit loads. */
-   if (tgsi_type_is_64bit(type)) {
+   if (llvm_type_is_64bit(ctx, type)) {
LLVMValueRef lo, hi;
 
-   lo = lds_load(bld_base, TGSI_TYPE_UNSIGNED, swizzle, dw_addr);
-   hi = lds_load(bld_base, TGSI_TYPE_UNSIGNED, swizzle + 1, 
dw_addr);
-   return si_llvm_emit_fetch_64bit(bld_base, 
tgsi2llvmtype(bld_base, type),
-   lo, hi);
+   lo = lds_load(bld_base, ctx->i32, swizzle, dw_addr);
+   hi = lds_load(bld_base, ctx->i32, swizzle + 1, dw_addr);
+   return si_llvm_emit_fetch_64bit(bld_base, type, lo, hi);
}
 
dw_addr = lp_build_add(_base->uint_bld, dw_addr,
@@ -1115,7 +1114,7 @@ static LLVMValueRef lds_load(struct lp_build_tgsi_context 
*bld_base,
 
value = ac_lds_load(>ac, dw_addr);
 
-   return bitcast(bld_base, type, value);
+   return LLVMBuildBitCast(ctx->ac.builder, value, type, "");
 }
 
 /**
@@ -1171,7 +1170,7 @@ static LLVMValueRef fetch_input_tcs(
dw_addr = get_tcs_in_current_patch_offset(ctx);
dw_addr = get_dw_address(ctx, NULL, reg, stride, dw_addr);
 
-   return lds_load(bld_base, type, swizzle, dw_addr);
+   return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, 
dw_addr);
 }
 
 static LLVMValueRef fetch_output_tcs(
@@ -1191,7 +1190,7 @@ static LLVMValueRef fetch_output_tcs(
dw_addr = get_dw_address(ctx, NULL, reg, NULL, dw_addr);
}
 
-   return lds_load(bld_base, type, swizzle, dw_addr);
+   return lds_load(bld_base, tgsi2llvmtype(bld_base, type), swizzle, 
dw_addr);
 }
 
 static LLVMValueRef fetch_input_tes(
@@ -1355,7 +1354,8 @@ static LLVMValueRef fetch_input_gs(
 
vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
  LLVMConstInt(ctx->i32, param * 4, 0), 
"");
-   return lds_load(bld_base, type, swizzle, vtx_offset);
+   return lds_load(bld_base, tgsi2llvmtype(bld_base, type),
+   swizzle, vtx_offset);
}
 
/* GFX6: input load from the ESGS ring in memory. */
@@ -2754,7 +2754,7 @@ static void si_copy_tcs_inputs(struct 
lp_build_tgsi_context *bld_base)
  invocation_id,
  LLVMConstInt(ctx->i32, i, 0));
 
-   LLVMValueRef value = lds_load(bld_base, TGSI_TYPE_SIGNED, ~0,
+   LLVMValueRef value = lds_load(bld_base, ctx->ac.i32, ~0,
  lds_ptr);
 
ac_build_buffer_store_dword(>ac, buffer, value, 4, 
buffer_addr,
@@ -2841,11 +2841,11 @@ static void si_write_tess_factors(struct 
lp_build_tgsi_context *bld_base,
 
for (i = 0; i < outer_comps; i++) {
outer[i] = out[i] =
-   lds_load(bld_base, TGSI_TYPE_SIGNED, i, 
lds_outer);
+   lds_load(bld_base, ctx->ac.i32, i, lds_outer);
}
for (i = 0; i < inner_comps; i++) {
inner[i] = out[outer_comps+i] =
-   lds_load(bld_base, TGSI_TYPE_SIGNED, i, 
lds_inner);
+   lds_load(bld_base, ctx->ac.i32, i, lds_inner);
}
}
 

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Mesa (master): radeonsi: create si_llvm_load_input_gs()

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 4184e7c417fef08a1a28295d60dbb2d5fee08633
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4184e7c417fef08a1a28295d60dbb2d5fee08633

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Nov  7 21:13:37 2017 +1100

radeonsi: create si_llvm_load_input_gs()

This creates a common function that can be shared by the tgsi
and nir backends.

v2: use LLVMBuildBitCast() directly

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader.c  | 61 ++-
 src/gallium/drivers/radeonsi/si_shader_internal.h |  6 +++
 2 files changed, 44 insertions(+), 23 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 012e79ada6..950207b303 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -1306,33 +1306,28 @@ static void store_output_tcs(struct 
lp_build_tgsi_context *bld_base,
}
 }
 
-static LLVMValueRef fetch_input_gs(
-   struct lp_build_tgsi_context *bld_base,
-   const struct tgsi_full_src_register *reg,
-   enum tgsi_opcode_type type,
-   unsigned swizzle)
+LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
+  unsigned input_index,
+  unsigned vtx_offset_param,
+  LLVMTypeRef type,
+  unsigned swizzle)
 {
-   struct si_shader_context *ctx = si_shader_context(bld_base);
+   struct si_shader_context *ctx = si_shader_context_from_abi(abi);
+   struct lp_build_tgsi_context *bld_base = >bld_base;
struct si_shader *shader = ctx->shader;
struct lp_build_context *uint = >bld_base.uint_bld;
LLVMValueRef vtx_offset, soffset;
struct tgsi_shader_info *info = >selector->info;
-   unsigned semantic_name = info->input_semantic_name[reg->Register.Index];
-   unsigned semantic_index = 
info->input_semantic_index[reg->Register.Index];
+   unsigned semantic_name = info->input_semantic_name[input_index];
+   unsigned semantic_index = info->input_semantic_index[input_index];
unsigned param;
LLVMValueRef value;
 
-   if (swizzle != ~0 && semantic_name == TGSI_SEMANTIC_PRIMID)
-   return get_primitive_id(ctx, swizzle);
-
-   if (!reg->Register.Dimension)
-   return NULL;
-
param = si_shader_io_get_unique_index(semantic_name, semantic_index);
 
/* GFX9 has the ESGS ring in LDS. */
if (ctx->screen->info.chip_class >= GFX9) {
-   unsigned index = reg->Dimension.Index;
+   unsigned index = vtx_offset_param;
 
switch (index / 2) {
case 0:
@@ -1354,8 +1349,7 @@ static LLVMValueRef fetch_input_gs(
 
vtx_offset = LLVMBuildAdd(ctx->ac.builder, vtx_offset,
  LLVMConstInt(ctx->i32, param * 4, 0), 
"");
-   return lds_load(bld_base, tgsi2llvmtype(bld_base, type),
-   swizzle, vtx_offset);
+   return lds_load(bld_base, type, swizzle, vtx_offset);
}
 
/* GFX6: input load from the ESGS ring in memory. */
@@ -1363,14 +1357,14 @@ static LLVMValueRef fetch_input_gs(
LLVMValueRef values[TGSI_NUM_CHANNELS];
unsigned chan;
for (chan = 0; chan < TGSI_NUM_CHANNELS; chan++) {
-   values[chan] = fetch_input_gs(bld_base, reg, type, 
chan);
+   values[chan] = si_llvm_load_input_gs(abi, input_index, 
vtx_offset_param,
+type, chan);
}
return lp_build_gather_values(>gallivm, values,
  TGSI_NUM_CHANNELS);
}
 
/* Get the vertex offset parameter on GFX6. */
-   unsigned vtx_offset_param = reg->Dimension.Index;
LLVMValueRef gs_vtx_offset = ctx->gs_vtx_offset[vtx_offset_param];
 
vtx_offset = lp_build_mul_imm(uint, gs_vtx_offset, 4);
@@ -1379,17 +1373,38 @@ static LLVMValueRef fetch_input_gs(
 
value = ac_build_buffer_load(>ac, ctx->esgs_ring, 1, ctx->i32_0,
 vtx_offset, soffset, 0, 1, 0, true, false);
-   if (tgsi_type_is_64bit(type)) {
+   if (llvm_type_is_64bit(ctx, type)) {
LLVMValueRef value2;
soffset = LLVMConstInt(ctx->i32, (param * 4 + swizzle + 1) * 
256, 0);
 
value2 = ac_build_buffer_load(>ac, ctx->esgs_ring, 1,
  ctx->i32_0, vtx_offset, soffset,
 

Mesa (master): radeonsi: add nir support for es epilogue

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 73918b317283414bf4079eec34b33887fdcac8bf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=73918b317283414bf4079eec34b33887fdcac8bf

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Mon Nov  6 22:35:50 2017 +1100

radeonsi: add nir support for es epilogue

v2: make use of existing si_tgsi_emit_epilogue()

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/gallium/drivers/radeonsi/si_shader.c | 29 +
 1 file changed, 13 insertions(+), 16 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
b/src/gallium/drivers/radeonsi/si_shader.c
index 81b6c38678..aa9af1541d 100644
--- a/src/gallium/drivers/radeonsi/si_shader.c
+++ b/src/gallium/drivers/radeonsi/si_shader.c
@@ -3183,9 +3183,11 @@ static void si_llvm_emit_ls_epilogue(struct 
ac_shader_abi *abi,
si_set_ls_return_value_for_tcs(ctx);
 }
 
-static void si_llvm_emit_es_epilogue(struct lp_build_tgsi_context *bld_base)
+static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
+unsigned max_outputs,
+LLVMValueRef *addrs)
 {
-   struct si_shader_context *ctx = si_shader_context(bld_base);
+   struct si_shader_context *ctx = si_shader_context_from_abi(abi);
struct si_shader *es = ctx->shader;
struct tgsi_shader_info *info = >selector->info;
LLVMValueRef soffset = LLVMGetParam(ctx->main_fn,
@@ -3206,7 +3208,6 @@ static void si_llvm_emit_es_epilogue(struct 
lp_build_tgsi_context *bld_base)
}
 
for (i = 0; i < info->num_outputs; i++) {
-   LLVMValueRef *out_ptr = ctx->outputs[i];
int param;
 
if (info->output_semantic_name[i] == 
TGSI_SEMANTIC_VIEWPORT_INDEX ||
@@ -3217,7 +3218,7 @@ static void si_llvm_emit_es_epilogue(struct 
lp_build_tgsi_context *bld_base)
  
info->output_semantic_index[i]);
 
for (chan = 0; chan < 4; chan++) {
-   LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, 
out_ptr[chan], "");
+   LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, 
addrs[4 * i + chan], "");
out_val = ac_to_integer(>ac, out_val);
 
/* GFX9 has the ESGS ring in LDS. */
@@ -4428,7 +4429,6 @@ static void create_function(struct si_shader_context *ctx)
declare_vs_specific_input_sgprs(ctx, );
 
if (shader->key.as_es) {
-   assert(!shader->selector->nir);
ctx->param_es2gs_offset = add_arg(, ARG_SGPR, 
ctx->i32);
} else if (shader->key.as_ls) {
/* no extra parameters */
@@ -5733,15 +5733,13 @@ static bool si_compile_tgsi_main(struct 
si_shader_context *ctx,
switch (ctx->type) {
case PIPE_SHADER_VERTEX:
ctx->load_input = declare_input_vs;
-   if (shader->key.as_ls) {
+   if (shader->key.as_ls)
ctx->abi.emit_outputs = si_llvm_emit_ls_epilogue;
-   bld_base->emit_epilogue = si_tgsi_emit_epilogue;
-   } else if (shader->key.as_es)
-   bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
-   else {
+   else if (shader->key.as_es)
+   ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
+   else
ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
-   bld_base->emit_epilogue = si_tgsi_emit_epilogue;
-   }
+   bld_base->emit_epilogue = si_tgsi_emit_epilogue;
break;
case PIPE_SHADER_TESS_CTRL:
bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tcs;
@@ -5752,11 +5750,10 @@ static bool si_compile_tgsi_main(struct 
si_shader_context *ctx,
case PIPE_SHADER_TESS_EVAL:
bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_tes;
if (shader->key.as_es)
-   bld_base->emit_epilogue = si_llvm_emit_es_epilogue;
-   else {
+   ctx->abi.emit_outputs = si_llvm_emit_es_epilogue;
+   else
ctx->abi.emit_outputs = si_llvm_emit_vs_epilogue;
-   bld_base->emit_epilogue = si_tgsi_emit_epilogue;
-   }
+   bld_base->emit_epilogue = si_tgsi_emit_epilogue;
break;
case PIPE_SHADER_GEOMETRY:
bld_base->emit_fetch_funcs[TGSI_FILE_INPUT] = fetch_input_gs;

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Mesa (master): ac: move build_varying_gather_values() to ac_llvm_build.h and expose

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: caf15ce67001f09e4258ac545b7ed655eb63211c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=caf15ce67001f09e4258ac545b7ed655eb63211c

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Fri Nov 10 13:55:48 2017 +1100

ac: move build_varying_gather_values() to ac_llvm_build.h and expose

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/amd/common/ac_llvm_build.c  | 22 ++
 src/amd/common/ac_llvm_build.h  |  4 
 src/amd/common/ac_nir_to_llvm.c | 34 ++
 3 files changed, 32 insertions(+), 28 deletions(-)

diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 5640a23b8a..b2bf1bf7b5 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -371,6 +371,28 @@ ac_build_vote_eq(struct ac_llvm_context *ctx, LLVMValueRef 
value)
 }
 
 LLVMValueRef
+ac_build_varying_gather_values(struct ac_llvm_context *ctx, LLVMValueRef 
*values,
+  unsigned value_count, unsigned component)
+{
+   LLVMValueRef vec = NULL;
+
+   if (value_count == 1) {
+   return values[component];
+   } else if (!value_count)
+   unreachable("value_count is 0");
+
+   for (unsigned i = component; i < value_count + component; i++) {
+   LLVMValueRef value = values[i];
+
+   if (!i)
+   vec = LLVMGetUndef( LLVMVectorType(LLVMTypeOf(value), 
value_count));
+   LLVMValueRef index = LLVMConstInt(ctx->i32, i - component, 
false);
+   vec = LLVMBuildInsertElement(ctx->builder, vec, value, index, 
"");
+   }
+   return vec;
+}
+
+LLVMValueRef
 ac_build_gather_values_extended(struct ac_llvm_context *ctx,
LLVMValueRef *values,
unsigned value_count,
diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index 1f51937c9e..655dc1dcc8 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -113,6 +113,10 @@ LLVMValueRef ac_build_vote_any(struct ac_llvm_context 
*ctx, LLVMValueRef value);
 LLVMValueRef ac_build_vote_eq(struct ac_llvm_context *ctx, LLVMValueRef value);
 
 LLVMValueRef
+ac_build_varying_gather_values(struct ac_llvm_context *ctx, LLVMValueRef 
*values,
+  unsigned value_count, unsigned component);
+
+LLVMValueRef
 ac_build_gather_values_extended(struct ac_llvm_context *ctx,
LLVMValueRef *values,
unsigned value_count,
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 8610e36715..db1936b311 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2705,28 +2705,6 @@ get_dw_address(struct nir_to_llvm_context *ctx,
 }
 
 static LLVMValueRef
-build_varying_gather_values(struct ac_llvm_context *ctx, LLVMValueRef *values,
-   unsigned value_count, unsigned component)
-{
-   LLVMValueRef vec = NULL;
-
-   if (value_count == 1) {
-   return values[component];
-   } else if (!value_count)
-   unreachable("value_count is 0");
-
-   for (unsigned i = component; i < value_count + component; i++) {
-   LLVMValueRef value = values[i];
-
-   if (!i)
-   vec = LLVMGetUndef( LLVMVectorType(LLVMTypeOf(value), 
value_count));
-   LLVMValueRef index = LLVMConstInt(ctx->i32, i - component, 
false);
-   vec = LLVMBuildInsertElement(ctx->builder, vec, value, index, 
"");
-   }
-   return vec;
-}
-
-static LLVMValueRef
 load_tcs_input(struct nir_to_llvm_context *ctx,
   nir_intrinsic_instr *instr)
 {
@@ -2754,7 +2732,7 @@ load_tcs_input(struct nir_to_llvm_context *ctx,
dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
   ctx->ac.i32_1, "");
}
-   result = build_varying_gather_values(>ac, value, 
instr->num_components, comp);
+   result = ac_build_varying_gather_values(>ac, value, 
instr->num_components, comp);
result = LLVMBuildBitCast(ctx->builder, result, get_def_type(ctx->nir, 
>dest.ssa), "");
return result;
 }
@@ -2793,7 +2771,7 @@ load_tcs_output(struct nir_to_llvm_context *ctx,
dw_addr = LLVMBuildAdd(ctx->builder, dw_addr,
   ctx->ac.i32_1, "");
}
-   result = build_varying_gather_values(>ac, value, 
instr->num_components, comp);
+   result = ac_build_varying_gather_values(>ac, value, 
instr->num_components, comp);
result = LLVMBuildBitCast(ctx-&

Mesa (master): nir: add array lowering function that assumes there are no indirects

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 2bc49ac3e6a6c8f93a2f32d62555bd653faf8d3e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2bc49ac3e6a6c8f93a2f32d62555bd653faf8d3e

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Nov 15 14:28:01 2017 +1100

nir: add array lowering function that assumes there are no indirects

The gallium glsl->nir pass currently lowers away all indirects on both inputs
and outputs. This fuction allows us to lower vs inputs and fs outputs and also
lower things one stage at a time as we don't need to worry about indirects
on the other side of the shaders interface.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/compiler/nir/nir.h |  1 +
 src/compiler/nir/nir_lower_io_arrays_to_elements.c | 44 +-
 2 files changed, 44 insertions(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 83858afe14..189c17d162 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -2496,6 +2496,7 @@ bool nir_lower_load_const_to_scalar(nir_shader *shader);
 bool nir_lower_read_invocation_to_scalar(nir_shader *shader);
 bool nir_lower_phis_to_scalar(nir_shader *shader);
 void nir_lower_io_arrays_to_elements(nir_shader *producer, nir_shader 
*consumer);
+void nir_lower_io_arrays_to_elements_no_indirects(nir_shader *shader);
 void nir_lower_io_to_scalar(nir_shader *shader, nir_variable_mode mask);
 void nir_lower_io_to_scalar_early(nir_shader *shader, nir_variable_mode mask);
 
diff --git a/src/compiler/nir/nir_lower_io_arrays_to_elements.c 
b/src/compiler/nir/nir_lower_io_arrays_to_elements.c
index 94b93e3ec9..c785e22b0e 100644
--- a/src/compiler/nir/nir_lower_io_arrays_to_elements.c
+++ b/src/compiler/nir/nir_lower_io_arrays_to_elements.c
@@ -35,6 +35,9 @@ static unsigned
 get_io_offset(nir_builder *b, nir_deref_var *deref, nir_variable *var,
   unsigned *element_index)
 {
+   bool vs_in = (b->shader->info.stage == MESA_SHADER_VERTEX) &&
+(var->data.mode == nir_var_shader_in);
+
nir_deref *tail = >deref;
 
/* For per-vertex input arrays (i.e. geometry shader inputs), skip the
@@ -52,7 +55,7 @@ get_io_offset(nir_builder *b, nir_deref_var *deref, 
nir_variable *var,
  nir_deref_array *deref_array = nir_deref_as_array(tail);
  assert(deref_array->deref_array_type != 
nir_deref_array_type_indirect);
 
- unsigned size = glsl_count_attribute_slots(tail->type, false);
+ unsigned size = glsl_count_attribute_slots(tail->type, vs_in);
  offset += size * deref_array->base_offset;
 
  unsigned num_elements = glsl_type_is_array(tail->type) ?
@@ -340,6 +343,45 @@ lower_io_arrays_to_elements(nir_shader *shader, 
nir_variable_mode mask,
 }
 
 void
+nir_lower_io_arrays_to_elements_no_indirects(nir_shader *shader)
+{
+   struct hash_table *split_inputs =
+  _mesa_hash_table_create(NULL, _mesa_hash_pointer,
+  _mesa_key_pointer_equal);
+   struct hash_table *split_outputs =
+  _mesa_hash_table_create(NULL, _mesa_hash_pointer,
+  _mesa_key_pointer_equal);
+
+   uint64_t indirects[4] = {0}, patch_indirects[4] = {0};
+
+   lower_io_arrays_to_elements(shader, nir_var_shader_out, indirects,
+   patch_indirects, split_outputs);
+
+   lower_io_arrays_to_elements(shader, nir_var_shader_in, indirects,
+   patch_indirects, split_inputs);
+
+   /* Remove old input from the shaders inputs list */
+   struct hash_entry *entry;
+   hash_table_foreach(split_inputs, entry) {
+  nir_variable *var = (nir_variable *) entry->key;
+  exec_node_remove(>node);
+
+  free(entry->data);
+   }
+
+   /* Remove old output from the shaders outputs list */
+   hash_table_foreach(split_outputs, entry) {
+  nir_variable *var = (nir_variable *) entry->key;
+  exec_node_remove(>node);
+
+  free(entry->data);
+   }
+
+   _mesa_hash_table_destroy(split_inputs, NULL);
+   _mesa_hash_table_destroy(split_outputs, NULL);
+}
+
+void
 nir_lower_io_arrays_to_elements(nir_shader *producer, nir_shader *consumer)
 {
struct hash_table *split_inputs =

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Mesa (master): ac: add si_nir_load_input_gs() to the abi

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: ccd1810bbaf38ee31bd973f903bc9871cc8b1171
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ccd1810bbaf38ee31bd973f903bc9871cc8b1171

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Wed Nov  8 14:20:23 2017 +1100

ac: add si_nir_load_input_gs() to the abi

V2: make use of driver_location and don't expose NIR to the ABI.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>

---

 src/amd/common/ac_nir_to_llvm.c   | 39 +++
 src/amd/common/ac_shader_abi.h|  9 ++
 src/gallium/drivers/radeonsi/si_shader.c  |  1 +
 src/gallium/drivers/radeonsi/si_shader_internal.h |  9 ++
 src/gallium/drivers/radeonsi/si_shader_nir.c  | 20 
 5 files changed, 64 insertions(+), 14 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index db1936b311..96ba289a81 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -2894,27 +2894,29 @@ load_tes_input(struct nir_to_llvm_context *ctx,
 }
 
 static LLVMValueRef
-load_gs_input(struct nir_to_llvm_context *ctx,
- nir_intrinsic_instr *instr)
+load_gs_input(struct ac_shader_abi *abi,
+ unsigned location,
+ unsigned driver_location,
+ unsigned component,
+ unsigned num_components,
+ unsigned vertex_index,
+ unsigned const_index,
+ LLVMTypeRef type)
 {
-   LLVMValueRef indir_index, vtx_offset;
-   unsigned const_index;
+   struct nir_to_llvm_context *ctx = nir_to_llvm_context_from_abi(abi);
+   LLVMValueRef vtx_offset;
LLVMValueRef args[9];
unsigned param, vtx_offset_param;
LLVMValueRef value[4], result;
-   unsigned vertex_index;
-   get_deref_offset(ctx->nir, instr->variables[0],
-false, _index, NULL,
-_index, _index);
+
vtx_offset_param = vertex_index;
assert(vtx_offset_param < 6);
vtx_offset = LLVMBuildMul(ctx->builder, 
ctx->gs_vtx_offset[vtx_offset_param],
  LLVMConstInt(ctx->ac.i32, 4, false), "");
 
-   param = 
shader_io_get_unique_index(instr->variables[0]->var->data.location);
+   param = shader_io_get_unique_index(location);
 
-   unsigned comp = instr->variables[0]->var->data.location_frac;
-   for (unsigned i = comp; i < instr->num_components + comp; i++) {
+   for (unsigned i = component; i < num_components + component; i++) {
if (ctx->ac.chip_class >= GFX9) {
LLVMValueRef dw_addr = 
ctx->gs_vtx_offset[vtx_offset_param];
dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
@@ -2937,7 +2939,7 @@ load_gs_input(struct nir_to_llvm_context *ctx,
  AC_FUNC_ATTR_LEGACY);
}
}
-   result = ac_build_varying_gather_values(>ac, value, 
instr->num_components, comp);
+   result = ac_build_varying_gather_values(>ac, value, 
num_components, component);
 
return result;
 }
@@ -3006,7 +3008,16 @@ static LLVMValueRef visit_load_var(struct ac_nir_context 
*ctx,
if (ctx->stage == MESA_SHADER_TESS_EVAL)
return load_tes_input(ctx->nctx, instr);
if (ctx->stage == MESA_SHADER_GEOMETRY) {
-   return load_gs_input(ctx->nctx, instr);
+   LLVMValueRef indir_index;
+   unsigned const_index, vertex_index;
+   get_deref_offset(ctx, instr->variables[0],
+false, _index, NULL,
+_index, _index);
+   return ctx->abi->load_inputs(ctx->abi, 
instr->variables[0]->var->data.location,
+
instr->variables[0]->var->data.driver_location,
+
instr->variables[0]->var->data.location_frac, ve,
+vertex_index, const_index,
+nir2llvmtype(ctx, 
instr->variables[0]->var->type));
}
 
for (unsigned chan = comp; chan < ve + comp; chan++) {
@@ -6560,8 +6571,8 @@ LLVMModuleRef 
ac_translate_nir_to_llvm(LLVMTargetMachineRef tm,
 
if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
ctx.gs_next_vertex = ac_build_alloca(, 
ctx.ac.i32, "gs_next_vertex");
-
ctx.gs_max_out_vertices = 
shaders[i]->info.gs.vertices_out;
+ 

Mesa (master): st/glsl_to_nir: split the st_glsl_to_nir() function in two

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: d586f39cb0fb65624d9e0534f5eaafbf2a3ccc88
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d586f39cb0fb65624d9e0534f5eaafbf2a3ccc88

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Nov 14 09:15:54 2017 +1100

st/glsl_to_nir: split the st_glsl_to_nir() function in two

We want to be able to generate NIR then apply NIR optimisations.
Once the optimisations are done we can then apply the new post opt
function which assigns uniforms etc based on the optimised IR.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/mesa/state_tracker/st_glsl_to_nir.cpp | 56 +++
 1 file changed, 34 insertions(+), 22 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index bb0ba07012..b51e738b8c 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -249,7 +249,7 @@ st_nir_assign_uniform_locations(struct gl_program *prog,
 
 extern "C" {
 
-/* First half of converting glsl_to_nir.. this leaves things in a pre-
+/* First third of converting glsl_to_nir.. this leaves things in a pre-
  * nir_lower_io state, so that shader variants can more easily insert/
  * replace variables, etc.
  */
@@ -261,7 +261,6 @@ st_glsl_to_nir(struct st_context *st, struct gl_program 
*prog,
struct pipe_screen *pscreen = st->pipe->screen;
enum pipe_shader_type ptarget = pipe_shader_type_from_mesa(stage);
const nir_shader_compiler_options *options;
-   nir_shader *nir;
 
assert(pscreen->get_compiler_options);   /* drivers using NIR must 
implement this */
 
@@ -272,7 +271,17 @@ st_glsl_to_nir(struct st_context *st, struct gl_program 
*prog,
if (prog->nir)
   return prog->nir;
 
-   nir = glsl_to_nir(shader_program, stage, options);
+   return glsl_to_nir(shader_program, stage, options);
+}
+
+/* Second third of converting glsl_to_nir. This creates uniforms, gathers
+ * info on varyings, etc after NIR link time opts have been applied.
+ */
+static void
+st_glsl_to_nir_post_opts(struct st_context *st, struct gl_program *prog,
+ struct gl_shader_program *shader_program)
+{
+   nir_shader *nir = prog->nir;
 
/* Make a pass over the IR to add state references for any built-in
 * uniforms that are used.  This has to be done now (during linking).
@@ -313,7 +322,7 @@ st_glsl_to_nir(struct st_context *st, struct gl_program 
*prog,
NIR_PASS_V(nir, nir_lower_var_copies);
 
/* fragment shaders may need : */
-   if (stage == MESA_SHADER_FRAGMENT) {
+   if (prog->info.stage == MESA_SHADER_FRAGMENT) {
   static const gl_state_index wposTransformState[STATE_LENGTH] = {
  STATE_INTERNAL, STATE_FB_WPOS_Y_TRANSFORM
   };
@@ -350,15 +359,11 @@ st_glsl_to_nir(struct st_context *st, struct gl_program 
*prog,
if (st->ctx->_Shader->Flags & GLSL_DUMP) {
   _mesa_log("\n");
   _mesa_log("NIR IR for linked %s program %d:\n",
- _mesa_shader_stage_to_string(stage),
+ _mesa_shader_stage_to_string(prog->info.stage),
  shader_program->Name);
   nir_print_shader(nir, _mesa_get_log_file());
   _mesa_log("\n\n");
}
-
-   prog->nir = nir;
-
-   return nir;
 }
 
 /* TODO any better helper somewhere to sort a list? */
@@ -387,7 +392,7 @@ sort_varyings(struct exec_list *var_list)
exec_list_move_nodes_to(_list, var_list);
 }
 
-/* Second half of preparing nir from glsl, which happens after shader
+/* Last third of preparing nir from glsl, which happens after shader
  * variant lowering.
  */
 void
@@ -477,7 +482,7 @@ set_st_program(struct gl_program *prog,
}
 }
 
-struct gl_program *
+static void
 st_nir_get_mesa_program(struct gl_context *ctx,
 struct gl_shader_program *shader_program,
 struct gl_linked_shader *shader)
@@ -510,29 +515,36 @@ st_nir_get_mesa_program(struct gl_context *ctx,
nir_shader *nir = st_glsl_to_nir(st, prog, shader_program, shader->Stage);
 
set_st_program(prog, shader_program, nir);
-
-   return prog;
+   prog->nir = nir;
 }
 
 bool
 st_link_nir(struct gl_context *ctx,
 struct gl_shader_program *shader_program)
 {
+   struct st_context *st = st_context(ctx);
+
for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
   struct gl_linked_shader *shader = shader_program->_LinkedShaders[i];
   if (shader == NULL)
  continue;
 
-  struct gl_program *linked_prog =
- st_nir_get_mesa_program(ctx, shader_program, shader);
+  st_nir_get_mesa_program(ctx, shader_program, shader);
+   }
 
-  if (linked_prog) {
- if (!ctx->Driver.ProgramStringNotify(ctx,
-  _mesa_shader_stage_to_program(i),
-  linked_prog)) {
-_

Mesa (master): st/glsl_to_nir: call some lowering passes earlier

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: 90abaf8a214affa2bffdc04ee24f941caedb29c0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=90abaf8a214affa2bffdc04ee24f941caedb29c0

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Nov 14 12:56:20 2017 +1100

st/glsl_to_nir: call some lowering passes earlier

This is required so that we can enbale NIR linking optimisations.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/mesa/state_tracker/st_glsl_to_nir.cpp | 20 
 1 file changed, 12 insertions(+), 8 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 1b4f07111c..5f92bcef00 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -300,7 +300,11 @@ st_glsl_to_nir(struct st_context *st, struct gl_program 
*prog,
if (prog->nir)
   return prog->nir;
 
-   return glsl_to_nir(shader_program, stage, options);
+   nir_shader *nir = glsl_to_nir(shader_program, stage, options);
+
+   st_nir_opts(nir);
+
+   return nir;
 }
 
 /* Second third of converting glsl_to_nir. This creates uniforms, gathers
@@ -343,13 +347,6 @@ st_glsl_to_nir_post_opts(struct st_context *st, struct 
gl_program *prog,
 */
_mesa_associate_uniform_storage(st->ctx, shader_program, prog, true);
 
-   NIR_PASS_V(nir, nir_lower_io_to_temporaries,
- nir_shader_get_entrypoint(nir),
- true, true);
-   NIR_PASS_V(nir, nir_lower_global_vars_to_local);
-   NIR_PASS_V(nir, nir_split_var_copies);
-   NIR_PASS_V(nir, nir_lower_var_copies);
-
/* fragment shaders may need : */
if (prog->info.stage == MESA_SHADER_FRAGMENT) {
   static const gl_state_index wposTransformState[STATE_LENGTH] = {
@@ -497,6 +494,13 @@ st_nir_get_mesa_program(struct gl_context *ctx,
 
set_st_program(prog, shader_program, nir);
prog->nir = nir;
+
+   NIR_PASS_V(nir, nir_lower_io_to_temporaries,
+  nir_shader_get_entrypoint(nir),
+  true, true);
+   NIR_PASS_V(nir, nir_lower_global_vars_to_local);
+   NIR_PASS_V(nir, nir_split_var_copies);
+   NIR_PASS_V(nir, nir_lower_var_copies);
 }
 
 extern "C" {

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Mesa (master): st/glsl_to_nir: create set_st_program() helper

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: d38f99baecb8335421b392ecc38435a42d7b372c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d38f99baecb8335421b392ecc38435a42d7b372c

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Nov 14 09:03:45 2017 +1100

st/glsl_to_nir: create set_st_program() helper

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/mesa/state_tracker/st_glsl_to_nir.cpp | 74 +--
 1 file changed, 40 insertions(+), 34 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 8b66f8277a..bb0ba07012 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -435,44 +435,17 @@ st_finalize_nir(struct st_context *st, struct gl_program 
*prog,
   NIR_PASS_V(nir, nir_lower_samplers, shader_program);
 }
 
-struct gl_program *
-st_nir_get_mesa_program(struct gl_context *ctx,
-struct gl_shader_program *shader_program,
-struct gl_linked_shader *shader)
+static void
+set_st_program(struct gl_program *prog,
+   struct gl_shader_program *shader_program,
+   nir_shader *nir)
 {
-   struct st_context *st = st_context(ctx);
-   struct gl_program *prog;
-
-   validate_ir_tree(shader->ir);
-
-   prog = shader->Program;
-
-   prog->Parameters = _mesa_new_parameter_list();
-
-   _mesa_copy_linked_program_data(shader_program, shader);
-   _mesa_generate_parameters_list_for_uniforms(ctx, shader_program, shader,
-   prog->Parameters);
-
-   if (ctx->_Shader->Flags & GLSL_DUMP) {
-  _mesa_log("\n");
-  _mesa_log("GLSL IR for linked %s program %d:\n",
- _mesa_shader_stage_to_string(shader->Stage),
- shader_program->Name);
-  _mesa_print_ir(_mesa_get_log_file(), shader->ir, NULL);
-  _mesa_log("\n\n");
-   }
-
-   prog->ExternalSamplersUsed = gl_external_samplers(prog);
-   _mesa_update_shader_textures_used(shader_program, prog);
-
struct st_vertex_program *stvp;
struct st_common_program *stp;
struct st_fragment_program *stfp;
struct st_compute_program *stcp;
 
-   nir_shader *nir = st_glsl_to_nir(st, prog, shader_program, shader->Stage);
-
-   switch (shader->Stage) {
+   switch (prog->info.stage) {
case MESA_SHADER_VERTEX:
   stvp = (struct st_vertex_program *)prog;
   stvp->shader_program = shader_program;
@@ -500,10 +473,43 @@ st_nir_get_mesa_program(struct gl_context *ctx,
   stcp->tgsi.prog = nir_shader_clone(NULL, nir);
   break;
default:
-  assert(!"should not be reached");
-  return NULL;
+  unreachable("unknown shader stage");
}
+}
+
+struct gl_program *
+st_nir_get_mesa_program(struct gl_context *ctx,
+struct gl_shader_program *shader_program,
+struct gl_linked_shader *shader)
+{
+   struct st_context *st = st_context(ctx);
+   struct gl_program *prog;
+
+   validate_ir_tree(shader->ir);
+
+   prog = shader->Program;
+
+   prog->Parameters = _mesa_new_parameter_list();
+
+   _mesa_copy_linked_program_data(shader_program, shader);
+   _mesa_generate_parameters_list_for_uniforms(ctx, shader_program, shader,
+   prog->Parameters);
+
+   if (ctx->_Shader->Flags & GLSL_DUMP) {
+  _mesa_log("\n");
+  _mesa_log("GLSL IR for linked %s program %d:\n",
+ _mesa_shader_stage_to_string(shader->Stage),
+ shader_program->Name);
+  _mesa_print_ir(_mesa_get_log_file(), shader->ir, NULL);
+  _mesa_log("\n\n");
+   }
+
+   prog->ExternalSamplersUsed = gl_external_samplers(prog);
+   _mesa_update_shader_textures_used(shader_program, prog);
+
+   nir_shader *nir = st_glsl_to_nir(st, prog, shader_program, shader->Stage);
 
+   set_st_program(prog, shader_program, nir);
 
return prog;
 }

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Mesa (master): st/glsl: move nir linking loop to new function st_link_nir( )

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: da953b641d806cdb8031ff8fe7ce458963a3fe4f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=da953b641d806cdb8031ff8fe7ce458963a3fe4f

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Thu Nov  9 17:32:08 2017 +1100

st/glsl: move nir linking loop to new function st_link_nir()

This will allow us to refactor linking and include some nir link
time optimisations.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/mesa/state_tracker/st_glsl_to_nir.cpp  | 25 +
 src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 26 +-
 src/mesa/state_tracker/st_nir.h|  7 +++
 3 files changed, 41 insertions(+), 17 deletions(-)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index d0375dd3aa..8b66f8277a 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -508,4 +508,29 @@ st_nir_get_mesa_program(struct gl_context *ctx,
return prog;
 }
 
+bool
+st_link_nir(struct gl_context *ctx,
+struct gl_shader_program *shader_program)
+{
+   for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
+  struct gl_linked_shader *shader = shader_program->_LinkedShaders[i];
+  if (shader == NULL)
+ continue;
+
+  struct gl_program *linked_prog =
+ st_nir_get_mesa_program(ctx, shader_program, shader);
+
+  if (linked_prog) {
+ if (!ctx->Driver.ProgramStringNotify(ctx,
+  _mesa_shader_stage_to_program(i),
+  linked_prog)) {
+_mesa_reference_program(ctx, >Program, NULL);
+return false;
+ }
+  }
+   }
+
+   return true;
+}
+
 } /* extern "C" */
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp 
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index fa51fef343..8eeae86dab 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
@@ -6901,6 +6901,7 @@ st_link_shader(struct gl_context *ctx, struct 
gl_shader_program *prog)
struct pipe_screen *pscreen = ctx->st->pipe->screen;
assert(prog->data->LinkStatus);
 
+   bool use_nir = false;
for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
   if (prog->_LinkedShaders[i] == NULL)
  continue;
@@ -6920,6 +6921,12 @@ st_link_shader(struct gl_context *ctx, struct 
gl_shader_program *prog)
   unsigned if_threshold = pscreen->get_shader_param(pscreen, ptarget,
 
PIPE_SHADER_CAP_LOWER_IF_THRESHOLD);
 
+  enum pipe_shader_ir preferred_ir = (enum pipe_shader_ir)
+ pscreen->get_shader_param(pscreen, ptarget,
+   PIPE_SHADER_CAP_PREFERRED_IR);
+  if (preferred_ir == PIPE_SHADER_IR_NIR)
+ use_nir = true;
+
   /* If there are forms of indirect addressing that the driver
* cannot handle, perform the lowering pass.
*/
@@ -7023,24 +7030,17 @@ st_link_shader(struct gl_context *ctx, struct 
gl_shader_program *prog)
 
build_program_resource_list(ctx, prog);
 
+   if (use_nir)
+  return st_link_nir(ctx, prog);
+
for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
   struct gl_linked_shader *shader = prog->_LinkedShaders[i];
   if (shader == NULL)
  continue;
 
-  enum pipe_shader_type ptarget =
- pipe_shader_type_from_mesa(shader->Stage);
-  enum pipe_shader_ir preferred_ir = (enum pipe_shader_ir)
- pscreen->get_shader_param(pscreen, ptarget,
-   PIPE_SHADER_CAP_PREFERRED_IR);
-
-  struct gl_program *linked_prog = NULL;
-  if (preferred_ir == PIPE_SHADER_IR_NIR) {
- linked_prog = st_nir_get_mesa_program(ctx, prog, shader);
-  } else {
- linked_prog = get_mesa_program_tgsi(ctx, prog, shader);
- st_set_prog_affected_state_flags(linked_prog);
-  }
+  struct gl_program *linked_prog =
+ get_mesa_program_tgsi(ctx, prog, shader);
+  st_set_prog_affected_state_flags(linked_prog);
 
   if (linked_prog) {
  if (!ctx->Driver.ProgramStringNotify(ctx,
diff --git a/src/mesa/state_tracker/st_nir.h b/src/mesa/state_tracker/st_nir.h
index 9302a7c786..c65e753f9b 100644
--- a/src/mesa/state_tracker/st_nir.h
+++ b/src/mesa/state_tracker/st_nir.h
@@ -45,10 +45,9 @@ void st_finalize_nir(struct st_context *st, struct 
gl_program *prog,
  struct gl_shader_program *shader_program,
  struct nir_shader *nir);
 
-struct gl_program *
-st_nir_get_mesa_program(struct gl_context *ctx,
-struct gl_shader_program *shader_program,
-struct gl_linked_shader *shader);
+bool
+st_link_nir(struct gl_context *ctx,
+

Mesa (master): st/glsl_to_nir: add basic NIR opt loop helper

[Timothy Arceri]

Module: Mesa
Branch: master
Commit: bd98b8c74ef9d404f98b77519eaf327b938a150a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bd98b8c74ef9d404f98b77519eaf327b938a150a

Author: Timothy Arceri <tarc...@itsqueeze.com>
Date:   Tue Nov 14 10:13:58 2017 +1100

st/glsl_to_nir: add basic NIR opt loop helper

We need to be able to do these NIR opts in the state tracker
rather than the driver in order for the NIR linking opts to
be useful.

Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>

---

 src/mesa/state_tracker/st_glsl_to_nir.cpp | 31 +++
 1 file changed, 31 insertions(+)

diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
b/src/mesa/state_tracker/st_glsl_to_nir.cpp
index 4a772e6542..1b4f07111c 100644
--- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
+++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
@@ -247,6 +247,37 @@ st_nir_assign_uniform_locations(struct gl_program *prog,
*size = max;
 }
 
+static void
+st_nir_opts(nir_shader *nir)
+{
+   bool progress;
+   do {
+  progress = false;
+
+  NIR_PASS(progress, nir, nir_copy_prop);
+  NIR_PASS(progress, nir, nir_opt_remove_phis);
+  NIR_PASS(progress, nir, nir_opt_dce);
+  if (nir_opt_trivial_continues(nir)) {
+ progress = true;
+ NIR_PASS(progress, nir, nir_copy_prop);
+ NIR_PASS(progress, nir, nir_opt_dce);
+  }
+  NIR_PASS(progress, nir, nir_opt_if);
+  NIR_PASS(progress, nir, nir_opt_dead_cf);
+  NIR_PASS(progress, nir, nir_opt_cse);
+  NIR_PASS(progress, nir, nir_opt_peephole_select, 8);
+
+  NIR_PASS(progress, nir, nir_opt_algebraic);
+  NIR_PASS(progress, nir, nir_opt_constant_folding);
+
+  NIR_PASS(progress, nir, nir_opt_undef);
+  NIR_PASS(progress, nir, nir_opt_conditional_discard);
+  if (nir->options->max_unroll_iterations) {
+ NIR_PASS(progress, nir, nir_opt_loop_unroll, (nir_variable_mode)0);
+  }
+   } while (progress);
+}
+
 /* First third of converting glsl_to_nir.. this leaves things in a pre-
  * nir_lower_io state, so that shader variants can more easily insert/
  * replace variables, etc.

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