Mesa (master): r600/llvm: Allow arbitrary amount of temps in tgsi to llvm

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 797894036d1196805f02a2428fff82ece5855af7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=797894036d1196805f02a2428fff82ece5855af7

Author: Vincent Lejeune 
Date:   Mon Dec  2 00:54:44 2013 +0100

r600/llvm: Allow arbitrary amount of temps in tgsi to llvm

---

 src/gallium/drivers/radeon/radeon_llvm.h   |6 +++
 .../drivers/radeon/radeon_setup_tgsi_llvm.c|   43 ++--
 2 files changed, 45 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_llvm.h 
b/src/gallium/drivers/radeon/radeon_llvm.h
index 2cab6b0..00714fb 100644
--- a/src/gallium/drivers/radeon/radeon_llvm.h
+++ b/src/gallium/drivers/radeon/radeon_llvm.h
@@ -112,6 +112,12 @@ struct radeon_llvm_context {
LLVMValueRef outputs[RADEON_LLVM_MAX_OUTPUTS][TGSI_NUM_CHANNELS];
unsigned output_reg_count;
 
+   /** This pointer is used to contain the temporary values.
+ * The amount of temporary used in tgsi can't be bound to a max value 
and
+ * thus we must allocate this array at runtime.
+ */
+   LLVMValueRef *temps;
+   unsigned temps_count;
LLVMValueRef system_values[RADEON_LLVM_MAX_SYSTEM_VALUES];
 
/*=== Private Members ===*/
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c 
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 57026bf..5af6f3f 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -142,6 +142,13 @@ emit_array_fetch(
return result;
 }
 
+static bool uses_temp_indirect_addressing(
+   struct lp_build_tgsi_context *bld_base)
+{
+   struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
+   return (bld->indirect_files & (1 << TGSI_FILE_TEMPORARY));
+}
+
 static LLVMValueRef
 emit_fetch(
struct lp_build_tgsi_context *bld_base,
@@ -184,7 +191,11 @@ emit_fetch(
break;
 
case TGSI_FILE_TEMPORARY:
-   ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, swizzle);
+   if (uses_temp_indirect_addressing(bld_base)) {
+   ptr = lp_get_temp_ptr_soa(bld, reg->Register.Index, 
swizzle);
+   break;
+   }
+   ptr = ctx->temps[reg->Register.Index * TGSI_NUM_CHANNELS + 
swizzle];
result = LLVMBuildLoad(builder, ptr, "");
break;
 
@@ -216,6 +227,7 @@ static void emit_declaration(
const struct tgsi_full_declaration *decl)
 {
struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
+   unsigned first, last, i, idx;
switch(decl->Declaration.File) {
case TGSI_FILE_ADDRESS:
{
@@ -234,7 +246,23 @@ static void emit_declaration(
case TGSI_FILE_TEMPORARY:
if (decl->Declaration.Array && decl->Array.ArrayID <= 
RADEON_LLVM_MAX_ARRAYS)
ctx->arrays[decl->Array.ArrayID - 1] = decl->Range;
-   lp_emit_declaration_soa(bld_base, decl);
+   if (uses_temp_indirect_addressing(bld_base)) {
+   lp_emit_declaration_soa(bld_base, decl);
+   break;
+   }
+   first = decl->Range.First;
+   last = decl->Range.Last;
+   if (!ctx->temps_count) {
+   ctx->temps_count = 
bld_base->info->file_max[TGSI_FILE_TEMPORARY] + 1;
+   ctx->temps = MALLOC(TGSI_NUM_CHANNELS * 
ctx->temps_count * sizeof(LLVMValueRef));
+   }
+   for (idx = first; idx <= last; idx++) {
+   for (i = 0; i < TGSI_NUM_CHANNELS; i++) {
+   ctx->temps[idx * TGSI_NUM_CHANNELS + i] =
+   lp_build_alloca(bld_base->base.gallivm, 
bld_base->base.vec_type,
+   "temp");
+   }
+   }
break;
 
case TGSI_FILE_INPUT:
@@ -284,6 +312,7 @@ emit_store(
const struct tgsi_opcode_info * info,
LLVMValueRef dst[4])
 {
+   struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
struct lp_build_tgsi_soa_context *bld = lp_soa_context(bld_base);
struct gallivm_state *gallivm = bld->bld_base.base.gallivm;
struct lp_build_context base = bld->bld_base.base;
@@ -359,7 +388,10 @@ emit_store(
break;
 
case TGSI_FILE_TEMPORARY:
-   temp_ptr = lp_get_temp_ptr_soa(bld, i + 
range.First, chan_index);
+   if 
(uses_temp_indirect_addressing(bld_base))
+   temp_ptr = 
lp_get_temp_ptr_soa(bld, i + range.Fir

Mesa (master): r600/llvm: Store inputs in function arguments

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 88c8f1972976c506e8fb048100ed11fef1ca938b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=88c8f1972976c506e8fb048100ed11fef1ca938b

Author: Vincent Lejeune 
Date:   Wed Oct 30 18:35:58 2013 +0100

r600/llvm: Store inputs in function arguments

---

 src/gallium/drivers/r600/r600_llvm.c |  119 ++
 src/gallium/drivers/r600/r600_shader.c   |1 +
 src/gallium/drivers/radeon/radeon_llvm.h |1 +
 3 files changed, 121 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index 5afe3cb..a2ff0ec 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -77,6 +77,11 @@ static void llvm_load_system_value(
default: assert(!"unknown system value");
}
 
+#if HAVE_LLVM >= 0x0304
+   ctx->system_values[index] = 
LLVMBuildExtractElement(ctx->gallivm.builder,
+   LLVMGetParam(ctx->main_fn, 0), 
lp_build_const_int32(&(ctx->gallivm), chan),
+   "");
+#else
LLVMValueRef reg = lp_build_const_int32(
ctx->soa.bld_base.base.gallivm, chan);
ctx->system_values[index] = build_intrinsic(
@@ -84,8 +89,49 @@ static void llvm_load_system_value(
"llvm.R600.load.input",
ctx->soa.bld_base.base.elem_type, ®, 1,
LLVMReadNoneAttribute);
+#endif
 }
 
+#if HAVE_LLVM >= 0x0304
+static LLVMValueRef
+llvm_load_input_vector(
+   struct radeon_llvm_context * ctx, unsigned location, unsigned ijregs,
+   boolean interp)
+{
+   LLVMTypeRef VecType;
+   LLVMValueRef Args[3] = {
+   lp_build_const_int32(&(ctx->gallivm), location)
+   };
+   unsigned ArgCount = 1;
+   if (interp) {
+   VecType = 
LLVMVectorType(ctx->soa.bld_base.base.elem_type, 2);
+   LLVMValueRef IJIndex = LLVMGetParam(ctx->main_fn, 
ijregs / 2);
+   Args[ArgCount++] = 
LLVMBuildExtractElement(ctx->gallivm.builder, IJIndex,
+   lp_build_const_int32(&(ctx->gallivm), 2 * 
(ijregs % 2)), "");
+   Args[ArgCount++] = 
LLVMBuildExtractElement(ctx->gallivm.builder, IJIndex,
+   lp_build_const_int32(&(ctx->gallivm), 2 * 
(ijregs % 2) + 1), "");
+   LLVMValueRef HalfVec[2] = {
+   build_intrinsic(ctx->gallivm.builder, 
"llvm.R600.interp.xy",
+   VecType, Args, ArgCount, 
LLVMReadNoneAttribute),
+   build_intrinsic(ctx->gallivm.builder, 
"llvm.R600.interp.zw",
+   VecType, Args, ArgCount, 
LLVMReadNoneAttribute)
+   };
+   LLVMValueRef MaskInputs[4] = {
+   lp_build_const_int32(&(ctx->gallivm), 0),
+   lp_build_const_int32(&(ctx->gallivm), 1),
+   lp_build_const_int32(&(ctx->gallivm), 2),
+   lp_build_const_int32(&(ctx->gallivm), 3)
+   };
+   LLVMValueRef Mask = LLVMConstVector(MaskInputs, 4);
+   return LLVMBuildShuffleVector(ctx->gallivm.builder, 
HalfVec[0], HalfVec[1],
+   Mask, "");
+   } else {
+   VecType = 
LLVMVectorType(ctx->soa.bld_base.base.elem_type, 4);
+   return build_intrinsic(ctx->gallivm.builder, 
"llvm.R600.interp.const",
+   VecType, Args, ArgCount, LLVMReadNoneAttribute);
+   }
+}
+#else
 static LLVMValueRef
 llvm_load_input_helper(
struct radeon_llvm_context * ctx,
@@ -110,7 +156,22 @@ llvm_load_input_helper(
return build_intrinsic(bb->gallivm->builder, intrinsic,
bb->elem_type, &arg[0], arg_count, LLVMReadNoneAttribute);
 }
+#endif
 
+#if HAVE_LLVM >= 0x0304
+static LLVMValueRef
+llvm_face_select_helper(
+   struct radeon_llvm_context * ctx,
+   LLVMValueRef face, LLVMValueRef front_color, LLVMValueRef back_color)
+{
+   const struct lp_build_context * bb = &ctx->soa.bld_base.base;
+   LLVMValueRef is_front = LLVMBuildFCmp(
+   bb->gallivm->builder, LLVMRealUGT, face,
+   lp_build_const_float(bb->gallivm, 0.0f),"");
+   return LLVMBuildSelect(bb->gallivm->builder, is_front,
+   front_color, back_color, "");
+}
+#else
 static LLVMValueRef
 llvm_face_select_helper(
struct radeon_llvm_context *

Mesa (master): r600/llvm: Fix isampleBuffer on preEG

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 08556073d1fae993be4a30e34065af55efd1e0cd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=08556073d1fae993be4a30e34065af55efd1e0cd

Author: Vincent Lejeune 
Date:   Mon Oct 21 21:05:57 2013 +0200

r600/llvm: Fix isampleBuffer on preEG

---

 src/gallium/drivers/r600/r600_llvm.c |   15 ++-
 1 files changed, 14 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index d7fa5f8..5afe3cb 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -415,9 +415,22 @@ static void llvm_emit_tex(
case TGSI_OPCODE_TXQ: {
struct radeon_llvm_context * ctx = 
radeon_llvm_context(bld_base);
ctx->uses_tex_buffers = true;
-   LLVMValueRef offset = 
lp_build_const_int32(bld_base->base.gallivm, 0);
+   bool isEgPlus = (ctx->chip_class >= EVERGREEN);
+   LLVMValueRef offset = 
lp_build_const_int32(bld_base->base.gallivm,
+   isEgPlus ? 0 : 1);
LLVMValueRef cvecval = llvm_load_const_buffer(bld_base, 
offset,
LLVM_R600_BUFFER_INFO_CONST_BUFFER);
+   if (!isEgPlus) {
+   LLVMValueRef maskval[4] = {
+   lp_build_const_int32(gallivm, 1),
+   lp_build_const_int32(gallivm, 2),
+   lp_build_const_int32(gallivm, 3),
+   lp_build_const_int32(gallivm, 0),
+   };
+   LLVMValueRef mask = LLVMConstVector(maskval, 4);
+   cvecval = 
LLVMBuildShuffleVector(gallivm->builder, cvecval, cvecval,
+   mask, "");
+   }
emit_data->output[0] = cvecval;
return;
}

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Mesa (master): r600/llvm: Fix texbuf for pre EG gen

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 1184f8fd34ac00fe4be495f00a4d2e0820eac153
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1184f8fd34ac00fe4be495f00a4d2e0820eac153

Author: Vincent Lejeune 
Date:   Mon Oct 21 18:48:21 2013 +0200

r600/llvm: Fix texbuf for pre EG gen

---

 src/gallium/drivers/r600/r600_llvm.c |   29 +
 1 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index 34dd3ad..d7fa5f8 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -427,6 +427,35 @@ static void llvm_emit_tex(
emit_data->output[0] = build_intrinsic(gallivm->builder,
"llvm.R600.load.texbuf",
emit_data->dst_type, 
args, 2, LLVMReadNoneAttribute);
+   if (ctx->chip_class >= EVERGREEN)
+   return;
+   ctx->uses_tex_buffers = true;
+   LLVMDumpValue(emit_data->output[0]);
+   emit_data->output[0] = 
LLVMBuildBitCast(gallivm->builder,
+   emit_data->output[0], 
LLVMVectorType(bld_base->base.int_elem_type, 4),
+   "");
+   LLVMValueRef Mask = llvm_load_const_buffer(bld_base,
+   lp_build_const_int32(gallivm, 0),
+   LLVM_R600_BUFFER_INFO_CONST_BUFFER);
+   Mask = LLVMBuildBitCast(gallivm->builder, Mask,
+   LLVMVectorType(bld_base->base.int_elem_type, 
4), "");
+   emit_data->output[0] = 
lp_build_emit_llvm_binary(bld_base, TGSI_OPCODE_AND,
+   emit_data->output[0],
+   Mask);
+   LLVMValueRef WComponent = 
LLVMBuildExtractElement(gallivm->builder,
+   emit_data->output[0], 
lp_build_const_int32(gallivm, 3), "");
+   Mask = llvm_load_const_buffer(bld_base, 
lp_build_const_int32(gallivm, 1),
+   LLVM_R600_BUFFER_INFO_CONST_BUFFER);
+   Mask = LLVMBuildExtractElement(gallivm->builder, Mask,
+   lp_build_const_int32(gallivm, 0), "");
+   Mask = LLVMBuildBitCast(gallivm->builder, Mask,
+   bld_base->base.int_elem_type, "");
+   WComponent = lp_build_emit_llvm_binary(bld_base, 
TGSI_OPCODE_OR,
+   WComponent, Mask);
+   emit_data->output[0] = 
LLVMBuildInsertElement(gallivm->builder,
+   emit_data->output[0], WComponent, 
lp_build_const_int32(gallivm, 3), "");
+   emit_data->output[0] = 
LLVMBuildBitCast(gallivm->builder,
+   emit_data->output[0], 
LLVMVectorType(bld_base->base.elem_type, 4), "");
}
return;
default:

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Mesa (master): radeonsi: Allow Sinking pass to move preloaded const/res/ sampl

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 6e51c2a941955fd2a34d62437fc149e633e79ec7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e51c2a941955fd2a34d62437fc149e633e79ec7

Author: Vincent Lejeune 
Date:   Sat Oct  5 16:04:48 2013 +0200

radeonsi: Allow Sinking pass to move preloaded const/res/sampl

This fixes a crash in Unigine Heaven 3.0, and probably in some
others apps.

---

 src/gallium/drivers/radeonsi/radeonsi_shader.c |   32 ---
 src/gallium/drivers/radeonsi/si_state.h|1 +
 2 files changed, 28 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c 
b/src/gallium/drivers/radeonsi/radeonsi_shader.c
index 3aa271e..80ee325 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c
@@ -114,8 +114,12 @@ static LLVMValueRef build_indexed_load(
 {
struct lp_build_context * base = 
&si_shader_ctx->radeon_bld.soa.bld_base.base;
 
+   LLVMValueRef indices[2] = {
+   LLVMConstInt(LLVMInt64TypeInContext(base->gallivm->context), 0, 
false),
+   offset
+   };
LLVMValueRef computed_ptr = LLVMBuildGEP(
-   base->gallivm->builder, base_ptr, &offset, 1, "");
+   base->gallivm->builder, base_ptr, indices, 2, "");
 
LLVMValueRef result = LLVMBuildLoad(base->gallivm->builder, 
computed_ptr, "");
LLVMSetMetadata(result, 1, si_shader_ctx->const_md);
@@ -1581,9 +1585,14 @@ static void create_function(struct si_shader_context 
*si_shader_ctx)
v2i32 = LLVMVectorType(i32, 2);
v3i32 = LLVMVectorType(i32, 3);
 
-   params[SI_PARAM_CONST] = LLVMPointerType(LLVMVectorType(i8, 16), 
CONST_ADDR_SPACE);
-   params[SI_PARAM_SAMPLER] = params[SI_PARAM_CONST];
-   params[SI_PARAM_RESOURCE] = LLVMPointerType(LLVMVectorType(i8, 32), 
CONST_ADDR_SPACE);
+   params[SI_PARAM_CONST] = LLVMPointerType(
+   LLVMArrayType(LLVMVectorType(i8, 16), NUM_CONST_BUFFERS), 
CONST_ADDR_SPACE);
+   /* We assume at most 16 textures per program at the moment.
+* This need probably need to be changed to support bindless textures */
+   params[SI_PARAM_SAMPLER] = LLVMPointerType(
+   LLVMArrayType(LLVMVectorType(i8, 16), NUM_SAMPLER_VIEWS), 
CONST_ADDR_SPACE);
+   params[SI_PARAM_RESOURCE] = LLVMPointerType(
+   LLVMArrayType(LLVMVectorType(i8, 32), NUM_SAMPLER_STATES), 
CONST_ADDR_SPACE);
 
switch (si_shader_ctx->type) {
case TGSI_PROCESSOR_VERTEX:
@@ -1650,7 +1659,20 @@ static void create_function(struct si_shader_context 
*si_shader_ctx)
 
for (i = 0; i <= last_sgpr; ++i) {
LLVMValueRef P = 
LLVMGetParam(si_shader_ctx->radeon_bld.main_fn, i);
-   LLVMAddAttribute(P, LLVMInRegAttribute);
+   switch (i) {
+   default:
+   LLVMAddAttribute(P, LLVMInRegAttribute);
+   break;
+#if HAVE_LLVM >= 0x0304
+   /* We tell llvm that array inputs are passed by value to allow 
Sinking pass
+* to move load. Inputs are constant so this is fine. */
+   case SI_PARAM_CONST:
+   case SI_PARAM_SAMPLER:
+   case SI_PARAM_RESOURCE:
+   LLVMAddAttribute(P, LLVMByValAttribute);
+   break;
+#endif
+   }
}
 
 #if HAVE_LLVM >= 0x0304
diff --git a/src/gallium/drivers/radeonsi/si_state.h 
b/src/gallium/drivers/radeonsi/si_state.h
index 94a1521..6dbf880 100644
--- a/src/gallium/drivers/radeonsi/si_state.h
+++ b/src/gallium/drivers/radeonsi/si_state.h
@@ -107,6 +107,7 @@ union si_state {
  */
 #define FMASK_TEX_OFFSET   NUM_TEX_UNITS
 #define NUM_SAMPLER_VIEWS  (FMASK_TEX_OFFSET+NUM_TEX_UNITS)
+#define NUM_SAMPLER_STATES NUM_TEX_UNITS
 
 #define NUM_CONST_BUFFERS 2
 

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Mesa (master): r600/llvm: Adds support for MSAA

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 4e4c32ba11598818583ad0aa689339297ddf1c74
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4e4c32ba11598818583ad0aa689339297ddf1c74

Author: Vincent Lejeune 
Date:   Wed Sep 25 16:06:11 2013 +0200

r600/llvm: Adds support for MSAA

---

 src/gallium/drivers/r600/r600_llvm.c |   52 +-
 src/gallium/drivers/r600/r600_shader.c   |2 +
 src/gallium/drivers/radeon/radeon_llvm.h |1 +
 3 files changed, 54 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index b1b88b8..34dd3ad 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -406,8 +406,9 @@ static void llvm_emit_tex(
struct lp_build_emit_data * emit_data)
 {
struct gallivm_state * gallivm = bld_base->base.gallivm;
-   LLVMValueRef args[6];
+   LLVMValueRef args[7];
unsigned c, sampler_src;
+   struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
 
if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
switch (emit_data->inst->Instruction.Opcode) {
@@ -481,6 +482,55 @@ static void llvm_emit_tex(
args[c++] = lp_build_const_int32(gallivm,
emit_data->inst->Texture.Texture);
 
+   if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_TXF &&
+   (emit_data->inst->Texture.Texture == TGSI_TEXTURE_2D_MSAA ||
+   emit_data->inst->Texture.Texture == 
TGSI_TEXTURE_2D_ARRAY_MSAA)) {
+
+   switch (emit_data->inst->Texture.Texture) {
+   case TGSI_TEXTURE_2D_MSAA:
+   args[6] = lp_build_const_int32(gallivm, 
TGSI_TEXTURE_2D);
+   break;
+   case TGSI_TEXTURE_2D_ARRAY_MSAA:
+   args[6] = lp_build_const_int32(gallivm, 
TGSI_TEXTURE_2D_ARRAY);
+   break;
+   default:
+   break;
+   }
+
+   if (ctx->has_compressed_msaa_texturing) {
+   LLVMValueRef ldptr_args[10] = {
+   args[0], // Coord
+   args[1], // Offset X
+   args[2], // Offset Y
+   args[3], // Offset Z
+   args[4],
+   args[5],
+   lp_build_const_int32(gallivm, 1),
+   lp_build_const_int32(gallivm, 1),
+   lp_build_const_int32(gallivm, 1),
+   lp_build_const_int32(gallivm, 1)
+   };
+   LLVMValueRef ptr = build_intrinsic(gallivm->builder,
+   "llvm.R600.ldptr",
+   emit_data->dst_type, ldptr_args, 10, 
LLVMReadNoneAttribute);
+   LLVMValueRef Tmp = 
LLVMBuildExtractElement(gallivm->builder, args[0],
+   lp_build_const_int32(gallivm, 3), "");
+   Tmp = LLVMBuildMul(gallivm->builder, Tmp,
+   lp_build_const_int32(gallivm, 4), "");
+   LLVMValueRef ResX = 
LLVMBuildExtractElement(gallivm->builder, ptr,
+   lp_build_const_int32(gallivm, 0), "");
+   ResX = LLVMBuildBitCast(gallivm->builder, ResX,
+   bld_base->base.int_elem_type, "");
+   Tmp = LLVMBuildLShr(gallivm->builder, ResX, Tmp, "");
+   Tmp = LLVMBuildAnd(gallivm->builder, Tmp,
+   lp_build_const_int32(gallivm, 0xF), "");
+   args[0] = LLVMBuildInsertElement(gallivm->builder, 
args[0], Tmp,
+   lp_build_const_int32(gallivm, 3), "");
+   args[c++] = lp_build_const_int32(gallivm,
+   emit_data->inst->Texture.Texture);
+   }
+   }
+
emit_data->output[0] = build_intrinsic(gallivm->builder,
action->intr_name,
emit_data->dst_type, args, c, 
LLVMReadNoneAttribute);
diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 6ad7b2b..206db04 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1110,6 +1110,8 @@ static int r600_shader_from_tgsi(struct r600_screen 
*rscreen,
radeon_llvm_ctx.stream_outputs = &so;
radeon_llvm_ctx.clip_vertex = ctx.cv_output;
radeon_llvm_ctx.alpha_to_one = key.alpha_

Mesa (master): r600g/llvm: Undef z and w component of 2D TXP inst

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 8edbd7609b161a61d47c6caa1ed7b1756f80f07a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8edbd7609b161a61d47c6caa1ed7b1756f80f07a

Author: Vincent Lejeune 
Date:   Fri Sep  6 00:26:16 2013 +0200

r600g/llvm: Undef z and w component of 2D TXP inst

---

 src/gallium/drivers/r600/r600_llvm.c |3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index 3fe6a81..b1b88b8 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -433,7 +433,8 @@ static void llvm_emit_tex(
}
}
 
-   if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_TEX) {
+   if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_TEX ||
+   emit_data->inst->Instruction.Opcode == TGSI_OPCODE_TXP) {
LLVMValueRef Vector[4] = {
LLVMBuildExtractElement(gallivm->builder, 
emit_data->args[0],
lp_build_const_int32(gallivm, 0), ""),

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Mesa (master): r600g/llvm: fix txq for texture buffer

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 9f183eb7deb2bd40e9717deb723e4976f443fb88
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f183eb7deb2bd40e9717deb723e4976f443fb88

Author: Vincent Lejeune 
Date:   Tue May 21 16:34:52 2013 +0200

r600g/llvm: fix txq for texture buffer

---

 src/gallium/drivers/r600/r600_llvm.c |9 +++--
 src/gallium/drivers/r600/r600_shader.c   |1 +
 src/gallium/drivers/radeon/radeon_llvm.h |1 +
 3 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index 03a68e4..3fe6a81 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -23,6 +23,8 @@
 #define CONSTANT_BUFFER_0_ADDR_SPACE 8
 #define CONSTANT_BUFFER_1_ADDR_SPACE (CONSTANT_BUFFER_0_ADDR_SPACE + 
R600_UCP_CONST_BUFFER)
 #define CONSTANT_TXQ_BUFFER (CONSTANT_BUFFER_0_ADDR_SPACE + 
R600_TXQ_CONST_BUFFER)
+#define LLVM_R600_BUFFER_INFO_CONST_BUFFER \
+   (CONSTANT_BUFFER_0_ADDR_SPACE + R600_BUFFER_INFO_CONST_BUFFER)
 
 static LLVMValueRef llvm_load_const_buffer(
struct lp_build_tgsi_context * bld_base,
@@ -410,8 +412,11 @@ static void llvm_emit_tex(
if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
switch (emit_data->inst->Instruction.Opcode) {
case TGSI_OPCODE_TXQ: {
-   LLVMValueRef offset = 
lp_build_const_int32(bld_base->base.gallivm, 1);
-   LLVMValueRef cvecval = llvm_load_const_buffer(bld_base, 
offset, R600_BUFFER_INFO_CONST_BUFFER);
+   struct radeon_llvm_context * ctx = 
radeon_llvm_context(bld_base);
+   ctx->uses_tex_buffers = true;
+   LLVMValueRef offset = 
lp_build_const_int32(bld_base->base.gallivm, 0);
+   LLVMValueRef cvecval = llvm_load_const_buffer(bld_base, 
offset,
+   LLVM_R600_BUFFER_INFO_CONST_BUFFER);
emit_data->output[0] = cvecval;
return;
}
diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 80cdcd5..6ad7b2b 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1112,6 +1112,7 @@ static int r600_shader_from_tgsi(struct r600_screen 
*rscreen,
radeon_llvm_ctx.alpha_to_one = key.alpha_to_one;
mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
ctx.shader->has_txq_cube_array_z_comp = 
radeon_llvm_ctx.has_txq_cube_array_z_comp;
+   ctx.shader->uses_tex_buffers = radeon_llvm_ctx.uses_tex_buffers;
 
if (r600_llvm_compile(mod, rscreen->b.family, ctx.bc, 
&use_kill, dump)) {
radeon_llvm_dispose(&radeon_llvm_ctx);
diff --git a/src/gallium/drivers/radeon/radeon_llvm.h 
b/src/gallium/drivers/radeon/radeon_llvm.h
index 14a8c34..345ae70 100644
--- a/src/gallium/drivers/radeon/radeon_llvm.h
+++ b/src/gallium/drivers/radeon/radeon_llvm.h
@@ -67,6 +67,7 @@ struct radeon_llvm_context {
unsigned fs_color_all;
unsigned alpha_to_one;
unsigned has_txq_cube_array_z_comp;
+   unsigned uses_tex_buffers;
 
/*=== Front end configuration ===*/
 

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Mesa (master): r600g/llvm: fix cubemap lod/bias

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 9fd7ea786c0bc821253fcdd5c1b9e6309535385d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9fd7ea786c0bc821253fcdd5c1b9e6309535385d

Author: Vincent Lejeune 
Date:   Sat May 18 23:42:37 2013 +0200

r600g/llvm: fix cubemap lod/bias

---

 .../drivers/radeon/radeon_setup_tgsi_llvm.c|3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c 
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 0629b89..3f7e79f 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -654,6 +654,9 @@ void radeon_llvm_emit_prepare_cube_coords(
opcode == TGSI_OPCODE_TXB2 ||
opcode == TGSI_OPCODE_TXL2) {
coords[3] = coords_arg[4];
+   } else if (opcode == TGSI_OPCODE_TXB ||
+   opcode == TGSI_OPCODE_TXL) {
+   coords[3] = coords_arg[3];
}
}
 

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Mesa (master): r600g/llvm: Fix texelFetchOffset-2D

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 9a95fb16053746578be856a76f317ef157f1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a95fb16053746578be856a76f317ef157f1

Author: Vincent Lejeune 
Date:   Sat May 18 22:22:41 2013 +0200

r600g/llvm: Fix texelFetchOffset-2D

---

 src/gallium/drivers/r600/r600_llvm.c |6 ++
 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index 3d2c492..c1809b3 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -460,6 +460,12 @@ static void llvm_emit_tex(
for (c = 1; c < emit_data->arg_count; ++c)
args[c] = emit_data->args[c];
 
+   if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_TXF) {
+   args[1] = LLVMBuildShl(gallivm->builder, args[1], 
lp_build_const_int32(gallivm, 1), "");
+   args[2] = LLVMBuildShl(gallivm->builder, args[2], 
lp_build_const_int32(gallivm, 1), "");
+   args[3] = LLVMBuildShl(gallivm->builder, args[3], 
lp_build_const_int32(gallivm, 1), "");
+   }
+
sampler_src = emit_data->inst->Instruction.NumSrcRegs-1;
 
args[c++] = lp_build_const_int32(gallivm,

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Mesa (master): r600g/llvm: Fix cubearray textureSize

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 32c9cbb38fc03d028500b1904ff4d66a07e9471e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=32c9cbb38fc03d028500b1904ff4d66a07e9471e

Author: Vincent Lejeune 
Date:   Sat May 18 22:17:51 2013 +0200

r600g/llvm: Fix cubearray textureSize

---

 src/gallium/drivers/r600/r600_llvm.c |   15 +++
 src/gallium/drivers/r600/r600_shader.c   |1 +
 src/gallium/drivers/radeon/radeon_llvm.h |1 +
 3 files changed, 17 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index 26d40a2..3d2c492 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -22,6 +22,7 @@
 
 #define CONSTANT_BUFFER_0_ADDR_SPACE 8
 #define CONSTANT_BUFFER_1_ADDR_SPACE (CONSTANT_BUFFER_0_ADDR_SPACE + 
R600_UCP_CONST_BUFFER)
+#define CONSTANT_TXQ_BUFFER (CONSTANT_BUFFER_0_ADDR_SPACE + 
R600_TXQ_CONST_BUFFER)
 
 static LLVMValueRef llvm_load_const_buffer(
struct lp_build_tgsi_context * bld_base,
@@ -471,6 +472,20 @@ static void llvm_emit_tex(
emit_data->output[0] = build_intrinsic(gallivm->builder,
action->intr_name,
emit_data->dst_type, args, c, 
LLVMReadNoneAttribute);
+
+   if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_TXQ &&
+   ((emit_data->inst->Texture.Texture == TGSI_TEXTURE_CUBE_ARRAY ||
+   emit_data->inst->Texture.Texture == 
TGSI_TEXTURE_SHADOWCUBE_ARRAY)))
+   if (emit_data->inst->Dst[0].Register.WriteMask & 4) {
+   LLVMValueRef offset = 
lp_build_const_int32(bld_base->base.gallivm, 0);
+   LLVMValueRef ZLayer = 
LLVMBuildExtractElement(gallivm->builder,
+   llvm_load_const_buffer(bld_base, offset, 
CONSTANT_TXQ_BUFFER),
+   lp_build_const_int32(gallivm, 0), "");
+
+   emit_data->output[0] = 
LLVMBuildInsertElement(gallivm->builder, emit_data->output[0], ZLayer, 
lp_build_const_int32(gallivm, 2), "");
+   struct radeon_llvm_context * ctx = 
radeon_llvm_context(bld_base);
+   ctx->has_txq_cube_array_z_comp = true;
+   }
 }
 
 static void emit_cndlt(
diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 4d74db0..81ed3ce 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1169,6 +1169,7 @@ static int r600_shader_from_tgsi(struct r600_screen 
*rscreen,
radeon_llvm_ctx.clip_vertex = ctx.cv_output;
radeon_llvm_ctx.alpha_to_one = key.alpha_to_one;
mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
+   ctx.shader->has_txq_cube_array_z_comp = 
radeon_llvm_ctx.has_txq_cube_array_z_comp;
 
if (r600_llvm_compile(mod, rscreen->family, ctx.bc, &use_kill, 
dump)) {
radeon_llvm_dispose(&radeon_llvm_ctx);
diff --git a/src/gallium/drivers/radeon/radeon_llvm.h 
b/src/gallium/drivers/radeon/radeon_llvm.h
index 1d4bd45..14a8c34 100644
--- a/src/gallium/drivers/radeon/radeon_llvm.h
+++ b/src/gallium/drivers/radeon/radeon_llvm.h
@@ -66,6 +66,7 @@ struct radeon_llvm_context {
unsigned color_buffer_count;
unsigned fs_color_all;
unsigned alpha_to_one;
+   unsigned has_txq_cube_array_z_comp;
 
/*=== Front end configuration ===*/
 

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Mesa (master): r600g/llvm: Factorize code loading from const buffer.

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 9c2943601e088c6fb3e871f8d706ded8f68493bc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9c2943601e088c6fb3e871f8d706ded8f68493bc

Author: Vincent Lejeune 
Date:   Sun May 19 15:40:19 2013 +0200

r600g/llvm: Factorize code loading from const buffer.

---

 src/gallium/drivers/r600/r600_llvm.c |   51 --
 1 files changed, 24 insertions(+), 27 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index c6c9123..26d40a2 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -23,30 +23,40 @@
 #define CONSTANT_BUFFER_0_ADDR_SPACE 8
 #define CONSTANT_BUFFER_1_ADDR_SPACE (CONSTANT_BUFFER_0_ADDR_SPACE + 
R600_UCP_CONST_BUFFER)
 
+static LLVMValueRef llvm_load_const_buffer(
+   struct lp_build_tgsi_context * bld_base,
+   LLVMValueRef OffsetValue,
+   unsigned ConstantAddressSpace)
+{
+   LLVMValueRef offset[2] = {
+   
LLVMConstInt(LLVMInt64TypeInContext(bld_base->base.gallivm->context), 0, false),
+   OffsetValue
+   };
+
+   LLVMTypeRef const_ptr_type = 
LLVMPointerType(LLVMArrayType(LLVMVectorType(bld_base->base.elem_type, 4), 
1024),
+   ConstantAddressSpace);
+   LLVMValueRef const_ptr = 
LLVMBuildIntToPtr(bld_base->base.gallivm->builder, 
lp_build_const_int32(bld_base->base.gallivm, 0), const_ptr_type, "");
+   LLVMValueRef ptr = LLVMBuildGEP(bld_base->base.gallivm->builder, 
const_ptr, offset, 2, "");
+   return LLVMBuildLoad(bld_base->base.gallivm->builder, ptr, "");
+}
+
 static LLVMValueRef llvm_fetch_const(
struct lp_build_tgsi_context * bld_base,
const struct tgsi_full_src_register *reg,
enum tgsi_opcode_type type,
unsigned swizzle)
 {
-   LLVMValueRef offset[2] = {
-   
LLVMConstInt(LLVMInt64TypeInContext(bld_base->base.gallivm->context), 0, false),
-   lp_build_const_int32(bld_base->base.gallivm, 
reg->Register.Index)
-   };
+   LLVMValueRef offset = lp_build_const_int32(bld_base->base.gallivm, 
reg->Register.Index);
if (reg->Register.Indirect) {
struct lp_build_tgsi_soa_context *bld = 
lp_soa_context(bld_base);
LLVMValueRef index = 
LLVMBuildLoad(bld_base->base.gallivm->builder, 
bld->addr[reg->Indirect.Index][reg->Indirect.Swizzle], "");
-   offset[1] = LLVMBuildAdd(bld_base->base.gallivm->builder, 
offset[1], index, "");
+   offset = LLVMBuildAdd(bld_base->base.gallivm->builder, offset, 
index, "");
}
unsigned ConstantAddressSpace = CONSTANT_BUFFER_0_ADDR_SPACE ;
if (reg->Register.Dimension) {
ConstantAddressSpace += reg->Dimension.Index;
}
-   LLVMTypeRef const_ptr_type = 
LLVMPointerType(LLVMArrayType(LLVMVectorType(bld_base->base.elem_type, 4), 
1024),
-   ConstantAddressSpace);
-   LLVMValueRef const_ptr = 
LLVMBuildIntToPtr(bld_base->base.gallivm->builder, 
lp_build_const_int32(bld_base->base.gallivm, 0), const_ptr_type, "");
-   LLVMValueRef ptr = LLVMBuildGEP(bld_base->base.gallivm->builder, 
const_ptr, offset, 2, "");
-   LLVMValueRef cvecval = LLVMBuildLoad(bld_base->base.gallivm->builder, 
ptr, "");
+   LLVMValueRef cvecval = llvm_load_const_buffer(bld_base, offset, 
ConstantAddressSpace);
LLVMValueRef cval = 
LLVMBuildExtractElement(bld_base->base.gallivm->builder, cvecval, 
lp_build_const_int32(bld_base->base.gallivm, swizzle), "");
return bitcast(bld_base, type, cval);
 }
@@ -250,14 +260,8 @@ static void llvm_emit_epilogue(struct 
lp_build_tgsi_context * bld_base)
LLVMValueRef adjusted_elements[4];
for (reg_index = 0; reg_index < 2; reg_index 
++) {
for (chan = 0; chan < 
TGSI_NUM_CHANNELS; chan++) {
-   LLVMValueRef offset[2] = {
-   
LLVMConstInt(LLVMInt64TypeInContext(bld_base->base.gallivm->context), 0, false),
-   
lp_build_const_int32(bld_base->base.gallivm, reg_index * 4 + chan)
-   };
-   LLVMTypeRef const_ptr_type = 
LLVMPointerType(LLVMArrayType(LLVMVectorType(bld_base->base.elem_type, 4), 
1024), CONSTANT_BUFFER_1_ADDR_SPACE);
-   LLVMValueRef const_ptr = 
LLVMBuildIntToPtr(bld

Mesa (master): r600g/llvm: Undefines unrequired texture coord values

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: b42fe195a2578473c433695fe417253e8786c4c6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b42fe195a2578473c433695fe417253e8786c4c6

Author: Vincent Lejeune 
Date:   Tue Apr 30 15:58:00 2013 +0200

r600g/llvm: Undefines unrequired texture coord values

This is a port of "r600g:mask unused source components for SAMPLE"
patch from Vadim Girlin.

---

 src/gallium/drivers/r600/r600_llvm.c |   29 -
 1 files changed, 28 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index 83d7340..2ff109c 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -429,9 +429,36 @@ static void llvm_emit_tex(
}
}
 
+   if (emit_data->inst->Instruction.Opcode == TGSI_OPCODE_TEX) {
+   LLVMValueRef Vector[4] = {
+   LLVMBuildExtractElement(gallivm->builder, 
emit_data->args[0],
+   lp_build_const_int32(gallivm, 0), ""),
+   LLVMBuildExtractElement(gallivm->builder, 
emit_data->args[0],
+   lp_build_const_int32(gallivm, 1), ""),
+   LLVMBuildExtractElement(gallivm->builder, 
emit_data->args[0],
+   lp_build_const_int32(gallivm, 2), ""),
+   LLVMBuildExtractElement(gallivm->builder, 
emit_data->args[0],
+   lp_build_const_int32(gallivm, 3), ""),
+   };
+   switch (emit_data->inst->Texture.Texture) {
+   case TGSI_TEXTURE_2D:
+   case TGSI_TEXTURE_RECT:
+   Vector[2] = Vector[3] = 
LLVMGetUndef(bld_base->base.elem_type);
+   break;
+   case TGSI_TEXTURE_1D:
+   Vector[1] = Vector[2] = Vector[3] = 
LLVMGetUndef(bld_base->base.elem_type);
+   break;
+   default:
+   break;
+   }
+   args[0] = lp_build_gather_values(gallivm, Vector, 4);
+   } else {
+   args[0] = emit_data->args[0];
+   }
+
assert(emit_data->arg_count + 2 <= Elements(args));
 
-   for (c = 0; c < emit_data->arg_count; ++c)
+   for (c = 1; c < emit_data->arg_count; ++c)
args[c] = emit_data->args[c];
 
sampler_src = emit_data->inst->Instruction.NumSrcRegs-1;

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Mesa (master): r600g/llvm: Fix opencl build

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: a6a4b70e2dc11132fbb29ef5e47c26e680c4e885
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a6a4b70e2dc11132fbb29ef5e47c26e680c4e885

Author: Vincent Lejeune 
Date:   Tue Apr 30 16:08:58 2013 +0200

r600g/llvm: Fix opencl build

---

 src/gallium/drivers/r600/r600_shader.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 81c4c36..bb54e38 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -280,7 +280,7 @@ int r600_compute_shader_create(struct pipe_context * ctx,
shader_ctx.bc->type = TGSI_PROCESSOR_COMPUTE;
shader_ctx.bc->isa = r600_ctx->isa;
r600_llvm_compile(mod, &bytes, &byte_count, r600_ctx->family,
-   shader_ctx.bc, dump);
+   shader_ctx.bc, &use_kill, dump);
r600_bytecode_from_byte_stream(&shader_ctx, bytes, byte_count);
if (shader_ctx.bc->chip_class == CAYMAN) {
cm_bytecode_add_cf_end(shader_ctx.bc);

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Mesa (master): r600g/llvm: get use_kill from compiler shader

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 51e9bfdc48b6d73aa0fa0a8f7911863b5968bdb9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=51e9bfdc48b6d73aa0fa0a8f7911863b5968bdb9

Author: Vincent Lejeune 
Date:   Sun Apr 28 00:01:00 2013 +0200

r600g/llvm: get use_kill from compiler shader

---

 src/gallium/drivers/r600/r600_llvm.c |2 ++
 src/gallium/drivers/r600/r600_llvm.h |1 +
 src/gallium/drivers/r600/r600_shader.c   |6 +-
 src/gallium/drivers/radeon/LLVM_REVISION.txt |2 +-
 4 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index 2050be2..83d7340 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -556,6 +556,7 @@ unsigned r600_llvm_compile(
unsigned * inst_byte_count,
enum radeon_family family,
struct r600_bytecode *bc,
+   boolean *use_kill,
unsigned dump)
 {
unsigned r;
@@ -566,6 +567,7 @@ unsigned r600_llvm_compile(
*inst_byte_count = binary.code_size;
bc->ngpr = util_le32_to_cpu(*(uint32_t*)binary.config);
bc->nstack = util_le32_to_cpu(*(uint32_t*)(binary.config + 4));
+   *use_kill = util_le32_to_cpu(*(uint32_t*)(binary.config + 8));
return r;
 }
 
diff --git a/src/gallium/drivers/r600/r600_llvm.h 
b/src/gallium/drivers/r600/r600_llvm.h
index 919dd24..50bbca6 100644
--- a/src/gallium/drivers/r600/r600_llvm.h
+++ b/src/gallium/drivers/r600/r600_llvm.h
@@ -22,6 +22,7 @@ unsigned r600_llvm_compile(
unsigned * inst_byte_count,
enum radeon_family family,
struct r600_bytecode *bc,
+   boolean *use_kill,
unsigned dump);
 
 #endif /* defined R600_USE_LLVM || defined HAVE_OPENCL */
diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 0204f80..81c4c36 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -271,6 +271,7 @@ int r600_compute_shader_create(struct pipe_context * ctx,
unsigned char * bytes;
unsigned byte_count;
struct r600_shader_ctx shader_ctx;
+   boolean use_kill = false;
bool dump = (r600_ctx->screen->debug_flags & DBG_CS) != 0;
 
shader_ctx.bc = bytecode;
@@ -1445,6 +1446,7 @@ static int r600_shader_from_tgsi(struct r600_screen 
*rscreen,
struct radeon_llvm_context radeon_llvm_ctx;
LLVMModuleRef mod;
bool dump = r600_can_dump_shader(rscreen, ctx.type);
+   boolean use_kill = false;
 
memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
radeon_llvm_ctx.type = ctx.type;
@@ -1461,7 +1463,7 @@ static int r600_shader_from_tgsi(struct r600_screen 
*rscreen,
mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
 
if (r600_llvm_compile(mod, &inst_bytes, &inst_byte_count,
- rscreen->family, ctx.bc, dump)) {
+ rscreen->family, ctx.bc, &use_kill, 
dump)) {
FREE(inst_bytes);
radeon_llvm_dispose(&radeon_llvm_ctx);
use_llvm = 0;
@@ -1471,6 +1473,8 @@ static int r600_shader_from_tgsi(struct r600_screen 
*rscreen,
ctx.file_offset[TGSI_FILE_OUTPUT] =
ctx.file_offset[TGSI_FILE_INPUT];
}
+   if (use_kill)
+   ctx.shader->uses_kill = use_kill;
radeon_llvm_dispose(&radeon_llvm_ctx);
}
 #endif
diff --git a/src/gallium/drivers/radeon/LLVM_REVISION.txt 
b/src/gallium/drivers/radeon/LLVM_REVISION.txt
index f003aab..fcd9387 100644
--- a/src/gallium/drivers/radeon/LLVM_REVISION.txt
+++ b/src/gallium/drivers/radeon/LLVM_REVISION.txt
@@ -1 +1 @@
-@180124
+@180751

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Mesa (master): r600/llvm: Read stacksize from config header

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: edd90a19ca2a13b8694f2560e77c9f02446cfaa7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=edd90a19ca2a13b8694f2560e77c9f02446cfaa7

Author: Vincent Lejeune 
Date:   Fri Apr 19 20:10:44 2013 +0200

r600/llvm: Read stacksize from config header

---

 src/gallium/drivers/r600/r600_llvm.c |2 ++
 src/gallium/drivers/r600/r600_llvm.h |1 +
 src/gallium/drivers/r600/r600_shader.c   |3 +--
 src/gallium/drivers/radeon/LLVM_REVISION.txt |2 +-
 4 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index 35d6c90..8344fb0 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -556,6 +556,7 @@ unsigned r600_llvm_compile(
unsigned * inst_byte_count,
enum radeon_family family,
unsigned *ngpr,
+   unsigned *stack_size,
unsigned dump)
 {
unsigned r;
@@ -565,6 +566,7 @@ unsigned r600_llvm_compile(
*inst_bytes = binary.code;
*inst_byte_count = binary.code_size;
*ngpr = util_le32_to_cpu(*(uint32_t*)binary.config);
+   *stack_size = util_le32_to_cpu(*(uint32_t*)binary.config + 4);
return r;
 }
 
diff --git a/src/gallium/drivers/r600/r600_llvm.h 
b/src/gallium/drivers/r600/r600_llvm.h
index afc6881..b08343a 100644
--- a/src/gallium/drivers/r600/r600_llvm.h
+++ b/src/gallium/drivers/r600/r600_llvm.h
@@ -21,6 +21,7 @@ unsigned r600_llvm_compile(
unsigned * inst_byte_count,
enum radeon_family family,
unsigned *ngpr,
+   unsigned *stack_size,
unsigned dump);
 
 #endif /* defined R600_USE_LLVM || defined HAVE_OPENCL */
diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 9e83ce6..606dbea 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -591,7 +591,6 @@ static void r600_bytecode_from_byte_stream(struct 
r600_shader_ctx *ctx,
unsigned char * bytes,  unsigned num_bytes)
 {
unsigned bytes_read = 0;
-   ctx->bc->nstack = bytes[bytes_read++];
unsigned i, byte;
while (bytes_read < num_bytes) {
char inst_type = bytes[bytes_read++];
@@ -1462,7 +1461,7 @@ static int r600_shader_from_tgsi(struct r600_screen 
*rscreen,
mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
 
if (r600_llvm_compile(mod, &inst_bytes, &inst_byte_count,
- rscreen->family, &ctx.bc->ngpr, dump)) {
+ rscreen->family, &ctx.bc->ngpr, 
&ctx.bc->nstack, dump)) {
FREE(inst_bytes);
radeon_llvm_dispose(&radeon_llvm_ctx);
use_llvm = 0;
diff --git a/src/gallium/drivers/radeon/LLVM_REVISION.txt 
b/src/gallium/drivers/radeon/LLVM_REVISION.txt
index f7e8f7d..f003aab 100644
--- a/src/gallium/drivers/radeon/LLVM_REVISION.txt
+++ b/src/gallium/drivers/radeon/LLVM_REVISION.txt
@@ -1 +1 @@
-@180123
+@180124

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Mesa (master): /bin/bash: q : commande introuvable

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: a7f73f5155d1b36bf493a70639ca9bcb023beba3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a7f73f5155d1b36bf493a70639ca9bcb023beba3

Author: Vincent Lejeune 
Date:   Sat Apr 13 16:35:39 2013 +0200

/bin/bash: q : commande introuvable

---

 src/gallium/drivers/r600/r600_shader.c   |2 +-
 src/gallium/drivers/radeon/LLVM_REVISION.txt |2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 2907c7c..9e83ce6 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1899,7 +1899,7 @@ static int r600_shader_from_tgsi(struct r600_screen 
*rscreen,
}
}
/* add program end */
-   if (ctx.bc->chip_class == CAYMAN)
+   if (!use_llvm && ctx.bc->chip_class == CAYMAN)
cm_bytecode_add_cf_end(ctx.bc);
 
/* check GPR limit - we have 124 = 128 - 4
diff --git a/src/gallium/drivers/radeon/LLVM_REVISION.txt 
b/src/gallium/drivers/radeon/LLVM_REVISION.txt
index b633ea6..f7e8f7d 100644
--- a/src/gallium/drivers/radeon/LLVM_REVISION.txt
+++ b/src/gallium/drivers/radeon/LLVM_REVISION.txt
@@ -1 +1 @@
-@179684
+@180123

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Mesa (master): r600g/llvm: Use gprcount from llvm

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 2b9ed257c0c4db879970afb2c5981c59ca70c21b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b9ed257c0c4db879970afb2c5981c59ca70c21b

Author: Vincent Lejeune 
Date:   Sat Apr 13 16:36:02 2013 +0200

r600g/llvm: Use gprcount from llvm

---

 src/gallium/drivers/r600/r600_llvm.c |2 ++
 src/gallium/drivers/r600/r600_llvm.h |1 +
 src/gallium/drivers/r600/r600_shader.c   |2 +-
 src/gallium/drivers/radeon/LLVM_REVISION.txt |2 +-
 4 files changed, 5 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index e605e6b..35d6c90 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -555,6 +555,7 @@ unsigned r600_llvm_compile(
unsigned char ** inst_bytes,
unsigned * inst_byte_count,
enum radeon_family family,
+   unsigned *ngpr,
unsigned dump)
 {
unsigned r;
@@ -563,6 +564,7 @@ unsigned r600_llvm_compile(
r = radeon_llvm_compile(mod, &binary, gpu_family, dump);
*inst_bytes = binary.code;
*inst_byte_count = binary.code_size;
+   *ngpr = util_le32_to_cpu(*(uint32_t*)binary.config);
return r;
 }
 
diff --git a/src/gallium/drivers/r600/r600_llvm.h 
b/src/gallium/drivers/r600/r600_llvm.h
index b5e2af2..afc6881 100644
--- a/src/gallium/drivers/r600/r600_llvm.h
+++ b/src/gallium/drivers/r600/r600_llvm.h
@@ -20,6 +20,7 @@ unsigned r600_llvm_compile(
unsigned char ** inst_bytes,
unsigned * inst_byte_count,
enum radeon_family family,
+   unsigned *ngpr,
unsigned dump);
 
 #endif /* defined R600_USE_LLVM || defined HAVE_OPENCL */
diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 5ac8c09..465186d 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1461,7 +1461,7 @@ static int r600_shader_from_tgsi(struct r600_screen 
*rscreen,
mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
 
if (r600_llvm_compile(mod, &inst_bytes, &inst_byte_count,
- rscreen->family, dump)) {
+ rscreen->family, &ctx.bc->ngpr, dump)) {
FREE(inst_bytes);
radeon_llvm_dispose(&radeon_llvm_ctx);
use_llvm = 0;
diff --git a/src/gallium/drivers/radeon/LLVM_REVISION.txt 
b/src/gallium/drivers/radeon/LLVM_REVISION.txt
index 3ff0602..b633ea6 100644
--- a/src/gallium/drivers/radeon/LLVM_REVISION.txt
+++ b/src/gallium/drivers/radeon/LLVM_REVISION.txt
@@ -1 +1 @@
-@179546
+@179684

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Mesa (master): r600g/llvm: Add support for native isa for pre EG

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 5019af21453d0e9fc5b0f8c1c2bfeb29029882c1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5019af21453d0e9fc5b0f8c1c2bfeb29029882c1

Author: Vincent Lejeune 
Date:   Sat Apr  6 18:12:26 2013 +0200

r600g/llvm: Add support for native isa for pre EG

This fixes bug 62756 :
https://bugs.freedesktop.org/show_bug.cgi?id=62756#c12

---

 src/gallium/drivers/r600/r600_asm.c  |6 +-
 src/gallium/drivers/radeon/LLVM_REVISION.txt |2 +-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_asm.c 
b/src/gallium/drivers/r600/r600_asm.c
index a0dc1de..26a848a 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -1494,7 +1494,11 @@ static int r600_bytecode_cf_build(struct r600_bytecode 
*bc, struct r600_bytecode
const struct cf_op_info *cfop = r600_isa_cf(cf->op);
unsigned opcode = r600_isa_cf_opcode(bc->isa->hw_class, cf->op);
 
-   if (cfop->flags & CF_ALU) {
+
+   if (cf->op == CF_NATIVE) {
+   bc->bytecode[id++] = cf->isa[0];
+   bc->bytecode[id++] = cf->isa[1];
+   } else if (cfop->flags & CF_ALU) {
bc->bytecode[id++] = S_SQ_CF_ALU_WORD0_ADDR(cf->addr >> 1) |
S_SQ_CF_ALU_WORD0_KCACHE_MODE0(cf->kcache[0].mode) |
S_SQ_CF_ALU_WORD0_KCACHE_BANK0(cf->kcache[0].bank) |
diff --git a/src/gallium/drivers/radeon/LLVM_REVISION.txt 
b/src/gallium/drivers/radeon/LLVM_REVISION.txt
index dcce2fa..e26c652 100644
--- a/src/gallium/drivers/radeon/LLVM_REVISION.txt
+++ b/src/gallium/drivers/radeon/LLVM_REVISION.txt
@@ -1 +1 @@
-@178928
+@179020

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Mesa (master): r600g/llvm: Workaround for wrong tex.offset_*

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 92769612233dade9b7d45d5058dc86efc18d7710
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=92769612233dade9b7d45d5058dc86efc18d7710

Author: Vincent Lejeune 
Date:   Wed Apr  3 21:19:22 2013 +0200

r600g/llvm: Workaround for wrong tex.offset_*

---

 src/gallium/drivers/r600/r600_shader.c |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index d24d8e7..a5d224f 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -511,6 +511,9 @@ static unsigned r600_tex_from_byte_stream(struct 
r600_shader_ctx *ctx,
tex.src_sel_y = G_SQ_TEX_WORD2_SRC_SEL_Y(word2);
tex.src_sel_z = G_SQ_TEX_WORD2_SRC_SEL_Z(word2);
tex.src_sel_w = G_SQ_TEX_WORD2_SRC_SEL_W(word2);
+   tex.offset_x <<= 1;
+   tex.offset_y <<= 1;
+   tex.offset_z <<= 1;
 
tex.inst_mod = 0;
 

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Mesa (master): r600g/llvm: Do not override llvm provided stack_size

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 159d9340662a70df3dcc9da1681f5b0a8e7650cf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=159d9340662a70df3dcc9da1681f5b0a8e7650cf

Author: Vincent Lejeune 
Date:   Wed Apr  3 18:39:18 2013 +0200

r600g/llvm: Do not override llvm provided stack_size

---

 src/gallium/drivers/r600/r600_asm.c |3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_asm.c 
b/src/gallium/drivers/r600/r600_asm.c
index c88b48d..a0dc1de 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -1557,7 +1557,8 @@ int r600_bytecode_build(struct r600_bytecode *bc)
unsigned addr;
int i, r;
 
-   bc->nstack = bc->stack.max_entries;
+   if (!bc->nstack) // If not 0, Stack_size already provided by llvm
+   bc->nstack = bc->stack.max_entries;
 
if (bc->type == TGSI_PROCESSOR_VERTEX && !bc->nstack) {
bc->nstack = 1;

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Mesa (master): r600g/llvm: Do not change cf_alu inst when adding alus

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 097a6ecdfe592fdf2c5f3b48a17da6507eaa405c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=097a6ecdfe592fdf2c5f3b48a17da6507eaa405c

Author: Vincent Lejeune 
Date:   Tue Apr  2 19:19:24 2013 +0200

r600g/llvm: Do not change cf_alu inst when adding alus

---

 src/gallium/drivers/r600/r600_shader.c |9 ++---
 1 files changed, 2 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 82885d1..d24d8e7 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -399,12 +399,7 @@ static unsigned r600_alu_from_byte_stream(struct 
r600_shader_ctx *ctx,
return bytes_read;
}
 
-   if (alu.execute_mask) {
-   alu.pred_sel = 0;
-   r600_bytecode_add_alu_type(ctx->bc, &alu, 
CF_OP_ALU_PUSH_BEFORE);
-   } else {
-   r600_bytecode_add_alu(ctx->bc, &alu);
-   }
+   r600_bytecode_add_alu_type(ctx->bc, &alu, ctx->bc->cf_last->op);
 
/* XXX: Handle other KILL instructions */
if (alu_op->flags & AF_KILL) {
@@ -632,7 +627,7 @@ static void r600_bytecode_from_byte_stream(struct 
r600_shader_ctx *ctx,
int32_t word1 = i32_from_byte_stream(bytes, 
&bytes_read);
 
r600_bytecode_add_cf(ctx->bc);
-   ctx->bc->cf_last->op = 
r600_isa_cf_by_opcode(ctx->bc->isa, 8/* CF_ALU*/, 1);
+   ctx->bc->cf_last->op = 
r600_isa_cf_by_opcode(ctx->bc->isa, G_SQ_CF_ALU_WORD1_CF_INST(word1), 1);
ctx->bc->cf_last->kcache[0].bank = 
G_SQ_CF_ALU_WORD0_KCACHE_BANK0(word0);
ctx->bc->cf_last->kcache[0].addr = 
G_SQ_CF_ALU_WORD1_KCACHE_ADDR0(word1);
ctx->bc->cf_last->kcache[0].mode = 
G_SQ_CF_ALU_WORD0_KCACHE_MODE0(word0);

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Mesa (master): r600g/llvm: Update LLVM_REVISION.txt

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 50fd9c454495d15239b059236e17d29b57297dd4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=50fd9c454495d15239b059236e17d29b57297dd4

Author: Vincent Lejeune 
Date:   Mon Apr  1 23:50:20 2013 +0200

r600g/llvm: Update LLVM_REVISION.txt

---

 src/gallium/drivers/radeon/LLVM_REVISION.txt |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/radeon/LLVM_REVISION.txt 
b/src/gallium/drivers/radeon/LLVM_REVISION.txt
index 7376a67..3bcada5 100644
--- a/src/gallium/drivers/radeon/LLVM_REVISION.txt
+++ b/src/gallium/drivers/radeon/LLVM_REVISION.txt
@@ -1 +1 @@
-@178452
+@178505

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Mesa (master): r600g/llvm: Use stack_size provided from llvm.

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 8c8c4e3977e3126d8bb23d1e30e27d869e32c89f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8c8c4e3977e3126d8bb23d1e30e27d869e32c89f

Author: Vincent Lejeune 
Date:   Sat Mar 30 02:09:15 2013 +0100

r600g/llvm: Use stack_size provided from llvm.

---

 src/gallium/drivers/r600/r600_shader.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index c51773a..57cf17b 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -592,6 +592,7 @@ static void r600_bytecode_from_byte_stream(struct 
r600_shader_ctx *ctx,
unsigned char * bytes,  unsigned num_bytes)
 {
unsigned bytes_read = 0;
+   ctx->bc->nstack = bytes[bytes_read++];
unsigned i, byte;
while (bytes_read < num_bytes) {
char inst_type = bytes[bytes_read++];

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Mesa (master): r600g/llvm: uses function attribute to pass shader type

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 4ac0d85ca68100aaecb3016273f4df71f40e289b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4ac0d85ca68100aaecb3016273f4df71f40e289b

Author: Vincent Lejeune 
Date:   Sat Mar 30 20:05:45 2013 +0100

r600g/llvm: uses function attribute to pass shader type

---

 src/gallium/drivers/r600/r600_llvm.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index 6e6edb7..e3e7d9f 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -179,6 +179,7 @@ static void llvm_load_input(
 static void llvm_emit_prologue(struct lp_build_tgsi_context * bld_base)
 {
struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
+   radeon_llvm_shader_type(ctx->main_fn, ctx->type);
 
 }
 

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Mesa (master): r600g/llvm: Add support for cf_alu native encode

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: af38695f5105a2f766f3df393c3e42067c3706f2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=af38695f5105a2f766f3df393c3e42067c3706f2

Author: Vincent Lejeune 
Date:   Tue Mar 26 15:00:18 2013 +0100

r600g/llvm: Add support for cf_alu native encode

---

 src/gallium/drivers/r600/r600_asm.c|2 +-
 src/gallium/drivers/r600/r600_asm.h|1 +
 src/gallium/drivers/r600/r600_shader.c |   14 ++
 3 files changed, 16 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_asm.c 
b/src/gallium/drivers/r600/r600_asm.c
index 0d570ca..65c705d 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -106,7 +106,7 @@ void r600_bytecode_init(struct r600_bytecode *bc,
bc->msaa_texture_mode = msaa_texture_mode;
 }
 
-static int r600_bytecode_add_cf(struct r600_bytecode *bc)
+int r600_bytecode_add_cf(struct r600_bytecode *bc)
 {
struct r600_bytecode_cf *cf = r600_bytecode_cf();
 
diff --git a/src/gallium/drivers/r600/r600_asm.h 
b/src/gallium/drivers/r600/r600_asm.h
index 1465c31..c1aa3ba 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -227,6 +227,7 @@ int r600_bytecode_add_tex(struct r600_bytecode *bc,
 int r600_bytecode_add_output(struct r600_bytecode *bc,
const struct r600_bytecode_output *output);
 int r600_bytecode_build(struct r600_bytecode *bc);
+int r600_bytecode_add_cf(struct r600_bytecode *bc);
 int r600_bytecode_add_cfinst(struct r600_bytecode *bc,
unsigned op);
 int r600_bytecode_add_alu_type(struct r600_bytecode *bc,
diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 1e21559..c51773a 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -626,6 +626,20 @@ static void r600_bytecode_from_byte_stream(struct 
r600_shader_ctx *ctx,
 bytes_read = r600_export_from_byte_stream(ctx, bytes,
 bytes_read);
 break;
+   case 6: {
+   int32_t word0 = i32_from_byte_stream(bytes, 
&bytes_read);
+   int32_t word1 = i32_from_byte_stream(bytes, 
&bytes_read);
+
+   r600_bytecode_add_cf(ctx->bc);
+   ctx->bc->cf_last->op = 
r600_isa_cf_by_opcode(ctx->bc->isa, 8/* CF_ALU*/, 1);
+   ctx->bc->cf_last->kcache[0].bank = 
G_SQ_CF_ALU_WORD0_KCACHE_BANK0(word0);
+   ctx->bc->cf_last->kcache[0].addr = 
G_SQ_CF_ALU_WORD1_KCACHE_ADDR0(word1);
+   ctx->bc->cf_last->kcache[0].mode = 
G_SQ_CF_ALU_WORD0_KCACHE_MODE0(word0);
+   ctx->bc->cf_last->kcache[1].bank = 
G_SQ_CF_ALU_WORD0_KCACHE_BANK1(word0);
+   ctx->bc->cf_last->kcache[1].addr = 
G_SQ_CF_ALU_WORD1_KCACHE_ADDR1(word1);
+   ctx->bc->cf_last->kcache[1].mode = 
G_SQ_CF_ALU_WORD1_KCACHE_MODE1(word1);
+   break;
+  }
default:
/* XXX: Error here */
break;

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Mesa (master): r600g/llvm: Update LLVM_REVISION

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: c3fb34ee8dac62cc7418151a38309acd1fb2bd59
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c3fb34ee8dac62cc7418151a38309acd1fb2bd59

Author: Vincent Lejeune 
Date:   Sun Mar 31 21:37:20 2013 +0200

r600g/llvm: Update LLVM_REVISION

---

 src/gallium/drivers/radeon/LLVM_REVISION.txt |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/radeon/LLVM_REVISION.txt 
b/src/gallium/drivers/radeon/LLVM_REVISION.txt
index adcef56..7376a67 100644
--- a/src/gallium/drivers/radeon/LLVM_REVISION.txt
+++ b/src/gallium/drivers/radeon/LLVM_REVISION.txt
@@ -1 +1 @@
-r178024
+@178452

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Mesa (master): r600g/llvm: use native encode for tex

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 67a8ee7aaaef00ac2b2d513a1afc49fab6eeb3d3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=67a8ee7aaaef00ac2b2d513a1afc49fab6eeb3d3

Author: Vincent Lejeune 
Date:   Tue Mar 26 00:47:08 2013 +0100

r600g/llvm: use native encode for tex

---

 src/gallium/drivers/r600/r600_shader.c |   50 +--
 1 files changed, 27 insertions(+), 23 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 29facf7..1e21559 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -489,29 +489,33 @@ static unsigned r600_tex_from_byte_stream(struct 
r600_shader_ctx *ctx,
 {
struct r600_bytecode_tex tex;
 
-   tex.op = r600_isa_fetch_by_opcode(ctx->bc->isa, bytes[bytes_read++]);
-   tex.resource_id = bytes[bytes_read++];
-   tex.src_gpr = bytes[bytes_read++];
-   tex.src_rel = bytes[bytes_read++];
-   tex.dst_gpr = bytes[bytes_read++];
-   tex.dst_rel = bytes[bytes_read++];
-   tex.dst_sel_x = bytes[bytes_read++];
-   tex.dst_sel_y = bytes[bytes_read++];
-   tex.dst_sel_z = bytes[bytes_read++];
-   tex.dst_sel_w = bytes[bytes_read++];
-   tex.lod_bias = bytes[bytes_read++];
-   tex.coord_type_x = bytes[bytes_read++];
-   tex.coord_type_y = bytes[bytes_read++];
-   tex.coord_type_z = bytes[bytes_read++];
-   tex.coord_type_w = bytes[bytes_read++];
-   tex.offset_x = bytes[bytes_read++];
-   tex.offset_y = bytes[bytes_read++];
-   tex.offset_z = bytes[bytes_read++];
-   tex.sampler_id = bytes[bytes_read++];
-   tex.src_sel_x = bytes[bytes_read++];
-   tex.src_sel_y = bytes[bytes_read++];
-   tex.src_sel_z = bytes[bytes_read++];
-   tex.src_sel_w = bytes[bytes_read++];
+   uint32_t word0 = i32_from_byte_stream(bytes, &bytes_read);
+   uint32_t word1 = i32_from_byte_stream(bytes, &bytes_read);
+   uint32_t word2 = i32_from_byte_stream(bytes, &bytes_read);
+
+   tex.op = r600_isa_fetch_by_opcode(ctx->bc->isa, 
G_SQ_TEX_WORD0_TEX_INST(word0));
+   tex.resource_id = G_SQ_TEX_WORD0_RESOURCE_ID(word0);
+   tex.src_gpr = G_SQ_TEX_WORD0_SRC_GPR(word0);
+   tex.src_rel = G_SQ_TEX_WORD0_SRC_REL(word0);
+   tex.dst_gpr = G_SQ_TEX_WORD1_DST_GPR(word1);
+   tex.dst_rel = G_SQ_TEX_WORD1_DST_REL(word1);
+   tex.dst_sel_x = G_SQ_TEX_WORD1_DST_SEL_X(word1);
+   tex.dst_sel_y = G_SQ_TEX_WORD1_DST_SEL_Y(word1);
+   tex.dst_sel_z = G_SQ_TEX_WORD1_DST_SEL_Z(word1);
+   tex.dst_sel_w = G_SQ_TEX_WORD1_DST_SEL_W(word1);
+   tex.lod_bias = G_SQ_TEX_WORD1_LOD_BIAS(word1);
+   tex.coord_type_x = G_SQ_TEX_WORD1_COORD_TYPE_X(word1);
+   tex.coord_type_y = G_SQ_TEX_WORD1_COORD_TYPE_Y(word1);
+   tex.coord_type_z = G_SQ_TEX_WORD1_COORD_TYPE_Z(word1);
+   tex.coord_type_w = G_SQ_TEX_WORD1_COORD_TYPE_W(word1);
+   tex.offset_x = G_SQ_TEX_WORD2_OFFSET_X(word2);
+   tex.offset_y = G_SQ_TEX_WORD2_OFFSET_Y(word2);
+   tex.offset_z = G_SQ_TEX_WORD2_OFFSET_Z(word2);
+   tex.sampler_id = G_SQ_TEX_WORD2_SAMPLER_ID(word2);
+   tex.src_sel_x = G_SQ_TEX_WORD2_SRC_SEL_X(word2);
+   tex.src_sel_y = G_SQ_TEX_WORD2_SRC_SEL_Y(word2);
+   tex.src_sel_z = G_SQ_TEX_WORD2_SRC_SEL_Z(word2);
+   tex.src_sel_w = G_SQ_TEX_WORD2_SRC_SEL_W(word2);
 
tex.inst_mod = 0;
 

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Mesa (master): r600g: Check comp_mask before merging export instructions

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 83e7d111afd8d340ce8fe13ea139271400eb362e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=83e7d111afd8d340ce8fe13ea139271400eb362e

Author: Vincent Lejeune 
Date:   Sun Mar  3 21:35:38 2013 +0100

r600g: Check comp_mask before merging export instructions

Fixes a llvm uncovered (rare) bug where consecutive exports were
merged even if they have incompatible mask.

---

 src/gallium/drivers/r600/r600_asm.c |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_asm.c 
b/src/gallium/drivers/r600/r600_asm.c
index b5a29cb..cb3e7a6 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -145,6 +145,7 @@ int r600_bytecode_add_output(struct r600_bytecode *bc,
output->swizzle_y == bc->cf_last->output.swizzle_y &&
output->swizzle_z == bc->cf_last->output.swizzle_z &&
output->swizzle_w == bc->cf_last->output.swizzle_w &&
+   output->comp_mask == bc->cf_last->output.comp_mask &&
(output->burst_count + bc->cf_last->output.burst_count) <= 16) {
 
if ((output->gpr + output->burst_count) == 
bc->cf_last->output.gpr &&

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Mesa (master): r600g: fix check_and_set_bank_swizzle for cayman

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 138b5b9a12b7e1537494aac556589ac9981b557b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=138b5b9a12b7e1537494aac556589ac9981b557b

Author: Vadim Girlin 
Date:   Tue Feb 26 20:50:25 2013 +0400

r600g: fix check_and_set_bank_swizzle for cayman

Tested-by: Vincent Lejeune 
Reviewed-by: Vincent Lejeune 

---

 src/gallium/drivers/r600/r600_asm.c |   10 +++---
 1 files changed, 3 insertions(+), 7 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_asm.c 
b/src/gallium/drivers/r600/r600_asm.c
index 3632aa5..b5a29cb 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -475,12 +475,6 @@ static int check_and_set_bank_swizzle(struct r600_bytecode 
*bc,
bank_swizzle[4] = SQ_ALU_SCL_210;
while(bank_swizzle[4] <= SQ_ALU_SCL_221) {
 
-   if (max_slots == 4) {
-   for (i = 0; i < max_slots; i++) {
-   if (bank_swizzle[i] == SQ_ALU_VEC_210)
- return -1;
-   }
-   }
init_bank_swizzle(&bs);
if (scalar_only == false) {
for (i = 0; i < 4; i++) {
@@ -512,8 +506,10 @@ static int check_and_set_bank_swizzle(struct r600_bytecode 
*bc,
bank_swizzle[i]++;
if (bank_swizzle[i] <= SQ_ALU_VEC_210)
break;
-   else
+   else if (i < max_slots - 1)
bank_swizzle[i] = 
SQ_ALU_VEC_012;
+   else
+   return -1;
}
}
}

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Mesa (master): r600g/llvm: Support for TBO

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 0527317e1f89ce6cb7ba4193a9196c880d223e59
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0527317e1f89ce6cb7ba4193a9196c880d223e59

Author: Vincent Lejeune 
Date:   Thu Feb 14 17:26:30 2013 +0100

r600g/llvm: Support for TBO

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/r600/r600_llvm.c |   28 
 1 files changed, 28 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index 59047e7..aee7cea 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -412,6 +412,34 @@ static void llvm_emit_tex(
LLVMValueRef args[6];
unsigned c, sampler_src;
 
+   if (emit_data->inst->Texture.Texture == TGSI_TEXTURE_BUFFER) {
+   switch (emit_data->inst->Instruction.Opcode) {
+   case TGSI_OPCODE_TXQ: {
+   LLVMValueRef offset[2] = {
+   
LLVMConstInt(LLVMInt64TypeInContext(bld_base->base.gallivm->context), 0, false),
+   lp_build_const_int32(bld_base->base.gallivm, 1)
+   };
+   LLVMTypeRef const_ptr_type = 
LLVMPointerType(LLVMArrayType(LLVMVectorType(bld_base->base.elem_type, 4), 
1024),
+   
R600_BUFFER_INFO_CONST_BUFFER);
+   LLVMValueRef const_ptr = 
LLVMBuildIntToPtr(bld_base->base.gallivm->builder, 
lp_build_const_int32(bld_base->base.gallivm, 0), const_ptr_type, "");
+   LLVMValueRef ptr = 
LLVMBuildGEP(bld_base->base.gallivm->builder, const_ptr, offset, 2, "");
+   LLVMValueRef cvecval = 
LLVMBuildLoad(bld_base->base.gallivm->builder, ptr, "");
+   emit_data->output[0] = cvecval;
+   return;
+   }
+   case TGSI_OPCODE_TXF: {
+   args[0] = LLVMBuildExtractElement(gallivm->builder, 
emit_data->args[0], lp_build_const_int32(gallivm, 0), "");
+   args[1] = lp_build_const_int32(gallivm, 
R600_MAX_CONST_BUFFERS);
+   emit_data->output[0] = build_intrinsic(gallivm->builder,
+   "llvm.R600.load.texbuf",
+   emit_data->dst_type, 
args, 2, LLVMReadNoneAttribute);
+   }
+   return;
+   default:
+   break;
+   }
+   }
+
assert(emit_data->arg_count + 2 <= Elements(args));
 
for (c = 0; c < emit_data->arg_count; ++c)

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Mesa (master): r600g/llvm: Set Inputs/Outputs count to 32 ( api reported value)

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: c116598f863db2e580ccb7c7a0613f2541cc0fea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c116598f863db2e580ccb7c7a0613f2541cc0fea

Author: Vincent Lejeune 
Date:   Wed Feb 13 20:20:04 2013 +0100

r600g/llvm: Set Inputs/Outputs count to 32 (api reported value)

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/radeon/radeon_llvm.h |4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_llvm.h 
b/src/gallium/drivers/radeon/radeon_llvm.h
index bfeacb5..b1e025b 100644
--- a/src/gallium/drivers/radeon/radeon_llvm.h
+++ b/src/gallium/drivers/radeon/radeon_llvm.h
@@ -31,8 +31,8 @@
 #include "gallivm/lp_bld_init.h"
 #include "gallivm/lp_bld_tgsi.h"
 
-#define RADEON_LLVM_MAX_INPUTS 16 * 4
-#define RADEON_LLVM_MAX_OUTPUTS 16 * 4
+#define RADEON_LLVM_MAX_INPUTS 32 * 4
+#define RADEON_LLVM_MAX_OUTPUTS 32 * 4
 #define RADEON_LLVM_MAX_BRANCH_DEPTH 16
 #define RADEON_LLVM_MAX_LOOP_DEPTH 16
 

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Mesa (master): r600g/llvm: Fix alpha_to_one piglit tests

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 90e6f47ac8c8fdbfd097ef099895cd2ae005eb55
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=90e6f47ac8c8fdbfd097ef099895cd2ae005eb55

Author: Vincent Lejeune 
Date:   Wed Feb 13 18:49:30 2013 +0100

r600g/llvm: Fix alpha_to_one piglit tests

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/r600/r600_llvm.c |2 ++
 src/gallium/drivers/r600/r600_shader.c   |1 +
 src/gallium/drivers/radeon/radeon_llvm.h |1 +
 3 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index 7a41688..59047e7 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -234,6 +234,8 @@ static void llvm_emit_epilogue(struct lp_build_tgsi_context 
* bld_base)
elements[chan] = LLVMBuildLoad(base->gallivm->builder,
ctx->soa.outputs[i][chan], "");
}
+   if (ctx->alpha_to_one && ctx->type == TGSI_PROCESSOR_FRAGMENT 
&& ctx->r600_outputs[i].name == TGSI_SEMANTIC_COLOR)
+   elements[3] = lp_build_const_float(base->gallivm, 1.0f);
LLVMValueRef output = lp_build_gather_values(base->gallivm, 
elements, 4);
 
if (ctx->type == TGSI_PROCESSOR_VERTEX) {
diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 59a7f92..8642463 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1428,6 +1428,7 @@ static int r600_shader_from_tgsi(struct r600_screen 
*rscreen,
radeon_llvm_ctx.fs_color_all = shader->fs_write_all && 
(rscreen->chip_class >= EVERGREEN);
radeon_llvm_ctx.stream_outputs = &so;
radeon_llvm_ctx.clip_vertex = ctx.cv_output;
+   radeon_llvm_ctx.alpha_to_one = key.alpha_to_one;
mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE)) {
dump = 1;
diff --git a/src/gallium/drivers/radeon/radeon_llvm.h 
b/src/gallium/drivers/radeon/radeon_llvm.h
index 21360e2..bfeacb5 100644
--- a/src/gallium/drivers/radeon/radeon_llvm.h
+++ b/src/gallium/drivers/radeon/radeon_llvm.h
@@ -64,6 +64,7 @@ struct radeon_llvm_context {
struct pipe_stream_output_info *stream_outputs;
unsigned color_buffer_count;
unsigned fs_color_all;
+   unsigned alpha_to_one;
 
/*=== Front end configuration ===*/
 

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Mesa (master): r600g/llvm: Add support for UBO

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: ef8fde6acbc575487388389b3af5eab18eae4537
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ef8fde6acbc575487388389b3af5eab18eae4537

Author: Vincent Lejeune 
Date:   Tue Feb 12 18:44:13 2013 +0100

r600g/llvm: Add support for UBO

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/r600/r600_llvm.c   |6 +-
 .../drivers/radeon/radeon_setup_tgsi_llvm.c|   17 +
 2 files changed, 22 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index fa66fcc..7a41688 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -38,8 +38,12 @@ static LLVMValueRef llvm_fetch_const(
LLVMValueRef index = 
LLVMBuildLoad(bld_base->base.gallivm->builder, 
bld->addr[reg->Indirect.Index][reg->Indirect.SwizzleX], "");
offset[1] = LLVMBuildAdd(bld_base->base.gallivm->builder, 
offset[1], index, "");
}
+   unsigned ConstantAddressSpace = CONSTANT_BUFFER_0_ADDR_SPACE ;
+   if (reg->Register.Dimension) {
+   ConstantAddressSpace += reg->Dimension.Index;
+   }
LLVMTypeRef const_ptr_type = 
LLVMPointerType(LLVMArrayType(LLVMVectorType(bld_base->base.elem_type, 4), 
1024),
-   
CONSTANT_BUFFER_0_ADDR_SPACE);
+   ConstantAddressSpace);
LLVMValueRef const_ptr = 
LLVMBuildIntToPtr(bld_base->base.gallivm->builder, 
lp_build_const_int32(bld_base->base.gallivm, 0), const_ptr_type, "");
LLVMValueRef ptr = LLVMBuildGEP(bld_base->base.gallivm->builder, 
const_ptr, offset, 2, "");
LLVMValueRef cvecval = LLVMBuildLoad(bld_base->base.gallivm->builder, 
ptr, "");
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c 
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 0f90991..8902ae4 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -766,6 +766,22 @@ static void emit_icmp(
emit_data->output[emit_data->chan] = v;
 }
 
+static void emit_ucmp(
+   const struct lp_build_tgsi_action * action,
+   struct lp_build_tgsi_context * bld_base,
+   struct lp_build_emit_data * emit_data)
+{
+   unsigned pred;
+   LLVMBuilderRef builder = bld_base->base.gallivm->builder;
+   LLVMContextRef context = bld_base->base.gallivm->context;
+
+
+   LLVMValueRef v = LLVMBuildFCmp(builder, LLVMRealUGE,
+   emit_data->args[0], 
lp_build_const_float(bld_base->base.gallivm, 0.), "");
+
+   emit_data->output[emit_data->chan] = LLVMBuildSelect(builder, v, 
emit_data->args[2], emit_data->args[1], "");
+}
+
 static void emit_cmp(
const struct lp_build_tgsi_action *action,
struct lp_build_tgsi_context * bld_base,
@@ -1241,6 +1257,7 @@ void radeon_llvm_context_init(struct radeon_llvm_context 
* ctx)
bld_base->op_actions[TGSI_OPCODE_USNE].emit = emit_icmp;
bld_base->op_actions[TGSI_OPCODE_U2F].emit = emit_u2f;
bld_base->op_actions[TGSI_OPCODE_XOR].emit = emit_xor;
+   bld_base->op_actions[TGSI_OPCODE_UCMP].emit = emit_ucmp;
 
bld_base->rsq_action.emit = build_tgsi_intrinsic_nomem;
bld_base->rsq_action.intr_name = "llvm.AMDGPU.rsq";

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Mesa (master): r600g/llvm: Fixes addressspace of basevectors for clipvertex

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: f9f5c92f734c517c1bd486f5a3b1931ea6f871a5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9f5c92f734c517c1bd486f5a3b1931ea6f871a5

Author: Vincent Lejeune 
Date:   Sat Jan 19 22:27:16 2013 +0100

r600g/llvm: Fixes addressspace of basevectors for clipvertex

---

 src/gallium/drivers/r600/r600_llvm.c |3 ++-
 1 files changed, 2 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index 0f0eb84..276ef5f 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -21,6 +21,7 @@
 #if defined R600_USE_LLVM || defined HAVE_OPENCL
 
 #define CONSTANT_BUFFER_0_ADDR_SPACE 9
+#define CONSTANT_BUFFER_1_ADDR_SPACE (CONSTANT_BUFFER_0_ADDR_SPACE + 
R600_UCP_CONST_BUFFER)
 
 static LLVMValueRef llvm_fetch_const(
struct lp_build_tgsi_context * bld_base,
@@ -316,7 +317,7 @@ static void llvm_emit_epilogue(struct lp_build_tgsi_context 
* bld_base)

LLVMConstInt(LLVMInt64TypeInContext(bld_base->base.gallivm->context), 0, false),

lp_build_const_int32(bld_base->base.gallivm, reg_index * 4 + chan)
};
-   LLVMTypeRef const_ptr_type = 
LLVMPointerType(LLVMArrayType(LLVMVectorType(bld_base->base.elem_type, 4), 
1024), 9);
+   LLVMTypeRef const_ptr_type = 
LLVMPointerType(LLVMArrayType(LLVMVectorType(bld_base->base.elem_type, 4), 
1024), CONSTANT_BUFFER_1_ADDR_SPACE);
LLVMValueRef const_ptr = 
LLVMBuildIntToPtr(bld_base->base.gallivm->builder, 
lp_build_const_int32(bld_base->base.gallivm, 0), const_ptr_type, "");
LLVMValueRef ptr = 
LLVMBuildGEP(bld_base->base.gallivm->builder, const_ptr, offset, 2, "");
LLVMValueRef base_vector = 
LLVMBuildLoad(bld_base->base.gallivm->builder, ptr, "");

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Mesa (master): r600g: use default action for min/max opcode in tgsi to llvm

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 00d77e9fe49924e39e211e1890c083847498a9a0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=00d77e9fe49924e39e211e1890c083847498a9a0

Author: Vincent Lejeune 
Date:   Thu Nov 29 23:46:15 2012 +0100

r600g: use default action for min/max opcode in tgsi to llvm

Reveiwed-by: Tom Stellard 

---

 .../drivers/radeon/radeon_setup_tgsi_llvm.c|4 
 1 files changed, 0 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c 
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 2521582..9cb0e9a 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -1120,11 +1120,7 @@ void radeon_llvm_context_init(struct radeon_llvm_context 
* ctx)
bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32";
bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp";
-   bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
-   bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.AMDIL.max.";
bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod;
-   bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
-   bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.AMDIL.min.";
bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not;
bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or;
bld_base->op_actions[TGSI_OPCODE_POW].emit = 
build_tgsi_intrinsic_readonly;

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Mesa (master): gallivm: Have a default emit function for min/max opcode

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 2d97f77b9f4ea58afe19f93dfc7ac7ed96819669
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2d97f77b9f4ea58afe19f93dfc7ac7ed96819669

Author: Vincent Lejeune 
Date:   Thu Nov 29 23:43:31 2012 +0100

gallivm: Have a default emit function for min/max opcode

Reveiwed-by: Tom Stellard 

---

 src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c |   29 
 1 files changed, 29 insertions(+), 0 deletions(-)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c 
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
index cd57fae..cc4bd2e 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
@@ -744,6 +744,32 @@ umul_emit(
emit_data->args[0], emit_data->args[1]);
 }
 
+/* TGSI_OPCODE_MAX */
+static void fmax_emit(
+   const struct lp_build_tgsi_action * action,
+   struct lp_build_tgsi_context * bld_base,
+   struct lp_build_emit_data * emit_data)
+{
+   LLVMBuilderRef builder = bld_base->base.gallivm->builder;
+   emit_data->output[emit_data->chan] = LLVMBuildSelect(builder,
+   LLVMBuildFCmp(builder, LLVMRealUGE,
+   emit_data->args[0], emit_data->args[1], ""),
+   emit_data->args[0], emit_data->args[1], "");
+}
+
+/* TGSI_OPCODE_MIN */
+static void fmin_emit(
+   const struct lp_build_tgsi_action * action,
+   struct lp_build_tgsi_context * bld_base,
+   struct lp_build_emit_data * emit_data)
+{
+   LLVMBuilderRef builder = bld_base->base.gallivm->builder;
+   emit_data->output[emit_data->chan] = LLVMBuildSelect(builder,
+   LLVMBuildFCmp(builder, LLVMRealUGE,
+   emit_data->args[0], emit_data->args[1], ""),
+   emit_data->args[1], emit_data->args[0], "");
+}
+
 /* TGSI_OPCODE_XPD */
 
 static void
@@ -844,6 +870,9 @@ lp_set_default_actions(struct lp_build_tgsi_context * 
bld_base)
bld_base->op_actions[TGSI_OPCODE_U2F].emit = u2f_emit;
bld_base->op_actions[TGSI_OPCODE_UMAD].emit = umad_emit;
bld_base->op_actions[TGSI_OPCODE_UMUL].emit = umul_emit;
+
+   bld_base->op_actions[TGSI_OPCODE_MAX].emit = fmax_emit;
+   bld_base->op_actions[TGSI_OPCODE_MIN].emit = fmin_emit;
 }
 
 /* CPU Only default actions */

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Mesa (master): r600g: use default action for fdiv/rcp opcode

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 2a03f28e5489d6eb841e70dcf7521e3f275a0159
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a03f28e5489d6eb841e70dcf7521e3f275a0159

Author: Vincent Lejeune 
Date:   Thu Nov 29 23:45:30 2012 +0100

r600g: use default action for fdiv/rcp opcode

Reveiwed-by: Tom Stellard 

---

 .../drivers/radeon/radeon_setup_tgsi_llvm.c|7 +--
 1 files changed, 1 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c 
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 00c068d..2521582 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -540,8 +540,7 @@ static void emit_prepare_cube_coords(
 
coords[2] = build_intrinsic(builder, "fabs",
type, &coords[2], 1, LLVMReadNoneAttribute);
-   coords[2] = build_intrinsic(builder, "llvm.AMDGPU.rcp",
-   type, &coords[2], 1, LLVMReadNoneAttribute);
+   coords[2] = lp_build_emit_llvm_unary(bld_base, TGSI_OPCODE_RCP, 
coords[2]);
 
mad_args[1] = coords[2];
mad_args[2] = LLVMConstReal(type, 1.5);
@@ -1088,8 +1087,6 @@ void radeon_llvm_context_init(struct radeon_llvm_context 
* ctx)
bld_base->op_actions[TGSI_OPCODE_DDX].fetch_args = tex_fetch_args;
bld_base->op_actions[TGSI_OPCODE_DDY].intr_name = "llvm.AMDGPU.ddy";
bld_base->op_actions[TGSI_OPCODE_DDY].fetch_args = tex_fetch_args;
-   bld_base->op_actions[TGSI_OPCODE_DIV].emit = build_tgsi_intrinsic_nomem;
-   bld_base->op_actions[TGSI_OPCODE_DIV].intr_name = "llvm.AMDGPU.div";
bld_base->op_actions[TGSI_OPCODE_ELSE].emit = else_emit;
bld_base->op_actions[TGSI_OPCODE_ENDIF].emit = endif_emit;
bld_base->op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit;
@@ -1132,8 +1129,6 @@ void radeon_llvm_context_init(struct radeon_llvm_context 
* ctx)
bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or;
bld_base->op_actions[TGSI_OPCODE_POW].emit = 
build_tgsi_intrinsic_readonly;
bld_base->op_actions[TGSI_OPCODE_POW].intr_name = "llvm.pow.f32";
-   bld_base->op_actions[TGSI_OPCODE_RCP].emit = build_tgsi_intrinsic_nomem;
-   bld_base->op_actions[TGSI_OPCODE_RCP].intr_name = "llvm.AMDGPU.rcp";
bld_base->op_actions[TGSI_OPCODE_ROUND].emit = 
build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_ROUND].intr_name = 
"llvm.AMDIL.round.nearest.";
bld_base->op_actions[TGSI_OPCODE_SGE].emit = emit_cmp;

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Mesa (master): gallivm: have a default emit function for fdiv/rcp

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 0a2f58f6ed3f4db98c1826e5e5be3159815042f6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a2f58f6ed3f4db98c1826e5e5be3159815042f6

Author: Vincent Lejeune 
Date:   Thu Nov 29 23:43:05 2012 +0100

gallivm: have a default emit function for fdiv/rcp

Reveiwed-by: Tom Stellard 

---

 src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c |   25 
 1 files changed, 25 insertions(+), 0 deletions(-)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c 
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
index 17f288f..cd57fae 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_action.c
@@ -584,6 +584,29 @@ mul_emit(
emit_data->args[0], emit_data->args[1]);
 }
 
+/*.TGSI_OPCODE_DIV.*/
+static void fdiv_emit(
+   const struct lp_build_tgsi_action * action,
+   struct lp_build_tgsi_context * bld_base,
+   struct lp_build_emit_data * emit_data)
+{
+   emit_data->output[emit_data->chan] = LLVMBuildFDiv(
+   bld_base->base.gallivm->builder,
+   emit_data->args[0], emit_data->args[1], "");
+}
+
+/*.TGSI_OPCODE_RCP.*/
+static void rcp_emit(
+   const struct lp_build_tgsi_action * action,
+   struct lp_build_tgsi_context * bld_base,
+   struct lp_build_emit_data * emit_data)
+{
+   LLVMValueRef one;
+   one = lp_build_const_float(bld_base->base.gallivm, 1.0f);
+   emit_data->output[emit_data->chan] = lp_build_emit_llvm_binary(bld_base,
+   TGSI_OPCODE_DIV, one, emit_data->args[0]);
+}
+
 /* TGSI_OPCODE_POW */
 
 static void
@@ -811,6 +834,8 @@ lp_set_default_actions(struct lp_build_tgsi_context * 
bld_base)
bld_base->op_actions[TGSI_OPCODE_MAD].emit = mad_emit;
bld_base->op_actions[TGSI_OPCODE_MOV].emit = mov_emit;
bld_base->op_actions[TGSI_OPCODE_MUL].emit = mul_emit;
+   bld_base->op_actions[TGSI_OPCODE_DIV].emit = fdiv_emit;
+   bld_base->op_actions[TGSI_OPCODE_RCP].emit = rcp_emit;
bld_base->op_actions[TGSI_OPCODE_SFL].emit = sfl_emit;
bld_base->op_actions[TGSI_OPCODE_STR].emit = str_emit;
bld_base->op_actions[TGSI_OPCODE_SUB].emit = sub_emit;

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Mesa (master): r600g: Use default mul/mad function for tgsi-to-llvm

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 0ad1fefd6951aa47ab58a41dc9ee73083cbcf85c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0ad1fefd6951aa47ab58a41dc9ee73083cbcf85c

Author: Vincent Lejeune 
Date:   Wed Nov 28 00:35:55 2012 +0100

r600g: Use default mul/mad function for tgsi-to-llvm

Reveiwed-by: Tom Stellard 

---

 .../drivers/radeon/radeon_setup_tgsi_llvm.c|   12 
 1 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c 
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 5e3d6c2..00c068d 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -547,12 +547,12 @@ static void emit_prepare_cube_coords(
mad_args[2] = LLVMConstReal(type, 1.5);
 
mad_args[0] = coords[0];
-   coords[0] = build_intrinsic(builder, "llvm.AMDIL.mad.",
-   type, mad_args, 3, LLVMReadNoneAttribute);
+   coords[0] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
+   mad_args[0], mad_args[1], mad_args[2]);
 
mad_args[0] = coords[1];
-   coords[1] = build_intrinsic(builder, "llvm.AMDIL.mad.",
-   type, mad_args, 3, LLVMReadNoneAttribute);
+   coords[1] = lp_build_emit_llvm_ternary(bld_base, TGSI_OPCODE_MAD,
+   mad_args[0], mad_args[1], mad_args[2]);
 
/* apply yxwy swizzle to cooords */
coords[2] = coords[3];
@@ -1123,15 +1123,11 @@ void radeon_llvm_context_init(struct 
radeon_llvm_context * ctx)
bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32";
bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp";
-   bld_base->op_actions[TGSI_OPCODE_MAD].emit = build_tgsi_intrinsic_nomem;
-   bld_base->op_actions[TGSI_OPCODE_MAD].intr_name = "llvm.AMDIL.mad.";
bld_base->op_actions[TGSI_OPCODE_MAX].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_MAX].intr_name = "llvm.AMDIL.max.";
bld_base->op_actions[TGSI_OPCODE_MOD].emit = emit_mod;
bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_MIN].intr_name = "llvm.AMDIL.min.";
-   bld_base->op_actions[TGSI_OPCODE_MUL].emit = build_tgsi_intrinsic_nomem;
-   bld_base->op_actions[TGSI_OPCODE_MUL].intr_name = "llvm.AMDGPU.mul";
bld_base->op_actions[TGSI_OPCODE_NOT].emit = emit_not;
bld_base->op_actions[TGSI_OPCODE_OR].emit = emit_or;
bld_base->op_actions[TGSI_OPCODE_POW].emit = 
build_tgsi_intrinsic_readonly;

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Mesa (master): glsl: add new variable declaration in function body in lower_output_read

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: e9f090e8b2ca2eda3e9a1b1c3ba4acce843720ba
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9f090e8b2ca2eda3e9a1b1c3ba4acce843720ba

Author: Vincent Lejeune 
Date:   Fri Nov 23 17:53:06 2012 +0100

glsl: add new variable declaration in function body in lower_output_read

Reviewed-by: Kenneth Graunke 

---

 src/glsl/lower_output_reads.cpp |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/glsl/lower_output_reads.cpp b/src/glsl/lower_output_reads.cpp
index 90d71b0..a6192a5 100644
--- a/src/glsl/lower_output_reads.cpp
+++ b/src/glsl/lower_output_reads.cpp
@@ -97,6 +97,7 @@ output_read_remover::visit(ir_dereference_variable *ir)
   temp = new(var_ctx) ir_variable(ir->var->type, ir->var->name,
   ir_var_temporary);
   hash_table_insert(replacements, temp, ir->var);
+  ir->var->insert_after(temp);
}
 
/* Update the dereference to use the temporary */

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Mesa (master): r600g: mirror simplification of if/break opcodes

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 3fcb3fbf22063cabfec04700dcf5aa4a2f30760f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3fcb3fbf22063cabfec04700dcf5aa4a2f30760f

Author: Vincent Lejeune 
Date:   Wed Nov 28 19:59:07 2012 +0100

r600g: mirror simplification of if/break opcodes

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/r600/r600_shader.c |   44 ---
 1 files changed, 12 insertions(+), 32 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 84821ac..72cb585 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -361,16 +361,14 @@ static unsigned r600_alu_from_byte_stream(struct 
r600_shader_ctx *ctx,
return bytes_read;
 }
 
-static void llvm_if(struct r600_shader_ctx *ctx, struct r600_bytecode_alu * 
alu,
-   unsigned pred_inst)
+static void llvm_if(struct r600_shader_ctx *ctx)
 {
r600_bytecode_add_cfinst(ctx->bc, 
CTX_INST(V_SQ_CF_WORD1_SQ_CF_INST_JUMP));
fc_pushlevel(ctx, FC_IF);
callstack_check_depth(ctx, FC_PUSH_VPM, 0);
 }
 
-static void r600_break_from_byte_stream(struct r600_shader_ctx *ctx,
-   struct r600_bytecode_alu *alu, unsigned compare_opcode)
+static void r600_break_from_byte_stream(struct r600_shader_ctx *ctx)
 {
unsigned opcode = TGSI_OPCODE_BRK;
if (ctx->bc->chip_class == CAYMAN)
@@ -379,7 +377,7 @@ static void r600_break_from_byte_stream(struct 
r600_shader_ctx *ctx,
ctx->inst_info = &eg_shader_tgsi_instruction[opcode];
else
ctx->inst_info = &r600_shader_tgsi_instruction[opcode];
-   llvm_if(ctx, alu, compare_opcode);
+   llvm_if(ctx);
tgsi_loop_brk_cont(ctx);
tgsi_endif(ctx);
 }
@@ -393,35 +391,25 @@ static unsigned r600_fc_from_byte_stream(struct 
r600_shader_ctx *ctx,
bytes_read = r600_src_from_byte_stream(bytes, bytes_read, &alu, 0);
inst = bytes[bytes_read++];
switch (inst) {
-   case 0: /* FC_IF */
-   llvm_if(ctx, &alu,
-   CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
+   case 0: /* IF_PREDICATED */
+   llvm_if(ctx);
break;
-   case 1: /* FC_IF_INT */
-   llvm_if(ctx, &alu,
-   
CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT));
-   break;
-   case 2: /* FC_ELSE */
+   case 1: /* ELSE */
tgsi_else(ctx);
break;
-   case 3: /* FC_ENDIF */
+   case 2: /* ENDIF */
tgsi_endif(ctx);
break;
-   case 4: /* FC_BGNLOOP */
+   case 3: /* BGNLOOP */
tgsi_bgnloop(ctx);
break;
-   case 5: /* FC_ENDLOOP */
+   case 4: /* ENDLOOP */
tgsi_endloop(ctx);
break;
-   case 6: /* FC_BREAK */
-   r600_break_from_byte_stream(ctx, &alu,
-   CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT));
-   break;
-   case 7: /* FC_BREAK_NZ_INT */
-   r600_break_from_byte_stream(ctx, &alu,
-   
CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE_INT));
+   case 5: /* PREDICATED_BREAK */
+   r600_break_from_byte_stream(ctx);
break;
-   case 8: /* FC_CONTINUE */
+   case 6: /* CONTINUE */
{
unsigned opcode = TGSI_OPCODE_CONT;
if (ctx->bc->chip_class == CAYMAN) {
@@ -437,14 +425,6 @@ static unsigned r600_fc_from_byte_stream(struct 
r600_shader_ctx *ctx,
tgsi_loop_brk_cont(ctx);
}
break;
-   case 9: /* FC_BREAK_Z_INT */
-   r600_break_from_byte_stream(ctx, &alu,
-   CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETE_INT));
-   break;
-   case 10: /* FC_BREAK_NZ */
-   r600_break_from_byte_stream(ctx, &alu,
-   CTX_INST(V_SQ_ALU_WORD1_OP2_SQ_OP2_INST_PRED_SETNE));
-   break;
}
 
return bytes_read;

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Mesa (master): r600g: separate resource_id and sampler_id tex info in tgsi-to-llvm

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 5fda2990aa1a52a11a87eeb5ccf914588e0afe21
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5fda2990aa1a52a11a87eeb5ccf914588e0afe21

Author: Vincent Lejeune 
Date:   Tue Nov 20 23:22:47 2012 +0100

r600g: separate resource_id and sampler_id tex info in tgsi-to-llvm

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/r600/r600_llvm.c |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index b3d4e6b..8f1ed26 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -11,6 +11,7 @@
 #include "r600_asm.h"
 #include "r600_opcodes.h"
 #include "r600_shader.h"
+#include "r600_pipe.h"
 #include "radeon_llvm.h"
 #include "radeon_llvm_emit.h"
 
@@ -325,6 +326,8 @@ static void llvm_emit_tex(
sampler_src = emit_data->inst->Instruction.NumSrcRegs-1;
 
args[c++] = lp_build_const_int32(gallivm,
+   
emit_data->inst->Src[sampler_src].Register.Index + R600_MAX_CONST_BUFFERS);
+   args[c++] = lp_build_const_int32(gallivm,

emit_data->inst->Src[sampler_src].Register.Index);
args[c++] = lp_build_const_int32(gallivm,
emit_data->inst->Texture.Texture);

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Mesa (master): glsl: store read vector in a temp in vec_index_to_cond

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 557d4918adf4cb99c4410af3bdf51c5eb3fc1d17
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=557d4918adf4cb99c4410af3bdf51c5eb3fc1d17

Author: Vincent Lejeune 
Date:   Sun Nov  4 23:04:30 2012 +0100

glsl: store read vector in a temp in vec_index_to_cond

Vector indexing on matrixes generates several copy of the
constant matrix, for instance vec=mat4[i][j] generates :
vec=mat4[i].x;
vec=(j==1)?mat4[i].y;
vec=(j==2)?mat4[i].z;
vec=(j==3)?mat4[i].w;
In the case of constant matrixes, the mat4[i] expression generates
copy of the 16 elements of the matrix 4 times ; indirect addressing
also prevents some conservative CSE algorithms (like the one in LLVM)
from factoring the mat4[i] expression.
This patch will make the vec_index_to_cond pass generates :
temp = mat4[i];
vec=temp.x;
vec=(j==1)?temp.y;
vec=(j==2)?temp.z;
vec=(j==3)?temp.w;

Reviewed-by: Kenneth Graunke 

---

 src/glsl/lower_vec_index_to_cond_assign.cpp |   16 
 1 files changed, 12 insertions(+), 4 deletions(-)

diff --git a/src/glsl/lower_vec_index_to_cond_assign.cpp 
b/src/glsl/lower_vec_index_to_cond_assign.cpp
index 789f62a..f85875f 100644
--- a/src/glsl/lower_vec_index_to_cond_assign.cpp
+++ b/src/glsl/lower_vec_index_to_cond_assign.cpp
@@ -68,9 +68,9 @@ ir_rvalue *
 
ir_vec_index_to_cond_assign_visitor::convert_vec_index_to_cond_assign(ir_rvalue 
*ir)
 {
ir_dereference_array *orig_deref = ir->as_dereference_array();
-   ir_assignment *assign;
-   ir_variable *index, *var;
-   ir_dereference *deref;
+   ir_assignment *assign, *value_assign;
+   ir_variable *index, *var, *value;
+   ir_dereference *deref, *deref_value;
unsigned i;
 
if (!orig_deref)
@@ -95,6 +95,14 @@ 
ir_vec_index_to_cond_assign_visitor::convert_vec_index_to_cond_assign(ir_rvalue
assign = new(base_ir) ir_assignment(deref, orig_deref->array_index, NULL);
list.push_tail(assign);
 
+   /* Store the value inside a temp, thus avoiding matrixes duplication */
+   value = new(base_ir) ir_variable(orig_deref->array->type, "vec_value_tmp",
+   ir_var_temporary);
+   list.push_tail(value);
+   deref_value = new(base_ir) ir_dereference_variable(value);
+   value_assign = new(base_ir) ir_assignment(deref_value, orig_deref->array);
+   list.push_tail(value_assign);
+
/* Temporary where we store whichever value we swizzle out. */
var = new(base_ir) ir_variable(ir->type, "vec_index_tmp_v",
  ir_var_temporary);
@@ -117,7 +125,7 @@ 
ir_vec_index_to_cond_assign_visitor::convert_vec_index_to_cond_assign(ir_rvalue
* underlying variable.
*/
   ir_rvalue *swizzle =
-new(base_ir) ir_swizzle(orig_deref->array->clone(mem_ctx, NULL),
+new(base_ir) ir_swizzle(deref_value->clone(mem_ctx, NULL),
 i, 0, 0, 0, 1);
 
   deref = new(base_ir) ir_dereference_variable(var);

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Mesa (master): r600g: fix pre eg export with llvm

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: e6b3858c89e5a8ba27bfdad18cd883f43489b924
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6b3858c89e5a8ba27bfdad18cd883f43489b924

Author: Vincent Lejeune 
Date:   Wed Nov  7 17:17:58 2012 +0100

r600g: fix pre eg export with llvm

Reviewed-by: Alex Deucher 
Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/r600/r600_asm.c |2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_asm.c 
b/src/gallium/drivers/r600/r600_asm.c
index 5f2548e..f06af44 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -2961,6 +2961,6 @@ void r600_bytecode_export_read(struct 
r600_bytecode_output *output, uint32_t wor
output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
output->end_of_program = 
G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
-   output->inst = 
EG_S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1));
+   output->inst = 
R600_S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1));
output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
 }

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Mesa (master): r600g: make tgsi-to-llvm generates store. pixel* intrinsic for fs

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 84b437213294ff4e1a3bcae2f9cbb36a9b4955c4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=84b437213294ff4e1a3bcae2f9cbb36a9b4955c4

Author: Vincent Lejeune 
Date:   Sat Sep 29 16:49:13 2012 +0200

r600g: make tgsi-to-llvm generates store.pixel* intrinsic for fs

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/r600/eg_asm.c|   17 +++
 src/gallium/drivers/r600/r600_asm.c  |   17 +++
 src/gallium/drivers/r600/r600_asm.h  |2 +
 src/gallium/drivers/r600/r600_llvm.c |   71 ++---
 src/gallium/drivers/r600/r600_shader.c   |   32 --
 src/gallium/drivers/radeon/radeon_llvm.h |3 +
 6 files changed, 130 insertions(+), 12 deletions(-)

diff --git a/src/gallium/drivers/r600/eg_asm.c 
b/src/gallium/drivers/r600/eg_asm.c
index 310d424..70dc94a 100644
--- a/src/gallium/drivers/r600/eg_asm.c
+++ b/src/gallium/drivers/r600/eg_asm.c
@@ -145,3 +145,20 @@ int eg_bytecode_cf_build(struct r600_bytecode *bc, struct 
r600_bytecode_cf *cf)
}
return 0;
 }
+
+void eg_bytecode_export_read(struct r600_bytecode_output *output, uint32_t 
word0, uint32_t word1)
+{
+   output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
+   output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
+   output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0);
+   output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0);
+
+   output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1);
+   output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1);
+   output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1);
+   output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
+   output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
+   output->end_of_program = 
G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
+   output->inst = 
EG_S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1));
+   output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
+}
diff --git a/src/gallium/drivers/r600/r600_asm.c 
b/src/gallium/drivers/r600/r600_asm.c
index f04a920..5f2548e 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -2947,3 +2947,20 @@ void r600_bytecode_alu_read(struct r600_bytecode_alu 
*alu, uint32_t word0, uint3
G_SQ_ALU_WORD1_OP2_UPDATE_EXECUTE_MASK(word1);
}
 }
+
+void r600_bytecode_export_read(struct r600_bytecode_output *output, uint32_t 
word0, uint32_t word1)
+{
+   output->array_base = G_SQ_CF_ALLOC_EXPORT_WORD0_ARRAY_BASE(word0);
+   output->type = G_SQ_CF_ALLOC_EXPORT_WORD0_TYPE(word0);
+   output->gpr = G_SQ_CF_ALLOC_EXPORT_WORD0_RW_GPR(word0);
+   output->elem_size = G_SQ_CF_ALLOC_EXPORT_WORD0_ELEM_SIZE(word0);
+
+   output->swizzle_x = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_X(word1);
+   output->swizzle_y = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Y(word1);
+   output->swizzle_z = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_Z(word1);
+   output->swizzle_w = G_SQ_CF_ALLOC_EXPORT_WORD1_SWIZ_SEL_W(word1);
+   output->burst_count = G_SQ_CF_ALLOC_EXPORT_WORD1_BURST_COUNT(word1);
+   output->end_of_program = 
G_SQ_CF_ALLOC_EXPORT_WORD1_END_OF_PROGRAM(word1);
+   output->inst = 
EG_S_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(G_SQ_CF_ALLOC_EXPORT_WORD1_CF_INST(word1));
+   output->barrier = G_SQ_CF_ALLOC_EXPORT_WORD1_BARRIER(word1);
+}
diff --git a/src/gallium/drivers/r600/r600_asm.h 
b/src/gallium/drivers/r600/r600_asm.h
index 2c7db2c..f3b036d 100644
--- a/src/gallium/drivers/r600/r600_asm.h
+++ b/src/gallium/drivers/r600/r600_asm.h
@@ -247,5 +247,7 @@ void *r600_create_vertex_fetch_shader(struct pipe_context 
*ctx,
 void r700_bytecode_cf_vtx_build(uint32_t *bytecode, const struct 
r600_bytecode_cf *cf);
 int r700_bytecode_alu_build(struct r600_bytecode *bc, struct r600_bytecode_alu 
*alu, unsigned id);
 void r700_bytecode_alu_read(struct r600_bytecode_alu *alu, uint32_t word0, 
uint32_t word1);
+void r600_bytecode_export_read(struct r600_bytecode_output *output, uint32_t 
word0, uint32_t word1);
+void eg_bytecode_export_read(struct r600_bytecode_output *output, uint32_t 
word0, uint32_t word1);
 
 #endif
diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index 3dec8ae..b3d4e6b 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -229,6 +229,9 @@ static void llvm_emit_epilogue(struct lp_build_tgsi_context 
* bld_base)
struct radeon_llvm_context * ctx = radeon_llvm_context(bld_base);
struct lp_build_context * base = &bld_base->base;
unsigned i;
+   
+   unsigned color_count = 0;
+   boolean has_color = false;
 
/* Add the necessary export instructions */
for (i = 0; i < ctx->

Mesa (master): configure.ac: Prevent build of radeon llvm backend with llvm < 3.2

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 1feb6b79ab5d099b7b53d800921e7e8577593a98
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1feb6b79ab5d099b7b53d800921e7e8577593a98

Author: Vincent Lejeune 
Date:   Wed Oct 31 21:02:29 2012 +0100

configure.ac: Prevent build of radeon llvm backend with llvm < 3.2

Reviewed-by: Tom Stellard 

---

 configure.ac |   18 +-
 1 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/configure.ac b/configure.ac
index d42462e..55a9fa7 100644
--- a/configure.ac
+++ b/configure.ac
@@ -1779,15 +1779,23 @@ gallium_require_drm_loader() {
 }
 
 radeon_llvm_check() {
-LLVM_VERSION_MAJOR=`echo $LLVM_VERSION | cut -d. -f1`
-if test "$LLVM_VERSION_MAJOR" -lt "3" -o "x$LLVM_VERSION" = "x3.0"; then
-AC_MSG_ERROR([LLVM 3.1 or newer is required for the r600/radeonsi llvm 
compiler.])
+LLVM_REQUIRED_VERSION_MAJOR="3"
+LLVM_REQUIRED_VERSION_MINOR="2"
+LLVM_AVAILABLE_VERSION_MAJOR=`echo $LLVM_VERSION | cut -d. -f1`
+LLVM_AVAILABLE_VERSION_MINOR=`echo $LLVM_VERSION | cut -d. -f2`
+if test "$LLVM_AVAILABLE_VERSION_MAJOR" -lt "$LLVM_REQUIRED_VERSION_MAJOR" 
-o [ "$LLVM_AVAILABLE_VERSION_MAJOR" -eq "$LLVM_REQUIRED_VERSION_MAJOR" -a 
"$LLVM_AVAILABLE_VERSION_MINOR" -lt "$LLVM_REQUIRED_VERSION_MINOR" ] ; then
+AC_MSG_ERROR([LLVM 
$LLVM_REQUIRED_VERSION_MAJOR.$LLVM_REQUIRED_VERSION_MINOR or newer with AMDGPU 
target enabled is required.
+ To use the r600/radeonsi LLVM backend, you need to fetch 
the LLVM source from:
+ git://people.freedesktop.org/~tstellar/llvm master
+ and build with --enable-experimental-targets=AMDGPU])
 fi
-if test "$LLVM_VERSION_MAJOR" -ge "3" -a "x$LLVM_VERSION" != "x3.1" && 
$LLVM_CONFIG --targets-built | grep -qv '\' ; then
-AC_MSG_ERROR([To use the r600/radeonsi LLVM backend with LLVM 3.2 and 
newer, you need to fetch the LLVM source from:
+if test true && $LLVM_CONFIG --targets-built | grep -qv '\' ; then
+AC_MSG_ERROR([LLVM AMDGPU Target not enabled.
+  To use the r600/radeonsi LLVM backend, you need to fetch 
the LLVM source from:
   git://people.freedesktop.org/~tstellar/llvm master
   and build with --enable-experimental-targets=AMDGPU])
 fi
+AC_MSG_WARN([Please ensure you use the latest llvm tree from 
git://people.freedesktop.org/~tstellar/llvm master before submitting a bug])
 if test "x$LLVM_VERSION" = "x3.2"; then
 LLVM_LIBS="$LLVM_LIBS `$LLVM_CONFIG --libs amdgpu`"
 fi

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Mesa (master): r600g: tgsi-to-llvm emits right input intrinsics

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 5ab82e0ccf84855e9311ebfc58d1b57b437ed991
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ab82e0ccf84855e9311ebfc58d1b57b437ed991

Author: Vincent Lejeune 
Date:   Fri Oct 19 15:49:06 2012 +0200

r600g: tgsi-to-llvm emits right input intrinsics

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/r600/r600_llvm.c   |   62 +---
 src/gallium/drivers/r600/r600_shader.c |   22 
 2 files changed, 64 insertions(+), 20 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index 321966e..3dec8ae 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -90,11 +90,11 @@ llvm_face_select_helper(
 
LLVMValueRef backcolor = llvm_load_input_helper(
ctx,
-   "llvm.R600.load.input",
+   intrinsic,
backcolor_regiser);
LLVMValueRef front_color = llvm_load_input_helper(
ctx,
-   "llvm.R600.load.input",
+   intrinsic,
frontcolor_register);
LLVMValueRef face = llvm_load_input_helper(
ctx,
@@ -120,6 +120,29 @@ static void llvm_load_input(
 {
unsigned chan;
 
+   const char *intrinsics = "llvm.R600.load.input";
+   unsigned offset = 4 * ctx->reserved_reg_count;
+
+   if (ctx->type == TGSI_PROCESSOR_FRAGMENT && ctx->chip_class >= 
EVERGREEN) {
+   switch (decl->Interp.Interpolate) {
+   case TGSI_INTERPOLATE_COLOR:
+   case TGSI_INTERPOLATE_PERSPECTIVE:
+   offset = 0;
+   intrinsics = "llvm.R600.load.input.perspective";
+   break;
+   case TGSI_INTERPOLATE_LINEAR:
+   offset = 0;
+   intrinsics = "llvm.R600.load.input.linear";
+   break;
+   case TGSI_INTERPOLATE_CONSTANT:
+   offset = 0;
+   intrinsics = "llvm.R600.load.input.constant";
+   break;
+   default:
+   assert(0 && "Unknow Interpolate mode");
+   }
+   }
+
for (chan = 0; chan < 4; chan++) {
unsigned soa_index = radeon_llvm_reg_index_soa(input_index,
chan);
@@ -145,24 +168,37 @@ static void llvm_load_input(
break;
case TGSI_SEMANTIC_COLOR:
if (ctx->two_side) {
+   unsigned front_location, back_location;
unsigned back_reg = 
ctx->r600_inputs[input_index]
.potential_back_facing_reg;
-   unsigned back_soa_index = 
radeon_llvm_reg_index_soa(
-   ctx->r600_inputs[back_reg].gpr,
-   chan);
+   if (ctx->chip_class >= EVERGREEN) {
+   front_location = 4 * 
ctx->r600_inputs[input_index].lds_pos + chan;
+   back_location = 4 * 
ctx->r600_inputs[back_reg].lds_pos + chan;
+   } else {
+   front_location = soa_index + 4 * 
ctx->reserved_reg_count;
+   back_location = 
radeon_llvm_reg_index_soa(
+   ctx->r600_inputs[back_reg].gpr,
+   chan);
+   }
ctx->inputs[soa_index] = 
llvm_face_select_helper(ctx,
-   "llvm.R600.load.input",
-   4 * ctx->face_input,
-   soa_index + 4 * ctx->reserved_reg_count,
-   back_soa_index);
+   intrinsics,
+   4 * ctx->face_input, front_location, 
back_location);
break;
}
default:
-   /* The * 4 is assuming that we are in soa mode. */
-   ctx->inputs[soa_index] = llvm_load_input_helper(ctx,
-   "llvm.R600.load.input",
-   soa_index + (ctx->reserved_reg_count * 4));
+   {
+   unsigned location;
+   if (ctx->chip_class >= EVERGREEN) {
+   location = 4 * 
ctx

Mesa (master): r600g: force bank_swizzle if already set

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 0f35702d798ead24497928af36236aa4c7e4b87b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0f35702d798ead24497928af36236aa4c7e4b87b

Author: Vincent Lejeune 
Date:   Fri Oct 19 15:40:38 2012 +0200

r600g: force bank_swizzle if already set

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/r600/r600_asm.c |2 ++
 src/gallium/drivers/r600/r700_asm.c |2 ++
 2 files changed, 4 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_asm.c 
b/src/gallium/drivers/r600/r600_asm.c
index 066fb67..51a2e4e 100644
--- a/src/gallium/drivers/r600/r600_asm.c
+++ b/src/gallium/drivers/r600/r600_asm.c
@@ -2914,6 +2914,8 @@ void r600_bytecode_alu_read(struct r600_bytecode_alu 
*alu, uint32_t word0, uint3
 
/* WORD1 */
alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
+   if (alu->bank_swizzle)
+   alu->bank_swizzle_force = alu->bank_swizzle;
alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);
diff --git a/src/gallium/drivers/r600/r700_asm.c 
b/src/gallium/drivers/r600/r700_asm.c
index 818933a..47b4f91 100644
--- a/src/gallium/drivers/r600/r700_asm.c
+++ b/src/gallium/drivers/r600/r700_asm.c
@@ -92,6 +92,8 @@ void r700_bytecode_alu_read(struct r600_bytecode_alu *alu, 
uint32_t word0, uint3
 
/* WORD1 */
alu->bank_swizzle = G_SQ_ALU_WORD1_BANK_SWIZZLE(word1);
+   if (alu->bank_swizzle)
+   alu->bank_swizzle_force = alu->bank_swizzle;
alu->dst.sel = G_SQ_ALU_WORD1_DST_GPR(word1);
alu->dst.rel = G_SQ_ALU_WORD1_DST_REL(word1);
alu->dst.chan = G_SQ_ALU_WORD1_DST_CHAN(word1);

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Mesa (master): r600g: rewrite tgsi-to-llvm load-input to handle fragcoord

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: d1eaa9ea70c7c1d77904bedf9cbac2e48bc41de9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d1eaa9ea70c7c1d77904bedf9cbac2e48bc41de9

Author: Vincent Lejeune 
Date:   Thu Oct 18 22:38:16 2012 +0200

r600g: rewrite tgsi-to-llvm load-input to handle fragcoord

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/r600/r600_llvm.c   |  124 +---
 src/gallium/drivers/r600/r600_shader.c |2 +-
 2 files changed, 84 insertions(+), 42 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index c6e60af..321966e 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -66,6 +66,53 @@ static LLVMValueRef llvm_fetch_system_value(
return bitcast(bld_base, type, cval);
 }
 
+static LLVMValueRef
+llvm_load_input_helper(
+   struct radeon_llvm_context * ctx,
+   const char *intrinsic, unsigned idx)
+{
+   LLVMValueRef reg = lp_build_const_int32(
+   ctx->soa.bld_base.base.gallivm,
+   idx);
+   return build_intrinsic(
+   ctx->soa.bld_base.base.gallivm->builder,
+   intrinsic,
+   ctx->soa.bld_base.base.elem_type, ®, 1,
+   LLVMReadNoneAttribute);
+}
+
+static LLVMValueRef
+llvm_face_select_helper(
+   struct radeon_llvm_context * ctx,
+   const char *intrinsic, unsigned face_register,
+   unsigned frontcolor_register, unsigned backcolor_regiser)
+{
+
+   LLVMValueRef backcolor = llvm_load_input_helper(
+   ctx,
+   "llvm.R600.load.input",
+   backcolor_regiser);
+   LLVMValueRef front_color = llvm_load_input_helper(
+   ctx,
+   "llvm.R600.load.input",
+   frontcolor_register);
+   LLVMValueRef face = llvm_load_input_helper(
+   ctx,
+   "llvm.R600.load.input",
+   face_register);
+   LLVMValueRef is_face_positive = LLVMBuildFCmp(
+   ctx->soa.bld_base.base.gallivm->builder,
+   LLVMRealUGT, face,
+   lp_build_const_float(ctx->soa.bld_base.base.gallivm, 0.0f),
+   "");
+   return LLVMBuildSelect(
+   ctx->soa.bld_base.base.gallivm->builder,
+   is_face_positive,
+   front_color,
+   backcolor,
+   "");
+}
+
 static void llvm_load_input(
struct radeon_llvm_context * ctx,
unsigned input_index,
@@ -77,50 +124,45 @@ static void llvm_load_input(
unsigned soa_index = radeon_llvm_reg_index_soa(input_index,
chan);
 
-   /* The * 4 is assuming that we are in soa mode. */
-   LLVMValueRef reg = lp_build_const_int32(
-   ctx->soa.bld_base.base.gallivm,
-   soa_index + (ctx->reserved_reg_count * 4));
-   ctx->inputs[soa_index] = build_intrinsic(
-   ctx->soa.bld_base.base.gallivm->builder,
+   switch (decl->Semantic.Name) {
+   case TGSI_SEMANTIC_FACE:
+   ctx->inputs[soa_index] = llvm_load_input_helper(ctx,
"llvm.R600.load.input",
-   ctx->soa.bld_base.base.elem_type, ®, 1,
-   LLVMReadNoneAttribute);
-   
-   if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR && 
ctx->two_side) {
-   unsigned back_reg = ctx->r600_inputs[input_index]
-   .potential_back_facing_reg;
-   unsigned back_soa_index = radeon_llvm_reg_index_soa(
-   ctx->r600_inputs[back_reg].gpr
-   , chan);
-   LLVMValueRef backcolor_reg = lp_build_const_int32(
-   ctx->soa.bld_base.base.gallivm,
-   back_soa_index);
-   LLVMValueRef backcolor = build_intrinsic(
-   ctx->soa.bld_base.base.gallivm->builder,
+   4 * ctx->face_input);
+   break;
+   case TGSI_SEMANTIC_POSITION:
+   if (ctx->type != TGSI_PROCESSOR_FRAGMENT || chan != 3) {
+   ctx->inputs[soa_index] = 
llvm_load_input_helper(ctx,
+   "llvm.R600.load.input",
+   soa_index + (ctx->reserved_reg_count * 
4));
+   } else {
+   LLVMValueRef w_coord = 
llvm_load_input_helper(ctx,
&

Mesa (master): radeon/llvm: use ceil intrinsic instead of llvm.AMDIL.round. posinf

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 5090ce42e4437a2f9d1043309417b3fa930ee330
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5090ce42e4437a2f9d1043309417b3fa930ee330

Author: Vincent Lejeune 
Date:   Mon Oct  8 15:37:39 2012 +0200

radeon/llvm: use ceil intrinsic instead of llvm.AMDIL.round.posinf

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/radeon/AMDGPUISelLowering.cpp  |2 --
 src/gallium/drivers/radeon/AMDILIntrinsics.td  |2 --
 .../drivers/radeon/radeon_setup_tgsi_llvm.c|4 ++--
 3 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp 
b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
index 7d4ce61..d37df6b 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
@@ -139,8 +139,6 @@ SDValue 
AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
   Op.getOperand(2));
 case AMDGPUIntrinsic::AMDIL_round_nearest:
   return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1));
-case AMDGPUIntrinsic::AMDIL_round_posinf:
-  return DAG.getNode(ISD::FCEIL, DL, VT, Op.getOperand(1));
   }
 }
 
diff --git a/src/gallium/drivers/radeon/AMDILIntrinsics.td 
b/src/gallium/drivers/radeon/AMDILIntrinsics.td
index 213c8bb..3f9e20f 100644
--- a/src/gallium/drivers/radeon/AMDILIntrinsics.td
+++ b/src/gallium/drivers/radeon/AMDILIntrinsics.td
@@ -146,8 +146,6 @@ let TargetPrefix = "AMDIL", isTarget = 1 in {
   UnaryIntFloat;
   def int_AMDIL_round_neginf : GCCBuiltin<"__amdil_round_neginf">,
   UnaryIntFloat;
-  def int_AMDIL_round_posinf : GCCBuiltin<"__amdil_round_posinf">,
-  UnaryIntFloat;
   def int_AMDIL_round_zero : GCCBuiltin<"__amdil_round_zero">,
   UnaryIntFloat;
   def int_AMDIL_acos : GCCBuiltin<"__amdil_acos">,
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c 
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 3b25193..57ec372 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -1117,8 +1117,8 @@ void radeon_llvm_context_init(struct radeon_llvm_context 
* ctx)
bld_base->op_actions[TGSI_OPCODE_TXF].intr_name = "llvm.AMDGPU.txf";
bld_base->op_actions[TGSI_OPCODE_TXQ].fetch_args = tex_fetch_args;
bld_base->op_actions[TGSI_OPCODE_TXQ].intr_name = "llvm.AMDGPU.txq";
-   bld_base->op_actions[TGSI_OPCODE_CEIL].emit = 
build_tgsi_intrinsic_nomem;
-   bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = 
"llvm.AMDIL.round.posinf.";
+   bld_base->op_actions[TGSI_OPCODE_CEIL].emit = 
build_tgsi_intrinsic_readonly;
+   bld_base->op_actions[TGSI_OPCODE_CEIL].intr_name = "ceil";
 
 
 

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Mesa (master): radeon/llvm: use floor intrinsic instead of llvm.AMDIL.floor

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 9a6bb3f645eec8ce9b04584f1bd8e76095f20a06
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a6bb3f645eec8ce9b04584f1bd8e76095f20a06

Author: Vincent Lejeune 
Date:   Mon Oct  8 15:34:36 2012 +0200

radeon/llvm: use floor intrinsic instead of llvm.AMDIL.floor

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/radeon/AMDGPUISelLowering.cpp  |1 +
 src/gallium/drivers/radeon/AMDGPUIntrinsics.td |1 -
 src/gallium/drivers/radeon/R600Instructions.td |2 +-
 src/gallium/drivers/radeon/SIInstructions.td   |2 +-
 .../drivers/radeon/radeon_setup_tgsi_llvm.c|4 ++--
 5 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp 
b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
index 30dd8f3..7d4ce61 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
@@ -37,6 +37,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) 
:
   setOperationAction(ISD::FPOW,   MVT::f32, Legal);
   setOperationAction(ISD::FLOG2,  MVT::f32, Legal);
   setOperationAction(ISD::FABS,   MVT::f32, Legal);
+  setOperationAction(ISD::FFLOOR, MVT::f32, Legal);
   setOperationAction(ISD::FRINT,  MVT::f32, Legal);
 
   setOperationAction(ISD::UDIV, MVT::i32, Expand);
diff --git a/src/gallium/drivers/radeon/AMDGPUIntrinsics.td 
b/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
index f300316..eaca4cf 100644
--- a/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
+++ b/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
@@ -23,7 +23,6 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in {
   def int_AMDGPU_cndlt : Intrinsic<[llvm_float_ty], [llvm_float_ty, 
llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
   def int_AMDGPU_div : Intrinsic<[llvm_float_ty], [llvm_float_ty, 
llvm_float_ty], [IntrNoMem]>;
   def int_AMDGPU_dp4 : Intrinsic<[llvm_float_ty], [llvm_v4f32_ty, 
llvm_v4f32_ty], [IntrNoMem]>;
-  def int_AMDGPU_floor : Intrinsic<[llvm_float_ty], [llvm_float_ty], 
[IntrNoMem]>;
   def int_AMDGPU_kill : Intrinsic<[], [llvm_float_ty], []>;
   def int_AMDGPU_kilp : Intrinsic<[], [], []>;
   def int_AMDGPU_lrp : Intrinsic<[llvm_float_ty], [llvm_float_ty, 
llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
diff --git a/src/gallium/drivers/radeon/R600Instructions.td 
b/src/gallium/drivers/radeon/R600Instructions.td
index 620fd38..120a71c 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -399,7 +399,7 @@ def RNDNE : R600_1OP <
 
 def FLOOR : R600_1OP <
   0x14, "FLOOR",
-  [(set R600_Reg32:$dst, (int_AMDGPU_floor R600_Reg32:$src))]
+  [(set R600_Reg32:$dst, (ffloor R600_Reg32:$src))]
 >;
 
 def MOV : InstR600 <0x19, (outs R600_Reg32:$dst),
diff --git a/src/gallium/drivers/radeon/SIInstructions.td 
b/src/gallium/drivers/radeon/SIInstructions.td
index dcd2d13..3dc0954 100644
--- a/src/gallium/drivers/radeon/SIInstructions.td
+++ b/src/gallium/drivers/radeon/SIInstructions.td
@@ -541,7 +541,7 @@ defm V_RNDNE_F32 : VOP1_32 <0x0023, "V_RNDNE_F32",
   [(set VReg_32:$dst, (frint AllReg_32:$src0))]
 >;
 defm V_FLOOR_F32 : VOP1_32 <0x0024, "V_FLOOR_F32",
-  [(set VReg_32:$dst, (int_AMDGPU_floor AllReg_32:$src0))]
+  [(set VReg_32:$dst, (ffloor AllReg_32:$src0))]
 >;
 defm V_EXP_F32 : VOP1_32 <0x0025, "V_EXP_F32",
   [(set VReg_32:$dst, (fexp2 AllReg_32:$src0))]
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c 
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index a8327ac..3b25193 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -1142,8 +1142,8 @@ void radeon_llvm_context_init(struct radeon_llvm_context 
* ctx)
bld_base->op_actions[TGSI_OPCODE_ENDLOOP].emit = endloop_emit;
bld_base->op_actions[TGSI_OPCODE_EX2].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_EX2].intr_name = "llvm.AMDIL.exp.";
-   bld_base->op_actions[TGSI_OPCODE_FLR].emit = build_tgsi_intrinsic_nomem;
-   bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "llvm.AMDGPU.floor";
+   bld_base->op_actions[TGSI_OPCODE_FLR].emit = 
build_tgsi_intrinsic_readonly;
+   bld_base->op_actions[TGSI_OPCODE_FLR].intr_name = "floor";
bld_base->op_actions[TGSI_OPCODE_FRC].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_FRC].intr_name = 
"llvm.AMDIL.fraction.";
bld_base->op_actions[TGSI_OPCODE_IF].emit = if_emit;

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Mesa (master): radeon/llvm: use llvm intrinsic for flog2

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 8db11bc4ed366354aa8b8153240c4a191888785b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8db11bc4ed366354aa8b8153240c4a191888785b

Author: Vincent Lejeune 
Date:   Thu Oct  4 23:55:02 2012 +0200

radeon/llvm: use llvm intrinsic for flog2

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/radeon/AMDGPUISelLowering.cpp  |1 +
 src/gallium/drivers/radeon/AMDILIntrinsics.td  |2 --
 src/gallium/drivers/radeon/R600Instructions.td |2 +-
 .../drivers/radeon/radeon_setup_tgsi_llvm.c|4 ++--
 4 files changed, 4 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp 
b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
index 04dadc3..aee625d 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
@@ -35,6 +35,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) 
:
   setOperationAction(ISD::FCEIL,  MVT::f32, Legal);
   setOperationAction(ISD::FEXP2,  MVT::f32, Legal);
   setOperationAction(ISD::FPOW,   MVT::f32, Legal);
+  setOperationAction(ISD::FLOG2,  MVT::f32, Legal);
   setOperationAction(ISD::FRINT,  MVT::f32, Legal);
 
   setOperationAction(ISD::UDIV, MVT::i32, Expand);
diff --git a/src/gallium/drivers/radeon/AMDILIntrinsics.td 
b/src/gallium/drivers/radeon/AMDILIntrinsics.td
index 104b32e..4de5767 100644
--- a/src/gallium/drivers/radeon/AMDILIntrinsics.td
+++ b/src/gallium/drivers/radeon/AMDILIntrinsics.td
@@ -180,8 +180,6 @@ let TargetPrefix = "AMDIL", isTarget = 1 in {
   UnaryIntFloat;
   def int_AMDIL_exn : GCCBuiltin<"__amdil_exn">,
   UnaryIntFloat;
-  def int_AMDIL_log : GCCBuiltin<"__amdil_log">,
-  UnaryIntFloat;
   def int_AMDIL_log_vec : GCCBuiltin<"__amdil_log_vec">,
   UnaryIntFloat;
   def int_AMDIL_ln : GCCBuiltin<"__amdil_ln">,
diff --git a/src/gallium/drivers/radeon/R600Instructions.td 
b/src/gallium/drivers/radeon/R600Instructions.td
index e32ea69..620fd38 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -761,7 +761,7 @@ class LOG_CLAMPED_Common  inst> : R600_1OP <
 
 class LOG_IEEE_Common  inst> : R600_1OP <
   inst, "LOG_IEEE",
-  [(set R600_Reg32:$dst, (int_AMDIL_log R600_Reg32:$src))]
+  [(set R600_Reg32:$dst, (flog2 R600_Reg32:$src))]
 >;
 
 class LSHL_Common  inst> : R600_2OP <
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c 
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 8b5eaed..cc690c0 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -1151,8 +1151,8 @@ void radeon_llvm_context_init(struct radeon_llvm_context 
* ctx)
bld_base->op_actions[TGSI_OPCODE_KIL].intr_name = "llvm.AMDGPU.kill";
bld_base->op_actions[TGSI_OPCODE_KILP].emit = lp_build_tgsi_intrinsic;
bld_base->op_actions[TGSI_OPCODE_KILP].intr_name = "llvm.AMDGPU.kilp";
-   bld_base->op_actions[TGSI_OPCODE_LG2].emit = build_tgsi_intrinsic_nomem;
-   bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.AMDIL.log.";
+   bld_base->op_actions[TGSI_OPCODE_LG2].emit = 
build_tgsi_intrinsic_readonly;
+   bld_base->op_actions[TGSI_OPCODE_LG2].intr_name = "llvm.log2.f32";
bld_base->op_actions[TGSI_OPCODE_LRP].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_LRP].intr_name = "llvm.AMDGPU.lrp";
bld_base->op_actions[TGSI_OPCODE_MIN].emit = build_tgsi_intrinsic_nomem;

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Mesa (master): radeon/llvm: use llvm fabs intrinsic

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: bfdf26892c2df430384d03ba356038df7853ffb9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bfdf26892c2df430384d03ba356038df7853ffb9

Author: Vincent Lejeune 
Date:   Mon Oct  8 15:27:47 2012 +0200

radeon/llvm: use llvm fabs intrinsic

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/radeon/AMDGPUISelLowering.cpp  |3 +--
 src/gallium/drivers/radeon/AMDILIntrinsics.td  |1 -
 .../drivers/radeon/radeon_setup_tgsi_llvm.c|6 +++---
 3 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp 
b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
index aee625d..30dd8f3 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
@@ -36,6 +36,7 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) 
:
   setOperationAction(ISD::FEXP2,  MVT::f32, Legal);
   setOperationAction(ISD::FPOW,   MVT::f32, Legal);
   setOperationAction(ISD::FLOG2,  MVT::f32, Legal);
+  setOperationAction(ISD::FABS,   MVT::f32, Legal);
   setOperationAction(ISD::FRINT,  MVT::f32, Legal);
 
   setOperationAction(ISD::UDIV, MVT::i32, Expand);
@@ -110,8 +111,6 @@ SDValue 
AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
   return LowerIntrinsicIABS(Op, DAG);
 case AMDGPUIntrinsic::AMDIL_exp:
   return DAG.getNode(ISD::FEXP2, DL, VT, Op.getOperand(1));
-case AMDGPUIntrinsic::AMDIL_fabs:
-  return DAG.getNode(ISD::FABS, DL, VT, Op.getOperand(1));
 case AMDGPUIntrinsic::AMDGPU_lrp:
   return LowerIntrinsicLRP(Op, DAG);
 case AMDGPUIntrinsic::AMDIL_fraction:
diff --git a/src/gallium/drivers/radeon/AMDILIntrinsics.td 
b/src/gallium/drivers/radeon/AMDILIntrinsics.td
index 4de5767..213c8bb 100644
--- a/src/gallium/drivers/radeon/AMDILIntrinsics.td
+++ b/src/gallium/drivers/radeon/AMDILIntrinsics.td
@@ -66,7 +66,6 @@ let TargetPrefix = "AMDIL", isTarget = 1 in {
 }
 
 let TargetPrefix = "AMDIL", isTarget = 1 in {
-  def int_AMDIL_fabs : GCCBuiltin<"__amdil_fabs">, UnaryIntFloat;
   def int_AMDIL_abs : GCCBuiltin<"__amdil_abs">, UnaryIntInt;
 
   def int_AMDIL_bit_extract_i32 : GCCBuiltin<"__amdil_ibit_extract">,
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c 
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index cc690c0..a8327ac 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -538,7 +538,7 @@ static void emit_prepare_cube_coords(
coords[i] = LLVMBuildExtractElement(builder, v, idx, "");
}
 
-   coords[2] = build_intrinsic(builder, "llvm.AMDIL.fabs.",
+   coords[2] = build_intrinsic(builder, "fabs",
type, &coords[2], 1, LLVMReadNoneAttribute);
coords[2] = build_intrinsic(builder, "llvm.AMDGPU.rcp",
type, &coords[2], 1, LLVMReadNoneAttribute);
@@ -1122,8 +1122,8 @@ void radeon_llvm_context_init(struct radeon_llvm_context 
* ctx)
 
 
 
-   bld_base->op_actions[TGSI_OPCODE_ABS].emit = build_tgsi_intrinsic_nomem;
-   bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "llvm.AMDIL.fabs.";
+   bld_base->op_actions[TGSI_OPCODE_ABS].emit = 
build_tgsi_intrinsic_readonly;
+   bld_base->op_actions[TGSI_OPCODE_ABS].intr_name = "fabs";
bld_base->op_actions[TGSI_OPCODE_ARL].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_ARL].intr_name = "llvm.AMDGPU.arl";
bld_base->op_actions[TGSI_OPCODE_BGNLOOP].emit = bgnloop_emit;

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Mesa (master): radeon/llvm: add support for cos/sin intrinsic

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 23e11ac8354b3807d9c69c19bcf958cca23ffc04
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=23e11ac8354b3807d9c69c19bcf958cca23ffc04

Author: Vincent Lejeune 
Date:   Wed Oct  3 22:28:59 2012 +0200

radeon/llvm: add support for cos/sin intrinsic

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/radeon/AMDGPUIntrinsics.td |2 --
 src/gallium/drivers/radeon/R600Instructions.td |   17 +++--
 .../drivers/radeon/radeon_setup_tgsi_llvm.c|8 
 3 files changed, 15 insertions(+), 12 deletions(-)

diff --git a/src/gallium/drivers/radeon/AMDGPUIntrinsics.td 
b/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
index 958e0bd..f300316 100644
--- a/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
+++ b/src/gallium/drivers/radeon/AMDGPUIntrinsics.td
@@ -21,7 +21,6 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in {
 
   def int_AMDGPU_arl : Intrinsic<[llvm_i32_ty], [llvm_float_ty], [IntrNoMem]>;
   def int_AMDGPU_cndlt : Intrinsic<[llvm_float_ty], [llvm_float_ty, 
llvm_float_ty, llvm_float_ty], [IntrNoMem]>;
-  def int_AMDGPU_cos : Intrinsic<[llvm_float_ty], [llvm_float_ty], 
[IntrNoMem]>;
   def int_AMDGPU_div : Intrinsic<[llvm_float_ty], [llvm_float_ty, 
llvm_float_ty], [IntrNoMem]>;
   def int_AMDGPU_dp4 : Intrinsic<[llvm_float_ty], [llvm_v4f32_ty, 
llvm_v4f32_ty], [IntrNoMem]>;
   def int_AMDGPU_floor : Intrinsic<[llvm_float_ty], [llvm_float_ty], 
[IntrNoMem]>;
@@ -35,7 +34,6 @@ let TargetPrefix = "AMDGPU", isTarget = 1 in {
   def int_AMDGPU_seq : Intrinsic<[llvm_float_ty], [llvm_float_ty, 
llvm_float_ty], [IntrNoMem]>;
   def int_AMDGPU_sgt : Intrinsic<[llvm_float_ty], [llvm_float_ty, 
llvm_float_ty], [IntrNoMem]>;
   def int_AMDGPU_sge : Intrinsic<[llvm_float_ty], [llvm_float_ty, 
llvm_float_ty], [IntrNoMem]>;
-  def int_AMDGPU_sin : Intrinsic<[llvm_float_ty], [llvm_float_ty], 
[IntrNoMem]>;
   def int_AMDGPU_sle : Intrinsic<[llvm_float_ty], [llvm_float_ty, 
llvm_float_ty], [IntrNoMem]>;
   def int_AMDGPU_sne : Intrinsic<[llvm_float_ty], [llvm_float_ty, 
llvm_float_ty], [IntrNoMem]>;
   def int_AMDGPU_ssg : Intrinsic<[llvm_float_ty], [llvm_float_ty], 
[IntrNoMem]>;
diff --git a/src/gallium/drivers/radeon/R600Instructions.td 
b/src/gallium/drivers/radeon/R600Instructions.td
index 01a5bba..e32ea69 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -905,8 +905,13 @@ let Predicates = [isR600] in {
 
 // Helper pattern for normalizing inputs to triginomic instructions for R700+
 // cards.
-class TRIG_eg  : Pat<
-  (intr R600_Reg32:$src),
+class COS_PAT  : Pat<
+  (fcos R600_Reg32:$src),
+  (trig (MUL (MOV_IMM_I32 (i32 ALU_LITERAL_X), CONST.TWO_PI_INV), 
R600_Reg32:$src))
+>;
+
+class SIN_PAT  : Pat<
+  (fsin R600_Reg32:$src),
   (trig (MUL (MOV_IMM_I32 (i32 ALU_LITERAL_X), CONST.TWO_PI_INV), 
R600_Reg32:$src))
 >;
 
@@ -919,8 +924,8 @@ let Predicates = [isR700] in {
   def COS_r700 : COS_Common<0x6F>;
 
   // R700 normalizes inputs to SIN/COS the same as EG
-  def : TRIG_eg ;
-  def : TRIG_eg ;
+  def : SIN_PAT ;
+  def : COS_PAT ;
 }
 
 
//===--===//
@@ -997,8 +1002,8 @@ let Predicates = [isEGorCayman] in {
   def SSG_eg : SSG_Common;
   def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common;
 
-  def : TRIG_eg ;
-  def : TRIG_eg ;
+  def : SIN_PAT ;
+  def : COS_PAT ;
 
   def FLT_TO_INT_eg : FLT_TO_INT_Common<0x50> {
 let Pattern = [];
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c 
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index 3c29122..8b5eaed 100644
--- a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
+++ b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
@@ -1133,8 +1133,8 @@ void radeon_llvm_context_init(struct radeon_llvm_context 
* ctx)
bld_base->op_actions[TGSI_OPCODE_CLAMP].intr_name = "llvm.AMDIL.clamp.";
bld_base->op_actions[TGSI_OPCODE_CMP].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_CMP].intr_name = "llvm.AMDGPU.cndlt";
-   bld_base->op_actions[TGSI_OPCODE_COS].emit = build_tgsi_intrinsic_nomem;
-   bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.AMDGPU.cos";
+   bld_base->op_actions[TGSI_OPCODE_COS].emit = 
build_tgsi_intrinsic_readonly;
+   bld_base->op_actions[TGSI_OPCODE_COS].intr_name = "llvm.cos.f32";
bld_base->op_actions[TGSI_OPCODE_DIV].emit = build_tgsi_intrinsic_nomem;
bld_base->op_actions[TGSI_OPCODE_DIV].intr_name = "llvm.AMDGPU.div";
bld_base->op_actions[TGSI_OPCODE_ELSE].emit = else_emit;
@@ -1175,8 +1175,8 @@ void radeon_llvm_context_init(struct radeon_llvm_context 
* ctx)
bld_base->op_actions[TGSI_OPCODE_SLT].emit = emit_cmp;
bld_bas

Mesa (master): radeon/llvm: add a pattern for fsqrt

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 876b42663c4a72040a2084ed094d5a496b86aecd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=876b42663c4a72040a2084ed094d5a496b86aecd

Author: Vincent Lejeune 
Date:   Wed Oct  3 21:40:49 2012 +0200

radeon/llvm: add a pattern for fsqrt

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/radeon/R600Instructions.td |3 +++
 1 files changed, 3 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/radeon/R600Instructions.td 
b/src/gallium/drivers/radeon/R600Instructions.td
index 1689a2f..01a5bba 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -1018,6 +1018,9 @@ let Predicates = [isEGorCayman] in {
   def : Pat<(fp_to_uint R600_Reg32:$src),
 (FLT_TO_UINT_eg (TRUNC R600_Reg32:$src))>;
 
+  def : Pat<(fsqrt R600_Reg32:$src),
+(MUL R600_Reg32:$src, (RECIPSQRT_CLAMPED_eg R600_Reg32:$src))>;
+
 
//===--===//
 // Memory read/write instructions
 
//===--===//

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Mesa (master): r600g: use a select to handle front/back color in llvm

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 11e08f42e4fa5f1d296429415be6da7c03f105b0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=11e08f42e4fa5f1d296429415be6da7c03f105b0

Author: Vincent Lejeune 
Date:   Sun Sep 23 19:46:53 2012 +0200

r600g: use a select to handle front/back color in llvm

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/r600/r600_llvm.c   |   36 
 src/gallium/drivers/r600/r600_shader.c |   13 +++
 2 files changed, 44 insertions(+), 5 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index 71ea578..c6e60af 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -86,6 +86,42 @@ static void llvm_load_input(
"llvm.R600.load.input",
ctx->soa.bld_base.base.elem_type, ®, 1,
LLVMReadNoneAttribute);
+   
+   if (decl->Semantic.Name == TGSI_SEMANTIC_COLOR && 
ctx->two_side) {
+   unsigned back_reg = ctx->r600_inputs[input_index]
+   .potential_back_facing_reg;
+   unsigned back_soa_index = radeon_llvm_reg_index_soa(
+   ctx->r600_inputs[back_reg].gpr
+   , chan);
+   LLVMValueRef backcolor_reg = lp_build_const_int32(
+   ctx->soa.bld_base.base.gallivm,
+   back_soa_index);
+   LLVMValueRef backcolor = build_intrinsic(
+   ctx->soa.bld_base.base.gallivm->builder,
+   "llvm.R600.load.input",
+   ctx->soa.bld_base.base.elem_type, 
&backcolor_reg, 1,
+   LLVMReadNoneAttribute);
+   LLVMValueRef face_reg = lp_build_const_int32(
+   ctx->soa.bld_base.base.gallivm,
+   ctx->face_input * 4);
+   LLVMValueRef face = build_intrinsic(
+   ctx->soa.bld_base.base.gallivm->builder,
+   "llvm.R600.load.input",
+   ctx->soa.bld_base.base.elem_type,
+   &face_reg, 1,
+   LLVMReadNoneAttribute);
+   LLVMValueRef is_face_positive = LLVMBuildFCmp(
+   ctx->soa.bld_base.base.gallivm->builder,
+   LLVMRealUGT, face, 
+   
lp_build_const_float(ctx->soa.bld_base.base.gallivm, 0.0f),
+   "");
+   ctx->inputs[soa_index] = LLVMBuildSelect(
+   ctx->soa.bld_base.base.gallivm->builder,
+   is_face_positive,
+   ctx->inputs[soa_index],
+   backcolor,
+   "");
+   }
}
 }
 
diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 0c585de..daa5082 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1128,7 +1128,7 @@ static int tgsi_split_literal_constant(struct 
r600_shader_ctx *ctx)
return 0;
 }
 
-static int process_twoside_color_inputs(struct r600_shader_ctx *ctx)
+static int process_twoside_color_inputs(struct r600_shader_ctx *ctx, unsigned 
use_llvm)
 {
int i, r, count = ctx->shader->ninput;
 
@@ -1139,9 +1139,12 @@ static int process_twoside_color_inputs(struct 
r600_shader_ctx *ctx)
if ((r = evergreen_interp_input(ctx, 
back_facing_reg)))
return r;
}
-   r = select_twoside_color(ctx, i, back_facing_reg);
-   if (r)
-   return r;
+   
+   if (!use_llvm) {
+   r = select_twoside_color(ctx, i, 
back_facing_reg);
+   if (r)
+   return r;
+   }
}
}
return 0;
@@ -1402,7 +1405,7 @@ static int r600_shader_from_tgsi(struct r600_screen 
*rscreen,
}
 
if (shader->two_side && ctx.colors_used) {
-   if ((r = process_twoside_color_inputs(&ctx)))
+   if ((r = process_twoside_color_inputs(&ctx, use_llvm)))
return r;
}
 

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Mesa (master): r600g: frontcolor tracks its associated backcolor

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 80663cb1859c3398804d720022eebcf9a0df1716
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=80663cb1859c3398804d720022eebcf9a0df1716

Author: Vincent Lejeune 
Date:   Sun Sep 23 16:52:30 2012 +0200

r600g: frontcolor tracks its associated backcolor

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/r600/r600_shader.c |   59 ++-
 src/gallium/drivers/r600/r600_shader.h |1 +
 2 files changed, 35 insertions(+), 25 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index bf4877a..0c585de 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1132,36 +1132,14 @@ static int process_twoside_color_inputs(struct 
r600_shader_ctx *ctx)
 {
int i, r, count = ctx->shader->ninput;
 
-   /* additional inputs will be allocated right after the existing inputs,
-* we won't need them after the color selection, so we don't need to
-* reserve these gprs for the rest of the shader code and to adjust
-* output offsets etc. */
-   int gpr = ctx->file_offset[TGSI_FILE_INPUT] +
-   ctx->info.file_max[TGSI_FILE_INPUT] + 1;
-
-   if (ctx->face_gpr == -1) {
-   i = ctx->shader->ninput++;
-   ctx->shader->input[i].name = TGSI_SEMANTIC_FACE;
-   ctx->shader->input[i].spi_sid = 0;
-   ctx->shader->input[i].gpr = gpr++;
-   ctx->face_gpr = ctx->shader->input[i].gpr;
-   }
-
for (i = 0; i < count; i++) {
if (ctx->shader->input[i].name == TGSI_SEMANTIC_COLOR) {
-   int ni = ctx->shader->ninput++;
-   memcpy(&ctx->shader->input[ni],&ctx->shader->input[i], 
sizeof(struct r600_shader_io));
-   ctx->shader->input[ni].name = TGSI_SEMANTIC_BCOLOR;
-   ctx->shader->input[ni].spi_sid = 
r600_spi_sid(&ctx->shader->input[ni]);
-   ctx->shader->input[ni].gpr = gpr++;
-
+   unsigned back_facing_reg = 
ctx->shader->input[i].potential_back_facing_reg;
if (ctx->bc->chip_class >= EVERGREEN) {
-   r = evergreen_interp_input(ctx, ni);
-   if (r)
+   if ((r = evergreen_interp_input(ctx, 
back_facing_reg)))
return r;
}
-
-   r = select_twoside_color(ctx, i, ni);
+   r = select_twoside_color(ctx, i, back_facing_reg);
if (r)
return r;
}
@@ -1323,6 +1301,37 @@ static int r600_shader_from_tgsi(struct r600_screen 
*rscreen,
goto out_err;
}
}
+   
+   /* Process two side if needed */
+   if (shader->two_side && ctx.colors_used) {
+   int i, count = ctx.shader->ninput;
+
+   /* additional inputs will be allocated right after the existing 
inputs,
+* we won't need them after the color selection, so we don't 
need to
+* reserve these gprs for the rest of the shader code and to 
adjust
+* output offsets etc. */
+   int gpr = ctx.file_offset[TGSI_FILE_INPUT] +
+   ctx.info.file_max[TGSI_FILE_INPUT] + 1;
+
+   if (ctx.face_gpr == -1) {
+   i = ctx.shader->ninput++;
+   ctx.shader->input[i].name = TGSI_SEMANTIC_FACE;
+   ctx.shader->input[i].spi_sid = 0;
+   ctx.shader->input[i].gpr = gpr++;
+   ctx.face_gpr = ctx.shader->input[i].gpr;
+   }
+
+   for (i = 0; i < count; i++) {
+   if (ctx.shader->input[i].name == TGSI_SEMANTIC_COLOR) {
+   int ni = ctx.shader->ninput++;
+   
memcpy(&ctx.shader->input[ni],&ctx.shader->input[i], sizeof(struct 
r600_shader_io));
+   ctx.shader->input[ni].name = 
TGSI_SEMANTIC_BCOLOR;
+   ctx.shader->input[ni].spi_sid = 
r600_spi_sid(&ctx.shader->input[ni]);
+   ctx.shader->input[ni].gpr = gpr++;
+   ctx.shader->input[i].potential_back_facing_reg 
= ni;
+   }
+   }
+   }
 
 /* LLVM backend setup */
 #ifdef R600_USE_LLVM
diff --git a/src/gallium/drivers/r600/r600_shader.h 
b/src/gallium/drivers/r600/r600_shader.h
index d68dd07..2b8412a 100644
--- a/src/gallium/drivers/r600/r600_shade

Mesa (master): r600g: add some members to radeon_llvm_context

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 92b3a99ce5f54f2c692c8db5a0c471aac0ff7c82
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=92b3a99ce5f54f2c692c8db5a0c471aac0ff7c82

Author: Vincent Lejeune 
Date:   Sun Sep 23 15:53:57 2012 +0200

r600g: add some members to radeon_llvm_context

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/r600/r600_shader.c   |5 +
 src/gallium/drivers/radeon/radeon_llvm.h |6 ++
 2 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 20bf79d..bf4877a 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1332,6 +1332,11 @@ static int r600_shader_from_tgsi(struct r600_screen 
*rscreen,
unsigned dump = 0;
memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
radeon_llvm_ctx.reserved_reg_count = 
ctx.file_offset[TGSI_FILE_INPUT];
+   radeon_llvm_ctx.type = ctx.type;
+   radeon_llvm_ctx.two_side = shader->two_side;
+   radeon_llvm_ctx.face_input = ctx.face_gpr;
+   radeon_llvm_ctx.r600_inputs = ctx.shader->input;
+   radeon_llvm_ctx.chip_class = ctx.bc->chip_class;
mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE)) {
dump = 1;
diff --git a/src/gallium/drivers/radeon/radeon_llvm.h 
b/src/gallium/drivers/radeon/radeon_llvm.h
index 7a32bb0..6118b11 100644
--- a/src/gallium/drivers/radeon/radeon_llvm.h
+++ b/src/gallium/drivers/radeon/radeon_llvm.h
@@ -54,6 +54,12 @@ struct radeon_llvm_context {
 
struct lp_build_tgsi_soa_context soa;
 
+   unsigned chip_class;
+   unsigned type;
+   unsigned face_input;
+   unsigned two_side;
+   struct r600_shader_io * r600_inputs;
+
/*=== Front end configuration ===*/
 
/* Special Intrinsics */

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Mesa (master): r600g: tgsi-to-llvm path is taken after declarations have been parsed

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: a1a3792b180e453d26bfd09853eee88460dfc466
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a1a3792b180e453d26bfd09853eee88460dfc466

Author: Vincent Lejeune 
Date:   Sun Sep 23 15:20:34 2012 +0200

r600g: tgsi-to-llvm path is taken after declarations have been parsed

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/r600/r600_shader.c |   58 +--
 1 files changed, 32 insertions(+), 26 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_shader.c 
b/src/gallium/drivers/r600/r600_shader.c
index 29616f9..20bf79d 100644
--- a/src/gallium/drivers/r600/r600_shader.c
+++ b/src/gallium/drivers/r600/r600_shader.c
@@ -1250,7 +1250,6 @@ static int r600_shader_from_tgsi(struct r600_screen 
*rscreen,
ctx.file_offset[TGSI_FILE_INPUT] = evergreen_gpr_count(&ctx);
}
 
-   /* LLVM backend setup */
 #ifdef R600_USE_LLVM
if (use_llvm && ctx.info.indirect_files) {
fprintf(stderr, "Warning: R600 LLVM backend does not support "
@@ -1258,34 +1257,13 @@ static int r600_shader_from_tgsi(struct r600_screen 
*rscreen,
"backend.\n");
use_llvm = 0;
}
-   if (use_llvm) {
-   struct radeon_llvm_context radeon_llvm_ctx;
-   LLVMModuleRef mod;
-   unsigned dump = 0;
-   memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
-   radeon_llvm_ctx.reserved_reg_count = 
ctx.file_offset[TGSI_FILE_INPUT];
-   mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
-   if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE)) {
-   dump = 1;
-   }
-   if (r600_llvm_compile(mod, &inst_bytes, &inst_byte_count,
-   rscreen->family, dump)) 
{
-   FREE(inst_bytes);
-   radeon_llvm_dispose(&radeon_llvm_ctx);
-   use_llvm = 0;
-   fprintf(stderr, "R600 LLVM backend failed to compile "
-   "shader.  Falling back to TGSI\n");
-   } else {
-   ctx.file_offset[TGSI_FILE_OUTPUT] =
-   ctx.file_offset[TGSI_FILE_INPUT];
-   }
-   radeon_llvm_dispose(&radeon_llvm_ctx);
-   }
 #endif
-   /* End of LLVM backend setup */
 
-   if (!use_llvm) {
+   if (use_llvm) {
ctx.file_offset[TGSI_FILE_OUTPUT] =
+   ctx.file_offset[TGSI_FILE_INPUT];
+   } else {
+  ctx.file_offset[TGSI_FILE_OUTPUT] =
ctx.file_offset[TGSI_FILE_INPUT] +
ctx.info.file_max[TGSI_FILE_INPUT] + 1;
}
@@ -1346,6 +1324,34 @@ static int r600_shader_from_tgsi(struct r600_screen 
*rscreen,
}
}
 
+/* LLVM backend setup */
+#ifdef R600_USE_LLVM
+   if (use_llvm) {
+   struct radeon_llvm_context radeon_llvm_ctx;
+   LLVMModuleRef mod;
+   unsigned dump = 0;
+   memset(&radeon_llvm_ctx, 0, sizeof(radeon_llvm_ctx));
+   radeon_llvm_ctx.reserved_reg_count = 
ctx.file_offset[TGSI_FILE_INPUT];
+   mod = r600_tgsi_llvm(&radeon_llvm_ctx, tokens);
+   if (debug_get_bool_option("R600_DUMP_SHADERS", FALSE)) {
+   dump = 1;
+   }
+   if (r600_llvm_compile(mod, &inst_bytes, &inst_byte_count,
+   rscreen->family, dump)) 
{
+   FREE(inst_bytes);
+   radeon_llvm_dispose(&radeon_llvm_ctx);
+   use_llvm = 0;
+   fprintf(stderr, "R600 LLVM backend failed to compile "
+   "shader.  Falling back to TGSI\n");
+   } else {
+   ctx.file_offset[TGSI_FILE_OUTPUT] =
+   ctx.file_offset[TGSI_FILE_INPUT];
+   }
+   radeon_llvm_dispose(&radeon_llvm_ctx);
+   }
+#endif
+/* End of LLVM backend setup */
+
if (shader->fs_write_all && rscreen->chip_class >= EVERGREEN)
shader->nr_ps_max_color_exports = 8;
 

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Mesa (master): radeon/llvm: improve select_cc lowering to generate CND* more often

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: ff947c6d65830b7be6e9fcbfe666fa7dba6341f6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff947c6d65830b7be6e9fcbfe666fa7dba6341f6

Author: Vincent Lejeune 
Date:   Mon Sep 24 16:04:26 2012 +0200

radeon/llvm: improve select_cc lowering to generate CND* more often

v2: - Simplify isZero()
- Remove a unused function prototype
- Clean whitespace trails

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/r600/r600_llvm.c|   15 
 src/gallium/drivers/radeon/R600ISelLowering.cpp |   89 ++-
 src/gallium/drivers/radeon/R600ISelLowering.h   |2 +
 src/gallium/drivers/radeon/R600Instructions.td  |   38 --
 4 files changed, 103 insertions(+), 41 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_llvm.c 
b/src/gallium/drivers/r600/r600_llvm.c
index dd0a714..71ea578 100644
--- a/src/gallium/drivers/r600/r600_llvm.c
+++ b/src/gallium/drivers/r600/r600_llvm.c
@@ -165,6 +165,20 @@ static void llvm_emit_tex(
emit_data->dst_type, args, c, 
LLVMReadNoneAttribute);
 }
 
+static void emit_cndlt(
+   const struct lp_build_tgsi_action * action,
+   struct lp_build_tgsi_context * bld_base,
+   struct lp_build_emit_data * emit_data)
+{
+   LLVMBuilderRef builder = bld_base->base.gallivm->builder;
+   LLVMValueRef float_zero = lp_build_const_float(
+   bld_base->base.gallivm, 0.0f);
+   LLVMValueRef cmp = LLVMBuildFCmp(
+   builder, LLVMRealULT, emit_data->args[0], float_zero, "");
+   emit_data->output[emit_data->chan] = LLVMBuildSelect(builder,
+   cmp, emit_data->args[1], emit_data->args[2], "");
+}
+
 static void dp_fetch_args(
struct lp_build_tgsi_context * bld_base,
struct lp_build_emit_data * emit_data)
@@ -241,6 +255,7 @@ LLVMModuleRef r600_tgsi_llvm(
bld_base->op_actions[TGSI_OPCODE_TXF].emit = llvm_emit_tex;
bld_base->op_actions[TGSI_OPCODE_TXQ].emit = llvm_emit_tex;
bld_base->op_actions[TGSI_OPCODE_TXP].emit = llvm_emit_tex;
+   bld_base->op_actions[TGSI_OPCODE_CMP].emit = emit_cndlt;
 
lp_build_tgsi_llvm(bld_base, tokens);
 
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp 
b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index 2fc9c67..5dd2f53 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -516,6 +516,17 @@ SDValue R600TargetLowering::LowerROTL(SDValue Op, 
SelectionDAG &DAG) const
  Op.getOperand(1)));
 }
 
+bool R600TargetLowering::isZero(SDValue Op) const
+{
+  if(ConstantSDNode *Cst = dyn_cast(Op)) {
+return Cst->isNullValue();
+  } else if(ConstantFPSDNode *CstFP = dyn_cast(Op)){
+return CstFP->isZero();
+  } else {
+return false;
+  }
+}
+
 SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const
 {
   DebugLoc DL = Op.getDebugLoc();
@@ -568,47 +579,58 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, 
SelectionDAG &DAG) const
   if (isHWTrueValue(False) && isHWFalseValue(True)) {
   }
 
-  // XXX Check if we can lower this to a SELECT or if it is supported by a 
native
-  // operation. (The code below does this but we don't have the Instruction
-  // selection patterns to do this yet.
-#if 0
+  // Check if we can lower this to a native operation.
+  // CND* instructions requires all operands to have the same type,
+  // and RHS to be zero.
+
   if (isZero(LHS) || isZero(RHS)) {
 SDValue Cond = (isZero(LHS) ? RHS : LHS);
-bool SwapTF = false;
+SDValue Zero = (isZero(LHS) ? LHS : RHS);
+ISD::CondCode CCOpcode = cast(CC)->get();
+if (CompareVT != VT) {
+  True = DAG.getNode(ISD::BITCAST, DL, CompareVT, True);
+  False = DAG.getNode(ISD::BITCAST, DL, CompareVT, False);
+}
+if (isZero(LHS)) {
+  CCOpcode = ISD::getSetCCSwappedOperands(CCOpcode);
+}
+
 switch (CCOpcode) {
-case ISD::SETOEQ:
-case ISD::SETUEQ:
-case ISD::SETEQ:
-  SwapTF = true;
-  // Fall through
 case ISD::SETONE:
 case ISD::SETUNE:
 case ISD::SETNE:
-  // We can lower to select
-  if (SwapTF) {
-Temp = True;
-True = False;
-False = Temp;
-  }
-  // CNDE
-  return DAG.getNode(ISD::SELECT, DL, VT, Cond, True, False);
+case ISD::SETULE:
+case ISD::SETULT:
+case ISD::SETOLE:
+case ISD::SETOLT:
+case ISD::SETLE:
+case ISD::SETLT:
+  CCOpcode = ISD::getSetCCInverse(CCOpcode, CompareVT == MVT::i32);
+  Temp = True;
+  True = False;
+  False = Temp;
+  break;
 default:
-  // Supported by a native operation (CNDGE, CNDGT)
-  return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
+  break;
 }
+SDValue Sele

Mesa (master): radeon/llvm: support for interpolation intrinsics

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: fb40f88338b6af23faae03ced5906add8507db26
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fb40f88338b6af23faae03ced5906add8507db26

Author: Vincent Lejeune 
Date:   Thu Sep  6 22:45:38 2012 +0200

radeon/llvm: support for interpolation intrinsics

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/radeon/AMDGPUISelLowering.cpp  |2 +
 src/gallium/drivers/radeon/AMDGPUISelLowering.h|2 +
 .../drivers/radeon/R600ExpandSpecialInstrs.cpp |  129 
 src/gallium/drivers/radeon/R600ISelLowering.cpp|   88 +-
 src/gallium/drivers/radeon/R600ISelLowering.h  |1 +
 src/gallium/drivers/radeon/R600Instructions.td |   54 
 .../drivers/radeon/R600IntrinsicsNoOpenCL.td   |   10 ++
 src/gallium/drivers/radeon/R600IntrinsicsOpenCL.td |   10 ++
 .../drivers/radeon/R600MachineFunctionInfo.cpp |   19 +++-
 .../drivers/radeon/R600MachineFunctionInfo.h   |5 +
 10 files changed, 318 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp 
b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
index d6304a2..04dadc3 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.cpp
@@ -346,5 +346,7 @@ const char* 
AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const
   NODE_NAME_CASE(SMIN)
   NODE_NAME_CASE(UMIN)
   NODE_NAME_CASE(URECIP)
+  NODE_NAME_CASE(INTERP)
+  NODE_NAME_CASE(INTERP_P0)
   }
 }
diff --git a/src/gallium/drivers/radeon/AMDGPUISelLowering.h 
b/src/gallium/drivers/radeon/AMDGPUISelLowering.h
index a6d2a50..2d8ed82 100644
--- a/src/gallium/drivers/radeon/AMDGPUISelLowering.h
+++ b/src/gallium/drivers/radeon/AMDGPUISelLowering.h
@@ -119,6 +119,8 @@ enum
   SMIN,
   UMIN,
   URECIP,
+  INTERP,
+  INTERP_P0,
   LAST_AMDGPU_ISD_NUMBER
 };
 
diff --git a/src/gallium/drivers/radeon/R600ExpandSpecialInstrs.cpp 
b/src/gallium/drivers/radeon/R600ExpandSpecialInstrs.cpp
index 69ab0ff..d6184e5 100644
--- a/src/gallium/drivers/radeon/R600ExpandSpecialInstrs.cpp
+++ b/src/gallium/drivers/radeon/R600ExpandSpecialInstrs.cpp
@@ -15,6 +15,7 @@
 #include "R600Defines.h"
 #include "R600InstrInfo.h"
 #include "R600RegisterInfo.h"
+#include "R600MachineFunctionInfo.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
@@ -29,6 +30,9 @@ private:
   static char ID;
   const R600InstrInfo *TII;
 
+  bool ExpandInputPerspective(MachineInstr& MI);
+  bool ExpandInputConstant(MachineInstr& MI);
+  
 public:
   R600ExpandSpecialInstrsPass(TargetMachine &tm) : MachineFunctionPass(ID),
 TII (static_cast(tm.getInstrInfo())) { }
@@ -48,6 +52,126 @@ FunctionPass 
*llvm::createR600ExpandSpecialInstrsPass(TargetMachine &TM) {
   return new R600ExpandSpecialInstrsPass(TM);
 }
 
+bool R600ExpandSpecialInstrsPass::ExpandInputPerspective(MachineInstr &MI)
+{
+  const R600RegisterInfo &TRI = TII->getRegisterInfo();
+  if (MI.getOpcode() != AMDGPU::input_perspective)
+return false;
+  
+  MachineBasicBlock::iterator I = &MI;
+  unsigned DstReg = MI.getOperand(0).getReg();
+  R600MachineFunctionInfo *MFI = MI.getParent()->getParent()
+  ->getInfo();
+  unsigned IJIndexBase;
+  
+  // In Evergreen ISA doc section 8.3.2 :
+  // We need to interpolate XY and ZW in two different instruction groups.
+  // An INTERP_* must occupy all 4 slots of an instruction group.
+  // Output of INTERP_XY is written in X,Y slots
+  // Output of INTERP_ZW is written in Z,W slots
+  //
+  // Thus interpolation requires the following sequences :
+  //
+  // AnyGPR.x = INTERP_ZW; (Write Masked Out)
+  // AnyGPR.y = INTERP_ZW; (Write Masked Out)
+  // DstGPR.z = INTERP_ZW;
+  // DstGPR.w = INTERP_ZW; (End of first IG)
+  // DstGPR.x = INTERP_XY;
+  // DstGPR.y = INTERP_XY;
+  // AnyGPR.z = INTERP_XY; (Write Masked Out)
+  // AnyGPR.w = INTERP_XY; (Write Masked Out) (End of second IG)
+  //
+  switch (MI.getOperand(1).getImm()) {
+  case 0:
+IJIndexBase = MFI->GetIJPerspectiveIndex();
+break;
+  case 1:
+IJIndexBase = MFI->GetIJLinearIndex();
+break;
+  default:
+assert(0 && "Unknow ij index");
+  }
+
+  for (unsigned i = 0; i < 8; i++) {
+unsigned IJIndex = AMDGPU::R600_TReg32RegClass.getRegister(
+2 * IJIndexBase + ((i + 1) % 2));
+unsigned ReadReg = AMDGPU::R600_TReg32RegClass.getRegister(
+4 * MI.getOperand(2).getImm());
+
+unsigned Sel;
+switch (i % 4) {
+case 0:Sel = AMDGPU::sel_x;break;
+case 1:Sel = AMDGPU::sel_y;break;
+case 2:Sel = AMDGPU::sel_z;break;
+case 3:Sel = AMDGPU::sel_w;break;
+default:break;
+}
+ 
+unsigned Res = TRI.getSubReg(DstReg, Sel);
+ 
+const MCInstrDesc &Opcode = (i < 4)?
+  

Mesa (master): radeon/llvm: reserve also corresponding 128bits reg

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 12c4526157ab029fd8c0b402d190cf5f7723b555
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=12c4526157ab029fd8c0b402d190cf5f7723b555

Author: Vincent Lejeune 
Date:   Tue Sep 11 17:56:39 2012 +0200

radeon/llvm: reserve also corresponding 128bits reg

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/radeon/R600RegisterInfo.cpp |1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/src/gallium/drivers/radeon/R600RegisterInfo.cpp 
b/src/gallium/drivers/radeon/R600RegisterInfo.cpp
index ef6bf87..4096cb0 100644
--- a/src/gallium/drivers/radeon/R600RegisterInfo.cpp
+++ b/src/gallium/drivers/radeon/R600RegisterInfo.cpp
@@ -50,6 +50,7 @@ BitVector R600RegisterInfo::getReservedRegs(const 
MachineFunction &MF) const
   for (std::vector::const_iterator I = MFI->ReservedRegs.begin(),
 E = MFI->ReservedRegs.end(); I != E; ++I) {
 Reserved.set(*I);
+Reserved.set(*(getSuperRegisters(*I)));
   }
 
   return Reserved;

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Mesa (master): radeon/llvm: Add a fdiv pattern.

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 175fdd7b86cce4e1fc945058fa2223b77edbf8a6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=175fdd7b86cce4e1fc945058fa2223b77edbf8a6

Author: Vincent Lejeune 
Date:   Mon Sep 17 22:20:18 2012 +0200

radeon/llvm: Add a fdiv pattern.

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/radeon/R600Instructions.td |   13 ++---
 1 files changed, 10 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeon/R600Instructions.td 
b/src/gallium/drivers/radeon/R600Instructions.td
index 8d2f137..e2f8d33 100644
--- a/src/gallium/drivers/radeon/R600Instructions.td
+++ b/src/gallium/drivers/radeon/R600Instructions.td
@@ -702,11 +702,18 @@ class COS_Common  inst> : R600_1OP <
 // Helper patterns for complex intrinsics
 
//===--===//
 
-class DIV_Common  : Pat<
+multiclass DIV_Common  {
+def : Pat<
   (int_AMDGPU_div R600_Reg32:$src0, R600_Reg32:$src1),
   (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
 >;
 
+def : Pat<
+  (fdiv R600_Reg32:$src0, R600_Reg32:$src1),
+  (MUL R600_Reg32:$src0, (recip_ieee R600_Reg32:$src1))
+>;
+}
+
 class SSG_Common  : Pat <
   (int_AMDGPU_ssg R600_Reg32:$src),
   (cndgt R600_Reg32:$src, (f32 ONE), (cndge R600_Reg32:$src, (f32 ZERO), (f32 
NEG_ONE)))
@@ -753,7 +760,7 @@ let Predicates = [isR600] in {
   def MULHI_UINT_r600 : MULHI_UINT_Common<0x76>;
   def RECIP_UINT_r600 : RECIP_UINT_Common <0x78>;
 
-  def DIV_r600 : DIV_Common;
+  defm DIV_r600 : DIV_Common;
   def POW_r600 : POW_Common;
   def SSG_r600 : SSG_Common;
   def TGSI_LIT_Z_r600 : TGSI_LIT_Z_Common;
@@ -849,7 +856,7 @@ let Predicates = [isEGorCayman] in {
   def : DOT4_Pat ;
   defm CUBE_eg : CUBE_Common<0xC0>;
 
-  def DIV_eg : DIV_Common;
+  defm DIV_eg : DIV_Common;
   def POW_eg : POW_Common;
   def SSG_eg : SSG_Common;
   def TGSI_LIT_Z_eg : TGSI_LIT_Z_Common;

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Mesa (master): radeon/llvm: custom lowering for FP_TO_UINT when dst is i1 ( bool)

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: a4325b32298cb99b1e99620a33ef0bee52298c3c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4325b32298cb99b1e99620a33ef0bee52298c3c

Author: Vincent Lejeune 
Date:   Tue Sep  4 17:29:48 2012 +0200

radeon/llvm: custom lowering for FP_TO_UINT when dst is i1 (bool)

v2:-wrap line at 80 characters

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/radeon/R600ISelLowering.cpp |   22 ++
 src/gallium/drivers/radeon/R600ISelLowering.h   |6 --
 2 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp 
b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index 7ad0178..79cd622 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -48,6 +48,7 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
 
   setOperationAction(ISD::SETCC, MVT::i32, Custom);
   setOperationAction(ISD::SETCC, MVT::f32, Custom);
+  setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
   setSchedulingPreference(Sched::VLIW);
 }
 
@@ -330,6 +331,27 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op, 
SelectionDAG &DAG) const
   return SDValue();
 }
 
+void R600TargetLowering::ReplaceNodeResults(SDNode *N,
+SmallVectorImpl &Results, 
+SelectionDAG &DAG) const
+{
+  switch (N->getOpcode()) {
+  default: return;
+  case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0), 
DAG));
+  }
+}
+
+SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const
+{
+  return DAG.getNode(
+  ISD::SETCC,
+  Op.getDebugLoc(),
+  MVT::i1,
+  Op, DAG.getConstantFP(0.0f, MVT::f32),
+  DAG.getCondCode(ISD::SETNE)
+  );
+}
+
 SDValue R600TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
 {
   SDValue Chain = Op.getOperand(0);
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.h 
b/src/gallium/drivers/radeon/R600ISelLowering.h
index 2eb7edd..49ea272 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.h
+++ b/src/gallium/drivers/radeon/R600ISelLowering.h
@@ -27,7 +27,9 @@ public:
   virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI,
   MachineBasicBlock * BB) const;
   virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
-
+  void ReplaceNodeResults(SDNode * N,
+  SmallVectorImpl &Results,
+  SelectionDAG &DAG) const;
 private:
   const R600InstrInfo * TII;
 
@@ -48,7 +50,7 @@ private:
 
   SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
-
+  SDValue LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const;
 };
 
 } // End namespace llvm;

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Mesa (master): radeon/llvm: do not convert f32 operand of select_cc node

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 8eaa36317a0a2911cb78066947bc841dd8ce86c8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8eaa36317a0a2911cb78066947bc841dd8ce86c8

Author: Vincent Lejeune 
Date:   Tue Sep  4 17:28:26 2012 +0200

radeon/llvm: do not convert f32 operand of select_cc node

v2:-use camel coding style

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/radeon/R600ISelLowering.cpp |   40 +++---
 1 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp 
b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index 79cd622..5642ee8 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -441,32 +441,32 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op, 
SelectionDAG &DAG) const
   // necessary we need to convert LHS and RHS to be the same type True and
   // False.  True and False are guaranteed to have the same type as this
   // SELECT_CC node.
-
-  if (CompareVT !=  VT) {
-ISD::NodeType ConversionOp = ISD::DELETED_NODE;
-if (VT == MVT::f32 && CompareVT == MVT::i32) {
-  if (isUnsignedIntSetCC(CCOpcode)) {
-ConversionOp = ISD::UINT_TO_FP;
+  
+  if (isHWTrueValue(True) && isHWFalseValue(False)) {
+if (CompareVT !=  VT) {
+  if (VT == MVT::f32 && CompareVT == MVT::i32) {
+SDValue Boolean = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
+LHS, RHS,
+DAG.getConstant(-1, MVT::i32),
+DAG.getConstant(0, MVT::i32),
+CC);
+return DAG.getNode(ISD::UINT_TO_FP, DL, VT, Boolean);
+  } else if (VT == MVT::i32 && CompareVT == MVT::f32) {
+SDValue BoolAsFlt = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
+LHS, RHS,
+DAG.getConstantFP(1.0f, MVT::f32),
+DAG.getConstantFP(0.0f, MVT::f32),
+CC);
+return DAG.getNode(ISD::FP_TO_UINT, DL, VT, BoolAsFlt);
   } else {
-ConversionOp = ISD::SINT_TO_FP;
+// I don't think there will be any other type pairings.
+assert(!"Unhandled operand type parings in SELECT_CC");
   }
-} else if (VT == MVT::i32 && CompareVT == MVT::f32) {
-  ConversionOp = ISD::FP_TO_SINT;
 } else {
-  // I don't think there will be any other type pairings.
-  assert(!"Unhandled operand type parings in SELECT_CC");
+  return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
 }
-// XXX Check the value of LHS and RHS and avoid creating sequences like
-// (FTOI (ITOF))
-LHS = DAG.getNode(ConversionOp, DL, VT, LHS);
-RHS = DAG.getNode(ConversionOp, DL, VT, RHS);
   }
 
-  // If True is a hardware TRUE value and False is a hardware FALSE value or
-  // vice-versa we can handle this with a native instruction (SET* 
instructions).
-  if ((isHWTrueValue(True) && isHWFalseValue(False))) {
-return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
-  }
 
   // XXX If True is a hardware TRUE value and False is a hardware FALSE value,
   // we can handle this with a native instruction, but we need to swap true

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Mesa (master): radeon/llvm: support setcc on f32

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: d9e135e18cb438aad4b0bdf89a7273d705549150
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d9e135e18cb438aad4b0bdf89a7273d705549150

Author: Vincent Lejeune 
Date:   Tue Sep  4 17:04:28 2012 +0200

radeon/llvm: support setcc on f32

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/radeon/R600ISelLowering.cpp |   36 +--
 1 files changed, 27 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp 
b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index 016befa..7ad0178 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -47,7 +47,7 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
   setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
 
   setOperationAction(ISD::SETCC, MVT::i32, Custom);
-
+  setOperationAction(ISD::SETCC, MVT::f32, Custom);
   setSchedulingPreference(Sched::VLIW);
 }
 
@@ -519,14 +519,32 @@ SDValue R600TargetLowering::LowerSETCC(SDValue Op, 
SelectionDAG &DAG) const
   SDValue CC  = Op.getOperand(2);
   DebugLoc DL = Op.getDebugLoc();
   assert(Op.getValueType() == MVT::i32);
-  Cond = DAG.getNode(
-  ISD::SELECT_CC,
-  Op.getDebugLoc(),
-  MVT::i32,
-  LHS, RHS,
-  DAG.getConstant(-1, MVT::i32),
-  DAG.getConstant(0, MVT::i32),
-  CC);
+  if (LHS.getValueType() == MVT::i32) {
+Cond = DAG.getNode(
+ISD::SELECT_CC,
+Op.getDebugLoc(),
+MVT::i32,
+LHS, RHS,
+DAG.getConstant(-1, MVT::i32),
+DAG.getConstant(0, MVT::i32),
+CC);
+  } else if (LHS.getValueType() == MVT::f32) {
+Cond = DAG.getNode(
+ISD::SELECT_CC,
+Op.getDebugLoc(),
+MVT::f32,
+LHS, RHS,
+DAG.getConstantFP(1.0f, MVT::f32),
+DAG.getConstantFP(0.0f, MVT::f32),
+CC);
+Cond = DAG.getNode(
+ISD::FP_TO_SINT,
+DL,
+MVT::i32,
+Cond);
+  } else {
+assert(0 && "Not valid type for set_cc");
+  }
   Cond = DAG.getNode(
   ISD::AND,
   DL,

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Mesa (master): radon/llvm: br_cc f32 now lowered without cast

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: a383142436a21403dd19abb25a654fc634770c74
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a383142436a21403dd19abb25a654fc634770c74

Author: Vincent Lejeune 
Date:   Tue Sep  4 17:04:27 2012 +0200

radon/llvm: br_cc f32 now lowered without cast

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/radeon/R600ISelLowering.cpp |   33 --
 1 files changed, 24 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp 
b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index 7c93935..016befa 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -34,7 +34,8 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
   computeRegisterProperties();
 
   setOperationAction(ISD::BR_CC, MVT::i32, Custom);
-
+  setOperationAction(ISD::BR_CC, MVT::f32, Custom);
+  
   setOperationAction(ISD::FSUB, MVT::f32, Expand);
 
   setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
@@ -338,14 +339,28 @@ SDValue R600TargetLowering::LowerBR_CC(SDValue Op, 
SelectionDAG &DAG) const
   SDValue JumpT  = Op.getOperand(4);
   SDValue CmpValue;
   SDValue Result;
-  CmpValue = DAG.getNode(
-  ISD::SELECT_CC,
-  Op.getDebugLoc(),
-  MVT::i32,
-  LHS, RHS,
-  DAG.getConstant(-1, MVT::i32),
-  DAG.getConstant(0, MVT::i32),
-  CC);
+  
+  if (LHS.getValueType() == MVT::i32) {
+CmpValue = DAG.getNode(
+ISD::SELECT_CC,
+Op.getDebugLoc(),
+MVT::i32,
+LHS, RHS,
+DAG.getConstant(-1, MVT::i32),
+DAG.getConstant(0, MVT::i32),
+CC);
+  } else if (LHS.getValueType() == MVT::f32) {
+CmpValue = DAG.getNode(
+ISD::SELECT_CC,
+Op.getDebugLoc(),
+MVT::f32,
+LHS, RHS,
+DAG.getConstantFP(1.0f, MVT::f32),
+DAG.getConstantFP(0.0f, MVT::f32),
+CC);
+  } else {
+assert(0 && "Not valid type for br_cc");
+  }
   Result = DAG.getNode(
   AMDGPUISD::BRANCH_COND,
   CmpValue.getDebugLoc(),

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Mesa (master): radeon/llvm: swap wrong OPCODE_IS_*_ZERO_* opcode and use

[Vincent Lejeune]

Module: Mesa
Branch: master
Commit: 6a85725f136862d8877dc76369c64e0c8b5ea4e6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a85725f136862d8877dc76369c64e0c8b5ea4e6

Author: Vincent Lejeune 
Date:   Tue Sep  4 16:49:25 2012 +0200

radeon/llvm: swap wrong OPCODE_IS_*_ZERO_* opcode and use

Reviewed-by: Tom Stellard 

---

 src/gallium/drivers/radeon/AMDGPUInstrInfo.h|4 ++--
 src/gallium/drivers/radeon/R600ISelLowering.cpp |4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h 
b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
index 2643119..a308076 100644
--- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
+++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h
@@ -25,8 +25,8 @@
 #define GET_INSTRINFO_ENUM
 #include "AMDGPUGenInstrInfo.inc"
 
-#define OPCODE_IS_ZERO_INT 0x0045
-#define OPCODE_IS_NOT_ZERO_INT 0x0042
+#define OPCODE_IS_ZERO_INT 0x0042
+#define OPCODE_IS_NOT_ZERO_INT 0x0045
 #define OPCODE_IS_ZERO 0x0020
 #define OPCODE_IS_NOT_ZERO 0x0023
 
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp 
b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index fec9d4e..7c93935 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -207,7 +207,7 @@ MachineBasicBlock * 
R600TargetLowering::EmitInstrWithCustomInserter(
 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X))
 .addReg(AMDGPU::PREDICATE_BIT)
 .addOperand(MI->getOperand(1))
-.addImm(OPCODE_IS_ZERO)
+.addImm(OPCODE_IS_NOT_ZERO)
 .addImm(0); // Flags
   TII->addFlag(NewMI, 1, MO_FLAG_PUSH);
   BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))
@@ -221,7 +221,7 @@ MachineBasicBlock * 
R600TargetLowering::EmitInstrWithCustomInserter(
 BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X))
   .addReg(AMDGPU::PREDICATE_BIT)
   .addOperand(MI->getOperand(1))
-  .addImm(OPCODE_IS_ZERO_INT)
+  .addImm(OPCODE_IS_NOT_ZERO_INT)
   .addImm(0); // Flags
   TII->addFlag(NewMI, 1, MO_FLAG_PUSH);
   BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP))

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