Mesa (8.0): i965: fix wrong cube/3D texture layout
Module: Mesa
Branch: 8.0
Commit: fa68a8bae3961808288cfd84d5a7843f6fc0f317
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa68a8bae3961808288cfd84d5a7843f6fc0f317
Author: Yuanhan Liu
Date: Wed May 2 17:29:11 2012 +0800
i965: fix wrong cube/3D texture layout
Fix wrong cube/3D texture layout for the tailing levels whose width or
height is smaller than the align unit.
>From 965 B-spec http://intellinuxgraphics.org/VOL_1_graphics_core.pdf at
page 135:
All of the LOD=0 q-planes are stacked vertically, then below that,
the LOD=1 qplanes are stacked two-wide, then the LOD=2 qplanes are
stacked four-wide below that, and so on.
Thus we should always inrease pack_x_nr, which results to the pitch of LODn
may greater than the pitch of LOD0. So we should refactor mt->total_width
when needed.
This would fix the following webgl test case on all gen4 platforms:
conformance/textures/texture-size-cube-maps.html
NOTE: This is a candidate for stable release branches.
Signed-off-by: Yuanhan Liu
(cherry picked from commit f939776cb2372a3427784f88d34bf14c18a5a212)
---
src/mesa/drivers/dri/i965/brw_tex_layout.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 7a1b91f..8bf1d3d 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -115,6 +115,8 @@ brw_miptree_layout(struct intel_context *intel, struct
intel_mipmap_tree *mt)
intel_miptree_set_image_offset(mt, level, q, x, y);
x += pack_x_pitch;
}
+if (x > mt->total_width)
+ mt->total_width = x;
x = 0;
y += pack_y_pitch;
@@ -135,10 +137,9 @@ brw_miptree_layout(struct intel_context *intel, struct
intel_mipmap_tree *mt)
pack_x_nr <<= 1;
}
} else {
+pack_x_nr <<= 1;
if (pack_x_pitch > 4) {
pack_x_pitch >>= 1;
- pack_x_nr <<= 1;
- assert(pack_x_pitch * pack_x_nr <= mt->total_width);
}
if (pack_y_pitch > 2) {
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Mesa (master): i965: fix wrong cube/3D texture layout
Module: Mesa
Branch: master
Commit: f939776cb2372a3427784f88d34bf14c18a5a212
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f939776cb2372a3427784f88d34bf14c18a5a212
Author: Yuanhan Liu
Date: Wed May 2 17:29:11 2012 +0800
i965: fix wrong cube/3D texture layout
Fix wrong cube/3D texture layout for the tailing levels whose width or
height is smaller than the align unit.
>From 965 B-spec http://intellinuxgraphics.org/VOL_1_graphics_core.pdf at
page 135:
All of the LOD=0 q-planes are stacked vertically, then below that,
the LOD=1 qplanes are stacked two-wide, then the LOD=2 qplanes are
stacked four-wide below that, and so on.
Thus we should always inrease pack_x_nr, which results to the pitch of LODn
may greater than the pitch of LOD0. So we should refactor mt->total_width
when needed.
This would fix the following webgl test case on all gen4 platforms:
conformance/textures/texture-size-cube-maps.html
NOTE: This is a candidate for stable release branches.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i965/brw_tex_layout.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 7a1b91f..8bf1d3d 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -115,6 +115,8 @@ brw_miptree_layout(struct intel_context *intel, struct
intel_mipmap_tree *mt)
intel_miptree_set_image_offset(mt, level, q, x, y);
x += pack_x_pitch;
}
+if (x > mt->total_width)
+ mt->total_width = x;
x = 0;
y += pack_y_pitch;
@@ -135,10 +137,9 @@ brw_miptree_layout(struct intel_context *intel, struct
intel_mipmap_tree *mt)
pack_x_nr <<= 1;
}
} else {
+pack_x_nr <<= 1;
if (pack_x_pitch > 4) {
pack_x_pitch >>= 1;
- pack_x_nr <<= 1;
- assert(pack_x_pitch * pack_x_nr <= mt->total_width);
}
if (pack_y_pitch > 2) {
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Mesa (8.0): i915: set SPRITE_POINT_ENABLE bit correctly
Module: Mesa
Branch: 8.0
Commit: 9f150ffe8ee5f184861a377637091e4f06210927
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f150ffe8ee5f184861a377637091e4f06210927
Author: Yuanhan Liu
Date: Sat Mar 17 10:48:23 2012 +0800
i915: set SPRITE_POINT_ENABLE bit correctly
When SPRITE_POINT_ENABLE bit is set, the texture coord would be
replaced, and this is only needed when we called something like
glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE).
And more, we currently handle varying inputs as texture coord,
we would be careful when setting this bit and set it just when
needed, or you will find the value of varying input is not right
and changed.
Thus we do set SPRITE_POINT_ENABLE bit only when all enabled tex
coord units need do CoordReplace. Or fallback is needed to make
sure the rendering is right.
With handling the bit setup at i915_update_sprite_point_enable(),
we don't need the relative code at i915Enable then.
This patch would _really_ fix the webglc point-size.html test case and
of course, not regress piglit point-sprite and glean-pointSprite
testcase.
NOTE: This is a candidate for stable release branches.
v2: fallback just when all enabled tex coord units need do
CoordReplace (Eric)
v3: move the sprite point validate code at I915InvalidateState (Eric)
v4: sprite point enable bit update based on _NEW_PROGRAM, too
add relative _NEW-state comments to show what state is being used(Eric)
Signed-off-by: Yuanhan Liu
(cherry picked from commit c6532875493ffe7de9c37924c70ebf6d0472e23d)
---
src/mesa/drivers/dri/i915/i915_context.c |2 +
src/mesa/drivers/dri/i915/i915_context.h |2 +
src/mesa/drivers/dri/i915/i915_state.c | 55 +++--
src/mesa/drivers/dri/i915/intel_tris.c |1 +
4 files changed, 48 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i915_context.c
b/src/mesa/drivers/dri/i915/i915_context.c
index 36563ef..dc32292 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -76,6 +76,8 @@ i915InvalidateState(struct gl_context * ctx, GLuint new_state)
i915_update_provoking_vertex(ctx);
if (new_state & (_NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS))
i915_update_program(ctx);
+ if (new_state & (_NEW_PROGRAM | _NEW_POINT))
+ i915_update_sprite_point_enable(ctx);
}
diff --git a/src/mesa/drivers/dri/i915/i915_context.h
b/src/mesa/drivers/dri/i915/i915_context.h
index 8167137..7037465 100644
--- a/src/mesa/drivers/dri/i915/i915_context.h
+++ b/src/mesa/drivers/dri/i915/i915_context.h
@@ -40,6 +40,7 @@
#define I915_FALLBACK_POINT_SMOOTH 0x8
#define I915_FALLBACK_POINT_SPRITE_COORD_ORIGIN 0x10
#define I915_FALLBACK_DRAW_OFFSET 0x20
+#define I915_FALLBACK_COORD_REPLACE 0x40
#define I915_UPLOAD_CTX 0x1
#define I915_UPLOAD_BUFFERS 0x2
@@ -338,6 +339,7 @@ extern void i915InitStateFunctions(struct dd_function_table
*functions);
extern void i915InitState(struct i915_context *i915);
extern void i915_update_stencil(struct gl_context * ctx);
extern void i915_update_provoking_vertex(struct gl_context *ctx);
+extern void i915_update_sprite_point_enable(struct gl_context *ctx);
/*==
diff --git a/src/mesa/drivers/dri/i915/i915_state.c
b/src/mesa/drivers/dri/i915/i915_state.c
index 756001f..94c7327 100644
--- a/src/mesa/drivers/dri/i915/i915_state.c
+++ b/src/mesa/drivers/dri/i915/i915_state.c
@@ -652,6 +652,48 @@ i915PointParameterfv(struct gl_context * ctx, GLenum
pname, const GLfloat *param
}
}
+void
+i915_update_sprite_point_enable(struct gl_context *ctx)
+{
+ struct intel_context *intel = intel_context(ctx);
+ /* _NEW_PROGRAM */
+ struct i915_fragment_program *p =
+ (struct i915_fragment_program *) ctx->FragmentProgram._Current;
+ const GLbitfield64 inputsRead = p->FragProg.Base.InputsRead;
+ struct i915_context *i915 = i915_context(ctx);
+ GLuint s4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_VFMT_MASK;
+ int i;
+ GLuint coord_replace_bits = 0x0;
+ GLuint tex_coord_unit_bits = 0x0;
+
+ for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) {
+ /* _NEW_POINT */
+ if (ctx->Point.CoordReplace[i] && ctx->Point.PointSprite)
+ coord_replace_bits |= (1 << i);
+ if (inputsRead & FRAG_BIT_TEX(i))
+ tex_coord_unit_bits |= (1 << i);
+ }
+
+ /*
+* Here we can't enable the SPRITE_POINT_ENABLE bit when the mis-match
+* of tex_coord_unit_bits and coord_replace_bits, or this will make all
+* the other non-point-sprite coords(like varying inputs, as we now use
+* tex coord to implement varying inputs) be replaced to value (0, 0)-(1,
1).
+*
+* Thus, do fallback when needed.
+*/
+ FALLBACK(intel, I915_FALLBACK_COORD_REPLACE,
+coord_r
Mesa (master): i915: set SPRITE_POINT_ENABLE bit correctly
Module: Mesa
Branch: master
Commit: c6532875493ffe7de9c37924c70ebf6d0472e23d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c6532875493ffe7de9c37924c70ebf6d0472e23d
Author: Yuanhan Liu
Date: Sat Mar 17 10:48:23 2012 +0800
i915: set SPRITE_POINT_ENABLE bit correctly
When SPRITE_POINT_ENABLE bit is set, the texture coord would be
replaced, and this is only needed when we called something like
glTexEnvi(GL_POINT_SPRITE, GL_COORD_REPLACE, GL_TRUE).
And more, we currently handle varying inputs as texture coord,
we would be careful when setting this bit and set it just when
needed, or you will find the value of varying input is not right
and changed.
Thus we do set SPRITE_POINT_ENABLE bit only when all enabled tex
coord units need do CoordReplace. Or fallback is needed to make
sure the rendering is right.
With handling the bit setup at i915_update_sprite_point_enable(),
we don't need the relative code at i915Enable then.
This patch would _really_ fix the webglc point-size.html test case and
of course, not regress piglit point-sprite and glean-pointSprite
testcase.
NOTE: This is a candidate for stable release branches.
v2: fallback just when all enabled tex coord units need do
CoordReplace (Eric)
v3: move the sprite point validate code at I915InvalidateState (Eric)
v4: sprite point enable bit update based on _NEW_PROGRAM, too
add relative _NEW-state comments to show what state is being used(Eric)
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/i915/i915_context.c |2 +
src/mesa/drivers/dri/i915/i915_context.h |2 +
src/mesa/drivers/dri/i915/i915_state.c | 55 +++--
src/mesa/drivers/dri/i915/intel_tris.c |1 +
4 files changed, 48 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i915_context.c
b/src/mesa/drivers/dri/i915/i915_context.c
index 36563ef..dc32292 100644
--- a/src/mesa/drivers/dri/i915/i915_context.c
+++ b/src/mesa/drivers/dri/i915/i915_context.c
@@ -76,6 +76,8 @@ i915InvalidateState(struct gl_context * ctx, GLuint new_state)
i915_update_provoking_vertex(ctx);
if (new_state & (_NEW_PROGRAM | _NEW_PROGRAM_CONSTANTS))
i915_update_program(ctx);
+ if (new_state & (_NEW_PROGRAM | _NEW_POINT))
+ i915_update_sprite_point_enable(ctx);
}
diff --git a/src/mesa/drivers/dri/i915/i915_context.h
b/src/mesa/drivers/dri/i915/i915_context.h
index 8167137..7037465 100644
--- a/src/mesa/drivers/dri/i915/i915_context.h
+++ b/src/mesa/drivers/dri/i915/i915_context.h
@@ -40,6 +40,7 @@
#define I915_FALLBACK_POINT_SMOOTH 0x8
#define I915_FALLBACK_POINT_SPRITE_COORD_ORIGIN 0x10
#define I915_FALLBACK_DRAW_OFFSET 0x20
+#define I915_FALLBACK_COORD_REPLACE 0x40
#define I915_UPLOAD_CTX 0x1
#define I915_UPLOAD_BUFFERS 0x2
@@ -338,6 +339,7 @@ extern void i915InitStateFunctions(struct dd_function_table
*functions);
extern void i915InitState(struct i915_context *i915);
extern void i915_update_stencil(struct gl_context * ctx);
extern void i915_update_provoking_vertex(struct gl_context *ctx);
+extern void i915_update_sprite_point_enable(struct gl_context *ctx);
/*==
diff --git a/src/mesa/drivers/dri/i915/i915_state.c
b/src/mesa/drivers/dri/i915/i915_state.c
index 756001f..94c7327 100644
--- a/src/mesa/drivers/dri/i915/i915_state.c
+++ b/src/mesa/drivers/dri/i915/i915_state.c
@@ -652,6 +652,48 @@ i915PointParameterfv(struct gl_context * ctx, GLenum
pname, const GLfloat *param
}
}
+void
+i915_update_sprite_point_enable(struct gl_context *ctx)
+{
+ struct intel_context *intel = intel_context(ctx);
+ /* _NEW_PROGRAM */
+ struct i915_fragment_program *p =
+ (struct i915_fragment_program *) ctx->FragmentProgram._Current;
+ const GLbitfield64 inputsRead = p->FragProg.Base.InputsRead;
+ struct i915_context *i915 = i915_context(ctx);
+ GLuint s4 = i915->state.Ctx[I915_CTXREG_LIS4] & ~S4_VFMT_MASK;
+ int i;
+ GLuint coord_replace_bits = 0x0;
+ GLuint tex_coord_unit_bits = 0x0;
+
+ for (i = 0; i < ctx->Const.MaxTextureCoordUnits; i++) {
+ /* _NEW_POINT */
+ if (ctx->Point.CoordReplace[i] && ctx->Point.PointSprite)
+ coord_replace_bits |= (1 << i);
+ if (inputsRead & FRAG_BIT_TEX(i))
+ tex_coord_unit_bits |= (1 << i);
+ }
+
+ /*
+* Here we can't enable the SPRITE_POINT_ENABLE bit when the mis-match
+* of tex_coord_unit_bits and coord_replace_bits, or this will make all
+* the other non-point-sprite coords(like varying inputs, as we now use
+* tex coord to implement varying inputs) be replaced to value (0, 0)-(1,
1).
+*
+* Thus, do fallback when needed.
+*/
+ FALLBACK(intel, I915_FALLBACK_COORD_REPLACE,
+coord_replace_bits && coord_replace_bits != tex_coord_unit_bits);
+
+ s4 &
Mesa (master): glx: fix compile warnings
Module: Mesa
Branch: master
Commit: 8b5b3b93d73d80a54d12d0d7a6a74fb97b27bf8a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b5b3b93d73d80a54d12d0d7a6a74fb97b27bf8a
Author: Yuanhan Liu
Date: Wed Mar 28 10:09:55 2012 +0800
glx: fix compile warnings
Fix 'set but not used' warnings; gl_version, gl_versions_profiles and
glx_extensions variables are used just only HAVE_XCB_GLX_CREATE_CONTEXT
is defined. Thus those warnings are shown when that macro isn't defined.
Signed-off-by: Yuanhan Liu
---
src/glx/clientinfo.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/src/glx/clientinfo.c b/src/glx/clientinfo.c
index 461030f..97d43ce 100644
--- a/src/glx/clientinfo.c
+++ b/src/glx/clientinfo.c
@@ -39,6 +39,7 @@ __glX_send_client_info(struct glx_display *glx_dpy)
Bool any_screen_has_ARB_create_context = False;
Bool any_screen_has_ARB_create_context_profile = False;
unsigned i;
+#ifdef HAVE_XCB_GLX_CREATE_CONTEXT
static const uint32_t gl_versions[] = {
1, 4,
};
@@ -47,6 +48,7 @@ __glX_send_client_info(struct glx_display *glx_dpy)
};
static const char glx_extensions[] =
"GLX_ARB_create_context GLX_ARB_create_context_profile";
+#endif
/* There are three possible flavors of the client info structure that the
* client could send to the server. The version sent depends on the
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Mesa (master): intel: fix un-blanced map_refcount issue
Module: Mesa
Branch: master
Commit: 9cb777eb71dde895ca0ad3454a9b44252e9b402e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9cb777eb71dde895ca0ad3454a9b44252e9b402e
Author: Yuanhan Liu
Date: Tue Mar 27 15:41:52 2012 +0800
intel: fix un-blanced map_refcount issue
This is a regression introduced by commit cdcfd5, which forget to
increase the map_refcount for successfully-mapped region. Thus caused a
wrong non-blanced map_refcount.
This would fix the regression found in the two following webglc testcase
on Pineview platform:
texture-npot.html
gl-max-texture-dimensions.html
Cc: Anuj Phogat
Signed-off-by: Yuanhan Liu
Reviewed-by: Anuj Phogat
---
src/mesa/drivers/dri/intel/intel_regions.c |8
1 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_regions.c
b/src/mesa/drivers/dri/intel/intel_regions.c
index d2b737b..abea2bd 100644
--- a/src/mesa/drivers/dri/intel/intel_regions.c
+++ b/src/mesa/drivers/dri/intel/intel_regions.c
@@ -133,10 +133,10 @@ intel_region_map(struct intel_context *intel, struct
intel_region *region,
drm_intel_bo_map(region->bo, true);
region->map = region->bo->virtual;
- if (region->map) {
- intel->num_mapped_regions++;
- region->map_refcount++;
- }
+ }
+ if (region->map) {
+ intel->num_mapped_regions++;
+ region->map_refcount++;
}
return region->map;
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Mesa (master): glx:dri_common.c: check psc->driScreen-> createDrawable return value
Module: Mesa
Branch: master
Commit: 7a6324dbfe8d354b9b5f3181af0ce6bebbb374cc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7a6324dbfe8d354b9b5f3181af0ce6bebbb374cc
Author: Wang YanQing
Date: Tue Mar 20 11:49:42 2012 +0800
glx:dri_common.c: check psc->driScreen->createDrawable return value
createDrawable may return NULL value, we should check it, or it will
make a segment failed.
[minor-indent-issue-fixed-by: Yuanhan Liu]
Signed-off-by: Wang YanQing
Reviewed-by: Yuanhan Liu
---
src/glx/dri_common.c |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/src/glx/dri_common.c b/src/glx/dri_common.c
index 0e06d51..07fd015 100644
--- a/src/glx/dri_common.c
+++ b/src/glx/dri_common.c
@@ -403,6 +403,12 @@ driFetchDrawable(struct glx_context *gc, GLXDrawable
glxDrawable)
pdraw = psc->driScreen->createDrawable(psc, glxDrawable,
glxDrawable, gc->config);
+
+ if (pdraw == NULL) {
+ ErrorMessageF("failed to create drawable\n");
+ return NULL;
+ }
+
if (__glxHashInsert(priv->drawHash, glxDrawable, pdraw)) {
(*pdraw->destroyDrawable) (pdraw);
return NULL;
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Mesa (8.0): i915: fallback for NPOT cubemap texture
Module: Mesa Branch: 8.0 Commit: adcb1806717f90f6acff2169a4a434997f433597 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=adcb1806717f90f6acff2169a4a434997f433597 Author: Yuanhan Liu Date: Wed Feb 29 15:04:45 2012 +0800 i915: fallback for NPOT cubemap texture Although some hardware support NPOT cubemap, but it seems we don't know the right layout for NPOT cubemap. Thus seems we need do fallback for other platforms as well. See comments inline the code for more detailed info. v2: give a more detailed info about why we need fallback for other platfroms as well. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=4 NOTE: This is a candidate for stable release branches. Signed-off-by: Yuanhan Liu (cherry picked from commit 40c995c1fd7865f1b25765aa783fdadbf948b3dd) --- src/mesa/drivers/dri/i915/i915_texstate.c | 22 ++ 1 files changed, 22 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index 9022548..fd63a69 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -319,6 +319,28 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) ((wt != GL_CLAMP) && (wt != GL_CLAMP_TO_EDGE return false; + /* + * According to 3DSTATE_MAP_STATE at page of 104 in Bspec + * Vol3d 3D Instructions: + * [DevGDG and DevAlv]: Must be a power of 2 for cube maps. + * [DevLPT, DevCST and DevBLB]: If not a power of 2, cube maps + * must have all faces enabled. + * + * But, as I tested on pineview(DevBLB derived), the rendering is + * bad(you will find the color isn't samplered right in some + * fragments). After checking, it seems that the texture layout is + * wrong: making the width and height align of 4(although this + * doesn't make much sense) will fix this issue and also broke some + * others. Well, Bspec mentioned nothing about the layout alignment + * and layout for NPOT cube map. I guess the Bspec just assume it's + * a POT cube map. + * + * Thus, I guess we need do this for other platforms as well. + */ + if (tObj->Target == GL_TEXTURE_CUBE_MAP_ARB && + !is_power_of_two(firstImage->Height)) + return false; + state[I915_TEXREG_SS3] = ss3; /* SS3_NORMALIZED_COORDS */ state[I915_TEXREG_SS3] |= ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i915: fallback for NPOT cubemap texture
Module: Mesa Branch: master Commit: 40c995c1fd7865f1b25765aa783fdadbf948b3dd URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=40c995c1fd7865f1b25765aa783fdadbf948b3dd Author: Yuanhan Liu Date: Wed Feb 29 15:04:45 2012 +0800 i915: fallback for NPOT cubemap texture Although some hardware support NPOT cubemap, but it seems we don't know the right layout for NPOT cubemap. Thus seems we need do fallback for other platforms as well. See comments inline the code for more detailed info. v2: give a more detailed info about why we need fallback for other platfroms as well. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=4 NOTE: This is a candidate for stable release branches. Signed-off-by: Yuanhan Liu --- src/mesa/drivers/dri/i915/i915_texstate.c | 22 ++ 1 files changed, 22 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i915/i915_texstate.c b/src/mesa/drivers/dri/i915/i915_texstate.c index 9022548..fd63a69 100644 --- a/src/mesa/drivers/dri/i915/i915_texstate.c +++ b/src/mesa/drivers/dri/i915/i915_texstate.c @@ -319,6 +319,28 @@ i915_update_tex_unit(struct intel_context *intel, GLuint unit, GLuint ss3) ((wt != GL_CLAMP) && (wt != GL_CLAMP_TO_EDGE return false; + /* + * According to 3DSTATE_MAP_STATE at page of 104 in Bspec + * Vol3d 3D Instructions: + * [DevGDG and DevAlv]: Must be a power of 2 for cube maps. + * [DevLPT, DevCST and DevBLB]: If not a power of 2, cube maps + * must have all faces enabled. + * + * But, as I tested on pineview(DevBLB derived), the rendering is + * bad(you will find the color isn't samplered right in some + * fragments). After checking, it seems that the texture layout is + * wrong: making the width and height align of 4(although this + * doesn't make much sense) will fix this issue and also broke some + * others. Well, Bspec mentioned nothing about the layout alignment + * and layout for NPOT cube map. I guess the Bspec just assume it's + * a POT cube map. + * + * Thus, I guess we need do this for other platforms as well. + */ + if (tObj->Target == GL_TEXTURE_CUBE_MAP_ARB && + !is_power_of_two(firstImage->Height)) + return false; + state[I915_TEXREG_SS3] = ss3; /* SS3_NORMALIZED_COORDS */ state[I915_TEXREG_SS3] |= ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (8.0): i965: handle gl_PointCoord for Gen4 and Gen5 platforms
Module: Mesa
Branch: 8.0
Commit: 7b1fbc688999fd568e65211d79d7678562061594
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7b1fbc688999fd568e65211d79d7678562061594
Author: Yuanhan Liu
Date: Mon Feb 27 15:46:32 2012 +0800
i965: handle gl_PointCoord for Gen4 and Gen5 platforms
This patch add the support of gl_PointCoord gl builtin variable for
platform gen4 and gen5(ILK).
Unlike gen6+, we don't have a hardware support of gl_PointCoord, means
hardware will not calculate the interpolation coefficient for you.
Instead, you should handle it yourself in sf shader stage.
But badly, gl_PointCoord is a FS instead of VS builtin variable, thus
it's not included in c.vue_map generated in VS stage. Thus the current
code doesn't aware of this attribute. And to handle it correctly, we
need add it to c.vue_map manually to let SF shader generate the needed
interpolation coefficient for FS shader. SF stage has it's own copy of
vue_map, thus I think it's safe to do it manually.
Since handling gl_PointCoord for gen4 and gen5 platforms is somehow a
little special, I added a lot of comments and hope I didn't overdo it ;)
v2: add a /* _NEW_BUFFERS */ comment to note the state flag dependency
and also add the _NEW_BUFFERS dirty mask (Eric).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45975
Piglit: glsl-fs-pointcoord and fbo-gl_pointcoord
NOTE: This is a candidate for stable release branches.
Signed-off-by: Yuanhan Liu
Reviewed-by: Eric Anholt
(cherry picked from commit 43af02ac731dac7d80f7e47feb0c80e4da156769)
---
src/mesa/drivers/dri/i965/brw_context.h |6 ++
src/mesa/drivers/dri/i965/brw_fs.cpp|9 +
src/mesa/drivers/dri/i965/brw_sf.c | 30 +-
src/mesa/drivers/dri/i965/brw_sf.h |1 +
src/mesa/drivers/dri/i965/brw_sf_emit.c |4
5 files changed, 45 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 72e5059..3cfc54b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -290,6 +290,12 @@ typedef enum
BRW_VERT_RESULT_NDC = VERT_RESULT_MAX,
BRW_VERT_RESULT_HPOS_DUPLICATE,
BRW_VERT_RESULT_PAD,
+ /*
+* It's actually not a vert_result but just a _mark_ to let sf aware that
+* he need do something special to handle gl_PointCoord builtin variable
+* correctly. see compile_sf_prog() for more info.
+*/
+ BRW_VERT_RESULT_PNTC,
BRW_VERT_RESULT_MAX
} brw_vert_result;
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 0de1eef..20b57bd 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -710,6 +710,15 @@ fs_visitor::calculate_urb_setup()
urb_setup[fp_index] = urb_next++;
}
}
+
+ /*
+ * It's a FS only attribute, and we did interpolation for this attribute
+ * in SF thread. So, count it here, too.
+ *
+ * See compile_sf_prog() for more info.
+ */
+ if (brw->fragment_program->Base.InputsRead &
BITFIELD64_BIT(FRAG_ATTRIB_PNTC))
+ urb_setup[FRAG_ATTRIB_PNTC] = urb_next++;
}
/* Each attribute is 4 setup channels, each of which is half a reg. */
diff --git a/src/mesa/drivers/dri/i965/brw_sf.c
b/src/mesa/drivers/dri/i965/brw_sf.c
index 54c27f9..ccef3e8 100644
--- a/src/mesa/drivers/dri/i965/brw_sf.c
+++ b/src/mesa/drivers/dri/i965/brw_sf.c
@@ -64,6 +64,16 @@ static void compile_sf_prog( struct brw_context *brw,
c.key = *key;
brw_compute_vue_map(&c.vue_map, intel, c.key.userclip_active, c.key.attrs);
+ if (c.key.do_point_coord) {
+ /*
+ * gl_PointCoord is a FS instead of VS builtin variable, thus it's
+ * not included in c.vue_map generated in VS stage. Here we add
+ * it manually to let SF shader generate the needed interpolation
+ * coefficient for FS shader.
+ */
+ c.vue_map.vert_result_to_slot[BRW_VERT_RESULT_PNTC] =
c.vue_map.num_slots;
+ c.vue_map.slot_to_vert_result[c.vue_map.num_slots++] =
BRW_VERT_RESULT_PNTC;
+ }
c.urb_entry_read_offset = brw_sf_compute_urb_entry_read_offset(intel);
c.nr_attr_regs = (c.vue_map.num_slots + 1)/2 - c.urb_entry_read_offset;
c.nr_setup_regs = c.nr_attr_regs;
@@ -125,6 +135,8 @@ brw_upload_sf_prog(struct brw_context *brw)
{
struct gl_context *ctx = &brw->intel.ctx;
struct brw_sf_prog_key key;
+ /* _NEW_BUFFERS */
+ bool render_to_fbo = ctx->DrawBuffer->Name != 0;
memset(&key, 0, sizeof(key));
@@ -167,7 +179,15 @@ brw_upload_sf_prog(struct brw_context *brw)
key.point_sprite_coord_replace |= (1 << i);
}
}
- key.sprite_origin_lower_left = (ctx->Point.SpriteOrigin == GL_LOWER_LEFT);
+ if (brw->fragment_program->Base.InputsRead &
BITFIELD64_BIT(
Mesa (8.0): i915: move the FALLBACK_DRAW_OFFSET check outside the drawing rect check
Module: Mesa
Branch: 8.0
Commit: 7f8ac0e70f265e1d4ec411e7165255c7270af8c2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7f8ac0e70f265e1d4ec411e7165255c7270af8c2
Author: Yuanhan Liu
Date: Tue Mar 6 14:40:32 2012 +0800
i915: move the FALLBACK_DRAW_OFFSET check outside the drawing rect check
We have to do fallback when the 'Clipped Drawing Rectangle X/Y Max'
exceed the hardware's limit no matter the drawing rectangle offset
changed or not.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=46665
NOTE: This is a candidate for stable release branches.
Signed-off-by: Yuanhan Liu
Reviewed-by: Eric Anholt
(cherry picked from commit cf2f9ef015c312ecaa6656519602ae535f7ce9d7)
---
src/mesa/drivers/dri/i915/i915_vtbl.c |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c
b/src/mesa/drivers/dri/i915/i915_vtbl.c
index 11e8a35..e78dbc8 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -665,12 +665,11 @@ i915_set_draw_region(struct intel_context *intel,
draw_offset = (draw_y << 16) | draw_x;
+ FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
+(ctx->DrawBuffer->Width + draw_x > 2048) ||
+(ctx->DrawBuffer->Height + draw_y > 2048));
/* When changing drawing rectangle offset, an MI_FLUSH is first required. */
if (draw_offset != i915->last_draw_offset) {
- FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
- (ctx->DrawBuffer->Width + draw_x > 2048) ||
- (ctx->DrawBuffer->Height + draw_y > 2048));
-
state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH |
INHIBIT_FLUSH_RENDER_CACHE;
i915->last_draw_offset = draw_offset;
} else
___
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Mesa (8.0): i915: fix wrong rendering of gl_PointSize on Pineview
Module: Mesa
Branch: 8.0
Commit: 5cfc7d1167edc97b81118652cd1cefaf94b997e5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5cfc7d1167edc97b81118652cd1cefaf94b997e5
Author: Yuanhan Liu
Date: Thu Feb 23 14:19:19 2012 +0800
i915: fix wrong rendering of gl_PointSize on Pineview
The current code would ignore the point size specified by gl_PointSize
builtin variable in vertex shader on Pineview. This patch servers as
fixing that.
This patch fixes the following issues on Pineview:
webglc:
https://cvs.khronos.org/svn/repos/registry/trunk/public/webgl/sdk/tests/conformance/rendering/point-size.html
piglit: glsl-vs-point-size
NOTE: This is a candidate for stable release branches.
v2: pick Eric's nice tip for fixing this issue in hardware rendering.
v3: the last arg of EMIT_ATTR specify the size in _byte_. (Eric)
Signed-off-by: Yuanhan Liu
Reviewed-by: Eric Anholt
(cherry picked from commit 058fc6521e3bc483bc948cc90dc5ee3b08d6ec64)
---
src/mesa/drivers/dri/i915/i915_fragprog.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c
b/src/mesa/drivers/dri/i915/i915_fragprog.c
index 4f016a3..5b7e93e 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -1361,6 +1361,10 @@ i915ValidateFragmentProgram(struct i915_context *i915)
EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_3F_VIEWPORT, S4_VFMT_XYZ, 12);
}
+ /* Handle gl_PointSize builtin var here */
+ if (ctx->Point._Attenuated || ctx->VertexProgram.PointSizeEnabled)
+ EMIT_ATTR(_TNL_ATTRIB_POINTSIZE, EMIT_1F, S4_VFMT_POINT_WIDTH, 4);
+
if (inputsRead & FRAG_BIT_COL0) {
intel->coloroffset = offset / 4;
EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, S4_VFMT_COLOR, 4);
___
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Mesa (8.0): tnl: let _TNL_ATTRIB_POINTSIZE do not depend on ctx-> VertexProgram._Enabled
Module: Mesa Branch: 8.0 Commit: fae3a31bbbefb2ac795ba0d5df613343a5a9e119 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=fae3a31bbbefb2ac795ba0d5df613343a5a9e119 Author: Yuanhan Liu Date: Thu Feb 23 14:19:18 2012 +0800 tnl: let _TNL_ATTRIB_POINTSIZE do not depend on ctx->VertexProgram._Enabled We may specify the point size in a glsl vertex shader. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=46311 piglit: glsl-vs-point-size NOTE: This is a candidate for stable release branches. Signed-off-by: Yuanhan Liu Reviewed-by: Brian Paul (cherry picked from commit 9962280c332aba4b945b73ae19862041a7053a71) --- src/mesa/tnl/t_context.c |3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/src/mesa/tnl/t_context.c b/src/mesa/tnl/t_context.c index 1ded44c..e38c0a3 100644 --- a/src/mesa/tnl/t_context.c +++ b/src/mesa/tnl/t_context.c @@ -151,8 +151,7 @@ _tnl_InvalidateState( struct gl_context *ctx, GLuint new_state ) if (ctx->RenderMode == GL_FEEDBACK) tnl->render_inputs_bitset |= BITFIELD64_BIT(_TNL_ATTRIB_TEX0); - if (ctx->Point._Attenuated || - (ctx->VertexProgram._Enabled && ctx->VertexProgram.PointSizeEnabled)) + if (ctx->Point._Attenuated || ctx->VertexProgram.PointSizeEnabled) tnl->render_inputs_bitset |= BITFIELD64_BIT(_TNL_ATTRIB_POINTSIZE); /* check for varying vars which are written by the vertex program */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: handle gl_PointCoord for Gen4 and Gen5 platforms
Module: Mesa
Branch: master
Commit: 43af02ac731dac7d80f7e47feb0c80e4da156769
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=43af02ac731dac7d80f7e47feb0c80e4da156769
Author: Yuanhan Liu
Date: Mon Feb 27 15:46:32 2012 +0800
i965: handle gl_PointCoord for Gen4 and Gen5 platforms
This patch add the support of gl_PointCoord gl builtin variable for
platform gen4 and gen5(ILK).
Unlike gen6+, we don't have a hardware support of gl_PointCoord, means
hardware will not calculate the interpolation coefficient for you.
Instead, you should handle it yourself in sf shader stage.
But badly, gl_PointCoord is a FS instead of VS builtin variable, thus
it's not included in c.vue_map generated in VS stage. Thus the current
code doesn't aware of this attribute. And to handle it correctly, we
need add it to c.vue_map manually to let SF shader generate the needed
interpolation coefficient for FS shader. SF stage has it's own copy of
vue_map, thus I think it's safe to do it manually.
Since handling gl_PointCoord for gen4 and gen5 platforms is somehow a
little special, I added a lot of comments and hope I didn't overdo it ;)
v2: add a /* _NEW_BUFFERS */ comment to note the state flag dependency
and also add the _NEW_BUFFERS dirty mask (Eric).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=45975
Piglit: glsl-fs-pointcoord and fbo-gl_pointcoord
NOTE: This is a candidate for stable release branches.
Signed-off-by: Yuanhan Liu
Reviewed-by: Eric Anholt
---
src/mesa/drivers/dri/i965/brw_context.h |6 ++
src/mesa/drivers/dri/i965/brw_fs.cpp|9 +
src/mesa/drivers/dri/i965/brw_sf.c | 30 +-
src/mesa/drivers/dri/i965/brw_sf.h |1 +
src/mesa/drivers/dri/i965/brw_sf_emit.c |4
5 files changed, 45 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index a16145b..0c50b6b 100644
--- a/src/mesa/drivers/dri/i965/brw_context.h
+++ b/src/mesa/drivers/dri/i965/brw_context.h
@@ -296,6 +296,12 @@ typedef enum
BRW_VERT_RESULT_NDC = VERT_RESULT_MAX,
BRW_VERT_RESULT_HPOS_DUPLICATE,
BRW_VERT_RESULT_PAD,
+ /*
+* It's actually not a vert_result but just a _mark_ to let sf aware that
+* he need do something special to handle gl_PointCoord builtin variable
+* correctly. see compile_sf_prog() for more info.
+*/
+ BRW_VERT_RESULT_PNTC,
BRW_VERT_RESULT_MAX
} brw_vert_result;
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index bf59da3..5f3d79d 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -710,6 +710,15 @@ fs_visitor::calculate_urb_setup()
urb_setup[fp_index] = urb_next++;
}
}
+
+ /*
+ * It's a FS only attribute, and we did interpolation for this attribute
+ * in SF thread. So, count it here, too.
+ *
+ * See compile_sf_prog() for more info.
+ */
+ if (brw->fragment_program->Base.InputsRead &
BITFIELD64_BIT(FRAG_ATTRIB_PNTC))
+ urb_setup[FRAG_ATTRIB_PNTC] = urb_next++;
}
/* Each attribute is 4 setup channels, each of which is half a reg. */
diff --git a/src/mesa/drivers/dri/i965/brw_sf.c
b/src/mesa/drivers/dri/i965/brw_sf.c
index 6e63583..37d1ee5 100644
--- a/src/mesa/drivers/dri/i965/brw_sf.c
+++ b/src/mesa/drivers/dri/i965/brw_sf.c
@@ -64,6 +64,16 @@ static void compile_sf_prog( struct brw_context *brw,
c.key = *key;
c.vue_map = brw->vs.prog_data->vue_map;
+ if (c.key.do_point_coord) {
+ /*
+ * gl_PointCoord is a FS instead of VS builtin variable, thus it's
+ * not included in c.vue_map generated in VS stage. Here we add
+ * it manually to let SF shader generate the needed interpolation
+ * coefficient for FS shader.
+ */
+ c.vue_map.vert_result_to_slot[BRW_VERT_RESULT_PNTC] =
c.vue_map.num_slots;
+ c.vue_map.slot_to_vert_result[c.vue_map.num_slots++] =
BRW_VERT_RESULT_PNTC;
+ }
c.urb_entry_read_offset = brw_sf_compute_urb_entry_read_offset(intel);
c.nr_attr_regs = (c.vue_map.num_slots + 1)/2 - c.urb_entry_read_offset;
c.nr_setup_regs = c.nr_attr_regs;
@@ -125,6 +135,8 @@ brw_upload_sf_prog(struct brw_context *brw)
{
struct gl_context *ctx = &brw->intel.ctx;
struct brw_sf_prog_key key;
+ /* _NEW_BUFFERS */
+ bool render_to_fbo = ctx->DrawBuffer->Name != 0;
memset(&key, 0, sizeof(key));
@@ -167,7 +179,15 @@ brw_upload_sf_prog(struct brw_context *brw)
key.point_sprite_coord_replace |= (1 << i);
}
}
- key.sprite_origin_lower_left = (ctx->Point.SpriteOrigin == GL_LOWER_LEFT);
+ if (brw->fragment_program->Base.InputsRead &
BITFIELD64_BIT(FRAG_ATTRIB_PNTC))
+ key.do_point_coord = 1;
+ /*
+* Window coordinates in a FBO
Mesa (master): i915: move the FALLBACK_DRAW_OFFSET check outside the drawing rect check
Module: Mesa
Branch: master
Commit: cf2f9ef015c312ecaa6656519602ae535f7ce9d7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cf2f9ef015c312ecaa6656519602ae535f7ce9d7
Author: Yuanhan Liu
Date: Tue Mar 6 14:40:32 2012 +0800
i915: move the FALLBACK_DRAW_OFFSET check outside the drawing rect check
We have to do fallback when the 'Clipped Drawing Rectangle X/Y Max'
exceed the hardware's limit no matter the drawing rectangle offset
changed or not.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=46665
NOTE: This is a candidate for stable release branches.
Signed-off-by: Yuanhan Liu
Reviewed-by: Eric Anholt
---
src/mesa/drivers/dri/i915/i915_vtbl.c |7 +++
1 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i915_vtbl.c
b/src/mesa/drivers/dri/i915/i915_vtbl.c
index 11e8a35..e78dbc8 100644
--- a/src/mesa/drivers/dri/i915/i915_vtbl.c
+++ b/src/mesa/drivers/dri/i915/i915_vtbl.c
@@ -665,12 +665,11 @@ i915_set_draw_region(struct intel_context *intel,
draw_offset = (draw_y << 16) | draw_x;
+ FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
+(ctx->DrawBuffer->Width + draw_x > 2048) ||
+(ctx->DrawBuffer->Height + draw_y > 2048));
/* When changing drawing rectangle offset, an MI_FLUSH is first required. */
if (draw_offset != i915->last_draw_offset) {
- FALLBACK(intel, I915_FALLBACK_DRAW_OFFSET,
- (ctx->DrawBuffer->Width + draw_x > 2048) ||
- (ctx->DrawBuffer->Height + draw_y > 2048));
-
state->Buffer[I915_DESTREG_DRAWRECT0] = MI_FLUSH |
INHIBIT_FLUSH_RENDER_CACHE;
i915->last_draw_offset = draw_offset;
} else
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Mesa (master): i915: fix wrong rendering of gl_PointSize on Pineview
Module: Mesa
Branch: master
Commit: 058fc6521e3bc483bc948cc90dc5ee3b08d6ec64
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=058fc6521e3bc483bc948cc90dc5ee3b08d6ec64
Author: Yuanhan Liu
Date: Thu Feb 23 14:19:19 2012 +0800
i915: fix wrong rendering of gl_PointSize on Pineview
The current code would ignore the point size specified by gl_PointSize
builtin variable in vertex shader on Pineview. This patch servers as
fixing that.
This patch fixes the following issues on Pineview:
webglc:
https://cvs.khronos.org/svn/repos/registry/trunk/public/webgl/sdk/tests/conformance/rendering/point-size.html
piglit: glsl-vs-point-size
NOTE: This is a candidate for stable release branches.
v2: pick Eric's nice tip for fixing this issue in hardware rendering.
v3: the last arg of EMIT_ATTR specify the size in _byte_. (Eric)
Signed-off-by: Yuanhan Liu
Reviewed-by: Eric Anholt
---
src/mesa/drivers/dri/i915/i915_fragprog.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/i915_fragprog.c
b/src/mesa/drivers/dri/i915/i915_fragprog.c
index 4f016a3..5b7e93e 100644
--- a/src/mesa/drivers/dri/i915/i915_fragprog.c
+++ b/src/mesa/drivers/dri/i915/i915_fragprog.c
@@ -1361,6 +1361,10 @@ i915ValidateFragmentProgram(struct i915_context *i915)
EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_3F_VIEWPORT, S4_VFMT_XYZ, 12);
}
+ /* Handle gl_PointSize builtin var here */
+ if (ctx->Point._Attenuated || ctx->VertexProgram.PointSizeEnabled)
+ EMIT_ATTR(_TNL_ATTRIB_POINTSIZE, EMIT_1F, S4_VFMT_POINT_WIDTH, 4);
+
if (inputsRead & FRAG_BIT_COL0) {
intel->coloroffset = offset / 4;
EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, S4_VFMT_COLOR, 4);
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Mesa (master): tnl: let _TNL_ATTRIB_POINTSIZE do not depend on ctx-> VertexProgram._Enabled
Module: Mesa Branch: master Commit: 9962280c332aba4b945b73ae19862041a7053a71 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=9962280c332aba4b945b73ae19862041a7053a71 Author: Yuanhan Liu Date: Thu Feb 23 14:19:18 2012 +0800 tnl: let _TNL_ATTRIB_POINTSIZE do not depend on ctx->VertexProgram._Enabled We may specify the point size in a glsl vertex shader. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=46311 piglit: glsl-vs-point-size NOTE: This is a candidate for stable release branches. Signed-off-by: Yuanhan Liu Reviewed-by: Brian Paul --- src/mesa/tnl/t_context.c |3 +-- 1 files changed, 1 insertions(+), 2 deletions(-) diff --git a/src/mesa/tnl/t_context.c b/src/mesa/tnl/t_context.c index ede1d74..dbda7a5 100644 --- a/src/mesa/tnl/t_context.c +++ b/src/mesa/tnl/t_context.c @@ -170,8 +170,7 @@ _tnl_InvalidateState( struct gl_context *ctx, GLuint new_state ) if (ctx->RenderMode == GL_FEEDBACK) tnl->render_inputs_bitset |= BITFIELD64_BIT(_TNL_ATTRIB_TEX0); - if (ctx->Point._Attenuated || - (ctx->VertexProgram._Enabled && ctx->VertexProgram.PointSizeEnabled)) + if (ctx->Point._Attenuated || ctx->VertexProgram.PointSizeEnabled) tnl->render_inputs_bitset |= BITFIELD64_BIT(_TNL_ATTRIB_POINTSIZE); /* check for varying vars which are written by the vertex program */ ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): i965: fix inverted point sprite origin when rendering to FBO
Module: Mesa
Branch: master
Commit: eaf360e5bffc5630789367020252cd12fe586177
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eaf360e5bffc5630789367020252cd12fe586177
Author: Yuanhan Liu
Date: Fri Jan 20 07:48:52 2012 +0800
i965: fix inverted point sprite origin when rendering to FBO
When rendering to FBO, rendering is inverted. At the same time, we would
also make sure the point sprite origin is inverted. Or, we will get an
inverted result correspoinding to rendering to the default winsys FBO.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=44613
NOTE: This is a candidate for stable release branches.
v2: add the simliar logic to ivb, too (comments from Ian)
simplify the logic operation (comments from Brian)
v3: pick a better comment from Eric
use != for the logic instead of ^ (comments from Ian)
Signed-off-by: Yuanhan Liu
Reviewed-by: Ian Romanick
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_defines.h |1 +
src/mesa/drivers/dri/i965/gen6_sf_state.c | 13 +++--
src/mesa/drivers/dri/i965/gen7_sf_state.c | 18 +++---
3 files changed, 27 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 4d90a99..029be87 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1128,6 +1128,7 @@ enum brw_message_target {
/* DW1 (for gen6) */
# define GEN6_SF_NUM_OUTPUTS_SHIFT 22
# define GEN6_SF_SWIZZLE_ENABLE(1 << 21)
+# define GEN6_SF_POINT_SPRITE_UPPERLEFT(0 << 20)
# define GEN6_SF_POINT_SPRITE_LOWERLEFT(1 << 20)
# define GEN6_SF_URB_ENTRY_READ_LENGTH_SHIFT 11
# define GEN6_SF_URB_ENTRY_READ_OFFSET_SHIFT 4
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 548c5a3..163b54c 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -129,6 +129,7 @@ upload_sf_state(struct brw_context *brw)
float point_size;
uint16_t attr_overrides[FRAG_ATTRIB_MAX];
bool userclip_active;
+ uint32_t point_sprite_origin;
/* _NEW_TRANSFORM */
userclip_active = (ctx->Transform.ClipPlanesEnabled != 0);
@@ -258,8 +259,16 @@ upload_sf_state(struct brw_context *brw)
/* Clamp to the hardware limits and convert to fixed point */
dw4 |= U_FIXED(CLAMP(point_size, 0.125, 255.875), 3);
- if (ctx->Point.SpriteOrigin == GL_LOWER_LEFT)
- dw1 |= GEN6_SF_POINT_SPRITE_LOWERLEFT;
+ /*
+* Window coordinates in an FBO are inverted, which means point
+* sprite origin must be inverted, too.
+*/
+ if ((ctx->Point.SpriteOrigin == GL_LOWER_LEFT) != render_to_fbo) {
+ point_sprite_origin = GEN6_SF_POINT_SPRITE_LOWERLEFT;
+ } else {
+ point_sprite_origin = GEN6_SF_POINT_SPRITE_UPPERLEFT;
+ }
+ dw1 |= point_sprite_origin;
/* _NEW_LIGHT */
if (ctx->Light.ProvokingVertex != GL_FIRST_VERTEX_CONVENTION) {
diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c
b/src/mesa/drivers/dri/i965/gen7_sf_state.c
index 7691cb2..da7ef81 100644
--- a/src/mesa/drivers/dri/i965/gen7_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c
@@ -48,6 +48,9 @@ upload_sbe_state(struct brw_context *brw)
int urb_entry_read_offset = 1;
bool userclip_active = (ctx->Transform.ClipPlanesEnabled != 0);
uint16_t attr_overrides[FRAG_ATTRIB_MAX];
+ /* _NEW_BUFFERS */
+ bool render_to_fbo = ctx->DrawBuffer->Name != 0;
+ uint32_t point_sprite_origin;
brw_compute_vue_map(&vue_map, intel, userclip_active, vs_outputs_written);
urb_entry_read_length = (vue_map.num_slots + 1)/2 - urb_entry_read_offset;
@@ -65,9 +68,18 @@ upload_sbe_state(struct brw_context *brw)
urb_entry_read_length << GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT |
urb_entry_read_offset << GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT;
- /* _NEW_POINT */
- if (ctx->Point.SpriteOrigin == GL_LOWER_LEFT)
- dw1 |= GEN6_SF_POINT_SPRITE_LOWERLEFT;
+ /* _NEW_POINT
+*
+* Window coordinates in an FBO are inverted, which means point
+* sprite origin must be inverted.
+*/
+ if ((ctx->Point.SpriteOrigin == GL_LOWER_LEFT) != render_to_fbo) {
+ point_sprite_origin = GEN6_SF_POINT_SPRITE_LOWERLEFT;
+ } else {
+ point_sprite_origin = GEN6_SF_POINT_SPRITE_UPPERLEFT;
+ }
+ dw1 |= point_sprite_origin;
+
dw10 = 0;
dw11 = 0;
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Mesa (master): vbo: introduce vbo_get_minmax_indices function
Module: Mesa
Branch: master
Commit: 42d4972bf0b147b0241c2be7e6579fd64cf2c216
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=42d4972bf0b147b0241c2be7e6579fd64cf2c216
Author: Yuanhan Liu
Date: Sat Dec 31 14:22:46 2011 +0800
vbo: introduce vbo_get_minmax_indices function
Introduce vbo_get_minmax_indices() function to handle the min/max index
computation for nr_prims(>= 1). The old code just compute the first
prim's min/max index; this would results an error rendering if user
called functions like glMultiDrawElements(). This patch servers as
fixing this issue.
As when nr_prims = 1, we can pass 1 to paramter nr_prims, thus I made
vbo_get_minmax_index() static.
v2: per Roland's suggestion, put the indices address compuation into
vbo_get_minmax_index() instead.
Also do comination if possible to reduce map/unmap count
v3: per Brian's suggestion, use a pointer for start_prim to avoid
structure copy per loop.
Signed-off-by: Yuanhan Liu
Reviewed-by: Roland Scheidegger
Reviewed-by: Brian Paul
---
src/mesa/drivers/dri/i965/brw_draw.c |2 +-
src/mesa/drivers/dri/nouveau/nouveau_vbo_t.c |3 +-
src/mesa/main/api_validate.c |2 +-
src/mesa/state_tracker/st_draw.c |3 +-
src/mesa/state_tracker/st_draw_feedback.c|2 +-
src/mesa/tnl/t_draw.c|2 +-
src/mesa/vbo/vbo.h |6 ++--
src/mesa/vbo/vbo_exec_array.c| 50 +
8 files changed, 53 insertions(+), 17 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index 621195d..f50fffd 100644
--- a/src/mesa/drivers/dri/i965/brw_draw.c
+++ b/src/mesa/drivers/dri/i965/brw_draw.c
@@ -586,7 +586,7 @@ void brw_draw_prims( struct gl_context *ctx,
if (!vbo_all_varyings_in_vbos(arrays)) {
if (!index_bounds_valid)
-vbo_get_minmax_index(ctx, prim, ib, &min_index, &max_index);
+vbo_get_minmax_indices(ctx, prim, ib, &min_index, &max_index,
nr_prims);
/* Decide if we want to rebase. If so we end up recursing once
* only into this function.
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_vbo_t.c
b/src/mesa/drivers/dri/nouveau/nouveau_vbo_t.c
index de04d18..59f1542 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_vbo_t.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_vbo_t.c
@@ -437,7 +437,8 @@ TAG(vbo_render_prims)(struct gl_context *ctx,
struct nouveau_render_state *render = to_render_state(ctx);
if (!index_bounds_valid)
- vbo_get_minmax_index(ctx, prims, ib, &min_index, &max_index);
+ vbo_get_minmax_indices(ctx, prims, ib, &min_index, &max_index,
+ nr_prims);
vbo_choose_render_mode(ctx, arrays);
vbo_choose_attrs(ctx, arrays);
diff --git a/src/mesa/main/api_validate.c b/src/mesa/main/api_validate.c
index 945f127..b6871d0 100644
--- a/src/mesa/main/api_validate.c
+++ b/src/mesa/main/api_validate.c
@@ -184,7 +184,7 @@ check_index_bounds(struct gl_context *ctx, GLsizei count,
GLenum type,
ib.ptr = indices;
ib.obj = ctx->Array.ArrayObj->ElementArrayBufferObj;
- vbo_get_minmax_index(ctx, &prim, &ib, &min, &max);
+ vbo_get_minmax_indices(ctx, &prim, &ib, &min, &max, 1);
if ((int)(min + basevertex) < 0 ||
max + basevertex > ctx->Array.ArrayObj->_MaxElement) {
diff --git a/src/mesa/state_tracker/st_draw.c b/src/mesa/state_tracker/st_draw.c
index 6d6fc85..c0554cf 100644
--- a/src/mesa/state_tracker/st_draw.c
+++ b/src/mesa/state_tracker/st_draw.c
@@ -990,7 +990,8 @@ st_draw_vbo(struct gl_context *ctx,
/* Gallium probably doesn't want this in some cases. */
if (!index_bounds_valid)
if (!all_varyings_in_vbos(arrays))
-vbo_get_minmax_index(ctx, prims, ib, &min_index, &max_index);
+vbo_get_minmax_indices(ctx, prims, ib, &min_index, &max_index,
+ nr_prims);
for (i = 0; i < nr_prims; i++) {
num_instances = MAX2(num_instances, prims[i].num_instances);
diff --git a/src/mesa/state_tracker/st_draw_feedback.c
b/src/mesa/state_tracker/st_draw_feedback.c
index fbf0349..a559b73 100644
--- a/src/mesa/state_tracker/st_draw_feedback.c
+++ b/src/mesa/state_tracker/st_draw_feedback.c
@@ -119,7 +119,7 @@ st_feedback_draw_vbo(struct gl_context *ctx,
st_validate_state(st);
if (!index_bounds_valid)
- vbo_get_minmax_index(ctx, prims, ib, &min_index, &max_index);
+ vbo_get_minmax_indices(ctx, prims, ib, &min_index, &max_index, nr_prims);
/* must get these after state validation! */
vp = st->vp;
diff --git a/src/mesa/tnl/t_draw.c b/src/mesa/tnl/t_draw.c
index f949c34..17042cf 100644
--- a/src/mesa/tnl/t_draw.c
+++ b/src/mesa/tnl/t_draw.c
@
Mesa (master): vbo: introduce vbo_sizeof_ib_type() function
Module: Mesa
Branch: master
Commit: efa1fac2158c9146b87f0d4340a864661721de21
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=efa1fac2158c9146b87f0d4340a864661721de21
Author: Yuanhan Liu
Date: Wed Dec 28 13:54:42 2011 +0800
vbo: introduce vbo_sizeof_ib_type() function
introduce vbo_sizeof_ib_type() function to return the index data type
size. I see some place use switch(ib->type) to get the index data type,
which is sort of duplicate.
Signed-off-by: Yuanhan Liu
Reviewed-by: Brian Paul
Reviewed-by: Eric Anholt
---
src/mesa/state_tracker/st_draw.c | 15 +
src/mesa/state_tracker/st_draw_feedback.c | 17 ++
src/mesa/tnl/t_draw.c | 20 +--
src/mesa/vbo/vbo.h|4 ++
src/mesa/vbo/vbo_exec_array.c | 52 ++--
5 files changed, 29 insertions(+), 79 deletions(-)
diff --git a/src/mesa/state_tracker/st_draw.c b/src/mesa/state_tracker/st_draw.c
index 87a9978..954f15a 100644
--- a/src/mesa/state_tracker/st_draw.c
+++ b/src/mesa/state_tracker/st_draw.c
@@ -584,20 +584,7 @@ setup_index_buffer(struct gl_context *ctx,
if (ib) {
struct gl_buffer_object *bufobj = ib->obj;
- switch (ib->type) {
- case GL_UNSIGNED_INT:
- ibuffer->index_size = 4;
- break;
- case GL_UNSIGNED_SHORT:
- ibuffer->index_size = 2;
- break;
- case GL_UNSIGNED_BYTE:
- ibuffer->index_size = 1;
- break;
- default:
- assert(0);
-return;
- }
+ ibuffer->index_size = vbo_sizeof_ib_type(ib->type);
/* get/create the index buffer object */
if (_mesa_is_bufferobj(bufobj)) {
diff --git a/src/mesa/state_tracker/st_draw_feedback.c
b/src/mesa/state_tracker/st_draw_feedback.c
index 4c1e674..a99eb2b 100644
--- a/src/mesa/state_tracker/st_draw_feedback.c
+++ b/src/mesa/state_tracker/st_draw_feedback.c
@@ -218,20 +218,9 @@ st_feedback_draw_vbo(struct gl_context *ctx,
if (ib) {
struct gl_buffer_object *bufobj = ib->obj;
- switch (ib->type) {
- case GL_UNSIGNED_INT:
- ibuffer.index_size = 4;
- break;
- case GL_UNSIGNED_SHORT:
- ibuffer.index_size = 2;
- break;
- case GL_UNSIGNED_BYTE:
- ibuffer.index_size = 1;
- break;
- default:
- assert(0);
-goto out_unref_vertex;
- }
+ ibuffer.index_size = vbo_sizeof_ib_type(ib->type);
+ if (ibuffer.index_size == 0)
+ goto out_unref_vertex;
if (bufobj && bufobj->Name) {
struct st_buffer_object *stobj = st_buffer_object(bufobj);
diff --git a/src/mesa/tnl/t_draw.c b/src/mesa/tnl/t_draw.c
index 83ded19..f949c34 100644
--- a/src/mesa/tnl/t_draw.c
+++ b/src/mesa/tnl/t_draw.c
@@ -349,26 +349,10 @@ static void bind_indices( struct gl_context *ctx,
if (_mesa_is_bufferobj(ib->obj) && !_mesa_bufferobj_mapped(ib->obj)) {
/* if the buffer object isn't mapped yet, map it now */
- unsigned map_size;
-
- switch (ib->type) {
- case GL_UNSIGNED_BYTE:
-map_size = ib->count * sizeof(GLubyte);
-break;
- case GL_UNSIGNED_SHORT:
-map_size = ib->count * sizeof(GLushort);
-break;
- case GL_UNSIGNED_INT:
-map_size = ib->count * sizeof(GLuint);
-break;
- default:
-assert(0);
-map_size = 0;
- }
-
bo[*nr_bo] = ib->obj;
(*nr_bo)++;
- ptr = ctx->Driver.MapBufferRange(ctx, (GLsizeiptr) ib->ptr, map_size,
+ ptr = ctx->Driver.MapBufferRange(ctx, (GLsizeiptr) ib->ptr,
+ ib->count *
vbo_sizeof_ib_type(ib->type),
GL_MAP_READ_BIT, ib->obj);
assert(ib->obj->Pointer);
} else {
diff --git a/src/mesa/vbo/vbo.h b/src/mesa/vbo/vbo.h
index 7384790..ed8fc17 100644
--- a/src/mesa/vbo/vbo.h
+++ b/src/mesa/vbo/vbo.h
@@ -122,6 +122,10 @@ void vbo_rebase_prims( struct gl_context *ctx,
GLuint min_index,
GLuint max_index,
vbo_draw_func draw );
+
+int
+vbo_sizeof_ib_type(GLenum type);
+
void
vbo_get_minmax_index(struct gl_context *ctx, const struct _mesa_prim *prim,
const struct _mesa_index_buffer *ib,
diff --git a/src/mesa/vbo/vbo_exec_array.c b/src/mesa/vbo/vbo_exec_array.c
index 2db85e2..fec49d3 100644
--- a/src/mesa/vbo/vbo_exec_array.c
+++ b/src/mesa/vbo/vbo_exec_array.c
@@ -75,6 +75,22 @@ vbo_check_buffers_are_unmapped(struct gl_context *ctx)
assert(!_mesa_bufferobj_mapped(exec->vtx.bufferobj));
}
+int
+vbo_sizeof_ib_type(GLenum type)
+{
+ switch (type) {
+ case GL_UNSIGNED_INT:
+ return sizeof(GLuint);
+ case GL_UNSIGNED_SHORT:
+ return sizeof(GLushort);
+ case GL_UNSIGNED_BYTE:
+ return sizeof(GLubyte);
+ defau
Mesa (master): i965: increase the brw eu instruction store size dynamically
Module: Mesa
Branch: master
Commit: 3aa3c3f75894ca0eb08087c0ec3dd114eeae4bb7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3aa3c3f75894ca0eb08087c0ec3dd114eeae4bb7
Author: Yuanhan Liu
Date: Wed Dec 21 15:38:44 2011 +0800
i965: increase the brw eu instruction store size dynamically
Here is the final patch to enable dynamic eu instruction store size:
increase the brw eu instruction store size dynamically instead of just
allocating it statically with a constant limit. This would fix something
that 'GL_MAX_PROGRAM_INSTRUCTIONS_ARB was 16384 while the driver would
limit it to 1'.
v2: comments from ken, do not hardcode the eu limit to (1024 * 1024)
Signed-off-by: Yuanhan Liu
Reviewed-by: Kenneth Graunke
Reviewed-by: Eric Anholt
---
src/mesa/drivers/dri/i965/brw_eu.c |7 +++
src/mesa/drivers/dri/i965/brw_eu.h |4 ++--
src/mesa/drivers/dri/i965/brw_eu_emit.c | 10 +-
3 files changed, 18 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu.c
b/src/mesa/drivers/dri/i965/brw_eu.c
index 9b4dde8..2b0593a 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -174,6 +174,13 @@ void
brw_init_compile(struct brw_context *brw, struct brw_compile *p, void *mem_ctx)
{
p->brw = brw;
+ /*
+* Set the initial instruction store array size to 1024, if found that
+* isn't enough, then it will double the store size at brw_next_insn()
+* until out of memory.
+*/
+ p->store_size = 1024;
+ p->store = rzalloc_array(mem_ctx, struct brw_instruction, p->store_size);
p->nr_insn = 0;
p->current = p->stack;
p->compressed = false;
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
b/src/mesa/drivers/dri/i965/brw_eu.h
index 75642a5..d967d93 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -101,10 +101,10 @@ struct brw_glsl_call;
#define BRW_EU_MAX_INSN_STACK 5
-#define BRW_EU_MAX_INSN 1
struct brw_compile {
- struct brw_instruction store[BRW_EU_MAX_INSN];
+ struct brw_instruction *store;
+ int store_size;
GLuint nr_insn;
void *mem_ctx;
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index ac91820..c22b408 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -691,7 +691,15 @@ brw_next_insn(struct brw_compile *p, GLuint opcode)
{
struct brw_instruction *insn;
- assert(p->nr_insn + 1 < BRW_EU_MAX_INSN);
+ if (p->nr_insn + 1 > p->store_size) {
+ if (0)
+ printf("incresing the store size to %d\n", p->store_size << 1);
+ p->store_size <<= 1;
+ p->store = reralloc(p->mem_ctx, p->store,
+ struct brw_instruction, p->store_size);
+ if (!p->store)
+ assert(!"realloc eu store memeory failed");
+ }
insn = &p->store[p->nr_insn++];
memcpy(insn, p->current, sizeof(*insn));
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Mesa (master): i965: call next_insn() before referencing a instruction by index
Module: Mesa
Branch: master
Commit: 8d1b378939768c4054b35b5da592af102345ebed
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8d1b378939768c4054b35b5da592af102345ebed
Author: Yuanhan Liu
Date: Wed Dec 21 15:32:02 2011 +0800
i965: call next_insn() before referencing a instruction by index
A single next_insn may change the base address of instruction store
memory(p->store), so call it first before referencing the instruction
store pointer from an index.
This the final prepare work to enable the dynamic store size.
v2: comments from Ken, define emit_endif as bool type
Signed-off-by: Yuanhan Liu
Reviewed-by: Kenneth Graunke
Reviewed-by: Eric Anholt
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 40 ---
1 files changed, 26 insertions(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index e2bb63c..ac91820 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -1197,15 +1197,7 @@ brw_ENDIF(struct brw_compile *p)
struct brw_instruction *else_inst = NULL;
struct brw_instruction *if_inst = NULL;
struct brw_instruction *tmp;
-
- /* Pop the IF and (optional) ELSE instructions from the stack */
- p->if_depth_in_loop[p->loop_stack_depth]--;
- tmp = pop_if_stack(p);
- if (tmp->header.opcode == BRW_OPCODE_ELSE) {
- else_inst = tmp;
- tmp = pop_if_stack(p);
- }
- if_inst = tmp;
+ bool emit_endif = true;
/* In single program flow mode, we can express IF and ELSE instructions
* equivalently as ADD instructions that operate on IP. On platforms prior
@@ -1219,14 +1211,32 @@ brw_ENDIF(struct brw_compile *p)
* instructions to conditional ADDs. So we only do this trick on Gen4 and
* Gen5.
*/
- if (intel->gen < 6 && p->single_program_flow) {
+ if (intel->gen < 6 && p->single_program_flow)
+ emit_endif = false;
+
+ /*
+* A single next_insn() may change the base adress of instruction store
+* memory(p->store), so call it first before referencing the instruction
+* store pointer from an index
+*/
+ if (emit_endif)
+ insn = next_insn(p, BRW_OPCODE_ENDIF);
+
+ /* Pop the IF and (optional) ELSE instructions from the stack */
+ p->if_depth_in_loop[p->loop_stack_depth]--;
+ tmp = pop_if_stack(p);
+ if (tmp->header.opcode == BRW_OPCODE_ELSE) {
+ else_inst = tmp;
+ tmp = pop_if_stack(p);
+ }
+ if_inst = tmp;
+
+ if (!emit_endif) {
/* ENDIF is useless; don't bother emitting it. */
convert_IF_ELSE_to_ADD(p, if_inst, else_inst);
return;
}
- insn = next_insn(p, BRW_OPCODE_ENDIF);
-
if (intel->gen < 6) {
brw_set_dest(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
brw_set_src0(p, insn, retype(brw_vec4_grf(0,0), BRW_REGISTER_TYPE_UD));
@@ -1392,13 +1402,12 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p)
struct brw_instruction *insn, *do_insn;
GLuint br = 1;
- do_insn = get_inner_do_insn(p);
-
if (intel->gen >= 5)
br = 2;
if (intel->gen >= 7) {
insn = next_insn(p, BRW_OPCODE_WHILE);
+ do_insn = get_inner_do_insn(p);
brw_set_dest(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
brw_set_src0(p, insn, retype(brw_null_reg(), BRW_REGISTER_TYPE_D));
@@ -1408,6 +1417,7 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p)
insn->header.execution_size = BRW_EXECUTE_8;
} else if (intel->gen == 6) {
insn = next_insn(p, BRW_OPCODE_WHILE);
+ do_insn = get_inner_do_insn(p);
brw_set_dest(p, insn, brw_imm_w(0));
insn->bits1.branch_gen6.jump_count = br * (do_insn - insn);
@@ -1418,6 +1428,7 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p)
} else {
if (p->single_program_flow) {
insn = next_insn(p, BRW_OPCODE_ADD);
+ do_insn = get_inner_do_insn(p);
brw_set_dest(p, insn, brw_ip_reg());
brw_set_src0(p, insn, brw_ip_reg());
@@ -1425,6 +1436,7 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p)
insn->header.execution_size = BRW_EXECUTE_1;
} else {
insn = next_insn(p, BRW_OPCODE_WHILE);
+ do_insn = get_inner_do_insn(p);
assert(do_insn->header.opcode == BRW_OPCODE_DO);
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Mesa (master): i965: let the if_stack just store the instruction index
Module: Mesa
Branch: master
Commit: 0a17093eaf84696b05d04a45d6d51281f7b2786b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0a17093eaf84696b05d04a45d6d51281f7b2786b
Author: Yuanhan Liu
Date: Wed Dec 21 14:51:59 2011 +0800
i965: let the if_stack just store the instruction index
If dynamic instruction store size is enabled, while after
the brw_IF/ELSE() and before the brw_ENDIF() function, the
eu instruction store base address(p->store) may change.
Thus let if_stack just store the instruction index. This is
somehow more flexible and safe than store the instruction
memory address.
Signed-off-by: Yuanhan Liu
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/i965/brw_eu.c |3 +--
src/mesa/drivers/dri/i965/brw_eu.h |4 +++-
src/mesa/drivers/dri/i965/brw_eu_emit.c | 22 +++---
3 files changed, 19 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu.c
b/src/mesa/drivers/dri/i965/brw_eu.c
index 83aae3b..9b4dde8 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -191,8 +191,7 @@ brw_init_compile(struct brw_context *brw, struct
brw_compile *p, void *mem_ctx)
/* Set up control flow stack */
p->if_stack_depth = 0;
p->if_stack_array_size = 16;
- p->if_stack =
- rzalloc_array(mem_ctx, struct brw_instruction *, p->if_stack_array_size);
+ p->if_stack = rzalloc_array(mem_ctx, int, p->if_stack_array_size);
p->loop_stack_depth = 0;
p->loop_stack_array_size = 16;
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
b/src/mesa/drivers/dri/i965/brw_eu.h
index 11e7161..c5a119f 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -123,8 +123,10 @@ struct brw_compile {
/* Control flow stacks:
* - if_stack contains IF and ELSE instructions which must be patched
* (and popped) once the matching ENDIF instruction is encountered.
+*
+* Just store the instruction pointer(an index).
*/
- struct brw_instruction **if_stack;
+ int *if_stack;
int if_stack_depth;
int if_stack_array_size;
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index 11f4080..a74ffce 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -901,16 +901,23 @@ struct brw_instruction *brw_JMPI(struct brw_compile *p,
static void
push_if_stack(struct brw_compile *p, struct brw_instruction *inst)
{
- p->if_stack[p->if_stack_depth] = inst;
+ p->if_stack[p->if_stack_depth] = inst - p->store;
p->if_stack_depth++;
if (p->if_stack_array_size <= p->if_stack_depth) {
p->if_stack_array_size *= 2;
- p->if_stack = reralloc(p->mem_ctx, p->if_stack, struct brw_instruction *,
+ p->if_stack = reralloc(p->mem_ctx, p->if_stack, int,
p->if_stack_array_size);
}
}
+static struct brw_instruction *
+pop_if_stack(struct brw_compile *p)
+{
+ p->if_stack_depth--;
+ return &p->store[p->if_stack[p->if_stack_depth]];
+}
+
static void
push_loop_stack(struct brw_compile *p, struct brw_instruction *inst)
{
@@ -1189,15 +1196,16 @@ brw_ENDIF(struct brw_compile *p)
struct brw_instruction *insn;
struct brw_instruction *else_inst = NULL;
struct brw_instruction *if_inst = NULL;
+ struct brw_instruction *tmp;
/* Pop the IF and (optional) ELSE instructions from the stack */
p->if_depth_in_loop[p->loop_stack_depth]--;
- p->if_stack_depth--;
- if (p->if_stack[p->if_stack_depth]->header.opcode == BRW_OPCODE_ELSE) {
- else_inst = p->if_stack[p->if_stack_depth];
- p->if_stack_depth--;
+ tmp = pop_if_stack(p);
+ if (tmp->header.opcode == BRW_OPCODE_ELSE) {
+ else_inst = tmp;
+ tmp = pop_if_stack(p);
}
- if_inst = p->if_stack[p->if_stack_depth];
+ if_inst = tmp;
/* In single program flow mode, we can express IF and ELSE instructions
* equivalently as ADD instructions that operate on IP. On platforms prior
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Mesa (master): i965: get the jmp distance by instruction index
Module: Mesa
Branch: master
Commit: 328e6a5497e54b0e8aed803cf6d2ae9a2a00b2fe
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=328e6a5497e54b0e8aed803cf6d2ae9a2a00b2fe
Author: Yuanhan Liu
Date: Wed Dec 21 15:10:40 2011 +0800
i965: get the jmp distance by instruction index
If dynamic instruction store size is enabled, while after the brw_JMPI()
and before the brw_land_fwd_jump() function, the eu instruction store
base address(p->store) may change. Thus, the safe way to reference the
jmp instruction is by index instead of by the instruction address.
v2: comments from Eric, don't change the prototype of brw_JMPI
Signed-off-by: Yuanhan Liu
Reviewed-by: Kenneth Graunke
Reviewed-by: Eric Anholt
---
src/mesa/drivers/dri/i965/brw_eu.h |3 +--
src/mesa/drivers/dri/i965/brw_eu_emit.c |7 +++
src/mesa/drivers/dri/i965/brw_sf_emit.c |8
src/mesa/drivers/dri/i965/brw_wm_emit.c |4 ++--
4 files changed, 10 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
b/src/mesa/drivers/dri/i965/brw_eu.h
index c5a119f..75642a5 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -1039,8 +1039,7 @@ struct brw_instruction *brw_CONT(struct brw_compile *p);
struct brw_instruction *gen6_CONT(struct brw_compile *p);
/* Forward jumps:
*/
-void brw_land_fwd_jump(struct brw_compile *p,
- struct brw_instruction *jmp_insn);
+void brw_land_fwd_jump(struct brw_compile *p, int jmp_insn_idx);
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index a74ffce..e2bb63c 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -1451,11 +1451,10 @@ struct brw_instruction *brw_WHILE(struct brw_compile *p)
/* FORWARD JUMPS:
*/
-void brw_land_fwd_jump(struct brw_compile *p,
- struct brw_instruction *jmp_insn)
+void brw_land_fwd_jump(struct brw_compile *p, int jmp_insn_idx)
{
struct intel_context *intel = &p->brw->intel;
- struct brw_instruction *landing = &p->store[p->nr_insn];
+ struct brw_instruction *jmp_insn = &p->store[jmp_insn_idx];
GLuint jmpi = 1;
if (intel->gen >= 5)
@@ -1464,7 +1463,7 @@ void brw_land_fwd_jump(struct brw_compile *p,
assert(jmp_insn->header.opcode == BRW_OPCODE_JMPI);
assert(jmp_insn->bits1.da1.src1_reg_file == BRW_IMMEDIATE_VALUE);
- jmp_insn->bits3.ud = jmpi * ((landing - jmp_insn) - 1);
+ jmp_insn->bits3.ud = jmpi * (p->nr_insn - jmp_insn_idx - 1);
}
diff --git a/src/mesa/drivers/dri/i965/brw_sf_emit.c
b/src/mesa/drivers/dri/i965/brw_sf_emit.c
index fe3341c..1ee0098 100644
--- a/src/mesa/drivers/dri/i965/brw_sf_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_sf_emit.c
@@ -717,7 +717,7 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c )
struct brw_reg payload_prim = brw_uw1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0);
struct brw_reg payload_attr =
get_element_ud(brw_vec1_reg(BRW_GENERAL_REGISTER_FILE, 1, 0), 0);
struct brw_reg primmask;
- struct brw_instruction *jmp;
+ int jmp;
struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_UD));
GLuint saveflag;
@@ -738,7 +738,7 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c )
(1<<_3DPRIM_POLYGON) |
(1<<_3DPRIM_RECTLIST) |
(1<<_3DPRIM_TRIFAN_NOSTIPPLE)));
- jmp = brw_JMPI(p, ip, ip, brw_imm_d(0));
+ jmp = brw_JMPI(p, ip, ip, brw_imm_d(0)) - p->store;
{
saveflag = p->flag_value;
brw_push_insn_state(p);
@@ -759,7 +759,7 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c )
(1<<_3DPRIM_LINESTRIP_CONT) |
(1<<_3DPRIM_LINESTRIP_BF) |
(1<<_3DPRIM_LINESTRIP_CONT_BF)));
- jmp = brw_JMPI(p, ip, ip, brw_imm_d(0));
+ jmp = brw_JMPI(p, ip, ip, brw_imm_d(0)) - p->store;
{
saveflag = p->flag_value;
brw_push_insn_state(p);
@@ -772,7 +772,7 @@ void brw_emit_anyprim_setup( struct brw_sf_compile *c )
brw_set_conditionalmod(p, BRW_CONDITIONAL_Z);
brw_AND(p, v1_null_ud, payload_attr,
brw_imm_ud(1<store;
{
saveflag = p->flag_value;
brw_push_insn_state(p);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c
b/src/mesa/drivers/dri/i965/brw_wm_emit.c
index 4f20546..80ed1ff 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c
@@ -1528,7 +1528,7 @@ void emit_fb_write(struct brw_wm_compile *c,
else {
struct brw_reg v1_null_ud = vec1(retype(brw_null_reg(),
BRW_REGISTER_TYPE_UD));
struct brw_reg ip = brw_ip_reg();
- s
Mesa (master): Add mismatch check for glGetTexImage or it will return -1 and may lead to segment fault .
Module: Mesa
Branch: master
Commit: 606d3a3c3de94665e47df47b48596293d588a420
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=606d3a3c3de94665e47df47b48596293d588a420
Author: Jian Zhao
Date: Tue Dec 13 13:31:41 2011 +0800
Add mismatch check for glGetTexImage or it will return -1 and may lead to
segment fault.
Reviewed-by: Brian Paul
---
src/mesa/main/texgetimage.c |8
1 files changed, 8 insertions(+), 0 deletions(-)
diff --git a/src/mesa/main/texgetimage.c b/src/mesa/main/texgetimage.c
index ae0d51f..3f24187 100644
--- a/src/mesa/main/texgetimage.c
+++ b/src/mesa/main/texgetimage.c
@@ -708,6 +708,14 @@ getteximage_error_check(struct gl_context *ctx, GLenum
target, GLint level,
return GL_TRUE;
}
+ if (!_mesa_is_legal_format_and_type(ctx, format, type)) {
+ /*GL_INVALID_OPERATION is generated by a format/type
+ * mismatch (see the 1.2 spec page 94, sec 3.6.4.)
+ */
+ _mesa_error(ctx, GL_INVALID_OPERATION, "glGetTexImage(target)");
+ return GL_TRUE;
+ }
+
baseFormat = _mesa_get_format_base_format(texImage->TexFormat);
/* Make sure the requested image format is compatible with the
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Mesa (master): mesa: move ElementArrayBufferObj to gl_array_object
Module: Mesa
Branch: master
Commit: a0a5bd4bb30a73c10b02c3c3b914940a03f9b790
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0a5bd4bb30a73c10b02c3c3b914940a03f9b790
Author: Yuanhan Liu
Date: Wed Nov 23 15:59:06 2011 +0800
mesa: move ElementArrayBufferObj to gl_array_object
According opengl spec 4.2.pdf table 6.12 (Vertex Array Object State) at
page 515, the element buffer object is listed in vertex array object.
So, move the ElementArrayBufferObj inside gl_array_object to make
element buffer object per-vao.
This would fix most of(3 left) intel oglc vao test fail
NOTE: this is a candidate for the 7.11 branch.
Signed-off-by: Yuanhan Liu
Reviewed-by: Brian Paul
---
src/mesa/main/api_arrayelt.c |2 +-
src/mesa/main/api_validate.c | 14 ++--
src/mesa/main/arrayobj.c |4 +++
src/mesa/main/attrib.c|7 ++---
src/mesa/main/bufferobj.c |9 ++-
src/mesa/main/context.c |1 -
src/mesa/main/get.c |2 +-
src/mesa/main/mtypes.h|3 +-
src/mesa/vbo/vbo_exec_array.c | 42
src/mesa/vbo/vbo_save_api.c |4 +-
10 files changed, 44 insertions(+), 44 deletions(-)
diff --git a/src/mesa/main/api_arrayelt.c b/src/mesa/main/api_arrayelt.c
index b93a057..4d9ff43 100644
--- a/src/mesa/main/api_arrayelt.c
+++ b/src/mesa/main/api_arrayelt.c
@@ -1580,7 +1580,7 @@ static void _ae_update_state( struct gl_context *ctx )
aa++;
}
- check_vbo(actx, ctx->Array.ElementArrayBufferObj);
+ check_vbo(actx, arrayObj->ElementArrayBufferObj);
ASSERT(at - actx->attribs <= VERT_ATTRIB_MAX);
ASSERT(aa - actx->arrays < 32);
diff --git a/src/mesa/main/api_validate.c b/src/mesa/main/api_validate.c
index 1fcf5cd..4c7baca 100644
--- a/src/mesa/main/api_validate.c
+++ b/src/mesa/main/api_validate.c
@@ -182,7 +182,7 @@ check_index_bounds(struct gl_context *ctx, GLsizei count,
GLenum type,
memset(&ib, 0, sizeof(ib));
ib.type = type;
ib.ptr = indices;
- ib.obj = ctx->Array.ElementArrayBufferObj;
+ ib.obj = ctx->Array.ArrayObj->ElementArrayBufferObj;
vbo_get_minmax_index(ctx, &prim, &ib, &min, &max);
@@ -254,10 +254,10 @@ _mesa_validate_DrawElements(struct gl_context *ctx,
return GL_FALSE;
/* Vertex buffer object tests */
- if (_mesa_is_bufferobj(ctx->Array.ElementArrayBufferObj)) {
+ if (_mesa_is_bufferobj(ctx->Array.ArrayObj->ElementArrayBufferObj)) {
/* use indices in the buffer object */
/* make sure count doesn't go outside buffer bounds */
- if (index_bytes(type, count) > ctx->Array.ElementArrayBufferObj->Size) {
+ if (index_bytes(type, count) >
ctx->Array.ArrayObj->ElementArrayBufferObj->Size) {
_mesa_warning(ctx, "glDrawElements index out of buffer bounds");
return GL_FALSE;
}
@@ -315,10 +315,10 @@ _mesa_validate_DrawRangeElements(struct gl_context *ctx,
GLenum mode,
return GL_FALSE;
/* Vertex buffer object tests */
- if (_mesa_is_bufferobj(ctx->Array.ElementArrayBufferObj)) {
+ if (_mesa_is_bufferobj(ctx->Array.ArrayObj->ElementArrayBufferObj)) {
/* use indices in the buffer object */
/* make sure count doesn't go outside buffer bounds */
- if (index_bytes(type, count) > ctx->Array.ElementArrayBufferObj->Size) {
+ if (index_bytes(type, count) >
ctx->Array.ArrayObj->ElementArrayBufferObj->Size) {
_mesa_warning(ctx, "glDrawRangeElements index out of buffer bounds");
return GL_FALSE;
}
@@ -454,10 +454,10 @@ _mesa_validate_DrawElementsInstanced(struct gl_context
*ctx,
return GL_FALSE;
/* Vertex buffer object tests */
- if (_mesa_is_bufferobj(ctx->Array.ElementArrayBufferObj)) {
+ if (_mesa_is_bufferobj(ctx->Array.ArrayObj->ElementArrayBufferObj)) {
/* use indices in the buffer object */
/* make sure count doesn't go outside buffer bounds */
- if (index_bytes(type, count) > ctx->Array.ElementArrayBufferObj->Size) {
+ if (index_bytes(type, count) >
ctx->Array.ArrayObj->ElementArrayBufferObj->Size) {
_mesa_warning(ctx,
"glDrawElementsInstanced index out of buffer bounds");
return GL_FALSE;
diff --git a/src/mesa/main/arrayobj.c b/src/mesa/main/arrayobj.c
index 1283940..a0c9b11 100644
--- a/src/mesa/main/arrayobj.c
+++ b/src/mesa/main/arrayobj.c
@@ -133,6 +133,7 @@ _mesa_delete_array_object( struct gl_context *ctx, struct
gl_array_object *obj )
{
(void) ctx;
unbind_array_object_vbos(ctx, obj);
+ _mesa_reference_buffer_object(ctx, &obj->ElementArrayBufferObj, NULL);
_glthread_DESTROY_MUTEX(obj->Mutex);
free(obj);
}
@@ -252,6 +253,9 @@ _mesa_initialize_array_object( struct gl_context *ctx,
#if FEATURE_point_size_arr
Mesa (master): swrast: fix unmatched span->array->ChanType
Module: Mesa
Branch: master
Commit: 2e6402feb754dd6384ee27fe623a7f9fce66dcaf
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2e6402feb754dd6384ee27fe623a7f9fce66dcaf
Author: Yuanhan Liu
Date: Mon Nov 21 16:31:58 2011 +0800
swrast: fix unmatched span->array->ChanType
texture_combine converts the result rgba to CHAN_TYPE from FLOAT. At the
same time, make sure the span->array->ChanType is changed, too.
v2: pick a nicer comment from Brian
Signed-off-by: Yuanhan Liu
Reviewed-by: Brian Paul
Reviewed-by: Ian Romanick
---
src/mesa/swrast/s_texcombine.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/src/mesa/swrast/s_texcombine.c b/src/mesa/swrast/s_texcombine.c
index 0686acd..1fce5c5 100644
--- a/src/mesa/swrast/s_texcombine.c
+++ b/src/mesa/swrast/s_texcombine.c
@@ -545,6 +545,10 @@ texture_combine( struct gl_context *ctx, GLuint unit,
UNCLAMPED_FLOAT_TO_CHAN(rgbaChan[i][BCOMP], rgba[i][BCOMP]);
UNCLAMPED_FLOAT_TO_CHAN(rgbaChan[i][ACOMP], rgba[i][ACOMP]);
}
+ /* The span->array->rgba values are of CHAN type so set
+* span->array->ChanType field accordingly.
+*/
+ span->array->ChanType = CHAN_TYPE;
end:
for (i = 0; i < numArgsRGB || i < numArgsA; i++) {
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Mesa (master): swrast: simplify the prototype of function texture_combine
Module: Mesa
Branch: master
Commit: 6ba8f0688a35ffac93bd025739aefe8e3694ca0c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ba8f0688a35ffac93bd025739aefe8e3694ca0c
Author: Yuanhan Liu
Date: Fri Nov 18 09:49:51 2011 +0800
swrast: simplify the prototype of function texture_combine
Parameter n and rgbaChan are both from structure span, thus using span
as paramter to simplify the prototype. Function texture_combine is only
used by _swrast_texture_span, so I guess it's safe to do so.
This patch is mainly for the next patch.
Signed-off-by: Yuanhan Liu
Reviewed-by: Brian Paul
Reviewed-by: Ian Romanick
---
src/mesa/swrast/s_texcombine.c | 19 +--
1 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/src/mesa/swrast/s_texcombine.c b/src/mesa/swrast/s_texcombine.c
index a7cbb44..0686acd 100644
--- a/src/mesa/swrast/s_texcombine.c
+++ b/src/mesa/swrast/s_texcombine.c
@@ -69,17 +69,18 @@ get_texel_array(SWcontext *swrast, GLuint unit)
*
* \param ctx rendering context
* \param unit the texture combiner unit
- * \param nnumber of fragments to process (span width)
* \param primary_rgba incoming fragment color array
* \param texelBuffer pointer to texel colors for all texture units
*
- * \param rgba incoming/result fragment colors
+ * \param span two fields are used in this function:
+ * span->end: number of fragments to process
+ * span->array->rgba: incoming/result fragment colors
*/
static void
-texture_combine( struct gl_context *ctx, GLuint unit, GLuint n,
+texture_combine( struct gl_context *ctx, GLuint unit,
const float4_array primary_rgba,
const GLfloat *texelBuffer,
- GLchan (*rgbaChan)[4] )
+ SWspan *span )
{
SWcontext *swrast = SWRAST_CONTEXT(ctx);
const struct gl_texture_unit *textureUnit = &(ctx->Texture.Unit[unit]);
@@ -92,6 +93,8 @@ texture_combine( struct gl_context *ctx, GLuint unit, GLuint
n,
const GLuint numArgsA = combine->_NumArgsA;
float4_array ccolor[4], rgba;
GLuint i, term;
+ GLuint n = span->end;
+ GLchan (*rgbaChan)[4] = span->array->rgba;
/* alloc temp pixel buffers */
rgba = (float4_array) malloc(4 * n * sizeof(GLfloat));
@@ -764,12 +767,8 @@ _swrast_texture_span( struct gl_context *ctx, SWspan *span
)
* We modify the span->color.rgba values.
*/
for (unit = 0; unit < ctx->Const.MaxTextureUnits; unit++) {
- if (ctx->Texture.Unit[unit]._ReallyEnabled) {
- texture_combine( ctx, unit, span->end,
- primary_rgba,
- swrast->TexelBuffer,
- span->array->rgba );
- }
+ if (ctx->Texture.Unit[unit]._ReallyEnabled)
+ texture_combine(ctx, unit, primary_rgba, swrast->TexelBuffer, span);
}
free(primary_rgba);
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Mesa (master): mesa: do not skip att and spot calculation for infinite light
Module: Mesa
Branch: master
Commit: 4f677ca5f9f998a6f57a1390156e772f1f87280a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4f677ca5f9f998a6f57a1390156e772f1f87280a
Author: Yuanhan Liu
Date: Wed Nov 16 11:29:08 2011 +0800
mesa: do not skip att and spot calculation for infinite light
glspec doesn't say that we should skip the attenuation and spot
calculation for infinite light(Ppli.w == 0). Instead, it gives a same
formula to do the light calculation for both finite light and infinite
light(see page 62 of glspec 2.1.pdf)
Also from the formula (2.4) at page 62 of glspec 2.1.pdf, we can skip
attenuation calculation if Ppli.w == 0.
This would fix all the intel oglc l_sed fail subcases and introduces no
intel oglc regressions.
v2: fix an wrong intendation(comments from Brian).
Signed-off-by: Yuanhan Liu
Acked-by: Brian Paul
---
src/mesa/main/ffvertex_prog.c | 115 ++---
1 files changed, 51 insertions(+), 64 deletions(-)
diff --git a/src/mesa/main/ffvertex_prog.c b/src/mesa/main/ffvertex_prog.c
index 8469078..2c93738 100644
--- a/src/mesa/main/ffvertex_prog.c
+++ b/src/mesa/main/ffvertex_prog.c
@@ -949,7 +949,7 @@ static struct ureg calculate_light_attenuation( struct
tnl_program *p,
{
struct ureg attenuation = register_param3(p, STATE_LIGHT, i,
STATE_ATTENUATION);
- struct ureg att = get_temp(p);
+ struct ureg att = undef;
/* Calculate spot attenuation:
*/
@@ -959,6 +959,8 @@ static struct ureg calculate_light_attenuation( struct
tnl_program *p,
struct ureg spot = get_temp(p);
struct ureg slt = get_temp(p);
+ att = get_temp(p);
+
emit_op2(p, OPCODE_DP3, spot, 0, negate(VPpli), spot_dir_norm);
emit_op2(p, OPCODE_SLT, slt, 0, swizzle1(spot_dir_norm,W), spot);
emit_op2(p, OPCODE_POW, spot, 0, spot, swizzle1(attenuation, W));
@@ -968,9 +970,13 @@ static struct ureg calculate_light_attenuation( struct
tnl_program *p,
release_temp(p, slt);
}
- /* Calculate distance attenuation:
+ /* Calculate distance attenuation(See formula (2.4) at glspec 2.1 page 62):
+*
+* Skip the calucation when _dist_ is undefined(light_eyepos3_is_zero)
*/
- if (p->state->unit[i].light_attenuated) {
+ if (p->state->unit[i].light_attenuated && !is_undef(dist)) {
+ if (is_undef(att))
+ att = get_temp(p);
/* 1/d,d,d,1/d */
emit_op1(p, OPCODE_RCP, dist, WRITEMASK_YZ, dist);
/* 1,d,d*d,1/d */
@@ -1113,73 +1119,54 @@ static void build_lighting( struct tnl_program *p )
if (p->state->unit[i].light_enabled) {
struct ureg half = undef;
struct ureg att = undef, VPpli = undef;
+struct ureg dist = undef;
count++;
+ if (p->state->unit[i].light_eyepos3_is_zero) {
+ VPpli = register_param3(p, STATE_INTERNAL,
+ STATE_LIGHT_POSITION_NORMALIZED, i);
+ } else {
+struct ureg Ppli = register_param3(p, STATE_INTERNAL,
+ STATE_LIGHT_POSITION, i);
+struct ureg V = get_eye_position(p);
+
+VPpli = get_temp(p);
+dist = get_temp(p);
+
+/* Calculate VPpli vector
+ */
+emit_op2(p, OPCODE_SUB, VPpli, 0, Ppli, V);
-if (p->state->unit[i].light_eyepos3_is_zero) {
- /* Can used precomputed constants in this case.
-* Attenuation never applies to infinite lights.
-*/
- VPpli = register_param3(p, STATE_INTERNAL,
- STATE_LIGHT_POSITION_NORMALIZED, i);
-
-if (!p->state->material_shininess_is_zero) {
- if (p->state->light_local_viewer) {
- struct ureg eye_hat = get_eye_position_normalized(p);
- half = get_temp(p);
- emit_op2(p, OPCODE_SUB, half, 0, VPpli, eye_hat);
- emit_normalize_vec3(p, half, half);
- }
- else {
- half = register_param3(p, STATE_INTERNAL,
- STATE_LIGHT_HALF_VECTOR, i);
- }
-}
-}
-else {
- struct ureg Ppli = register_param3(p, STATE_INTERNAL,
- STATE_LIGHT_POSITION, i);
- struct ureg V = get_eye_position(p);
- struct ureg dist = get_temp(p);
-
- VPpli = get_temp(p);
-
- /* Calculate VPpli vector
-*/
- emit_op2(p, OPCODE_SUB, VPpli, 0, Ppli, V);
-
- /* Normalize VPpli. The dist value also used in
-* attenuation below.
-*/
- emit_op2(p, OPCODE_DP3, dist, 0, VPpli, VPpli);
- emit_op1(p, OPCODE_RSQ, dist, 0, dist);
- emit_op2(p, OPCODE_MUL, VPpli,
Mesa (master): mesa: make sure all lighting tables are updated before the computation
Module: Mesa
Branch: master
Commit: 099c4e372df0acb2bda61ccf9e6538b3d8349ea3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=099c4e372df0acb2bda61ccf9e6538b3d8349ea3
Author: Yuanhan Liu
Date: Tue Nov 15 15:40:53 2011 +0800
mesa: make sure all lighting tables are updated before the computation
Make sure all lighting tables are updated before using the table to
calculate something, say using _SpotExpTable to calculate
_VP_inf_spot_attenuation.
Signed-off-by: Yuanhan Liu
Reviewed-by: Brian Paul
---
src/mesa/main/light.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/src/mesa/main/light.c b/src/mesa/main/light.c
index c27cf1d..60daa89 100644
--- a/src/mesa/main/light.c
+++ b/src/mesa/main/light.c
@@ -1138,6 +1138,9 @@ compute_light_positions( struct gl_context *ctx )
TRANSFORM_NORMAL( ctx->_EyeZDir, eye_z, ctx->ModelviewMatrixStack.Top->m
);
}
+ /* Make sure all the light tables are updated before the computation */
+ _mesa_validate_all_lighting_tables(ctx);
+
foreach (light, &ctx->Light.EnabledList) {
if (ctx->_NeedEyeCoords) {
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Mesa (master): ir_to_mesa: don't init unfirom if link failed
Module: Mesa
Branch: master
Commit: 9d4d9d34d82646e4e7781bb25a64174d35680578
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9d4d9d34d82646e4e7781bb25a64174d35680578
Author: Yuanhan Liu
Date: Wed Nov 9 14:55:53 2011 +0800
ir_to_mesa: don't init unfirom if link failed
Don't call set_unfiform_initializers if link failed, or it would trigger
a GL_INVALID_OPERATION error. That's not an expected behavior of
glLinkProgram function.
Signed-off-by: Yuanhan Liu
Reviewed-by: Paul Berry
---
src/mesa/program/ir_to_mesa.cpp |4 +++-
1 files changed, 3 insertions(+), 1 deletions(-)
diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
index 0dd44bd..5cee837 100644
--- a/src/mesa/program/ir_to_mesa.cpp
+++ b/src/mesa/program/ir_to_mesa.cpp
@@ -3458,7 +3458,9 @@ _mesa_glsl_link_shader(struct gl_context *ctx, struct
gl_shader_program *prog)
}
}
- set_uniform_initializers(ctx, prog);
+ if (prog->LinkStatus) {
+ set_uniform_initializers(ctx, prog);
+ }
if (ctx->Shader.Flags & GLSL_DUMP) {
if (!prog->LinkStatus) {
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Mesa (master): swrast: simplify the condition test for _swrast_choose_texture_sample_func
Module: Mesa
Branch: master
Commit: 9f7b6a39f6ebc070ff5020578cea2d299b21d476
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f7b6a39f6ebc070ff5020578cea2d299b21d476
Author: Yuanhan Liu
Date: Wed Nov 2 14:46:06 2011 +0800
swrast: simplify the condition test for _swrast_choose_texture_sample_func
remove another long if condition test. I don't feel a strong need of
this patch. But for it make the code a little simpler(I do think so),
I send it out.
Signed-off-by: Yuanhan Liu
Reviewed-by: Brian Paul
---
src/mesa/swrast/s_texfilter.c | 22 +-
1 files changed, 9 insertions(+), 13 deletions(-)
diff --git a/src/mesa/swrast/s_texfilter.c b/src/mesa/swrast/s_texfilter.c
index 9de5c02..5662625 100644
--- a/src/mesa/swrast/s_texfilter.c
+++ b/src/mesa/swrast/s_texfilter.c
@@ -3647,25 +3647,21 @@ _swrast_choose_texture_sample_func( struct gl_context
*ctx,
const struct gl_texture_image *img = t->Image[0][t->BaseLevel];
const struct swrast_texture_image *swImg =
swrast_texture_image_const(img);
+texture_sample_func func;
ASSERT(t->Sampler.MinFilter == GL_NEAREST);
+func = &sample_nearest_2d;
if (t->Sampler.WrapS == GL_REPEAT &&
t->Sampler.WrapT == GL_REPEAT &&
swImg->_IsPowerOfTwo &&
-img->Border == 0 &&
-img->TexFormat == MESA_FORMAT_RGB888) {
- return &opt_sample_rgb_2d;
-}
-else if (t->Sampler.WrapS == GL_REPEAT &&
- t->Sampler.WrapT == GL_REPEAT &&
- swImg->_IsPowerOfTwo &&
- img->Border == 0 &&
- img->TexFormat == MESA_FORMAT_RGBA) {
- return &opt_sample_rgba_2d;
-}
-else {
- return &sample_nearest_2d;
+img->Border == 0) {
+ if (img->TexFormat == MESA_FORMAT_RGB888)
+ func = &opt_sample_rgb_2d;
+ else if (img->TexFormat == MESA_FORMAT_RGBA)
+ func = &opt_sample_rgba_2d;
}
+
+return func;
}
case GL_TEXTURE_3D:
if (needLambda) {
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Mesa (master): mesa: fix the low limit of width and height for glRenderbufferStorage
Module: Mesa
Branch: master
Commit: 49f8447acc430944504c658c2d2b4a2ccb3af0bc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=49f8447acc430944504c658c2d2b4a2ccb3af0bc
Author: Yuanhan Liu
Date: Tue Oct 25 15:36:59 2011 +0800
mesa: fix the low limit of width and height for glRenderbufferStorage
glRenderbufferStorage man page says:
GL_INVALID_VALUE is generated if either of width or height is negative,
or greater than the value of GL_MAX_RENDERBUFFER_SIZE.
NOTE: this is a candidate for the 7.11 branch
Signed-off-by: Yuanhan Liu
Reviewed-by: Brian Paul
---
src/mesa/main/fbobject.c |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index c56062a..ff46570 100644
--- a/src/mesa/main/fbobject.c
+++ b/src/mesa/main/fbobject.c
@@ -1370,12 +1370,12 @@ renderbuffer_storage(GLenum target, GLenum
internalFormat,
return;
}
- if (width < 1 || width > (GLsizei) ctx->Const.MaxRenderbufferSize) {
+ if (width < 0 || width > (GLsizei) ctx->Const.MaxRenderbufferSize) {
_mesa_error(ctx, GL_INVALID_VALUE, "%s(width)", func);
return;
}
- if (height < 1 || height > (GLsizei) ctx->Const.MaxRenderbufferSize) {
+ if (height < 0 || height > (GLsizei) ctx->Const.MaxRenderbufferSize) {
_mesa_error(ctx, GL_INVALID_VALUE, "%s(height)", func);
return;
}
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Mesa (master): mesa: fix inital value for new renderbuffer
Module: Mesa Branch: master Commit: 1f5bd65efa228736d41956f9e76df350dfe2d5d2 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f5bd65efa228736d41956f9e76df350dfe2d5d2 Author: Yuanhan Liu Date: Tue Oct 25 15:28:50 2011 +0800 mesa: fix inital value for new renderbuffer EXT_framebuffer_object bspec says: Get Value TypeGet Command Initial Value ----- --- --- RENDERBUFFER_INTERNAL_FORMAT_EXT Z+ GetRenderbufferParameterivEXT RGBA NOTE: this is a candidate for the 7.11 branch Signed-off-by: Yuanhan Liu Reviewed-by: Brian Paul --- src/mesa/main/renderbuffer.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/main/renderbuffer.c b/src/mesa/main/renderbuffer.c index 5dd46cc..33bec42 100644 --- a/src/mesa/main/renderbuffer.c +++ b/src/mesa/main/renderbuffer.c @@ -2011,7 +2011,7 @@ _mesa_init_renderbuffer(struct gl_renderbuffer *rb, GLuint name) rb->Width = 0; rb->Height = 0; - rb->InternalFormat = GL_NONE; + rb->InternalFormat = GL_RGBA; rb->Format = MESA_FORMAT_NONE; rb->DataType = GL_NONE; ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa: complete the GL_TEXTURE_SWIZZLE* setup
Module: Mesa
Branch: master
Commit: 77cd3bf18d509dcbb2f121e4082027f4048ca623
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=77cd3bf18d509dcbb2f121e4082027f4048ca623
Author: Yuanhan Liu
Date: Fri Oct 21 11:27:25 2011 +0800
mesa: complete the GL_TEXTURE_SWIZZLE* setup
The ARB_texture_swizzle spec says:
The error INVALID_OPERATION is generated if TexParameteri,
TexParameterf, TexParameteriv, or TexParameterfv, parameter
is TEXTURE_SWIZZLE_R, TEXTURE_SWIZZLE_G, TEXTURE_SWIZZLE_B,
or TEXTURE_SWIZZLE_A, and is not RED, GREEN, BLUE, ALPHA,
ZERO, or ONE.
The error INVALID_OPERATION is generated if TexParameteriv, or
TexParameterfv, parameter TEXTURE_SWIZZLE_RGBA, and the four
consecutive values pointed to by are not all RED, GREEN, BLUE,
ALPHA, ZERO, or ONE.
So, the GL_TEXTURE_SWIZZLE* pname is legal for glTexParameterf(v)
NOTE: this is a candidate for the 7.11 branch
Signed-off-by: Yuanhan Liu
Reviewed-by: Brian Paul
---
src/mesa/main/texparam.c | 27 +++
1 files changed, 27 insertions(+), 0 deletions(-)
diff --git a/src/mesa/main/texparam.c b/src/mesa/main/texparam.c
index 6da730d..73e5cbe 100644
--- a/src/mesa/main/texparam.c
+++ b/src/mesa/main/texparam.c
@@ -596,6 +596,17 @@ _mesa_TexParameterf(GLenum target, GLenum pname, GLfloat
param)
need_update = set_tex_parameteri(ctx, texObj, pname, p);
}
break;
+ case GL_TEXTURE_SWIZZLE_R_EXT:
+ case GL_TEXTURE_SWIZZLE_G_EXT:
+ case GL_TEXTURE_SWIZZLE_B_EXT:
+ case GL_TEXTURE_SWIZZLE_A_EXT:
+ {
+ GLint p[4];
+ p[0] = (GLint) param;
+ p[1] = p[2] = p[3] = 0;
+ need_update = set_tex_parameteri(ctx, texObj, pname, p);
+ }
+ break;
default:
{
/* this will generate an error if pname is illegal */
@@ -661,6 +672,22 @@ _mesa_TexParameterfv(GLenum target, GLenum pname, const
GLfloat *params)
break;
#endif
+ case GL_TEXTURE_SWIZZLE_R_EXT:
+ case GL_TEXTURE_SWIZZLE_G_EXT:
+ case GL_TEXTURE_SWIZZLE_B_EXT:
+ case GL_TEXTURE_SWIZZLE_A_EXT:
+ case GL_TEXTURE_SWIZZLE_RGBA_EXT:
+ {
+ GLint p[4] = {0, 0, 0, 0};
+ p[0] = (GLint) params[0];
+ if (pname == GL_TEXTURE_SWIZZLE_RGBA_EXT) {
+p[1] = (GLint) params[1];
+p[2] = (GLint) params[2];
+p[3] = (GLint) params[3];
+ }
+ need_update = set_tex_parameteri(ctx, texObj, pname, p);
+ }
+ break;
default:
/* this will generate an error if pname is illegal */
need_update = set_tex_parameterf(ctx, texObj, pname, params);
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Mesa (master): mesa: remove the redundant check
Module: Mesa
Branch: master
Commit: d9f05ac828986a2fcdca9fcae29d76f79847d8d3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d9f05ac828986a2fcdca9fcae29d76f79847d8d3
Author: Yuanhan Liu
Date: Fri Oct 21 11:24:18 2011 +0800
mesa: remove the redundant check
Signed-off-by: Yuanhan Liu
Reviewed-by: Brian Paul
---
src/mesa/main/texparam.c | 11 +--
1 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/src/mesa/main/texparam.c b/src/mesa/main/texparam.c
index a242448..6da730d 100644
--- a/src/mesa/main/texparam.c
+++ b/src/mesa/main/texparam.c
@@ -394,12 +394,11 @@ set_tex_parameteri(struct gl_context *ctx,
return GL_FALSE;
}
ASSERT(comp < 4);
- if (swz >= 0) {
-flush(ctx);
-texObj->Swizzle[comp] = params[0];
-set_swizzle_component(&texObj->_Swizzle, comp, swz);
-return GL_TRUE;
- }
+
+ flush(ctx);
+ texObj->Swizzle[comp] = params[0];
+ set_swizzle_component(&texObj->_Swizzle, comp, swz);
+ return GL_TRUE;
}
goto invalid_pname;
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Mesa (master): intel: fix potential segfault error
Module: Mesa
Branch: master
Commit: 81d5195a6105606910d0d19ab059962e5712c2e0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=81d5195a6105606910d0d19ab059962e5712c2e0
Author: Yuanhan Liu
Date: Tue Nov 1 17:41:08 2011 +0800
intel: fix potential segfault error
Signed-off-by: Yuanhan Liu
Reviewed-by: Kenneth Graunke
---
src/mesa/drivers/dri/intel/intel_tex_validate.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c
b/src/mesa/drivers/dri/intel/intel_tex_validate.c
index a657732..f4c1a68 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c
@@ -125,14 +125,16 @@ intel_tex_map_image_for_swrast(struct intel_context
*intel,
struct intel_texture_image *intel_image,
GLbitfield mode)
{
- int level = intel_image->base.Base.Level;
- int face = intel_image->base.Base.Face;
+ int level;
+ int face;
struct intel_mipmap_tree *mt;
unsigned int x, y;
if (!intel_image || !intel_image->mt)
return;
+ level = intel_image->base.Base.Level;
+ face = intel_image->base.Base.Face;
mt = intel_image->mt;
if (mt->target == GL_TEXTURE_3D ||
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Mesa (master): mesa: handle PBO access error in display list mode
Module: Mesa Branch: master Commit: 46d5fb576a37bdd50cd4a2795b27852b4c8a8250 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=46d5fb576a37bdd50cd4a2795b27852b4c8a8250 Author: Yuanhan Liu Date: Wed Oct 19 11:20:18 2011 +0800 mesa: handle PBO access error in display list mode Simply generate GL_INVALID_OPERATION error at display list mode. As explained by Brian, we are going to access PBO data at compile time. No need to defer the error at execution time. Signed-off-by: Yuanhan Liu Reviewed-by: Brian Paul --- src/mesa/main/dlist.c |2 ++ 1 files changed, 2 insertions(+), 0 deletions(-) diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c index 625649e..d901bdd 100644 --- a/src/mesa/main/dlist.c +++ b/src/mesa/main/dlist.c @@ -939,7 +939,9 @@ unpack_image(struct gl_context *ctx, GLuint dimensions, } return image; } + /* bad access! */ + _mesa_error(ctx, GL_INVALID_OPERATION, "invalid PBO access"); return NULL; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa: handle the pbo case for save_Bitmap
Module: Mesa
Branch: master
Commit: 02b801c1edec6400a4192e3e5b0595b13b771b18
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=02b801c1edec6400a4192e3e5b0595b13b771b18
Author: Yuanhan Liu
Date: Sat Oct 15 22:44:18 2011 +0800
mesa: handle the pbo case for save_Bitmap
Wrap _mesa_unpack_bitmap to handle the case that data is stored in pixel
buffer object.
This would make calling Bitmap with data stored in PBO by display list work.
Signed-off-by: Yuanhan Liu
Reviewed-by: Brian Paul
---
src/mesa/main/dlist.c | 22 +++---
1 files changed, 15 insertions(+), 7 deletions(-)
diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c
index ceb75c4..625649e 100644
--- a/src/mesa/main/dlist.c
+++ b/src/mesa/main/dlist.c
@@ -875,7 +875,7 @@ translate_id(GLsizei n, GLenum type, const GLvoid * list)
/**/
/**
- * Wrapper for _mesa_unpack_image() that handles pixel buffer objects.
+ * Wrapper for _mesa_unpack_image/bitmap() that handles pixel buffer objects.
* If width < 0 or height < 0 or format or type are invalid we'll just
* return NULL. We will not generate an error since OpenGL command
* arguments aren't error-checked until the command is actually executed
@@ -899,8 +899,13 @@ unpack_image(struct gl_context *ctx, GLuint dimensions,
if (!_mesa_is_bufferobj(unpack->BufferObj)) {
/* no PBO */
- GLvoid *image = _mesa_unpack_image(dimensions, width, height, depth,
- format, type, pixels, unpack);
+ GLvoid *image;
+
+ if (type == GL_BITMAP)
+ image = _mesa_unpack_bitmap(width, height, pixels, unpack);
+ else
+ image = _mesa_unpack_image(dimensions, width, height, depth,
+format, type, pixels, unpack);
if (pixels && !image) {
_mesa_error(ctx, GL_OUT_OF_MEMORY, "display list construction");
}
@@ -921,8 +926,11 @@ unpack_image(struct gl_context *ctx, GLuint dimensions,
}
src = ADD_POINTERS(map, pixels);
- image = _mesa_unpack_image(dimensions, width, height, depth,
- format, type, src, unpack);
+ if (type == GL_BITMAP)
+ image = _mesa_unpack_bitmap(width, height, src, unpack);
+ else
+ image = _mesa_unpack_image(dimensions, width, height, depth,
+format, type, src, unpack);
ctx->Driver.UnmapBuffer(ctx, unpack->BufferObj);
@@ -935,7 +943,6 @@ unpack_image(struct gl_context *ctx, GLuint dimensions,
return NULL;
}
-
/**
* Allocate space for a display list instruction (opcode + payload space).
* \param opcode the instruction opcode (OPCODE_* value)
@@ -1121,7 +1128,8 @@ save_Bitmap(GLsizei width, GLsizei height,
n[4].f = yorig;
n[5].f = xmove;
n[6].f = ymove;
- n[7].data = _mesa_unpack_bitmap(width, height, pixels, &ctx->Unpack);
+ n[7].data = unpack_image(ctx, 2, width, height, 1, GL_COLOR_INDEX,
+ GL_BITMAP, pixels, &ctx->Unpack);
}
if (ctx->ExecuteFlag) {
CALL_Bitmap(ctx->Exec, (width, height,
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Mesa (master): mesa: fix inverted pbo test error at _mesa_GetnCompressedTexImageARB
Module: Mesa
Branch: master
Commit: 403cf7c56fc6decb7636114dc1dadb7adf99a7a4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=403cf7c56fc6decb7636114dc1dadb7adf99a7a4
Author: Yuanhan Liu
Date: Sun Oct 16 09:35:33 2011 +0800
mesa: fix inverted pbo test error at _mesa_GetnCompressedTexImageARB
It seems like a typo.
Signed-off-by: Yuanhan Liu
Reviewed-by: Brian Paul
---
src/mesa/main/texgetimage.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/mesa/main/texgetimage.c b/src/mesa/main/texgetimage.c
index f911886..06e0323 100644
--- a/src/mesa/main/texgetimage.c
+++ b/src/mesa/main/texgetimage.c
@@ -884,7 +884,7 @@ _mesa_GetnCompressedTexImageARB(GLenum target, GLint level,
GLsizei bufSize,
return;
}
- if (_mesa_is_bufferobj(ctx->Pack.BufferObj) && !img) {
+ if (!_mesa_is_bufferobj(ctx->Pack.BufferObj) && !img) {
/* not an error, do nothing */
return;
}
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Mesa (master): mesa: generate error if pbo offset is not aligned with the size of specified type
Module: Mesa
Branch: master
Commit: 9024d8af0ae832a0b4278eb6683bc0e76c69baac
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9024d8af0ae832a0b4278eb6683bc0e76c69baac
Author: Yuanhan Liu
Date: Mon Oct 17 09:57:36 2011 +0800
mesa: generate error if pbo offset is not aligned with the size of specified
type
v2: quote the spec; explicitly exclude the GL_BITMAP case to make code
more readable. (comments from Ian)
v3: Cast the offset by GLintptr to remove the compile warning(comments
from Brian).
I also found that I should use _mesa_sizeof_packed_type() instead,
as it includes packed pixel type, like GL_UNSIGNED_SHORT_5_6_5.
Signed-off-by: Yuanhan Liu
Reviewed-by: Brian Paul
---
src/mesa/main/pbo.c | 13 +
1 files changed, 13 insertions(+), 0 deletions(-)
diff --git a/src/mesa/main/pbo.c b/src/mesa/main/pbo.c
index 4e7e6f9..41ff2ff 100644
--- a/src/mesa/main/pbo.c
+++ b/src/mesa/main/pbo.c
@@ -82,6 +82,19 @@ _mesa_validate_pbo_access(GLuint dimensions,
} else {
offset = ptr;
sizeAddr = ((const GLubyte *) 0) + pack->BufferObj->Size;
+ /* The ARB_pixel_buffer_object spec says:
+ *"INVALID_OPERATION is generated by ColorTable, ColorSubTable,
+ *ConvolutionFilter2D, ConvolutionFilter1D, SeparableFilter2D,
+ *TexImage1D, TexImage2D, TexImage3D, TexSubImage1D,
+ *TexSubImage2D, TexSubImage3D, and DrawPixels if the current
+ *PIXEL_UNPACK_BUFFER_BINDING_ARB value is non-zero and the data
+ *parameter is not evenly divisible into the number of basic machine
+ *units needed to store in memory a datum indicated by the type
+ *parameter."
+ */
+ if (type != GL_BITMAP &&
+ ((GLintptr)offset % _mesa_sizeof_packed_type(type)))
+ return GL_FALSE;
}
if (sizeAddr == 0)
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Mesa (master): i965: setup address rounding enable bits
Module: Mesa Branch: master Commit: 76669381c0de6a49a1edd0b88fa1ae6b86f10b30 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=76669381c0de6a49a1edd0b88fa1ae6b86f10b30 Author: Yuanhan Liu Date: Fri Oct 14 13:47:10 2011 +0800 i965: setup address rounding enable bits The patch(based on the reading of the emulator) came from while I was trying to fix the oglc pbo texImage.1PBODefaults fail. This case generates a texture with the width and height equal to window's width and height respectively, then try to texture it on the whole window. So, it's exactly one texel for one pixel. And, the min filter and mag filter are GL_LINEAR. It runs with swrast OK, as expected. But it failed with i965 driver. Well, you can't tell the difference from the screen, as the error is quite tiny. From my digging, it seems that there are some tiny error happened while getting tex address. This will break the one texel for one pixel rule in this case. Thus the linear result is taken, with tiny error. This patch would fix all oglc pbo subcase fail with the same issue on both ILK, SNB and IVB. v2: comments from Ian, make the address_round filed assignment consistent. (the sampler is alread memset to 0 by the xxx_update_samper_state caller, so need to assign 0 first) Signed-off-by: Yuanhan Liu --- src/mesa/drivers/dri/i965/brw_defines.h |7 +++ src/mesa/drivers/dri/i965/brw_wm_sampler_state.c |9 + src/mesa/drivers/dri/i965/gen7_sampler_state.c |9 + 3 files changed, 25 insertions(+), 0 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 308a842..5314ac6 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -196,6 +196,13 @@ #define BRW_MIPFILTER_NEAREST 1 #define BRW_MIPFILTER_LINEAR 3 +#define BRW_ADDRESS_ROUNDING_ENABLE_U_MAG 0x20 +#define BRW_ADDRESS_ROUNDING_ENABLE_U_MIN 0x10 +#define BRW_ADDRESS_ROUNDING_ENABLE_V_MAG 0x08 +#define BRW_ADDRESS_ROUNDING_ENABLE_V_MIN 0x04 +#define BRW_ADDRESS_ROUNDING_ENABLE_R_MAG 0x02 +#define BRW_ADDRESS_ROUNDING_ENABLE_R_MIN 0x01 + #define BRW_POLYGON_FRONT_FACING 0 #define BRW_POLYGON_BACK_FACING 1 diff --git a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c index 6834eba..8938561 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_sampler_state.c @@ -312,6 +312,15 @@ static void brw_update_sampler_state(struct brw_context *brw, intel->batch.bo, brw->wm.sdc_offset[unit], I915_GEM_DOMAIN_SAMPLER, 0); } + + if (sampler->ss0.min_filter != BRW_MAPFILTER_NEAREST) + sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN | +BRW_ADDRESS_ROUNDING_ENABLE_V_MIN | +BRW_ADDRESS_ROUNDING_ENABLE_R_MIN; + if (sampler->ss0.mag_filter != BRW_MAPFILTER_NEAREST) + sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG | +BRW_ADDRESS_ROUNDING_ENABLE_V_MAG | +BRW_ADDRESS_ROUNDING_ENABLE_R_MAG; } diff --git a/src/mesa/drivers/dri/i965/gen7_sampler_state.c b/src/mesa/drivers/dri/i965/gen7_sampler_state.c index aee67c8..f6f51c5 100644 --- a/src/mesa/drivers/dri/i965/gen7_sampler_state.c +++ b/src/mesa/drivers/dri/i965/gen7_sampler_state.c @@ -167,6 +167,15 @@ gen7_update_sampler_state(struct brw_context *brw, int unit, upload_default_color(brw, gl_sampler, unit); sampler->ss2.default_color_pointer = brw->wm.sdc_offset[unit] >> 5; + + if (sampler->ss0.min_filter != BRW_MAPFILTER_NEAREST) + sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MIN | +BRW_ADDRESS_ROUNDING_ENABLE_V_MIN | +BRW_ADDRESS_ROUNDING_ENABLE_R_MIN; + if (sampler->ss0.mag_filter != BRW_MAPFILTER_NEAREST) + sampler->ss3.address_round |= BRW_ADDRESS_ROUNDING_ENABLE_U_MAG | +BRW_ADDRESS_ROUNDING_ENABLE_V_MAG | +BRW_ADDRESS_ROUNDING_ENABLE_R_MAG; } ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): mesa: add a function to do the image data copy stuff for save_CompressedTex(Sub) Image
Module: Mesa
Branch: master
Commit: e9edcf8b1d6f319af6db8dd25aa267f662456139
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e9edcf8b1d6f319af6db8dd25aa267f662456139
Author: Yuanhan Liu
Date: Fri Oct 14 14:28:22 2011 +0800
mesa: add a function to do the image data copy stuff for
save_CompressedTex(Sub)Image
Introuduce a simple function called copy_data to do the image data copy
stuff for all the save_CompressedTex*Image function. The function check
the NULL data case to avoid some potential segfault. This also would
make the code a bit simpler and less redundance.
Signed-off-by: Yuanhan Liu
Reviewed-by: Brian Paul
---
src/mesa/main/dlist.c | 102 +
1 files changed, 27 insertions(+), 75 deletions(-)
diff --git a/src/mesa/main/dlist.c b/src/mesa/main/dlist.c
index 343feec..567629d 100644
--- a/src/mesa/main/dlist.c
+++ b/src/mesa/main/dlist.c
@@ -4509,6 +4509,24 @@ save_MultTransposeMatrixfARB(const GLfloat m[16])
save_MultMatrixf(tm);
}
+static GLvoid *copy_data(const GLvoid *data, GLsizei size, const char *func)
+{
+ GET_CURRENT_CONTEXT(ctx);
+ GLvoid *image;
+
+ if (!data)
+ return NULL;
+
+ image = malloc(size);
+ if (!image) {
+ _mesa_error(ctx, GL_OUT_OF_MEMORY, func);
+ return NULL;
+ }
+ memcpy(image, data, size);
+
+ return image;
+}
+
/* GL_ARB_texture_compression */
static void GLAPIENTRY
@@ -4526,15 +4544,8 @@ save_CompressedTexImage1DARB(GLenum target, GLint level,
}
else {
Node *n;
- GLvoid *image;
ASSERT_OUTSIDE_SAVE_BEGIN_END_AND_FLUSH(ctx);
- /* make copy of image */
- image = malloc(imageSize);
- if (!image) {
- _mesa_error(ctx, GL_OUT_OF_MEMORY, "glCompressedTexImage1DARB");
- return;
- }
- memcpy(image, data, imageSize);
+
n = alloc_instruction(ctx, OPCODE_COMPRESSED_TEX_IMAGE_1D, 7);
if (n) {
n[1].e = target;
@@ -4543,10 +4554,7 @@ save_CompressedTexImage1DARB(GLenum target, GLint level,
n[4].i = (GLint) width;
n[5].i = border;
n[6].i = imageSize;
- n[7].data = image;
- }
- else if (image) {
- free(image);
+ n[7].data = copy_data(data, imageSize, "glCompressedTexImage1DARB");
}
if (ctx->ExecuteFlag) {
CALL_CompressedTexImage1DARB(ctx->Exec,
@@ -4572,15 +4580,8 @@ save_CompressedTexImage2DARB(GLenum target, GLint level,
}
else {
Node *n;
- GLvoid *image;
ASSERT_OUTSIDE_SAVE_BEGIN_END_AND_FLUSH(ctx);
- /* make copy of image */
- image = malloc(imageSize);
- if (!image) {
- _mesa_error(ctx, GL_OUT_OF_MEMORY, "glCompressedTexImage2DARB");
- return;
- }
- memcpy(image, data, imageSize);
+
n = alloc_instruction(ctx, OPCODE_COMPRESSED_TEX_IMAGE_2D, 8);
if (n) {
n[1].e = target;
@@ -4590,10 +4591,7 @@ save_CompressedTexImage2DARB(GLenum target, GLint level,
n[5].i = (GLint) height;
n[6].i = border;
n[7].i = imageSize;
- n[8].data = image;
- }
- else if (image) {
- free(image);
+ n[8].data = copy_data(data, imageSize, "glCompressedTexImage2DARB");
}
if (ctx->ExecuteFlag) {
CALL_CompressedTexImage2DARB(ctx->Exec,
@@ -4619,15 +4617,8 @@ save_CompressedTexImage3DARB(GLenum target, GLint level,
}
else {
Node *n;
- GLvoid *image;
ASSERT_OUTSIDE_SAVE_BEGIN_END_AND_FLUSH(ctx);
- /* make copy of image */
- image = malloc(imageSize);
- if (!image) {
- _mesa_error(ctx, GL_OUT_OF_MEMORY, "glCompressedTexImage3DARB");
- return;
- }
- memcpy(image, data, imageSize);
+
n = alloc_instruction(ctx, OPCODE_COMPRESSED_TEX_IMAGE_3D, 9);
if (n) {
n[1].e = target;
@@ -4638,10 +4629,7 @@ save_CompressedTexImage3DARB(GLenum target, GLint level,
n[6].i = (GLint) depth;
n[7].i = border;
n[8].i = imageSize;
- n[9].data = image;
- }
- else if (image) {
- free(image);
+ n[9].data = copy_data(data, imageSize, "glCompressedTexImage3DARB");
}
if (ctx->ExecuteFlag) {
CALL_CompressedTexImage3DARB(ctx->Exec,
@@ -4659,18 +4647,9 @@ save_CompressedTexSubImage1DARB(GLenum target, GLint
level, GLint xoffset,
GLsizei imageSize, const GLvoid * data)
{
Node *n;
- GLvoid *image;
-
GET_CURRENT_CONTEXT(ctx);
ASSERT_OUTSIDE_SAVE_BEGIN_END_AND_FLUSH(ctx);
- /* make copy of image */
- image = malloc(imageSize);
- if (!image) {
- _mesa_error(ctx, GL_OUT_OF_MEMORY, "glCompressedTexSubImage1DARB");
- return;
- }
- memcpy(image, data, imageSize);
n = alloc_instruction(ctx, OPCODE_COMPRESSED_TEX_SUB_IMAGE_1D, 7);
if (n) {
n[1].e = ta
Mesa (master): intel: fix potential segfault error at intel_(un) map_texture_image
Module: Mesa
Branch: master
Commit: 455a19b1b3d7ca0a40c65d89e45209dbd8ac7b35
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=455a19b1b3d7ca0a40c65d89e45209dbd8ac7b35
Author: Yuanhan Liu
Date: Mon Sep 26 09:23:06 2011 +0800
intel: fix potential segfault error at intel_(un)map_texture_image
intel_image->mt might be NULL, say with border width set. It then would
trigger a segfault at intel_map/unmap_texture_image function.
This would fix the oglc misctest(basic.textureBorderIgnore) fail.
Signed-off-by: Yuanhan Liu
---
src/mesa/drivers/dri/intel/intel_tex.c |5 +++--
1 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_tex.c
b/src/mesa/drivers/dri/intel/intel_tex.c
index 8d3cbd6..f8c3f77 100644
--- a/src/mesa/drivers/dri/intel/intel_tex.c
+++ b/src/mesa/drivers/dri/intel/intel_tex.c
@@ -113,7 +113,7 @@ intel_map_texture_image(struct gl_context *ctx,
* row of blocks. intel_miptree_get_image_offset() already does
* the divide.
*/
- _mesa_get_format_block_size(mt->format, &bw, &bh);
+ _mesa_get_format_block_size(tex_image->TexFormat, &bw, &bh);
assert(y % bh == 0);
y /= bh;
@@ -150,7 +150,8 @@ intel_unmap_texture_image(struct gl_context *ctx,
struct intel_context *intel = intel_context(ctx);
struct intel_texture_image *intel_image = intel_texture_image(tex_image);
- intel_region_unmap(intel, intel_image->mt->region);
+ if (intel_image->mt)
+ intel_region_unmap(intel, intel_image->mt->region);
if (intel_image->stencil_rb) {
/*
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Mesa (master): intel: fix the wrong code to detect null texture.
Module: Mesa
Branch: master
Commit: 1a662e7c18cab98f1b122f6766faf338725de673
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1a662e7c18cab98f1b122f6766faf338725de673
Author: Yuanhan Liu
Date: Fri Sep 23 13:34:26 2011 +0800
intel: fix the wrong code to detect null texture.
There is already comments show how to detect a null texture. Fix the
code to match the comments.
This would fix the oglc divzero(basic.texQOrWEqualsZero) and
divzero(basic.texTrivialPrim) test case fail.
Signed-off-by: Yuanhan Liu
Reviewed-by: Kenneth Graunke
Reviewed-by: Eric Anholt
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index b77c5d7..18427b5 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -136,7 +136,7 @@ intel_miptree_create(struct intel_context *intel,
/*
* pitch == 0 || height == 0 indicates the null texture
*/
- if (!mt || !mt->total_height) {
+ if (!mt || !mt->total_width || !mt->total_height) {
free(mt);
return NULL;
}
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Mesa (master): i965: fix the constant interp bitmask for flat mode
Module: Mesa
Branch: master
Commit: cd6b8421cac2df89dc6365ce368232e461caffcd
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cd6b8421cac2df89dc6365ce368232e461caffcd
Author: Yuanhan Liu
Date: Tue Sep 6 09:29:37 2011 +0800
i965: fix the constant interp bitmask for flat mode
Fix the constant interpolation enable bit mask for flat light mode.
FRAG_BIT_COL0 attribute bit might be 0, in which case we need to
shift one more bit right.
This would fix the oglc specularColor test fail on both Sandybridge and
Ivybridge.
v2: move the constant interp bitmask setup code into for(; attr <
FRAG_ATTRIB_MAX; attr++) loop suggested by Eric.
Signed-off-by: Yuanhan Liu
Signed-off-by: Xiang, Haihao
---
src/mesa/drivers/dri/i965/gen6_sf_state.c | 19 +--
src/mesa/drivers/dri/i965/gen7_sf_state.c | 19 +--
2 files changed, 26 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen6_sf_state.c
b/src/mesa/drivers/dri/i965/gen6_sf_state.c
index 4482e9c..5cbfe78 100644
--- a/src/mesa/drivers/dri/i965/gen6_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_sf_state.c
@@ -263,12 +263,6 @@ upload_sf_state(struct brw_context *brw)
(1 << GEN6_SF_TRIFAN_PROVOKE_SHIFT);
}
- /* flat shading */
- if (ctx->Light.ShadeModel == GL_FLAT) {
- dw17 |= ((brw->fragment_program->Base.InputsRead & (FRAG_BIT_COL0 |
FRAG_BIT_COL1)) >>
-((brw->fragment_program->Base.InputsRead & FRAG_BIT_WPOS) ? 0
: 1));
- }
-
/* Create the mapping from the FS inputs we produce to the VS outputs
* they source from.
*/
@@ -286,6 +280,19 @@ upload_sf_state(struct brw_context *brw)
if (attr == FRAG_ATTRIB_PNTC)
dw16 |= (1 << input_index);
+ /* flat shading */
+ if (ctx->Light.ShadeModel == GL_FLAT) {
+ /*
+ * Setup the Constant Interpolation Enable bit mask for each
+ * corresponding attribute(currently, we only care two attrs:
+ * FRAG_BIT_COL0 and FRAG_BIT_COL1).
+ *
+ * FIXME: should we care other attributes?
+ */
+ if (attr == FRAG_ATTRIB_COL0 || attr == FRAG_ATTRIB_COL1)
+ dw17 |= (1 << input_index);
+ }
+
/* The hardware can only do the overrides on 16 overrides at a
* time, and the other up to 16 have to be lined up so that the
* input index = the output index. We'll need to do some
diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c
b/src/mesa/drivers/dri/i965/gen7_sf_state.c
index 85d2d87..b1bec1a 100644
--- a/src/mesa/drivers/dri/i965/gen7_sf_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c
@@ -68,13 +68,7 @@ upload_sbe_state(struct brw_context *brw)
dw1 |= GEN6_SF_POINT_SPRITE_LOWERLEFT;
dw10 = 0;
-
- /* _NEW_LIGHT (flat shading) */
dw11 = 0;
- if (ctx->Light.ShadeModel == GL_FLAT) {
- dw11 |= ((brw->fragment_program->Base.InputsRead & (FRAG_BIT_COL0 |
FRAG_BIT_COL1)) >>
-((brw->fragment_program->Base.InputsRead & FRAG_BIT_WPOS) ? 0
: 1));
- }
/* Create the mapping from the FS inputs we produce to the VS outputs
* they source from.
@@ -92,6 +86,19 @@ upload_sbe_state(struct brw_context *brw)
if (attr == FRAG_ATTRIB_PNTC)
dw10 |= (1 << input_index);
+ /* flat shading */
+ if (ctx->Light.ShadeModel == GL_FLAT) {
+ /*
+ * Setup the Constant Interpolation Enable bit mask for each
+ * corresponding attribute(currently, we only care two attrs:
+ * FRAG_BIT_COL0 and FRAG_BIT_COL1).
+ *
+ * FIXME: should we care other attributes?
+ */
+ if (attr == FRAG_ATTRIB_COL0 || attr == FRAG_ATTRIB_COL1)
+ dw11 |= (1 << input_index);
+ }
+
/* The hardware can only do the overrides on 16 overrides at a
* time, and the other up to 16 have to be lined up so that the
* input index = the output index. We'll need to do some
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