URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bcb7e8b084f334e101d3a95c8f1d78bc77d653c2
Author: Emil Velikov <emil.veli...@collabora.com>
Date: Wed Mar 30 00:10:07 2016 +0100
Update version to 11.2.0-rc4
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0efb7fb803f49b358a7976eba2d8b9f4956ab052
Author: Kenneth Graunke <kenn...@whitecape.org>
Date: Fri Mar 25 15:33:35 2016 -0700
i965: Fix brw_render_cache_set_check_flush's PIPE_CONTROLs.
Our driver uses the brw_render_cache mechanism to track buffers we've
rendered to and are about to sample from.
Previously, we did a single PIPE_CONTROL with the following bits set:
- Render Target Flush
- Depth Cache Flush
- Texture Cache Invalidate
- VF Cache Invalidate
- Instruction Cache Invalidate
- CS Stall
This combined both "top of pipe" invalidations and "bottom of pipe"
flushes, which isn't how the hardware is intended to be programmed.
The "top of pipe" invalidations may happen right away, without any
guarantees that rendering using those caches has completed. That
rendering may continue altering the caches. The "bottom of pipe"
flushes do wait for the rendering to complete. The CS stall also
prevents further work from happening until data is flushed out.
What we wanted to do was wait for rendering complete, flush the new
data out of the render and depth caches, wait, then invalidate any
stale data in read-only caches. We can accomplish this by doing the
"bottom of pipe" flushes with a CS stall, then the "top of pipe"
flushes as a second PIPE_CONTROL. The flushes will wait until the
rendering is complete, and the CS stall will prevent the second
PIPE_CONTROL with the invalidations from executing until the first
is done.
Fixes dEQP-GLES3.functional.texture.specification.teximage2d_pbo
subtests on Braswell and Skylake. These tests hit the meta PBO
texture upload path, which binds the PBO as a texture and samples
from it, while rendering to the destination texture. The tests
then sample from the texture.
For now, we leave Gen4-5 alone. It probably needs work too, but
apparently it hasn't even been setting the (G45+) TC invalidation
bit at all...
v2: Add Sandybridge post-sync non-zero workaround, for safety.
Cc: mesa-sta...@lists.freedesktop.org
Suggested-by: Francisco Jerez <curroje...@riseup.net>
Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
Reviewed-by: Francisco Jerez <curroje...@riseup.net>
(cherry picked from commit 72473658c51d5e074ce219c1e6385a4cce29f467)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=11654dda562188ba3cc743bcc286e7e48dde43e0
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Sat Mar 26 22:32:43 2016 -0400
nvc0: disable primitive restart and index bias during blits
Back in the dawn of time, we used to do immediate uploads for the vertex
data, and all was well. However Maxwell dropped support for immediate
vertex data, so we started feeding in a VBO (in all cases). But we
forgot to disable some things that apply in such cases, specifically
primitive restart and index bias. The latter was causing WoW and other
Blizzard games trouble as they use a pattern where they draw with a base
vertex (aka index bias), followed by texture uploads (aka blits,
internally).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91526
Cc: "11.1 11.2" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Tested-by: Karol Herbst <nouv...@karolherbst.de>
(cherry picked from commit 41100b6b44e747b9003937f123fce571fd3dec46)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a715e4f40f4b2359cdd9712601a069e6e0f95607
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Sun Mar 20 17:26:13 2016 -0400
nvc0/ir: fix picking of coordinates from tex instruction for textureGrad
On Fermi, there's an argument in front of the coords that combines array
and indirect handle, while on Kepler the array and the indirect handle
are separate (and in front of the coords). We were previously only
accounting for the array bit of it, if there were an indirect access it
wouldn't be counted in the formula.
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Cc: "11.1 11.2" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit f667d15561820ee9dd8e836d43cce3ee52a4780e)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=afd477472120b2c0646a59525dd717dac9dee80c
Author: Anuj Phogat <anuj.pho...@gmail.com>
Date: Fri Mar 11 15:24:36 2016 -0800
i965: Fix assert conditions for src/dst x/y offsets
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
(cherry picked from commit 4ba47f7b2adf71ed100cd390a1a9fbd4434e896a)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=864eba84dd8437e7f13473e68d43a9c1d3f9575f
Author: xavier <xavi...@gmail.com>
Date: Wed Mar 9 09:58:48 2016 +0100
r600/sb: Do not distribute neg in expr_handler::fold_assoc() when folding
multiplications.
Previously it was doing this transformation for a Trine 3 shader:
MUL R6.x.12, R13.x.23, 0.5|3f000000
- MULADD R4.x.12, -R6.x.12, 2|40000000, 1|3f800000
+ MULADD R4.x.12, -R13.x.23, -1|bf800000, 1|3f800000
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94412
Signed-off-by: Xavier Bouchoux <xavi...@gmail.com>
Cc: "11.0 11.1 11.2" <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Glenn Kennard <glenn.kenn...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit fce0b55ccbc33d320b9734a53c2a9f7886450c73)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=98380e02d526419d21dd7b48de3e3fcf7256c8db
Author: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Date: Mon Mar 21 13:15:44 2016 +0100
nvc0: make sure to delete samplers used by compute shaders
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Reviewed-by: Ilia Mirkin <imir...@alum.mit.edu>
Cc: "11.1 11.2" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 9efd8b590f716bb7766ae6816bc080e7ef60a010)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7ce73f2608623c24cd36885df9ce92aa89706680
Author: Nicolai Hähnle <nicolai.haeh...@amd.com>
Date: Fri Mar 18 17:16:39 2016 -0500
st/mesa: use the texture view's format for render-to-texture
Aside from the bug below, it fixes a simplistic test I've written locally,
and I see no regression in Piglit for radeonsi.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94595
Cc: "11.0 11.1 11.2" <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Ilia Mirkin <imir...@alum.mit.edu>
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
(cherry picked from commit a8b315b8271e867db30650dedb52e53d8dd9667c)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3b6bda665a5a890f2c98e19d2939d7de92b8cb4c
Author: Nishanth Peethambaran <nishanth.peethamba...@amd.com>
Date: Fri Mar 11 01:23:00 2016 -0500
st/omx/dec: Correct the timestamping
Attach the timestamp to the dpb buffer and use that timestamp
while pushing buffer from dpb list to the omx client.
Reviewed-by: Christian König <christian.koe...@amd.com>
Signed-off-by: Nishanth Peethambaran <nishanth.peethamba...@amd.com>
Cc: "11.1 11.2" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit eeb117a09d6c0eb2b4fa94d55e8015c8aa982727)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c1763ec83cb502e4124365efa09d7f5272456891
Author: Nishanth Peethambaran <nishanth.peethamba...@amd.com>
Date: Tue Mar 15 01:56:18 2016 -0400
st/omx: Remove trailing spaces
Reviewed-by: Christian König <christian.koe...@amd.com>
Signed-off-by: Nishanth Peethambaran <nishanth.peethamba...@amd.com>
Cc: "11.1 11.2" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 46de6bbb775602ab237d0054e5351b0fc90d942b)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b4045c43ae7781aa2004b72353b98d09008f2d62
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Sun Mar 20 13:43:43 2016 -0400
nv50/ir: fix indirect texturing for non-array textures on nvc0
If a layer parameter is provided, we want to flip it to position 0 (and
combine it with any indirect params). However if the target is not an
array, there is no layer, so we have to shift all of the arguments down
by one to make room for it.
This fixes situations where there were non-coordinate parameters, such
as bias, lod, depth compare, explicit derivatives. Instead of adding a
new parameter at the front for the indirect reference, we would swap one
of those in its place.
Fixes
dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.uniform.compute.*shadow
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Reported-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Tested-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Cc: "11.1 11.2" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 7d98bfedd73d632041d27ff12ccf7c7be74a2ddd)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9bcedb95535299f05e5a97bea8b16494c1f03825
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Sat Mar 19 21:25:36 2016 -0400
st/mesa: only minify depth for 3d targets
We make sure that that image depth matches the level's depth before
copying it into place. However we should only be minifying the first
level's depth for 3d textures - array textures have the same depth for
all levels.
This fixes tests such as
dEQP-GLES3.functional.texture.specification.texsubimage3d_depth.* and I
suspect account for a number of other odd situations I've run into where
level > 0 of array textures was messed up.
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Reviewed-by: Dave Airlie <airl...@redhat.com>
Cc: "11.1 11.2" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit adb40a739943d62508b9c79cbd85e3c67ee3b43b)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4b83793283098466481e0f133f058396f2df5254
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Sat Mar 19 11:58:25 2016 -0400
nv50/ir: normalize cube coordinates after derivatives have been computed
In "manual" derivative mode (always used on nv50 and sometimes on nvc0
but always for cube), the idea is that using the quadop instruction, we
set up the "other" quads to have values such that the derivatives work
out, and then run the texture instruction as if nothing were strange. It
pulls values from the other lanes, and does its magic.
However cube coordinates have to be normalized - one of the 3 coords has
to be 1, to determine which is the major axis, to say which face is
being sampled. We were normalizing the coordinates first, and then
adding the derivatives. This is wrong for two reasons:
- the coordinates got normalized by a scaling factor but the
derivatives didn't
- the result of the addition didn't end up normalized
To resolve this, we flip the logic around to normalize *after* the
per-lane coordinates are set up.
This fixes a bunch of textureGrad cube dEQP tests.
NOTE: nv50 cube arrays with explicit derivatives are still broken, to be
resolved at a later date.
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Cc: "11.1 11.2" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 6eeb284e4f74a2fe5ae6cba90f97f219935e24df)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b0ff22cce6423060cd9135899d3c1302ad6f7f92
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Sat Mar 19 11:46:11 2016 -0400
nv50/ir: force-enable derivatives on TXD ops
This matters especially in vertex shaders, where derivatives are
disabled by default. This fixes textureGrad in vertex shaders on nv50.
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Cc: "11.1 11.2" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit d2445b00837c9123b59a1ac743c136546f334504)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=fa6debe633de90a1f02285aac65b37282a576deb
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Sat Mar 19 11:43:37 2016 -0400
nv50: reset TFB bufctx when we no longer hold a reference to the buffers
This fix is analogous to commit ff085d014.
This fixes some use-after-free situations in dEQP when an xfb state is
removed, and then a clear is triggered, which only does a partial
validation. It would attempt to read the no-longer-valid buffers,
resulting in crashes.
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Cc: "11.1 11.2" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit d1b85dbffa0eec2b44bb2a9f339a2617a39730da)
[Emil Velikov: attribute for the introduction of _3d in various names]
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=db8df3ac13fa4d4b09d7cddb68ac9df16c472a20
Author: Kenneth Graunke <kenn...@whitecape.org>
Date: Mon Mar 14 14:22:39 2016 -0700
i965: Fix gl_TessLevelOuter[] for isolines.
Thanks to James Legg for finding this!
From the ARB_tessellation_shader spec:
"The number of isolines generated is derived from the first outer
tessellation level; the number of segments in each isoline is
derived from the second outer tessellation level."
According to the PRM, "TF.LineDensity determines # lines" while
"TF.LineDetail determines # segments". Line Density is stored at
DWord 6, while Line Detail is at DWord 7. So, they're not reversed
like they are for triangles and quads.
Fixes Piglit's spec/arb_tessellation_shader/execution/isoline,
and about 24 dEQP isoline tests (with GL_EXT_tessellation_shader
hacked on - it's not normally enabled).
Cc: mesa-sta...@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94524
Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.jus...@intel.com>
(cherry picked from commit 5b2d8c2273c6f48e764a1386240ec674cb4aa4ad)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=06c15635efb4edf05961687543d0d8431e73510d
Author: Kenneth Graunke <kenn...@whitecape.org>
Date: Wed Feb 17 00:37:04 2016 -0800
i965: Push most TES inputs in vec4 mode.
(This is commit 4a1c8a3037cd29938b2a6e2c680c341e9903cfbe for vec4 mode.)
Using the push model for inputs is much more efficient than pulling
inputs - the hardware can simply copy a large chunk into URB registers
at thread creation time, rather than having the thread send messages to
request data from the L3 cache. Unfortunately, it's possible to have
more TES inputs than fit in registers, so we have to fall back to the
pull model in some cases.
However, it turns out that most tessellation evaluation shaders are
fairly simple, and don't use many inputs. An arbitrary cut-off of
24 vec4 slots (12 registers) should suffice. (I chose this instead of
the 32 vec4 slots used in the scalar backend to avoid regressing a few
Piglit tests due to the vec4 register allocator being too stupid to
figure out what to do. We probably ought to fix that, but it's a
separate issue.)
Improves performance in GPUTest's tessmark_x64 microbenchmark by
41.5394% +/- 0.288519% (n = 115) at 1024x768 on my Clevo W740SU
(with Iris Pro 5200).
Improves performance in Synmark's Gl40TerrainFlyTess microbenchmark by
38.3576% +/- 0.759748% (n = 42).
v2: Simplify abs/negate handling, as requested by Matt.
Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Chris Forbes <chr...@ijw.co.nz>
Reviewed-by: Matt Turner <matts...@gmail.com>
(cherry picked from commit 24994ae926629ac8521df3cab4a02eb81de15907)
[Emil Velikov: Required by the next patch]
Nominated-by: Emil Velikov <emil.veli...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=582ae91e3a615afdecbb8c3dc98d1397ebee1cd6
Author: Daniel Czarnowski <daniel.czarnow...@intel.com>
Date: Mon Feb 22 08:00:14 2016 +0200
egl: support EGL_LARGEST_PBUFFER in eglCreatePbufferSurface(...)
Patch provides a default for a set pbuffer surface size when
EGL_LARGEST_PBUFFER is used by the client. MIN2 macro is moved
to egldefines so that it can be shared.
Fixes following Piglit test:
egl-create-largest-pbuffer-surface
From EGL 1.5 spec:
"Use EGL_LARGEST_PBUFFER to get the largest available pbuffer
when the allocation of the pbuffer would otherwise fail."
Currently there exists no API to query largest available pixmap size
using xlib or xcb so right now this seems most straightforward way to
ensure that we fulfill above API and also we don't attempt to allocate
'too big' pixmap which might succeed on server side but not work in
practice when driver starts to use it as a texture.
v2: add more explanation about the change (Emil)
Signed-off-by: Matt Roper <matthew.d.ro...@intel.com>
Cc: "11.0 11.1" <mesa-sta...@lists.freedesktop.org
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
(cherry picked from commit d4714512e4077b8079efe526d7823e19fdb9be37)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=64cd74d3b50f175d20ae2b4ffd85f381cfd88dfb
Author: Marek Olšák <marek.ol...@amd.com>
Date: Tue Mar 15 21:49:54 2016 +0100
radeonsi: fix Hyper-Z hangs on P2 configs
Cc: 11.1 11.2 <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
(cherry picked from commit 4ab2ac334921ae9bbd1791adaf8977fccf744580)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6ac586ad8867cb9d48dfeca595585a0d8e6aab31
Author: Roland Scheidegger <srol...@vmware.com>
Date: Tue Mar 15 16:39:55 2016 +0100
llvmpipe: fix lp_rast_plane alignment on 32bit
Some rasterization code relies (for sse) on the first and third planes
(but not the second for now) being 128bit aligned, and we didn't get that
on 32bit - I mistakenly thought the 64bit number in the struct would get
the thing aligned to 64bit even on 32bit archs.
Stephane Marchesin really figured this out.
Reviewed-by: Jose Fonseca <jfons...@vmware.com>
CC: <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit bb2c5e657b5f4c55bcec49a8d96f352ed4c1e013)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2c592ae450cf3586ea309bab69ada59ec6cd8453
Author: Roland Scheidegger <srol...@vmware.com>
Date: Tue Mar 15 19:40:44 2016 +0100
draw: fix line stippling
The logic was comparing actual ints, not true/false values.
This meant that it was emitting always multiple line segments instead of
just
one even if the stipple test had the same result, which looks inefficient,
and
the segments also overlapped thus breaking line aa as well.
(In practice, with the no-op default line stipple pattern, for a 10-pixel
long line from 0-9 it was emitting 10 segments, with the individual segments
ranging from 0-1, 0-2, 0-3 and so on.)
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=94193
Reviewed-by: Jose Fonseca <jfons...@vmware.com>
CC: <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 12a4f0bed6ff03031587e1eb6d69f18b131f5655)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0cf59903853fbf49a210b6a361c554acf2bbfe7d
Author: Roland Scheidegger <srol...@vmware.com>
Date: Sun Mar 13 19:13:09 2016 +0100
softpipe: fix anisotropic filtering crash
The filt_args->offset wasn't assigned but was always used later leading
to a crash (as far as I can tell, texel offsets don't actually make much
sense with anisotropic filtering, but because there's no explicit setting
if offsets are enabled there the array is always accessed).
This fixes https://bugs.freedesktop.org/show_bug.cgi?id=94481
Reviewed-by: Eduardo Lima Mitev <el...@igalia.com>
CC: <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 9e9d69979c7aff7dac2d670af950f4a50273bcde)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d8dd8f30bde85f86c3a9880df5b31a91b894e7e8
Author: Francisco Jerez <curroje...@riseup.net>
Date: Sun Mar 13 19:15:45 2016 -0700
i965/vec4: Consider removal of no-op MOVs as progress during register
coalesce.
Bug found by the liveness analysis validation pass that will be
introduced in a later commit. The no-op MOV check in
opt_register_coalesce() was removing instructions which makes the
cached liveness analysis calculation inconsistent with the shader IR.
We were failing to set progress to true in that case though, which
means that invalidate_live_intervals() wouldn't necessarily be called
at the end of the function.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Matt Turner <matts...@gmail.com>
(cherry picked from commit 7d7990cf657550be4d038a0424ffdc0ef7fd8faa)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9de08603e70db4a5aac7165ad48668023b73936b
Author: Francisco Jerez <curroje...@riseup.net>
Date: Fri Mar 11 15:27:22 2016 -0800
i965/fs: Add missing analysis invalidation in fixup_3src_null_dest().
Bug found by the liveness analysis validation pass that will be
introduced in a later commit. fixup_3src_null_dest() was allocating
registers which makes the cached liveness analysis calculation
incomplete, so it must be invalidated.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Matt Turner <matts...@gmail.com>
(cherry picked from commit 93be4158aed9accab06e3df2d8c526d3312bfff8)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a0268d6cb5d0a479081c435ccbf73adeb3227393
Author: Francisco Jerez <curroje...@riseup.net>
Date: Fri Mar 11 15:22:56 2016 -0800
i965/fs: Add missing analysis invalidation in opt_sampler_eot().
Bug found by the liveness analysis validation pass that will be
introduced in a later commit. opt_sampler_eot() was allocating
registers and inserting and removing instructions, which makes the
cached liveness analysis calculation inconsistent with the shader IR,
so it must be invalidated.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Matt Turner <matts...@gmail.com>
(cherry picked from commit 6691c03fd39be463e1d222b56e3ec8da9f3b7f24)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ed74d2703406bebcff07dcec4b63b0a35bdf97c4
Author: Hans de Goede <hdego...@redhat.com>
Date: Mon Mar 14 15:01:05 2016 +0100
clover: Fix pipe_grid_info.indirect not being initialized.
After pipe_grid_info.indirect was introduced, clover was not modified
to set it causing it to pass uninitialized memory for it to launch_grid.
This commit fixes this by zero-ing the entire pipe_grid_info struct when
declaring it, to avoid similar problems popping-up in the future.
Cc: "11.2" <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Hans de Goede <hdego...@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
[ Francisco Jerez: Trivial codestyle fix. ]
Reviewed-by: Francisco Jerez <curroje...@riseup.net>
(cherry picked from commit 4d02e91e4938c98bcf9d4e57ab2e5463bb42e836)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=aa422705dc94fa702820bb1f33906ced91c3c2ed
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Fri Mar 11 21:26:31 2016 -0500
nvc0: fix blit triangle size to fully cover FB's > 8192x8192
The idea is that a single triangle will cover the whole area being
drawn, allowing the blit shader to do its work. However the max fb size
is 16384x16384, which means that the triangle we draw needs to be twice
that in order to cover the whole area fully. Increase the size of the
triangle to 32768x32768.
This fixes a number of dEQP tests that were failing because a blit was
involved which would miss some of the resulting texture.
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Cc: "11.1 11.2" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit a651bc027d5ed4150bb5240fc9f46a6ca569f665)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f755b71f45d6ecf7e349c1712098a593eec68a9c
Author: Nicolai Hähnle <nicolai.haeh...@amd.com>
Date: Fri Mar 11 11:07:38 2016 -0500
radeonsi: avoid crash when a sampler state is bound for a buffer texture
Sampler states don't really make sense with buffer textures, but they
can be set anyway, so we need to be defensive here. This bug was lurking
for a while and was finally noticed due to PBO uploads setting sampler
states.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94284
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
Tested-by: Laurent Carlier <lordhea...@gmail.com>
Tested-by: Shawn Starr <shawn.st...@rogers.com>
(cherry picked from commit 28d2a7e67c4e8a9835710e5775cd758aa7e27f47)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c64875ec6893ae761e5fb7148007d3498a784d74
Author: Emil Velikov <emil.l.veli...@gmail.com>
Date: Tue Mar 29 11:13:40 2016 +0100
Revert "meta: Fix the pbo usage in meta for GLES{1,2} contexts"
This reverts commit 017f64745138efd5ec5525a8a80d76dc1610ac14.
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=017f64745138efd5ec5525a8a80d76dc1610ac14
Author: Anuj Phogat <anuj.pho...@gmail.com>
Date: Fri Dec 18 15:33:35 2015 -0800
meta: Fix the pbo usage in meta for GLES{1,2} contexts
OpenGL ES 1.0 doesn't support using GL_STREAM_DRAW and both
ES 1.0 and 2.0 don't support GL_STREAM_READ in glBufferData().
So, handle it correctly by calling the _mesa_meta_begin()
before create_texture_for_pbo().
V2: Remove the changes related to allocate_storage. (Ian)
Cc: <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Anuj Phogat <anuj.pho...@gmail.com>
Reviewed-by: Ian Romanick <ian.d.roman...@intel.com>
(cherry picked from commit 6d4ebbe9e5798edee199671c0a98cbf2c5b042e2)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=adec0763a9c88a8dc080b9b718edc2536eed3f16
Author: Nicolai Hähnle <nicolai.haeh...@amd.com>
Date: Thu Mar 10 21:19:56 2016 -0500
r600g: clear compressed_depthtex/colortex_mask when binding buffer texture
Found by inspection of the source based on a bisected bug report.
This bug has been in the code for a long time, but the more recent PBO
upload
feature exposed it because it leads to more uses of buffer textures.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94388
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
Cc: "11.0 11.1 11.2" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit e502801d9843984233426f1b31e42bf6095d63be)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b290082b45be186c51ef0485f36bfecd17521931
Author: Emil Velikov <emil.l.veli...@gmail.com>
Date: Sat Mar 5 21:25:44 2016 +0000
egl/x11: check the return value of xcb_dri2_get_buffers_reply()
... before using it. The function can return NULL, which we should check
prior to refererencing it in the next function(s).
Cc: Fabian Vogt <fv...@suse.com>
Cc: "11.1 11.2" <mesa-sta...@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93667
Signed-off-by: Emil Velikov <emil.l.veli...@gmail.com>
Reviewed-by: Eduardo Lima Mitev <el...@igalia.com>
(cherry picked from commit b9c5c4af6dbfab28b1f0a78e41bffff1b2e06ce9)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9edda787f55047a82be1481e1fca48498b171198
Author: Tamil velan <tamil-velan.jayaku...@amd.com>
Date: Mon Mar 7 15:17:29 2016 +0530
radeon/uvd: increase max height to 4096 for VI and newer
With this issue 'mpv --hwdec=vdpau --vo=vdpau <stream>' fails
for vdpau decode if the stream height is 4096. Vdpau decode of
height upto 4096 is necessary usecase on amdgpu driver for VI
and newer platforms.
The fix is in driver specific implementation of "Decoder
Query Capabilities" API to return 4096 for VI and newer
platforms. With this fix vdpauinfo reports height support as
4096 and mpv for vdpau decode works fine for 4096 height streams.
Signed-off-by: Tamil velan <tamil-velan.jayaku...@amd.com>
Reviewed-by: Christian König <christian.koe...@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Cc: "11.1 11.2" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 353a4f844f9e845dad93de9c28fa0d484b4b92d3)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d9f03f7fa53b24c464fda36e7a3652a56f1923e3
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sat Feb 20 01:22:08 2016 -0800
i965/hsw: Initialize SLM index in state register
For Haswell, we need to initialize the SLM index in the state
register. This can be copied out of the CS header dword 0.
v2:
* Use UW move to avoid changing upper 16-bits of sr0.1 (mattst88)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94081
Fixes: piglit arb_compute_shader/execution/shared-atomics.shader_test
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Cc: "11.2" <mesa-sta...@lists.freedesktop.org>
Tested-by: Ilia Mirkin <imir...@alum.mit.edu> (v1)
Reviewed-by: Matt Turner <matts...@gmail.com>
(cherry picked from commit a100a57e30010da49c96f84a661cec9c57f9eebe)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=26620402b6297e8cd32fed28e17e51f63bc43683
Author: Jordan Justen <jordan.l.jus...@intel.com>
Date: Sun Feb 21 20:55:09 2016 -0800
i965/fs: Allow spilling for SIMD16 compute shaders
For fragment shaders, we can always use a SIMD8 program. Therefore, if
we detect spilling with a SIMD16 program, then it is better to skip
generating a SIMD16 program to only rely on a SIMD8 program.
Unfortunately, this doesn't work for compute shaders. For a compute
shader, we may be required to use SIMD16 if the local workgroup size
is bigger than a certain size. For example, on gen7, if the local
workgroup size is larger than 512, then a SIMD16 program is required.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93840
Signed-off-by: Jordan Justen <jordan.l.jus...@intel.com>
Cc: "11.2" <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Matt Turner <matts...@gmail.com>
(cherry picked from commit e1d54b1ba5a9d579020fab058bb065866bc35554)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d867628244878a5c31bca2939036c8432ecb0007
Author: Marek Olšák <marek.ol...@amd.com>
Date: Thu Feb 25 23:39:42 2016 +0100
gallium/radeon: don't use temporary buffers for persistent mappings
Cc: 11.1 11.2 <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daen...@amd.com>
(cherry picked from commit 3146014d5f0f68b3c7524257ca095f1b475d25f2)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d760368ee1eeadaa413091a3bca315357146c24
Author: Christian König <christian.koe...@amd.com>
Date: Fri Feb 5 09:25:59 2016 +0100
radeon/uvd: disable MPEG1
The hardware simply doesn't support that correctly.
Signed-off-by: Christian König <christian.koe...@amd.com>
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
Cc: "11.1 11.2" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit e148a3b6e9e5c5cd941b70edb67e82058a8187a5)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=938e6dfdee6ea5f85e324febb6d1c288a3d88588
Author: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Date: Mon Mar 7 18:52:19 2016 +0100
tgsi: fix parsing of shared memory declarations
The SHARED TGSI keyword is only allowed with TGSI_FILE_MEMORY and not
with TGSI_FILE_BUFFER. I have found this by using the nouveau_compiler
from command line.
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Reviewed-by: Ilia Mirkin <imir...@alum.mit.edu>
Cc: "11.2" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 7f8565f0b2bf54a8106ae9080386bb186609713d)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=41dbfcd1cd67dd043f6815c6ddf2eeddd815872e
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Sun Mar 6 12:19:04 2016 -0500
glsl: avoid stack smashing when there are too many attributes
This fixes a crash in
dEQP-GLES3.functional.transform_feedback.array_element.separate.points.lowp_mat3x2
and likely others. The vertex shader has > 16 input variables (without
explicit locations), which causes us to index outside of the to_assign
array.
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Reviewed-by: Timothy Arceri <timothy.arc...@collabora.com>
Cc: "11.1 11.2" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit f6827e20d12ab062440bc809b8f2338b68edac45)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e9d8fa8a81abd01d935d381a59ce87c91a595ea
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Tue Feb 16 01:02:52 2016 -0500
nvc0: reset TFB bufctx when we no longer hold a reference to the buffers
This fixes some use-after-free situations in dEQP when an xfb state is
removed, and then a clear is triggered, which only does a partial
validation. It would attempt to read the no-longer-valid buffers,
resulting in crashes.
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Cc: "11.1 11.2" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit ff085d014ed8ccce230769575e50924561218d98)
[Emil Velikov: s/NVC0_BIND_3D_TFB/NVC0_BIND_TFB/]
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
Conflicts:
src/gallium/drivers/nouveau/nvc0/nvc0_shader_state.c
src/gallium/drivers/nouveau/nvc0/nvc0_state.c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=580cab2d9958280227437c0b7209caf848582667
Author: Ilia Mirkin <imir...@alum.mit.edu>
Date: Thu Mar 3 21:00:06 2016 -0500
swrast: fix GL_ANY_SAMPLES_PASSED values in Result
Since commit 922be4eab, the expectation is that the query result
contains the correct value. Unfortunately swrast does not distinguish
between GL_SAMPLES_PASSED and GL_ANY_SAMPLES_PASSED. As a result, we
must fix up the query result in a post-draw fixup.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94274
Signed-off-by: Ilia Mirkin <imir...@alum.mit.edu>
Tested-by: Vinson Lee <v...@freedesktop.org>
Reviewed-by: Brian Paul <bri...@vmware.com>
Cc: "11.2" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit dcbf8377befde50fe4d75738e2af5813e06e8f04)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9a5bcf1571d1b93d40ae6ad06a5ea4e7bf780c4a
Author: Kenneth Graunke <kenn...@whitecape.org>
Date: Thu Mar 3 11:13:29 2016 -0800
i965: Only magnify depth for 3D textures, not array textures.
When BaseLevel > 0, we magnify the dimensions to fill out the size of
miplevels [0..BaseLevel). In particular, this was magnifying depth,
thinking that the depth doubles at each level. This is perfectly
reasonable for 3D textures, but dead wrong for array textures.
Changing the depth != 1 condition to a target == GL_TEXTURE_3D check
should make this only happen in the appropriate cases.
Fixes about 32 dEQP tests:
- dEQP-GLES31.functional.texture.gather.*.level_{1,2}
Signed-off-by: Kenneth Graunke <kenn...@whitecape.org>
Reviewed-by: Matt Turner <matts...@gmail.com>
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit 4ba7ad6cc13b087e5e95073ab2e24de591d8b5a5)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c693ddf731fa6aed3863ecf70c0f483196d7a931
Author: Thomas Hellstrom <thellst...@vmware.com>
Date: Thu Feb 25 11:02:03 2016 +0100
winsys/svga: Increase the fence timeout
If running with a software renderer backend, the timeout may be
insufficient, and we don't want to release busy buffers too early.
In practice, SVGA gpu lockups are extremely rare.
Signed-off-by: Thomas Hellstrom <thellst...@vmware.com>
Reviewed-by: Brian Paul <bri...@vmware.com>
Cc: "11.0 11.1" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 395c7b8fa17069fe996a63a8bca2bfd0fe3f16a0)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7155c2441e5915f99cc8df1cdf5fffa9c9117b5a
Author: Thomas Hellstrom <thellst...@vmware.com>
Date: Thu Feb 25 11:02:02 2016 +0100
winsys/svga: Fix an uninitialized return value
Reported-by: Brian Paul <bri...@vmware.com>
Signed-off-by: Thomas Hellstrom <thellst...@vmware.com>
Reviwed-by: Brian Paul <bri...@vmware.com>
Cc: "11.0 11.1" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 24ad7e16cd0fb67c8646e8860cfb382a260a9126)
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