URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5d961e1630c9623b40e1b7ed5756b6f1e8f46531
Author: Emil Velikov <emil.veli...@collabora.com>
Date: Fri Feb 9 03:43:57 2018 +0000
cherry-ignore: add a few more meson fixes
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1bf16e4fbcc861814cc95865ba59e1c025bb7278
Author: Roland Scheidegger <srol...@vmware.com>
Date: Tue Jan 30 05:48:27 2018 +0100
r600: don't do stack workarounds for hemlock
By the looks of it it seems hemlock is treated separately to cypress, but
certainly it won't need the stack workarounds cedar/redwood (and
seemingly every other eg chip except cypress/juniper) need.
(Discovered by accident.)
Acked-by: Alex Deucher <alexander.deuc...@amd.com>
(cherry picked from commit c2f0e0885776f3f0a18b9db08149564d4b98e5b7)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=70604e880876ff6f7216623e196e0d34d1b2fae6
Author: Jon Turney <jon.tur...@dronecode.org.uk>
Date: Tue Jan 16 16:26:57 2018 +0000
glx/apple: locate dispatch table functions to wrap by name
Avoid reaching into the dispatch table internals (and thus having to deal
with the complexities of remap etc.) by identifying functions to wrap by
name.
See:
https://lists.freedesktop.org/archives/mesa-dev/2015-June/086721.html et
seq.
https://bugs.freedesktop.org/show_bug.cgi?id=90311
Signed-off-by: Jon Turney <jon.tur...@dronecode.org.uk>
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
(cherry picked from commit d3540b405b975450b9c2f9d8eb273be062cbf73a)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=15beac3a010176b384f3b0bd70a8ee2ca3ccc416
Author: Jon Turney <jon.tur...@dronecode.org.uk>
Date: Sat Dec 2 17:05:43 2017 +0000
glx/apple: include util/debug.h for env_var_as_boolean prototype
mesa/src/glx/glxcmds.c:1295:21: error: implicit declaration of function
'env_var_as_boolean' is invalid in C99 [-Werror,-Wimplicit-function-declaration]
mesa/src/glx/apple/apple_visual.c:85:28: error: implicit declaration of
function 'env_var_as_boolean' is invalid in C99
[-Werror,-Wimplicit-function-declaration]
Signed-off-by: Jon Turney <jon.tur...@dronecode.org.uk>
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
(cherry picked from commit b37b7b42dcc33d636c3db0558d032d7d95664c56)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e55ca6768ff7918dfc0ebd8dd5ef680d2e155c73
Author: Jon Turney <jon.tur...@dronecode.org.uk>
Date: Tue Jan 16 23:27:43 2018 +0000
configure: Default to gbm=no on osx
Signed-off-by: Jon Turney <jon.tur...@dronecode.org.uk>
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
(cherry picked from commit 7ad7a07c88b1b1c697132e8f990c0d9530fdf827)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9f6e05d11f39012fb1fd5953e8324fac6d7951b0
Author: Igor Gnatenko <ignate...@redhat.com>
Date: Mon Jan 1 22:49:00 2018 +0100
link mesautil with pthreads
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function
`u_thread_setname':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:66:
undefined reference to `pthread_setname_np'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function
`thrd_join':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../include/c11/threads_posix.h:336:
undefined reference to `pthread_join'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function
`u_thread_create':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:48:
undefined reference to `pthread_sigmask'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function
`thrd_create':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../include/c11/threads_posix.h:296:
undefined reference to `pthread_create'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function
`u_thread_create':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:50:
undefined reference to `pthread_sigmask'
/builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:50:
undefined reference to `pthread_sigmask'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function
`call_once':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../include/c11/threads_posix.h:96:
undefined reference to `pthread_once'
../../src/util/.libs/libmesautil.a(libmesautil_la-u_queue.o): In function
`u_thread_get_time_nano':
/builddir/build/BUILD/mesa-17.3.1/src/util/../../src/util/u_thread.h:84:
undefined reference to `pthread_getcpuclockid'
collect2: error: ld returned 1 exit status
Reviewed-by: Adam Jackson <a...@redhat.com>
Signed-off-by: Igor Gnatenko <ignate...@redhat.com>
(cherry picked from commit 23ce168048698eeea3df6bb8c9de5be3ca4784cd)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104818
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5f862311e79afb5beab6d2af3b5c6a48bdde8221
Author: Kenneth Graunke <kenn...@whitecape.org>
Date: Wed Jan 31 07:03:17 2018 -0800
i965: Bump official kernel requirement to Linux v3.9.
In commit 3f353342a6b6744773c26ed66b12afed42bd57af (present in 17.3.0)
we started unconditionally using I915_EXEC_NO_RELOC, which was
introduced in Linux v3.9. ChromeOS kernel 3.8 has backported this,
so it should work too.
Running on older kernels would likely result in every single batch
being rejected by the kernel, which is pretty catastrophic. Yet, it
appears that nobody noticed. So, let's just bump the official
requirement and move forward ever so slowly.
Fixes: 3f353342a6b ("i965: Use I915_EXEC_NO_RELOC")
Reviewed-by: Chris Wilson <ch...@chris-wilson.co.uk>
Acked-by: Emil Velikov <emil.veli...@collabora.com>
(cherry picked from commit c3cd2aac279908a2de755d9454f293761d7b8d5a)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=833808f01c37685bf9c48800c93fa18543860ac2
Author: Andres Gomez <ago...@igalia.com>
Date: Mon Jan 29 18:25:30 2018 +0200
i965: perform 2 uploads with dual slot *64*PASSTHRU formats on gen<8
The emission of vertex attributes corresponding to dvec3 and dvec4
vertex shader input variables was not correct when the <size> passed
to the VertexAttribL* commands was <= 2.
In 61a8a55f557 ("i965/gen8: Fix vertex attrib upload for dvec3/4
shader inputs"), for gen8+ we needed to determine if the attrib was
dual slot to emit 128 or 256-bit, independently of the VAO size.
Similarly, for gen < 8 we also need to determine whether the attrib is
dual slot to force the emission of 256-bits through 2 uploads.
Additionally, we make use of the ISL_FORMAT_R32_FLOAT format in this
second upload to fill these unspecified components with zeros, as we
also do for gen8+.
Fixes the following test on Haswell:
KHR-GL46.vertex_attrib_binding.basic-inputL-case1
v2: Added more inline comments to explain why we are using
ISL_FORMAT_R32_FLOAT and its consequences, as requested by
Alejandro and Antía.
Fixes: 75968a668e4 ("i965/gen7: expose OpenGL 4.2 on Haswell when
supported")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103006
Cc: Alejandro Piñeiro <apinhe...@igalia.com>
Cc: Juan A. Suarez Romero <jasua...@igalia.com>
Cc: Antia Puentes <apuen...@igalia.com>
Cc: Rafael Antognolli <rafael.antogno...@intel.com>
Cc: Kenneth Graunke <kenn...@whitecape.org>
Signed-off-by: Andres Gomez <ago...@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinhe...@igalia.com>
Reviewed-by: Antia Puentes <apuen...@igalia.com>
Reviewed-by: Rafael Antognolli <rafael.antogno...@intel.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
(cherry picked from commit 5a7aba2e0a7fb3414a94d04d5970a2ed10c1f63e)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=790cc8abe520c039f05873a05fe8e6c6d8a622be
Author: Michel Dänzer <michel.daen...@amd.com>
Date: Fri Jan 26 18:32:32 2018 +0100
winsys/radeon: Compute is_displayable in surf_drm_to_winsys
It was always 0, breaking (at least) DRI3 with Xwayland.
Bugzilla: https://bugs.freedesktop.org/104306
Fixes: 5f2073be3282 ("ac/surface: add ac_surface::is_displayable")
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
(cherry picked from commit 1cf1bf32eff5ffca0b928c0884b0e792207b61b7)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=69beac3f38566aea5e486a8228911ae4e05bb8d7
Author: Matthew Nicholls <mnicho...@feralinteractive.com>
Date: Mon Jan 29 16:26:18 2018 +0000
radv: remove predication on cache flushes
This can lead to a situation where cache flushes could get conditionally
disabled while still clearing the flush_bits, and thus flushes due to
application pipeline barriers may never get executed.
Fixes: a6c2001ace (radv: add support for cmd predication.)
Signed-off-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit ef272b161e05e8216f2d1f4df5023f3aed0ae4fa)
[Emil Velikov: trivial conflicts]
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
Conflicts:
src/amd/vulkan/radv_cmd_buffer.c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=da327c6ce6645f2e7057ce5a5c6626f6ca83d37f
Author: Dave Airlie <airl...@redhat.com>
Date: Tue Nov 14 06:52:06 2017 +1000
virgl: also remove dimension on indirect.
This fixes some dEQP tests that generated bad shaders.
Fixes: b6f6ead19 (virgl: drop const dimensions on first block.)
Reviewed-by: Gurchetan Singh <gurchetansi...@chromium.org>
Tested-by: Gurchetan Singh <gurchetansi...@chromium.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit 49c61d8b841538e09b8c2b2d2f409147fd7b549a)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=64ab67602be30caf654cfb1ac62bcf4d5083b4e9
Author: Dave Airlie <airl...@redhat.com>
Date: Mon Jan 29 04:15:09 2018 +0000
radv/gfx9: fix block compression texture views. (v2)
This ports a fix from amdvlk, to fix the sizing for mip levels
when block compressed images are viewed using uncompressed views.
My original fix didn't power the clamping, but it looks like
the clamping is required to stop the sizing going too large.
Fixes:
dEQP-VK.image.texel_view_compatible.graphic.extended*bc*
Doesn't crash DOW3 anymore.
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Fixes: e38685cc62e 'Revert "radv: disable support for VEGA for now."'
Signed-off-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit f6cc15dccd54ff70be987457af790cac1c8fe5bb)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e27f066126cc153aa327d281491be6356c86fa35
Author: Emil Velikov <emil.veli...@collabora.com>
Date: Fri Feb 2 18:08:00 2018 +0000
cherry-ignore: add meson fix
Meson is disabled in branch.
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d2258c553851256c7dcf077c19a24c38c97b2d4b
Author: Maxin B. John <maxin.j...@intel.com>
Date: Thu Jan 18 13:33:37 2018 +0200
anv_icd.py: improve reproducible builds
Sort the output to ensure build reproducibility
Signed-off-by: Maxin B. John <maxin.j...@intel.com>
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
Fixes: 0ab04ba979b ("anv: Use python to generate ICD json files")
Reviewed-by: Dylan Baker <dy...@pnwbakers.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
(cherry picked from commit 8116b9170bc36bb15512f97a7680ad97bddd56a8)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ef9c58f4bc423b59a49e2a82341efaab217bdbc
Author: Dave Airlie <airl...@redhat.com>
Date: Thu Jan 25 09:29:55 2018 +1000
radv: don't enable tc compat for d32s8 + 4/8 samples (v1.1)
This seems to be broken, at least the cts tests fail.
This fixes:
dEQP-VK.renderpass.suballocation.multisample.d32_sfloat_s8_uint.samples_4
dEQP-VK.renderpass.suballocation.multisample.d32_sfloat_s8_uint.samples_8
2 samples seems to pass fine, amdvlk doesn't appear to enable TC for
possibly some other reasons here.
This is most likely a hack.
v1.1: add a bit of explaination text. (Samuel)
Fixes: ad3d98da9 (radv: enable tc compatible htile for d32s8 also.)
Signed-off-by: Dave Airlie <airl...@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
(cherry picked from commit f4c534ef68a479055190f8ec8d551be0f56ef361)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=47542b1f99da76e9f2ddabcac6383b09d0fbdd93
Author: Emil Velikov <emil.veli...@collabora.com>
Date: Wed Dec 20 17:34:55 2017 +0000
configure.ac: correct driglx-direct help text
The default was toggled a while back, but the text wasn't updated.
Fixes: bd526ec9e1b ("configure: Always default to
--enable-driglx-direct")
Cc: Jon TURNEY <jon.tur...@dronecode.org.uk>
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
Reviewed-by: Daniel Stone <dani...@collabora.com>
(cherry picked from commit 6aeef5464497a2dfd2eb63c7e4aa3349c7794eae)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=caad5571fb390115d0666f18c7fa1c3bf55f0789
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Wed Jan 31 17:31:39 2018 -0800
i965: Call prepare_external after implicit window-system MSAA resolves
This fixes some rendering corruption in a couple of Android apps that
use window-system MSAA.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104741
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Tapani Pälli <tapani.pa...@intel.com>
(cherry picked from commit 2f7205be47bbb730cdfa0a037224b9ebd5224fd1)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d3a990c7fdc84e3f91264c62d568df9982b8502
Author: Emil Velikov <emil.veli...@collabora.com>
Date: Mon Feb 5 19:04:56 2018 +0000
cherry-ignore: radv: Don't expose VK_KHX_multiview on android.
stable: The KHX extension is disabled all together in the stable
branches.
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b9e16d182a7ce45c4028c440807448a209b08b0
Author: Emil Velikov <emil.veli...@collabora.com>
Date: Mon Feb 5 19:00:48 2018 +0000
radv: Stop advertising VK_KHX_multiview
We don't want to advertise experimental extensions in actual releases.
However, there's no harm in leaving the code lying around in the tree.
[Emil Velikov: port from equivalent ANV commit]
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=87ffdbae1cdd7975047abdcfef740a75bfdbffd5
Author: Jason Ekstrand <ja...@jlekstrand.net>
Date: Mon Jul 31 11:27:23 2017 -0700
anv: Stop advertising VK_KHX_multiview
We don't want to advertise experimental extensions in actual releases.
However, there's no harm in leaving the code lying around in the tree.
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
Conflicts:
src/intel/vulkan/anv_device.c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ac087eb40daa8323bce1c16175ac34642dc9c50a
Author: Lucas Stach <l.st...@pengutronix.de>
Date: Tue Jan 30 15:11:35 2018 +0100
renderonly: fix dumb BO allocation for non 32bpp formats
Take into account the resource format, instead of applying a hardcoded
32bpp. This not only over-allocates 16bpp formats, but also results in
a wrong stride being filled into the handle.
Fixes: 848b49b288f ("gallium: add renderonly library")
CC: <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Lucas Stach <l.st...@pengutronix.de>
Reviewed-by: Philipp Zabel <p.za...@pengutronix.de>
Reviewed-by: Daniel Stone <dani...@collabora.com>
(cherry picked from commit 0c71a19fe4368beaaf7ac676403b3079ad658890)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a7e3a152e55b1ff9c56977638eb18d36aed30f6
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Jan 26 16:22:27 2018 -0800
anv/cmd_buffer: Re-emit the pipeline at every subpass
If we ever hit this edge-case, it can theoretically cause problem for
CNL because we could end up changing render targets without re-emitting
3DSTATE_MULTISAMPLE which is part of the pipeline. Just get rid of the
edge case.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <ito...@igalia.com>
(cherry picked from commit 97938dac36e2875001ba24a7968e4cd8e2271321)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b75f12a2f2402af6346ff51f24ff52acaa9f9187
Author: Dave Airlie <airl...@redhat.com>
Date: Tue Jan 30 16:38:51 2018 +1000
r600/sb: insert the else clause when we might depart from a loop
If there is a break inside the else clause and this means we
are breaking from a loop, the loop finalise will want to insert
the LOOP_BREAK/CONTINUE instruction, however if we don't emit
the else there is no where for these to end up, so they will end
up in the wrong place.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101442
Tested-By: Gert Wollny <gw.foss...@gmail.com>
Cc: <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Roland Scheidegger <srol...@vmware.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit 8d633f067b8a3d74e3f39faea0773a229d4b93b3)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9161ac5c6da2030fa7b0c6020bcd0cf54583a426
Author: Emil Velikov <emil.veli...@collabora.com>
Date: Fri Feb 2 15:26:35 2018 +0000
cherry-ignore: nir: mark unused space in packed_tex_data
stable: The commit covers nir serialise, which did not land in branch
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=56427ff05ebe7bd105b2bfa47b15a55e262c6c46
Author: Emil Velikov <emil.veli...@collabora.com>
Date: Fri Feb 2 15:20:01 2018 +0000
cherry-ignore: add i965 shader cache fixes
The feature is available in the 18.0 branch
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e1ab1de6b684f009fb7ee4a8fac60f667ca6bd37
Author: Emil Velikov <emil.veli...@collabora.com>
Date: Fri Feb 2 15:18:06 2018 +0000
cherry-ignore: add r600/amdgpu 18.0 nominations
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eaa9449c26f84bad5d5cad667ee47ff5af746045
Author: Emil Velikov <emil.veli...@collabora.com>
Date: Fri Feb 2 15:16:28 2018 +0000
cherry-ignore: add gen10 fixes
Initial gen10 support landed in the 18.0 series.
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=62e0a8893b5007adaf079d5ffecb39e11685e8d6
Author: Eleni Maria Stea <es...@igalia.com>
Date: Thu Jan 25 13:09:00 2018 -0700
mesa: Fix function pointers initialization in status tracker
We assigned the function that gets the device uuid to the GetDriverUuid
function pointer and the function that gets the driver uuid to the
GetDeviceUuid function pointer inside the state tracker. Exchanged the
pointers.
cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Brian Paul <bri...@vmware.com>
(cherry picked from commit 8096b558a7d769b20b1545b83399d67b8a3df94a)
[Emil Velikov: trivial conflicts]
Signed-off-by: Emil Velikov <emil.veli...@collaboral.com>
Signed-off-by: Emil Velikov <emil.l.veli...@gmail.com>
Conflicts:
src/mesa/state_tracker/st_context.c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7e7b4c2c6880717916b5e1e6ca26edc1fe390211
Author: Emil Velikov <emil.veli...@collabora.com>
Date: Fri Feb 2 14:41:01 2018 +0000
cherry-ignore: ac/nir: set amdgpu.uniform and invariant.load for UBOs
stable: The commit requires earlier commit w41c36c45 which did not land
in branch
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ae5e793fd7bb408fa6924924df06662010273a18
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Wed Jan 17 17:10:34 2018 -0800
anv/pipeline: Don't look at blend state unless we have an attachment
Without this, we may end up dereferencing blend before we check for
binding->index != UINT32_MAX. However, Vulkan allows the blend state to
be NULL so long as you don't have any color attachments. This fixes a
segfault when running The Talos Principal.
Fixes: 12f4e00b69e724a23504b7bd3958fb75dc462950
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Alex Smith <asm...@feralinteractive.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwer...@intel.com>
(cherry picked from commit c8949e24984266cca3593291c30ea199baef5358)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0bc9182f89f166f141e0f847d42c9fc557cc3aea
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Tue Oct 17 18:59:26 2017 -0700
intel/fs: Use the original destination region for int MUL lowering
Some hardware (CHV, BXT) have special restrictions on register regions
when doing integer multiplication. We want to respect those when we
lower to DxW multiplication.
Reviewed-by: Iago Toral Quiroga <ito...@igalia.com>
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit 18fde36ced4279f2577097a1a7d31b55f2f5f141)
Squashed with:
i965/fs: Reset the register file to VGRF in lower_integer_multiplication
18fde36ced4279f2577097a1a7d31b55f2f5f141 changed the way temporary
registers were allocated in lower_integer_multiplication so that we
allocate regs_written(inst) space and keep the stride of the original
destination register. This was to ensure that any MUL which originally
followed the CHV/BXT integer multiply regioning restrictions would
continue to follow those restrictions even after lowering. This works
fine except that I forgot to reset the register file to VGRF so, even
though they were assigned a number from alloc.allocate(), they had the
wrong register file. This caused some GLES 3.0 CTS tests to start
failing on Sandy Bridge due to attempted reads from the MRF:
ES3-CTS.functional.shaders.precision.int.highp_mul_fragment.snbm64
ES3-CTS.functional.shaders.precision.int.mediump_mul_fragment.snbm64
ES3-CTS.functional.shaders.precision.int.lowp_mul_fragment.snbm64
ES3-CTS.functional.shaders.precision.uint.highp_mul_fragment.snbm64
ES3-CTS.functional.shaders.precision.uint.mediump_mul_fragment.snbm64
ES3-CTS.functional.shaders.precision.uint.lowp_mul_fragment.snbm64
This commit remedies this problem by, instead of copying inst->dst and
overwriting nr, just make a new register and set the region to match
inst->dst.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103626
Fixes: 18fde36ced4279f2577097a1a7d31b55f2f5f141
Cc: "17.3" <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Matt Turner <matts...@gmail.com>
(cherry picked from commit db682b8f0eafd3b9d58e736e9e2f520943a89942)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a094314340387ef2463ed8b4ddc9317bc539832b
Author: Emil Velikov <emil.l.veli...@gmail.com>
Date: Fri Feb 2 14:33:50 2018 +0000
Revert "cherry-ignore: intel/fs: Use the original destination region for
int MUL lowering"
This reverts commit 7295b97d61104e971aa925c2370e3f3cbb23a408.
Originally the nomination was causing a regression. With that addressed,
we can pick it up alongside it's fix.
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=557f2cd46c0284247911ed742edec84785b52202
Author: Chuck Atkins <chuck.atk...@kitware.com>
Date: Tue Jan 23 08:52:46 2018 -0500
configure.ac: add missing llvm dependencies to .pc files
v2: Only add as dependencies for gallium-osmesa and gallium-xlib
CC: <mesa-sta...@lists.freedesktop.org>
Signed-of-by: Chuck Atkins <chuck.atk...@kitware.com>
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
(cherry picked from commit 6ac5e851f1a0b83d84156bc79983fd9527d4c296)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f23257b623c3af9d8e5c8338dd0bd215ee43eb61
Author: Emil Velikov <emil.veli...@collabora.com>
Date: Fri Feb 2 14:30:06 2018 +0000
cherry-ignore: swr/rast: support llvm 3.9 type declarations
stable: The commit requires earlier commit 01ab218bbc which did not land
in branch
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a78ff020c6f8ee8e4efaa49d99e9a76299381ca4
Author: Dave Airlie <airl...@redhat.com>
Date: Wed Jan 24 12:53:26 2018 +1000
radv: move spi_baryc_cntl to pipeline
We need to enable the pos float location 2 mode anytime we have
persample not just when forced by the frag shader.
This fixes:
dEQP-VK.pipeline.multisample.min_sample_shading*
Fixes: 58c97a079 (radv: enable location at sample when persample is forced.)
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Signed-off-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit 298554541da220ebdcd9aa9b9055ede2481d5817)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5ef3cadf157ce9b868511cb5c13114eb22ba0b51
Author: Emil Velikov <emil.veli...@collabora.com>
Date: Thu Jan 25 05:02:57 2018 +0000
cherry-ignore: meson: multiple fixes
stable: The commits address the Meson build that is explicitly disabled
in branch
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4987b561b59b040be0b14d7e57d1042eb3b166df
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Wed Jan 24 11:43:55 2018 -0800
i965/surface_state: Drop brw_aux_surface_disabled
The only purpose of this function is to disable aux on texture surfaces
when the corresponding renderbuffer has aux disabled. However, the act
of disabling aux on the renderbuffer will cause it to be resolved and
intel_miptree_texture_aux_usage will already check the resolved status
of a texture and return ISL_AUX_USAGE_NONE for it. Even if we used CCS
for it, that wouldn't really be a problem because the CCS will be in the
pass-through state and so it would effectively be ignored.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
(cherry picked from commit 468ea3cc451f2c71e7d1be528090cb0334d500c2)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=468a2b6525f3b1e950d8b14138ccf62227aab73a
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Mon Jan 22 23:40:48 2018 -0800
i965/miptree: Add an aux_disabled parameter to render_aux_usage
Only one of the callers of intel_miptree_render_aux_usage actually took
brw->draw_aux_buffer_disabled into account. This was causing us to
ignore draw_aux_buffer_disabled for the intel_miptree_prepare_render.
This isn't a problem because the draw_aux_buffer_disabled entry was set
during texture preparation and we already did the resolve at that time.
However, this also meant that the aux_usage we were passing to
brw_cache_flush_for_render and brw_render_cache_add_bo was wrong so our
automatic cache flushing around aux_usage changes wasn't happening.
This was causing GPU hangs in Oxenfree.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104711
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104411
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104383
Fixes: ea0d2e98ecb369ab84e78c84709c0930ea8c293a
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <ito...@igalia.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
(cherry picked from commit d38ec24f531fac0b53c406a09d17427309a3ffca)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0dd5120deddc97467e18b715390e929b50787e63
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Mon Jan 22 23:33:53 2018 -0800
i965/miptree: Take an aux_usage in prepare/finish_render
Both callers of intel_miptree_prepare/finish_render have to call
intel_miptree_render_aux_usage anyway for other reasons. They may as
well pass the result in instead of us calling it again.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Iago Toral Quiroga <ito...@igalia.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
(cherry picked from commit dfe02179055b2504303e23988ab3d446b40de05a)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1d7d13ffc6778c9ba67f8929458e21f9cfd34f6c
Author: Marek Olšák <marek.ol...@amd.com>
Date: Wed Jan 10 13:37:08 2018 +0100
radeonsi: don't ignore pitch for imported textures
Cc: 17.2 17.3 <mesa-sta...@lists.freedesktop.org>
Tested-by: Dieter Nützel <die...@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
(cherry picked from commit 022c5b22fee5d92da67f48601ea80b1c810a829d)
[Emil Velikov: attribute for lack of slice_size_dw]
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
Signed-off-by: Emil Velikov <emil.l.veli...@gmail.com>
Conflicts:
src/gallium/drivers/radeon/r600_texture.c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=36e1b57bade13c0529f989f1c4109b08946f75e1
Author: Boyuan Zhang <boyuan.zh...@amd.com>
Date: Fri Dec 15 11:23:25 2017 -0500
radeon/uvd: add and manage render picture list
Create a list in decoder to store all render picture buffer pointers that
currently being used in reference picture lists.
During get message buffer call, check each pointer in render_pic_list[]
within given pic->ref[] list, remove pointer that no longer being used by
pic->ref[]. Then add current render surface pointer to the render_pic_list[]
and assign the associated index to result.curr_idx.
As a result, result.curr_idx will have the correct index to represent the
current render picture, instead of the previous increamenting values.
Signed-off-by: Boyuan Zhang <boyuan.zh...@amd.com>
Reviewed-by: Christian König <christian.koe...@amd.com>
(cherry picked from commit 2ec48039b8aa1f6a5e16f3f12483b88981d0f5d3)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104745
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
Conflicts:
src/gallium/drivers/radeon/radeon_uvd.c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2b6d2f6a81985e52c3955e68d6c9f0889b6a6e52
Author: Boyuan Zhang <boyuan.zh...@amd.com>
Date: Fri Dec 15 11:17:32 2017 -0500
radeon/vcn: add and manage render picture list
Create a list in decoder to store all render picture buffer pointers that
currently being used in reference picture lists.
During get message buffer call, check each pointer in render_pic_list[]
within given pic->ref[] list, remove pointer that no longer being used by
pic->ref[]. Then add current render surface pointer to the render_pic_list[]
and assign the associated index to result.curr_idx.
As a result, result.curr_idx will have the correct index to represent the
current render picture, instead of the previous increamenting values.
Signed-off-by: Boyuan Zhang <boyuan.zh...@amd.com>
Reviewed-by: Christian König <christian.koe...@amd.com>
(cherry picked from commit f2bfd1cbb7e72945ca192845a1ad28426c7aea89)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104745
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=30a35f8d439c71fce10ea26e87103d03a0e6af4a
Author: Indrajit Das <indrajit-kumar....@amd.com>
Date: Wed Jan 10 15:13:37 2018 +0530
st/va: clear pointers for mpeg2 quantiser matrices
This is to fix VA-API issues with GStreamer and MPEG2.
Since gstreamer does not pass quantiser matrices with each frame, invalid
pointers were being passed to the driver. This patch addresses the same.
Signed-off-by: Indrajit Das <indrajit-kumar....@amd.com>
Reviewed-by: Christian König <christian.koe...@amd.com>
(cherry picked from commit 338638a8afc9f330bacc1cdd7e6392a3ea9d828a)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e46597f2731f9b5623f51393309415bad15b38ca
Author: Indrajit Das <indrajit-kumar....@amd.com>
Date: Wed Jan 10 15:12:44 2018 +0530
radeon/vcn: update quantiser matrices only when requested
Only update them when the pointers are valid.
Signed-off-by: Indrajit Das <indrajit-kumar....@amd.com>
Reviewed-by: Christian König <christian.koe...@amd.com>
(cherry picked from commit f5277e84925b69b0bf01340122684becd45c1f7d)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=08ad68ea1913a238f22373ba962bbdac812da769
Author: Indrajit Das <indrajit-kumar....@amd.com>
Date: Wed Jan 10 15:10:17 2018 +0530
radeon/uvd: update quantiser matrices only when requested
Only upload them when the pointers are valid.
Signed-off-by: Indrajit Das <indrajit-kumar....@amd.com>
Reviewed-by: Christian König <christian.koe...@amd.com>
(cherry picked from commit 38dee62c9a0ced17fb1f25256f9da3b163a16f81)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=339b43b0af8a403b4b925f9e62aa676b699540e1
Author: Indrajit Das <indrajit-kumar....@amd.com>
Date: Fri Jan 5 04:36:18 2018 -0500
st/omx_bellagio: Update default intra matrix per MPEG2 spec
Signed-off-by: Indrajit Das <indrajit-kumar....@amd.com>
Reviewed-by: Christian König <christian.koe...@amd.com>
(cherry picked from commit e05d5b0cf31f3212ba1666a6baaae77bc30433a0)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1bfeb763fb28dc2d662db9addc31f9d951bff41a
Author: Emil Velikov <emil.veli...@collabora.com>
Date: Thu Jan 25 03:04:46 2018 +0000
cherry-ignore: radv: fix sample_mask_in loading. (v3.1)
fixes: The commit requires earlier commit 49d035122ee which did not land
in branch.
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c465067ff8236296a3042ed8aada16dc91fbc782
Author: Emil Velikov <emil.veli...@collabora.com>
Date: Thu Jan 25 03:26:13 2018 +0000
cherry-ignore: anv: add explicit 18.0 only nominations
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b31e232baa75578e2117b236be377d716ef10e4b
Author: Emil Velikov <emil.veli...@collabora.com>
Date: Thu Jan 25 03:22:28 2018 +0000
cherry-ignore: swr: refactor swr_create_screen to allow for proper cleanup
on error
stable: The commit depends on earlier commit a4be2bcee2 which did not
land in branch
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d20d97ec8f52673a8952bfd727b1749372a00049
Author: Emil Velikov <emil.veli...@collabora.com>
Date: Thu Jan 25 03:16:37 2018 +0000
cherry-ignore: i965: Accept CONTEXT_ATTRIB_PRIORITY for brwCreateContext
stable: The commit addresses earlier commit 6d87500fe12 which did not
land in branch
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=eaa3da4189b65d960eddc191eeb0ca70d7ce2bae
Author: Dave Airlie <airl...@redhat.com>
Date: Tue Jan 23 16:07:50 2018 +1000
radv: don't use hw resolves for r16g16 norm formats.
radeonsi has a workaround for this, but it uses a R16A16 format,
which vulkan doesn't have, we could probably come up with a work
around but for now just avoid hw resolves.
Fixes:
dEQP-VK.renderpass.suballocation.multisample.r16g16_*norm*
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Fixes: 2a04f5481d (radv/meta: select resolve paths)
Signed-off-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit c727ea9370adc5362e00208b9f1481764b8ef215)
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
Conflicts:
src/amd/vulkan/radv_meta_resolve.c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c30a6252c2db5586652b93e0d26375d4859a4c50
Author: Dave Airlie <airl...@redhat.com>
Date: Tue Jan 23 14:57:12 2018 +1000
radv: don't use hw resolve for integer image formats
From reading AMDVLK it currently never uses hw resolve paths.
This patch takes from radeonsi which doesn't use hw resolve
for integer formats, and does the same for radv.
This fixes:
dEQP-VK.renderpass.suballocation.multisample*uint tests.
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Fixes: 2a04f5481d (radv/meta: select resolve paths)
Signed-off-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit 4df414bbd2f1a44840c982198f4c8353f242ca15)
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
Conflicts:
src/amd/vulkan/radv_meta_resolve.c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1bd25a4d9912800ecb410f388792790af4781969
Author: Dave Airlie <airl...@redhat.com>
Date: Tue Jan 23 15:48:08 2018 +1000
radv: add fs_key meta format support to resolve passes.
Some of the hw resolve passes need the SPI color format setup
correctly.
This fixes lots of 16-bit and 32-bit format tests in
dEQP-VK.renderpass.suballocation.multisample*
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Fixes: f4e499ec7914 "radv: add initial non-conformant radv vulkan driver"
Signed-off-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit 316d762186f0bfc225b82794fdae520275a448db)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5e889ae22cae111c6b7b99bd72ec2328386bf94e
Author: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Date: Mon Dec 18 19:38:52 2017 +0100
radv: create pipeline layout objects for all meta operations
They are dummy objects but the spec requires layout to not be
NULL, this just makes sure we are creating valid pipeline layout
objects. This will allow us to remove some useless checks.
Signed-off-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
(cherry picked from commit 3595a116489d6f3b2f7fd2aa3eeff6376b82beb2)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=558411c21e09203f9ca774e5fbe1938046e54913
Author: Eric Engestrom <eric.engest...@imgtec.com>
Date: Tue Dec 19 13:41:35 2017 +0000
radeon: remove left over dead code
Fixes: 4e0d99a63588c67a955f "r100: Use shared debug code"
Cc: Pauli Nieminen <suok...@gmail.com>
Signed-off-by: Eric Engestrom <eric.engest...@imgtec.com>
Reviewed-by: Eric Anholt <e...@anholt.net>
(cherry picked from commit eee8dd7c3360ec0daf3d44168b6d1c32c52bf69b)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a79113e2bc4dc78c7e5af8376f76ab475f2fc43
Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date: Wed Jan 17 14:33:39 2018 +0100
ac/nir: Fix vector extraction if source vector has >4 elements.
v2: Add forgotten argument and start offset.
Fixes: 91074bb11bda "radv/ac: Implement Float64 SSBO stores."
Tested-by: Timothy Arceri <tarc...@itsqueeze.com>
Acked-by: Timothy Arceri <tarc...@itsqueeze.com>
(cherry picked from commit 32170d87e3b7bee37234b44ff787ff60fcd3a9aa)
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
Conflicts:
src/amd/common/ac_nir_to_llvm.c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=022cdd4eaa3255c7cc298b218368a1b3868d3c65
Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date: Wed Jan 17 14:23:17 2018 +0100
ac/nir: Use correct 32-bit component writemask for 64-bit SSBO stores.
Fixes: 91074bb11bda "radv/ac: Implement Float64 SSBO stores."
Tested-by: Timothy Arceri <tarc...@itsqueeze.com>
Acked-by: Timothy Arceri <tarc...@itsqueeze.com>
(cherry picked from commit f4211e6f9314b225cdcdc799e0c123b3dceee9eb)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a45a6ed8084a82f2a6d6848fee93a1379c96b7d8
Author: Timothy Arceri <tarc...@itsqueeze.com>
Date: Thu Jan 18 12:01:33 2018 +1100
ac: fix visit_ssa_undef() for doubles
V2: use LLVMIntTypeInContext()
Fixes: f4e499ec7914 "radv: add initial non-conformant radv vulkan driver"
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
(cherry picked from commit 3bccb5dba9415f98f7a3dbb7c43a5eace64b4ec6)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a060dc27b095885a651cf159ac9fcc7b158b6ef3
Author: Dave Airlie <airl...@redhat.com>
Date: Thu Jan 18 02:31:40 2018 +0000
ac/nir: account for view index in the user sgpr allocation.
The view index user sgpr wasn't being accounted for properly,
this refactors out the code to decide if it's required and then
uses that info to account for it.
Fixes: 180c1b924e (ac/nir: Add shader support for multiviews.)
Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit 3153d742078d9842d867e8affddf0b157de762f0)
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
Conflicts:
src/amd/common/ac_nir_to_llvm.c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=78e1165645f28f7345d499d5ac38d471ec8ed18b
Author: Timothy Arceri <tarc...@itsqueeze.com>
Date: Tue Jan 16 17:45:30 2018 +1100
ac: fix buffer overflow bug in 64bit SSBO loads
Fixes: 441ee1e65b04 "radv/ac: Implement Float64 SSBO loads"
Reviewed-by: Marek Olšák <marek.ol...@amd.com>
(cherry picked from commit e2b9296146746635cd631c5212ae56f0cd270820)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ff063689509d4fd8b7a066146463af25a4314b0b
Author: Samuel Thibault <samuel.thiba...@ens-lyon.org>
Date: Mon Jan 15 15:38:25 2018 +0100
glx: fix non-dri build
glXGetDriverConfig parameters do not provide a context to dynamically
check for the presence of the function, so the dispatcher directly calls
glXGetDriverConfig, but in non-dri builds dri_glx.c didn't provide
glXGetDriverConfig.
This change make it just return NULL in that case.
Fixes: 84f764a7591 "glxglvnddispatch: Add missing dispatch for
GetDriverConfig
Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com>
Reviewed-by: Hans de Goede <hdego...@redhat.com>
Reviewed-by: Emil Velikov <emil.veli...@collabora.com>
(cherry picked from commit 47ac11bcf8bd9e4525e0fb4308d0bca87a8900c6)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=ad764e365beb8a119369b97f22225cb95fc7ea8c
Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date: Mon Jan 22 09:01:29 2018 +0100
ac/nir: Use instance_rate_inputs per attribute, not per variable.
This did the wrong thing if we had e.g. an array for which only some
of the attributes use the instance index. Tripped up some new CTS
tests.
CC: <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Reviewed-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit 5a4dc285002e1924dbc8c72d17481a3dbc4c0142)
Conflicts:
src/amd/common/ac_nir_to_llvm.c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=473d665a4d37081d5bcc69cccee41affda4ede50
Author: Jose Fonseca <jfons...@vmware.com>
Date: Mon Jan 22 15:05:22 2018 +0000
svga: Prevent use after free.
Courtesy of clang static analyzer.
I was hunting for potential sources of memory corruption using Mesa with
a GL trace, and happened to find this (unrelated) issue.
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Emil Velikov <emil.l.veli...@gmail.com>
(cherry picked from commit dcbb224c688bfdacb76107a9816647f64088e67e)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=93ffa56658a180bc13387e2fc572bf40f5c61978
Author: Matthew Nicholls <mnicho...@feralinteractive.com>
Date: Fri Jan 19 14:11:48 2018 +0000
radv: restore previous stencil reference after depth-stencil clear
Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Samuel Pitoiset <samuel.pitoi...@gmail.com>
Reviewed-by: Alex Smith <asm...@feralinteractive.com>
(cherry picked from commit 005375717b18b2eb04bdc54a260b096cabab15d2)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=623d843692a416b8496029388b017733e7474090
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Thu Jan 11 17:33:36 2018 -0800
i965: Set tiling on BOs imported with modifiers
We need this to ensure that GTT maps work on buffers we get from Vulkan
on the off chance that someone does a readpixels or something. Soon, we
will be removing GTT maps from i965 entirely and this can be reverted.
None the less, it's needed for stable.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit 50485723523d2948a44570ba110f02f726f86a54)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8ebfa265e2636f61da5d88d48176627d4b040b97
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Thu Jan 18 20:39:50 2018 -0800
i965/bufmgr: Add a create_from_prime_tiled function
This new function is an import and a set tiling in one go.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit b9e7b29705cb17ef7f88d346db823c9b99810249)
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
Conflicts:
src/mesa/drivers/dri/i965/brw_bufmgr.c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9b2ac06cd6a32aeedab94cbcacddf9c783f238a6
Author: Jason Ekstrand <ja...@jlekstrand.net>
Date: Fri Nov 17 16:10:54 2017 -0800
i965/miptree: Use the tiling from the modifier instead of the BO
This fixes a bug where we were taking the tiling from the BO regardless
of what the modifier said. When we got images in from Vulkan where it
doesn't set the tiling on the BO, we would treat them as linear even
though the modifier expressly said to treat it as Y-tiled.
Reviewed-by: Daniel Stone <dani...@collabora.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit ad424b2243023b0299de700fb2d220c2f7849ce6)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=be2a7b6a28f325fb8557af1cbd44c399d93874c5
Author: Jason Ekstrand <ja...@jlekstrand.net>
Date: Fri Nov 17 16:10:53 2017 -0800
i965/miptree: Add an explicit tiling parameter to create_for_bo
Otherwise, create_for_bo will just grab the tiling from the BO which is
not what we want when using modifiers.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit 0465dd13d26451e2a57684d1ca6329dfbdeac9f4)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=17647d08a59f7da710ac945eaad5d2b46d62ec12
Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date: Sun Jan 21 23:39:36 2018 +0100
radv: Don't allow 3d or 1d depth/stencil textures.
addrlib asserts when that happens, and supporting it is not
required so lets not allow this for now.
It also assert on fmask, but we don't have the number of samples here.
CC: <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit 4584c4ef049ac604ebbeab56992d569e4d1f8a46)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=635b9549dc437f31f43b2e23d374c53f5a976371
Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date: Sun Jan 21 22:03:02 2018 +0100
radv: Init variant entry with memset.
This gets memcpy'd and written driectly, and due to alignment, this
resulted in uninitialized gaps. This makes those gaps go away.
CC: <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit 8b98929074f77156d8e1a10bc42b8eda0f9ce4ec)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=43d8d13377065d3774b64ef8aca466cc765cb963
Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date: Sun Jan 21 22:01:49 2018 +0100
radv: Fix bufimage failure deallocation.
The inidividual init parts don't clean up their own stuff on failure.
CC: <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit fb0992e967e7f56604e1f5db8579ae6c2b8d0f2a)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1663b7edf0d3509f96cf3e5bf8e03d75b859ece3
Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date: Sun Jan 21 21:59:26 2018 +0100
radv: Fix fragment resolve init memory allocation failure paths.
CC: <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit 2c802ca66c480a1038e1fe52350e30a27658e78a)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f1c8bc6e85df37f00d247ee3f95a45e1de772246
Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date: Sun Jan 21 21:47:31 2018 +0100
radv: Fix freeing meta state if the device pipeline cache fails to allocate.
CC: <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit c685076ab0706309d7ba2012a7bc4e2c6637d402)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=87d254b818f8d9cc2d03a4661cbf0cb7bebaf5d0
Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date: Sun Jan 21 20:20:50 2018 +0100
radv: Fix memory allocation failure path in compute resolve init.
CC: <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit 71f0315a8861ac20cd9ed36d89eb9db60462931f)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=acca16e3fb9ac360f024680978235ed7fb02ed3e
Author: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Date: Sun Jan 21 20:19:48 2018 +0100
radv: Fix ordering issue in meta memory allocation failure path.
CC: <mesa-sta...@lists.freedesktop.org>
Reviewed-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit d956e0bdf53a9dd51d4a07d3cb58ee16e37a4ace)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cf807eff6592520f0696702d3a463d552efed4d5
Author: Lucas Stach <l.st...@pengutronix.de>
Date: Thu Jan 11 11:29:29 2018 +0100
etnaviv: dirty TS state when framebuffer has changed
When switching between framebuffers with and without TS, the TS state
needs to be flushed to the command stream even if the derived state
isn't changed.
Fixes: 4ee7c2c2843c ("etnaviv: enable TS, but disable autodisable")
Cc: mesa-sta...@lists.freedesktop.org
Signed-off-by: Lucas Stach <l.st...@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmei...@gmail.com>
(cherry picked from commit 29a0ea699a4fcd837d0478ad23b50e3cb0431ee4)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=212a59e2163343b6aee35a7517c64391a632c422
Author: Grazvydas Ignotas <nota...@gmail.com>
Date: Tue Jan 16 00:00:33 2018 +0200
st/vdpau: release held lock in error path
Signed-off-by: Grazvydas Ignotas <nota...@gmail.com>
Reviewed-by: Christian König <christian.koe...@amd.com>
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit e6abc613e2a78c01d1e79e4cd3be79e58d52eac2)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3cd9d65a1b82e9f58e7ef84f9a7195b3ff662e6d
Author: Kenneth Graunke <kenn...@whitecape.org>
Date: Wed Jan 17 14:16:04 2018 -0800
i965: Bind null render targets for shadow sampling + color.
Portal 2 appears to bind RGBA8888_UNORM textures to a sampler2DShadow,
and calls shadow2D() on it. This causes undefined behavior in OpenGL.
Unfortunately, our sampler appears to hang in this scenario, which is
not acceptable. Just give them a null surface instead, which returns
all zeroes.
Fixes GPU hangs in Portal 2 on Kabylake.
Huge thanks to Jason Ekstrand for noticing this crazy behavior while
sifting through crash dumps.
Cc: mesa-sta...@lists.freedesktop.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104487
Reviewed-by: Topi Pohjolainen <topi.pohjolai...@intel.com>
Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net>
(cherry picked from commit 3e18c53e59457f585de217208e1745f2683be0b9)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=14ebd7ecd9796a2e530da2abae61084e5d3239e8
Author: Dave Airlie <airl...@redhat.com>
Date: Wed Jan 10 03:41:57 2018 +0000
r600/sb: fix a bug emitting ar load from a constant.
Some tess shaders were doing MOVA_INT _, c0.x on cayman, and then
hitting an assert in sb_bc_finalize.cpp:translate_kcache.
This makes sure the toplevel kcache tracker gets updated,
and the clause gets fixed up.
Reviewed-by: Roland Scheidegger <srol...@vmware.com>
Cc: <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit 68b976bd91d1a23d2d04f383ab194980b5084970)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=48db8ed8225f895e45d9d0b5c0e1fa7104eae89a
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Sun Dec 17 19:42:09 2017 -0800
i965/miptree: Refactor CCS_E and CCS_D cases in render_aux_usage
This commit unifies the CCS_E and CCS_D cases. This should fix a couple
of subtle issues. One is that when you use INTEL_DEBUG=norbc to disable
CCS_E, we don't get the sRGB blending workaround. By unifying the code,
we give CCS_D that workaround as well.
The second issue fixed by this refactor is that the blending workaround
was appears to be enabled on all gens but really only applies on gen9.
Due to a happy accident in the way code was laid out, it was only
getting enabled on gen9: gen8 and earlier don't support non-zero-one
clear colors, and gen10 supports sRGB for CCS_E so it got caught in the
format_ccs_e_compat_with_miptree case. This refactor moves it above the
format_ccs_e_compat_with_miptree case so it's an explicit early exit and
makes it explicitly only on gen9.
Reviewed-by: Nanley Chery <nanley.g.ch...@intel.com>
Reviewed-by: Iago Toral Quiroga <ito...@igalia.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Cc: "17.3" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 361e1df1edb23b08e36027136f1dc73f52dea536)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0b31126ba9c57876a2ec57540a3ec243703e5002
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Tue Dec 5 14:41:48 2017 -0800
Re-enable regular fast-clears (CCS_D) on gen9+
This reverts commit ee57b15ec764736e2d5360beaef9fb2045ed0f68, "i965:
Disable regular fast-clears (CCS_D) on gen9+". How taht we've fixed the
issue with too many different aux usages in the render cache, it should
be safe to re-enable CCS_D for sRGB.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=104163
Tested-by: Eero Tamminen <eero.t.tammi...@intel.com>
Reviewed-by: Iago Toral Quiroga <ito...@igalia.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Cc: "17.3" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit f79bb2e651f329364dfb3db0aac4b72f91f130cc)
[Emil Velikov: resolve trivial conflicts - gen10 is missing in branch]
Signed-off-by: Emil Velikov <emil.veli...@collabora.com>
Conflicts:
src/mesa/drivers/dri/i965/brw_meta_util.c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6bfb9c31a0b3faae52f489535033fd9784698ac
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Wed Dec 13 17:25:26 2017 -0800
i965: Track format and aux usage in the render cache
This lets us perform render cache flushes whenever a surface goes from
being used with one aux+format to a different aux+format.
This is the "proper" fix for https://bugs.freedesktop.org/102435.
ee57b15ec764736e2d5360beaef9fb2045ed0f68 which was really just a partial
revert of 3e57e9494c2279580ad6a83ab8c065d01e7e634e was just a hack to
get rid of a hang in a bunch of Valve games. This solves the actual
problem responsible for the hang and lets us enable CCS_E once again.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102435
Reviewed-by: Iago Toral Quiroga <ito...@igalia.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Cc: "17.3" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit d84275b884244a2fd3a6e67ceb2a5277e5edf89a)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6fce0e20659de14ce055578df22463e9e0cd22c6
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Nov 3 16:11:54 2017 -0700
i965: Track the depth and render caches separately
Previously, we just had one hash set for tracking depth and render
caches called brw_context::render_cache. This is less than ideal
because the depth and render caches are separate and we can't track
moves between the depth and the render caches. This limitation led
to some unnecessary flushing around the depth cache. There are cases
(mostly with BLORP) where we can end up touching a depth or stencil
buffer through the render cache. To guard against this, blorp would
unconditionally do a render_cache_set_check_flush on it's destination
which meant that if you did any rendering (including a BLORP operation)
to a given surface and then used it as a blorp destination, you would
end up flushing it out of the render cache before rendering into it.
Things get worse when you dig into the depth/stencil state code for
regular GL draw calls. Because we may end up rendering to a depth
or stencil buffer via BLORP, we did a render_cache_set_check_flush on
all depth and stencil buffers in brw_emit_depthbuffer to ensure that
they got flushed out of the render cache prior to using them for depth
or stencil testing. However, because we also need to track dirtiness
for depth and stencil so that we can implement depth and stencil
texturing correctly, we were adding all depth and stencil buffers to the
render cache set in brw_postdraw_set_buffers_need_resolve. This meant
that, if anything caused 3DSTATE_DEPTH_BUFFER to get re-emitted
(currently _NEW_BUFFERS, BRW_NEW_BATCH, and BRW_NEW_BLORP), we would
almost always do a full pipeline stall and render/depth cache flush.
The root cause of both of these problems is that we can't tell the
difference between the render and depth caches in our tracking. This
commit splits our cache tracking into two sets, one for render and one
for depth, and properly handles transitioning between the two. We still
flush all the caches whenever anything needs to be flushed. The idea is
that if we're going to take the hit of a flush and stall, we may as well
flush everything in the hopes that we can avoid a flush by something
else later.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
(cherry picked from commit fb0e9b5197cb65bde1e116d89acd5deb32f9132c)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0bbd60f3e9c45a93b9dc6e72d3134474d38de079
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Nov 3 16:03:52 2017 -0700
i965/blorp: Add more destination flushing
Right now we just always flush the destination for render and aren't
particularly careful about depth or stencil. Soon, flush_for_render
isn't going to do the same thing as flush_for_depth and we may be doing
a good deal less depth flushing so we should be a bit more precise.
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
(cherry picked from commit d6d0ac95d5d77bd18b2064c3ed9aad70cf38cb6f)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6f5752dba7ae0f7c8a650c134e2662e40cd4c0b1
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Fri Nov 3 16:01:28 2017 -0700
i965: Add more precise cache tracking helpers
In theory, this will let us track the depth and render caches
separately. Right now, they're just wrappers around
brw_render_cache_set_*
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
(cherry picked from commit 4a09070295294e9017fa686fc8e113989ef0f41b)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e66bafa97360ac5c1be310a25a7a77b90fb5c08e
Author: Jason Ekstrand <jason.ekstr...@intel.com>
Date: Wed Dec 13 17:23:41 2017 -0800
i965: Call brw_cache_flush_for_render in predraw_resolve_framebuffer
This makes sure we flush things out of other caches prior to using a
surface through the render cache. Currently, this is a no-op because GL
won't let you bind anything other than a color surface as color so it
should never end up in the depth cache. However, this does complete the
flush/add_bo pair for regular drawing which will be required for the
next commit.
Reviewed-by: Iago Toral Quiroga <ito...@igalia.com>
Reviewed-by: Kenneth Graunke <kenn...@whitecape.org>
Cc: "17.3" <mesa-sta...@lists.freedesktop.org>
(cherry picked from commit 622786c20c6cd073071b00ddf6e50c447f8c5768)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=510f1b3cb9fd52e86c8972e516a201d7e6626f68
Author: Grazvydas Ignotas <nota...@gmail.com>
Date: Mon Jan 15 23:59:20 2018 +0200
st/va: release held locks in error paths
Found with the help of following Coccinelle semantic patch:
// <smpl>
@@
expression E;
@@
\(pthread_mutex_lock\|mtx_lock\|simple_mtx_lock\)(E)
...
(
\(pthread_mutex_unlock\|mtx_unlock\|simple_mtx_unlock\)(E);
...
return ...;
|
+ maybe need_unlock(E);
return ...;
)
// </smpl>
Signed-off-by: Grazvydas Ignotas <nota...@gmail.com>
Reviewed-by: Christian König <christian.koe...@amd.com>
Cc: mesa-sta...@lists.freedesktop.org
(cherry picked from commit 0ad73031ec2f9dee6d3ad20dd625b0134ea8ec8b)
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=694ed0d61a93f3e91c2fa9f7fbc3d736a8d701ec
Author: Gert Wollny <gw.foss...@gmail.com>
Date: Sun Jan 14 18:13:31 2018 +0100
r600/shader: Initialize max_driver_temp_used correctly for the first time
Without this initialization the temp registers used in tgsi_declaration
may used random indices, and this may result in failing translation from
TGSI
with an error message "GPR limit exceeded", because the random index is
greater
then the allowed limit implying that the shader uses more temporary
registers then
available.
Signed-off-by: Gert Wollny <gw.foss...@gmail.com>
Cc: <mesa-sta...@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airl...@redhat.com>
(cherry picked from commit 5d6470d26b267d522dd343740878bde46f21c446)
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