Module: Mesa
Branch: master
Commit: 4b467c759ea1e9d5960a5e668a166f33ef03e9d6
URL:    
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4b467c759ea1e9d5960a5e668a166f33ef03e9d6

Author: Dave Airlie <airl...@redhat.com>
Date:   Tue Mar 28 11:34:46 2017 +1000

radv: move shader_z_format calculation to pipeline.

No need to recalculate this every time.

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airl...@redhat.com>

---

 src/amd/vulkan/radv_cmd_buffer.c | 5 +----
 src/amd/vulkan/radv_pipeline.c   | 6 ++++++
 src/amd/vulkan/radv_private.h    | 1 +
 3 files changed, 8 insertions(+), 4 deletions(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 8e35dc5299..c3b141ea3a 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -709,10 +709,7 @@ radv_emit_fragment_shader(struct radv_cmd_buffer 
*cmd_buffer,
        radeon_set_context_reg(cmd_buffer->cs, R_0286E0_SPI_BARYC_CNTL, 
spi_baryc_cntl);
 
        radeon_set_context_reg(cmd_buffer->cs, R_028710_SPI_SHADER_Z_FORMAT,
-                              ps->info.fs.writes_sample_mask ? 
V_028710_SPI_SHADER_32_ABGR :
-                              ps->info.fs.writes_stencil ? 
V_028710_SPI_SHADER_32_GR :
-                              ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
-                              V_028710_SPI_SHADER_ZERO);
+                              pipeline->graphics.shader_z_format);
 
        radeon_set_context_reg(cmd_buffer->cs, R_028714_SPI_SHADER_COL_FORMAT, 
blend->spi_shader_col_format);
 
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 42e8abd84e..550b773e9a 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -1666,6 +1666,12 @@ radv_pipeline_init(struct radv_pipeline *pipeline,
                S_02880C_EXEC_ON_HIER_FAIL(ps->info.fs.writes_memory) |
                S_02880C_EXEC_ON_NOOP(ps->info.fs.writes_memory);
 
+       pipeline->graphics.shader_z_format =
+               ps->info.fs.writes_sample_mask ? V_028710_SPI_SHADER_32_ABGR :
+               ps->info.fs.writes_stencil ? V_028710_SPI_SHADER_32_GR :
+               ps->info.fs.writes_z ? V_028710_SPI_SHADER_32_R :
+               V_028710_SPI_SHADER_ZERO;
+
        const VkPipelineVertexInputStateCreateInfo *vi_info =
                pCreateInfo->pVertexInputState;
        for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) 
{
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 8e45e95b77..dff0aef832 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -956,6 +956,7 @@ struct radv_pipeline {
                        struct radv_raster_state raster;
                        struct radv_multisample_state ms;
                        uint32_t db_shader_control;
+                       uint32_t shader_z_format;
                        unsigned prim;
                        unsigned gs_out;
                        uint32_t vgt_gs_mode;

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