Module: Mesa Branch: master Commit: 55dac91adc40db191c385f9a2ce393f46dd9b859 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=55dac91adc40db191c385f9a2ce393f46dd9b859
Author: Jonathan Marek <jonat...@marek.ca> Date: Tue Dec 17 17:29:02 2019 -0500 turnip: fix tile->slot calculation Fixes HW binning cases when the horizontal number of tiles isn't divisible by the horizontal number of pipes (only happens with more than 32 tiles). Signed-off-by: Jonathan Marek <jonat...@marek.ca> Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3142> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/3142> --- src/freedreno/vulkan/tu_cmd_buffer.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c b/src/freedreno/vulkan/tu_cmd_buffer.c index b9408f87a4b..74997b31933 100644 --- a/src/freedreno/vulkan/tu_cmd_buffer.c +++ b/src/freedreno/vulkan/tu_cmd_buffer.c @@ -318,6 +318,10 @@ tu_tiling_config_get_tile(const struct tu_tiling_config *tiling, const uint32_t py = ty / tiling->pipe0.height; const uint32_t sx = tx - tiling->pipe0.width * px; const uint32_t sy = ty - tiling->pipe0.height * py; + /* last pipe has different width */ + const uint32_t pipe_width = + MIN2(tiling->pipe0.width, + tiling->tile_count.width - px * tiling->pipe0.width); assert(tx < tiling->tile_count.width && ty < tiling->tile_count.height); assert(px < tiling->pipe_count.width && py < tiling->pipe_count.height); @@ -325,7 +329,7 @@ tu_tiling_config_get_tile(const struct tu_tiling_config *tiling, /* convert to 1D indices */ tile->pipe = tiling->pipe_count.width * py + px; - tile->slot = tiling->pipe0.width * sy + sx; + tile->slot = pipe_width * sy + sx; /* get the blit area for the tile */ tile->begin = (VkOffset2D) { _______________________________________________ mesa-commit mailing list mesa-commit@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-commit
