Mesa (master): gallivm, llvmpipe: Use 4-wide vectors on AMD Bulldozer.
Module: Mesa
Branch: master
Commit: 7eb504019731368fd55f01e0264b195d4f99ae93
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7eb504019731368fd55f01e0264b195d4f99ae93
Author: José Fonseca
Date: Fri Aug 31 17:01:50 2012 +0100
gallivm,llvmpipe: Use 4-wide vectors on AMD Bulldozer.
8-wide vectors is slower.
Reviewed-by: Roland Scheidegger
---
src/gallium/auxiliary/gallivm/lp_bld_init.c | 10 +-
src/gallium/auxiliary/util/u_cpu_detect.c |5 +
src/gallium/auxiliary/util/u_cpu_detect.h |1 +
3 files changed, 15 insertions(+), 1 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_init.c
b/src/gallium/auxiliary/gallivm/lp_bld_init.c
index 068a2cd..ffbe3ea 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_init.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_init.c
@@ -434,8 +434,16 @@ lp_build_init(void)
util_cpu_detect();
+ /* AMD Bulldozer AVX's throughput is the same as SSE2; and because using
+* 8-wide vector needs more floating ops than 4-wide (due to padding), it is
+* actually more efficient to use 4-wide vectors on this processor.
+*
+* See also:
+* -
http://www.anandtech.com/show/4955/the-bulldozer-review-amd-fx8150-tested/2
+*/
if (HAVE_AVX &&
- util_cpu_caps.has_avx) {
+ util_cpu_caps.has_avx &&
+ util_cpu_caps.has_intel) {
lp_native_vector_width = 256;
} else {
/* Leave it at 128, even when no SIMD extensions are available.
diff --git a/src/gallium/auxiliary/util/u_cpu_detect.c
b/src/gallium/auxiliary/util/u_cpu_detect.c
index 945f0b0..d7f0be4 100644
--- a/src/gallium/auxiliary/util/u_cpu_detect.c
+++ b/src/gallium/auxiliary/util/u_cpu_detect.c
@@ -286,6 +286,11 @@ util_cpu_detect(void)
util_cpu_caps.cacheline = cacheline;
}
+ if (regs[1] == 0x756e6547 && regs[2] == 0x6c65746e && regs[3] ==
0x49656e69) {
+ /* GenuineIntel */
+ util_cpu_caps.has_intel = 1;
+ }
+
cpuid(0x8000, regs);
if (regs[0] >= 0x8001) {
diff --git a/src/gallium/auxiliary/util/u_cpu_detect.h
b/src/gallium/auxiliary/util/u_cpu_detect.h
index b44d9d9..acac686 100644
--- a/src/gallium/auxiliary/util/u_cpu_detect.h
+++ b/src/gallium/auxiliary/util/u_cpu_detect.h
@@ -52,6 +52,7 @@ struct util_cpu_caps {
int x86_cpu_type;
unsigned cacheline;
+ unsigned has_intel:1;
unsigned has_tsc:1;
unsigned has_mmx:1;
unsigned has_mmx2:1;
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Mesa (master): radeon/llvm: fix SelectADDR8BitOffset
Module: Mesa
Branch: master
Commit: 8758183f0aa7147310fb5c5e46a47f59c2d4bcc1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8758183f0aa7147310fb5c5e46a47f59c2d4bcc1
Author: Christian König
Date: Fri Aug 31 13:49:06 2012 +0200
radeon/llvm: fix SelectADDR8BitOffset
The offset is unsigned, not signed.
Signed-off-by: Christian König
Reviewed-by: Michel Dänzer
---
src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp
b/src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp
index 63bc21e..8071131 100644
--- a/src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp
+++ b/src/gallium/drivers/radeon/AMDILISelDAGToDAG.cpp
@@ -337,7 +337,7 @@ bool AMDGPUDAGToDAGISel::SelectADDR8BitOffset(SDValue Addr,
SDValue& Base,
}
// Check if the constant argument fits in 8-bits. The offset is in bytes
// so we need to convert it to dwords.
- if (isInt<8>(OffsetNode->getZExtValue() >> 2)) {
+ if (isUInt<8>(OffsetNode->getZExtValue() >> 2)) {
Match = true;
Offset = CurDAG->getTargetConstant(OffsetNode->getZExtValue() >> 2,
MVT::i32);
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Mesa (master): radeonsi: adjust PIPE_SHADER_CAP_MAX_CONSTS
Module: Mesa Branch: master Commit: de7d3825a0a2e4144e0b38a0d8fef759819af64a URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=de7d3825a0a2e4144e0b38a0d8fef759819af64a Author: Christian König Date: Fri Aug 31 13:59:14 2012 +0200 radeonsi: adjust PIPE_SHADER_CAP_MAX_CONSTS So it matches what we really can do. Signed-off-by: Christian König Reviewed-by: Michel Dänzer --- src/gallium/drivers/radeonsi/radeonsi_pipe.c |4 ++-- src/gallium/drivers/radeonsi/radeonsi_pipe.h |3 --- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c b/src/gallium/drivers/radeonsi/radeonsi_pipe.c index 48b9a3e..f3914d7 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c +++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c @@ -450,9 +450,9 @@ static int r600_get_shader_param(struct pipe_screen* pscreen, unsigned shader, e /* FIXME Isn't this equal to TEMPS? */ return 1; /* Max native address registers */ case PIPE_SHADER_CAP_MAX_CONSTS: - return R600_MAX_CONST_BUFFER_SIZE; + return 64; case PIPE_SHADER_CAP_MAX_CONST_BUFFERS: - return R600_MAX_CONST_BUFFERS; + return 1; case PIPE_SHADER_CAP_MAX_PREDS: return 0; /* FIXME */ case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED: diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.h b/src/gallium/drivers/radeonsi/radeonsi_pipe.h index 099b509..a23f34f 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_pipe.h +++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.h @@ -41,9 +41,6 @@ #include "r600_resource.h" #include "sid.h" -#define R600_MAX_CONST_BUFFERS 1 -#define R600_MAX_CONST_BUFFER_SIZE 4096 - #ifdef PIPE_ARCH_BIG_ENDIAN #define R600_BIG_ENDIAN 1 #else ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeonsi: stop big offsets from hanging the GPU v2
Module: Mesa
Branch: master
Commit: 88a4fd8fe6b47b4685e3fb5e36047d27f764703b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=88a4fd8fe6b47b4685e3fb5e36047d27f764703b
Author: Christian König
Date: Wed Aug 29 10:48:01 2012 +0200
radeonsi: stop big offsets from hanging the GPU v2
v2: rebased of radeon/llvm fix.
Signed-off-by: Christian König
Reviewed-by: Michel Dänzer
---
src/gallium/drivers/radeonsi/radeonsi_shader.c | 11 +--
1 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c
b/src/gallium/drivers/radeonsi/radeonsi_shader.c
index 9734ab3..8c92149 100644
--- a/src/gallium/drivers/radeonsi/radeonsi_shader.c
+++ b/src/gallium/drivers/radeonsi/radeonsi_shader.c
@@ -357,6 +357,7 @@ static LLVMValueRef fetch_constant(
unsigned swizzle)
{
struct lp_build_context * base = &bld_base->base;
+ unsigned idx;
LLVMValueRef const_ptr;
LLVMValueRef offset;
@@ -376,8 +377,14 @@ static LLVMValueRef fetch_constant(
/* XXX: This assumes that the constant buffer is not packed, so
* CONST[0].x will have an offset of 0 and CONST[1].x will have an
* offset of 4. */
- offset = lp_build_const_int32(base->gallivm,
- (reg->Register.Index * 4) + swizzle);
+ idx = (reg->Register.Index * 4) + swizzle;
+
+ /* index loads above 255 are currently not supported */
+ if (idx > 255) {
+ assert(0);
+ idx = 0;
+ }
+ offset = lp_build_const_int32(base->gallivm, idx);
load = build_indexed_load(base->gallivm, const_ptr, offset);
return bitcast(bld_base, type, load);
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Mesa (master): winsys/radeon: create only one winsys for each fd
Module: Mesa
Branch: master
Commit: 73dd82061e7a5242c88b529c274784731462e039
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=73dd82061e7a5242c88b529c274784731462e039
Author: Christian König
Date: Thu Aug 30 10:26:48 2012 +0200
winsys/radeon: create only one winsys for each fd
Fixing problems with GLAMOR.
Signed-off-by: Christian König
Reviewed-by: Michel Dänzer
---
src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 38 +++-
src/gallium/winsys/radeon/drm/radeon_winsys.h |5 +++
2 files changed, 41 insertions(+), 2 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
index c03dd04..33451ab 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_winsys.c
@@ -37,6 +37,7 @@
#include "pipebuffer/pb_bufmgr.h"
#include "util/u_memory.h"
+#include "util/u_hash_table.h"
#include
#include
@@ -89,6 +90,7 @@
#define RADEON_INFO_TIMESTAMP 0x11
#endif
+static struct util_hash_table *fd_tab = NULL;
/* Enable/disable feature access for one command stream.
* If enable == TRUE, return TRUE on success.
@@ -318,6 +320,10 @@ static void radeon_winsys_destroy(struct radeon_winsys
*rws)
{
struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
+if (!pipe_reference(&ws->base.reference, NULL)) {
+return;
+}
+
pipe_mutex_destroy(ws->hyperz_owner_mutex);
pipe_mutex_destroy(ws->cmask_owner_mutex);
@@ -326,6 +332,9 @@ static void radeon_winsys_destroy(struct radeon_winsys *rws)
if (ws->gen >= R600) {
radeon_surface_manager_free(ws->surf_man);
}
+if (fd_tab) {
+util_hash_table_remove(fd_tab, intptr_to_pointer(ws->fd));
+}
FREE(rws);
}
@@ -395,14 +404,36 @@ static uint64_t radeon_query_timestamp(struct
radeon_winsys *rws)
return ts;
}
+static unsigned hash_fd(void *key)
+{
+return pointer_to_intptr(key);
+}
+
+static int compare_fd(void *key1, void *key2)
+{
+return pointer_to_intptr(key1) != pointer_to_intptr(key2);
+}
+
struct radeon_winsys *radeon_drm_winsys_create(int fd)
{
-struct radeon_drm_winsys *ws = CALLOC_STRUCT(radeon_drm_winsys);
+struct radeon_drm_winsys *ws;
+
+if (!fd_tab) {
+fd_tab = util_hash_table_create(hash_fd, compare_fd);
+}
+
+ws = util_hash_table_get(fd_tab, intptr_to_pointer(fd));
+if (ws) {
+pipe_reference(NULL, &ws->base.reference);
+return &ws->base;
+}
+
+ws = CALLOC_STRUCT(radeon_drm_winsys);
if (!ws) {
return NULL;
}
-
ws->fd = fd;
+util_hash_table_set(fd_tab, intptr_to_pointer(fd), ws);
if (!do_winsys_init(ws))
goto fail;
@@ -421,6 +452,9 @@ struct radeon_winsys *radeon_drm_winsys_create(int fd)
goto fail;
}
+/* init reference */
+pipe_reference_init(&ws->base.reference, 1);
+
/* Set functions. */
ws->base.destroy = radeon_winsys_destroy;
ws->base.query_info = radeon_query_info;
diff --git a/src/gallium/winsys/radeon/drm/radeon_winsys.h
b/src/gallium/winsys/radeon/drm/radeon_winsys.h
index 4eb57fb..8e4693b 100644
--- a/src/gallium/winsys/radeon/drm/radeon_winsys.h
+++ b/src/gallium/winsys/radeon/drm/radeon_winsys.h
@@ -108,6 +108,11 @@ enum radeon_feature_id {
struct radeon_winsys {
/**
+ * Reference counting
+ */
+struct pipe_reference reference;
+
+/**
* Destroy this winsys.
*
* \param wsThe winsys this function is called from.
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Mesa (master): radeon/llvm: swap wrong OPCODE_IS_*_ZERO_* opcode and use
Module: Mesa Branch: master Commit: 6a85725f136862d8877dc76369c64e0c8b5ea4e6 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=6a85725f136862d8877dc76369c64e0c8b5ea4e6 Author: Vincent Lejeune Date: Tue Sep 4 16:49:25 2012 +0200 radeon/llvm: swap wrong OPCODE_IS_*_ZERO_* opcode and use Reviewed-by: Tom Stellard --- src/gallium/drivers/radeon/AMDGPUInstrInfo.h|4 ++-- src/gallium/drivers/radeon/R600ISelLowering.cpp |4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h index 2643119..a308076 100644 --- a/src/gallium/drivers/radeon/AMDGPUInstrInfo.h +++ b/src/gallium/drivers/radeon/AMDGPUInstrInfo.h @@ -25,8 +25,8 @@ #define GET_INSTRINFO_ENUM #include "AMDGPUGenInstrInfo.inc" -#define OPCODE_IS_ZERO_INT 0x0045 -#define OPCODE_IS_NOT_ZERO_INT 0x0042 +#define OPCODE_IS_ZERO_INT 0x0042 +#define OPCODE_IS_NOT_ZERO_INT 0x0045 #define OPCODE_IS_ZERO 0x0020 #define OPCODE_IS_NOT_ZERO 0x0023 diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp b/src/gallium/drivers/radeon/R600ISelLowering.cpp index fec9d4e..7c93935 100644 --- a/src/gallium/drivers/radeon/R600ISelLowering.cpp +++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp @@ -207,7 +207,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter( BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X)) .addReg(AMDGPU::PREDICATE_BIT) .addOperand(MI->getOperand(1)) -.addImm(OPCODE_IS_ZERO) +.addImm(OPCODE_IS_NOT_ZERO) .addImm(0); // Flags TII->addFlag(NewMI, 1, MO_FLAG_PUSH); BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP)) @@ -221,7 +221,7 @@ MachineBasicBlock * R600TargetLowering::EmitInstrWithCustomInserter( BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::PRED_X)) .addReg(AMDGPU::PREDICATE_BIT) .addOperand(MI->getOperand(1)) - .addImm(OPCODE_IS_ZERO_INT) + .addImm(OPCODE_IS_NOT_ZERO_INT) .addImm(0); // Flags TII->addFlag(NewMI, 1, MO_FLAG_PUSH); BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::JUMP)) ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radon/llvm: br_cc f32 now lowered without cast
Module: Mesa
Branch: master
Commit: a383142436a21403dd19abb25a654fc634770c74
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a383142436a21403dd19abb25a654fc634770c74
Author: Vincent Lejeune
Date: Tue Sep 4 17:04:27 2012 +0200
radon/llvm: br_cc f32 now lowered without cast
Reviewed-by: Tom Stellard
---
src/gallium/drivers/radeon/R600ISelLowering.cpp | 33 --
1 files changed, 24 insertions(+), 9 deletions(-)
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp
b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index 7c93935..016befa 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -34,7 +34,8 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
computeRegisterProperties();
setOperationAction(ISD::BR_CC, MVT::i32, Custom);
-
+ setOperationAction(ISD::BR_CC, MVT::f32, Custom);
+
setOperationAction(ISD::FSUB, MVT::f32, Expand);
setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
@@ -338,14 +339,28 @@ SDValue R600TargetLowering::LowerBR_CC(SDValue Op,
SelectionDAG &DAG) const
SDValue JumpT = Op.getOperand(4);
SDValue CmpValue;
SDValue Result;
- CmpValue = DAG.getNode(
- ISD::SELECT_CC,
- Op.getDebugLoc(),
- MVT::i32,
- LHS, RHS,
- DAG.getConstant(-1, MVT::i32),
- DAG.getConstant(0, MVT::i32),
- CC);
+
+ if (LHS.getValueType() == MVT::i32) {
+CmpValue = DAG.getNode(
+ISD::SELECT_CC,
+Op.getDebugLoc(),
+MVT::i32,
+LHS, RHS,
+DAG.getConstant(-1, MVT::i32),
+DAG.getConstant(0, MVT::i32),
+CC);
+ } else if (LHS.getValueType() == MVT::f32) {
+CmpValue = DAG.getNode(
+ISD::SELECT_CC,
+Op.getDebugLoc(),
+MVT::f32,
+LHS, RHS,
+DAG.getConstantFP(1.0f, MVT::f32),
+DAG.getConstantFP(0.0f, MVT::f32),
+CC);
+ } else {
+assert(0 && "Not valid type for br_cc");
+ }
Result = DAG.getNode(
AMDGPUISD::BRANCH_COND,
CmpValue.getDebugLoc(),
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Mesa (master): radeon/llvm: support setcc on f32
Module: Mesa
Branch: master
Commit: d9e135e18cb438aad4b0bdf89a7273d705549150
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d9e135e18cb438aad4b0bdf89a7273d705549150
Author: Vincent Lejeune
Date: Tue Sep 4 17:04:28 2012 +0200
radeon/llvm: support setcc on f32
Reviewed-by: Tom Stellard
---
src/gallium/drivers/radeon/R600ISelLowering.cpp | 36 +--
1 files changed, 27 insertions(+), 9 deletions(-)
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp
b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index 016befa..7ad0178 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -47,7 +47,7 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
setOperationAction(ISD::SETCC, MVT::i32, Custom);
-
+ setOperationAction(ISD::SETCC, MVT::f32, Custom);
setSchedulingPreference(Sched::VLIW);
}
@@ -519,14 +519,32 @@ SDValue R600TargetLowering::LowerSETCC(SDValue Op,
SelectionDAG &DAG) const
SDValue CC = Op.getOperand(2);
DebugLoc DL = Op.getDebugLoc();
assert(Op.getValueType() == MVT::i32);
- Cond = DAG.getNode(
- ISD::SELECT_CC,
- Op.getDebugLoc(),
- MVT::i32,
- LHS, RHS,
- DAG.getConstant(-1, MVT::i32),
- DAG.getConstant(0, MVT::i32),
- CC);
+ if (LHS.getValueType() == MVT::i32) {
+Cond = DAG.getNode(
+ISD::SELECT_CC,
+Op.getDebugLoc(),
+MVT::i32,
+LHS, RHS,
+DAG.getConstant(-1, MVT::i32),
+DAG.getConstant(0, MVT::i32),
+CC);
+ } else if (LHS.getValueType() == MVT::f32) {
+Cond = DAG.getNode(
+ISD::SELECT_CC,
+Op.getDebugLoc(),
+MVT::f32,
+LHS, RHS,
+DAG.getConstantFP(1.0f, MVT::f32),
+DAG.getConstantFP(0.0f, MVT::f32),
+CC);
+Cond = DAG.getNode(
+ISD::FP_TO_SINT,
+DL,
+MVT::i32,
+Cond);
+ } else {
+assert(0 && "Not valid type for set_cc");
+ }
Cond = DAG.getNode(
ISD::AND,
DL,
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Mesa (master): radeon/llvm: do not convert f32 operand of select_cc node
Module: Mesa
Branch: master
Commit: 8eaa36317a0a2911cb78066947bc841dd8ce86c8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8eaa36317a0a2911cb78066947bc841dd8ce86c8
Author: Vincent Lejeune
Date: Tue Sep 4 17:28:26 2012 +0200
radeon/llvm: do not convert f32 operand of select_cc node
v2:-use camel coding style
Reviewed-by: Tom Stellard
---
src/gallium/drivers/radeon/R600ISelLowering.cpp | 40 +++---
1 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp
b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index 79cd622..5642ee8 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -441,32 +441,32 @@ SDValue R600TargetLowering::LowerSELECT_CC(SDValue Op,
SelectionDAG &DAG) const
// necessary we need to convert LHS and RHS to be the same type True and
// False. True and False are guaranteed to have the same type as this
// SELECT_CC node.
-
- if (CompareVT != VT) {
-ISD::NodeType ConversionOp = ISD::DELETED_NODE;
-if (VT == MVT::f32 && CompareVT == MVT::i32) {
- if (isUnsignedIntSetCC(CCOpcode)) {
-ConversionOp = ISD::UINT_TO_FP;
+
+ if (isHWTrueValue(True) && isHWFalseValue(False)) {
+if (CompareVT != VT) {
+ if (VT == MVT::f32 && CompareVT == MVT::i32) {
+SDValue Boolean = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
+LHS, RHS,
+DAG.getConstant(-1, MVT::i32),
+DAG.getConstant(0, MVT::i32),
+CC);
+return DAG.getNode(ISD::UINT_TO_FP, DL, VT, Boolean);
+ } else if (VT == MVT::i32 && CompareVT == MVT::f32) {
+SDValue BoolAsFlt = DAG.getNode(ISD::SELECT_CC, DL, CompareVT,
+LHS, RHS,
+DAG.getConstantFP(1.0f, MVT::f32),
+DAG.getConstantFP(0.0f, MVT::f32),
+CC);
+return DAG.getNode(ISD::FP_TO_UINT, DL, VT, BoolAsFlt);
} else {
-ConversionOp = ISD::SINT_TO_FP;
+// I don't think there will be any other type pairings.
+assert(!"Unhandled operand type parings in SELECT_CC");
}
-} else if (VT == MVT::i32 && CompareVT == MVT::f32) {
- ConversionOp = ISD::FP_TO_SINT;
} else {
- // I don't think there will be any other type pairings.
- assert(!"Unhandled operand type parings in SELECT_CC");
+ return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
}
-// XXX Check the value of LHS and RHS and avoid creating sequences like
-// (FTOI (ITOF))
-LHS = DAG.getNode(ConversionOp, DL, VT, LHS);
-RHS = DAG.getNode(ConversionOp, DL, VT, RHS);
}
- // If True is a hardware TRUE value and False is a hardware FALSE value or
- // vice-versa we can handle this with a native instruction (SET*
instructions).
- if ((isHWTrueValue(True) && isHWFalseValue(False))) {
-return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
- }
// XXX If True is a hardware TRUE value and False is a hardware FALSE value,
// we can handle this with a native instruction, but we need to swap true
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Mesa (master): radeon/llvm: custom lowering for FP_TO_UINT when dst is i1 ( bool)
Module: Mesa
Branch: master
Commit: a4325b32298cb99b1e99620a33ef0bee52298c3c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a4325b32298cb99b1e99620a33ef0bee52298c3c
Author: Vincent Lejeune
Date: Tue Sep 4 17:29:48 2012 +0200
radeon/llvm: custom lowering for FP_TO_UINT when dst is i1 (bool)
v2:-wrap line at 80 characters
Reviewed-by: Tom Stellard
---
src/gallium/drivers/radeon/R600ISelLowering.cpp | 22 ++
src/gallium/drivers/radeon/R600ISelLowering.h |6 --
2 files changed, 26 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.cpp
b/src/gallium/drivers/radeon/R600ISelLowering.cpp
index 7ad0178..79cd622 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.cpp
+++ b/src/gallium/drivers/radeon/R600ISelLowering.cpp
@@ -48,6 +48,7 @@ R600TargetLowering::R600TargetLowering(TargetMachine &TM) :
setOperationAction(ISD::SETCC, MVT::i32, Custom);
setOperationAction(ISD::SETCC, MVT::f32, Custom);
+ setOperationAction(ISD::FP_TO_UINT, MVT::i1, Custom);
setSchedulingPreference(Sched::VLIW);
}
@@ -330,6 +331,27 @@ SDValue R600TargetLowering::LowerOperation(SDValue Op,
SelectionDAG &DAG) const
return SDValue();
}
+void R600TargetLowering::ReplaceNodeResults(SDNode *N,
+SmallVectorImpl &Results,
+SelectionDAG &DAG) const
+{
+ switch (N->getOpcode()) {
+ default: return;
+ case ISD::FP_TO_UINT: Results.push_back(LowerFPTOUINT(N->getOperand(0),
DAG));
+ }
+}
+
+SDValue R600TargetLowering::LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const
+{
+ return DAG.getNode(
+ ISD::SETCC,
+ Op.getDebugLoc(),
+ MVT::i1,
+ Op, DAG.getConstantFP(0.0f, MVT::f32),
+ DAG.getCondCode(ISD::SETNE)
+ );
+}
+
SDValue R600TargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const
{
SDValue Chain = Op.getOperand(0);
diff --git a/src/gallium/drivers/radeon/R600ISelLowering.h
b/src/gallium/drivers/radeon/R600ISelLowering.h
index 2eb7edd..49ea272 100644
--- a/src/gallium/drivers/radeon/R600ISelLowering.h
+++ b/src/gallium/drivers/radeon/R600ISelLowering.h
@@ -27,7 +27,9 @@ public:
virtual MachineBasicBlock * EmitInstrWithCustomInserter(MachineInstr *MI,
MachineBasicBlock * BB) const;
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
-
+ void ReplaceNodeResults(SDNode * N,
+ SmallVectorImpl &Results,
+ SelectionDAG &DAG) const;
private:
const R600InstrInfo * TII;
@@ -48,7 +50,7 @@ private:
SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
-
+ SDValue LowerFPTOUINT(SDValue Op, SelectionDAG &DAG) const;
};
} // End namespace llvm;
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Mesa (master): mesa: fix DIFFERENT_SIGNS() function
Module: Mesa Branch: master Commit: f73ffacbf0c65ad843406af37aa35e9112bc8038 URL: http://cgit.freedesktop.org/mesa/mesa/commit/?id=f73ffacbf0c65ad843406af37aa35e9112bc8038 Author: Brian Paul Date: Tue Sep 4 10:02:20 2012 -0600 mesa: fix DIFFERENT_SIGNS() function Looks like converting this to a macro, returning bool, caused us to lose the high (31st) bit result. Fixes piglit fbo-1d test. Strange that none of the other tests I ran caught this. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=54365 Tested-by: Vinson Lee --- src/mesa/main/macros.h |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/main/macros.h b/src/mesa/main/macros.h index fc6f2a2..04d59d7 100644 --- a/src/mesa/main/macros.h +++ b/src/mesa/main/macros.h @@ -711,7 +711,7 @@ DIFFERENT_SIGNS(GLfloat x, GLfloat y) fi_type xfi, yfi; xfi.f = x; yfi.f = y; - return (xfi.i ^ yfi.i) & (1u << 31); + return !!((xfi.i ^ yfi.i) & (1u << 31)); #else /* Could just use (x*y<0) except for the flatshading requirements. * Maybe there's a better way? ___ mesa-commit mailing list mesa-commit@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-commit
Mesa (master): radeon/llvm: Fix encoding of V_CNDMASK_B32
Module: Mesa
Branch: master
Commit: f9fede884b7ace711ccf63152afdbdaf209edced
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f9fede884b7ace711ccf63152afdbdaf209edced
Author: Tom Stellard
Date: Fri Aug 31 16:11:38 2012 -0400
radeon/llvm: Fix encoding of V_CNDMASK_B32
The CodeEmitter was not setting the VGPR bit for src0, because the
instruction definition had the VCC register in the src0 slot, instead of
the actual src0 register. This has been fixed by moving the VCC
register to the end of the operand list.
---
src/gallium/drivers/radeon/SIISelLowering.cpp |4 ++--
src/gallium/drivers/radeon/SIInstructions.td |4 ++--
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/radeon/SIISelLowering.cpp
b/src/gallium/drivers/radeon/SIISelLowering.cpp
index d2fd995..a64e2a3 100644
--- a/src/gallium/drivers/radeon/SIISelLowering.cpp
+++ b/src/gallium/drivers/radeon/SIISelLowering.cpp
@@ -242,9 +242,9 @@ void SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI,
MachineBasicBlock &BB,
BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CNDMASK_B32))
.addOperand(MI->getOperand(0))
- .addReg(AMDGPU::VCC)
.addOperand(MI->getOperand(2))
- .addOperand(MI->getOperand(3));
+ .addOperand(MI->getOperand(3))
+ .addReg(AMDGPU::VCC);
MI->eraseFromParent();
}
diff --git a/src/gallium/drivers/radeon/SIInstructions.td
b/src/gallium/drivers/radeon/SIInstructions.td
index 291c034..e9e91fd 100644
--- a/src/gallium/drivers/radeon/SIInstructions.td
+++ b/src/gallium/drivers/radeon/SIInstructions.td
@@ -670,7 +670,7 @@ def S_WAITCNT : SOPP <0x000c, (ins i32imm:$simm16),
"S_WAITCNT $simm16",
/* XXX: No VOP3 version of this instruction yet */
def V_CNDMASK_B32 : VOP2 <0x, (outs VReg_32:$dst),
- (ins VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1), "V_CNDMASK_B32",
+ (ins AllReg_32:$src0, VReg_32:$src1, VCCReg:$vcc), "V_CNDMASK_B32",
[(set (i32 VReg_32:$dst),
(select VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1))] > {
@@ -680,7 +680,7 @@ def V_CNDMASK_B32 : VOP2 <0x, (outs VReg_32:$dst),
//f32 pattern for V_CNDMASK_B32
def : Pat <
(f32 (select VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1)),
- (V_CNDMASK_B32 VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1)
+ (V_CNDMASK_B32 AllReg_32:$src0, VReg_32:$src1, VCCReg:$vcc)
>;
defm V_READLANE_B32 : VOP2_32 <0x0001, "V_READLANE_B32", []>;
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Mesa (master): radeon/llvm: Fix lowering of SI_V_CNDLT
Module: Mesa
Branch: master
Commit: 446d19c12a576e36c3da34ada01b708fcbc196c5
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=446d19c12a576e36c3da34ada01b708fcbc196c5
Author: Tom Stellard
Date: Tue Sep 4 11:20:01 2012 -0400
radeon/llvm: Fix lowering of SI_V_CNDLT
SREG_LIT_0 is a scalar register, so it can only be used in the
first argument of vector instructoins.
---
src/gallium/drivers/radeon/SIISelLowering.cpp |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeon/SIISelLowering.cpp
b/src/gallium/drivers/radeon/SIISelLowering.cpp
index a64e2a3..2c81673 100644
--- a/src/gallium/drivers/radeon/SIISelLowering.cpp
+++ b/src/gallium/drivers/radeon/SIISelLowering.cpp
@@ -235,10 +235,10 @@ void SITargetLowering::LowerSI_KIL(MachineInstr *MI,
MachineBasicBlock &BB,
void SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB,
MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const
{
- BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMP_LT_F32_e32),
+ BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CMP_GT_F32_e32),
AMDGPU::VCC)
- .addOperand(MI->getOperand(1))
- .addReg(AMDGPU::SREG_LIT_0);
+ .addReg(AMDGPU::SREG_LIT_0)
+ .addOperand(MI->getOperand(1));
BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CNDMASK_B32))
.addOperand(MI->getOperand(0))
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Mesa (9.0): xmlconfig: use __progname when building for Android
Module: Mesa
Branch: 9.0
Commit: 8cffec495c73f104819deab2bc5631abc1b36429
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8cffec495c73f104819deab2bc5631abc1b36429
Author: Tapani Pälli
Date: Tue Jun 5 16:04:14 2012 +0300
xmlconfig: use __progname when building for Android
__progname symbol and strrchr are available with bionic.
Signed-off-by: Tapani Pälli
Signed-off-by: Chad Versace
(cherry picked from commit 4d02b018f456c447e2c24ebd1460c27d6e5fb385)
---
src/mesa/drivers/dri/common/xmlconfig.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/src/mesa/drivers/dri/common/xmlconfig.c
b/src/mesa/drivers/dri/common/xmlconfig.c
index 6d1d5ec..039e98a 100644
--- a/src/mesa/drivers/dri/common/xmlconfig.c
+++ b/src/mesa/drivers/dri/common/xmlconfig.c
@@ -86,7 +86,7 @@ static const char *__getProgramName () {
#endif
#if !defined(GET_PROGRAM_NAME)
-#if defined(__OpenBSD__) || defined(NetBSD) || defined(__UCLIBC__)
+#if defined(__OpenBSD__) || defined(NetBSD) || defined(__UCLIBC__) ||
defined(ANDROID)
/* This is a hack. It's said to work on OpenBSD, NetBSD and GNU.
* Rogelio M.Serrano Jr. reported it's also working with UCLIBC. It's
* used as a last resort, if there is no documented facility available. */
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Mesa (9.0): android: fix liblog API changes
Module: Mesa
Branch: 9.0
Commit: 2a69de60bf9d8a4b35a115a0b1ac115301dd954d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2a69de60bf9d8a4b35a115a0b1ac115301dd954d
Author: Tapani Pälli
Date: Mon Aug 13 09:03:06 2012 +0300
android: fix liblog API changes
android logging macros changed their name in JellyBean.
Signed-off-by: Bruce E. Robertson
Signed-off-by: Tapani Pälli
Signed-off-by: Chad Versace
(cherry picked from commit 29d394b9ba4d7a23524fc6fba6da6e043085744b)
---
src/egl/drivers/dri2/platform_android.c | 17 ++---
1 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/src/egl/drivers/dri2/platform_android.c
b/src/egl/drivers/dri2/platform_android.c
index 66142cd..7e57295 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -660,18 +660,29 @@ droid_open_device(void)
return (fd >= 0) ? dup(fd) : -1;
}
+/* support versions < JellyBean */
+#ifndef ALOGW
+#define ALOGW LOGW
+#endif
+#ifndef ALOGD
+#define ALOGD LOGD
+#endif
+#ifndef ALOGI
+#define ALOGI LOGI
+#endif
+
static void
droid_log(EGLint level, const char *msg)
{
switch (level) {
case _EGL_DEBUG:
- LOGD("%s", msg);
+ ALOGD("%s", msg);
break;
case _EGL_INFO:
- LOGI("%s", msg);
+ ALOGI("%s", msg);
break;
case _EGL_WARNING:
- LOGW("%s", msg);
+ ALOGW("%s", msg);
break;
case _EGL_FATAL:
LOG_FATAL("%s", msg);
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Mesa (9.0): android: do not expose single buffered eglconfigs
Module: Mesa
Branch: 9.0
Commit: c7775e842bec815ede6badc35dbfe4991c183e3a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c7775e842bec815ede6badc35dbfe4991c183e3a
Author: Tapani Pälli
Date: Mon Aug 13 16:47:52 2012 +0300
android: do not expose single buffered eglconfigs
On Android we want to add only double buffered configs for visuals.
Earlier implementation set the SurfaceType as 0 for single buffered
configs but driver still exposed these configs that were not compatible
with any egl surface type. This caused Khronos conformance test runs to
fail on Android. This patch fixes the issue by skipping single buffered
configs earlier and not exposing them.
Signed-off-by: Tapani Pälli
Signed-off-by: Chad Versace
(cherry picked from commit d58ca43b809593314907694e744780ab9b28d590)
---
src/egl/drivers/dri2/platform_android.c | 19 ---
1 files changed, 8 insertions(+), 11 deletions(-)
diff --git a/src/egl/drivers/dri2/platform_android.c
b/src/egl/drivers/dri2/platform_android.c
index 7e57295..15bf054 100644
--- a/src/egl/drivers/dri2/platform_android.c
+++ b/src/egl/drivers/dri2/platform_android.c
@@ -500,6 +500,14 @@ droid_add_configs_for_visuals(_EGLDriver *drv, _EGLDisplay
*dpy)
for (j = 0; dri2_dpy->driver_configs[j]; j++) {
const EGLint surface_type = EGL_WINDOW_BIT | EGL_PBUFFER_BIT;
struct dri2_egl_config *dri2_conf;
+ unsigned int double_buffered = 0;
+
+ dri2_dpy->core->getConfigAttrib(dri2_dpy->driver_configs[j],
+__DRI_ATTRIB_DOUBLE_BUFFER, &double_buffered);
+
+ /* support only double buffered configs */
+ if (!double_buffered)
+continue;
dri2_conf = dri2_add_config(dpy, dri2_dpy->driver_configs[j],
count + 1, visuals[i].size, surface_type, NULL,
@@ -525,17 +533,6 @@ droid_add_configs_for_visuals(_EGLDriver *drv, _EGLDisplay
*dpy)
/* there is no front buffer so no OpenGL */
dri2_conf->base.RenderableType &= ~EGL_OPENGL_BIT;
dri2_conf->base.Conformant &= ~EGL_OPENGL_BIT;
-
- /*
- * We want to make sure GL_DRAW_BUFFER for windows or pbuffers is always
- * GL_BACK. For EGL configs that do not have a double DRI config, clear
- * the surface type.
- *
- * This is just to be on the safe side. dri2_add_config never sets
- * EGL_WINDOW_BIT or EGL_PBUFFER_BIT for such configs.
- */
- if (!dri2_conf->dri_double_config)
- dri2_conf->base.SurfaceType = 0;
}
return (count != 0);
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