Mesa (main): util/u_trace: Add json output

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 850ae76970dabec1fe9c53674e515f496914915d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=850ae76970dabec1fe9c53674e515f496914915d

Author: Danylo Piliaiev 
Date:   Wed May 11 12:29:52 2022 +0300

util/u_trace: Add json output

If we want to load the u_trace output somewhere for analysis it's much
easier to deal with json than to parse strings.

Signed-off-by: Danylo Piliaiev 
Reviewed-by: Lionel Landwerlin 
Part-of: 

---

 src/util/perf/u_trace.c  | 195 +++
 src/util/perf/u_trace.h  |   5 ++
 src/util/perf/u_trace.py |  30 +++
 src/util/perf/u_trace_priv.h |   1 +
 4 files changed, 216 insertions(+), 15 deletions(-)

diff --git a/src/util/perf/u_trace.c b/src/util/perf/u_trace.c
index 29c9c8c5652..ce2b3d411e6 100644
--- a/src/util/perf/u_trace.c
+++ b/src/util/perf/u_trace.c
@@ -108,6 +108,139 @@ struct u_trace_chunk {
bool free_flush_data;
 };
 
+struct u_trace_printer {
+   void (*start)(struct u_trace_context *utctx);
+   void (*end)(struct u_trace_context *utctx);
+   void (*start_of_frame)(struct u_trace_context *utctx);
+   void (*end_of_frame)(struct u_trace_context *utctx);
+   void (*start_of_batch)(struct u_trace_context *utctx);
+   void (*end_of_batch)(struct u_trace_context *utctx);
+   void (*event)(struct u_trace_context *utctx,
+ struct u_trace_chunk *chunk,
+ const struct u_trace_event *evt,
+ uint64_t ns, int32_t delta);
+};
+
+static void
+print_txt_start(struct u_trace_context *utctx)
+{
+
+}
+
+static void
+print_txt_end_of_frame(struct u_trace_context *utctx)
+{
+   fprintf(utctx->out, "END OF FRAME %u\n", utctx->frame_nr);
+}
+
+static void
+print_txt_start_of_batch(struct u_trace_context *utctx)
+{
+   fprintf(utctx->out, "+- NS -+ +-- Δ --+  +- MSG -\n");
+}
+
+static void
+print_txt_end_of_batch(struct u_trace_context *utctx)
+{
+   uint64_t elapsed = utctx->last_time_ns - utctx->first_time_ns;
+   fprintf(utctx->out, "ELAPSED: %"PRIu64" ns\n", elapsed);
+}
+
+static void
+print_txt_event(struct u_trace_context *utctx,
+struct u_trace_chunk *chunk,
+const struct u_trace_event *evt,
+uint64_t ns, int32_t delta)
+{
+   if (evt->tp->print) {
+  fprintf(utctx->out, "%016"PRIu64" %+9d: %s: ", ns, delta, evt->tp->name);
+  evt->tp->print(utctx->out, evt->payload);
+   } else {
+  fprintf(utctx->out, "%016"PRIu64" %+9d: %s\n", ns, delta, evt->tp->name);
+   }
+}
+
+static struct u_trace_printer txt_printer = {
+   .start = &print_txt_start,
+   .end = &print_txt_start,
+   .start_of_frame = &print_txt_start,
+   .end_of_frame = &print_txt_end_of_frame,
+   .start_of_batch = &print_txt_start_of_batch,
+   .end_of_batch = &print_txt_end_of_batch,
+   .event = &print_txt_event,
+};
+
+static void
+print_json_start(struct u_trace_context *utctx)
+{
+   fprintf(utctx->out, "[\n");
+}
+
+static void
+print_json_end(struct u_trace_context *utctx)
+{
+   fprintf(utctx->out, "\n]");
+}
+
+static void
+print_json_start_of_frame(struct u_trace_context *utctx)
+{
+   if (utctx->frame_nr != 0)
+  fprintf(utctx->out, ",\n");
+   fprintf(utctx->out, "{\n\"frame\": %u,\n", utctx->frame_nr);
+   fprintf(utctx->out, "\"batches\": [\n");
+}
+
+static void
+print_json_end_of_frame(struct u_trace_context *utctx)
+{
+   fprintf(utctx->out, "]\n}\n");
+   fflush(utctx->out);
+}
+
+static void
+print_json_start_of_batch(struct u_trace_context *utctx)
+{
+   if (utctx->batch_nr != 0)
+  fprintf(utctx->out, ",\n");
+   fprintf(utctx->out, "{\n\"events\": [\n");
+}
+
+static void
+print_json_end_of_batch(struct u_trace_context *utctx)
+{
+   uint64_t elapsed = utctx->last_time_ns - utctx->first_time_ns;
+   fprintf(utctx->out, "],\n");
+   fprintf(utctx->out, "\"duration_ns\": %"PRIu64"\n", elapsed);
+   fprintf(utctx->out, "}\n");
+}
+
+static void
+print_json_event(struct u_trace_context *utctx,
+ struct u_trace_chunk *chunk,
+ const struct u_trace_event *evt,
+ uint64_t ns, int32_t delta)
+{
+   if (utctx->event_nr != 0)
+  fprintf(utctx->out, ",\n");
+   fprintf(utctx->out, "{\n\"event\": \"%s\",\n", evt->tp->name);
+   fprintf(utctx->out, "\"time_ns\": \"%016"PRIu64"\",\n", ns);
+   fprintf(utctx->out, "\"params\": {");
+   if (evt->tp->print)
+  evt->tp->print_json(utctx->out, evt->payload);
+   fprintf(utctx->out, "}\n}\n");
+}
+
+static struct u_trace_printer json_printer = {
+   .start = print_json_start,
+   .end = print_json_end,
+   .start_of_frame = &print_json_start_of_frame,
+   .end_of_frame = &print_json_end_of_frame,
+   .start_of_batch = &print_json_start_of_batch,
+   .end_of_batch = &print_json_end_of_batch,
+   .event = &print_json_event,
+};
+
 static struct u_trace_payload_buf *
 u_trace_payload_buf_create(void)
 {
@@ -222,6 +355,7 @@ get_

Mesa (main): Revert "ci: Disable jobs to the Collabora lab"

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 0d8cbf551db482e6168a4353fe41e174749728a4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d8cbf551db482e6168a4353fe41e174749728a4

Author: Tomeu Vizoso 
Date:   Thu May 19 07:36:33 2022 +0200

Revert "ci: Disable jobs to the Collabora lab"

This reverts commit 224544dc33c60b933b379eef067058ad31ef7bae.

Work has finished and the lab is up and running.

Signed-off-by: Tomeu Vizoso 
Part-of: 

---

 .gitlab-ci.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 9614e087192..5fb25d37718 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -18,7 +18,7 @@ variables:
   # Individual CI farm status, set to "offline" to disable jobs
   # running on a particular CI farm (ie. for outages, etc):
   FD_FARM: "online"
-  COLLABORA_FARM: "offline"
+  COLLABORA_FARM: "online"
   MICROSOFT_FARM: "offline"
   LIMA_FARM: "online"
 

Mesa (main): radeonsi: save the fs constant buffer to the util blitter context

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 03bc7503d471dd2d2795a8f18a7212e98209a051
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=03bc7503d471dd2d2795a8f18a7212e98209a051

Author: Indrajit Kumar Das 
Date:   Fri May 13 17:11:51 2022 +0530

radeonsi: save the fs constant buffer to the util blitter context

Reviewed-by: Marek Olšák 
Part-of: 

---

 src/gallium/drivers/radeonsi/si_blit.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 8a65ad240e2..f46ffea7080 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -52,6 +52,10 @@ void si_blitter_begin(struct si_context *sctx, enum 
si_blitter_op op)
util_blitter_save_rasterizer(sctx->blitter, sctx->queued.named.rasterizer);
 
if (op & SI_SAVE_FRAGMENT_STATE) {
+  struct pipe_constant_buffer fs_cb = {};
+  si_get_pipe_constant_buffer(sctx, PIPE_SHADER_FRAGMENT, 0, &fs_cb);
+  util_blitter_save_fragment_constant_buffer_slot(sctx->blitter, &fs_cb);
+  pipe_resource_reference(&fs_cb.buffer, NULL);
   util_blitter_save_blend(sctx->blitter, sctx->queued.named.blend);
   util_blitter_save_depth_stencil_alpha(sctx->blitter, 
sctx->queued.named.dsa);
   util_blitter_save_stencil_ref(sctx->blitter, &sctx->stencil_ref.state);

Mesa (main): gallium/u_blitter: clear color buffers using color from a constant buffer

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 773a23eb6daa470766a537ea34891237b790c2e6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=773a23eb6daa470766a537ea34891237b790c2e6

Author: Indrajit Kumar Das 
Date:   Fri May 13 17:20:14 2022 +0530

gallium/u_blitter: clear color buffers using color from a constant buffer

Reviewed-by: Marek Olšák 
Part-of: 

---

 src/gallium/auxiliary/util/u_blitter.c| 44 +--
 src/gallium/auxiliary/util/u_simple_shaders.c | 25 +++
 src/gallium/auxiliary/util/u_simple_shaders.h |  3 ++
 3 files changed, 50 insertions(+), 22 deletions(-)

diff --git a/src/gallium/auxiliary/util/u_blitter.c 
b/src/gallium/auxiliary/util/u_blitter.c
index bea898edcae..f55c580fec7 100644
--- a/src/gallium/auxiliary/util/u_blitter.c
+++ b/src/gallium/auxiliary/util/u_blitter.c
@@ -76,7 +76,7 @@ struct blitter_context_priv
/* Fragment shaders. */
void *fs_empty;
void *fs_write_one_cbuf;
-   void *fs_write_all_cbufs;
+   void *fs_clear_all_cbufs;
 
/* FS which outputs a color from a texture where
 * the 1st index indicates the texture type / destination type,
@@ -467,18 +467,16 @@ static void bind_fs_write_one_cbuf(struct 
blitter_context_priv *ctx)
ctx->bind_fs_state(pipe, ctx->fs_write_one_cbuf);
 }
 
-static void bind_fs_write_all_cbufs(struct blitter_context_priv *ctx)
+static void bind_fs_clear_all_cbufs(struct blitter_context_priv *ctx)
 {
struct pipe_context *pipe = ctx->base.pipe;
 
-   if (!ctx->fs_write_all_cbufs) {
+   if (!ctx->fs_clear_all_cbufs) {
   assert(!ctx->cached_all_shaders);
-  ctx->fs_write_all_cbufs =
- util_make_fragment_passthrough_shader(pipe, TGSI_SEMANTIC_GENERIC,
-   TGSI_INTERPOLATE_CONSTANT, 
true);
+  ctx->fs_clear_all_cbufs = util_make_fs_clear_all_cbufs(pipe);
}
 
-   ctx->bind_fs_state(pipe, ctx->fs_write_all_cbufs);
+   ctx->bind_fs_state(pipe, ctx->fs_clear_all_cbufs);
 }
 
 void util_blitter_destroy(struct blitter_context *blitter)
@@ -576,8 +574,8 @@ void util_blitter_destroy(struct blitter_context *blitter)
   ctx->delete_fs_state(pipe, ctx->fs_empty);
if (ctx->fs_write_one_cbuf)
   ctx->delete_fs_state(pipe, ctx->fs_write_one_cbuf);
-   if (ctx->fs_write_all_cbufs)
-  ctx->delete_fs_state(pipe, ctx->fs_write_all_cbufs);
+   if (ctx->fs_clear_all_cbufs)
+  ctx->delete_fs_state(pipe, ctx->fs_clear_all_cbufs);
 
for (i = 0; i < ARRAY_SIZE(ctx->fs_stencil_blit_fallback); ++i)
   if (ctx->fs_stencil_blit_fallback[i])
@@ -1354,9 +1352,7 @@ void util_blitter_cache_all_shaders(struct 
blitter_context *blitter)
   util_make_fragment_passthrough_shader(pipe, TGSI_SEMANTIC_GENERIC,
 TGSI_INTERPOLATE_CONSTANT, false);
 
-   ctx->fs_write_all_cbufs =
-  util_make_fragment_passthrough_shader(pipe, TGSI_SEMANTIC_GENERIC,
-TGSI_INTERPOLATE_CONSTANT, true);
+   ctx->fs_clear_all_cbufs = util_make_fs_clear_all_cbufs(pipe);
 
ctx->cached_all_shaders = true;
 }
@@ -1556,17 +1552,20 @@ static void util_blitter_clear_custom(struct 
blitter_context *blitter,
sr.ref_value[0] = stencil & 0xff;
pipe->set_stencil_ref(pipe, sr);
 
-   union blitter_attrib attrib;
-   memcpy(attrib.color, color->ui, sizeof(color->ui));
-
bool pass_generic = (clear_buffers & PIPE_CLEAR_COLOR) != 0;
-   enum blitter_attrib_type type = pass_generic ? UTIL_BLITTER_ATTRIB_COLOR :
-  UTIL_BLITTER_ATTRIB_NONE;
+   enum blitter_attrib_type type = UTIL_BLITTER_ATTRIB_NONE;
 
-   if (pass_generic)
-  bind_fs_write_all_cbufs(ctx);
-   else
+   if (pass_generic) {
+  struct pipe_constant_buffer cb = {
+ .user_buffer = color->f,
+ .buffer_size = 4 * sizeof(float),
+  };
+  pipe->set_constant_buffer(pipe, PIPE_SHADER_FRAGMENT, blitter->cb_slot,
+false, &cb);
+  bind_fs_clear_all_cbufs(ctx);
+   } else {
   bind_fs_empty(ctx);
+   }
 
if (num_layers > 1 && ctx->has_layered) {
   blitter_get_vs_func get_vs = get_vs_layered;
@@ -1574,7 +1573,7 @@ static void util_blitter_clear_custom(struct 
blitter_context *blitter,
   blitter_set_common_draw_rect_state(ctx, false, msaa);
   blitter->draw_rectangle(blitter, ctx->velem_state, get_vs,
   0, 0, width, height,
-  (float) depth, num_layers, type, &attrib);
+  (float) depth, num_layers, type, NULL);
} else {
   blitter_get_vs_func get_vs;
 
@@ -1586,11 +1585,12 @@ static void util_blitter_clear_custom(struct 
blitter_context *blitter,
   blitter_set_common_draw_rect_state(ctx, false, msaa);
   blitter->draw_rectangle(blitter, ctx->velem_state, get_vs,
   0, 0, width, height,
-   

Mesa (main): mesa/st: add nir shader to clear color buffers using constant value

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 2204bf509d6d85ac47d029809bb004a03fd12a9a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2204bf509d6d85ac47d029809bb004a03fd12a9a

Author: Indrajit Kumar Das 
Date:   Fri May 13 17:21:20 2022 +0530

mesa/st: add nir shader to clear color buffers using constant value

v2: use load_uniform instead of load_ubo to fix vc4

Reviewed-by: Marek Olšák 
Part-of: 

---

 src/mesa/state_tracker/st_nir.h  |  4 
 src/mesa/state_tracker/st_nir_builtins.c | 32 
 2 files changed, 36 insertions(+)

diff --git a/src/mesa/state_tracker/st_nir.h b/src/mesa/state_tracker/st_nir.h
index 58003d82b60..28fa476589b 100644
--- a/src/mesa/state_tracker/st_nir.h
+++ b/src/mesa/state_tracker/st_nir.h
@@ -74,6 +74,10 @@ st_nir_make_passthrough_shader(struct st_context *st,
unsigned sysval_mask);
 void
 st_nir_add_point_size(struct nir_shader *nir);
+
+struct pipe_shader_state *
+st_nir_make_clearcolor_shader(struct st_context *st);
+
 #ifdef __cplusplus
 }
 #endif
diff --git a/src/mesa/state_tracker/st_nir_builtins.c 
b/src/mesa/state_tracker/st_nir_builtins.c
index 06959dcd078..bfbe0a939b8 100644
--- a/src/mesa/state_tracker/st_nir_builtins.c
+++ b/src/mesa/state_tracker/st_nir_builtins.c
@@ -131,3 +131,35 @@ st_nir_make_passthrough_shader(struct st_context *st,
 
return st_nir_finish_builtin_shader(st, b.shader);
 }
+
+/**
+ * Make a simple shader that reads color value from a constant buffer
+ * and uses it to clear all color buffers.
+ */
+struct pipe_shader_state *
+st_nir_make_clearcolor_shader(struct st_context *st)
+{
+   const nir_shader_compiler_options *options =
+  st_get_nir_compiler_options(st, MESA_SHADER_FRAGMENT);
+
+   nir_builder b = nir_builder_init_simple_shader(MESA_SHADER_FRAGMENT, 
options,
+  "clear color FS");
+   b.shader->info.num_ubos = 1;
+   b.shader->num_outputs = 1;
+   b.shader->num_uniforms = 1;
+
+   /* Read clear color from constant buffer */
+   nir_ssa_def *clear_color = nir_load_uniform(&b, 4, 32, nir_imm_int(&b,0),
+   .range = 16,
+   .dest_type = nir_type_float32);
+
+   nir_variable *color_out =
+  nir_variable_create(b.shader, nir_var_shader_out, glsl_vec_type(4),
+ "outcolor");
+   color_out->data.location = FRAG_RESULT_COLOR;
+
+   /* Write out the color */
+   nir_store_var(&b, color_out, clear_color, 0xf);
+
+   return st_nir_finish_builtin_shader(st, b.shader);
+}

Mesa (main): mesa/st: clear color buffers using color from a constant buffer

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: c6bb8961a89f81749b73efd92419b7a793327cf3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c6bb8961a89f81749b73efd92419b7a793327cf3

Author: Indrajit Kumar Das 
Date:   Fri May 13 17:22:15 2022 +0530

mesa/st: clear color buffers using color from a constant buffer

v2: fixed GLCTS failures (mareko)

Reviewed-by: Marek Olšák 
Part-of: 

---

 src/mesa/state_tracker/st_cb_clear.c | 41 
 1 file changed, 18 insertions(+), 23 deletions(-)

diff --git a/src/mesa/state_tracker/st_cb_clear.c 
b/src/mesa/state_tracker/st_cb_clear.c
index 75228555923..f24ddb9a288 100644
--- a/src/mesa/state_tracker/st_cb_clear.c
+++ b/src/mesa/state_tracker/st_cb_clear.c
@@ -103,56 +103,49 @@ st_destroy_clear(struct st_context *st)
 
 
 /**
- * Helper function to set the fragment shaders.
+ * Helper function to set the clear color fragment shader.
  */
-static inline void
-set_fragment_shader(struct st_context *st)
+static void
+set_clearcolor_fs(struct st_context *st, union pipe_color_union *color)
 {
struct pipe_screen *pscreen = st->screen;
bool use_nir = PIPE_SHADER_IR_NIR ==
   pscreen->get_shader_param(pscreen, PIPE_SHADER_VERTEX,
 PIPE_SHADER_CAP_PREFERRED_IR);
+   struct pipe_constant_buffer cb = {
+  .user_buffer = color->f,
+  .buffer_size = 4 * sizeof(float),
+   };
+   st->pipe->set_constant_buffer(st->pipe, PIPE_SHADER_FRAGMENT, 0,
+false, &cb);
 
if (!st->clear.fs) {
   if (use_nir) {
- unsigned inputs[] = { VARYING_SLOT_VAR0 };
- unsigned outputs[] = { FRAG_RESULT_COLOR };
- unsigned interpolation[] = { INTERP_MODE_FLAT };
- st->clear.fs = st_nir_make_passthrough_shader(st, "clear FS",
-   MESA_SHADER_FRAGMENT,
-   1, inputs, outputs,
-   interpolation, 0);
+ st->clear.fs = st_nir_make_clearcolor_shader(st);
   } else {
- st->clear.fs =
-util_make_fragment_passthrough_shader(st->pipe,
-  TGSI_SEMANTIC_GENERIC,
-  TGSI_INTERPOLATE_CONSTANT,
-  TRUE);
+ st->clear.fs = util_make_fs_clear_all_cbufs(st->pipe);
   }
}
 
cso_set_fragment_shader_handle(st->cso_context, st->clear.fs);
 }
 
-
 static void *
 make_nir_clear_vertex_shader(struct st_context *st, bool layered)
 {
const char *shader_name = layered ? "layered clear VS" : "clear VS";
unsigned inputs[] = {
   VERT_ATTRIB_POS,
-  VERT_ATTRIB_GENERIC0,
   SYSTEM_VALUE_INSTANCE_ID,
};
unsigned outputs[] = {
   VARYING_SLOT_POS,
-  VARYING_SLOT_VAR0,
   VARYING_SLOT_LAYER
};
 
return st_nir_make_passthrough_shader(st, shader_name, MESA_SHADER_VERTEX,
- layered ? 3 : 2, inputs, outputs,
- NULL, (1 << 2));
+ layered ? 2 : 1, inputs, outputs,
+ NULL, (1 << 1));
 }
 
 
@@ -320,7 +313,7 @@ clear_with_quad(struct gl_context *ctx, unsigned 
clear_buffers)
   cso_set_depth_stencil_alpha(cso, &depth_stencil);
}
 
-   st->util_velems.count = 2;
+   st->util_velems.count = 1;
cso_set_vertex_elements(cso, &st->util_velems);
 
cso_set_stream_outputs(cso, 0, NULL, NULL);
@@ -333,7 +326,8 @@ clear_with_quad(struct gl_context *ctx, unsigned 
clear_buffers)
cso_set_viewport_dims(st->cso_context, fb_width, fb_height,
  _mesa_fb_orientation(fb) == Y_0_TOP);
 
-   set_fragment_shader(st);
+   /* Set constant buffer */
+   set_clearcolor_fs(st, (union pipe_color_union*)&ctx->Color.ClearColor);
cso_set_tessctrl_shader_handle(cso, NULL);
cso_set_tesseval_shader_handle(cso, NULL);
 
@@ -361,7 +355,8 @@ clear_with_quad(struct gl_context *ctx, unsigned 
clear_buffers)
/* Restore pipe state */
cso_restore_state(cso, 0);
ctx->Array.NewVertexElements = true;
-   st->dirty |= ST_NEW_VERTEX_ARRAYS;
+   st->dirty |= ST_NEW_VERTEX_ARRAYS |
+ST_NEW_FS_CONSTANTS;
 }
 
 

Mesa (main): amd: rename fishes to Navi21, Navi22, Navi23, Navi24, and Rembrandt

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 244305493240ee9e0fc08a9b3da806d47a5cf257
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=244305493240ee9e0fc08a9b3da806d47a5cf257

Author: Marek Olšák 
Date:   Thu May 19 05:37:09 2022 -0400

amd: rename fishes to Navi21, Navi22, Navi23, Navi24, and Rembrandt

Reviewed-by: Mihai Preda 
Acked-by: Timur Kristóf 
Reviewed-by: Samuel Pitoiset 
Acked-by: Martin Roukala 
Part-of: 

---

 src/amd/addrlib/src/amdgpu_asic_addr.h | 24 ++---
 src/amd/addrlib/src/core/addrlib.cpp   |  2 +-
 src/amd/addrlib/src/gfx10/gfx10addrlib.cpp | 12 +++
 src/amd/ci/gitlab-ci.yml   |  6 ++--
 ...lid-aco-fails.txt => radv-navi21-aco-fails.txt} |  0
 ...d-aco-flakes.txt => radv-navi21-aco-flakes.txt} |  0
 src/amd/ci/radv-skips.txt  |  2 +-
 src/amd/common/ac_gpu_info.c   | 40 +++---
 src/amd/common/ac_surface.c|  4 +--
 src/amd/common/ac_surface_test_common.h|  2 +-
 src/amd/common/amd_family.c| 20 +--
 src/amd/common/amd_family.h| 10 +++---
 src/amd/compiler/tests/helpers.cpp |  2 +-
 src/amd/llvm/ac_llvm_util.c| 10 +++---
 src/amd/vulkan/radv_cmd_buffer.c   |  2 +-
 src/amd/vulkan/radv_device.c   | 10 +++---
 src/amd/vulkan/radv_pipeline.c |  4 +--
 src/amd/vulkan/radv_shader.c   |  2 +-
 src/amd/vulkan/winsys/null/radv_null_winsys.c  | 10 +++---
 ...na_cichlid-fail.csv => gfx10_3-navi21-fail.csv} |  0
 src/gallium/drivers/radeonsi/gfx10_shader_ngg.c|  2 +-
 src/gallium/drivers/radeonsi/radeon_vcn_dec.c  | 16 -
 src/gallium/drivers/radeonsi/radeon_vcn_enc.c  |  2 +-
 src/gallium/drivers/radeonsi/si_get.c  |  6 ++--
 src/gallium/drivers/radeonsi/si_state_shaders.cpp  |  4 +--
 src/gallium/drivers/zink/ci/zink-radv-skips.txt|  2 +-
 src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c  |  2 +-
 27 files changed, 98 insertions(+), 98 deletions(-)

diff --git a/src/amd/addrlib/src/amdgpu_asic_addr.h 
b/src/amd/addrlib/src/amdgpu_asic_addr.h
index 5226585620e..28faf83e7e1 100644
--- a/src/amd/addrlib/src/amdgpu_asic_addr.h
+++ b/src/amd/addrlib/src/amdgpu_asic_addr.h
@@ -46,7 +46,7 @@
 #define FAMILY_VGH 0x90
 #define FAMILY_GFX1100 0x91
 #define FAMILY_GFX1103 0x94
-#define FAMILY_YC  0x92
+#define FAMILY_RMB 0x92
 #define FAMILY_GC_10_3_6  0x95
 #define FAMILY_GC_10_3_7  0x97
 
@@ -62,7 +62,7 @@
 #define FAMILY_IS_AI(f)  FAMILY_IS(f, AI)
 #define FAMILY_IS_RV(f)  FAMILY_IS(f, RV)
 #define FAMILY_IS_NV(f)  FAMILY_IS(f, NV)
-#define FAMILY_IS_YC(f)  FAMILY_IS(f, YC)
+#define FAMILY_IS_RMB(f) FAMILY_IS(f, RMB)
 #define FAMILY_IS_GFX1100(f) FAMILY_IS(f, GFX1100)
 #define FAMILY_IS_GFX1103(f) FAMILY_IS(f, GFX1103)
 
@@ -107,10 +107,10 @@
 #define AMDGPU_NAVI10_RANGE 0x01, 0x0A
 #define AMDGPU_NAVI12_RANGE 0x0A, 0x14
 #define AMDGPU_NAVI14_RANGE 0x14, 0x28
-#define AMDGPU_SIENNA_CICHLID_RANGE 0x28, 0x32
-#define AMDGPU_NAVY_FLOUNDER_RANGE  0x32, 0x3C
-#define AMDGPU_DIMGREY_CAVEFISH_RANGE   0x3C, 0x46
-#define AMDGPU_BEIGE_GOBY_RANGE 0x46, 0x50
+#define AMDGPU_NAVI21_RANGE 0x28, 0x32
+#define AMDGPU_NAVI22_RANGE 0x32, 0x3C
+#define AMDGPU_NAVI23_RANGE 0x3C, 0x46
+#define AMDGPU_NAVI24_RANGE 0x46, 0x50
 
 #define AMDGPU_VANGOGH_RANGE0x01, 0xFF
 
@@ -120,7 +120,7 @@
 
 #define AMDGPU_GFX1103_RANGE0x01, 0xFF
 
-#define AMDGPU_YELLOW_CARP_RANGE 0x01, 0xFF
+#define AMDGPU_REMBRANDT_RANGE  0x01, 0xFF
 
 #define AMDGPU_GFX1036_RANGE0x01, 0xFF
 
@@ -177,13 +177,13 @@
 
 #define ASICREV_IS_NAVI14_M(r) ASICREV_IS(r, NAVI14)
 
-#define ASICREV_IS_SIENNA_CICHLID(r)   ASICREV_IS(r, SIENNA_CICHLID)
+#define ASICREV_IS_NAVI21_M(r) ASICREV_IS(r, NAVI21)
 
-#define ASICREV_IS_NAVY_FLOUNDER(r)ASICREV_IS(r, NAVY_FLOUNDER)
+#define ASICREV_IS_NAVI22_P(r) ASICREV_IS(r, NAVI22)
 
-#define ASICREV_IS_DIMGREY_CAVEFISH(r) ASICREV_IS(r, DIMGREY_CAVEFISH)
+#define ASICREV_IS_NAVI23_P(r) ASICREV_IS(r, NAVI23)
 
-#define ASICREV_IS_BEIGE_GOBY(r)   ASICREV_IS(r, BEIGE_GOBY)
+#define ASICREV_IS_NAVI24_P(r) ASICREV_IS(r, NAVI24)
 
 #define ASICREV_IS_VANGOGH(r)  ASICREV_IS(r, VANGOGH)
 
@@ -192,7 +192,7 @@
 #define ASICREV_IS_GFX1102(r)  ASICREV_IS(r, GFX1102)
 #define ASICREV_IS_GFX1103(r)  ASICREV_IS(r, GFX1103)
 
-#define ASICREV_IS_YELLOW_CARP(r)  ASICREV_IS(r, YELLOW_CARP)
+#define ASICREV_IS_REMBRANDT(r)ASICREV_IS(r, REMBRANDT)
 
 #define ASICREV_IS_GFX1036(r)  ASICREV_IS(r, GFX1036)
 
diff --git a/src/amd/addrlib/src/core/addrlib.cpp 
b/src/amd/addrlib/src/core/addrlib.cpp
index 674acc0a52a..4594271f998 100644
---

Mesa (main): radeonsi: wait for PS idle in si_set_framebuffer_state

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: cf9ee6d43203803dfad3780582da0872ac534e27
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cf9ee6d43203803dfad3780582da0872ac534e27

Author: Pierre-Eric Pelloux-Prayer 
Date:   Mon May 16 21:06:36 2022 +0200

radeonsi: wait for PS idle in si_set_framebuffer_state

This is needed to avoid write-after-read hazards in
texture -> render transitions.

This fixes fbo-depth tests that were flaky on GPUs (at
least sienna_cichlid and vega20).

Reviewed-by: Mihai Preda 
Reviewed-by: Marek Olšák 
Part-of: 

---

 src/gallium/drivers/radeonsi/ci/gfx9-vega20-flakes.csv | 12 
 src/gallium/drivers/radeonsi/si_state.c|  5 -
 2 files changed, 4 insertions(+), 13 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/ci/gfx9-vega20-flakes.csv 
b/src/gallium/drivers/radeonsi/ci/gfx9-vega20-flakes.csv
index bddcf453ee6..ce8429c79ad 100644
--- a/src/gallium/drivers/radeonsi/ci/gfx9-vega20-flakes.csv
+++ b/src/gallium/drivers/radeonsi/ci/gfx9-vega20-flakes.csv
@@ -6,27 +6,15 @@ spec@!opengl 1.1@depthstencil-default_fb-blit
 spec@!opengl 1.1@depthstencil-default_fb-copypixels samples=2
 spec@!opengl 1.1@depthstencil-default_fb-copypixels samples=4
 spec@!opengl 1.1@depthstencil-default_fb-copypixels
-spec@arb_depth_buffer_float@fbo-depth-gl_depth32f_stencil8-blit
-spec@arb_depth_buffer_float@fbo-depth-gl_depth32f_stencil8-copypixels
-spec@arb_depth_buffer_float@fbo-depth-gl_depth_component32f-blit
-spec@arb_depth_buffer_float@fbo-depth-gl_depth_component32f-copypixels
 spec@arb_depth_buffer_float@fbo-depthstencil-gl_depth32f_stencil8-blit
 spec@arb_depth_buffer_float@fbo-depthstencil-gl_depth32f_stencil8-copypixels
 spec@arb_depth_buffer_float@fbo-stencil-gl_depth32f_stencil8-blit
-spec@arb_depth_texture@fbo-depth-gl_depth_component16-blit
-spec@arb_depth_texture@fbo-depth-gl_depth_component16-copypixels
-spec@arb_depth_texture@fbo-depth-gl_depth_component24-blit
-spec@arb_depth_texture@fbo-depth-gl_depth_component24-copypixels
-spec@arb_depth_texture@fbo-depth-gl_depth_component32-blit
-spec@arb_depth_texture@fbo-depth-gl_depth_component32-copypixels
 spec@arb_texture_stencil8@fbo-stencil-blit
 spec@ext_framebuffer_object@fbo-stencil-gl_stencil_index1-blit
 spec@ext_framebuffer_object@fbo-stencil-gl_stencil_index16-copypixels
 spec@ext_framebuffer_object@fbo-stencil-gl_stencil_index4-blit
 spec@ext_framebuffer_object@fbo-stencil-gl_stencil_index4-copypixels
 spec@ext_framebuffer_object@fbo-stencil-gl_stencil_index8-blit
-spec@ext_packed_depth_stencil@fbo-depth-gl_depth24_stencil8-blit
-spec@ext_packed_depth_stencil@fbo-depth-gl_depth24_stencil8-copypixels
 spec@ext_packed_depth_stencil@fbo-depthstencil-gl_depth24_stencil8-blit
 spec@ext_packed_depth_stencil@fbo-depthstencil-gl_depth24_stencil8-copypixels
 spec@ext_packed_depth_stencil@fbo-stencil-gl_depth24_stencil8-copypixels
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index a91145a836c..3cf7fc2f214 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2971,6 +2971,9 @@ static void si_set_framebuffer_state(struct pipe_context 
*ctx,
 * - FB write -> shader read
 * - shader write -> FB read
 *
+* Wait for draws because of possible transitions:
+* - texture -> render (eg: glBlitFramebuffer(with src=dst) then glDraw*)
+*
 * DB caches are flushed on demand (using si_decompress_textures).
 *
 * When MSAA is enabled, CB and TC caches are flushed on demand
@@ -2986,7 +2989,7 @@ static void si_set_framebuffer_state(struct pipe_context 
*ctx,
  sctx->framebuffer.all_DCC_pipe_aligned);
}
 
-   sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
+   sctx->flags |= SI_CONTEXT_CS_PARTIAL_FLUSH | SI_CONTEXT_PS_PARTIAL_FLUSH;
 
/* u_blitter doesn't invoke depth decompression when it does multiple
 * blits in a row, but the only case when it matters for DB is when

Mesa (main): nir: call nir_metadata_preserve in nir_io_add_const_offset_to_base

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: f10d4bf963a4ba7ac5caafa809281b31bed13b9f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f10d4bf963a4ba7ac5caafa809281b31bed13b9f

Author: Rhys Perry 
Date:   Wed Aug 18 14:19:32 2021 +0100

nir: call nir_metadata_preserve in nir_io_add_const_offset_to_base

This is necessary to use this pass with the NIR_PASS() macro.

Signed-off-by: Rhys Perry 
Reviewed-by: Samuel Pitoiset 
Part-of: 

---

 src/compiler/nir/nir_lower_io.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir_lower_io.c b/src/compiler/nir/nir_lower_io.c
index d7aaad6af8c..5e3b866ff20 100644
--- a/src/compiler/nir/nir_lower_io.c
+++ b/src/compiler/nir/nir_lower_io.c
@@ -2827,11 +2827,17 @@ nir_io_add_const_offset_to_base(nir_shader *nir, 
nir_variable_mode modes)
 
nir_foreach_function(f, nir) {
   if (f->impl) {
+ bool impl_progress = false;
  nir_builder b;
  nir_builder_init(&b, f->impl);
  nir_foreach_block(block, f->impl) {
-progress |= add_const_offset_to_base_block(block, &b, modes);
+impl_progress |= add_const_offset_to_base_block(block, &b, modes);
  }
+ progress |= impl_progress;
+ if (impl_progress)
+nir_metadata_preserve(f->impl, nir_metadata_block_index | 
nir_metadata_dominance);
+ else
+nir_metadata_preserve(f->impl, nir_metadata_all);
   }
}
 

Mesa (main): radv: add missing NIR_PASS() and switch from NIR_PASS_V()

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 75c80be484d19d9b54939d0d4bff78959e9d10bc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=75c80be484d19d9b54939d0d4bff78959e9d10bc

Author: Rhys Perry 
Date:   Wed Aug 18 13:50:49 2021 +0100

radv: add missing NIR_PASS() and switch from NIR_PASS_V()

Unlike NIR_PASS_V(), NIR_PASS() can skip printing the shader when
NIR_DEBUG=print.

Signed-off-by: Rhys Perry 
Reviewed-by: Samuel Pitoiset 
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5244
Part-of: 

---

 src/amd/common/ac_nir.c   |   2 +-
 src/amd/vulkan/radv_pipeline.c| 145 +---
 src/amd/vulkan/radv_pipeline_rt.c |  22 ++--
 src/amd/vulkan/radv_shader.c  | 231 ++
 4 files changed, 201 insertions(+), 199 deletions(-)

diff --git a/src/amd/common/ac_nir.c b/src/amd/common/ac_nir.c
index c2f2d66ba54..6c8db43c516 100644
--- a/src/amd/common/ac_nir.c
+++ b/src/amd/common/ac_nir.c
@@ -74,6 +74,6 @@ ac_nir_lower_indirect_derefs(nir_shader *shader,
 */
indirect_mask |= nir_var_function_temp;
 
-   progress |= nir_lower_indirect_derefs(shader, indirect_mask, UINT32_MAX);
+   NIR_PASS(progress, shader, nir_lower_indirect_derefs, indirect_mask, 
UINT32_MAX);
return progress;
 }
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 1fb2fdc2116..71760293c09 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2840,18 +2840,20 @@ radv_link_shaders(struct radv_pipeline *pipeline,
  if (ordered_shaders[i]->info.stage != last)
 mask = mask | nir_var_shader_out;
 
- if (nir_lower_io_to_scalar_early(ordered_shaders[i], mask)) {
+ bool progress = false;
+ NIR_PASS(progress, ordered_shaders[i], nir_lower_io_to_scalar_early, 
mask);
+ if (progress) {
 /* Optimize the new vector code and then remove dead vars */
-nir_copy_prop(ordered_shaders[i]);
-nir_opt_shrink_vectors(ordered_shaders[i]);
+NIR_PASS(_, ordered_shaders[i], nir_copy_prop);
+NIR_PASS(_, ordered_shaders[i], nir_opt_shrink_vectors);
 
 if (ordered_shaders[i]->info.stage != last) {
/* Optimize swizzled movs of load_const for
 * nir_link_opt_varyings's constant propagation
 */
-   nir_opt_constant_folding(ordered_shaders[i]);
+   NIR_PASS(_, ordered_shaders[i], nir_opt_constant_folding);
/* For nir_link_opt_varyings's duplicate input opt */
-   nir_opt_cse(ordered_shaders[i]);
+   NIR_PASS(_, ordered_shaders[i], nir_opt_cse);
 }
 
 /* Run copy-propagation to help remove dead
@@ -2863,12 +2865,11 @@ radv_link_shaders(struct radv_pipeline *pipeline,
  * not have worked because the outputs were vector.
  */
 if (ordered_shaders[i]->info.stage == MESA_SHADER_TESS_CTRL)
-   nir_opt_copy_prop_vars(ordered_shaders[i]);
+   NIR_PASS(_, ordered_shaders[i], nir_opt_copy_prop_vars);
 
-nir_opt_dce(ordered_shaders[i]);
-nir_remove_dead_variables(
-   ordered_shaders[i], nir_var_function_temp | nir_var_shader_in | 
nir_var_shader_out,
-   NULL);
+NIR_PASS(_, ordered_shaders[i], nir_opt_dce);
+NIR_PASS(_, ordered_shaders[i], nir_remove_dead_variables,
+ nir_var_function_temp | nir_var_shader_in | 
nir_var_shader_out, NULL);
  }
   }
}
@@ -2903,9 +2904,10 @@ radv_link_shaders(struct radv_pipeline *pipeline,
}
 }
 if (fixup_derefs) {
-   nir_fixup_deref_modes(ordered_shaders[i]);
-   nir_remove_dead_variables(ordered_shaders[i], 
nir_var_shader_temp, NULL);
-   nir_opt_dce(ordered_shaders[i]);
+   NIR_PASS_V(ordered_shaders[i], nir_fixup_deref_modes);
+   NIR_PASS(_, ordered_shaders[i], nir_remove_dead_variables, 
nir_var_shader_temp,
+NULL);
+   NIR_PASS(_, ordered_shaders[i], nir_opt_dce);
 }
 continue;
  }
@@ -2935,9 +2937,9 @@ radv_link_shaders(struct radv_pipeline *pipeline,
 psiz_var->data.mode = nir_var_shader_temp;
 
 info->outputs_written &= ~VARYING_BIT_PSIZ;
-nir_fixup_deref_modes(ordered_shaders[i]);
-nir_remove_dead_variables(ordered_shaders[i], nir_var_shader_temp, 
NULL);
-nir_opt_dce(ordered_shaders[i]);
+NIR_PASS_V(ordered_shaders[i], nir_fixup_deref_modes);
+NIR_PASS(_, ordered_shaders[i], nir_remove_dead_variables, 
nir_var_shader_temp, NULL);
+NIR_PASS(_, ordered_shaders[i], nir_opt_dce);
  }
   }
}
@@ -2946,7 +2948,7 @@ radv_link_shaders(struct radv_pipeli

Mesa (main): radv: validate shaders after linking passes

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 1e710f7a2c6f9ce719e05a71eca12eacbdfc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1e710f7a2c6f9ce719e05a71eca12eacbdfc

Author: Rhys Perry 
Date:   Wed Aug 18 14:07:42 2021 +0100

radv: validate shaders after linking passes

Signed-off-by: Rhys Perry 
Reviewed-by: Samuel Pitoiset 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5244
Part-of: 

---

 src/amd/vulkan/radv_pipeline.c | 7 +++
 1 file changed, 7 insertions(+)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 71760293c09..e8db770eede 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2829,6 +2829,8 @@ radv_link_shaders(struct radv_pipeline *pipeline,
 
   for (int i = 1; i < shader_count; ++i) {
  nir_lower_io_arrays_to_elements(ordered_shaders[i], ordered_shaders[i 
- 1]);
+ nir_validate_shader(ordered_shaders[i], "after 
nir_lower_io_arrays_to_elements");
+ nir_validate_shader(ordered_shaders[i - 1], "after 
nir_lower_io_arrays_to_elements");
   }
 
   for (int i = 0; i < shader_count; ++i) {
@@ -2961,6 +2963,9 @@ radv_link_shaders(struct radv_pipeline *pipeline,
 
for (int i = 1; !optimize_conservatively && (i < shader_count); ++i) {
   if (nir_link_opt_varyings(ordered_shaders[i], ordered_shaders[i - 1])) {
+ nir_validate_shader(ordered_shaders[i], "after 
nir_link_opt_varyings");
+ nir_validate_shader(ordered_shaders[i - 1], "after 
nir_link_opt_varyings");
+
  NIR_PASS(_, ordered_shaders[i - 1], nir_opt_constant_folding);
  NIR_PASS(_, ordered_shaders[i - 1], nir_opt_algebraic);
  NIR_PASS(_, ordered_shaders[i - 1], nir_opt_dce);
@@ -2972,6 +2977,8 @@ radv_link_shaders(struct radv_pipeline *pipeline,
   bool progress = nir_remove_unused_varyings(ordered_shaders[i], 
ordered_shaders[i - 1]);
 
   nir_compact_varyings(ordered_shaders[i], ordered_shaders[i - 1], true);
+  nir_validate_shader(ordered_shaders[i], "after nir_compact_varyings");
+  nir_validate_shader(ordered_shaders[i - 1], "after 
nir_compact_varyings");
   if (ordered_shaders[i]->info.stage == MESA_SHADER_MESH) {
  /* nir_compact_varyings can change the location of per-vertex and 
per-primitive outputs */
  nir_shader_gather_info(ordered_shaders[i], 
nir_shader_get_entrypoint(ordered_shaders[i]));

Mesa (main): nir: call nir_metadata_preserve in nir_vectorize_tess_levels

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 3eed871f41fd7d590c57c684ca841a61513b7b8d
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3eed871f41fd7d590c57c684ca841a61513b7b8d

Author: Rhys Perry 
Date:   Wed Aug 18 14:24:50 2021 +0100

nir: call nir_metadata_preserve in nir_vectorize_tess_levels

This is necessary to use this pass with the NIR_PASS() macro.

Signed-off-by: Rhys Perry 
Reviewed-by: Samuel Pitoiset 
Part-of: 

---

 src/compiler/nir/nir_lower_io_to_vector.c | 5 +
 1 file changed, 5 insertions(+)

diff --git a/src/compiler/nir/nir_lower_io_to_vector.c 
b/src/compiler/nir/nir_lower_io_to_vector.c
index e49fda5d587..e17f6ddb158 100644
--- a/src/compiler/nir/nir_lower_io_to_vector.c
+++ b/src/compiler/nir/nir_lower_io_to_vector.c
@@ -677,6 +677,11 @@ nir_vectorize_tess_levels_impl(nir_function_impl *impl)
   }
}
 
+   if (progress)
+  nir_metadata_preserve(impl, nir_metadata_block_index | 
nir_metadata_dominance);
+   else
+  nir_metadata_preserve(impl, nir_metadata_all);
+
return progress;
 }
 

Mesa (main): nir: print file when validation fails

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 0d9ead8ca24f38966490c51dfc57e237e40c7af3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0d9ead8ca24f38966490c51dfc57e237e40c7af3

Author: Rhys Perry 
Date:   Wed Aug 18 14:18:15 2021 +0100

nir: print file when validation fails

This should make it clear whether a validation failure happens in RADV or
zink.

Signed-off-by: Rhys Perry 
Reviewed-by: Samuel Pitoiset 
Part-of: 

---

 src/compiler/nir/nir.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 1d70f7f66f2..93b6b39065a 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -4347,7 +4347,7 @@ static inline bool should_print_nir(UNUSED nir_shader 
*shader) { return false; }
if (should_print_nir(nir))\
   printf("%s\n", #pass); \
if (pass(nir, ##__VA_ARGS__)) {   \
-  nir_validate_shader(nir, "after " #pass);  \
+  nir_validate_shader(nir, "after " #pass " in " __FILE__);  \
   UNUSED bool _; \
   progress = true;   \
   if (should_print_nir(nir)) \
@@ -4360,7 +4360,7 @@ static inline bool should_print_nir(UNUSED nir_shader 
*shader) { return false; }
if (should_print_nir(nir))\
   printf("%s\n", #pass); \
pass(nir, ##__VA_ARGS__); \
-   nir_validate_shader(nir, "after " #pass); \
+   nir_validate_shader(nir, "after " #pass " in " __FILE__); \
if (should_print_nir(nir))\
   nir_print_shader(nir, stdout); \
 )

Mesa (main): nir: allow NIR_PASS(_, )

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 836470d433164b274a881bbcd4835f5784766bce
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=836470d433164b274a881bbcd4835f5784766bce

Author: Rhys Perry 
Date:   Wed Aug 18 13:50:58 2021 +0100

nir: allow NIR_PASS(_, )

If a user wants to skip printing the shader if no changes were made
without declaring a dummy variable for the progress.

Signed-off-by: Rhys Perry 
Reviewed-by: Samuel Pitoiset 
Part-of: 

---

 src/compiler/nir/nir.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index 329d642300e..1d70f7f66f2 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
@@ -4348,6 +4348,7 @@ static inline bool should_print_nir(UNUSED nir_shader 
*shader) { return false; }
   printf("%s\n", #pass); \
if (pass(nir, ##__VA_ARGS__)) {   \
   nir_validate_shader(nir, "after " #pass);  \
+  UNUSED bool _; \
   progress = true;   \
   if (should_print_nir(nir)) \
  nir_print_shader(nir, stdout);  \

Mesa (main): radv: call nir_metadata_preserve in various lowering passes

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: d98b7817fcf657af8a49a2a89a3f30b4b998eda8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d98b7817fcf657af8a49a2a89a3f30b4b998eda8

Author: Rhys Perry 
Date:   Thu Apr 14 16:13:40 2022 +0100

radv: call nir_metadata_preserve in various lowering passes

Signed-off-by: Rhys Perry 
Reviewed-by: Samuel Pitoiset 
Part-of: 

---

 src/amd/vulkan/radv_pipeline.c | 32 +---
 src/amd/vulkan/radv_shader.c   | 33 +++--
 2 files changed, 60 insertions(+), 5 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 0539d1e80c1..1fb2fdc2116 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2653,6 +2653,7 @@ static bool
 radv_lower_viewport_to_zero(nir_shader *nir)
 {
nir_function_impl *impl = nir_shader_get_entrypoint(nir);
+   bool progress = false;
 
nir_builder b;
nir_builder_init(&b, impl);
@@ -2675,11 +2676,19 @@ radv_lower_viewport_to_zero(nir_shader *nir)
  b.cursor = nir_before_instr(instr);
 
  nir_ssa_def_rewrite_uses(&intr->dest.ssa, nir_imm_zero(&b, 1, 32));
- return true;
+ progress = true;
+ break;
   }
+  if (progress)
+ break;
}
 
-   return false;
+   if (progress)
+  nir_metadata_preserve(impl, nir_metadata_block_index | 
nir_metadata_dominance);
+   else
+  nir_metadata_preserve(impl, nir_metadata_all);
+
+   return progress;
 }
 
 static nir_variable *
@@ -2746,10 +2755,17 @@ radv_lower_multiview(nir_shader *nir)
 
  progress = true;
  if (nir->info.stage == MESA_SHADER_VERTEX)
-return progress;
+break;
   }
+  if (nir->info.stage == MESA_SHADER_VERTEX && progress)
+ break;
}
 
+   if (progress)
+  nir_metadata_preserve(impl, nir_metadata_block_index | 
nir_metadata_dominance);
+   else
+  nir_metadata_preserve(impl, nir_metadata_all);
+
return progress;
 }
 
@@ -4054,6 +4070,11 @@ radv_lower_vs_input(nir_shader *nir, const struct 
radv_pipeline_key *pipeline_ke
   }
}
 
+   if (progress)
+  nir_metadata_preserve(impl, nir_metadata_block_index | 
nir_metadata_dominance);
+   else
+  nir_metadata_preserve(impl, nir_metadata_all);
+
return progress;
 }
 
@@ -4213,6 +4234,11 @@ radv_lower_fs_output(nir_shader *nir, const struct 
radv_pipeline_key *pipeline_k
   }
}
 
+   if (progress)
+  nir_metadata_preserve(impl, nir_metadata_block_index | 
nir_metadata_dominance);
+   else
+  nir_metadata_preserve(impl, nir_metadata_all);
+
return progress;
 }
 
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 6f7c49ab446..ba1345297c6 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -333,6 +333,11 @@ lower_intrinsics(nir_shader *nir, const struct 
radv_pipeline_key *key)
   }
}
 
+   if (progress)
+  nir_metadata_preserve(entry, nir_metadata_block_index | 
nir_metadata_dominance);
+   else
+  nir_metadata_preserve(entry, nir_metadata_all);
+
return progress;
 }
 
@@ -401,10 +406,17 @@ radv_lower_primitive_shading_rate(nir_shader *nir)
 
  progress = true;
  if (nir->info.stage == MESA_SHADER_VERTEX)
-return progress;
+break;
   }
+  if (nir->info.stage == MESA_SHADER_VERTEX && progress)
+ break;
}
 
+   if (progress)
+  nir_metadata_preserve(impl, nir_metadata_block_index | 
nir_metadata_dominance);
+   else
+  nir_metadata_preserve(impl, nir_metadata_all);
+
return progress;
 }
 
@@ -459,11 +471,18 @@ radv_force_primitive_shading_rate(nir_shader *nir, struct 
radv_device *device)
 
 progress = true;
 if (nir->info.stage == MESA_SHADER_VERTEX)
-   return progress;
+   break;
  }
   }
+  if (nir->info.stage == MESA_SHADER_VERTEX && progress)
+ break;
}
 
+   if (progress)
+  nir_metadata_preserve(impl, nir_metadata_block_index | 
nir_metadata_dominance);
+   else
+  nir_metadata_preserve(impl, nir_metadata_all);
+
return progress;
 }
 
@@ -549,6 +568,11 @@ radv_lower_fs_intrinsics(nir_shader *nir, const struct 
radv_pipeline_stage *fs_s
   }
}
 
+   if (progress)
+  nir_metadata_preserve(impl, nir_metadata_block_index | 
nir_metadata_dominance);
+   else
+  nir_metadata_preserve(impl, nir_metadata_all);
+
return progress;
 }
 
@@ -986,6 +1010,11 @@ lower_view_index(nir_shader *nir)
   }
}
 
+   if (progress)
+  nir_metadata_preserve(entry, nir_metadata_block_index | 
nir_metadata_dominance);
+   else
+  nir_metadata_preserve(entry, nir_metadata_all);
+
return progress;
 }
 

Mesa (main): nir: call nir_metadata_preserve in nir_lower_memory_model

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 6087f1951e42f71b9b5043f0d5e23e7c31762572
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6087f1951e42f71b9b5043f0d5e23e7c31762572

Author: Rhys Perry 
Date:   Thu Apr 14 16:26:45 2022 +0100

nir: call nir_metadata_preserve in nir_lower_memory_model

Signed-off-by: Rhys Perry 
Reviewed-by: Samuel Pitoiset 
Part-of: 

---

 src/compiler/nir/nir_lower_memory_model.c | 8 +++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/src/compiler/nir/nir_lower_memory_model.c 
b/src/compiler/nir/nir_lower_memory_model.c
index eb16eb9f6eb..8180f5ef041 100644
--- a/src/compiler/nir/nir_lower_memory_model.c
+++ b/src/compiler/nir/nir_lower_memory_model.c
@@ -274,7 +274,8 @@ nir_lower_memory_model(nir_shader *shader)
 {
bool progress = false;
 
-   struct exec_list *cf_list = &nir_shader_get_entrypoint(shader)->body;
+   nir_function_impl *impl = nir_shader_get_entrypoint(shader);
+   struct exec_list *cf_list = &impl->body;
 
uint32_t modes = 0;
foreach_list_typed(nir_cf_node, cf_node, node, cf_list)
@@ -284,5 +285,10 @@ nir_lower_memory_model(nir_shader *shader)
foreach_list_typed_reverse(nir_cf_node, cf_node, node, cf_list)
   progress |= lower_make_available(cf_node, &modes);
 
+   if (progress)
+  nir_metadata_preserve(impl, nir_metadata_block_index | 
nir_metadata_dominance);
+   else
+  nir_metadata_preserve(impl, nir_metadata_all);
+
return progress;
 }

Mesa (main): vulkan: Fall back to raw data objects when deserializing if ops == NULL

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 8b13ee75ba9f27ceac6b6180ca05d321caa13612
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8b13ee75ba9f27ceac6b6180ca05d321caa13612

Author: Jason Ekstrand 
Date:   Wed May 18 10:05:41 2022 -0500

vulkan: Fall back to raw data objects when deserializing if ops == NULL

This can happen if an object is serialized whose object type isn't in
the pipeline cache import ops.  In this case, we generate a raw data
object and plan to turn it into the right object type later.

Fixes: d35e78bb8536 ("vulkan/pipeline_cache: Implement deserialize for raw 
objects")
Reviewed-by: Connor Abbott 
Part-of: 

---

 src/vulkan/runtime/vk_pipeline_cache.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/vulkan/runtime/vk_pipeline_cache.c 
b/src/vulkan/runtime/vk_pipeline_cache.c
index b9a3c4c0e6c..ab9379ac4c4 100644
--- a/src/vulkan/runtime/vk_pipeline_cache.c
+++ b/src/vulkan/runtime/vk_pipeline_cache.c
@@ -271,6 +271,9 @@ vk_pipeline_cache_object_deserialize(struct 
vk_pipeline_cache *cache,
  const void *data, size_t data_size,
  const struct vk_pipeline_cache_object_ops 
*ops)
 {
+   if (ops == NULL)
+  ops = &raw_data_object_ops;
+
if (unlikely(ops->deserialize == NULL)) {
   vk_logw(VK_LOG_OBJS(cache),
   "Pipeline cache object cannot be deserialized");

Mesa (main): 34 new commits

[GitLab Mirror]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6ece34d0c3329c6518633dacec338a19e8f5e38
Author: Alyssa Rosenzweig 
Date:   Mon May 9 16:03:27 2022 -0400

pan/va: Use ^ instead of ` to indicate last-use

This syncs the ISA syntax with other Valhall ISA users. It's also somewhat
easier to read.

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9fb8ca1851b2670fa019ea01dc8c549a812e3e87
Author: Alyssa Rosenzweig 
Date:   Wed May 18 11:57:55 2022 -0400

pan/va: Remove DISCARD.f32 destination

It doesn't actually write anything. This is a pointless divergence from 
Bifrost.

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=69d64e0f42bcf2bba0b7ba19cce667a19542
Author: Alyssa Rosenzweig 
Date:   Mon May 16 09:43:34 2022 -0400

pan/va: Handle 2-src blend in lower_split_src

Fixes assertion fail in shaders/dolphin/smg.1.shader_test

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0576cad958b459701a5dde73ac2f27afb91fe391
Author: Alyssa Rosenzweig 
Date:   Thu May 12 20:21:42 2022 -0400

pan/bi: Validate vector widths

Now that our IR is much more strongly typed, and RA code quality depends on
correct typing, add a validation pass to make sure we didn't screw it up. 
This
pass found a massive number of bugs in early versions of this series.

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4c1bb23a86b0531c096c40017ced194880e6cf8c
Author: Alyssa Rosenzweig 
Date:   Wed May 11 15:47:39 2022 -0400

pan/bi: Validate preload constraints are satisfied

We tightened the rules around preloading substantially and take advantage 
of the
rules in RA. The safe helpers it introduced should ensure the rules are
followed, but just in case, add a validation pass to check our work. This 
pass
found (multiple) bugs in early versions of this series.

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3636cddde1658ae56cad498940d3264c4c364cd3
Author: Alyssa Rosenzweig 
Date:   Fri May 13 11:54:19 2022 -0400

pan/bi: See through splits for var_tex fusion

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1f25f78a9feff41380aa7cf031c3bfd5be67433b
Author: Alyssa Rosenzweig 
Date:   Thu May 12 13:10:57 2022 -0400

pan/bi: Optimize split of collect

Required to get decent codegen from UBO pushing.

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=4a8bde21904df4b31e25af98b3202448655973bf
Author: Alyssa Rosenzweig 
Date:   Thu May 12 12:37:00 2022 -0400

pan/bi: Don't propagate discard

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d81b872465722b5aa096a46c014e2700a9d04217
Author: Alyssa Rosenzweig 
Date:   Wed May 11 17:12:13 2022 -0400

pan/bi: Remove liveness metadata tracking

We don't use it for anything, and with no pass infrastructure it's just an
accident waiting to happen.

Signed-off-by: Alyssa Rosenzweig 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3df5446cbd460aee6c02c570ecbc285102abc9f0
Author: Alyssa Rosenzweig 
Date:   Wed May 11 15:39:56 2022 -0400

pan/bi: Simplify register precolouring in the IR

In the current IR, any register may be preloaded by reading it anywhere, 
and any
register may be precoloured by writing it anywhere. This is convenient for
instruction selection, but requires the register allocator to do 
considerable
gymnastics to ensure it doesn't clobber precoloured registers. It also 
breaks
the purity of our SSA representation, which complicates optimization passes
(e.g. copyprop).

Let's trade some instruction selection complexity for simplifying register
allocation by constraining how register precolouring works. Under the new 
model:

* Registers may only be preloaded at the start of the program.
* Precoloured destinations are handled explicitly by RA.

Internally, a stronger invariant is 

Mesa (staging/22.0): r300: guard for unsigned underflow when unrolling loops

[GitLab Mirror]

Module: Mesa
Branch: staging/22.0
Commit: 0844c6c618c2864e9ab608b629a662e5203d6b11
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0844c6c618c2864e9ab608b629a662e5203d6b11

Author: Pavel Ondračka 
Date:   Tue Feb  8 15:46:36 2022 +0100

r300: guard for unsigned underflow when unrolling loops

If we by some chance end with more instructions than the maximum
amount we can handle, for example from previous branch lowering,
we would underflow while calculating the number of unrolling
iterations and unroll till OOM.

Fixes OOM in gnome-shell 42

Signed-off-by: Pavel Ondračka 
Part-of: 

---

 src/gallium/drivers/r300/compiler/radeon_emulate_loops.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/drivers/r300/compiler/radeon_emulate_loops.c 
b/src/gallium/drivers/r300/compiler/radeon_emulate_loops.c
index ef627b95ca5..c3445a50bfd 100644
--- a/src/gallium/drivers/r300/compiler/radeon_emulate_loops.c
+++ b/src/gallium/drivers/r300/compiler/radeon_emulate_loops.c
@@ -61,6 +61,8 @@ static unsigned int loop_max_possible_iterations(struct 
radeon_compiler *c,
 {
unsigned int total_i = rc_recompute_ips(c);
unsigned int loop_i = (loop->EndLoop->IP - loop->BeginLoop->IP) - 1;
+   if(total_i > c->max_alu_insts)
+   return 1;
/* +1 because the program already has one iteration of the loop. */
return 1 + ((c->max_alu_insts - total_i) / loop_i);
 }

Mesa (main): relnotes: Add sha256sum and fix minor formatting issues

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 35e3aea0b2374610e21a4aecc28bf5048c7f9e2a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=35e3aea0b2374610e21a4aecc28bf5048c7f9e2a

Author: Dylan Baker 
Date:   Wed May 18 13:31:26 2022 -0700

relnotes: Add sha256sum and fix minor formatting issues

Part-of: 

---

 docs/relnotes/22.1.0.rst | 12 ++--
 1 file changed, 2 insertions(+), 10 deletions(-)

diff --git a/docs/relnotes/22.1.0.rst b/docs/relnotes/22.1.0.rst
index d2ca8fa6308..525a204882f 100644
--- a/docs/relnotes/22.1.0.rst
+++ b/docs/relnotes/22.1.0.rst
@@ -21,29 +21,21 @@ SHA256 checksum
 
 ::
 
-TBD.
+   df6270c1371eaa2aa6eb65b95cbbb2a98b14fa4b7ba0ed45e4ca2fd32df60477  
mesa-22.1.0.tar.xz
 
 
 New features
 
 
 - d3d12 GL4.2
-
 - GL_NV_pack_subimage
-
 - VK_EXT_depth_clip_control on lavapipe and RADV
-
 - Vulkan 1.3 support on lavapipe
-
 - VK_EXT_graphics_pipeline_library on lavapipe
-
 - VK_EXT_primitives_generated_query on lavapipe
-
 - VK_EXT_image_2d_view_of_3d on ANV and lavapipe
-
 - VK_KHR_swapchain_mutable_format on lavapipe
-
-- None
+- Intel DG2 support
 
 
 Bug fixes

Mesa (main): docs: add release notes for 22.1.0

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 5944b9ab836e187f81d08501efaf1d2c19086692
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5944b9ab836e187f81d08501efaf1d2c19086692

Author: Dylan Baker 
Date:   Wed May 18 12:30:26 2022 -0700

docs: add release notes for 22.1.0

Part-of: 

---

 docs/relnotes/22.1.0.rst | 3562 ++
 1 file changed, 3562 insertions(+)

Diff:   
http://cgit.freedesktop.org/mesa/mesa/diff/?id=5944b9ab836e187f81d08501efaf1d2c19086692

Mesa (main): docs: update calendar and link releases notes for 22.1.0

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: e84de9c04f8bb5217bcc952997bf61170fe04ee2
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e84de9c04f8bb5217bcc952997bf61170fe04ee2

Author: Dylan Baker 
Date:   Thu May 19 09:00:04 2022 -0700

docs: update calendar and link releases notes for 22.1.0

Part-of: 

---

 docs/release-calendar.csv | 1 -
 docs/relnotes.rst | 2 ++
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/docs/release-calendar.csv b/docs/release-calendar.csv
index d119a6ba509..9e5c027cadd 100644
--- a/docs/release-calendar.csv
+++ b/docs/release-calendar.csv
@@ -1,2 +1 @@
 22.0,2022-05-18,22.0.4,Dylan Baker,This is the last planned release of the 
22.0.x series.
-22.1,2022-05-11,22.1.0-rc5,Dylan Baker,Or 22.1.0 final.
diff --git a/docs/relnotes.rst b/docs/relnotes.rst
index d633b076015..c6eee26cc68 100644
--- a/docs/relnotes.rst
+++ b/docs/relnotes.rst
@@ -3,6 +3,7 @@ Release Notes
 
 The release notes summarize what's new or changed in each Mesa release.
 
+-  :doc:`22.1.0 release notes `
 -  :doc:`22.0.3 release notes `
 -  :doc:`22.0.2 release notes `
 -  :doc:`22.0.1 release notes `
@@ -361,6 +362,7 @@ release notes, or in the `old docs`_.
:maxdepth: 1
:hidden:
 
+   relnotes/22.1.0
relnotes/22.0.3
relnotes/22.0.2
relnotes/22.0.1

Mesa (main): docs: Add calendar entries for 22.1 release.

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 9565ea56409d3056e42ee98032aa92c3f423a914
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=9565ea56409d3056e42ee98032aa92c3f423a914

Author: Dylan Baker 
Date:   Thu May 19 09:03:09 2022 -0700

docs: Add calendar entries for 22.1 release.

Part-of: 

---

 docs/release-calendar.csv | 4 
 1 file changed, 4 insertions(+)

diff --git a/docs/release-calendar.csv b/docs/release-calendar.csv
index 9e5c027cadd..6caa72a7aad 100644
--- a/docs/release-calendar.csv
+++ b/docs/release-calendar.csv
@@ -1 +1,5 @@
 22.0,2022-05-18,22.0.4,Dylan Baker,This is the last planned release of the 
22.0.x series.
+22.1,2022-06-01,22.1.1,Dylan Baker
+,2022-06-15,22.1.2,Dylan Baker
+,2022-06-29,22.1.3,Dylan Baker,
+,2022-07-13,22.1.4,Dylan Baker,This is the last planned release of the 22.1.x 
series.

Mesa (staging/22.0): ci: Some panfrost tests are unexpectedly passing.

[GitLab Mirror]

Module: Mesa
Branch: staging/22.0
Commit: bfe805750b2cb9c3f6c3158ad276ffb1bcfbd0c9
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bfe805750b2cb9c3f6c3158ad276ffb1bcfbd0c9

Author: Dylan Baker 
Date:   Thu May 19 10:06:22 2022 -0700

ci: Some panfrost tests are unexpectedly passing.

That's good, I guess?

---

 src/panfrost/ci/panfrost-t860-fails.txt | 3 ---
 1 file changed, 3 deletions(-)

diff --git a/src/panfrost/ci/panfrost-t860-fails.txt 
b/src/panfrost/ci/panfrost-t860-fails.txt
index 73b25f1ef85..e5009f7b599 100644
--- a/src/panfrost/ci/panfrost-t860-fails.txt
+++ b/src/panfrost/ci/panfrost-t860-fails.txt
@@ -46,11 +46,8 @@ dEQP-GLES31.functional.separate_shader.random.68,Fail
 dEQP-GLES31.functional.separate_shader.random.79,Fail
 dEQP-GLES31.functional.separate_shader.random.80,Fail
 dEQP-GLES31.functional.separate_shader.random.89,Fail
-dEQP-GLES31.functional.shaders.builtin_functions.integer.findlsb.ivec3_lowp_compute,Fail
 
dEQP-GLES31.functional.shaders.builtin_functions.integer.findmsb.ivec2_lowp_compute,Fail
-dEQP-GLES31.functional.shaders.builtin_functions.integer.findmsb.ivec3_lowp_compute,Fail
 
dEQP-GLES31.functional.shaders.builtin_functions.integer.findmsb.uvec2_lowp_compute,Fail
-dEQP-GLES31.functional.shaders.builtin_functions.integer.findmsb.uvec3_lowp_compute,Fail
 
dEQP-GLES31.functional.shaders.builtin_functions.integer.imulextended.ivec3_highp_fragment,Fail
 
dEQP-GLES31.functional.shaders.builtin_functions.integer.umulextended.uvec3_highp_fragment,Fail
 
dEQP-GLES31.functional.synchronization.in_invocation.image_alias_overwrite,Crash

Mesa (main): intel/ds: fix compilation

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 5398c9183ed710fddc406d345a169ad231988bcc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=5398c9183ed710fddc406d345a169ad231988bcc

Author: Lionel Landwerlin 
Date:   Thu May 19 10:43:23 2022 +0300

intel/ds: fix compilation

Signed-off-by: Lionel Landwerlin 
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6518
Fixes: efc2782f970c ("intel/perf: store a copy of devinfo")
Reviewed-by: Jordan Justen 
Part-of: 

---

 src/intel/ds/intel_pps_driver.cc | 1 -
 1 file changed, 1 deletion(-)

diff --git a/src/intel/ds/intel_pps_driver.cc b/src/intel/ds/intel_pps_driver.cc
index c54aaca643e..7ed59d269f8 100644
--- a/src/intel/ds/intel_pps_driver.cc
+++ b/src/intel/ds/intel_pps_driver.cc
@@ -302,7 +302,6 @@ uint64_t IntelDriver::gpu_next()
 
intel_perf_query_result_accumulate_fields(&perf->result,
  selected_query,
- &perf->devinfo,
  record_a + 1,
  record_b + 1,
  false /* no_oa_accumulate */);

Mesa (main): svga: fix aa point

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 8cabf134a85eb047e1dc26ea1e118df3ac31aee8
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8cabf134a85eb047e1dc26ea1e118df3ac31aee8

Author: Charmaine Lee 
Date:   Wed May 18 15:33:05 2022 -0700

svga: fix aa point

Use in_prim from current geometry shader to check for point prim type
when determine if aa point is enabled or not.

Reviewed-by: Neha Bhende 
Part-of: 

---

 src/gallium/drivers/svga/svga_state_fs.c | 18 ++
 1 file changed, 10 insertions(+), 8 deletions(-)

diff --git a/src/gallium/drivers/svga/svga_state_fs.c 
b/src/gallium/drivers/svga/svga_state_fs.c
index 492a2cbdde0..3c09e19171b 100644
--- a/src/gallium/drivers/svga/svga_state_fs.c
+++ b/src/gallium/drivers/svga/svga_state_fs.c
@@ -169,14 +169,16 @@ make_fs_key(const struct svga_context *svga,
   key->fs.pstipple = (svga->curr.rast->templ.poly_stipple_enable &&
   prim_mode == PIPE_PRIM_TRIANGLES);
 
-  key->fs.aa_point = (svga->curr.rast->templ.point_smooth &&
-  prim_mode == PIPE_PRIM_POINTS &&
-  (svga->curr.rast->pointsize > 1.0 ||
-   shader->info.writes_psize));
-
-  if (key->fs.aa_point && svga->curr.gs) {
- assert(svga->curr.gs->aa_point_coord_index != -1);
- key->fs.aa_point_coord_index = svga->curr.gs->aa_point_coord_index;
+  if (svga->curr.gs) {
+ key->fs.aa_point = (svga->curr.rast->templ.point_smooth &&
+shader->info.gs.in_prim == PIPE_PRIM_POINTS &&
+ (svga->curr.rast->pointsize > 1.0 ||
+  shader->info.writes_psize));
+
+ if (key->fs.aa_point) {
+assert(svga->curr.gs->aa_point_coord_index != -1);
+key->fs.aa_point_coord_index = svga->curr.gs->aa_point_coord_index;
+}
   }
}
 

Mesa (main): svga: add need_texcoord_semantic to tgsi_add_point_sprite & tgsi_add_aa_point

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 8cbcdb4f10a4146123c8bbb8cf16fbb2a3f794a7
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=8cbcdb4f10a4146123c8bbb8cf16fbb2a3f794a7

Author: Charmaine Lee 
Date:   Tue May 17 17:20:53 2022 -0700

svga: add need_texcoord_semantic to tgsi_add_point_sprite & tgsi_add_aa_point

Since PIPE_CAP_TGSI_TEXCOORD is now set in SVGA vgpu10 driver,
we need to add a new parameter need_texcoord_semantic to
tgsi_add_point_sprite and tgsi_add_aa_point
to allow setting texcoords using tgsi texcoord semantic.

Reviewed-by: Neha Bhende 
Part-of: 

---

 src/gallium/auxiliary/tgsi/tgsi_aa_point.c | 16 ++--
 src/gallium/auxiliary/tgsi/tgsi_aa_point.h |  3 +-
 src/gallium/auxiliary/tgsi/tgsi_point_sprite.c | 43 --
 src/gallium/auxiliary/tgsi/tgsi_point_sprite.h |  1 +
 src/gallium/drivers/svga/svga_link.c   |  5 +++
 .../drivers/svga/svga_state_tgsi_transform.c   |  6 +++
 src/gallium/drivers/svga/svga_tgsi_vgpu10.c| 11 --
 7 files changed, 67 insertions(+), 18 deletions(-)

diff --git a/src/gallium/auxiliary/tgsi/tgsi_aa_point.c 
b/src/gallium/auxiliary/tgsi/tgsi_aa_point.c
index 58f610fc485..ace4d9a104b 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_aa_point.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_aa_point.c
@@ -47,6 +47,7 @@ struct aa_transform_context
unsigned num_imm;   // number of immediates
unsigned num_input; // number of inputs
unsigned aa_point_coord_index;
+   bool need_texcoord_semantic;
 };
 
 static inline struct aa_transform_context *
@@ -113,8 +114,15 @@ aa_prolog(struct tgsi_transform_context *ctx)
 
/* Declare new generic input/texcoord */
texIn = ts->num_input++;
-   tgsi_transform_input_decl(ctx, texIn, TGSI_SEMANTIC_GENERIC,
- ts->aa_point_coord_index, 
TGSI_INTERPOLATE_LINEAR);
+   if (ts->need_texcoord_semantic) {
+  tgsi_transform_input_decl(ctx, texIn, TGSI_SEMANTIC_TEXCOORD,
+ts->aa_point_coord_index,
+TGSI_INTERPOLATE_LINEAR);
+   } else {
+  tgsi_transform_input_decl(ctx, texIn, TGSI_SEMANTIC_GENERIC,
+ts->aa_point_coord_index,
+TGSI_INTERPOLATE_LINEAR);
+   }
 
/* Declare extra immediates */
imm = ts->num_imm++;
@@ -271,7 +279,8 @@ aa_epilog(struct tgsi_transform_context *ctx)
  */
 struct tgsi_token *
 tgsi_add_aa_point(const struct tgsi_token *tokens_in,
-  const int aa_point_coord_index)
+  const int aa_point_coord_index,
+  const bool need_texcoord_semantic)
 {
struct aa_transform_context transform;
const uint num_new_tokens = 200; /* should be enough */
@@ -291,6 +300,7 @@ tgsi_add_aa_point(const struct tgsi_token *tokens_in,
 
assert(aa_point_coord_index != -1);
transform.aa_point_coord_index = (unsigned)aa_point_coord_index;
+   transform.need_texcoord_semantic = need_texcoord_semantic;
 
transform.num_tmp = 0;
transform.num_imm = 0;
diff --git a/src/gallium/auxiliary/tgsi/tgsi_aa_point.h 
b/src/gallium/auxiliary/tgsi/tgsi_aa_point.h
index d89f40cc389..160bc037530 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_aa_point.h
+++ b/src/gallium/auxiliary/tgsi/tgsi_aa_point.h
@@ -30,6 +30,7 @@ struct tgsi_token;
 
 struct tgsi_token *
 tgsi_add_aa_point(const struct tgsi_token *tokens_in,
-  const int aa_point_coord_index);
+  const int aa_point_coord_index,
+  const bool need_texcoord_semantic);
 
 #endif /* TGSI_AA_POINT_H */
diff --git a/src/gallium/auxiliary/tgsi/tgsi_point_sprite.c 
b/src/gallium/auxiliary/tgsi/tgsi_point_sprite.c
index 432a137fcd7..eb17a1be07d 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_point_sprite.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_point_sprite.c
@@ -95,6 +95,7 @@ struct psprite_transform_context
unsigned point_coord_k;  // aa point coord threshold distance
unsigned stream_out_point_pos:1; // set if to stream out original point pos
unsigned aa_point:1; // set if doing aa point
+   unsigned need_texcoord_semantic:1;   // set if need texcoord semantic
unsigned out_tmp_index[PIPE_MAX_SHADER_OUTPUTS];
int max_generic; // max generic semantic index
 };
@@ -131,11 +132,16 @@ psprite_decl(struct tgsi_transform_context *ctx,
   else if (decl->Semantic.Name == TGSI_SEMANTIC_POSITION) {
  ts->point_pos_out = decl->Range.First;
   }
-  else if (decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&
+  else if (!ts->need_texcoord_semantic &&
+  decl->Semantic.Name == TGSI_SEMANTIC_GENERIC &&
decl->Semantic.Index < 32) {
  ts->point_coord_decl |= 1 << decl->Semantic.Index;
  ts->max_generic = MAX2(ts->max_generic, (int)decl->Semantic.Index);
   }
+  else if (ts->need_te

Mesa (main): docs/u_trace: document u_trace usage

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 12773d40704286c2bfdf18964312150c2039d7bb
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=12773d40704286c2bfdf18964312150c2039d7bb

Author: Danylo Piliaiev 
Date:   Wed May 18 13:08:22 2022 +0300

docs/u_trace: document u_trace usage

Signed-off-by: Danylo Piliaiev 
Reviewed-by: Lionel Landwerlin 
Part-of: 

---

 docs/gpu-perf-tracing.rst | 10 ++
 docs/index.rst|  2 +-
 docs/u_trace.rst  | 43 +++
 3 files changed, 54 insertions(+), 1 deletion(-)

diff --git a/docs/gpu-perf-tracing.rst b/docs/gpu-perf-tracing.rst
new file mode 100644
index 000..fe553b6cef2
--- /dev/null
+++ b/docs/gpu-perf-tracing.rst
@@ -0,0 +1,10 @@
+GPU Performance Tracing
+===
+
+TODO: Add general tips for performance measurement.
+
+.. toctree::
+   :maxdepth: 1
+
+   u_trace
+   perfetto
diff --git a/docs/index.rst b/docs/index.rst
index d92d98c7c42..76758548986 100644
--- a/docs/index.rst
+++ b/docs/index.rst
@@ -72,7 +72,7 @@ Linux, FreeBSD, and other operating systems.
osmesa
debugging
perf
-   perfetto
+   gpu-perf-tracing
extensions
application-issues
viewperf
diff --git a/docs/u_trace.rst b/docs/u_trace.rst
new file mode 100644
index 000..088bd10b654
--- /dev/null
+++ b/docs/u_trace.rst
@@ -0,0 +1,43 @@
+u_trace GPU Performance Tracing
+===
+
+Mesa has its own GPU performance tracing framework which drivers may
+choose to implement. ``gpu.renderstages.*`` producer for
+:doc:`Perfetto Tracing ` is based on u_trace.
+
+It doesn't require external dependencies and much simpler to use. Though
+it provides information only about GPU timings and is harder to analyze
+for complex rendering.
+
+u_trace is useful when one needs to quickly identify performance bottleneck,
+or to build a tool to analyze the raw performance data.
+
+Drivers which support u_trace:
+   - Intel drivers: Anv, Iris
+   - Adreno drivers: Freedreno, Turnip
+
+Usage
+-
+
+u_trace is controlled by environment variables:
+
+:envvar:`GPU_TRACE`
+   if set to ``1`` enables tracing and outputs the data into ``stdout``
+
+:envvar:`GPU_TRACEFILE`
+   specifies a file where to write the output instead of ``stdout``
+
+:envvar:`GPU_TRACE_FORMAT`
+   controls a format of the output
+
+   ``txt``
+  human readable text format
+   ``json``
+  json format, suitable for parsing. Application should appropriately
+  finish its rendering in order for trace's json to be valid.
+  For Vulkan api it is expected to destroy the device, for GL it is
+  expected to destroy the context.
+
+:envvar:`GPU_TRACE_INSTRUMENT`
+   Meaningful only for Perfetto tracing. If set to ``1`` enables
+   instrumentation of GPU commands before the tracing is enabled.

Mesa (22.0): 64 new commits

[GitLab Mirror]

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8194a93115a9b68401ba0a354512b2302f5e9cc
Author: Dylan Baker 
Date:   Thu May 19 11:08:07 2022 -0700

VERSION: bump for 22.0.4

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e91e2931039a0959e9a740364d413b9469938ea
Author: Dylan Baker 
Date:   Thu May 19 11:06:58 2022 -0700

docs: add release notes for 22.0.4

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=bfe805750b2cb9c3f6c3158ad276ffb1bcfbd0c9
Author: Dylan Baker 
Date:   Thu May 19 10:06:22 2022 -0700

ci: Some panfrost tests are unexpectedly passing.

That's good, I guess?

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=0844c6c618c2864e9ab608b629a662e5203d6b11
Author: Pavel Ondračka 
Date:   Tue Feb 8 15:46:36 2022 +0100

r300: guard for unsigned underflow when unrolling loops

If we by some chance end with more instructions than the maximum
amount we can handle, for example from previous branch lowering,
we would underflow while calculating the number of unrolling
iterations and unroll till OOM.

Fixes OOM in gnome-shell 42

Signed-off-by: Pavel Ondračka 
Part-of: 

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d40d80e3872efb25e8187e10c16dce80842c2d4c
Author: Mike Blumenkrantz 
Date:   Fri May 13 11:28:37 2022 -0400

zink: stop leaking shader image surfaces

the code here was fine for checking the base resource unbinds and whatever,
but it never actually destroyed the surfaces/bufferviews created,
which meant they were always being leaked

cc: mesa-stable

Reviewed-by: Dave Airlie 
Part-of: 
(cherry picked from commit 1526df283c3659d510066f58b152597ea15913a0)

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a87a630efbd365458e2f5c6280c3e848b50619a9
Author: Mike Blumenkrantz 
Date:   Fri May 13 11:28:08 2022 -0400

zink: copy incoming shader image struct after doing updates

no functional changes

cc: mesa-stable

Reviewed-by: Dave Airlie 
Part-of: 
(cherry picked from commit 2df1c061688c14d51ad3eeaab886bb7ae4a6172a)

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=56f8047947dac4f9c4bc6497070bda525c83475b
Author: Mike Blumenkrantz 
Date:   Fri May 13 11:25:30 2022 -0400

zink: read shader image r/w usage from incoming data struct

no functional changes

cc: mesa-stable

Reviewed-by: Dave Airlie 
Part-of: 
(cherry picked from commit 32a77b1e255c5213124200076160902928a07830)

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=507ace17b9e0df9b61a58f1aba0179b717363f50
Author: Mike Blumenkrantz 
Date:   Fri May 13 11:23:10 2022 -0400

zink: simplify dumb update flagging in set_shader_images

cc: mesa-stable

Reviewed-by: Dave Airlie 
Part-of: 
(cherry picked from commit a3dff53487bceb42230d525daa9ac57694dc98a2)

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=67a8137be4c148a95f270d6eff3eff605aee9b5e
Author: Mike Blumenkrantz 
Date:   Fri May 13 11:22:50 2022 -0400

zink: reuse local res pointer in set_shader_images

no functional changes

cc: mesa-stable

Reviewed-by: Dave Airlie 
Part-of: 
(cherry picked from commit 22954b486067e08780ba5a1679edfbad7f23c45a)

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=722686d7292cc84ff02a4938a7b95743dcfa35c4
Author: Mike Blumenkrantz 
Date:   Fri May 13 11:18:17 2022 -0400

zink: remove refs from shader images

these have implicit refs from the surface/bufferview that gets created,
so adding a ref here is redundant and less performant

cc: mesa-stable

Reviewed-by: Dave Airlie 
Part-of: 
(cherry picked from commit d0df4889707e94a7bae6a9f6b4092b00f1b42b2a)

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a73d7b14a96d37816ff748c4ba94bca112b86cec
Author: Jason Ekstrand 
Date:   Thu May 12 13:59:30 2022 -0500

nir: Preserve metadata if remove_dead_derefs makes no progress

Cc: mesa-sta...@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin 
Part-of: 
(cherry picked from commit c23b20d43a03634bf528f9870cdd5b0159a69eb4)

URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cf34bbd908c3c48e116381d34212533a89a5b3f0
Author: Mike Blumenkrantz 
Date:   Wed May 11 16:59:31 2022 -0400

zink: fix sparse texture depth calcs for arrayed textures

Mesa (main): u_trace/anv/iris: drop cs argument for recording traces

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 1c077ca9c009b1045ffdd0a5764643e4959e288a
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1c077ca9c009b1045ffdd0a5764643e4959e288a

Author: Lionel Landwerlin 
Date:   Thu May 19 13:09:25 2022 +0300

u_trace/anv/iris: drop cs argument for recording traces

Signed-off-by: Lionel Landwerlin 
Reviewed-by: Danylo Piliaiev 
Part-of: 

---

 src/gallium/drivers/iris/iris_batch.c  |  2 +-
 src/gallium/drivers/iris/iris_batch.h  |  2 +-
 src/gallium/drivers/iris/iris_blorp.c  |  4 +--
 src/gallium/drivers/iris/iris_state.c  | 18 +--
 src/gallium/drivers/iris/iris_utrace.c |  4 +--
 src/intel/ds/intel_tracepoints.py  |  3 +-
 src/intel/vulkan/anv_utrace.c  |  6 ++--
 src/intel/vulkan/genX_blorp_exec.c |  4 +--
 src/intel/vulkan/genX_cmd_buffer.c | 57 --
 src/util/perf/u_trace.py   | 30 ++
 10 files changed, 74 insertions(+), 56 deletions(-)

diff --git a/src/gallium/drivers/iris/iris_batch.c 
b/src/gallium/drivers/iris/iris_batch.c
index f4a52f04ce6..71cb2096ad1 100644
--- a/src/gallium/drivers/iris/iris_batch.c
+++ b/src/gallium/drivers/iris/iris_batch.c
@@ -708,7 +708,7 @@ iris_finish_batch(struct iris_batch *batch)
 
finish_seqno(batch);
 
-   trace_intel_end_batch(&batch->trace, batch, batch->name);
+   trace_intel_end_batch(&batch->trace, batch->name);
 
/* Emit MI_BATCH_BUFFER_END to finish our batch. */
uint32_t *map = batch->map_next;
diff --git a/src/gallium/drivers/iris/iris_batch.h 
b/src/gallium/drivers/iris/iris_batch.h
index cf34e7f3472..a1dfa6e63e1 100644
--- a/src/gallium/drivers/iris/iris_batch.h
+++ b/src/gallium/drivers/iris/iris_batch.h
@@ -253,7 +253,7 @@ iris_get_command_space(struct iris_batch *batch, unsigned 
bytes)
 {
if (!batch->begin_trace_recorded) {
   batch->begin_trace_recorded = true;
-  trace_intel_begin_batch(&batch->trace, batch);
+  trace_intel_begin_batch(&batch->trace);
}
iris_require_command_space(batch, bytes);
void *map = batch->map_next;
diff --git a/src/gallium/drivers/iris/iris_blorp.c 
b/src/gallium/drivers/iris/iris_blorp.c
index b54653846cb..a0af9d6d343 100644
--- a/src/gallium/drivers/iris/iris_blorp.c
+++ b/src/gallium/drivers/iris/iris_blorp.c
@@ -453,7 +453,7 @@ blorp_measure_start(struct blorp_batch *blorp_batch,
struct iris_context *ice = blorp_batch->blorp->driver_ctx;
struct iris_batch *batch = blorp_batch->driver_batch;
 
-   trace_intel_begin_blorp(&batch->trace, batch);
+   trace_intel_begin_blorp(&batch->trace);
 
if (batch->measure == NULL)
   return;
@@ -468,7 +468,7 @@ blorp_measure_end(struct blorp_batch *blorp_batch,
 {
struct iris_batch *batch = blorp_batch->driver_batch;
 
-   trace_intel_end_blorp(&batch->trace, batch,
+   trace_intel_end_blorp(&batch->trace,
  params->x1 - params->x0,
  params->y1 - params->y0,
  params->hiz_op,
diff --git a/src/gallium/drivers/iris/iris_state.c 
b/src/gallium/drivers/iris/iris_state.c
index 7535c646c2a..09500e4085e 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -6067,7 +6067,7 @@ iris_upload_dirty_render_state(struct iris_context *ice,
}
 
if (dirty & IRIS_DIRTY_RENDER_BUFFER)
-  trace_framebuffer_state(&batch->trace, batch, &ice->state.framebuffer);
+  trace_framebuffer_state(&batch->trace, NULL, &ice->state.framebuffer);
 
for (int stage = 0; stage <= MESA_SHADER_FRAGMENT; stage++) {
   if (stage_dirty & (IRIS_STAGE_DIRTY_BINDINGS_VS << stage)) {
@@ -6860,7 +6860,7 @@ iris_upload_render_state(struct iris_context *ice,
 {
bool use_predicate = ice->state.predicate == IRIS_PREDICATE_STATE_USE_BIT;
 
-   trace_intel_begin_draw(&batch->trace, batch);
+   trace_intel_begin_draw(&batch->trace);
 
if (ice->state.dirty & IRIS_DIRTY_VERTEX_BUFFER_FLUSHES)
   flush_vbos(ice, batch);
@@ -7074,7 +7074,7 @@ iris_upload_render_state(struct iris_context *ice,
 
iris_batch_sync_region_end(batch);
 
-   trace_intel_end_draw(&batch->trace, batch, 0);
+   trace_intel_end_draw(&batch->trace, 0);
 }
 
 static void
@@ -7119,7 +7119,7 @@ iris_upload_compute_walker(struct iris_context *ice,
const struct brw_cs_dispatch_info dispatch =
   brw_cs_get_dispatch_info(devinfo, cs_prog_data, grid->block);
 
-   trace_intel_begin_compute(&batch->trace, batch);
+   trace_intel_begin_compute(&batch->trace);
 
if (stage_dirty & IRIS_STAGE_DIRTY_CS) {
   iris_emit_cmd(batch, GENX(CFE_STATE), cfe) {
@@ -7160,7 +7160,7 @@ iris_upload_compute_walker(struct iris_context *ice,
   assert(brw_cs_push_const_total_size(cs_prog_data, dispatch.threads) == 
0);
}
 
-   trace_intel_end_compute(&batch->trace, batch, grid->grid[0], grid->grid[1], 
grid->grid[2]);
+   trace_intel_end_compute(&batch->trace, grid->grid[0], grid->gr

Mesa (main): spirv: Use nir_vec_scalars() to simplify matrix transpose.

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 87d74311985257dd9bbef15f9010c9fe9f64c84c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=87d74311985257dd9bbef15f9010c9fe9f64c84c

Author: Emma Anholt 
Date:   Mon May  2 15:54:12 2022 -0700

spirv: Use nir_vec_scalars() to simplify matrix transpose.

This should emit fewer instructions that need to be copy-propagated away.

Reviewed-by: Matt Turner 
Part-of: 

---

 src/compiler/spirv/spirv_to_nir.c | 15 ++-
 1 file changed, 6 insertions(+), 9 deletions(-)

diff --git a/src/compiler/spirv/spirv_to_nir.c 
b/src/compiler/spirv/spirv_to_nir.c
index 635fdda2527..f9b4eb85530 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++ b/src/compiler/spirv/spirv_to_nir.c
@@ -3872,19 +3872,16 @@ vtn_ssa_transpose(struct vtn_builder *b, struct 
vtn_ssa_value *src)
   vtn_create_ssa_value(b, glsl_transposed_type(src->type));
 
for (unsigned i = 0; i < glsl_get_matrix_columns(dest->type); i++) {
-  nir_alu_instr *vec = create_vec(b, glsl_get_matrix_columns(src->type),
- glsl_get_bit_size(src->type));
   if (glsl_type_is_vector_or_scalar(src->type)) {
-  vec->src[0].src = nir_src_for_ssa(src->def);
-  vec->src[0].swizzle[0] = i;
+ dest->elems[i]->def = nir_channel(&b->nb, src->def, i);
   } else {
- for (unsigned j = 0; j < glsl_get_matrix_columns(src->type); j++) {
-vec->src[j].src = nir_src_for_ssa(src->elems[j]->def);
-vec->src[j].swizzle[0] = i;
+ unsigned cols = glsl_get_matrix_columns(src->type);
+ nir_ssa_scalar srcs[cols];
+ for (unsigned j = 0; j < cols; j++) {
+srcs[j] = nir_get_ssa_scalar(src->elems[j]->def, i);
  }
+ dest->elems[i]->def = nir_vec_scalars(&b->nb, srcs, cols);
   }
-  nir_builder_instr_insert(&b->nb, &vec->instr);
-  dest->elems[i]->def = &vec->dest.dest.ssa;
}
 
dest->transposed = src;

Mesa (main): spirv_to_nir: Cast RelaxedPrecision ALU op dests to mediump.

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 260559050afc11b50e05209203bc7e77bd42bcfe
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=260559050afc11b50e05209203bc7e77bd42bcfe

Author: Emma Anholt 
Date:   Tue Apr 26 16:29:04 2022 -0700

spirv_to_nir: Cast RelaxedPrecision ALU op dests to mediump.

This is controlled by spirv_to_nir_options.relaxed_precision_alu, because
some drivers don't want it.

This gets us mostly 16-bit math on turnip in vk-5-normal.

Reviewed-by: Matt Turner 
Part-of: 

---

 src/compiler/spirv/nir_spirv.h   |  10 +++
 src/compiler/spirv/vtn_alu.c | 136 ++-
 src/compiler/spirv/vtn_glsl450.c |  43 +
 src/compiler/spirv/vtn_private.h |   7 ++
 4 files changed, 193 insertions(+), 3 deletions(-)

diff --git a/src/compiler/spirv/nir_spirv.h b/src/compiler/spirv/nir_spirv.h
index 0410c5f7f51..8899eae7623 100644
--- a/src/compiler/spirv/nir_spirv.h
+++ b/src/compiler/spirv/nir_spirv.h
@@ -75,6 +75,16 @@ struct spirv_to_nir_options {
 */
uint16_t float_controls_execution_mode;
 
+   /* True if RelaxedPrecision-decorated ALU result values should be performed
+* with 16-bit math.
+*/
+   bool mediump_16bit_alu;
+
+   /* When mediump_16bit_alu is set, determines whether nir_op_fddx/fddy can be
+* performed in 16-bit math.
+*/
+   bool mediump_16bit_derivatives;
+
struct spirv_supported_capabilities caps;
 
/* Address format for various kinds of pointers. */
diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c
index 6fd7a05afc2..b35f38bffc5 100644
--- a/src/compiler/spirv/vtn_alu.c
+++ b/src/compiler/spirv/vtn_alu.c
@@ -153,6 +153,48 @@ mat_times_scalar(struct vtn_builder *b,
return dest;
 }
 
+nir_ssa_def *
+vtn_mediump_downconvert(struct vtn_builder *b, enum glsl_base_type base_type, 
nir_ssa_def *def)
+{
+   if (def->bit_size == 16)
+  return def;
+
+   switch (base_type) {
+   case GLSL_TYPE_FLOAT:
+  return nir_f2fmp(&b->nb, def);
+   case GLSL_TYPE_INT:
+   case GLSL_TYPE_UINT:
+  return nir_i2imp(&b->nb, def);
+   default:
+  unreachable("bad relaxed precision input type");
+   }
+}
+
+struct vtn_ssa_value *
+vtn_mediump_downconvert_value(struct vtn_builder *b, struct vtn_ssa_value *src)
+{
+   if (!src)
+  return src;
+
+   struct vtn_ssa_value *srcmp = vtn_create_ssa_value(b, src->type);
+
+   if (src->transposed) {
+  srcmp->transposed = vtn_mediump_downconvert_value(b, src->transposed);
+   } else {
+  enum glsl_base_type base_type = glsl_get_base_type(src->type);
+
+  if (glsl_type_is_vector_or_scalar(src->type)) {
+ srcmp->def = vtn_mediump_downconvert(b, base_type, src->def);
+  } else {
+ assert(glsl_get_base_type(src->type) == GLSL_TYPE_FLOAT);
+ for (int i = 0; i < glsl_get_matrix_columns(src->type); i++)
+srcmp->elems[i]->def = vtn_mediump_downconvert(b, base_type, 
src->elems[i]->def);
+  }
+   }
+
+   return srcmp;
+}
+
 static struct vtn_ssa_value *
 vtn_handle_matrix_alu(struct vtn_builder *b, SpvOp opcode,
   struct vtn_ssa_value *src0, struct vtn_ssa_value *src1)
@@ -465,6 +507,84 @@ handle_no_wrap(UNUSED struct vtn_builder *b, UNUSED struct 
vtn_value *val,
}
 }
 
+static void
+vtn_value_is_relaxed_precision_cb(struct vtn_builder *b,
+  struct vtn_value *val, int member,
+  const struct vtn_decoration *dec, void *void_ctx)
+{
+   bool *relaxed_precision = void_ctx;
+   switch (dec->decoration) {
+   case SpvDecorationRelaxedPrecision:
+  *relaxed_precision = true;
+  break;
+
+   default:
+  break;
+   }
+}
+
+bool
+vtn_value_is_relaxed_precision(struct vtn_builder *b, struct vtn_value *val)
+{
+   bool result = false;
+   vtn_foreach_decoration(b, val,
+  vtn_value_is_relaxed_precision_cb, &result);
+   return result;
+}
+
+static bool
+vtn_alu_op_mediump_16bit(struct vtn_builder *b, SpvOp opcode, struct vtn_value 
*dest_val)
+{
+   if (!b->options->mediump_16bit_alu || !vtn_value_is_relaxed_precision(b, 
dest_val))
+  return false;
+
+   switch (opcode) {
+   case SpvOpDPdx:
+   case SpvOpDPdy:
+   case SpvOpDPdxFine:
+   case SpvOpDPdyFine:
+   case SpvOpDPdxCoarse:
+   case SpvOpDPdyCoarse:
+   case SpvOpFwidth:
+   case SpvOpFwidthFine:
+   case SpvOpFwidthCoarse:
+  return b->options->mediump_16bit_derivatives;
+   default:
+  return true;
+   }
+}
+
+static nir_ssa_def *
+vtn_mediump_upconvert(struct vtn_builder *b, enum glsl_base_type base_type, 
nir_ssa_def *def)
+{
+   if (def->bit_size != 16)
+  return def;
+
+   switch (base_type) {
+   case GLSL_TYPE_FLOAT:
+  return nir_f2f32(&b->nb, def);
+   case GLSL_TYPE_INT:
+  return nir_i2i32(&b->nb, def);
+   case GLSL_TYPE_UINT:
+  return nir_u2u32(&b->nb, def);
+   default:
+  unreachable("bad relaxed precision output type");
+   }
+

Mesa (main): turnip: Make RelaxedPrecision-decorated ALU ops 16-bit.

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: a28d2e87d347b94c41ad9299c7e88978faf7174c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a28d2e87d347b94c41ad9299c7e88978faf7174c

Author: Emma Anholt 
Date:   Mon May  2 16:22:37 2022 -0700

turnip: Make RelaxedPrecision-decorated ALU ops 16-bit.

Improves gfxbench vk-5-normal performance 5.5%.

Fixes: #6346
Reviewed-by: Matt Turner 
Part-of: 

---

 src/freedreno/vulkan/tu_shader.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/freedreno/vulkan/tu_shader.c b/src/freedreno/vulkan/tu_shader.c
index c977b1d8566..2d41900f84e 100644
--- a/src/freedreno/vulkan/tu_shader.c
+++ b/src/freedreno/vulkan/tu_shader.c
@@ -54,6 +54,9 @@ tu_spirv_to_nir(struct tu_device *dev,
   /* Accessed via stg/ldg (not used with Vulkan?) */
   .global_addr_format = nir_address_format_64bit_global,
 
+  /* Use 16-bit math for RelaxedPrecision ALU ops */
+  .mediump_16bit_alu = true,
+
   /* ViewID is a sysval in geometry stages and an input in the FS */
   .view_index_is_input = stage == MESA_SHADER_FRAGMENT,
   .caps = {

Mesa (main): freedreno/ir3: Add support for 16-bit nir_texop_lod.

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 1cf0736f1c44ae3cd53163a4a21ed290a2c0836c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=1cf0736f1c44ae3cd53163a4a21ed290a2c0836c

Author: Emma Anholt 
Date:   Wed May 11 19:55:45 2022 -0700

freedreno/ir3: Add support for 16-bit nir_texop_lod.

Same basic path, just do the rescaling in half float.

Reviewed-by: Matt Turner 
Part-of: 

---

 src/freedreno/ir3/ir3_compiler_nir.c | 11 +++
 1 file changed, 7 insertions(+), 4 deletions(-)

diff --git a/src/freedreno/ir3/ir3_compiler_nir.c 
b/src/freedreno/ir3/ir3_compiler_nir.c
index 5a02af2e253..23dc383828c 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -3280,12 +3280,15 @@ emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
 
/* GETLOD returns results in 4.8 fixed point */
if (opc == OPC_GETLOD) {
-  struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
+  bool half = nir_dest_bit_size(tex->dest) == 16;
+  struct ir3_instruction *factor =
+ half ? create_immed_typed(b, _mesa_float_to_half(1.0 / 256), TYPE_F16)
+  : create_immed(b, fui(1.0 / 256));
 
-  compile_assert(ctx, tex->dest_type == nir_type_float32);
   for (i = 0; i < 2; i++) {
- dst[i] =
-ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0, factor, 0);
+ dst[i] = ir3_MUL_F(
+b, ir3_COV(b, dst[i], TYPE_S32, half ? TYPE_F16 : TYPE_F32), 0,
+factor, 0);
   }
}
 

Mesa (main): freedreno/ir3: Lower texture instructions used only for f2f16 to 16-bit.

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 7938ce4af3ac6fba99826f41f7f9d5f1386fc22c
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=7938ce4af3ac6fba99826f41f7f9d5f1386fc22c

Author: Emma Anholt 
Date:   Wed May 11 17:33:11 2022 -0700

freedreno/ir3: Lower texture instructions used only for f2f16 to 16-bit.

2.5% improvement in gfxbench vk-5-normal.  No obvious change on
gl-5-normal.

shader-db on Rob's android shaders:

total instructions in shared programs: 770644 -> 770595 (<.01%)
instructions in affected programs: 14880 -> 14831 (-0.33%)
total nops in shared programs: 167784 -> 167860 (0.05%)
nops in affected programs: 3351 -> 3427 (2.27%)
total non-nops in shared programs: 602860 -> 602735 (-0.02%)
non-nops in affected programs: 10523 -> 10398 (-1.19%)
total mov in shared programs: 19313 -> 19286 (-0.14%)
mov in affected programs: 365 -> 338 (-7.40%)
total cov in shared programs: 18075 -> 17978 (-0.54%)
cov in affected programs: 566 -> 469 (-17.14%)
total dwords in shared programs: 1612848 -> 1612596 (-0.02%)
dwords in affected programs: 13882 -> 13630 (-1.82%)
total last-baryf in shared programs: 56144 -> 55975 (-0.30%)
last-baryf in affected programs: 482 -> 313 (-35.06%)
total full in shared programs: 36094 -> 36092 (<.01%)
full in affected programs: 10 -> 8 (-20.00%)
total sstall in shared programs: 66986 -> 66923 (-0.09%)
sstall in affected programs: 1392 -> 1329 (-4.53%)
total systall in shared programs: 91244 -> 91072 (-0.19%)
systall in affected programs: 1194 -> 1022 (-14.41%)
total (sy) in shared programs: 4316 -> 4321 (0.12%)
(sy) in affected programs: 19 -> 24 (26.32%)

Reviewed-by: Matt Turner 
Part-of: 

---

 src/freedreno/ir3/ir3_nir.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/freedreno/ir3/ir3_nir.c b/src/freedreno/ir3/ir3_nir.c
index 8ce844af77a..8ca723900f2 100644
--- a/src/freedreno/ir3/ir3_nir.c
+++ b/src/freedreno/ir3/ir3_nir.c
@@ -696,6 +696,8 @@ ir3_nir_lower_variant(struct ir3_shader_variant *so, 
nir_shader *s)
bool more_late_algebraic = true;
while (more_late_algebraic) {
   more_late_algebraic = OPT(s, nir_opt_algebraic_late);
+  if (!more_late_algebraic)
+ OPT(s, nir_fold_16bit_sampler_conversions, 0, ~0);
   OPT_V(s, nir_opt_constant_folding);
   OPT_V(s, nir_copy_prop);
   OPT_V(s, nir_opt_dce);

Mesa (main): freedreno/ir3: Fix 16-bit bit_count.

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 633cf4eca1dec92605bfcf045c37ffc797132fa3
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=633cf4eca1dec92605bfcf045c37ffc797132fa3

Author: Emma Anholt 
Date:   Wed May 11 16:31:33 2022 -0700

freedreno/ir3: Fix 16-bit bit_count.

No need to do the 16-bit lowering if it already is.

Reviewed-by: Matt Turner 
Part-of: 

---

 src/freedreno/ir3/ir3_compiler_nir.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/freedreno/ir3/ir3_compiler_nir.c 
b/src/freedreno/ir3/ir3_compiler_nir.c
index 980c83b48ba..5a02af2e253 100644
--- a/src/freedreno/ir3/ir3_compiler_nir.c
+++ b/src/freedreno/ir3/ir3_compiler_nir.c
@@ -769,7 +769,7 @@ emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
   break;
}
case nir_op_bit_count: {
-  if (ctx->compiler->gen < 5) {
+  if (ctx->compiler->gen < 5 || (src[0]->dsts[0]->flags & IR3_REG_HALF)) {
  dst[0] = ir3_CBITS_B(b, src[0], 0);
  break;
   }

Mesa (22.0): docs: add sha256sum to 22.0.4 notes

[GitLab Mirror]

Module: Mesa
Branch: 22.0
Commit: b9c1dfa26573dde5dced3ab4be2ea1e98779fc18
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9c1dfa26573dde5dced3ab4be2ea1e98779fc18

Author: Dylan Baker 
Date:   Thu May 19 14:21:30 2022 -0700

docs: add sha256sum to 22.0.4 notes

---

 docs/relnotes/22.0.4.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/relnotes/22.0.4.rst b/docs/relnotes/22.0.4.rst
index fe51dea45ac..683d72ed887 100644
--- a/docs/relnotes/22.0.4.rst
+++ b/docs/relnotes/22.0.4.rst
@@ -19,7 +19,7 @@ SHA256 checksum
 
 ::
 
-TBD.
+   c7971f58fa826e474617cda53250c6600fce60994b9fac5b641522e21f471ed4  
mesa-22.0.4.tar.xz
 
 
 New features

Mesa (main): intel: Drop Wa_1409226450 (stall before instruction cache invalidation)

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 27314718a34d420b7f36eeefce22ee06919cdbed
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=27314718a34d420b7f36eeefce22ee06919cdbed

Author: Kenneth Graunke 
Date:   Tue May 17 16:37:35 2022 -0700

intel: Drop Wa_1409226450 (stall before instruction cache invalidation)

Production Tigerlake and DG1 hardware shouldn't need this workaround.
It was only needed on the very first steppings which never went public.

Reviewed-by: Tapani Pälli 
Part-of: 

---

 src/gallium/drivers/iris/iris_state.c | 12 
 src/intel/vulkan/genX_cmd_buffer.c|  6 --
 2 files changed, 18 deletions(-)

diff --git a/src/gallium/drivers/iris/iris_state.c 
b/src/gallium/drivers/iris/iris_state.c
index 09500e4085e..24dae802611 100644
--- a/src/gallium/drivers/iris/iris_state.c
+++ b/src/gallium/drivers/iris/iris_state.c
@@ -7810,18 +7810,6 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
  0, NULL, 0, 0);
}
 
-   /* Wa_1409226450, Wait for EU to be idle before pipe control which
-* invalidates the instruction cache
-*/
-   if (GFX_VER == 12 && (flags & PIPE_CONTROL_INSTRUCTION_INVALIDATE)) {
-  iris_emit_raw_pipe_control(batch,
- "workaround: CS stall before instruction "
- "cache invalidate",
- PIPE_CONTROL_CS_STALL |
- PIPE_CONTROL_STALL_AT_SCOREBOARD, bo, offset,
- imm);
-   }
-
if (GFX_VER == 9 && IS_COMPUTE_PIPELINE(batch) && post_sync_flags) {
   /* Project: SKL / Argument: LRI Post Sync Operation [23]
*
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 089677e62fb..3d249d09aef 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -2132,12 +2132,6 @@ genX(emit_apply_pipe_flushes)(struct anv_batch *batch,
   bits &= ~ANV_PIPE_NEEDS_END_OF_PIPE_SYNC_BIT;
}
 
-   /* Wa_1409226450, Wait for EU to be idle before pipe control which
-* invalidates the instruction cache
-*/
-   if (GFX_VER == 12 && (bits & ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT))
-  bits |= ANV_PIPE_CS_STALL_BIT | ANV_PIPE_STALL_AT_SCOREBOARD_BIT;
-
/* Project: SKL / Argument: LRI Post Sync Operation [23]
 *
 * "PIPECONTROL command with “Command Streamer Stall Enable” must be

Mesa (staging/22.0): docs: add release notes for 22.0.4

[GitLab Mirror]

Module: Mesa
Branch: staging/22.0
Commit: 6e91e2931039a0959e9a740364d413b9469938ea
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=6e91e2931039a0959e9a740364d413b9469938ea

Author: Dylan Baker 
Date:   Thu May 19 11:06:58 2022 -0700

docs: add release notes for 22.0.4

---

 docs/relnotes/22.0.4.rst | 152 +++
 1 file changed, 152 insertions(+)

diff --git a/docs/relnotes/22.0.4.rst b/docs/relnotes/22.0.4.rst
new file mode 100644
index 000..fe51dea45ac
--- /dev/null
+++ b/docs/relnotes/22.0.4.rst
@@ -0,0 +1,152 @@
+Mesa 22.0.4 Release Notes / 2022-05-19
+==
+
+Mesa 22.0.4 is a bug fix release which fixes bugs found since the 22.0.3 
release.
+
+Mesa 22.0.4 implements the OpenGL 4.6 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.6. OpenGL
+4.6 is **only** available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+
+Mesa 22.0.4 implements the Vulkan 1.2 API, but the version reported by
+the apiVersion property of the VkPhysicalDeviceProperties struct
+depends on the particular driver being used.
+
+SHA256 checksum
+---
+
+::
+
+TBD.
+
+
+New features
+
+
+- None
+
+
+Bug fixes
+-
+
+- turnip: gfxbench mh3.1 offscreen crash with ANGLE
+- [radv] DCC causes artifacts in Senran Kagura Shinovi Versus
+- Radeon RX 5700XT crash when using prusa-slicer
+- clover: Assertion \`NumContainedTys && "Attempting to get element type of 
opaque pointer"' failed
+
+
+Changes
+---
+
+Alyssa Rosenzweig (1):
+
+- nir: Don't set writes_memory for reading XFB
+
+Chia-I Wu (1):
+
+- anv: advertise rectangularLines only for Gen10+
+
+Danylo Piliaiev (3):
+
+- tu: Fix indices of drm_msm_gem_submit_cmd when filling them
+- tu: Do not flush ccu in clear/blits during renderpass
+- pps: Open writable renderer node in DrmDevice::create
+
+Dylan Baker (17):
+
+- docs: Add sh256sum for mesa 20.0.3
+- .pick_status.json: Update to 7f91e8fad94dd34f83c6a124dbbe5d210be7715f
+- .pick_status.json: Update to 14b1ed1ce105d42652f70e2fd13c90fc4f2e7ffc
+- .pick_status.json: Mark 69e6417e19793043e4bb3cd500cfcf377bce4c03 as 
denominated
+- .pick_status.json: Mark c025cb9ee9d79ebfb66a577556e04deecfe012ed as 
denominated
+- .pick_status.json: Mark 6317f88b044501354a052064478d5b43dfe41809 as 
denominated
+- .pick_status.json: Mark 5ff3fa5912778adb8117fa26bfe4786b583e741b as 
denominated
+- .pick_status.json: Mark 9a412c10b7a96adf71c9a2ca44a0abca75de1c49 as 
denominated
+- .pick_status.json: Mark 0e49ef5c9f2ec34567613226ad498edca28bce88 as 
denominated
+- .pick_status.json: Mark ae369e9f6d4f2c826f1f2a748c32a14f9d5f1f54 as 
denominated
+- .pick_status.json: Update to 14b1ed1ce105d42652f70e2fd13c90fc4f2e7ffc
+- .pick_status.json: Mark 8c1d9c7b744b2e5b40fd42cfd51256b16deea6a8 as 
denominated
+- .pick_status.json: Mark f1d1371e512e32d03f7f54d873020e589ee67d47 as 
denominated
+- .pick_status.json: Update to 57293dee2b11ba7e52052edc4d0437f08db19144
+- .pick_status.json: Update to 5c90eb1c53f46e86717c6bf4d5253dd23c4dac1f
+- .pick_status.json: Mark 5a3aee78cbb70918b413cdd40dffcae7c9e97d8c as 
denominated
+- ci: Some panfrost tests are unexpectedly passing.
+
+Georg Lehmann (1):
+
+- nir/opt_algebraic: Fix mask in shift by constant combining.
+
+Icecream95 (6):
+
+- nir/lower_tex: Copy more fields in lower_tex_to_txd and friends
+- pan/mdg: Keep min_bound at 16 when alignment requires it
+- pan/mdg: Use MAX2 to set min_alignment
+- pan/mdg: Fix mask usage when filling before a spill
+- pan/mdg: Return the instruction from mir_insert_instruction_*_scheduled
+- pan/mdg: Fix multiple spilt writes in the same bundle
+
+Jason Ekstrand (4):
+
+- vulkan/wsi: Set the right stage flags for semaphore waits
+- gallium/u_threaded_context: Use PIPE_MAX_SHADER_SAMPLER_VIEWS for 
sampler_buffers
+- nir/cf: Return a cursor from nir_cf_extract as well
+- nir: Preserve metadata if remove_dead_derefs makes no progress
+
+Lionel Landwerlin (4):
+
+- nir/cf: return cursor after insertion of cf_list
+- nir/lower_shader_calls: don't use nop instructions as cursors
+- nir/lower_shader_calls: don't insert code after break/continue
+- nir/lower_shader_calls: put inserted instructions into a dummy block
+
+Marcin Ślusarz (2):
+
+- anv: update task/mesh distribution with the recommended values
+- anv: disable streamout before emitting mesh shading state
+
+Marek Olšák (2):
+
+- ac/llvm: set the correct cache policy for sparse buffer loads
+- radeonsi: fix a crash when failing to create a context
+
+Mike Blumenkrantz (14):
+
+- util/blitter: fix sampler restore with 0 saved samplers
+- st/draw_feedback: set constant buffer stride
+- llvmpipe: always set ssbo data pointers for draw
+- gallivm: fix oob txf swizzl

Mesa (staging/22.0): VERSION: bump for 22.0.4

[GitLab Mirror]

Module: Mesa
Branch: staging/22.0
Commit: a8194a93115a9b68401ba0a354512b2302f5e9cc
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a8194a93115a9b68401ba0a354512b2302f5e9cc

Author: Dylan Baker 
Date:   Thu May 19 11:08:07 2022 -0700

VERSION: bump for 22.0.4

---

 VERSION | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/VERSION b/VERSION
index 8b740661820..758704512b5 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-22.0.3
+22.0.4

Mesa (staging/22.0): docs: add sha256sum to 22.0.4 notes

[GitLab Mirror]

Module: Mesa
Branch: staging/22.0
Commit: b9c1dfa26573dde5dced3ab4be2ea1e98779fc18
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b9c1dfa26573dde5dced3ab4be2ea1e98779fc18

Author: Dylan Baker 
Date:   Thu May 19 14:21:30 2022 -0700

docs: add sha256sum to 22.0.4 notes

---

 docs/relnotes/22.0.4.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/relnotes/22.0.4.rst b/docs/relnotes/22.0.4.rst
index fe51dea45ac..683d72ed887 100644
--- a/docs/relnotes/22.0.4.rst
+++ b/docs/relnotes/22.0.4.rst
@@ -19,7 +19,7 @@ SHA256 checksum
 
 ::
 
-TBD.
+   c7971f58fa826e474617cda53250c6600fce60994b9fac5b641522e21f471ed4  
mesa-22.0.4.tar.xz
 
 
 New features

Mesa (main): lavapipe: Use the correct ICD path on Win32

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: c6cddd2e17e30e02d476bfd04c9c3af5aea4f6b1
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c6cddd2e17e30e02d476bfd04c9c3af5aea4f6b1

Author: Jason Ekstrand 
Date:   Thu May 19 12:47:50 2022 -0500

lavapipe: Use the correct ICD path on Win32

Acked-by: Mike Blumenkrantz 
Part-of: 

---

 src/gallium/targets/lavapipe/meson.build | 17 +++--
 1 file changed, 11 insertions(+), 6 deletions(-)

diff --git a/src/gallium/targets/lavapipe/meson.build 
b/src/gallium/targets/lavapipe/meson.build
index bda4fbc574d..f410b444815 100644
--- a/src/gallium/targets/lavapipe/meson.build
+++ b/src/gallium/targets/lavapipe/meson.build
@@ -21,16 +21,21 @@ if with_platform_windows
   icd_file_name = 'vulkan_lvp.dll'
 endif
 
+icd_command = [
+  prog_python, '@INPUT0@',
+  '--api-version', '1.1', '--xml', '@INPUT1@',
+  '--lib-path', join_paths(module_dir, icd_file_name),
+  '--out', '@OUTPUT@',
+]
+if with_platform_windows
+  icd_command += '--use-backslash'
+endif
+
 lvp_icd = custom_target(
   'lvp_icd',
   input : [vk_icd_gen, vk_api_xml],
   output : 'lvp_icd.@0@.json'.format(host_machine.cpu()),
-  command : [
-prog_python, '@INPUT0@',
-'--api-version', '1.1', '--xml', '@INPUT1@',
-'--lib-path', join_paths(module_dir, icd_file_name),
-'--out', '@OUTPUT@',
-  ],
+  command : icd_command,
   build_by_default : true,
   install_dir : with_vulkan_icd_dir,
   install : true,

Mesa (main): docs: update calendar and link releases notes for 22.0.4

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: e6981d6da2312cedf2381552d0f8413a9fcf97d4
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=e6981d6da2312cedf2381552d0f8413a9fcf97d4

Author: Dylan Baker 
Date:   Thu May 19 14:57:47 2022 -0700

docs: update calendar and link releases notes for 22.0.4

Part-of: 

---

 docs/release-calendar.csv | 3 +--
 docs/relnotes.rst | 2 ++
 2 files changed, 3 insertions(+), 2 deletions(-)

diff --git a/docs/release-calendar.csv b/docs/release-calendar.csv
index f6e104551d1..3d86b6c0f6d 100644
--- a/docs/release-calendar.csv
+++ b/docs/release-calendar.csv
@@ -1,5 +1,4 @@
-22.0,2022-05-18,22.0.4,Dylan Baker,
-,2022-06-01,22.0.5,Dylan Baker,This is the last planned release of the 22.0.x 
series.
+22.0,2022-06-01,22.0.5,Dylan Baker,This is the last planned release of the 
22.0.x series.
 22.1,2022-06-01,22.1.1,Dylan Baker
 ,2022-06-15,22.1.2,Dylan Baker
 ,2022-06-29,22.1.3,Dylan Baker,
diff --git a/docs/relnotes.rst b/docs/relnotes.rst
index c6eee26cc68..79c829d5b2f 100644
--- a/docs/relnotes.rst
+++ b/docs/relnotes.rst
@@ -3,6 +3,7 @@ Release Notes
 
 The release notes summarize what's new or changed in each Mesa release.
 
+-  :doc:`22.0.4 release notes `
 -  :doc:`22.1.0 release notes `
 -  :doc:`22.0.3 release notes `
 -  :doc:`22.0.2 release notes `
@@ -362,6 +363,7 @@ release notes, or in the `old docs`_.
:maxdepth: 1
:hidden:
 
+   relnotes/22.0.4
relnotes/22.1.0
relnotes/22.0.3
relnotes/22.0.2

Mesa (main): docs: add sha256sum to 22.0.4 notes

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 569553f7c4b553754e39ee091af802b6cc7e0034
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=569553f7c4b553754e39ee091af802b6cc7e0034

Author: Dylan Baker 
Date:   Thu May 19 14:21:30 2022 -0700

docs: add sha256sum to 22.0.4 notes

Part-of: 

---

 docs/relnotes/22.0.4.rst | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/docs/relnotes/22.0.4.rst b/docs/relnotes/22.0.4.rst
index fe51dea45ac..683d72ed887 100644
--- a/docs/relnotes/22.0.4.rst
+++ b/docs/relnotes/22.0.4.rst
@@ -19,7 +19,7 @@ SHA256 checksum
 
 ::
 
-TBD.
+   c7971f58fa826e474617cda53250c6600fce60994b9fac5b641522e21f471ed4  
mesa-22.0.4.tar.xz
 
 
 New features

Mesa (main): docs: add release notes for 22.0.4

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 3cfcb3a1e07387c803a3500954e02c5b26663b21
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=3cfcb3a1e07387c803a3500954e02c5b26663b21

Author: Dylan Baker 
Date:   Thu May 19 11:06:58 2022 -0700

docs: add release notes for 22.0.4

Part-of: 

---

 docs/relnotes/22.0.4.rst | 152 +++
 1 file changed, 152 insertions(+)

diff --git a/docs/relnotes/22.0.4.rst b/docs/relnotes/22.0.4.rst
new file mode 100644
index 000..fe51dea45ac
--- /dev/null
+++ b/docs/relnotes/22.0.4.rst
@@ -0,0 +1,152 @@
+Mesa 22.0.4 Release Notes / 2022-05-19
+==
+
+Mesa 22.0.4 is a bug fix release which fixes bugs found since the 22.0.3 
release.
+
+Mesa 22.0.4 implements the OpenGL 4.6 API, but the version reported by
+glGetString(GL_VERSION) or glGetIntegerv(GL_MAJOR_VERSION) /
+glGetIntegerv(GL_MINOR_VERSION) depends on the particular driver being used.
+Some drivers don't support all the features required in OpenGL 4.6. OpenGL
+4.6 is **only** available if requested at context creation.
+Compatibility contexts may report a lower version depending on each driver.
+
+Mesa 22.0.4 implements the Vulkan 1.2 API, but the version reported by
+the apiVersion property of the VkPhysicalDeviceProperties struct
+depends on the particular driver being used.
+
+SHA256 checksum
+---
+
+::
+
+TBD.
+
+
+New features
+
+
+- None
+
+
+Bug fixes
+-
+
+- turnip: gfxbench mh3.1 offscreen crash with ANGLE
+- [radv] DCC causes artifacts in Senran Kagura Shinovi Versus
+- Radeon RX 5700XT crash when using prusa-slicer
+- clover: Assertion \`NumContainedTys && "Attempting to get element type of 
opaque pointer"' failed
+
+
+Changes
+---
+
+Alyssa Rosenzweig (1):
+
+- nir: Don't set writes_memory for reading XFB
+
+Chia-I Wu (1):
+
+- anv: advertise rectangularLines only for Gen10+
+
+Danylo Piliaiev (3):
+
+- tu: Fix indices of drm_msm_gem_submit_cmd when filling them
+- tu: Do not flush ccu in clear/blits during renderpass
+- pps: Open writable renderer node in DrmDevice::create
+
+Dylan Baker (17):
+
+- docs: Add sh256sum for mesa 20.0.3
+- .pick_status.json: Update to 7f91e8fad94dd34f83c6a124dbbe5d210be7715f
+- .pick_status.json: Update to 14b1ed1ce105d42652f70e2fd13c90fc4f2e7ffc
+- .pick_status.json: Mark 69e6417e19793043e4bb3cd500cfcf377bce4c03 as 
denominated
+- .pick_status.json: Mark c025cb9ee9d79ebfb66a577556e04deecfe012ed as 
denominated
+- .pick_status.json: Mark 6317f88b044501354a052064478d5b43dfe41809 as 
denominated
+- .pick_status.json: Mark 5ff3fa5912778adb8117fa26bfe4786b583e741b as 
denominated
+- .pick_status.json: Mark 9a412c10b7a96adf71c9a2ca44a0abca75de1c49 as 
denominated
+- .pick_status.json: Mark 0e49ef5c9f2ec34567613226ad498edca28bce88 as 
denominated
+- .pick_status.json: Mark ae369e9f6d4f2c826f1f2a748c32a14f9d5f1f54 as 
denominated
+- .pick_status.json: Update to 14b1ed1ce105d42652f70e2fd13c90fc4f2e7ffc
+- .pick_status.json: Mark 8c1d9c7b744b2e5b40fd42cfd51256b16deea6a8 as 
denominated
+- .pick_status.json: Mark f1d1371e512e32d03f7f54d873020e589ee67d47 as 
denominated
+- .pick_status.json: Update to 57293dee2b11ba7e52052edc4d0437f08db19144
+- .pick_status.json: Update to 5c90eb1c53f46e86717c6bf4d5253dd23c4dac1f
+- .pick_status.json: Mark 5a3aee78cbb70918b413cdd40dffcae7c9e97d8c as 
denominated
+- ci: Some panfrost tests are unexpectedly passing.
+
+Georg Lehmann (1):
+
+- nir/opt_algebraic: Fix mask in shift by constant combining.
+
+Icecream95 (6):
+
+- nir/lower_tex: Copy more fields in lower_tex_to_txd and friends
+- pan/mdg: Keep min_bound at 16 when alignment requires it
+- pan/mdg: Use MAX2 to set min_alignment
+- pan/mdg: Fix mask usage when filling before a spill
+- pan/mdg: Return the instruction from mir_insert_instruction_*_scheduled
+- pan/mdg: Fix multiple spilt writes in the same bundle
+
+Jason Ekstrand (4):
+
+- vulkan/wsi: Set the right stage flags for semaphore waits
+- gallium/u_threaded_context: Use PIPE_MAX_SHADER_SAMPLER_VIEWS for 
sampler_buffers
+- nir/cf: Return a cursor from nir_cf_extract as well
+- nir: Preserve metadata if remove_dead_derefs makes no progress
+
+Lionel Landwerlin (4):
+
+- nir/cf: return cursor after insertion of cf_list
+- nir/lower_shader_calls: don't use nop instructions as cursors
+- nir/lower_shader_calls: don't insert code after break/continue
+- nir/lower_shader_calls: put inserted instructions into a dummy block
+
+Marcin Ślusarz (2):
+
+- anv: update task/mesh distribution with the recommended values
+- anv: disable streamout before emitting mesh shading state
+
+Marek Olšák (2):
+
+- ac/llvm: set the correct cache policy for sparse buffer loads
+- radeonsi: fix a crash when failing to create a context
+
+Mike Blumenkrantz (14):
+
+- util/blitter: fix sampler restore with 0 saved samplers
+- st/draw_feedback: set constant buffer stride
+- llvmpipe: a

Mesa (main): docs: Extend calendar entries for 22.0 by 1 releases.

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: f0e3c71c9694618963814e3278a5cb4a1aa27e50
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=f0e3c71c9694618963814e3278a5cb4a1aa27e50

Author: Dylan Baker 
Date:   Thu May 19 14:57:38 2022 -0700

docs: Extend calendar entries for 22.0 by 1 releases.

Part-of: 

---

 docs/release-calendar.csv | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/docs/release-calendar.csv b/docs/release-calendar.csv
index 6caa72a7aad..f6e104551d1 100644
--- a/docs/release-calendar.csv
+++ b/docs/release-calendar.csv
@@ -1,4 +1,5 @@
-22.0,2022-05-18,22.0.4,Dylan Baker,This is the last planned release of the 
22.0.x series.
+22.0,2022-05-18,22.0.4,Dylan Baker,
+,2022-06-01,22.0.5,Dylan Baker,This is the last planned release of the 22.0.x 
series.
 22.1,2022-06-01,22.1.1,Dylan Baker
 ,2022-06-15,22.1.2,Dylan Baker
 ,2022-06-29,22.1.3,Dylan Baker,

Mesa (main): egl: Fix EGL_EXT_platform_xcb name string to match the registry

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: d6b943addeb72a1309b449cea42f4908b17a75d0
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=d6b943addeb72a1309b449cea42f4908b17a75d0

Author: Nicolas Caramelli 
Date:   Thu May 19 16:58:05 2022 +0200

egl: Fix EGL_EXT_platform_xcb name string to match the registry

Signed-off-by: Nicolas Caramelli 
Part-of: 

---

 docs/_extra/specs/enums.txt | 2 +-
 src/egl/main/eglglobals.c   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/docs/_extra/specs/enums.txt b/docs/_extra/specs/enums.txt
index 07c7ca0f9d6..09211c92303 100644
--- a/docs/_extra/specs/enums.txt
+++ b/docs/_extra/specs/enums.txt
@@ -100,7 +100,7 @@ EGL_WL_bind_wayland_display
 EGL_TEXTURE_Y_XUXV_WL   0x31D9
 EGL_WAYLAND_Y_INVERTED_WL   0x31DB
 
-EGL_MESA_platform_xcb
+EGL_EXT_platform_xcb
 
 EGL_PLATFORM_XCB_EXT0x31DC
 EGL_PLATFORM_XCB_SCREEN_EXT 0x31DE
diff --git a/src/egl/main/eglglobals.c b/src/egl/main/eglglobals.c
index 8d815967f90..a3f5484a2ff 100644
--- a/src/egl/main/eglglobals.c
+++ b/src/egl/main/eglglobals.c
@@ -91,7 +91,7 @@ struct _egl_global _eglGlobal =
" EGL_KHR_platform_x11"
 #endif
 #ifdef HAVE_XCB_PLATFORM
-   " EGL_MESA_platform_xcb"
+   " EGL_EXT_platform_xcb"
 #endif
 #ifdef HAVE_DRM_PLATFORM
" EGL_MESA_platform_gbm"

Mesa (main): zink: update radv baseline

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 2fbbb8ad631cfbe67345683233b57dcaef8a295e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2fbbb8ad631cfbe67345683233b57dcaef8a295e

Author: Mike Blumenkrantz 
Date:   Thu May 19 19:50:25 2022 -0400

zink: update radv baseline

Part-of: 

---

 src/gallium/drivers/zink/ci/zink-radv-fails.txt | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/src/gallium/drivers/zink/ci/zink-radv-fails.txt 
b/src/gallium/drivers/zink/ci/zink-radv-fails.txt
index 1a0afd19382..91295e22c4c 100644
--- a/src/gallium/drivers/zink/ci/zink-radv-fails.txt
+++ b/src/gallium/drivers/zink/ci/zink-radv-fails.txt
@@ -1,10 +1,3 @@
-# probable ACO bug: #6276
-KHR-GL46.shader_storage_buffer_object.basic-operations-case1-cs,Fail
-KHR-GL46.shader_storage_buffer_object.basic-operations-case1-vs,Fail
-
-# probable sparse binding bug: #6245
-KHR-GL46.sparse_buffer_tests.BufferStorageTest,Fail
-
 # 3D isn't supported by radv yet: #5822
 KHR-GL46.sparse_texture_tests.InternalFormatQueries,Fail
 KHR-GL46.sparse_texture_tests.SparseTextureAllocation,Fail

Mesa (add_assert): zink: update radv baseline

[GitLab Mirror]

Module: Mesa
Branch: add_assert
Commit: 2fbbb8ad631cfbe67345683233b57dcaef8a295e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2fbbb8ad631cfbe67345683233b57dcaef8a295e

Author: Mike Blumenkrantz 
Date:   Thu May 19 19:50:25 2022 -0400

zink: update radv baseline

Part-of: 

---

 src/gallium/drivers/zink/ci/zink-radv-fails.txt | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/src/gallium/drivers/zink/ci/zink-radv-fails.txt 
b/src/gallium/drivers/zink/ci/zink-radv-fails.txt
index 1a0afd19382..91295e22c4c 100644
--- a/src/gallium/drivers/zink/ci/zink-radv-fails.txt
+++ b/src/gallium/drivers/zink/ci/zink-radv-fails.txt
@@ -1,10 +1,3 @@
-# probable ACO bug: #6276
-KHR-GL46.shader_storage_buffer_object.basic-operations-case1-cs,Fail
-KHR-GL46.shader_storage_buffer_object.basic-operations-case1-vs,Fail
-
-# probable sparse binding bug: #6245
-KHR-GL46.sparse_buffer_tests.BufferStorageTest,Fail
-
 # 3D isn't supported by radv yet: #5822
 KHR-GL46.sparse_texture_tests.InternalFormatQueries,Fail
 KHR-GL46.sparse_texture_tests.SparseTextureAllocation,Fail

Mesa (radv_fix_assertion): zink: update radv baseline

[GitLab Mirror]

Module: Mesa
Branch: radv_fix_assertion
Commit: 2fbbb8ad631cfbe67345683233b57dcaef8a295e
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=2fbbb8ad631cfbe67345683233b57dcaef8a295e

Author: Mike Blumenkrantz 
Date:   Thu May 19 19:50:25 2022 -0400

zink: update radv baseline

Part-of: 

---

 src/gallium/drivers/zink/ci/zink-radv-fails.txt | 7 ---
 1 file changed, 7 deletions(-)

diff --git a/src/gallium/drivers/zink/ci/zink-radv-fails.txt 
b/src/gallium/drivers/zink/ci/zink-radv-fails.txt
index 1a0afd19382..91295e22c4c 100644
--- a/src/gallium/drivers/zink/ci/zink-radv-fails.txt
+++ b/src/gallium/drivers/zink/ci/zink-radv-fails.txt
@@ -1,10 +1,3 @@
-# probable ACO bug: #6276
-KHR-GL46.shader_storage_buffer_object.basic-operations-case1-cs,Fail
-KHR-GL46.shader_storage_buffer_object.basic-operations-case1-vs,Fail
-
-# probable sparse binding bug: #6245
-KHR-GL46.sparse_buffer_tests.BufferStorageTest,Fail
-
 # 3D isn't supported by radv yet: #5822
 KHR-GL46.sparse_texture_tests.InternalFormatQueries,Fail
 KHR-GL46.sparse_texture_tests.SparseTextureAllocation,Fail

Mesa (main): radeonsi: lower nir_intrinsic_sparse_residency_code_and

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: cc4d5b16661a156e6b3aa4170f7d8f7919efc270
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=cc4d5b16661a156e6b3aa4170f7d8f7919efc270

Author: Qiang Yu 
Date:   Wed May 18 11:17:20 2022 +0800

radeonsi: lower nir_intrinsic_sparse_residency_code_and

This is required by lower_tg4_offsets which split one
sparseTextureGatherOffsetsARB call to four sparseTextureGatherOffsetARB
calls and merge their resisident results into one.

Fixes: ee040a6b639 ("radeonsi: enable ARB_sparse_texture2")

Reviewed-by: Marek Olšák 
Signed-off-by: Qiang Yu 
Part-of: 

---

 src/gallium/drivers/radeonsi/si_shader_nir.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_shader_nir.c 
b/src/gallium/drivers/radeonsi/si_shader_nir.c
index d3bbc864b6e..612e75b8130 100644
--- a/src/gallium/drivers/radeonsi/si_shader_nir.c
+++ b/src/gallium/drivers/radeonsi/si_shader_nir.c
@@ -205,6 +205,8 @@ lower_intrinsic_instr(nir_builder *b, nir_instr *instr, 
void *dummy)
case nir_intrinsic_is_sparse_texels_resident:
   /* code==0 means sparse texels are resident */
   return nir_ieq_imm(b, intrin->src[0].ssa, 0);
+   case nir_intrinsic_sparse_residency_code_and:
+  return nir_ior(b, intrin->src[0].ssa, intrin->src[1].ssa);
default:
   return NULL;
}

Mesa (main): lavapipe: Use the common BindVertexBuffers wrapper

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: b58dd252aaa5b99ebae719018874994897ffd39b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=b58dd252aaa5b99ebae719018874994897ffd39b

Author: Jason Ekstrand 
Date:   Thu May 19 11:12:46 2022 -0500

lavapipe: Use the common BindVertexBuffers wrapper

Reviewed-by: Mike Blumenkrantz 
Part-of: 

---

 src/gallium/frontends/lavapipe/lvp_execute.c | 61 +++-
 1 file changed, 15 insertions(+), 46 deletions(-)

diff --git a/src/gallium/frontends/lavapipe/lvp_execute.c 
b/src/gallium/frontends/lavapipe/lvp_execute.c
index 2253744778f..8519ce29106 100644
--- a/src/gallium/frontends/lavapipe/lvp_execute.c
+++ b/src/gallium/frontends/lavapipe/lvp_execute.c
@@ -964,56 +964,29 @@ static void handle_pipeline(struct vk_cmd_queue_entry 
*cmd,
state->push_size[pipeline->is_compute_pipeline] = 
pipeline->layout->push_constant_size;
 }
 
-static void vertex_buffers(uint32_t first_binding,
-   uint32_t binding_count,
-   const VkBuffer *buffers,
-   const VkDeviceSize *offsets,
-   const VkDeviceSize *strides,
-   struct rendering_state *state)
+static void handle_vertex_buffers2(struct vk_cmd_queue_entry *cmd,
+   struct rendering_state *state)
 {
+   struct vk_cmd_bind_vertex_buffers2 *vcb = &cmd->u.bind_vertex_buffers2;
+
int i;
-   for (i = 0; i < binding_count; i++) {
-  int idx = i + first_binding;
+   for (i = 0; i < vcb->binding_count; i++) {
+  int idx = i + vcb->first_binding;
 
-  state->vb[idx].buffer_offset = offsets[i];
-  state->vb[idx].buffer.resource = buffers[i] ? 
lvp_buffer_from_handle(buffers[i])->bo : NULL;
+  state->vb[idx].buffer_offset = vcb->offsets[i];
+  state->vb[idx].buffer.resource =
+ vcb->buffers[i] ? lvp_buffer_from_handle(vcb->buffers[i])->bo : NULL;
 
-  if (strides)
- state->vb[idx].stride = strides[i];
+  if (vcb->strides)
+ state->vb[idx].stride = vcb->strides[i];
}
-   if (first_binding < state->start_vb)
-  state->start_vb = first_binding;
-   if (first_binding + binding_count >= state->num_vb)
-  state->num_vb = first_binding + binding_count;
+   if (vcb->first_binding < state->start_vb)
+  state->start_vb = vcb->first_binding;
+   if (vcb->first_binding + vcb->binding_count >= state->num_vb)
+  state->num_vb = vcb->first_binding + vcb->binding_count;
state->vb_dirty = true;
 }
 
-static void handle_vertex_buffers(struct vk_cmd_queue_entry *cmd,
-  struct rendering_state *state)
-{
-   struct vk_cmd_bind_vertex_buffers *vcb = &cmd->u.bind_vertex_buffers;
-
-   vertex_buffers(vcb->first_binding,
-  vcb->binding_count,
-  vcb->buffers,
-  vcb->offsets,
-  NULL,
-  state);
-}
-
-static void handle_vertex_buffers2(struct vk_cmd_queue_entry *cmd,
-   struct rendering_state *state)
-{
-   struct vk_cmd_bind_vertex_buffers2 *vcb = &cmd->u.bind_vertex_buffers2;
-
-   vertex_buffers(vcb->first_binding,
-  vcb->binding_count,
-  vcb->buffers,
-  vcb->offsets,
-  vcb->strides,
-  state);
-}
-
 struct dyn_info {
struct {
   uint16_t const_buffer_count;
@@ -3678,7 +3651,6 @@ void lvp_add_enqueue_cmd_entrypoints(struct 
vk_device_dispatch_table *disp)
ENQUEUE_CMD(CmdSetStencilReference)
ENQUEUE_CMD(CmdBindDescriptorSets)
ENQUEUE_CMD(CmdBindIndexBuffer)
-   ENQUEUE_CMD(CmdBindVertexBuffers)
ENQUEUE_CMD(CmdBindVertexBuffers2)
ENQUEUE_CMD(CmdDraw)
ENQUEUE_CMD(CmdDrawMultiEXT)
@@ -3798,9 +3770,6 @@ static void lvp_execute_cmd_buffer(struct lvp_cmd_buffer 
*cmd_buffer,
   case VK_CMD_BIND_INDEX_BUFFER:
  handle_index_buffer(cmd, state);
  break;
-  case VK_CMD_BIND_VERTEX_BUFFERS:
- handle_vertex_buffers(cmd, state);
- break;
   case VK_CMD_BIND_VERTEX_BUFFERS2:
  handle_vertex_buffers2(cmd, state);
  break;

Mesa (main): vulkan,anv,turnip: Add a common CmdBindVertexBuffers wrapper

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: c24aa449d0ff784adaea6310657f4eef72ac3594
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=c24aa449d0ff784adaea6310657f4eef72ac3594

Author: Jason Ekstrand 
Date:   Thu May 19 11:10:23 2022 -0500

vulkan,anv,turnip: Add a common CmdBindVertexBuffers wrapper

Part-of: 

---

 src/freedreno/vulkan/tu_cmd_buffer.c   | 11 ---
 src/intel/vulkan/anv_cmd_buffer.c  | 12 
 src/vulkan/runtime/vk_command_buffer.c | 15 +++
 3 files changed, 15 insertions(+), 23 deletions(-)

diff --git a/src/freedreno/vulkan/tu_cmd_buffer.c 
b/src/freedreno/vulkan/tu_cmd_buffer.c
index 8c06f051506..3a291d00d78 100644
--- a/src/freedreno/vulkan/tu_cmd_buffer.c
+++ b/src/freedreno/vulkan/tu_cmd_buffer.c
@@ -1759,17 +1759,6 @@ tu_BeginCommandBuffer(VkCommandBuffer commandBuffer,
return VK_SUCCESS;
 }
 
-VKAPI_ATTR void VKAPI_CALL
-tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
-uint32_t firstBinding,
-uint32_t bindingCount,
-const VkBuffer *pBuffers,
-const VkDeviceSize *pOffsets)
-{
-   tu_CmdBindVertexBuffers2EXT(commandBuffer, firstBinding, bindingCount,
-   pBuffers, pOffsets, NULL, NULL);
-}
-
 VKAPI_ATTR void VKAPI_CALL
 tu_CmdBindVertexBuffers2EXT(VkCommandBuffer commandBuffer,
 uint32_t firstBinding,
diff --git a/src/intel/vulkan/anv_cmd_buffer.c 
b/src/intel/vulkan/anv_cmd_buffer.c
index e549cdcc4cb..80efd6af21b 100644
--- a/src/intel/vulkan/anv_cmd_buffer.c
+++ b/src/intel/vulkan/anv_cmd_buffer.c
@@ -1197,18 +1197,6 @@ void anv_CmdBindVertexBuffers2(
}
 }
 
-void anv_CmdBindVertexBuffers(
-VkCommandBuffer commandBuffer,
-uint32_tfirstBinding,
-uint32_tbindingCount,
-const VkBuffer* pBuffers,
-const VkDeviceSize* pOffsets)
-{
-   return anv_CmdBindVertexBuffers2(commandBuffer, firstBinding,
-bindingCount, pBuffers, pOffsets,
-NULL, NULL);
-}
-
 void anv_CmdBindTransformFeedbackBuffersEXT(
 VkCommandBuffer commandBuffer,
 uint32_tfirstBinding,
diff --git a/src/vulkan/runtime/vk_command_buffer.c 
b/src/vulkan/runtime/vk_command_buffer.c
index 5675b73440b..477562ee8fb 100644
--- a/src/vulkan/runtime/vk_command_buffer.c
+++ b/src/vulkan/runtime/vk_command_buffer.c
@@ -81,3 +81,18 @@ vk_common_CmdExecuteCommands(VkCommandBuffer commandBuffer,
   vk_cmd_queue_execute(&secondary->cmd_queue, commandBuffer, disp);
}
 }
+
+VKAPI_ATTR void VKAPI_CALL
+vk_common_CmdBindVertexBuffers(VkCommandBuffer commandBuffer,
+   uint32_t firstBinding,
+   uint32_t bindingCount,
+   const VkBuffer *pBuffers,
+   const VkDeviceSize *pOffsets)
+{
+   VK_FROM_HANDLE(vk_command_buffer, cmd_buffer, commandBuffer);
+   const struct vk_device_dispatch_table *disp =
+  &cmd_buffer->base.device->dispatch_table;
+
+   disp->CmdBindVertexBuffers2(commandBuffer, firstBinding, bindingCount,
+   pBuffers, pOffsets, NULL, NULL);
+}

Mesa (main): radv: Use the common CmdBindVertexBuffers wrapper

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: a299e5efbb4a4d8675a2a871b19d6f2ea9ba5b25
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=a299e5efbb4a4d8675a2a871b19d6f2ea9ba5b25

Author: Jason Ekstrand 
Date:   Thu May 19 11:28:51 2022 -0500

radv: Use the common CmdBindVertexBuffers wrapper

Reviewed-by: Samuel Pitoiset 
Part-of: 

---

 src/amd/vulkan/layers/radv_sqtt_layer.c | 8 
 src/amd/vulkan/radv_cmd_buffer.c| 9 -
 2 files changed, 17 deletions(-)

diff --git a/src/amd/vulkan/layers/radv_sqtt_layer.c 
b/src/amd/vulkan/layers/radv_sqtt_layer.c
index b22c5c14a2b..e56991cb264 100644
--- a/src/amd/vulkan/layers/radv_sqtt_layer.c
+++ b/src/amd/vulkan/layers/radv_sqtt_layer.c
@@ -644,14 +644,6 @@ sqtt_CmdBindIndexBuffer(VkCommandBuffer commandBuffer, 
VkBuffer buffer, VkDevice
API_MARKER(BindIndexBuffer, commandBuffer, buffer, offset, indexType);
 }
 
-VKAPI_ATTR void VKAPI_CALL
-sqtt_CmdBindVertexBuffers(VkCommandBuffer commandBuffer, uint32_t firstBinding,
-  uint32_t bindingCount, const VkBuffer *pBuffers,
-  const VkDeviceSize *pOffsets)
-{
-   API_MARKER(BindVertexBuffers, commandBuffer, firstBinding, bindingCount, 
pBuffers, pOffsets);
-}
-
 VKAPI_ATTR void VKAPI_CALL
 sqtt_CmdBindVertexBuffers2(VkCommandBuffer commandBuffer, uint32_t 
firstBinding,
uint32_t bindingCount, const VkBuffer *pBuffers,
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 1fb960c73ac..8ccdc19e640 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -4702,15 +4702,6 @@ radv_BeginCommandBuffer(VkCommandBuffer commandBuffer, 
const VkCommandBufferBegi
return result;
 }
 
-VKAPI_ATTR void VKAPI_CALL
-radv_CmdBindVertexBuffers(VkCommandBuffer commandBuffer, uint32_t firstBinding,
-  uint32_t bindingCount, const VkBuffer *pBuffers,
-  const VkDeviceSize *pOffsets)
-{
-   radv_CmdBindVertexBuffers2(commandBuffer, firstBinding, bindingCount, 
pBuffers, pOffsets,
-  NULL, NULL);
-}
-
 VKAPI_ATTR void VKAPI_CALL
 radv_CmdBindVertexBuffers2(VkCommandBuffer commandBuffer, uint32_t 
firstBinding,
uint32_t bindingCount, const VkBuffer *pBuffers,

Mesa (main): radv: Add a sqtt entrypoint for CmdBindVertexBuffers2

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 50a00f889c6d5593c89554452c177a3873fe673f
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=50a00f889c6d5593c89554452c177a3873fe673f

Author: Jason Ekstrand 
Date:   Thu May 19 11:28:03 2022 -0500

radv: Add a sqtt entrypoint for CmdBindVertexBuffers2

Fixes: b2622843003e ("radv: add support for dynamic vertex input binding 
stride")
Reviewed-by: Samuel Pitoiset 
Part-of: 

---

 src/amd/vulkan/layers/radv_sqtt_layer.c | 10 ++
 1 file changed, 10 insertions(+)

diff --git a/src/amd/vulkan/layers/radv_sqtt_layer.c 
b/src/amd/vulkan/layers/radv_sqtt_layer.c
index e52ae4086b3..b22c5c14a2b 100644
--- a/src/amd/vulkan/layers/radv_sqtt_layer.c
+++ b/src/amd/vulkan/layers/radv_sqtt_layer.c
@@ -652,6 +652,16 @@ sqtt_CmdBindVertexBuffers(VkCommandBuffer commandBuffer, 
uint32_t firstBinding,
API_MARKER(BindVertexBuffers, commandBuffer, firstBinding, bindingCount, 
pBuffers, pOffsets);
 }
 
+VKAPI_ATTR void VKAPI_CALL
+sqtt_CmdBindVertexBuffers2(VkCommandBuffer commandBuffer, uint32_t 
firstBinding,
+   uint32_t bindingCount, const VkBuffer *pBuffers,
+   const VkDeviceSize *pOffsets, const VkDeviceSize* 
pSizes,
+   const VkDeviceSize* pStrides)
+{
+   API_MARKER_ALIAS(BindVertexBuffers2, BindVertexBuffers, commandBuffer, 
firstBinding,
+bindingCount, pBuffers, pOffsets, pSizes, pStrides);
+}
+
 VKAPI_ATTR void VKAPI_CALL
 sqtt_CmdBeginQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, 
uint32_t query,
VkQueryControlFlags flags)

Mesa (main): radv: Fix RTPSO hashing of pGroups.

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 04459c82874b648a9c3ed4c9384b831772bb07e6
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=04459c82874b648a9c3ed4c9384b831772bb07e6

Author: Hans-Kristian Arntzen 
Date:   Wed May 18 15:44:30 2022 +0200

radv: Fix RTPSO hashing of pGroups.

There are padding bytes here. Only hash relevant members.

Fixes: ca2d96db51e ("radv: Add caching for RT pipelines.")
Signed-off-by: Hans-Kristian Arntzen 
Reviewed-by: Georg Lehmann 
Reviewed-by: Samuel Pitoiset 
Part-of: 

---

 src/amd/vulkan/radv_pipeline_cache.c | 14 --
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_pipeline_cache.c 
b/src/amd/vulkan/radv_pipeline_cache.c
index cce39e5a66d..fb7f33934b9 100644
--- a/src/amd/vulkan/radv_pipeline_cache.c
+++ b/src/amd/vulkan/radv_pipeline_cache.c
@@ -164,8 +164,18 @@ radv_hash_rt_shaders(unsigned char *hash, const 
VkRayTracingPipelineCreateInfoKH
   }
}
 
-   _mesa_sha1_update(&ctx, pCreateInfo->pGroups,
- pCreateInfo->groupCount * sizeof(*pCreateInfo->pGroups));
+   for (uint32_t i = 0; i < pCreateInfo->groupCount; i++) {
+  _mesa_sha1_update(&ctx, &pCreateInfo->pGroups[i].type,
+sizeof(pCreateInfo->pGroups[i].type));
+  _mesa_sha1_update(&ctx, &pCreateInfo->pGroups[i].generalShader,
+sizeof(pCreateInfo->pGroups[i].generalShader));
+  _mesa_sha1_update(&ctx, &pCreateInfo->pGroups[i].anyHitShader,
+sizeof(pCreateInfo->pGroups[i].anyHitShader));
+  _mesa_sha1_update(&ctx, &pCreateInfo->pGroups[i].closestHitShader,
+sizeof(pCreateInfo->pGroups[i].closestHitShader));
+  _mesa_sha1_update(&ctx, &pCreateInfo->pGroups[i].intersectionShader,
+sizeof(pCreateInfo->pGroups[i].intersectionShader));
+   }
 
if (!radv_rt_pipeline_has_dynamic_stack_size(pCreateInfo))
   _mesa_sha1_update(&ctx, &pCreateInfo->maxPipelineRayRecursionDepth, 4);