Mesa (main): intel/fs/xehp+: Emit scheduling fence for all NIR barriers on platforms with LSC.

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 96e7e92f0dca44cc47b22e2e1a60e69eca632873
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=96e7e92f0dca44cc47b22e2e1a60e69eca632873

Author: Francisco Jerez 
Date:   Wed Apr 27 09:20:21 2022 +0300

intel/fs/xehp+: Emit scheduling fence for all NIR barriers on platforms with 
LSC.

Tested-by: Lionel Landwerlin 
Reviewed-by: Jason Ekstrand 
Part-of: 

---

 src/intel/compiler/brw_fs_nir.cpp | 6 --
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index 86121d42149..9864acbea6f 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -4623,7 +4623,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, 
nir_intrinsic_instr *instr
 
   assert(fence_regs_count <= ARRAY_SIZE(fence_regs));
 
-  /* There are three cases where we want to insert a stall:
+  /* There are four cases where we want to insert a stall:
*
*  1. If we're a nir_intrinsic_end_invocation_interlock.  This is
* required to ensure that the shader EOT doesn't happen until
@@ -4637,9 +4637,11 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, 
nir_intrinsic_instr *instr
*  3. If we have no fences.  In this case, we need at least a
* scheduling barrier to keep the compiler from moving things
* around in an invalid way.
+   *
+   *  4. On platforms with LSC.
*/
   if (instr->intrinsic == nir_intrinsic_end_invocation_interlock ||
-  fence_regs_count != 1) {
+  fence_regs_count != 1 || devinfo->has_lsc) {
  ubld.exec_all().group(1, 0).emit(
 FS_OPCODE_SCHEDULING_FENCE, ubld.null_reg_ud(),
 fence_regs, fence_regs_count);

Mesa (main): intel/fs: setup SEND message descriptor from nir scope

[GitLab Mirror]

Module: Mesa
Branch: main
Commit: 47773a5d7c85733c1d007a7374e9373ee354bd1b
URL:
http://cgit.freedesktop.org/mesa/mesa/commit/?id=47773a5d7c85733c1d007a7374e9373ee354bd1b

Author: Tapani Pälli 
Date:   Tue Apr  5 07:59:51 2022 +0300

intel/fs: setup SEND message descriptor from nir scope

This fixes many tests in following groups on DG2:
   dEQP-VK.memory_model.*
   dEQP-VK.fragment_shader_interlock.*

v2: use memory scope and setup descriptor also
for barriers without defined scope (Curro),
use local scope and flush type none with
NIR_SCOPE_NONE scope, cleanups (Lionel)

v3: use LSC_FENCE_THREADGROUP for NIR_SCOPE_WORKGROUP,
remove default case (Curro), use eviction if scope
was not defined, use LSC_FENCE_GPU scope for vertex
stage

v4: use LSC_FENCE_TILE independent of stage for device
scope (Curro)

Signed-off-by: Tapani Pälli 
Reviewed-by: Lionel Landwerlin 
Part-of: 

---

 src/intel/compiler/brw_fs_nir.cpp | 57 ---
 1 file changed, 48 insertions(+), 9 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index b51435f47c7..86121d42149 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -4229,7 +4229,8 @@ increment_a64_address(const fs_builder &bld, fs_reg 
address, uint32_t v)
 
 static fs_reg
 emit_fence(const fs_builder &bld, enum opcode opcode,
-   uint8_t sfid, bool commit_enable, uint8_t bti)
+   uint8_t sfid, uint32_t desc,
+   bool commit_enable, uint8_t bti)
 {
assert(opcode == SHADER_OPCODE_INTERLOCK ||
   opcode == SHADER_OPCODE_MEMORY_FENCE);
@@ -4239,9 +4240,45 @@ emit_fence(const fs_builder &bld, enum opcode opcode,
  brw_imm_ud(commit_enable),
  brw_imm_ud(bti));
fence->sfid = sfid;
+   fence->desc = desc;
+
return dst;
 }
 
+static uint32_t
+lsc_fence_descriptor_for_intrinsic(const struct intel_device_info *devinfo,
+   nir_intrinsic_instr *instr)
+{
+   assert(devinfo->has_lsc);
+
+   enum lsc_fence_scope scope = LSC_FENCE_LOCAL;
+   enum lsc_flush_type flush_type = LSC_FLUSH_TYPE_NONE;
+
+   if (nir_intrinsic_has_memory_scope(instr)) {
+  switch (nir_intrinsic_memory_scope(instr)) {
+  case NIR_SCOPE_DEVICE:
+  case NIR_SCOPE_QUEUE_FAMILY:
+ scope = LSC_FENCE_TILE;
+ flush_type = LSC_FLUSH_TYPE_EVICT;
+ break;
+  case NIR_SCOPE_WORKGROUP:
+ scope = LSC_FENCE_THREADGROUP;
+ flush_type = LSC_FLUSH_TYPE_EVICT;
+ break;
+  case NIR_SCOPE_SHADER_CALL:
+  case NIR_SCOPE_INVOCATION:
+  case NIR_SCOPE_SUBGROUP:
+  case NIR_SCOPE_NONE:
+ break;
+  }
+   } else {
+  /* No scope defined. */
+  scope = LSC_FENCE_TILE;
+  flush_type = LSC_FLUSH_TYPE_EVICT;
+   }
+   return lsc_fence_msg_desc(devinfo, scope, flush_type, true);
+}
+
 void
 fs_visitor::nir_emit_intrinsic(const fs_builder &bld, nir_intrinsic_instr 
*instr)
 {
@@ -4511,16 +4548,18 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, 
nir_intrinsic_instr *instr
 
   if (devinfo->has_lsc) {
  assert(devinfo->verx10 >= 125);
+ uint32_t desc =
+lsc_fence_descriptor_for_intrinsic(devinfo, instr);
  if (ugm_fence) {
 fence_regs[fence_regs_count++] =
-   emit_fence(ubld, opcode, GFX12_SFID_UGM,
+   emit_fence(ubld, opcode, GFX12_SFID_UGM, desc,
   true /* commit_enable */,
   0 /* bti; ignored for LSC */);
  }
 
  if (tgm_fence) {
 fence_regs[fence_regs_count++] =
-   emit_fence(ubld, opcode, GFX12_SFID_TGM,
+   emit_fence(ubld, opcode, GFX12_SFID_TGM, desc,
   true /* commit_enable */,
   0 /* bti; ignored for LSC */);
  }
@@ -4528,7 +4567,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, 
nir_intrinsic_instr *instr
  if (slm_fence) {
 assert(opcode == SHADER_OPCODE_MEMORY_FENCE);
 fence_regs[fence_regs_count++] =
-   emit_fence(ubld, opcode, GFX12_SFID_SLM,
+   emit_fence(ubld, opcode, GFX12_SFID_SLM, desc,
   true /* commit_enable */,
   0 /* BTI; ignored for LSC */);
  }
@@ -4536,14 +4575,14 @@ fs_visitor::nir_emit_intrinsic(const fs_builder &bld, 
nir_intrinsic_instr *instr
  if (urb_fence) {
 assert(opcode == SHADER_OPCODE_MEMORY_FENCE);
 fence_regs[fence_regs_count++] =
-   emit_fence(ubld, opcode, BRW_SFID_URB,
+   emit_fence(ubld, opcode, BRW_SFID_URB, desc,
   true /* commit_enable */,
   0 /* BTI; ignored for LSC */);
  }