[Mesa-dev] [GSoC 13]Interested in the idea: Improved application of GLSL complier optimizations
Hi,
My name is Sida Li and I am a senior student from Peking University in China. I
am interested in the idea that improved application of GLSL complier
optimizations.
I have downloaded the source code and read some parts of the it. First let me
talk about my understanding about the problem.
The loop we try to improve should be in the main.cpp:
do {
progress = do_common_optimization(shader-ir, false, false, 32);
} while (progress);
In the function do_common_optimization, all optimization passes are called in a
certain order. As the loop goes in a few times, some optimization passes do not
contribute to optimizing the code since the original unoptimized code has been
optimized and no more code that can be optimized by these optimization passes
is generated by other optimization passes. So time spending on these
optimization passes is wasted.
The goal is to find a static ordering, with possible repeats, of optimization
passes that does not compromise the quality of the generated code. I find it
difficult to start because a single optimization pass or a combo of
optimization passes may generate some code that can be optimized by other
optimization pass, which can not be decided before.
Can you give me some advice?
Best regards,
Sida Li___
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[Mesa-dev] GSOC 2013
Hello, I am really interested in doing the GSOC 2013 project Find common patterns in real GLSL shaders. Implementation: Algorithm:- Max-miner algorithm as it uses the same data structure as Apriori i.e. hash tree. The following implementation has been found faster than normal ways: Max-Miner uses the hash tree to quickly look up all candidate groups whose head appears in the transaction. Then, for each candidate group g identified, it traverses down its tail items one by one. (Efficiently mining long patterns from database). I would like some reviews on my idea. Thanks Piyush ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radeon/llvm: Use LLVM C API for compiling LLVM IR to ISA.
On Sat, Apr 20, 2013 at 02:20:23PM +0200, Christian König wrote:
Am 20.04.2013 09:27, schrieb Mathias Fröhlich:
Hi Tom,
May be I need to tell where the problem really appears in real life.
OpenSceneGraph has some nifty features regarding multi channel rendering.
Assume a setup of multiple full screen views running on different graphics
boards into a single mashine composing a view into a single scene.
Now the recommended way to do this with osg is to set up a X screen per
graphics board. Even if this spans multiple monitors/projectors. Set up a GL
graphics context per graphics board and set up a viewport per projector in
the
graphics contexts. Rendering happens now in parallel for each graphics
context. I do drive such a thing here with two radeons and three monitors
for
testing and here the problem appears.
When I start the favourite flight simulation application of my choice with
this
setup, then it crashes almost immediately without llvm_start_multithreaded
being called. Wheres it works stable if we ensure llvm being multithreaded.
So, I tried to distill a piglit testcase out of this somehow huger setup
with
flightgear, OpenSceneGraph, multiple gpu's and what not.
On Friday, April 19, 2013 20:08:54 Tom Stellard wrote:
On Wed, Apr 17, 2013 at 07:54:32AM +0200, Mathias Fröhlich wrote:
Tom,
-class LLVMEnsureMultithreaded {
-public:
- LLVMEnsureMultithreaded()
- {
- llvm_start_multithreaded();
- }
-};
-
-static LLVMEnsureMultithreaded lLVMEnsureMultithreaded;
Removing this leads to crashes in llvm with applications that concurrently
work on different gl contexts.
The test you wrote still passes with this patch. Do you see that
we are now calling the C API version of llvm_start_multithreaded(),
LLVMStartMutithreaded() from inside radeon_llvm_compile() protected by a
static variable?
Oh, no I did not see this. I did not realize that the
llvm_start_multithreaded
call is not just plain C. So I thought grepping for the call I used is
sufficient.
But negative. If I really apply your patch and try to run this with the
above
setup I get the crashes. The same with the piglit test here.
Too bad, that reproducing races is racy for itself.
With the piglit test I get about 2/3 of the runs either glibc memory
corruption aborts. Or one of the below asserts from llvm:
bool llvm::llvm_start_multithreaded(): Assertion `!multithreaded_mode
Already multithreaded!' failed.
void
llvm::PassRegistry::removeRegistrationListener(llvm::PassRegistrationListener*):
Assertion `I != Impl-Listeners.end() PassRegistrationListener not
registered!' failed.
bool llvm::sys::SmartMutexmt_only::release() [with bool mt_only = true]:
Assertion `((recursive acquired) || (acquired == 1)) Lock not
acquired
before release!' failed.
So the biggest problem IIRC was that use of llvm::sys::SmartMutexmt_only
which is spread around here and there in llvm. The pass registry was (is?)
one
of the users for that. If you did not tell llvm to run multithreaded these
locks get noops and you concurrently access containers and that ...
Looking at the first assert, the llvm guys have made this problem even worse
IMO since I looked at this before. We need to check for multithreading being
enabled before trying to set this. Both of which being racy for itself in
this
way and all of them not being save against already happening llvm access
from
an other thread and an other foreign use.
Sorry about that. I didn't have piglit commit access at the time, and
I forgot about the patch. I fixed a few things and sent v3 to the list.
The same here. Thanks for this.
Regarding the point where this funciton is called I had choosen static
initialization time since llvm requires this function to be called single
threaded which we cannot guarantee in any case. Keep in mind that you need
to ensure this function called non concurrently even against applications
that itself already use the llvm libs in some way while the driver is
loaded. But the best bet is to do this in the dynamic loder which is
itself serialized, so I could avoid calling this function concurrently by
initialization of different contexts. That should at least shield against
applications that itself do the same trick by calling this funtion in the
dlopen phase in some static initializer ...
We may get around part of this problem with dlopening the driver with
better isolation but up to now the problem can get that far.
This is a tricky problem, and I'm not sure that radeon_llvm_compile() is
the best place to call llvm_start_multithreaded(). Maybe it would be
better to move this into gallivm, because this problem could affect any
driver that uses the gallivm code, which includes: llvmpipe, r300g, r600g,
radeonsi, and i915g. What do you think?
Yep, an other place would be better.
Re: [Mesa-dev] [PATCH] radeon/llvm: Use LLVM C API for compiling LLVM IR to ISA.
Hi all,
On Monday, April 22, 2013 00:39:57 Tom Stellard wrote:
[...]
The only pro for further investigating the dlopen flags is that I fear the
distribution builders who invented dynamic linking in the drivers. That change
destroyed symbol isolation in the drivers at that point. They will probably
argue again about the memory footprint on disc and insist on using the
distribution provided shared llvm at some point, which can only be solved then
with the dlopen approach.
Tom, to untangle your patch in question from symbol isolation, I think if you
put
static void ensure_llvm_is_multithreaded() __attribute__ ((__constructor__));
void ensure_llvm_is_multithreaded()
{
if (LLVMIsMultithreaded())
return;
LLVMStartMultithreaded();
}
into your new created c file, we should be no worse than we were before.
Regarding reproducing the problem at your site:
Does it help to increase the amount of concurrent context creations to a
higher number than the now coded 100?
completely agree with Mathias here. I also suggested on IRC a couple of
weeks ago that libllvmradeon should definitely be static and hide all
internal symbols and only export those needed by the drivers. That
should isolate us mostly from the mess that comes with having multiple
LLVM instances (and probably also different versions) around at the same
time.
How would you recommend doing this? Version scripts?
Probably yes.
Greetings and Thanks
Mathias
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[Mesa-dev] [PATCH 1/4] gallium/dri: Allow drivers to support DRI Image v7
From: Christopher James Halse Rogers r...@ubuntu.com This is only exposed by drivers wich support the new PIPE_CAP_PRIME parameter, for PRIME import/export. --- This stubs out texture_from_renderbuffer, which I don't care about, but that looks like it wouldn't be terribly painful to implement if it's a blocker for the PRIME support, which I do care about. src/gallium/drivers/freedreno/freedreno_screen.c | 1 + src/gallium/drivers/i915/i915_screen.c | 1 + src/gallium/drivers/llvmpipe/lp_screen.c | 2 + src/gallium/drivers/nv30/nv30_screen.c | 1 + src/gallium/drivers/nv50/nv50_screen.c | 2 + src/gallium/drivers/nvc0/nvc0_screen.c | 2 + src/gallium/drivers/r300/r300_screen.c | 1 + src/gallium/drivers/r600/r600_pipe.c | 1 + src/gallium/drivers/radeonsi/radeonsi_pipe.c | 1 + src/gallium/drivers/softpipe/sp_screen.c | 2 + src/gallium/drivers/svga/svga_screen.c | 1 + src/gallium/include/pipe/p_defines.h | 3 +- src/gallium/include/state_tracker/drm_driver.h | 9 +- src/gallium/state_trackers/dri/drm/dri2.c | 120 +++-- .../state_trackers/egl/common/native_helper.c | 1 + src/gallium/state_trackers/egl/x11/native_dri2.c | 1 + 16 files changed, 137 insertions(+), 12 deletions(-) diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 4a9a54e..db122d3 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -201,6 +201,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_USER_INDEX_BUFFERS: case PIPE_CAP_QUERY_PIPELINE_STATISTICS: case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: + case PIPE_CAP_PRIME: return 0; /* Stream output. */ diff --git a/src/gallium/drivers/i915/i915_screen.c b/src/gallium/drivers/i915/i915_screen.c index dfb76b3..6623dca 100644 --- a/src/gallium/drivers/i915/i915_screen.c +++ b/src/gallium/drivers/i915/i915_screen.c @@ -214,6 +214,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap) case PIPE_CAP_TEXTURE_MULTISAMPLE: case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: + case PIPE_CAP_PRIME: return 0; case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c index 667ade1..5ff30f1 100644 --- a/src/gallium/drivers/llvmpipe/lp_screen.c +++ b/src/gallium/drivers/llvmpipe/lp_screen.c @@ -228,6 +228,8 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param) return 1; case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: return 0; + case PIPE_CAP_PRIME: + return 0; } /* should only get here on unhandled cases */ debug_printf(Unexpected PIPE_CAP %d query\n, param); diff --git a/src/gallium/drivers/nv30/nv30_screen.c b/src/gallium/drivers/nv30/nv30_screen.c index 5b3b470..97471a7 100644 --- a/src/gallium/drivers/nv30/nv30_screen.c +++ b/src/gallium/drivers/nv30/nv30_screen.c @@ -124,6 +124,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: case PIPE_CAP_QUERY_PIPELINE_STATISTICS: case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: + case PIPE_CAP_PRIME: return 0; case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: diff --git a/src/gallium/drivers/nv50/nv50_screen.c b/src/gallium/drivers/nv50/nv50_screen.c index 5aa8ef3..1177c1b 100644 --- a/src/gallium/drivers/nv50/nv50_screen.c +++ b/src/gallium/drivers/nv50/nv50_screen.c @@ -188,6 +188,8 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 0; case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50; + case PIPE_CAP_PRIME: + return 0; default: NOUVEAU_ERR(unknown PIPE_CAP %d\n, param); return 0; diff --git a/src/gallium/drivers/nvc0/nvc0_screen.c b/src/gallium/drivers/nvc0/nvc0_screen.c index 8dfd4d1..e3eff40 100644 --- a/src/gallium/drivers/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nvc0/nvc0_screen.c @@ -178,6 +178,8 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 1; case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50; + case PIPE_CAP_PRIME: + return 0; default: NOUVEAU_ERR(unknown PIPE_CAP %d\n, param); return 0; diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index a932be9..000c71d 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -163,6 +163,7 @@
[Mesa-dev] [PATCH 2/4] nouveau: Populate PIPE_CAP_PRIME, enabling DRI Image 7 support
From: Christopher James Halse Rogers r...@ubuntu.com
---
src/gallium/drivers/nouveau/nouveau_screen.c | 19 ++-
src/gallium/drivers/nouveau/nouveau_screen.h | 2 ++
src/gallium/drivers/nv30/nv30_screen.c | 6 +-
src/gallium/drivers/nv50/nv50_screen.c | 5 -
src/gallium/drivers/nvc0/nvc0_screen.c | 5 -
5 files changed, 33 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/nouveau/nouveau_screen.c
b/src/gallium/drivers/nouveau/nouveau_screen.c
index d129a55..6308a91 100644
--- a/src/gallium/drivers/nouveau/nouveau_screen.c
+++ b/src/gallium/drivers/nouveau/nouveau_screen.c
@@ -14,6 +14,7 @@
#include errno.h
#include stdlib.h
+#include xf86drm.h
#include libdrm/nouveau_drm.h
#include nouveau_winsys.h
@@ -86,7 +87,18 @@ nouveau_screen_bo_from_handle(struct pipe_screen *pscreen,
struct nouveau_bo *bo = 0;
int ret;
- ret = nouveau_bo_name_ref(dev, whandle-handle, bo);
+ if (whandle-type != DRM_API_HANDLE_TYPE_SHARED
+ whandle-type != DRM_API_HANDLE_TYPE_FD) {
+ debug_printf(%s: attempt to import unsupported handle type
%d\n,
+__FUNCTION__, whandle-type);
+ return NULL;
+ }
+
+ if (whandle-type == DRM_API_HANDLE_TYPE_SHARED)
+ ret = nouveau_bo_name_ref(dev, whandle-handle, bo);
+ else
+ ret = nouveau_bo_prime_handle_ref(dev, whandle-handle, bo);
+
if (ret) {
debug_printf(%s: ref name 0x%08x failed with %d\n,
__FUNCTION__, whandle-handle, ret);
@@ -111,6 +123,8 @@ nouveau_screen_bo_get_handle(struct pipe_screen *pscreen,
} else if (whandle-type == DRM_API_HANDLE_TYPE_KMS) {
whandle-handle = bo-handle;
return TRUE;
+ } else if (whandle-type == DRM_API_HANDLE_TYPE_FD) {
+ return nouveau_bo_set_prime(bo, (int *)whandle-handle) == 0;
} else {
return FALSE;
}
@@ -161,6 +175,9 @@ nouveau_screen_init(struct nouveau_screen *screen, struct
nouveau_device *dev)
if (!ret)
screen-cpu_gpu_time_delta = time - screen-cpu_gpu_time_delta *
1000;
+ screen-prime_caps = 0;
+ ret = drmGetCap(dev-fd, DRM_CAP_PRIME, screen-prime_caps);
+
pscreen-get_name = nouveau_screen_get_name;
pscreen-get_vendor = nouveau_screen_get_vendor;
diff --git a/src/gallium/drivers/nouveau/nouveau_screen.h
b/src/gallium/drivers/nouveau/nouveau_screen.h
index 7f15d10..fc5531b 100644
--- a/src/gallium/drivers/nouveau/nouveau_screen.h
+++ b/src/gallium/drivers/nouveau/nouveau_screen.h
@@ -47,6 +47,8 @@ struct nouveau_screen {
int64_t cpu_gpu_time_delta;
+ uint64_t prime_caps;
+
boolean hint_buf_keep_sysmem_copy;
#ifdef NOUVEAU_ENABLE_DRIVER_STATISTICS
diff --git a/src/gallium/drivers/nv30/nv30_screen.c
b/src/gallium/drivers/nv30/nv30_screen.c
index 97471a7..d014fb9 100644
--- a/src/gallium/drivers/nv30/nv30_screen.c
+++ b/src/gallium/drivers/nv30/nv30_screen.c
@@ -31,6 +31,8 @@
#include nv30-40_3d.xml.h
#include nv01_2d.xml.h
+#include drm.h
+
#include nouveau/nouveau_fence.h
#include nv30_screen.h
#include nv30_context.h
@@ -124,13 +126,15 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
- case PIPE_CAP_PRIME:
return 0;
case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
return 1;
+ case PIPE_CAP_PRIME:
+ return screen-base.prime_caps
+ (DRM_PRIME_CAP_EXPORT | DRM_PRIME_CAP_IMPORT);
default:
debug_printf(unknown param %d\n, param);
return 0;
diff --git a/src/gallium/drivers/nv50/nv50_screen.c
b/src/gallium/drivers/nv50/nv50_screen.c
index 1177c1b..7194604 100644
--- a/src/gallium/drivers/nv50/nv50_screen.c
+++ b/src/gallium/drivers/nv50/nv50_screen.c
@@ -24,6 +24,8 @@
#include util/u_format_s3tc.h
#include pipe/p_screen.h
+#include drm.h
+
#include nv50_context.h
#include nv50_screen.h
@@ -189,7 +191,8 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum
pipe_cap param)
case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50;
case PIPE_CAP_PRIME:
- return 0;
+ return nouveau_screen(pscreen)-prime_caps
+ (DRM_PRIME_CAP_EXPORT | DRM_PRIME_CAP_IMPORT);
default:
NOUVEAU_ERR(unknown PIPE_CAP %d\n, param);
return 0;
diff --git a/src/gallium/drivers/nvc0/nvc0_screen.c
b/src/gallium/drivers/nvc0/nvc0_screen.c
index e3eff40..c2ae7e1 100644
--- a/src/gallium/drivers/nvc0/nvc0_screen.c
+++
[Mesa-dev] [PATCH 3/4] radeon: Rename bo_handles hashtable to match its actual contents.
From: Christopher James Halse Rogers r...@ubuntu.com
It's a map of GEM name-bo, so identify it as such
---
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 6ec1713..c0ea4c0 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -114,8 +114,8 @@ struct radeon_bomgr {
/* Winsys. */
struct radeon_drm_winsys *rws;
-/* List of buffer handles and its mutex. */
-struct util_hash_table *bo_handles;
+/* List of buffer GEM names. Protected by bo_handles_mutex. */
+struct util_hash_table *bo_names;
pipe_mutex bo_handles_mutex;
pipe_mutex bo_va_mutex;
@@ -372,7 +372,7 @@ static void radeon_bo_destroy(struct pb_buffer *_buf)
if (bo-name) {
pipe_mutex_lock(bo-mgr-bo_handles_mutex);
-util_hash_table_remove(bo-mgr-bo_handles,
+util_hash_table_remove(bo-mgr-bo_names,
(void*)(uintptr_t)bo-name);
pipe_mutex_unlock(bo-mgr-bo_handles_mutex);
}
@@ -658,7 +658,7 @@ static boolean radeon_bomgr_is_buffer_busy(struct
pb_manager *_mgr,
static void radeon_bomgr_destroy(struct pb_manager *_mgr)
{
struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
-util_hash_table_destroy(mgr-bo_handles);
+util_hash_table_destroy(mgr-bo_names);
pipe_mutex_destroy(mgr-bo_handles_mutex);
pipe_mutex_destroy(mgr-bo_va_mutex);
FREE(mgr);
@@ -690,7 +690,7 @@ struct pb_manager *radeon_bomgr_create(struct
radeon_drm_winsys *rws)
mgr-base.is_buffer_busy = radeon_bomgr_is_buffer_busy;
mgr-rws = rws;
-mgr-bo_handles = util_hash_table_create(handle_hash, handle_compare);
+mgr-bo_names = util_hash_table_create(handle_hash, handle_compare);
pipe_mutex_init(mgr-bo_handles_mutex);
pipe_mutex_init(mgr-bo_va_mutex);
@@ -884,7 +884,7 @@ static struct pb_buffer
*radeon_winsys_bo_from_handle(struct radeon_winsys *rws,
pipe_mutex_lock(mgr-bo_handles_mutex);
/* First check if there already is an existing bo for the handle. */
-bo = util_hash_table_get(mgr-bo_handles,
(void*)(uintptr_t)whandle-handle);
+bo = util_hash_table_get(mgr-bo_names, (void*)(uintptr_t)whandle-handle);
if (bo) {
/* Increase the refcount. */
struct pb_buffer *b = NULL;
@@ -918,7 +918,7 @@ static struct pb_buffer
*radeon_winsys_bo_from_handle(struct radeon_winsys *rws,
bo-va = 0;
pipe_mutex_init(bo-map_mutex);
-util_hash_table_set(mgr-bo_handles, (void*)(uintptr_t)whandle-handle,
bo);
+util_hash_table_set(mgr-bo_names, (void*)(uintptr_t)whandle-handle, bo);
done:
pipe_mutex_unlock(mgr-bo_handles_mutex);
@@ -984,7 +984,7 @@ static boolean radeon_winsys_bo_get_handle(struct pb_buffer
*buffer,
bo-flink = flink.name;
pipe_mutex_lock(bo-mgr-bo_handles_mutex);
-util_hash_table_set(bo-mgr-bo_handles,
(void*)(uintptr_t)bo-flink, bo);
+util_hash_table_set(bo-mgr-bo_names,
(void*)(uintptr_t)bo-flink, bo);
pipe_mutex_unlock(bo-mgr-bo_handles_mutex);
}
whandle-handle = bo-flink;
--
1.8.1.2
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[Mesa-dev] [PATCH 4/4] radeon: Enable DRI Image 7 support
From: Christopher James Halse Rogers r...@ubuntu.com --- src/gallium/drivers/r300/r300_screen.c| 8 ++- src/gallium/drivers/r300/r300_texture.c | 2 +- src/gallium/drivers/r600/r600_pipe.c | 7 ++- src/gallium/drivers/r600/r600_texture.c | 2 +- src/gallium/drivers/radeonsi/r600_texture.c | 2 +- src/gallium/drivers/radeonsi/radeonsi_pipe.c | 6 +- src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 70 ++- src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 4 ++ src/gallium/winsys/radeon/drm/radeon_winsys.h | 3 + 9 files changed, 84 insertions(+), 20 deletions(-) diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 000c71d..b7a7a2d 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -28,6 +28,8 @@ #include vl/vl_decoder.h #include vl/vl_video_buffer.h +#include drm.h + #include r300_context.h #include r300_texture.h #include r300_screen_buffer.h @@ -163,7 +165,6 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: -case PIPE_CAP_PRIME: return 0; /* SWTCL-only features. */ @@ -191,6 +192,11 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param) /* Render targets. */ case PIPE_CAP_MAX_RENDER_TARGETS: return 4; + +/* PRIME import/export support */ +case PIPE_CAP_PRIME: +return r300screen-info.prime_caps + (DRM_PRIME_CAP_IMPORT | DRM_PRIME_CAP_EXPORT); } return 0; } diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c index 13e9bc3..442b575 100644 --- a/src/gallium/drivers/r300/r300_texture.c +++ b/src/gallium/drivers/r300/r300_texture.c @@ -,7 +,7 @@ struct pipe_resource *r300_texture_from_handle(struct pipe_screen *screen, return NULL; } -buffer = rws-buffer_from_handle(rws, whandle, stride); +buffer = rws-buffer_from_handle(rws, whandle, base-height0, stride); if (!buffer) return NULL; diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index b056041..03e67f9 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -26,6 +26,8 @@ #include evergreen_compute.h #include r600d.h +#include drm.h + #include errno.h #include pipe/p_shader_tokens.h #include util/u_blitter.h @@ -612,7 +614,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: case PIPE_CAP_VERTEX_COLOR_CLAMPED: case PIPE_CAP_USER_VERTEX_BUFFERS: - case PIPE_CAP_PRIME: return 0; /* Stream output. */ @@ -655,9 +656,11 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_MAX_TEXEL_OFFSET: return 7; - case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600; + case PIPE_CAP_PRIME: + return rscreen-info.prime_caps + (DRM_PRIME_CAP_IMPORT | DRM_PRIME_CAP_EXPORT); } return 0; } diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c index 98cb118..8fa821b 100644 --- a/src/gallium/drivers/r600/r600_texture.c +++ b/src/gallium/drivers/r600/r600_texture.c @@ -670,7 +670,7 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, templ-depth0 != 1 || templ-last_level != 0) return NULL; - buf = rscreen-ws-buffer_from_handle(rscreen-ws, whandle, stride); + buf = rscreen-ws-buffer_from_handle(rscreen-ws, whandle, templ-height0, stride); if (!buf) return NULL; diff --git a/src/gallium/drivers/radeonsi/r600_texture.c b/src/gallium/drivers/radeonsi/r600_texture.c index 8992f9a..5ef526c 100644 --- a/src/gallium/drivers/radeonsi/r600_texture.c +++ b/src/gallium/drivers/radeonsi/r600_texture.c @@ -602,7 +602,7 @@ struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen, templ-depth0 != 1 || templ-last_level != 0) return NULL; - buf = rscreen-ws-buffer_from_handle(rscreen-ws, whandle, stride); + buf = rscreen-ws-buffer_from_handle(rscreen-ws, whandle, templ-height0, stride); if (!buf) return NULL; diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c b/src/gallium/drivers/radeonsi/radeonsi_pipe.c index 1705e3e..60c40f5 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_pipe.c +++ b/src/gallium/drivers/radeonsi/radeonsi_pipe.c @@ -20,6 +20,7 @@ * OTHERWISE,
[Mesa-dev] [PATCH] gallium/dri2: Set winsys_handle type to KMS for stride query.
From: Christopher James Halse Rogers r...@ubuntu.com
Otherwise the default is TYPE_SHARED, which will flink the bo. This seems
unnecessary for a simple stride query.
---
src/gallium/state_trackers/dri/drm/dri2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/state_trackers/dri/drm/dri2.c
b/src/gallium/state_trackers/dri/drm/dri2.c
index 7f1dc0e..ddd9ad1 100644
--- a/src/gallium/state_trackers/dri/drm/dri2.c
+++ b/src/gallium/state_trackers/dri/drm/dri2.c
@@ -642,6 +642,7 @@ dri2_query_image(__DRIimage *image, int attrib, int *value)
switch (attrib) {
case __DRI_IMAGE_ATTRIB_STRIDE:
+ whandle.type = DRM_API_HANDLE_TYPE_KMS;
image-texture-screen-resource_get_handle(image-texture-screen,
image-texture, whandle);
*value = whandle.stride;
--
1.8.1.2
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[Mesa-dev] [PATCH] gallium/dri: Return failures from dri2_query_image.
From: Christopher James Halse Rogers r...@ubuntu.com
resource_get_handle can fail, so we might as well bubble that failure
up to the client.
---
src/gallium/state_trackers/dri/drm/dri2.c | 39 +++
1 file changed, 24 insertions(+), 15 deletions(-)
diff --git a/src/gallium/state_trackers/dri/drm/dri2.c
b/src/gallium/state_trackers/dri/drm/dri2.c
index ddd9ad1..ca90bb8 100644
--- a/src/gallium/state_trackers/dri/drm/dri2.c
+++ b/src/gallium/state_trackers/dri/drm/dri2.c
@@ -643,27 +643,36 @@ dri2_query_image(__DRIimage *image, int attrib, int
*value)
switch (attrib) {
case __DRI_IMAGE_ATTRIB_STRIDE:
whandle.type = DRM_API_HANDLE_TYPE_KMS;
- image-texture-screen-resource_get_handle(image-texture-screen,
-image-texture, whandle);
- *value = whandle.stride;
- return GL_TRUE;
+ if (image-texture-screen-resource_get_handle(image-texture-screen,
+ image-texture,
whandle)) {
+ *value = whandle.stride;
+ return GL_TRUE;
+ } else
+ return GL_FALSE;
case __DRI_IMAGE_ATTRIB_HANDLE:
whandle.type = DRM_API_HANDLE_TYPE_KMS;
- image-texture-screen-resource_get_handle(image-texture-screen,
- image-texture, whandle);
- *value = whandle.handle;
- return GL_TRUE;
+ if (image-texture-screen-resource_get_handle(image-texture-screen,
+ image-texture,
whandle)) {
+ *value = whandle.handle;
+ return GL_TRUE;
+ } else
+ return GL_FALSE;
case __DRI_IMAGE_ATTRIB_NAME:
whandle.type = DRM_API_HANDLE_TYPE_SHARED;
- image-texture-screen-resource_get_handle(image-texture-screen,
- image-texture, whandle);
- *value = whandle.handle;
- return GL_TRUE;
+ if (image-texture-screen-resource_get_handle(image-texture-screen,
+ image-texture,
whandle)) {
+ *value = whandle.handle;
+ return GL_TRUE;
+ } else
+ return GL_FALSE;
case __DRI_IMAGE_ATTRIB_FD:
whandle.type= DRM_API_HANDLE_TYPE_FD;
- image-texture-screen-resource_get_handle(image-texture-screen,
- image-texture, whandle);
- *value = whandle.handle;
+ if (image-texture-screen-resource_get_handle(image-texture-screen,
+ image-texture,
whandle)) {
+ *value = whandle.handle;
+ return GL_TRUE;
+ } else
+ return GL_FALSE;
case __DRI_IMAGE_ATTRIB_FORMAT:
*value = image-dri_format;
return GL_TRUE;
--
1.8.1.2
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[Mesa-dev] [PATCH] mesa/st: Don't copy propagate from swizzles.
Do not propagate a copy if source and destination are identical. Otherwise code like MOV TEMP[0].xyzw, TEMP[0].wzyx mov TEMP[1].xyzw, TEMP[0].xyzw is changed to MOV TEMP[0].xyzw, TEMP[0].wzyx mov TEMP[1].xyzw, TEMP[0].wzyx --- src/mesa/state_tracker/st_glsl_to_tgsi.cpp |2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index f2eb3e7..b5d0534 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -3544,6 +3544,8 @@ glsl_to_tgsi_visitor::copy_propagate(void) /* If this is a copy, add it to the ACP. */ if (inst-op == TGSI_OPCODE_MOV inst-dst.file == PROGRAM_TEMPORARY + !(inst-dst.file == inst-src[0].file + inst-dst.index == inst-src[0].index) !inst-dst.reladdr !inst-saturate !inst-src[0].reladdr -- 1.7.10.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] mesa: fix bogus comment about PrimitiveRestart fields
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/main/mtypes.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 6108a35..7b51ec8 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -1536,8 +1536,8 @@ struct gl_array_attrib
* \name Primitive restart controls
*
* Primitive restart is enabled if either \c PrimitiveRestart or
-* \c PrimitiveRestart is set. If \c PrimitiveRestart is set, then
-* \c RestartIndex is used as the cut vertex. Otherwise ~0 is used.
+* \c PrimitiveRestartFixedIndex is set. If \c PrimitiveRestart is set,
+* then \c RestartIndex is used as the cut vertex. Otherwise ~0 is used.
*/
/*@{*/
GLboolean PrimitiveRestart;
--
1.8.2.1
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Re: [Mesa-dev] [PATCH 3/4] radeon: Rename bo_handles hashtable to match its actual contents.
Reviewed-by: Marek Olšák mar...@gmail.com
Marek
On Mon, Apr 22, 2013 at 8:38 AM,
christopher.halse.rog...@canonical.com wrote:
From: Christopher James Halse Rogers r...@ubuntu.com
It's a map of GEM name-bo, so identify it as such
---
src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
index 6ec1713..c0ea4c0 100644
--- a/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
+++ b/src/gallium/winsys/radeon/drm/radeon_drm_bo.c
@@ -114,8 +114,8 @@ struct radeon_bomgr {
/* Winsys. */
struct radeon_drm_winsys *rws;
-/* List of buffer handles and its mutex. */
-struct util_hash_table *bo_handles;
+/* List of buffer GEM names. Protected by bo_handles_mutex. */
+struct util_hash_table *bo_names;
pipe_mutex bo_handles_mutex;
pipe_mutex bo_va_mutex;
@@ -372,7 +372,7 @@ static void radeon_bo_destroy(struct pb_buffer *_buf)
if (bo-name) {
pipe_mutex_lock(bo-mgr-bo_handles_mutex);
-util_hash_table_remove(bo-mgr-bo_handles,
+util_hash_table_remove(bo-mgr-bo_names,
(void*)(uintptr_t)bo-name);
pipe_mutex_unlock(bo-mgr-bo_handles_mutex);
}
@@ -658,7 +658,7 @@ static boolean radeon_bomgr_is_buffer_busy(struct
pb_manager *_mgr,
static void radeon_bomgr_destroy(struct pb_manager *_mgr)
{
struct radeon_bomgr *mgr = radeon_bomgr(_mgr);
-util_hash_table_destroy(mgr-bo_handles);
+util_hash_table_destroy(mgr-bo_names);
pipe_mutex_destroy(mgr-bo_handles_mutex);
pipe_mutex_destroy(mgr-bo_va_mutex);
FREE(mgr);
@@ -690,7 +690,7 @@ struct pb_manager *radeon_bomgr_create(struct
radeon_drm_winsys *rws)
mgr-base.is_buffer_busy = radeon_bomgr_is_buffer_busy;
mgr-rws = rws;
-mgr-bo_handles = util_hash_table_create(handle_hash, handle_compare);
+mgr-bo_names = util_hash_table_create(handle_hash, handle_compare);
pipe_mutex_init(mgr-bo_handles_mutex);
pipe_mutex_init(mgr-bo_va_mutex);
@@ -884,7 +884,7 @@ static struct pb_buffer
*radeon_winsys_bo_from_handle(struct radeon_winsys *rws,
pipe_mutex_lock(mgr-bo_handles_mutex);
/* First check if there already is an existing bo for the handle. */
-bo = util_hash_table_get(mgr-bo_handles,
(void*)(uintptr_t)whandle-handle);
+bo = util_hash_table_get(mgr-bo_names,
(void*)(uintptr_t)whandle-handle);
if (bo) {
/* Increase the refcount. */
struct pb_buffer *b = NULL;
@@ -918,7 +918,7 @@ static struct pb_buffer
*radeon_winsys_bo_from_handle(struct radeon_winsys *rws,
bo-va = 0;
pipe_mutex_init(bo-map_mutex);
-util_hash_table_set(mgr-bo_handles, (void*)(uintptr_t)whandle-handle,
bo);
+util_hash_table_set(mgr-bo_names, (void*)(uintptr_t)whandle-handle,
bo);
done:
pipe_mutex_unlock(mgr-bo_handles_mutex);
@@ -984,7 +984,7 @@ static boolean radeon_winsys_bo_get_handle(struct
pb_buffer *buffer,
bo-flink = flink.name;
pipe_mutex_lock(bo-mgr-bo_handles_mutex);
-util_hash_table_set(bo-mgr-bo_handles,
(void*)(uintptr_t)bo-flink, bo);
+util_hash_table_set(bo-mgr-bo_names,
(void*)(uintptr_t)bo-flink, bo);
pipe_mutex_unlock(bo-mgr-bo_handles_mutex);
}
whandle-handle = bo-flink;
--
1.8.1.2
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Re: [Mesa-dev] [PATCH 2/2] gallium: Replaced gl_rasterization_rules with lower_left_origin and half_pixel_center.
On 21.04.2013 14:35, Jose Fonseca wrote: - Original Message - On 21.04.2013 13:18, Jose Fonseca wrote: I think that drivers can just report all 4 CAPs as supported and do the adjustment in the shader themselves (no need for recompilation, just use uniforms, the st already does it like that), provided that the state tracker actually uses the rasterizer origin bit instead of changing the viewport and applies no transformation to the fragment coordinate whatsoever. I'm not sure how much that simplifies in the end. If the drivers need to resort to uniforms to deal with all combinations, then how will making the gl_Fragcoord/viewport transformation depend on lower_left_origin simplify things? Is it really true that for all hardware gl_FragCoord will depend on the lower_left_origin rasterizer state? I don't know about all hardware. R600 doesn't have that origin switch, but the half-integers switch might have an effect. My suggestion about letting the driver modify the coordinate was to avoid having a dependency in the gallium interface between the shader setting, or worse, yet another cap about whether it exists. The only (small) issue is, if a driver does handle the origin switch and compensates for the effect on FragCoord, and the state tracker decides to not use that switch and just flips the viewport, it has to do its own transformation on FragCoord, we get to do 2 transformations. Finally, I think this is precisely what Marek was concerned; so to allow existing drivers to opt out from having to deal with this, we'll need a cap. Which is, I guess, why we have to add both versions depending on a CAP once again, i.e. for some drivers the origin switch in the rasterizer is used (nouveau at least; this should affect the edge rule; I think I looked for an independent switch way back and didn't find one) and for other drivers the viewport is flipped in combination with changing a separate edge rule rasterizer state. Maybe some drivers even support both (independent change of edge rule and origin) ... That said, I don't oppose any of this if it make HW driver implementer lives easier. But how seriously/quickly are you and other hardware drivers maintainers actually aiming at implementing this? I don't wanna go through all that trouble if nobody will care. Well, there's not much code (in terms of lines) to write on the driver side, but code that uglifies things always takes a bit longer to become comfortable with ... Either way, I think that this patch series already is a good improvement over the ugly one-bit-fit-all-needs gl_rasterization_rules state, and should cause no regressions whatsoever. I'd like to tackle the entanglement of lower_left_origin with other bits of state in a follow-on gallium change after there is a clearer understanding/consensus if/how will HW implement this. Jose ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radeonsi: cleanup disabling tiling for UVD
On Sam, 2013-04-20 at 13:21 +0200, Christian König wrote: From: Christian König christian.koe...@amd.com Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=63702 Signed-off-by: Christian König christian.koe...@amd.com --- src/gallium/drivers/radeonsi/radeonsi_uvd.c |6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/radeonsi_uvd.c b/src/gallium/drivers/radeonsi/radeonsi_uvd.c index d49c088..20d079f 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_uvd.c +++ b/src/gallium/drivers/radeonsi/radeonsi_uvd.c @@ -76,6 +76,7 @@ struct pipe_video_buffer *radeonsi_video_buffer_create(struct pipe_context *pipe template.height = align(tmpl-height / depth, VL_MACROBLOCK_HEIGHT); vl_vide_buffer_template(templ, template, resource_formats[0], depth, PIPE_USAGE_STATIC, 0); + templ.flags = R600_RESOURCE_FLAG_TRANSFER; resources[0] = (struct r600_resource_texture *) pipe-screen-resource_create(pipe-screen, templ); if (!resources[0]) Are these resources really used as transfers, i.e. for accessing data with the CPU? If not, I think it would be better to add a new R600_RESOURCE_* flag instead of (ab)using R600_RESOURCE_FLAG_TRANSFER for this. -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Debian, X and DRI developer ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] radeonsi: cleanup disabling tiling for UVD
Am 22.04.2013 09:35, schrieb Michel Dänzer: On Sam, 2013-04-20 at 13:21 +0200, Christian König wrote: From: Christian König christian.koe...@amd.com Should fix: https://bugs.freedesktop.org/show_bug.cgi?id=63702 Signed-off-by: Christian König christian.koe...@amd.com --- src/gallium/drivers/radeonsi/radeonsi_uvd.c |6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/radeonsi/radeonsi_uvd.c b/src/gallium/drivers/radeonsi/radeonsi_uvd.c index d49c088..20d079f 100644 --- a/src/gallium/drivers/radeonsi/radeonsi_uvd.c +++ b/src/gallium/drivers/radeonsi/radeonsi_uvd.c @@ -76,6 +76,7 @@ struct pipe_video_buffer *radeonsi_video_buffer_create(struct pipe_context *pipe template.height = align(tmpl-height / depth, VL_MACROBLOCK_HEIGHT); vl_vide_buffer_template(templ, template, resource_formats[0], depth, PIPE_USAGE_STATIC, 0); + templ.flags = R600_RESOURCE_FLAG_TRANSFER; resources[0] = (struct r600_resource_texture *) pipe-screen-resource_create(pipe-screen, templ); if (!resources[0]) Are these resources really used as transfers, i.e. for accessing data with the CPU? If not, I think it would be better to add a new R600_RESOURCE_* flag instead of (ab)using R600_RESOURCE_FLAG_TRANSFER for this. That's just a temporary workaround till I figure out why tiling with UVD on SI doesn't work like it should. And you're right I should probably document that or cleanup the flag name. Christian. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/3] gallivm: Emit vector selects.
Am 20.04.2013 10:57, schrieb jfons...@vmware.com:
From: José Fonseca jfons...@vmware.com
They are supported on LLVM 3.1, at least on x86. (I haven't tested on PPC
though.)
Actually lp_build_linear_mip_levels() already has been emitting them for
some time.
This avoids intrinsics, which tend to be an obstacle for certain
optimization passes.
---
src/gallium/auxiliary/gallivm/lp_bld_logic.c | 14 ++
1 file changed, 2 insertions(+), 12 deletions(-)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_logic.c
b/src/gallium/auxiliary/gallivm/lp_bld_logic.c
index f56b61b..cdb7e0a 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_logic.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_logic.c
@@ -458,20 +458,10 @@ lp_build_select(struct lp_build_context *bld,
mask = LLVMBuildTrunc(builder, mask, LLVMInt1TypeInContext(lc), );
res = LLVMBuildSelect(builder, mask, a, b, );
}
- else if (0) {
+ else if (HAVE_LLVM = 0x301) {
/* Generate a vector select.
*
- * XXX: Using vector selects would avoid emitting intrinsics, but they
aren't
- * properly supported yet.
- *
- * LLVM 3.0 includes experimental support provided the
-promote-elements
- * options is passed to LLVM's command line (e.g., via
- * llvm::cl::ParseCommandLineOptions), but resulting code quality is
much
- * worse, probably because some optimization passes don't know how to
- * handle vector selects.
- *
- * See also:
- * -
http://lists.cs.uiuc.edu/pipermail/llvmdev/2011-October/043659.html
+ * Only supported on LLVM 3.1 onwards
*/
/* Convert the mask to a vector of booleans.
Series looks good to me.
Roland
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Re: [Mesa-dev] [PATCH 1/4] gallium/dri: Allow drivers to support DRI Image v7
- Original Message - From: Christopher James Halse Rogers r...@ubuntu.com This is only exposed by drivers wich support the new PIPE_CAP_PRIME parameter, for PRIME import/export. What does exactly PIPE_CAP_PRIME entail? Please document it. Jose ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 4/4] radeon: Enable DRI Image 7 support
On Mon, Apr 22, 2013 at 8:38 AM, christopher.halse.rog...@canonical.com wrote: From: Christopher James Halse Rogers r...@ubuntu.com --- src/gallium/drivers/r300/r300_screen.c| 8 ++- src/gallium/drivers/r300/r300_texture.c | 2 +- src/gallium/drivers/r600/r600_pipe.c | 7 ++- src/gallium/drivers/r600/r600_texture.c | 2 +- src/gallium/drivers/radeonsi/r600_texture.c | 2 +- src/gallium/drivers/radeonsi/radeonsi_pipe.c | 6 +- src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 70 ++- src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 4 ++ src/gallium/winsys/radeon/drm/radeon_winsys.h | 3 + 9 files changed, 84 insertions(+), 20 deletions(-) diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 000c71d..b7a7a2d 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -28,6 +28,8 @@ #include vl/vl_decoder.h #include vl/vl_video_buffer.h +#include drm.h + #include r300_context.h #include r300_texture.h #include r300_screen_buffer.h @@ -163,7 +165,6 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: -case PIPE_CAP_PRIME: return 0; /* SWTCL-only features. */ @@ -191,6 +192,11 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param) /* Render targets. */ case PIPE_CAP_MAX_RENDER_TARGETS: return 4; + +/* PRIME import/export support */ +case PIPE_CAP_PRIME: +return r300screen-info.prime_caps + (DRM_PRIME_CAP_IMPORT | DRM_PRIME_CAP_EXPORT); } return 0; } diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c index 13e9bc3..442b575 100644 --- a/src/gallium/drivers/r300/r300_texture.c +++ b/src/gallium/drivers/r300/r300_texture.c @@ -,7 +,7 @@ struct pipe_resource *r300_texture_from_handle(struct pipe_screen *screen, return NULL; } -buffer = rws-buffer_from_handle(rws, whandle, stride); +buffer = rws-buffer_from_handle(rws, whandle, base-height0, stride); if (!buffer) return NULL; diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index b056041..03e67f9 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -26,6 +26,8 @@ #include evergreen_compute.h #include r600d.h +#include drm.h + #include errno.h #include pipe/p_shader_tokens.h #include util/u_blitter.h @@ -612,7 +614,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: case PIPE_CAP_VERTEX_COLOR_CLAMPED: case PIPE_CAP_USER_VERTEX_BUFFERS: - case PIPE_CAP_PRIME: return 0; /* Stream output. */ @@ -655,9 +656,11 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_MAX_TEXEL_OFFSET: return 7; - case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600; + case PIPE_CAP_PRIME: + return rscreen-info.prime_caps + (DRM_PRIME_CAP_IMPORT | DRM_PRIME_CAP_EXPORT); } return 0; } diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c index 98cb118..8fa821b 100644 --- a/src/gallium/drivers/r600/r600_texture.c +++ b/src/gallium/drivers/r600/r600_texture.c @@ -670,7 +670,7 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, templ-depth0 != 1 || templ-last_level != 0) return NULL; - buf = rscreen-ws-buffer_from_handle(rscreen-ws, whandle, stride); + buf = rscreen-ws-buffer_from_handle(rscreen-ws, whandle, templ-height0, stride); if (!buf) return NULL; diff --git a/src/gallium/drivers/radeonsi/r600_texture.c b/src/gallium/drivers/radeonsi/r600_texture.c index 8992f9a..5ef526c 100644 --- a/src/gallium/drivers/radeonsi/r600_texture.c +++ b/src/gallium/drivers/radeonsi/r600_texture.c @@ -602,7 +602,7 @@ struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen, templ-depth0 != 1 || templ-last_level != 0) return NULL; - buf = rscreen-ws-buffer_from_handle(rscreen-ws, whandle, stride); + buf = rscreen-ws-buffer_from_handle(rscreen-ws, whandle, templ-height0, stride); if (!buf) return NULL; diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
Re: [Mesa-dev] [PATCH 4/4] radeon: Enable DRI Image 7 support
Am 22.04.2013 13:21, schrieb Marek Olšák: On Mon, Apr 22, 2013 at 8:38 AM, christopher.halse.rog...@canonical.com wrote: From: Christopher James Halse Rogers r...@ubuntu.com --- src/gallium/drivers/r300/r300_screen.c| 8 ++- src/gallium/drivers/r300/r300_texture.c | 2 +- src/gallium/drivers/r600/r600_pipe.c | 7 ++- src/gallium/drivers/r600/r600_texture.c | 2 +- src/gallium/drivers/radeonsi/r600_texture.c | 2 +- src/gallium/drivers/radeonsi/radeonsi_pipe.c | 6 +- src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 70 ++- src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 4 ++ src/gallium/winsys/radeon/drm/radeon_winsys.h | 3 + 9 files changed, 84 insertions(+), 20 deletions(-) diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 000c71d..b7a7a2d 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -28,6 +28,8 @@ #include vl/vl_decoder.h #include vl/vl_video_buffer.h +#include drm.h + #include r300_context.h #include r300_texture.h #include r300_screen_buffer.h @@ -163,7 +165,6 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_BUFFER_OBJECTS: case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: -case PIPE_CAP_PRIME: return 0; /* SWTCL-only features. */ @@ -191,6 +192,11 @@ static int r300_get_param(struct pipe_screen* pscreen, enum pipe_cap param) /* Render targets. */ case PIPE_CAP_MAX_RENDER_TARGETS: return 4; + +/* PRIME import/export support */ +case PIPE_CAP_PRIME: +return r300screen-info.prime_caps + (DRM_PRIME_CAP_IMPORT | DRM_PRIME_CAP_EXPORT); } return 0; } diff --git a/src/gallium/drivers/r300/r300_texture.c b/src/gallium/drivers/r300/r300_texture.c index 13e9bc3..442b575 100644 --- a/src/gallium/drivers/r300/r300_texture.c +++ b/src/gallium/drivers/r300/r300_texture.c @@ -,7 +,7 @@ struct pipe_resource *r300_texture_from_handle(struct pipe_screen *screen, return NULL; } -buffer = rws-buffer_from_handle(rws, whandle, stride); +buffer = rws-buffer_from_handle(rws, whandle, base-height0, stride); if (!buffer) return NULL; diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index b056041..03e67f9 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -26,6 +26,8 @@ #include evergreen_compute.h #include r600d.h +#include drm.h + #include errno.h #include pipe/p_shader_tokens.h #include util/u_blitter.h @@ -612,7 +614,6 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_FRAGMENT_COLOR_CLAMPED: case PIPE_CAP_VERTEX_COLOR_CLAMPED: case PIPE_CAP_USER_VERTEX_BUFFERS: - case PIPE_CAP_PRIME: return 0; /* Stream output. */ @@ -655,9 +656,11 @@ static int r600_get_param(struct pipe_screen* pscreen, enum pipe_cap param) case PIPE_CAP_MAX_TEXEL_OFFSET: return 7; - case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_R600; + case PIPE_CAP_PRIME: + return rscreen-info.prime_caps + (DRM_PRIME_CAP_IMPORT | DRM_PRIME_CAP_EXPORT); } return 0; } diff --git a/src/gallium/drivers/r600/r600_texture.c b/src/gallium/drivers/r600/r600_texture.c index 98cb118..8fa821b 100644 --- a/src/gallium/drivers/r600/r600_texture.c +++ b/src/gallium/drivers/r600/r600_texture.c @@ -670,7 +670,7 @@ struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen, templ-depth0 != 1 || templ-last_level != 0) return NULL; - buf = rscreen-ws-buffer_from_handle(rscreen-ws, whandle, stride); + buf = rscreen-ws-buffer_from_handle(rscreen-ws, whandle, templ-height0, stride); if (!buf) return NULL; diff --git a/src/gallium/drivers/radeonsi/r600_texture.c b/src/gallium/drivers/radeonsi/r600_texture.c index 8992f9a..5ef526c 100644 --- a/src/gallium/drivers/radeonsi/r600_texture.c +++ b/src/gallium/drivers/radeonsi/r600_texture.c @@ -602,7 +602,7 @@ struct pipe_resource *si_texture_from_handle(struct pipe_screen *screen, templ-depth0 != 1 || templ-last_level != 0) return NULL; - buf = rscreen-ws-buffer_from_handle(rscreen-ws, whandle, stride); + buf = rscreen-ws-buffer_from_handle(rscreen-ws, whandle, templ-height0, stride); if (!buf) return NULL; diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
[Mesa-dev] [PATCH] r600g: disable hyperz by default on 9.1
From: Alex Deucher alexander.deuc...@amd.com There are too many cases were we end up with lockups. Once we sort out the remaining issues on master, they can be backported and hyperz can be re-enabled on 9.1 Signed-off-by: Alex Deucher alexander.deuc...@amd.com --- src/gallium/drivers/r600/r600_pipe.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index a7973a5..80b859f 100644 --- a/src/gallium/drivers/r600/r600_pipe.c +++ b/src/gallium/drivers/r600/r600_pipe.c @@ -1157,7 +1157,7 @@ struct pipe_screen *r600_screen_create(struct radeon_winsys *ws) * case were triggering lockup quickly such as : * piglit/bin/depthstencil-render-miplevels 1024 d=s=z24_s8 */ - rscreen-use_hyperz = debug_get_bool_option(R600_HYPERZ, TRUE); + rscreen-use_hyperz = debug_get_bool_option(R600_HYPERZ, FALSE); rscreen-use_hyperz = rscreen-info.drm_minor = 26 ? rscreen-use_hyperz : FALSE; rscreen-global_pool = compute_memory_pool_new(rscreen); -- 1.7.7.5 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 4/4] radeon: Enable DRI Image 7 support
On 04/22/2013 12:38 AM, christopher.halse.rog...@canonical.com wrote: From: Christopher James Halse Rogersr...@ubuntu.com --- src/gallium/drivers/r300/r300_screen.c| 8 ++- src/gallium/drivers/r300/r300_texture.c | 2 +- src/gallium/drivers/r600/r600_pipe.c | 7 ++- src/gallium/drivers/r600/r600_texture.c | 2 +- src/gallium/drivers/radeonsi/r600_texture.c | 2 +- src/gallium/drivers/radeonsi/radeonsi_pipe.c | 6 +- src/gallium/winsys/radeon/drm/radeon_drm_bo.c | 70 ++- src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 4 ++ src/gallium/winsys/radeon/drm/radeon_winsys.h | 3 + 9 files changed, 84 insertions(+), 20 deletions(-) diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index 000c71d..b7a7a2d 100644 --- a/src/gallium/drivers/r300/r300_screen.c +++ b/src/gallium/drivers/r300/r300_screen.c @@ -28,6 +28,8 @@ #include vl/vl_decoder.h #include vl/vl_video_buffer.h +#includedrm.h [...] Just a high-level comment: isn't including DRM-related stuff in the driver an interface violation? That is, shouldn't all the DRM stuff be contained in the winsys module? A guiding principle of gallium drivers is that they only contain device-specific code, not window system or OS-specific code. -Brian ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/2] gallium/u_blitter: implement buffer clearing
On 04/21/2013 05:25 PM, Marek Olšák wrote:
Although this might be useful for ARB_clear_buffer_object,
I need it for initializating resources in r600g.
---
src/gallium/auxiliary/util/u_blitter.c | 81 +---
src/gallium/auxiliary/util/u_blitter.h | 18 ++-
2 files changed, 91 insertions(+), 8 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_blitter.c
b/src/gallium/auxiliary/util/u_blitter.c
index 2a4a13e..2f7a1a8 100644
--- a/src/gallium/auxiliary/util/u_blitter.c
+++ b/src/gallium/auxiliary/util/u_blitter.c
@@ -100,7 +100,7 @@ struct blitter_context_priv
void *velem_state;
void *velem_uint_state;
void *velem_sint_state;
- void *velem_state_readbuf;
+ void *velem_state_readbuf[4];
It took me a minute to understand what '4' is all about. Maybe add a
comment like this:
void *velem_state_readbuf[4]; /** X, XY, XYZ, XYZW */
/* Sampler state. */
void *sampler_state;
@@ -285,9 +285,19 @@ struct blitter_context *util_blitter_create(struct
pipe_context *pipe)
}
if (ctx-has_stream_out) {
- velem[0].src_format = PIPE_FORMAT_R32_UINT;
- velem[0].vertex_buffer_index = ctx-base.vb_slot;
- ctx-velem_state_readbuf = pipe-create_vertex_elements_state(pipe,
1,velem[0]);
+ static enum pipe_format formats[4] = {
+ PIPE_FORMAT_R32_UINT,
+ PIPE_FORMAT_R32G32_UINT,
+ PIPE_FORMAT_R32G32B32_UINT,
+ PIPE_FORMAT_R32G32B32A32_UINT
+ };
+
+ for (i = 0; i 4; i++) {
+ velem[0].src_format = formats[i];
+ velem[0].vertex_buffer_index = ctx-base.vb_slot;
+ ctx-velem_state_readbuf[i] =
+ pipe-create_vertex_elements_state(pipe, 1,velem[0]);
+ }
}
/* fragment shaders are created on-demand */
@@ -352,8 +362,11 @@ void util_blitter_destroy(struct blitter_context *blitter)
pipe-delete_vertex_elements_state(pipe, ctx-velem_sint_state);
pipe-delete_vertex_elements_state(pipe, ctx-velem_uint_state);
}
- if (ctx-velem_state_readbuf)
- pipe-delete_vertex_elements_state(pipe, ctx-velem_state_readbuf);
+ for (i = 0; i 4; i++) {
+ if (ctx-velem_state_readbuf[i]) {
+ pipe-delete_vertex_elements_state(pipe, ctx-velem_state_readbuf[i]);
+ }
+ }
for (i = 0; i PIPE_MAX_TEXTURE_TYPES; i++) {
if (ctx-fs_texfetch_col[i])
@@ -1739,7 +1752,7 @@ void util_blitter_copy_buffer(struct blitter_context
*blitter,
vb.stride = 4;
pipe-set_vertex_buffers(pipe, ctx-base.vb_slot, 1,vb);
- pipe-bind_vertex_elements_state(pipe, ctx-velem_state_readbuf);
+ pipe-bind_vertex_elements_state(pipe, ctx-velem_state_readbuf[0]);
pipe-bind_vs_state(pipe, ctx-vs_pos_only);
if (ctx-has_geometry_shader)
pipe-bind_gs_state(pipe, NULL);
@@ -1756,6 +1769,60 @@ void util_blitter_copy_buffer(struct blitter_context
*blitter,
pipe_so_target_reference(so_target, NULL);
}
+void util_blitter_clear_buffer(struct blitter_context *blitter,
+ struct pipe_resource *dst,
+ unsigned offset, unsigned size,
+ unsigned num_channels,
+ const union pipe_color_union *clear_value)
+{
+ struct blitter_context_priv *ctx = (struct blitter_context_priv*)blitter;
+ struct pipe_context *pipe = ctx-base.pipe;
+ struct pipe_vertex_buffer vb = {0};
+ struct pipe_stream_output_target *so_target;
+
+ assert(num_channels= 1);
+ assert(num_channels= 4);
Do we want some sort of assertion to check that the driver actually
supports SO?
+
+ /* IMPORTANT: DON'T DO ANY BOUNDS CHECKING HERE!
+*
+* R600 uses this to initialize texture resources, so width0 might not be
+* what you think it is.
+*/
+
+ /* Some alignment is required. */
+ if (offset % 4 != 0 || size % 4 != 0 || !ctx-has_stream_out) {
+ assert(0);
assert(!Bad alignment in util_blitter_clear_buffer());
There's way too many assert(0) macros in gallium, btw.
+ return;
+ }
+
+ u_upload_data(ctx-upload, 0, num_channels*4, clear_value,
+vb.buffer_offset,vb.buffer);
+ vb.stride = 0;
+
+ blitter_set_running_flag(ctx);
+ blitter_check_saved_vertex_states(ctx);
+ blitter_disable_render_cond(ctx);
+
+ pipe-set_vertex_buffers(pipe, ctx-base.vb_slot, 1,vb);
+ pipe-bind_vertex_elements_state(pipe,
+ctx-velem_state_readbuf[num_channels-1]);
+ pipe-bind_vs_state(pipe, ctx-vs_pos_only);
+ if (ctx-has_geometry_shader)
+ pipe-bind_gs_state(pipe, NULL);
+ pipe-bind_rasterizer_state(pipe, ctx-rs_discard_state);
+
+ so_target = pipe-create_stream_output_target(pipe, dst, offset, size);
+ pipe-set_stream_output_targets(pipe, 1,so_target, 0);
+
+ util_draw_arrays(pipe, PIPE_PRIM_POINTS, 0, size / 4);
+
+ blitter_restore_vertex_states(ctx);
+ blitter_restore_render_cond(ctx);
+ blitter_unset_running_flag(ctx);
+
[Mesa-dev] [PATCH] gallivm: Fix assignment of unsigned values to OUT register.
From: José Fonseca jfons...@vmware.com
TEMP is not the only register file that accept unsigned. OUT too.
Actually, what determines the appropriate type of the destination value is
not the opcode, but rather the register.
Also cleanup/simplify code. Add a few more asserts, but also make
code more robust by handling graceful if assert fails.
This fixes segfault / assertion in the included vert-uadd.sh graw shader.
---
src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c | 127 -
src/gallium/tests/graw/vertex-shader/vert-uadd.sh |9 ++
2 files changed, 59 insertions(+), 77 deletions(-)
create mode 100755 src/gallium/tests/graw/vertex-shader/vert-uadd.sh
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
index c48c6e9..467d395 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_tgsi_soa.c
@@ -569,7 +569,7 @@ static void lp_exec_default(struct lp_exec_mask *mask,
}
-/* stores val into an address pointed to by dst.
+/* stores val into an address pointed to by dst_ptr.
* mask-exec_mask is used to figure out which bits of val
* should be stored into the address
* (0 means don't store this bit, 1 means do store).
@@ -578,10 +578,14 @@ static void lp_exec_mask_store(struct lp_exec_mask *mask,
struct lp_build_context *bld_store,
LLVMValueRef pred,
LLVMValueRef val,
- LLVMValueRef dst)
+ LLVMValueRef dst_ptr)
{
LLVMBuilderRef builder = mask-bld-gallivm-builder;
+ assert(lp_check_value(bld_store-type, val));
+ assert(LLVMGetTypeKind(LLVMTypeOf(dst_ptr)) == LLVMPointerTypeKind);
+ assert(LLVMGetElementType(LLVMTypeOf(dst_ptr)) == LLVMTypeOf(val));
+
/* Mix the predicate and execution mask */
if (mask-has_mask) {
if (pred) {
@@ -592,16 +596,13 @@ static void lp_exec_mask_store(struct lp_exec_mask *mask,
}
if (pred) {
- LLVMValueRef real_val, dst_val;
-
- dst_val = LLVMBuildLoad(builder, dst, );
- real_val = lp_build_select(bld_store,
- pred,
- val, dst_val);
+ LLVMValueRef res, dst;
- LLVMBuildStore(builder, real_val, dst);
+ dst = LLVMBuildLoad(builder, dst_ptr, );
+ res = lp_build_select(bld_store, pred, val, dst);
+ LLVMBuildStore(builder, res, dst_ptr);
} else
- LLVMBuildStore(builder, val, dst);
+ LLVMBuildStore(builder, val, dst_ptr);
}
static void lp_exec_mask_call(struct lp_exec_mask *mask,
@@ -1312,54 +1313,38 @@ emit_store_chan(
LLVMValueRef value)
{
struct lp_build_tgsi_soa_context * bld = lp_soa_context(bld_base);
- struct gallivm_state *gallivm = bld-bld_base.base.gallivm;
+ struct gallivm_state *gallivm = bld_base-base.gallivm;
LLVMBuilderRef builder = gallivm-builder;
const struct tgsi_full_dst_register *reg = inst-Dst[index];
+ struct lp_build_context *float_bld = bld_base-base;
+ struct lp_build_context *int_bld = bld_base-int_bld;
struct lp_build_context *uint_bld = bld_base-uint_bld;
LLVMValueRef indirect_index = NULL;
- struct lp_build_context *bld_store;
enum tgsi_opcode_type dtype =
tgsi_opcode_infer_dst_type(inst-Instruction.Opcode);
- switch (dtype) {
- default:
- case TGSI_TYPE_FLOAT:
- case TGSI_TYPE_UNTYPED:
- bld_store = bld_base-base;
- break;
- case TGSI_TYPE_UNSIGNED:
- bld_store = bld_base-uint_bld;
- break;
- case TGSI_TYPE_SIGNED:
- bld_store = bld_base-int_bld;
- break;
- case TGSI_TYPE_DOUBLE:
- case TGSI_TYPE_VOID:
- assert(0);
- bld_store = NULL;
- break;
- }
-
- /* If the destination is untyped then the source can be anything,
-* but LLVM won't like if the types don't match so lets cast
-* to the correct destination type as expected by LLVM. */
- if (dtype == TGSI_TYPE_UNTYPED
- !lp_check_vec_type(bld_store-type, LLVMTypeOf(value))) {
- value = LLVMBuildBitCast(builder, value, bld_store-vec_type,
- src_casted);
- }
-
+ /*
+* Apply saturation.
+*
+* It is always assumed to be float.
+*/
switch( inst-Instruction.Saturate ) {
case TGSI_SAT_NONE:
break;
case TGSI_SAT_ZERO_ONE:
- value = lp_build_max(bld-bld_base.base, value,
bld-bld_base.base.zero);
- value = lp_build_min(bld-bld_base.base, value, bld-bld_base.base.one);
+ assert(dtype == TGSI_TYPE_FLOAT ||
+ dtype == TGSI_TYPE_UNTYPED);
+ value = LLVMBuildBitCast(builder, value, float_bld-vec_type, );
+ value = lp_build_max(float_bld, value, float_bld-zero);
+ value = lp_build_min(float_bld, value, float_bld-one);
break;
case TGSI_SAT_MINUS_PLUS_ONE:
- value = lp_build_max(bld-bld_base.base, value,
Re: [Mesa-dev] License header tidying
On 04/21/2013 03:09 PM, Kenneth Graunke wrote: I was reviewing some patches and saw more new files that said IN NO EVENT SHALL BRIAN PAUL BE LIABLE but were...not authored by Brian. People keep doing that by accident, and a lot of those files have been altered by other people by now anyway. This series does the sed job to replace BRIAN PAUL BE LIABLE to THE AUTHORS BE LIABLE. It then changes it to THE AUTHORS OR COPYRIGHT HOLDERS, which is the text in the OSI approved version of the MIT license. It then re-word wraps the license headers. Commits contain the shell commands needed to reproduce the results, and all manual changes are in separate commits. This way, you can keep me honest and verify that I didn't try to slip anything in. Thoughts? I didn't review every single line, but looks OK to me. Thanks. I have a feeling there's some of the same issue in piglit, BTW. Reviewed-by: Brian Paul bri...@vmware.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 09/17] glsl_symbol_table: add interface block namespaces
On Sun, Apr 21, 2013 at 12:30 PM, Kenneth Graunke kenn...@whitecape.org wrote: On 04/19/2013 12:35 PM, Jordan Justen wrote: For interface blocks, there are three separate namespaces for uniform, input and output blocks. http://knowyourmeme.com/photos/2109 There are? Similarly, for your next patch: Uniform/interface blocks are a separate namespace from types. They are? I should definitely add some spec references to this commit. Anyway, this is tested by my proposed piglit test: glsl-1.50: allow the same name for uniform and varying interface And, I actually properly referenced the spec there. :) GLSLangSpec.1.50.11, 4.3.7 Interface Blocks: A block name is allowed to have different definitions in different interfaces. Which kind of confused me until I read: GLSLangSpec.4.30.8, 4.3.9 Interface Blocks: A block name is allowed to have different definitions in different interfaces within the same shader, allowing, for example, an input block and output block to have the same name. Did I misinterpreted this text? Thanks, -Jordan As I understand it, variables, structure types (constructors), function names, UBO block names, and interface block instance names are all in a single namespace as of GLSL 1.20+. I can't find any text to indicate that there are multiple namespaces...maybe I'm just being dense, but could you point me at what you found? --Ken ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] r600g: disable hyperz by default on 9.1
On Mon, 2013-04-22 at 10:20 -0400, alexdeuc...@gmail.com wrote: From: Alex Deucher alexander.deuc...@amd.com There are too many cases were we end up with lockups. Once we sort out the remaining issues on master, they can be backported and hyperz can be re-enabled on 9.1 Signed-off-by: Alex Deucher alexander.deuc...@amd.com Reviewed-by: Michel Dänzer michel.daen...@amd.com -- Earthling Michel Dänzer | http://www.amd.com Libre software enthusiast | Debian, X and DRI developer ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 63404] [wayland egl] intel_do_flush_locked failed: invalid argument, crash
https://bugs.freedesktop.org/show_bug.cgi?id=63404 Joe Konno joe.ko...@linux.intel.com changed: What|Removed |Added Depends on||54111, 59299 --- Comment #5 from Joe Konno joe.ko...@linux.intel.com --- Adding references to DRI bugs related to this issue. -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] swrast MapTextureImage fetches
34 files changed, 311 insertions(+), 889 deletions(-) Also, swrast_dri.so now passes two FXT1 tests that failed before, and i915's vertex shader texturing works. I haven't tested the radeon/nouveau code, nor have I been as invasive as I could be, because I don't have any AGP systems left. nouveau's got a giant pile of code to be deleted if anyone gets around to doing AllocTextureImageBuffer for it. The way swrast renderbuffers are linked to swrast textures is still pretty hokey, but it's the best I could do at the moment. I think we should have MapRenderbuffer in general call MapTextureImage for texture renderbuffers, without drivers having to manually do so. To do that we'd want the gl_renderbuffer to have a pointer to its TextureImage/slice instead of that being in the gl_renderbuffer_attachment. Branch is at swrast-texture-mapping of my tree. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 01/17] radeon: Add missing swrast field initialization.
This is the equivalent of intel's 80513ec8b4c812b9c6249cc5824337a5f04ab34c. --- src/mesa/drivers/dri/radeon/radeon_texture.c |3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c b/src/mesa/drivers/dri/radeon/radeon_texture.c index 0bd2c24..b1bc0fc 100644 --- a/src/mesa/drivers/dri/radeon/radeon_texture.c +++ b/src/mesa/drivers/dri/radeon/radeon_texture.c @@ -120,6 +120,9 @@ radeonAllocTextureImageBuffer(struct gl_context *ctx, } assert(!image-base.ImageOffsets); image-base.ImageOffsets = malloc(slices * sizeof(GLuint)); + + _swrast_init_texture_image(timage); + teximage_assign_miptree(rmesa, texobj, timage); return GL_TRUE; -- 1.7.10.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 03/17] swrast: Factor out texture slice counting.
This function going to get used a lot more in upcoming patches.
---
src/mesa/swrast/s_texture.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/mesa/swrast/s_texture.c b/src/mesa/swrast/s_texture.c
index 51048be..36a90dd 100644
--- a/src/mesa/swrast/s_texture.c
+++ b/src/mesa/swrast/s_texture.c
@@ -58,6 +58,14 @@ _swrast_delete_texture_image(struct gl_context *ctx,
_mesa_delete_texture_image(ctx, texImage);
}
+static unsigned int
+texture_slices(struct gl_texture_image *texImage)
+{
+ if (texImage-TexObject-Target == GL_TEXTURE_1D_ARRAY)
+ return texImage-Height;
+ else
+ return texImage-Depth;
+}
/**
* Called via ctx-Driver.AllocTextureImageBuffer()
@@ -83,11 +91,11 @@ _swrast_alloc_texture_image_buffer(struct gl_context *ctx,
* We allocate the array for 1D/2D textures too in order to avoid special-
* case code in the texstore routines.
*/
- swImg-ImageOffsets = malloc(texImage-Depth * sizeof(GLuint));
+ swImg-ImageOffsets = malloc(texture_slices(texImage) * sizeof(GLuint));
if (!swImg-ImageOffsets)
return GL_FALSE;
- for (i = 0; i texImage-Depth; i++) {
+ for (i = 0; i texture_slices(texImage); i++) {
swImg-ImageOffsets[i] = i * texImage-Width * texImage-Height;
}
@@ -209,20 +217,20 @@ _swrast_map_teximage(struct gl_context *ctx,
map = swImage-Buffer;
+ assert(slice texture_slices(texImage));
+
if (texImage-TexObject-Target == GL_TEXTURE_3D ||
texImage-TexObject-Target == GL_TEXTURE_2D_ARRAY) {
GLuint sliceSize = _mesa_format_image_size(texImage-TexFormat,
texImage-Width,
texImage-Height,
1);
- assert(slice texImage-Depth);
map += slice * sliceSize;
} else if (texImage-TexObject-Target == GL_TEXTURE_1D_ARRAY) {
GLuint sliceSize = _mesa_format_image_size(texImage-TexFormat,
texImage-Width,
1,
1);
- assert(slice texImage-Height);
map += slice * sliceSize;
}
--
1.7.10.4
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[Mesa-dev] [PATCH 04/17] swrast: Clean up and explain the mapping process.
---
src/mesa/swrast/s_texture.c | 17 -
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/src/mesa/swrast/s_texture.c b/src/mesa/swrast/s_texture.c
index 36a90dd..b6dd8cb 100644
--- a/src/mesa/swrast/s_texture.c
+++ b/src/mesa/swrast/s_texture.c
@@ -218,18 +218,17 @@ _swrast_map_teximage(struct gl_context *ctx,
map = swImage-Buffer;
assert(slice texture_slices(texImage));
+ if (slice != 0) {
+ int sliceHeight = texImage-Height;
+ /* For 1D array textures, the slices are all 1 pixel high, and Height is
+ * the number of slices.
+ */
+ if (texImage-TexObject-Target == GL_TEXTURE_1D_ARRAY)
+ sliceHeight = 1;
- if (texImage-TexObject-Target == GL_TEXTURE_3D ||
- texImage-TexObject-Target == GL_TEXTURE_2D_ARRAY) {
GLuint sliceSize = _mesa_format_image_size(texImage-TexFormat,
texImage-Width,
- texImage-Height,
- 1);
- map += slice * sliceSize;
- } else if (texImage-TexObject-Target == GL_TEXTURE_1D_ARRAY) {
- GLuint sliceSize = _mesa_format_image_size(texImage-TexFormat,
- texImage-Width,
- 1,
+ sliceHeight,
1);
map += slice * sliceSize;
}
--
1.7.10.4
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[Mesa-dev] [PATCH 10/17] nouveau: Just use MapTextureImage instead of duplicating the logic.
MapTextureImage has the exact same logic, except it can also handle
swrast-allocated buffers.
---
src/mesa/drivers/dri/nouveau/nouveau_texture.c | 99 +---
1 file changed, 18 insertions(+), 81 deletions(-)
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_texture.c
b/src/mesa/drivers/dri/nouveau/nouveau_texture.c
index 4e3c26b..4176681 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_texture.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_texture.c
@@ -80,75 +80,6 @@ nouveau_teximage_free(struct gl_context *ctx, struct
gl_texture_image *ti)
}
static void
-nouveau_teximage_map(struct gl_context *ctx, struct gl_texture_image *ti,
-int access, int x, int y, int w, int h)
-{
- struct nouveau_teximage *nti = to_nouveau_teximage(ti);
- struct nouveau_surface *s = nti-surface;
- struct nouveau_surface *st = nti-transfer.surface;
- struct nouveau_client *client = context_client(ctx);
-
- if (s-bo) {
- if (!(access GL_MAP_READ_BIT)
- nouveau_pushbuf_refd(context_push(ctx), s-bo)) {
- unsigned size;
- /*
-* Heuristic: use a bounce buffer to pipeline
-* teximage transfers.
-*/
- st-layout = LINEAR;
- st-format = s-format;
- st-cpp = s-cpp;
- st-width = w;
- st-height = h;
- st-pitch = s-pitch;
- nti-transfer.x = x;
- nti-transfer.y = y;
-
- size = get_format_blocksy(st-format, h) * st-pitch;
- nti-base.Map = nouveau_get_scratch(ctx, size,
- st-bo, st-offset);
-
- } else {
- int ret, flags = 0;
-
- if (access GL_MAP_READ_BIT)
- flags |= NOUVEAU_BO_RD;
- if (access GL_MAP_WRITE_BIT)
- flags |= NOUVEAU_BO_WR;
-
- if (!s-bo-map) {
- ret = nouveau_bo_map(s-bo, flags, client);
- assert(!ret);
- }
-
- nti-base.Map = s-bo-map +
- get_format_blocksy(s-format, y) * s-pitch +
- get_format_blocksx(s-format, x) * s-cpp;
-
- }
- }
-}
-
-static void
-nouveau_teximage_unmap(struct gl_context *ctx, struct gl_texture_image *ti)
-{
- struct nouveau_teximage *nti = to_nouveau_teximage(ti);
- struct nouveau_surface *s = nti-surface;
- struct nouveau_surface *st = nti-transfer.surface;
-
- if (st-bo) {
- context_drv(ctx)-surface_copy(ctx, s, st, nti-transfer.x,
- nti-transfer.y, 0, 0,
- st-width, st-height);
- nouveau_surface_ref(NULL, st);
-
- }
- nti-base.Map = NULL;
-}
-
-
-static void
nouveau_map_texture_image(struct gl_context *ctx,
struct gl_texture_image *ti,
GLuint slice,
@@ -509,19 +440,24 @@ nouveau_teximage(struct gl_context *ctx, GLint dims,
pixels, packing, glTexImage);
if (pixels) {
+ GLubyte *map;
+ int row_stride;
+
/* Store the pixel data. */
- nouveau_teximage_map(ctx, ti, GL_MAP_WRITE_BIT,
-0, 0, ti-Width, ti-Height);
+ nouveau_map_texture_image(ctx, ti, 0,
+ 0, 0, ti-Width, ti-Height,
+ GL_MAP_WRITE_BIT,
+ map, row_stride);
ret = _mesa_texstore(ctx, dims, ti-_BaseFormat,
ti-TexFormat,
-s-pitch,
- nti-base.Map,
+row_stride,
+map,
ti-Width, ti-Height, depth,
format, type, pixels, packing);
assert(ret);
- nouveau_teximage_unmap(ctx, ti);
+ nouveau_unmap_texture_image(ctx, ti, 0);
_mesa_unmap_teximage_pbo(ctx, packing);
if (!validate_teximage(ctx, t, level, 0, 0, 0,
@@ -570,8 +506,6 @@ nouveau_texsubimage(struct gl_context *ctx, GLint dims,
const struct gl_pixelstore_attrib *packing,
GLboolean compressed)
{
- struct nouveau_surface *s = to_nouveau_teximage(ti)-surface;
- struct nouveau_teximage *nti = to_nouveau_teximage(ti);
[Mesa-dev] [PATCH 06/17] swrast: Reuse _swrast_free_texture_image_buffer from drivers.
---
src/mesa/drivers/dri/intel/intel_tex.c |8 +---
src/mesa/drivers/dri/radeon/radeon_texture.c |9 +
2 files changed, 2 insertions(+), 15 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_tex.c
b/src/mesa/drivers/dri/intel/intel_tex.c
index 2fbd5c4..24f13df 100644
--- a/src/mesa/drivers/dri/intel/intel_tex.c
+++ b/src/mesa/drivers/dri/intel/intel_tex.c
@@ -121,13 +121,7 @@ intel_free_texture_image_buffer(struct gl_context * ctx,
intel_miptree_release(intelImage-mt);
- if (intelImage-base.Buffer) {
- _mesa_align_free(intelImage-base.Buffer);
- intelImage-base.Buffer = NULL;
- }
-
- free(intelImage-base.ImageOffsets);
- intelImage-base.ImageOffsets = NULL;
+ _swrast_free_texture_image_buffer(ctx, texImage);
}
/**
diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c
b/src/mesa/drivers/dri/radeon/radeon_texture.c
index a953858..23942cb 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texture.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texture.c
@@ -127,20 +127,13 @@ void radeonFreeTextureImageBuffer(struct gl_context *ctx,
struct gl_texture_imag
if (image-mt) {
radeon_miptree_unreference(image-mt);
- } else {
- _swrast_free_texture_image_buffer(ctx, timage);
}
if (image-bo) {
radeon_bo_unref(image-bo);
image-bo = NULL;
}
- if (image-base.Buffer) {
- _mesa_align_free(image-base.Buffer);
- image-base.Buffer = NULL;
- }
- free(image-base.ImageOffsets);
- image-base.ImageOffsets = NULL;
+_swrast_free_texture_image_buffer(ctx, timage);
}
/**
--
1.7.10.4
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[Mesa-dev] [PATCH 05/17] swrast: Move ImageOffsets allocation to shared code.
---
src/mesa/drivers/dri/intel/intel_tex.c | 20 ++--
src/mesa/drivers/dri/radeon/radeon_texture.c | 15 ++-
src/mesa/swrast/s_texture.c | 24
src/mesa/swrast/swrast.h |2 +-
4 files changed, 17 insertions(+), 44 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_tex.c
b/src/mesa/drivers/dri/intel/intel_tex.c
index ee8db71..2fbd5c4 100644
--- a/src/mesa/drivers/dri/intel/intel_tex.c
+++ b/src/mesa/drivers/dri/intel/intel_tex.c
@@ -64,7 +64,6 @@ intel_alloc_texture_image_buffer(struct gl_context *ctx,
struct intel_texture_image *intel_image = intel_texture_image(image);
struct gl_texture_object *texobj = image-TexObject;
struct intel_texture_object *intel_texobj = intel_texture_object(texobj);
- GLuint slices;
assert(image-Border == 0);
@@ -81,23 +80,8 @@ intel_alloc_texture_image_buffer(struct gl_context *ctx,
*/
ctx-Driver.FreeTextureImageBuffer(ctx, image);
- /* Allocate the swrast_texture_image::ImageOffsets array now */
- switch (texobj-Target) {
- case GL_TEXTURE_3D:
- case GL_TEXTURE_2D_ARRAY:
- case GL_TEXTURE_2D_MULTISAMPLE_ARRAY:
- slices = image-Depth;
- break;
- case GL_TEXTURE_1D_ARRAY:
- slices = image-Height;
- break;
- default:
- slices = 1;
- }
- assert(!intel_image-base.ImageOffsets);
- intel_image-base.ImageOffsets = malloc(slices * sizeof(GLuint));
-
- _swrast_init_texture_image(image);
+ if (!_swrast_init_texture_image(image))
+ return false;
if (intel_texobj-mt
intel_miptree_match_image(intel_texobj-mt, image)) {
diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c
b/src/mesa/drivers/dri/radeon/radeon_texture.c
index b6e551c..a953858 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texture.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texture.c
@@ -105,23 +105,12 @@ radeonAllocTextureImageBuffer(struct gl_context *ctx,
struct gl_texture_image *timage)
{
radeonContextPtr rmesa = RADEON_CONTEXT(ctx);
- radeon_texture_image *image = get_radeon_texture_image(timage);
struct gl_texture_object *texobj = timage-TexObject;
- int slices;
ctx-Driver.FreeTextureImageBuffer(ctx, timage);
- switch (texobj-Target) {
- case GL_TEXTURE_3D:
- slices = timage-Depth;
- break;
- default:
- slices = 1;
- }
- assert(!image-base.ImageOffsets);
- image-base.ImageOffsets = malloc(slices * sizeof(GLuint));
-
- _swrast_init_texture_image(timage);
+ if (!_swrast_init_texture_image(timage))
+ return GL_FALSE;
teximage_assign_miptree(rmesa, texobj, timage);
diff --git a/src/mesa/swrast/s_texture.c b/src/mesa/swrast/s_texture.c
index b6dd8cb..c60fe2d 100644
--- a/src/mesa/swrast/s_texture.c
+++ b/src/mesa/swrast/s_texture.c
@@ -79,6 +79,9 @@ _swrast_alloc_texture_image_buffer(struct gl_context *ctx,
texImage-Height, texImage-Depth);
GLuint i;
+ if (!_swrast_init_texture_image(texImage))
+ return GL_FALSE;
+
assert(!swImg-Buffer);
swImg-Buffer = _mesa_align_malloc(bytes, 512);
if (!swImg-Buffer)
@@ -87,20 +90,10 @@ _swrast_alloc_texture_image_buffer(struct gl_context *ctx,
/* RowStride and ImageOffsets[] describe how to address texels in 'Data' */
swImg-RowStride = texImage-Width;
- /* Allocate the ImageOffsets array and initialize to typical values.
-* We allocate the array for 1D/2D textures too in order to avoid special-
-* case code in the texstore routines.
-*/
- swImg-ImageOffsets = malloc(texture_slices(texImage) * sizeof(GLuint));
- if (!swImg-ImageOffsets)
- return GL_FALSE;
-
for (i = 0; i texture_slices(texImage); i++) {
swImg-ImageOffsets[i] = i * texImage-Width * texImage-Height;
}
- _swrast_init_texture_image(texImage);
-
return GL_TRUE;
}
@@ -108,11 +101,11 @@ _swrast_alloc_texture_image_buffer(struct gl_context *ctx,
/**
* Code that overrides ctx-Driver.AllocTextureImageBuffer may use this to
* initialize the fields of swrast_texture_image without allocating the image
- * buffer or initializing ImageOffsets or RowStride.
+ * buffer or initializing RowStride or the contents of ImageOffsets.
*
* Returns GL_TRUE on success, GL_FALSE on memory allocation failure.
*/
-void
+GLboolean
_swrast_init_texture_image(struct gl_texture_image *texImage)
{
struct swrast_texture_image *swImg = swrast_texture_image(texImage);
@@ -136,6 +129,13 @@ _swrast_init_texture_image(struct gl_texture_image
*texImage)
swImg-HeightScale = (GLfloat) texImage-Height;
swImg-DepthScale = (GLfloat) texImage-Depth;
}
+
+ assert(!swImg-ImageOffsets);
+ swImg-ImageOffsets = malloc(texture_slices(texImage) * sizeof(GLuint));
+ if
[Mesa-dev] [PATCH 13/17] mesa: Remove the Map field from texture images.
--- src/mesa/swrast/s_context.h |1 - 1 file changed, 1 deletion(-) diff --git a/src/mesa/swrast/s_context.h b/src/mesa/swrast/s_context.h index 509759e..3e007b0 100644 --- a/src/mesa/swrast/s_context.h +++ b/src/mesa/swrast/s_context.h @@ -149,7 +149,6 @@ struct swrast_texture_image GLint RowStride; void **ImageSlices; /** if 3D texture: array [Depth] of offsets to each 2D slice in 'Data', in texels */ - GLubyte *Map; /** Pointer to mapped image memory */ /** Malloc'd texture memory */ GLubyte *Buffer; -- 1.7.10.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 09/17] swrast: Make a teximage's stored RowStride be in terms of bytes per row.
For hardware drivers with pitch alignment requirements, a
non-power-of-two-sized texture format won't end up being an integer number
of pixels per row. Also, avoids having to change our units between
MapTextureImage's rowStride and swrast's RowStride.
This doesn't fully convert the compressed texel fetch path, but does make
sure we don't drop any bits (not that we'd expect to).
---
src/mesa/swrast/s_context.h | 12 ++--
src/mesa/swrast/s_texfetch.c | 10 +-
src/mesa/swrast/s_texfetch_tmp.h |7 ---
src/mesa/swrast/s_texfilter.c|4 +++-
src/mesa/swrast/s_texture.c |3 ++-
src/mesa/swrast/s_triangle.c |3 ++-
6 files changed, 30 insertions(+), 9 deletions(-)
diff --git a/src/mesa/swrast/s_context.h b/src/mesa/swrast/s_context.h
index c9a8ee5..509759e 100644
--- a/src/mesa/swrast/s_context.h
+++ b/src/mesa/swrast/s_context.h
@@ -137,8 +137,16 @@ struct swrast_texture_image
/** used for mipmap LOD computation */
GLfloat WidthScale, HeightScale, DepthScale;
- /** These fields only valid when texture memory is mapped */
- GLint RowStride;/** Padded width in units of texels */
+ /**
+* Byte stride between rows in ImageSlices.
+*
+* For compressed textures, this is the byte stride between one row of
+* blocks and the next row of blocks.
+*
+* Only valid while one of the ImageSlices is mapped, and must be the same
+* between all slices.
+*/
+ GLint RowStride;
void **ImageSlices; /** if 3D texture: array [Depth] of offsets to
each 2D slice in 'Data', in texels */
GLubyte *Map; /** Pointer to mapped image memory */
diff --git a/src/mesa/swrast/s_texfetch.c b/src/mesa/swrast/s_texfetch.c
index fd9a93e..8438823 100644
--- a/src/mesa/swrast/s_texfetch.c
+++ b/src/mesa/swrast/s_texfetch.c
@@ -97,8 +97,16 @@ static void
fetch_compressed(const struct swrast_texture_image *swImage,
GLint i, GLint j, GLint k, GLfloat *texel)
{
+ /* The FetchCompressedTexel function takes an integer pixel rowstride,
+* while the image's rowstride is bytes per row of blocks.
+*/
+ GLuint bw, bh;
+ GLuint texelBytes = _mesa_get_format_bytes(swImage-Base.TexFormat);
+ _mesa_get_format_block_size(swImage-Base.TexFormat, bw, bh);
+ assert(swImage-RowStride * bw % texelBytes == 0);
+
swImage-FetchCompressedTexel(swImage-ImageSlices[k],
- swImage-RowStride,
+ swImage-RowStride * bw / texelBytes,
i, j, texel);
}
diff --git a/src/mesa/swrast/s_texfetch_tmp.h b/src/mesa/swrast/s_texfetch_tmp.h
index c2fdb89..2bf8042 100644
--- a/src/mesa/swrast/s_texfetch_tmp.h
+++ b/src/mesa/swrast/s_texfetch_tmp.h
@@ -51,15 +51,16 @@
#define TEXEL_ADDR( type, image, i, j, k, size ) \
((void) (k),\
-((type *)(image)-ImageSlices[0] + ((image)-RowStride * (j) + (i)) *
(size)))
+((type *)((image)-ImageSlices[0] + (image)-RowStride * (j)) + \
+ (i) * (size)))
#define FETCH(x) fetch_texel_2d_##x
#elif DIM == 3
#define TEXEL_ADDR( type, image, i, j, k, size ) \
- ((type *)(image)-ImageSlices[k] + \
- ((image)-RowStride * (j) + (i)) * (size))
+ ((type *)((image)-ImageSlices[k] + \
+ (image)-RowStride * (j)) + (i) * (size))
#define FETCH(x) fetch_texel_3d_##x
diff --git a/src/mesa/swrast/s_texfilter.c b/src/mesa/swrast/s_texfilter.c
index 9c28bfe..4c34d8d 100644
--- a/src/mesa/swrast/s_texfilter.c
+++ b/src/mesa/swrast/s_texfilter.c
@@ -1504,7 +1504,9 @@ sample_lambda_2d(struct gl_context *ctx,
const GLboolean repeatNoBorderPOT = (samp-WrapS == GL_REPEAT)
(samp-WrapT == GL_REPEAT)
- (tImg-Border == 0 (tImg-Width == swImg-RowStride))
+ (tImg-Border == 0)
+ (_mesa_format_row_stride(tImg-TexFormat, tImg-Width) ==
+ swImg-RowStride)
swImg-_IsPowerOfTwo;
ASSERT(lambda != NULL);
diff --git a/src/mesa/swrast/s_texture.c b/src/mesa/swrast/s_texture.c
index f6e0aa4..bfc2e9d 100644
--- a/src/mesa/swrast/s_texture.c
+++ b/src/mesa/swrast/s_texture.c
@@ -95,7 +95,8 @@ _swrast_alloc_texture_image_buffer(struct gl_context *ctx,
return GL_FALSE;
/* RowStride and ImageSlices[] describe how to address texels in 'Data' */
- swImg-RowStride = texImage-Width;
+ swImg-RowStride = _mesa_format_row_stride(texImage-TexFormat,
+ texImage-Width);
for (i = 0; i slices; i++) {
swImg-ImageSlices[i] = swImg-Buffer + bytesPerSlice * i;
diff --git a/src/mesa/swrast/s_triangle.c b/src/mesa/swrast/s_triangle.c
index 761c42d..dce5568 100644
--- a/src/mesa/swrast/s_triangle.c
+++ b/src/mesa/swrast/s_triangle.c
[Mesa-dev] [PATCH 08/17] swrast: Replace use of teximage Map in 1D/2D paths with ImageSlices[0].
This gets us ready for the Map field to die. --- src/mesa/swrast/s_texfetch_tmp.h |4 ++-- src/mesa/swrast/s_texfilter.c|4 ++-- src/mesa/swrast/s_triangle.c |8 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mesa/swrast/s_texfetch_tmp.h b/src/mesa/swrast/s_texfetch_tmp.h index e66de2d..c2fdb89 100644 --- a/src/mesa/swrast/s_texfetch_tmp.h +++ b/src/mesa/swrast/s_texfetch_tmp.h @@ -43,7 +43,7 @@ #if DIM == 1 #define TEXEL_ADDR( type, image, i, j, k, size ) \ - ((void) (j), (void) (k), ((type *)(image)-Map + (i) * (size))) + ((void) (j), (void) (k), ((type *)(image)-ImageSlices[0] + (i) * (size))) #define FETCH(x) fetch_texel_1d_##x @@ -51,7 +51,7 @@ #define TEXEL_ADDR( type, image, i, j, k, size ) \ ((void) (k),\ -((type *)(image)-Map + ((image)-RowStride * (j) + (i)) * (size))) +((type *)(image)-ImageSlices[0] + ((image)-RowStride * (j) + (i)) * (size))) #define FETCH(x) fetch_texel_2d_##x diff --git a/src/mesa/swrast/s_texfilter.c b/src/mesa/swrast/s_texfilter.c index ae3ffe5..9c28bfe 100644 --- a/src/mesa/swrast/s_texfilter.c +++ b/src/mesa/swrast/s_texfilter.c @@ -1435,7 +1435,7 @@ opt_sample_rgb_2d(struct gl_context *ctx, GLint i = IFLOOR(texcoords[k][0] * width) colMask; GLint j = IFLOOR(texcoords[k][1] * height) rowMask; GLint pos = (j shift) | i; - GLubyte *texel = swImg-Map + 3 * pos; + GLubyte *texel = swImg-ImageSlices[0] + 3 * pos; rgba[k][RCOMP] = UBYTE_TO_FLOAT(texel[2]); rgba[k][GCOMP] = UBYTE_TO_FLOAT(texel[1]); rgba[k][BCOMP] = UBYTE_TO_FLOAT(texel[0]); @@ -1480,7 +1480,7 @@ opt_sample_rgba_2d(struct gl_context *ctx, const GLint col = IFLOOR(texcoords[i][0] * width) colMask; const GLint row = IFLOOR(texcoords[i][1] * height) rowMask; const GLint pos = (row shift) | col; - const GLuint texel = *((GLuint *) swImg-Map + pos); + const GLuint texel = *((GLuint *) swImg-ImageSlices[0] + pos); rgba[i][RCOMP] = UBYTE_TO_FLOAT( (texel 24)); rgba[i][GCOMP] = UBYTE_TO_FLOAT( (texel 16) 0xff ); rgba[i][BCOMP] = UBYTE_TO_FLOAT( (texel 8) 0xff ); diff --git a/src/mesa/swrast/s_triangle.c b/src/mesa/swrast/s_triangle.c index f0b1d38..761c42d 100644 --- a/src/mesa/swrast/s_triangle.c +++ b/src/mesa/swrast/s_triangle.c @@ -133,7 +133,7 @@ _swrast_culltriangle( struct gl_context *ctx, const GLfloat twidth = (GLfloat) texImg-Width; \ const GLfloat theight = (GLfloat) texImg-Height; \ const GLint twidth_log2 = texImg-WidthLog2; \ - const GLubyte *texture = (const GLubyte *) swImg-Map; \ + const GLubyte *texture = (const GLubyte *) swImg-ImageSlices[0]; \ const GLint smask = texImg-Width - 1; \ const GLint tmask = texImg-Height - 1; \ ASSERT(texImg-TexFormat == MESA_FORMAT_RGB888);\ @@ -191,7 +191,7 @@ _swrast_culltriangle( struct gl_context *ctx, const GLfloat twidth = (GLfloat) texImg-Width; \ const GLfloat theight = (GLfloat) texImg-Height; \ const GLint twidth_log2 = texImg-WidthLog2; \ - const GLubyte *texture = (const GLubyte *) swImg-Map; \ + const GLubyte *texture = (const GLubyte *) swImg-ImageSlices[0]; \ const GLint smask = texImg-Width - 1; \ const GLint tmask = texImg-Height - 1; \ ASSERT(texImg-TexFormat == MESA_FORMAT_RGB888);\ @@ -547,7 +547,7 @@ affine_span(struct gl_context *ctx, SWspan *span, swrast_texture_image_const(texImg); \ const GLfloat twidth = (GLfloat) texImg-Width; \ const GLfloat theight = (GLfloat) texImg-Height; \ - info.texture = (const GLchan *) swImg-Map; \ + info.texture = (const GLchan *) swImg-ImageSlices[0]; \ info.twidth_log2 = texImg-WidthLog2; \ info.smask = texImg-Width - 1; \ info.tmask = texImg-Height - 1;\ @@ -814,7 +814,7 @@ fast_persp_span(struct gl_context *ctx, SWspan *span, obj-Image[0][obj-BaseLevel]; \ const struct swrast_texture_image *swImg = \ swrast_texture_image_const(texImg); \ - info.texture = (const GLchan *) swImg-Map; \ + info.texture = (const GLchan *) swImg-ImageSlices[0]; \ info.twidth_log2 = texImg-WidthLog2; \ info.smask = texImg-Width - 1;
[Mesa-dev] [PATCH 11/17] nouveau: Replace swrast_texture_image-Map usage with -Buffer.
This code is trying to deal with providing a map in the case that
AllocTexImageBuffer was called, which is hooked up to the swrast variant.
---
src/mesa/drivers/dri/nouveau/nouveau_texture.c |4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/nouveau/nouveau_texture.c
b/src/mesa/drivers/dri/nouveau/nouveau_texture.c
index 4176681..0889b5a 100644
--- a/src/mesa/drivers/dri/nouveau/nouveau_texture.c
+++ b/src/mesa/drivers/dri/nouveau/nouveau_texture.c
@@ -136,7 +136,7 @@ nouveau_map_texture_image(struct gl_context *ctx,
*stride = s-pitch;
}
} else {
- *map = nti-base.Map +
+ *map = nti-base.Buffer +
get_format_blocksy(s-format, y) * s-pitch +
get_format_blocksx(s-format, x) * s-cpp;
*stride = s-pitch;
@@ -158,8 +158,6 @@ nouveau_unmap_texture_image(struct gl_context *ctx, struct
gl_texture_image *ti,
nouveau_surface_ref(NULL, st);
}
-
- nti-base.Map = NULL;
}
static gl_format
--
1.7.10.4
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[Mesa-dev] [PATCH 07/17] swrast: Replace ImageOffsets with an ImageSlices pointer.
This is a step toward allowing drivers to use their normal mapping paths,
instead of requiring that all slice mappings come from an aligned offset
from the first slice's map.
This incidentally fixes missing slice handling in FXT1 swrast.
---
src/mesa/drivers/dri/intel/intel_tex_validate.c | 37
src/mesa/drivers/dri/radeon/radeon_texture.c| 13 ++---
src/mesa/main/texcompress.c |2 +-
src/mesa/main/texcompress.h |3 +-
src/mesa/main/texcompress_etc.c | 51 +++--
src/mesa/main/texcompress_fxt1.c|8 +--
src/mesa/main/texcompress_rgtc.c| 70 +--
src/mesa/main/texcompress_s3tc.c| 56 --
src/mesa/swrast/s_context.h |2 +-
src/mesa/swrast/s_texfetch.c|5 +-
src/mesa/swrast/s_texfetch_tmp.h|4 +-
src/mesa/swrast/s_texrender.c | 14 +
src/mesa/swrast/s_texture.c | 54 +
13 files changed, 127 insertions(+), 192 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_tex_validate.c
b/src/mesa/drivers/dri/intel/intel_tex_validate.c
index c880bce..6068733 100644
--- a/src/mesa/drivers/dri/intel/intel_tex_validate.c
+++ b/src/mesa/drivers/dri/intel/intel_tex_validate.c
@@ -163,34 +163,19 @@ intel_tex_map_image_for_swrast(struct intel_context
*intel,
for (int i = 0; i mt-level[level].depth; i++)
intel_miptree_slice_resolve_depth(intel, mt, level, i);
- if (mt-target == GL_TEXTURE_3D ||
- mt-target == GL_TEXTURE_2D_ARRAY ||
- mt-target == GL_TEXTURE_1D_ARRAY) {
- int i;
-
- /* ImageOffsets[] is only used for swrast's fetch_texel_3d, so we can't
- * share code with the normal path.
- */
- for (i = 0; i mt-level[level].depth; i++) {
-intel_miptree_get_image_offset(mt, level, i, x, y);
-intel_image-base.ImageOffsets[i] = x + y * (mt-region-pitch /
- mt-region-cpp);
- }
-
- DBG(%s \n, __FUNCTION__);
-
- intel_image-base.Map = intel_miptree_map_raw(intel, mt);
- } else {
- assert(intel_image-base.Base.Depth == 1);
- intel_miptree_get_image_offset(mt, level, face, x, y);
-
- DBG(%s: (%d,%d) - (%d, %d)/%d\n,
- __FUNCTION__, face, level, x, y, mt-region-pitch);
-
- intel_image-base.Map = intel_miptree_map_raw(intel, mt) +
-x * mt-cpp + y * mt-region-pitch;
+ void *map = intel_miptree_map_raw(intel, mt);
+
+ for (int i = 0; i mt-level[level].depth; i++) {
+ intel_miptree_get_image_offset(mt, level, i, x, y);
+ intel_image-base.ImageSlices[i] = (map +
+ y * mt-region-pitch +
+ x * mt-cpp);
+ DBG(%s: (%d,%d,%d) - (%d, %d)/%d\n,
+ __FUNCTION__, face, level, i, x, y, mt-region-pitch);
}
+ intel_image-base.Map = intel_image-base.ImageSlices[0];
+
assert(mt-region-pitch % mt-region-cpp == 0);
intel_image-base.RowStride = mt-region-pitch / mt-region-cpp;
}
diff --git a/src/mesa/drivers/dri/radeon/radeon_texture.c
b/src/mesa/drivers/dri/radeon/radeon_texture.c
index 23942cb..aa2f734 100644
--- a/src/mesa/drivers/dri/radeon/radeon_texture.c
+++ b/src/mesa/drivers/dri/radeon/radeon_texture.c
@@ -638,7 +638,6 @@ radeon_swrast_map_image(radeonContextPtr rmesa,
radeon_mipmap_tree *mt;
GLuint texel_size;
radeon_mipmap_level *lvl;
- int rs;
if (!image || !image-mt)
return;
@@ -650,18 +649,16 @@ radeon_swrast_map_image(radeonContextPtr rmesa,
lvl = image-mt-levels[level];
- rs = lvl-rowstride / texel_size;
-
radeon_bo_map(mt-bo, 1);
image-base.Map = mt-bo-ptr + lvl-faces[face].offset;
- if (mt-target == GL_TEXTURE_3D) {
- int i;
- for (i = 0; i mt-levels[level].depth; i++)
- image-base.ImageOffsets[i] = rs * lvl-height * i;
+ for (int i = 0; i mt-levels[level].depth; i++) {
+ image-base.ImageSlices[i] =
+ image-base.Map + (lvl-rowstride * lvl-height * i);
}
- image-base.RowStride = rs;
+
+ image-base.RowStride = lvl-rowstride / texel_size;
}
static void
diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index f74ac5d..1afd51c 100644
--- a/src/mesa/main/texcompress.c
+++ b/src/mesa/main/texcompress.c
@@ -587,7 +587,7 @@ _mesa_decompress_image(gl_format format, GLuint width,
GLuint height,
for (j = 0; j height; j++) {
for (i = 0; i width; i++) {
- fetch(src, NULL, stride, i, j, 0, dest);
+ fetch(src, stride, i, j, dest);
dest += 4;
}
}
diff --git a/src/mesa/main/texcompress.h b/src/mesa/main/texcompress.h
index 50c0293..772e1a9
[Mesa-dev] [PATCH 12/17] swrast: Always use MapTextureImage for mapping textures for swrast.
Now that everything goes through ImageSlices[], we can rely on the
driver's existing texture mapping function.
A big block of code goes away on Radeon that looks like it was to deal with
the validate that happened at SpanRenderStart, which no longer occurs since we
don't need validation for the MapTextureImage hook.
---
src/mesa/drivers/dri/i915/intel_tris.c |2 -
src/mesa/drivers/dri/intel/intel_span.c | 80 ++-
src/mesa/drivers/dri/intel/intel_span.h |2 -
src/mesa/drivers/dri/intel/intel_tex.h |6 --
src/mesa/drivers/dri/intel/intel_tex_validate.c | 90 --
src/mesa/drivers/dri/radeon/radeon_mipmap_tree.c | 21 -
src/mesa/drivers/dri/radeon/radeon_span.c| 18 +
src/mesa/drivers/dri/radeon/radeon_texture.c | 74 --
src/mesa/drivers/dri/radeon/radeon_texture.h |3 -
src/mesa/swrast/s_texture.c | 61 ---
10 files changed, 59 insertions(+), 298 deletions(-)
diff --git a/src/mesa/drivers/dri/i915/intel_tris.c
b/src/mesa/drivers/dri/i915/intel_tris.c
index 4516db6..30eb6ac 100644
--- a/src/mesa/drivers/dri/i915/intel_tris.c
+++ b/src/mesa/drivers/dri/i915/intel_tris.c
@@ -1096,11 +1096,9 @@ intelRunPipeline(struct gl_context * ctx)
intel-NewGLState = 0;
}
- intel_map_vertex_shader_textures(ctx);
intel-tnl_pipeline_running = true;
_tnl_run_pipeline(ctx);
intel-tnl_pipeline_running = false;
- intel_unmap_vertex_shader_textures(ctx);
_mesa_unlock_context_textures(ctx);
}
diff --git a/src/mesa/drivers/dri/intel/intel_span.c
b/src/mesa/drivers/dri/intel/intel_span.c
index d7eaa41..e74398d 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -105,31 +105,8 @@ intel_offset_S8(uint32_t stride, uint32_t x, uint32_t y,
bool swizzled)
}
/**
- * Map the regions needed by intelSpanRenderStart().
- */
-static void
-intel_span_map_buffers(struct intel_context *intel)
-{
- struct gl_context *ctx = intel-ctx;
- struct intel_texture_object *tex_obj;
-
- for (int i = 0; i ctx-Const.MaxTextureImageUnits; i++) {
- if (!ctx-Texture.Unit[i]._ReallyEnabled)
-continue;
- tex_obj = intel_texture_object(ctx-Texture.Unit[i]._Current);
- intel_finalize_mipmap_tree(intel, i);
- intel_tex_map_images(intel, tex_obj,
- GL_MAP_READ_BIT | GL_MAP_WRITE_BIT);
- }
-
- _swrast_map_renderbuffers(ctx);
-}
-
-/**
* Prepare for software rendering. Map current read/draw framebuffers'
- * renderbuffes and all currently bound texture objects.
- *
- * Old note: Moved locking out to get reasonable span performance.
+ * renderbuffers and all currently bound texture objects.
*/
void
intelSpanRenderStart(struct gl_context * ctx)
@@ -139,7 +116,9 @@ intelSpanRenderStart(struct gl_context * ctx)
intel_flush(ctx);
intel_prepare_render(intel);
intel_flush(ctx);
- intel_span_map_buffers(intel);
+
+ _swrast_map_textures(ctx);
+ _swrast_map_renderbuffers(ctx);
}
/**
@@ -149,18 +128,8 @@ intelSpanRenderStart(struct gl_context * ctx)
void
intelSpanRenderFinish(struct gl_context * ctx)
{
- struct intel_context *intel = intel_context(ctx);
- GLuint i;
-
_swrast_flush(ctx);
-
- for (i = 0; i ctx-Const.MaxTextureImageUnits; i++) {
- if (ctx-Texture.Unit[i]._ReallyEnabled) {
- struct gl_texture_object *texObj = ctx-Texture.Unit[i]._Current;
- intel_tex_unmap_images(intel, intel_texture_object(texObj));
- }
- }
-
+ _swrast_unmap_textures(ctx);
_swrast_unmap_renderbuffers(ctx);
}
@@ -174,42 +143,3 @@ intelInitSpanFuncs(struct gl_context * ctx)
swdd-SpanRenderFinish = intelSpanRenderFinish;
}
}
-
-void
-intel_map_vertex_shader_textures(struct gl_context *ctx)
-{
- struct intel_context *intel = intel_context(ctx);
- int i;
-
- if (ctx-VertexProgram._Current == NULL)
- return;
-
- for (i = 0; i ctx-Const.MaxTextureImageUnits; i++) {
- if (ctx-Texture.Unit[i]._ReallyEnabled
- ctx-VertexProgram._Current-Base.TexturesUsed[i] != 0) {
- struct gl_texture_object *texObj = ctx-Texture.Unit[i]._Current;
-
- intel_tex_map_images(intel, intel_texture_object(texObj),
- GL_MAP_READ_BIT | GL_MAP_WRITE_BIT);
- }
- }
-}
-
-void
-intel_unmap_vertex_shader_textures(struct gl_context *ctx)
-{
- struct intel_context *intel = intel_context(ctx);
- int i;
-
- if (ctx-VertexProgram._Current == NULL)
- return;
-
- for (i = 0; i ctx-Const.MaxTextureImageUnits; i++) {
- if (ctx-Texture.Unit[i]._ReallyEnabled
- ctx-VertexProgram._Current-Base.TexturesUsed[i] != 0) {
- struct gl_texture_object *texObj = ctx-Texture.Unit[i]._Current;
-
- intel_tex_unmap_images(intel, intel_texture_object(texObj));
- }
- }
-}
diff --git
[Mesa-dev] [PATCH 14/17] mesa: Add a clarifying comment about rowStride of compressed textures.
I always forget how we do this for compressed textures.
---
src/mesa/main/dd.h |4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/main/dd.h b/src/mesa/main/dd.h
index 8f3cd3d..471d963 100644
--- a/src/mesa/main/dd.h
+++ b/src/mesa/main/dd.h
@@ -354,7 +354,9 @@ struct dd_function_table {
* \param mode bitmask of GL_MAP_READ_BIT, GL_MAP_WRITE_BIT and
* GL_MAP_INVALIDATE_RANGE_BIT (if writing)
* \param mapOut returns start of mapping of region of interest
-* \param rowStrideOut returns row stride (in bytes)
+* \param rowStrideOut returns row stride (in bytes). In the case of a
+* compressed texture, this is the byte stride between one row of blocks
+* and another.
*/
void (*MapTextureImage)(struct gl_context *ctx,
struct gl_texture_image *texImage,
--
1.7.10.4
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[Mesa-dev] [PATCH 15/17] intel: Ensure renderbuffers are current when mapping them.
In the case of renering to windows in X, we would render to stale buffers
(or not render at all!) if you hit a MapRenderbuffer as the first thing
done to your window after new buffers are ready to be collected in DRI2.
I think this also covers the weird comment about irb-mt being missing
sometimes.
---
src/mesa/drivers/dri/intel/intel_fbo.c |7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_fbo.c
b/src/mesa/drivers/dri/intel/intel_fbo.c
index d22de68..21c30f8 100644
--- a/src/mesa/drivers/dri/intel/intel_fbo.c
+++ b/src/mesa/drivers/dri/intel/intel_fbo.c
@@ -123,12 +123,7 @@ intel_map_renderbuffer(struct gl_context *ctx,
return;
}
- /* We sometimes get called with this by our intel_span.c usage. */
- if (!irb-mt) {
- *out_map = NULL;
- *out_stride = 0;
- return;
- }
+ intel_prepare_render(intel);
/* For a window-system renderbuffer, we need to flip the mapping we receive
* upside-down. So we need to ask for a rectangle on flipped vertically,
and
--
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[Mesa-dev] [PATCH 16/17] intel: Move the S8 offset calc function near its remaining usage.
It's not really span code ever since we stopped using spans for S8.
---
src/mesa/drivers/dri/intel/intel_mipmap_tree.c | 56
src/mesa/drivers/dri/intel/intel_span.c| 56
src/mesa/drivers/dri/intel/intel_span.h|2 -
3 files changed, 56 insertions(+), 58 deletions(-)
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 47f81b1..126970e 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -1215,6 +1215,62 @@ intel_miptree_all_slices_resolve_depth(struct
intel_context *intel,
GEN6_HIZ_OP_DEPTH_RESOLVE);
}
+/**
+ * \brief Get pointer offset into stencil buffer.
+ *
+ * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
+ * must decode the tile's layout in software.
+ *
+ * See
+ * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
+ * Format.
+ * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
+ *
+ * Even though the returned offset is always positive, the return type is
+ * signed due to
+ *commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
+ *mesa: Fix return type of _mesa_get_format_bytes() (#37351)
+ */
+static intptr_t
+intel_offset_S8(uint32_t stride, uint32_t x, uint32_t y, bool swizzled)
+{
+ uint32_t tile_size = 4096;
+ uint32_t tile_width = 64;
+ uint32_t tile_height = 64;
+ uint32_t row_size = 64 * stride;
+
+ uint32_t tile_x = x / tile_width;
+ uint32_t tile_y = y / tile_height;
+
+ /* The byte's address relative to the tile's base addres. */
+ uint32_t byte_x = x % tile_width;
+ uint32_t byte_y = y % tile_height;
+
+ uintptr_t u = tile_y * row_size
+ + tile_x * tile_size
+ + 512 * (byte_x / 8)
+ + 64 * (byte_y / 8)
+ + 32 * ((byte_y / 4) % 2)
+ + 16 * ((byte_x / 4) % 2)
+ + 8 * ((byte_y / 2) % 2)
+ + 4 * ((byte_x / 2) % 2)
+ + 2 * (byte_y % 2)
+ + 1 * (byte_x % 2);
+
+ if (swizzled) {
+ /* adjust for bit6 swizzling */
+ if (((byte_x / 8) % 2) == 1) {
+if (((byte_y / 8) % 2) == 0) {
+ u += 64;
+} else {
+ u -= 64;
+}
+ }
+ }
+
+ return u;
+}
+
static void
intel_miptree_updownsample(struct intel_context *intel,
struct intel_mipmap_tree *src,
diff --git a/src/mesa/drivers/dri/intel/intel_span.c
b/src/mesa/drivers/dri/intel/intel_span.c
index e74398d..940f3c2 100644
--- a/src/mesa/drivers/dri/intel/intel_span.c
+++ b/src/mesa/drivers/dri/intel/intel_span.c
@@ -49,62 +49,6 @@
#include swrast/s_renderbuffer.h
/**
- * \brief Get pointer offset into stencil buffer.
- *
- * The stencil buffer is W tiled. Since the GTT is incapable of W fencing, we
- * must decode the tile's layout in software.
- *
- * See
- * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.2.1 W-Major Tile
- * Format.
- * - PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section 4.5.3 Tiling Algorithm
- *
- * Even though the returned offset is always positive, the return type is
- * signed due to
- *commit e8b1c6d6f55f5be3bef25084fdd8b6127517e137
- *mesa: Fix return type of _mesa_get_format_bytes() (#37351)
- */
-intptr_t
-intel_offset_S8(uint32_t stride, uint32_t x, uint32_t y, bool swizzled)
-{
- uint32_t tile_size = 4096;
- uint32_t tile_width = 64;
- uint32_t tile_height = 64;
- uint32_t row_size = 64 * stride;
-
- uint32_t tile_x = x / tile_width;
- uint32_t tile_y = y / tile_height;
-
- /* The byte's address relative to the tile's base addres. */
- uint32_t byte_x = x % tile_width;
- uint32_t byte_y = y % tile_height;
-
- uintptr_t u = tile_y * row_size
- + tile_x * tile_size
- + 512 * (byte_x / 8)
- + 64 * (byte_y / 8)
- + 32 * ((byte_y / 4) % 2)
- + 16 * ((byte_x / 4) % 2)
- + 8 * ((byte_y / 2) % 2)
- + 4 * ((byte_x / 2) % 2)
- + 2 * (byte_y % 2)
- + 1 * (byte_x % 2);
-
- if (swizzled) {
- /* adjust for bit6 swizzling */
- if (((byte_x / 8) % 2) == 1) {
-if (((byte_y / 8) % 2) == 0) {
- u += 64;
-} else {
- u -= 64;
-}
- }
- }
-
- return u;
-}
-
-/**
* Prepare for software rendering. Map current read/draw framebuffers'
* renderbuffers and all currently bound texture objects.
*/
diff --git a/src/mesa/drivers/dri/intel/intel_span.h
b/src/mesa/drivers/dri/intel/intel_span.h
index 412f244..ba49df9 100644
--- a/src/mesa/drivers/dri/intel/intel_span.h
+++ b/src/mesa/drivers/dri/intel/intel_span.h
@@ -36,6 +36,4 @@ extern void intelInitSpanFuncs(struct gl_context * ctx);
extern void intelSpanRenderFinish(struct
Re: [Mesa-dev] [PATCH] i965: Fix a mistake in the comments for software counters.
Kenneth Graunke kenn...@whitecape.org writes: The code doesn't set brw-query.obj to NULL, it sets query-bo to NULL. Reviewed-by: Eric Anholt e...@anholt.net pgpHt7PZ8akua.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 03/14] mesa: move _NEW_BUFFER_OBJECT flagging from BufferData to drivers
Marek Olšák mar...@gmail.com writes: A driver doesn't have to set _NEW_BUFFER_OBJECT if it doesn't reallocate the buffer from core Mesa's point of view, which avoids unnecessary state validation. Gallium drivers can be asked to reallocate a buffer privately by setting PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE. st/mesa doesn't set _NEW_BUFFER_OBJECT if transfer_inline_write is used. _NEW_BUFFER_OBJECT is used in Mesa core only for MaxElement updates. So Mesa core could flag its state update only when size changes and have its state tracking correct, and then the question is what drivers need to track internally when they need to, say, shove a new BO data pointer down to the hardware. Elsewhere, your plan seems to be for drivers to define their own flags, while in this case you have the driver start adding core flags to NewState. We have a few cases of that already (radeon FBOs, and a piece in st_cb_fbo.c that looks dubious), but I think I'd rather see progress towards making that go away in favor of NewDriverState like you do in the rest of the series. diff --git a/src/mesa/drivers/dri/nouveau/nouveau_bufferobj.c b/src/mesa/drivers/dri/nouveau/nouveau_bufferobj.c index 717c0b8..2508933 100644 --- a/src/mesa/drivers/dri/nouveau/nouveau_bufferobj.c +++ b/src/mesa/drivers/dri/nouveau/nouveau_bufferobj.c @@ -79,7 +79,9 @@ nouveau_bufferobj_data(struct gl_context *ctx, GLenum target, GLsizeiptrARB size struct nouveau_bufferobj *nbo = to_nouveau_bufferobj(obj); int ret; - obj-Size = size; +ctx-NewState |= _NEW_BUFFER_OBJECT; + +obj-Size = size; obj-Usage = usage; /* Free previous storage */ nouveau is tab indentation (quite consistently, too). I should dump in the .dir-locals.el needed, since I threw some together for my recent swrast work. pgpwuenVrHrN9.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 04/14] mesa: remove redundant _NEW_BUFFERS setting in ReadPixels
Marek Olšák mar...@gmail.com writes: already set by _mesa_readbuffer --- src/mesa/main/buffers.c |1 - 1 file changed, 1 deletion(-) diff --git a/src/mesa/main/buffers.c b/src/mesa/main/buffers.c index 3f5cbcd..36b0312 100644 --- a/src/mesa/main/buffers.c +++ b/src/mesa/main/buffers.c @@ -645,7 +645,6 @@ _mesa_ReadBuffer(GLenum buffer) /* OK, all error checking has been completed now */ _mesa_readbuffer(ctx, buffer, srcBuffer); - ctx-NewState |= _NEW_BUFFERS; /* * Call device driver function. Reviewed-by: Eric Anholt e...@anholt.net pgpIbN9jaf6Nz.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 03/17] swrast: Factor out texture slice counting.
On Mon, Apr 22, 2013 at 11:14 AM, Eric Anholt e...@anholt.net wrote:
This function going to get used a lot more in upcoming patches.
---
src/mesa/swrast/s_texture.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/mesa/swrast/s_texture.c b/src/mesa/swrast/s_texture.c
index 51048be..36a90dd 100644
--- a/src/mesa/swrast/s_texture.c
+++ b/src/mesa/swrast/s_texture.c
@@ -58,6 +58,14 @@ _swrast_delete_texture_image(struct gl_context *ctx,
_mesa_delete_texture_image(ctx, texImage);
}
+static unsigned int
+texture_slices(struct gl_texture_image *texImage)
+{
+ if (texImage-TexObject-Target == GL_TEXTURE_1D_ARRAY)
+ return texImage-Height;
+ else
+ return texImage-Depth;
+}
I think you can const-qualify 'texImage'.
/**
* Called via ctx-Driver.AllocTextureImageBuffer()
@@ -83,11 +91,11 @@ _swrast_alloc_texture_image_buffer(struct gl_context
*ctx,
* We allocate the array for 1D/2D textures too in order to avoid
special-
* case code in the texstore routines.
*/
- swImg-ImageOffsets = malloc(texImage-Depth * sizeof(GLuint));
+ swImg-ImageOffsets = malloc(texture_slices(texImage) *
sizeof(GLuint));
if (!swImg-ImageOffsets)
return GL_FALSE;
- for (i = 0; i texImage-Depth; i++) {
+ for (i = 0; i texture_slices(texImage); i++) {
swImg-ImageOffsets[i] = i * texImage-Width * texImage-Height;
}
@@ -209,20 +217,20 @@ _swrast_map_teximage(struct gl_context *ctx,
map = swImage-Buffer;
+ assert(slice texture_slices(texImage));
+
if (texImage-TexObject-Target == GL_TEXTURE_3D ||
texImage-TexObject-Target == GL_TEXTURE_2D_ARRAY) {
GLuint sliceSize = _mesa_format_image_size(texImage-TexFormat,
texImage-Width,
texImage-Height,
1);
- assert(slice texImage-Depth);
map += slice * sliceSize;
} else if (texImage-TexObject-Target == GL_TEXTURE_1D_ARRAY) {
GLuint sliceSize = _mesa_format_image_size(texImage-TexFormat,
texImage-Width,
1,
1);
- assert(slice texImage-Height);
map += slice * sliceSize;
}
--
1.7.10.4
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[Mesa-dev] [PATCH] mesa: fix MapBufferRange/MapBuffer typo in create_beginend_table()
MapBufferRange was present twice. MapBuffer was missing. Note: This is a candidate for the stable branches. --- src/mesa/main/context.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c index ce76243..0fb57ad 100644 --- a/src/mesa/main/context.c +++ b/src/mesa/main/context.c @@ -922,7 +922,7 @@ create_beginend_table(const struct gl_context *ctx) COPY_DISPATCH(ClientWaitSync); COPY_DISPATCH(MapBuffer); COPY_DISPATCH(UnmapBuffer); - COPY_DISPATCH(MapBufferRange); + COPY_DISPATCH(MapBuffer); COPY_DISPATCH(MapBufferRange); COPY_DISPATCH(ObjectPurgeableAPPLE); COPY_DISPATCH(ObjectUnpurgeableAPPLE); -- 1.7.3.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa: fix bogus comment about PrimitiveRestart fields
Chris Forbes chr...@ijw.co.nz writes:
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/main/mtypes.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 6108a35..7b51ec8 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -1536,8 +1536,8 @@ struct gl_array_attrib
* \name Primitive restart controls
*
* Primitive restart is enabled if either \c PrimitiveRestart or
-* \c PrimitiveRestart is set. If \c PrimitiveRestart is set, then
-* \c RestartIndex is used as the cut vertex. Otherwise ~0 is used.
+* \c PrimitiveRestartFixedIndex is set. If \c PrimitiveRestart is set,
+* then \c RestartIndex is used as the cut vertex. Otherwise ~0 is used.
*/
/*@{*/
GLboolean PrimitiveRestart;
Reviewed-by: Eric Anholt e...@anholt.net
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Re: [Mesa-dev] [PATCH 4/8] intel: prepare for dri images having more than plane
Pohjolainen, Topi topi.pohjolai...@intel.com writes: On Tue, Apr 16, 2013 at 04:57:49PM -0700, Eric Anholt wrote: Topi Pohjolainen topi.pohjolai...@intel.com writes: + if (image-regions[i]-bo) + intel_region_release(image-regions[i]); Why are you looking at the BO for deciding whether to free the region? A region should always have a BO. If you're trying to null-check the region, intel_region_release already does that. As I switched to using a fixed sized array of regions (holding up-to-three planes), the images having one or two planes would have the rest of the regions initialized to zero. And I simply decided to use the 'bo'-pointer as telling if the region was in use or not. The struct has an array of region pointers, and there's no region should be region[i] == NULL, not region[i]-bo == NULL. pgp9lD_EX5qRd.pgp Description: PGP signature ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa: fix MapBufferRange/MapBuffer typo in create_beginend_table()
On 04/22/2013 11:38 AM, Brian Paul wrote: MapBufferRange was present twice. MapBuffer was missing. Note: This is a candidate for the stable branches. --- src/mesa/main/context.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c index ce76243..0fb57ad 100644 --- a/src/mesa/main/context.c +++ b/src/mesa/main/context.c @@ -922,7 +922,7 @@ create_beginend_table(const struct gl_context *ctx) COPY_DISPATCH(ClientWaitSync); COPY_DISPATCH(MapBuffer); COPY_DISPATCH(UnmapBuffer); - COPY_DISPATCH(MapBufferRange); + COPY_DISPATCH(MapBuffer); COPY_DISPATCH(MapBufferRange); COPY_DISPATCH(ObjectPurgeableAPPLE); COPY_DISPATCH(ObjectUnpurgeableAPPLE); Jose pointed out that MapBuffer already appears a few lines earlier. I'll post a new patch that just removes the duplicate. -Brian ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH] mesa: Remove extra MapBufferRange in create_beginend_table()
Looks like a copypaste typo. --- src/mesa/main/context.c |1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c index ce76243..9d915b6 100644 --- a/src/mesa/main/context.c +++ b/src/mesa/main/context.c @@ -923,7 +923,6 @@ create_beginend_table(const struct gl_context *ctx) COPY_DISPATCH(MapBuffer); COPY_DISPATCH(UnmapBuffer); COPY_DISPATCH(MapBufferRange); - COPY_DISPATCH(MapBufferRange); COPY_DISPATCH(ObjectPurgeableAPPLE); COPY_DISPATCH(ObjectUnpurgeableAPPLE); -- 1.7.3.4 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa: Remove extra MapBufferRange in create_beginend_table()
- Original Message - Looks like a copypaste typo. --- src/mesa/main/context.c |1 - 1 files changed, 0 insertions(+), 1 deletions(-) diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c index ce76243..9d915b6 100644 --- a/src/mesa/main/context.c +++ b/src/mesa/main/context.c @@ -923,7 +923,6 @@ create_beginend_table(const struct gl_context *ctx) COPY_DISPATCH(MapBuffer); COPY_DISPATCH(UnmapBuffer); COPY_DISPATCH(MapBufferRange); - COPY_DISPATCH(MapBufferRange); COPY_DISPATCH(ObjectPurgeableAPPLE); COPY_DISPATCH(ObjectUnpurgeableAPPLE); Reviewed-by: Jose Fonseca jfons...@vmware.com ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa: fix MapBufferRange/MapBuffer typo in create_beginend_table()
On 22/04/13 19:38, Brian Paul wrote: MapBufferRange was present twice. MapBuffer was missing. Note: This is a candidate for the stable branches. --- src/mesa/main/context.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c index ce76243..0fb57ad 100644 --- a/src/mesa/main/context.c +++ b/src/mesa/main/context.c @@ -922,7 +922,7 @@ create_beginend_table(const struct gl_context *ctx) COPY_DISPATCH(ClientWaitSync); COPY_DISPATCH(MapBuffer); It's already here COPY_DISPATCH(UnmapBuffer); - COPY_DISPATCH(MapBufferRange); + COPY_DISPATCH(MapBuffer); COPY_DISPATCH(MapBufferRange); Maybe 'UnmapBufferRange'? COPY_DISPATCH(ObjectPurgeableAPPLE); COPY_DISPATCH(ObjectUnpurgeableAPPLE); -- Ferry Huberts ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 2/2] i965: Add support for GL_AMD_performance_monitor on Ironlake.
On 04/12/2013 11:21 AM, Eric Anholt wrote:
Kenneth Graunke kenn...@whitecape.org writes:
Ironlake's counters are always enabled; userspace can simply send a
MI_REPROT_PERF_COUNT packet to take a snapshot of them. This makes it
easy to implement.
The counters are documented in the source code for the intel-gpu-tools
intel_perf_counters utility.
+/**
+ * i965 representation of a performance monitor object.
+ */
+struct brw_perf_monitor_object
+{
+ /** The base class. */
+ struct gl_perf_monitor_object base;
+
+ /**
+* The GPU-facing BO, holding raw counter data in a hardware specific form.
+*/
+ drm_intel_bo *gpu_facing_bo;
+};
Why all the emphasis of GPU-facing? We don't use BOs for anything
that the GPU doesn't touch.
At one point, I thought that we returned the data to the application in
a buffer object...so we'd have two BOs, one GPU-facing, and one
API-facing. But we actually just copy it to them via a normal pointer,
so the careful distinction isn't necessary.
I'll rename it to bo in the next version.
+/**
+ * Driver hook for glEndPerformanceMonitorAMD().
+ */
+static void
+brw_end_perf_monitor(struct gl_context *ctx,
+ struct gl_perf_monitor_object *m)
+{
+ struct brw_context *brw = brw_context(ctx);
+ struct brw_perf_monitor_object *monitor = brw_perf_monitor(m);
+ if (aggregating_counters_needed(brw, m)) {
+ snapshot_aggregating_counters(brw, monitor-gpu_facing_bo,
+brw-perfmon.total_counter_size);
At least some variants of the command require 64b alignment -- I'd
probably stick the ending dump at some fixed offset in the BO, like
halfway through.
Sounds like a good idea. It ended up working out, but using a fixed
2048 byte offset is guaranteed to work out and simplifies things.
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Re: [Mesa-dev] [PATCH 2/2] i965: Add support for GL_AMD_performance_monitor on Ironlake.
On 04/12/2013 01:16 PM, Eric Anholt wrote:
Kenneth Graunke kenn...@whitecape.org writes:
Ironlake's counters are always enabled; userspace can simply send a
MI_REPROT_PERF_COUNT packet to take a snapshot of them. This makes it
easy to implement.
The counters are documented in the source code for the intel-gpu-tools
intel_perf_counters utility.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
+/**
+ * Is a performance monitor result available?
+ */
+static GLboolean
+brw_is_perf_monitor_result_available(struct gl_perf_monitor_object *m)
+{
+ struct brw_perf_monitor_object *monitor = brw_perf_monitor(m);
+ return !m-Active monitor-gpu_facing_bo
+ !drm_intel_bo_busy(monitor-gpu_facing_bo);
+}
This also needs to check for !drm_intel_bo_references by the batch --
otherwise if the batch hasn't flushed, we'll report result_available
when it isn't ready.
Good catch. Fixed for v2. Thanks!
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Re: [Mesa-dev] [PATCH 03/17] swrast: Factor out texture slice counting.
Patrick Baggett baggett.patr...@gmail.com writes:
On Mon, Apr 22, 2013 at 11:14 AM, Eric Anholt e...@anholt.net wrote:
This function going to get used a lot more in upcoming patches.
---
src/mesa/swrast/s_texture.c | 16
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/src/mesa/swrast/s_texture.c b/src/mesa/swrast/s_texture.c
index 51048be..36a90dd 100644
--- a/src/mesa/swrast/s_texture.c
+++ b/src/mesa/swrast/s_texture.c
@@ -58,6 +58,14 @@ _swrast_delete_texture_image(struct gl_context *ctx,
_mesa_delete_texture_image(ctx, texImage);
}
+static unsigned int
+texture_slices(struct gl_texture_image *texImage)
+{
+ if (texImage-TexObject-Target == GL_TEXTURE_1D_ARRAY)
+ return texImage-Height;
+ else
+ return texImage-Depth;
+}
I think you can const-qualify 'texImage'.
Given that const-qualification does nothing for generated code and just
consumes developer time, I don't do it unless someone blocks review on
it.
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Re: [Mesa-dev] [PATCH resend] mesa: Add core support for the GL_AMD_performance_monitor extension.
On 04/13/2013 11:07 AM, Christoph Bumiller wrote:
On 12.04.2013 21:14, Kenneth Graunke wrote:
This provides an interface for applications (and OpenGL-based tools) to
access GPU performance counters. Since the exact performance counters
available vary between vendors and hardware generations, the extension
provides an API the application can use to get the names, types, and
minimum/maximum values of all available counters. Counters are also
organized into groups.
+ /**
+* \name Performance monitors
+*/
+ /*@{*/
+ struct gl_perf_monitor_object * (*NewPerfMonitor)(void);
+ void (*DeletePerfMonitor)(struct gl_perf_monitor_object *m);
Could we get a gl_context for these as well ? It might be useful since
if we want allocate or destroy (more likely) gallium objects we'll need
a context.
NewQueryObject has a context argument as well.
I could save the context from the Begin/End calls, but if there's no
reason not to pass a context to New/Delete, having it as arg would be
preferable.
Regards,
Christoph
Sure thing! I just didn't pass it because I didn't need it. I've
updated the patch to pass gl_context to every driver hook.
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Re: [Mesa-dev] [PATCH] mesa: fix MapBufferRange/MapBuffer typo in create_beginend_table()
On 04/22/2013 12:17 PM, Ferry Huberts wrote: On 22/04/13 19:38, Brian Paul wrote: MapBufferRange was present twice. MapBuffer was missing. Note: This is a candidate for the stable branches. --- src/mesa/main/context.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c index ce76243..0fb57ad 100644 --- a/src/mesa/main/context.c +++ b/src/mesa/main/context.c @@ -922,7 +922,7 @@ create_beginend_table(const struct gl_context *ctx) COPY_DISPATCH(ClientWaitSync); COPY_DISPATCH(MapBuffer); It's already here Yeah, Jose spotted that. Fixed. COPY_DISPATCH(UnmapBuffer); - COPY_DISPATCH(MapBufferRange); + COPY_DISPATCH(MapBuffer); COPY_DISPATCH(MapBufferRange); Maybe 'UnmapBufferRange'? There's no such GL function. -Brian ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH] mesa: fix MapBufferRange/MapBuffer typo in create_beginend_table()
On 22/04/13 21:03, Brian Paul wrote: On 04/22/2013 12:17 PM, Ferry Huberts wrote: On 22/04/13 19:38, Brian Paul wrote: MapBufferRange was present twice. MapBuffer was missing. Note: This is a candidate for the stable branches. --- src/mesa/main/context.c |2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/src/mesa/main/context.c b/src/mesa/main/context.c index ce76243..0fb57ad 100644 --- a/src/mesa/main/context.c +++ b/src/mesa/main/context.c @@ -922,7 +922,7 @@ create_beginend_table(const struct gl_context *ctx) COPY_DISPATCH(ClientWaitSync); COPY_DISPATCH(MapBuffer); It's already here Yeah, Jose spotted that. Fixed. COPY_DISPATCH(UnmapBuffer); - COPY_DISPATCH(MapBufferRange); + COPY_DISPATCH(MapBuffer); COPY_DISPATCH(MapBufferRange); Maybe 'UnmapBufferRange'? There's no such GL function. I'm not limited by any form of knowledge in the GL area ;-) Just guessed the symmetrical thing :-) Following the list out of intense interest, and have to compliment all of you on your work! Much appreciated. -Brian -- Ferry Huberts ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/3] draw: add code to reset instance dependent data
We want to be able to reset certain parts of the pipeline,
in particular the input primitive index, but only either with
seperate invocations of the draw_vbo or new instances. In all
other cases (e.g. new invocations due to primitive restart)
that data needs to be preserved. Add a function through which
we can reset instance dependent data.
Signed-off-by: Zack Rusin za...@vmware.com
---
src/gallium/auxiliary/draw/draw_context.c | 13 +
src/gallium/auxiliary/draw/draw_gs.c | 14 +-
src/gallium/auxiliary/draw/draw_gs.h |2 ++
src/gallium/auxiliary/draw/draw_private.h |1 +
src/gallium/auxiliary/draw/draw_pt.c |2 ++
5 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/src/gallium/auxiliary/draw/draw_context.c
b/src/gallium/auxiliary/draw/draw_context.c
index 5272951..25f79ae 100644
--- a/src/gallium/auxiliary/draw/draw_context.c
+++ b/src/gallium/auxiliary/draw/draw_context.c
@@ -156,6 +156,19 @@ boolean draw_init(struct draw_context *draw)
return TRUE;
}
+/*
+ * Called whenever we're starting to draw a new instance.
+ * Some internal structures don't want to have to reset internal
+ * members on each invocation (because their state might have to persist
+ * between multiple primitive restart rendering call) but might have to
+ * for each new instance.
+ * This is particularly the case for primitive id's in geometry shader.
+ */
+void draw_new_instance(struct draw_context *draw)
+{
+ draw_geometry_shader_new_instance(draw-gs.geometry_shader);
+}
+
void draw_destroy( struct draw_context *draw )
{
diff --git a/src/gallium/auxiliary/draw/draw_gs.c
b/src/gallium/auxiliary/draw/draw_gs.c
index 2f94eae..fbb01b4 100644
--- a/src/gallium/auxiliary/draw/draw_gs.c
+++ b/src/gallium/auxiliary/draw/draw_gs.c
@@ -560,7 +560,6 @@ int draw_geometry_shader_run(struct draw_geometry_shader
*shader,
shader-emitted_primitives = 0;
shader-vertex_size = vertex_size;
shader-tmp_output = (float (*)[4])output_verts-verts-data;
- shader-in_prim_idx = 0;
shader-fetched_prim_count = 0;
shader-input_vertex_stride = input_stride;
shader-input = input;
@@ -869,3 +868,16 @@ void draw_gs_set_current_variant(struct
draw_geometry_shader *shader,
shader-current_variant = variant;
}
#endif
+
+/*
+ * Called at the very begin of the draw call with a new instance
+ * Used to reset state that should persist between primitive restart.
+ */
+void
+draw_geometry_shader_new_instance(struct draw_geometry_shader *gs)
+{
+ if (!gs)
+ return;
+
+ gs-in_prim_idx = 0;
+}
diff --git a/src/gallium/auxiliary/draw/draw_gs.h
b/src/gallium/auxiliary/draw/draw_gs.h
index ca744ce..46d2d61 100644
--- a/src/gallium/auxiliary/draw/draw_gs.h
+++ b/src/gallium/auxiliary/draw/draw_gs.h
@@ -114,6 +114,8 @@ struct draw_geometry_shader {
unsigned input_primitives);
};
+void draw_geometry_shader_new_instance(struct draw_geometry_shader *gs);
+
/*
* Returns the number of vertices emitted.
* The vertex shader can emit any number of vertices as long as it's
diff --git a/src/gallium/auxiliary/draw/draw_private.h
b/src/gallium/auxiliary/draw/draw_private.h
index d6a3e7c..25a8ae6 100644
--- a/src/gallium/auxiliary/draw/draw_private.h
+++ b/src/gallium/auxiliary/draw/draw_private.h
@@ -355,6 +355,7 @@ struct draw_prim_info {
* Draw common initialization code
*/
boolean draw_init(struct draw_context *draw);
+void draw_new_instance(struct draw_context *draw);
/***
* Vertex shader code:
diff --git a/src/gallium/auxiliary/draw/draw_pt.c
b/src/gallium/auxiliary/draw/draw_pt.c
index 10f32fd..602d076 100644
--- a/src/gallium/auxiliary/draw/draw_pt.c
+++ b/src/gallium/auxiliary/draw/draw_pt.c
@@ -561,6 +561,8 @@ draw_vbo(struct draw_context *draw,
for (instance = 0; instance info-instance_count; instance++) {
draw-instance_id = instance + info-start_instance;
+ draw_new_instance(draw);
+
if (info-primitive_restart) {
draw_pt_arrays_restart(draw, info);
}
--
1.7.10.4
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Re: [Mesa-dev] [PATCH 3/3] tgsi/scan: set correct input limits for geometry shader
Am 20.04.2013 09:04, schrieb Zack Rusin:
TGSI geometry shader input declerations are of the IN[][2] format
and the dimensions of the array have to be deduced from the input
primitive property.
Signed-off-by: Zack Rusin za...@vmware.com
---
src/gallium/auxiliary/tgsi/tgsi_scan.c | 17 +
1 file changed, 17 insertions(+)
diff --git a/src/gallium/auxiliary/tgsi/tgsi_scan.c
b/src/gallium/auxiliary/tgsi/tgsi_scan.c
index 373391d..bd79405 100644
--- a/src/gallium/auxiliary/tgsi/tgsi_scan.c
+++ b/src/gallium/auxiliary/tgsi/tgsi_scan.c
@@ -36,6 +36,7 @@
#include util/u_debug.h
#include util/u_math.h
+#include util/u_prim.h
#include tgsi/tgsi_parse.h
#include tgsi/tgsi_util.h
#include tgsi/tgsi_scan.h
@@ -261,6 +262,22 @@ tgsi_scan_shader(const struct tgsi_token *tokens,
case TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS:
info-color0_writes_all_cbufs = info-properties[i].data[0];
break;
+ case TGSI_PROPERTY_GS_INPUT_PRIM:
+ /* The dimensions of the IN decleration in geometry shader have
+ * to be deduced from the type of the input primitive.
+ */
+ if (procType == TGSI_PROCESSOR_GEOMETRY) {
+unsigned input_primitive = info-properties[i].data[0];
+int num_verts = u_vertices_per_prim(input_primitive);
+unsigned j;
+info-file_count[TGSI_FILE_INPUT] = num_verts;
+info-file_max[TGSI_FILE_INPUT] =
+ MAX2(info-file_max[TGSI_FILE_INPUT], num_verts - 1);
+for (j = 0; j num_verts; ++j) {
+ info-file_mask[TGSI_FILE_INPUT] |= (1 j);
+}
+ }
+ break;
default:
;
}
Can you even have that property in in a non-geometry shader?
In any case, series looks good to me, though your patches seem to appear
with some retro-date.
Roland
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Re: [Mesa-dev] [PATCH 3/3] tgsi/scan: set correct input limits for geometry shader
Can you even have that property in in a non-geometry shader? No, not in well formed shaders at least. One could of course force it through graw. I thought about an assert there but I figured that a conditional there won't matter much. In any case, series looks good to me, though your patches seem to appear with some retro-date. Ah, thanks. I think I fixed that vm now. z ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 01/16] mesa: Add infrastructure for ARB_gpu_shader5.
---
src/glsl/builtins/tools/generate_builtins.py |1 +
src/glsl/glcpp/glcpp-parse.y |3 +++
src/glsl/glsl_parser_extras.cpp |1 +
src/glsl/glsl_parser_extras.h|2 ++
src/glsl/standalone_scaffolding.cpp |1 +
src/mesa/main/extensions.c |1 +
src/mesa/main/mtypes.h |1 +
7 files changed, 10 insertions(+), 0 deletions(-)
diff --git a/src/glsl/builtins/tools/generate_builtins.py
b/src/glsl/builtins/tools/generate_builtins.py
index 75d3c21..85bd5dd 100755
--- a/src/glsl/builtins/tools/generate_builtins.py
+++ b/src/glsl/builtins/tools/generate_builtins.py
@@ -192,6 +192,7 @@ read_builtins(GLenum target, const char *protos, const char
**functions, unsigne
st-ARB_shading_language_packing_enable = true;
st-ARB_texture_multisample_enable = true;
st-ARB_texture_query_lod_enable = true;
+ st-ARB_gpu_shader5_enable = true;
_mesa_glsl_initialize_types(st);
sh-ir = new(sh) exec_list;
diff --git a/src/glsl/glcpp/glcpp-parse.y b/src/glsl/glcpp/glcpp-parse.y
index 00edbbf..f0d2ab0 100644
--- a/src/glsl/glcpp/glcpp-parse.y
+++ b/src/glsl/glcpp/glcpp-parse.y
@@ -1236,6 +1236,9 @@ glcpp_parser_create (const struct gl_extensions
*extensions, int api)
if (extensions-ARB_texture_query_lod)
add_builtin_define(parser, GL_ARB_texture_query_lod, 1);
+
+ if (extensions-ARB_gpu_shader5)
+add_builtin_define(parser, GL_ARB_gpu_shader5, 1);
}
}
diff --git a/src/glsl/glsl_parser_extras.cpp b/src/glsl/glsl_parser_extras.cpp
index 0992294..e4636f8 100644
--- a/src/glsl/glsl_parser_extras.cpp
+++ b/src/glsl/glsl_parser_extras.cpp
@@ -468,6 +468,7 @@ static const _mesa_glsl_extension
_mesa_glsl_supported_extensions[] = {
EXT(ARB_shading_language_packing, true, false, true, true, false,
ARB_shading_language_packing),
EXT(ARB_texture_multisample,true, false, true, true, false,
ARB_texture_multisample),
EXT(ARB_texture_query_lod, false, false, true, true, false,
ARB_texture_query_lod),
+ EXT(ARB_gpu_shader5,true, true, true, true, false,
ARB_gpu_shader5),
};
#undef EXT
diff --git a/src/glsl/glsl_parser_extras.h b/src/glsl/glsl_parser_extras.h
index 95891b5..c77dda8 100644
--- a/src/glsl/glsl_parser_extras.h
+++ b/src/glsl/glsl_parser_extras.h
@@ -284,6 +284,8 @@ struct _mesa_glsl_parse_state {
bool ARB_texture_multisample_warn;
bool ARB_texture_query_lod_enable;
bool ARB_texture_query_lod_warn;
+ bool ARB_gpu_shader5_enable;
+ bool ARB_gpu_shader5_warn;
/*@}*/
/** Extensions supported by the OpenGL implementation. */
diff --git a/src/glsl/standalone_scaffolding.cpp
b/src/glsl/standalone_scaffolding.cpp
index 0c1f52f..3c8f70f 100644
--- a/src/glsl/standalone_scaffolding.cpp
+++ b/src/glsl/standalone_scaffolding.cpp
@@ -104,6 +104,7 @@ void initialize_context_to_defaults(struct gl_context *ctx,
gl_api api)
ctx-Extensions.ARB_texture_cube_map_array = true;
ctx-Extensions.ARB_texture_multisample = true;
ctx-Extensions.ARB_texture_query_lod = true;
+ ctx-Extensions.ARB_gpu_shader5 = true;
ctx-Const.GLSLVersion = 120;
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index 64473b9..c56ba15 100644
--- a/src/mesa/main/extensions.c
+++ b/src/mesa/main/extensions.c
@@ -101,6 +101,7 @@ static const struct extension extension_table[] = {
{ GL_ARB_framebuffer_object, o(ARB_framebuffer_object),
GL, 2005 },
{ GL_ARB_framebuffer_sRGB,o(EXT_framebuffer_sRGB),
GL, 1998 },
{ GL_ARB_get_program_binary, o(ARB_shader_objects),
GL, 2010 },
+ { GL_ARB_gpu_shader5, o(ARB_gpu_shader5),
GL, 2010 },
{ GL_ARB_half_float_pixel,o(ARB_half_float_pixel),
GL, 2003 },
{ GL_ARB_half_float_vertex, o(ARB_half_float_vertex),
GL, 2008 },
{ GL_ARB_instanced_arrays,o(ARB_instanced_arrays),
GL, 2008 },
diff --git a/src/mesa/main/mtypes.h b/src/mesa/main/mtypes.h
index 6108a35..ef646ce 100644
--- a/src/mesa/main/mtypes.h
+++ b/src/mesa/main/mtypes.h
@@ -2965,6 +2965,7 @@ struct gl_extensions
GLboolean ARB_framebuffer_object;
GLboolean ARB_explicit_attrib_location;
GLboolean ARB_geometry_shader4;
+ GLboolean ARB_gpu_shader5;
GLboolean ARB_half_float_pixel;
GLboolean ARB_half_float_vertex;
GLboolean ARB_instanced_arrays;
--
1.7.8.6
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[Mesa-dev] [PATCH 03/16] glsl: Add new bit built-ins IR and prototypes from ARB_gpu_shader5.
--- src/glsl/builtins/ir/bitCount.ir| 41 ++ src/glsl/builtins/ir/bitfieldExtract.ir | 57 src/glsl/builtins/ir/bitfieldInsert.ir | 65 +++ src/glsl/builtins/ir/bitfieldReverse.ir | 41 ++ src/glsl/builtins/ir/findLSB.ir | 41 ++ src/glsl/builtins/ir/findMSB.ir | 41 ++ src/glsl/builtins/profiles/ARB_gpu_shader5.glsl | 56 +++ 7 files changed, 342 insertions(+), 0 deletions(-) create mode 100644 src/glsl/builtins/ir/bitCount.ir create mode 100644 src/glsl/builtins/ir/bitfieldExtract.ir create mode 100644 src/glsl/builtins/ir/bitfieldInsert.ir create mode 100644 src/glsl/builtins/ir/bitfieldReverse.ir create mode 100644 src/glsl/builtins/ir/findLSB.ir create mode 100644 src/glsl/builtins/ir/findMSB.ir create mode 100644 src/glsl/builtins/profiles/ARB_gpu_shader5.glsl diff --git a/src/glsl/builtins/ir/bitCount.ir b/src/glsl/builtins/ir/bitCount.ir new file mode 100644 index 000..71fcae2 --- /dev/null +++ b/src/glsl/builtins/ir/bitCount.ir @@ -0,0 +1,41 @@ +((function bitCount + (signature int + (parameters + (declare (in) int value)) + ((return (expression int bit_count (var_ref value) + + (signature ivec2 + (parameters + (declare (in) ivec2 value)) + ((return (expression ivec2 bit_count (var_ref value) + + (signature ivec3 + (parameters + (declare (in) ivec3 value)) + ((return (expression ivec3 bit_count (var_ref value) + + (signature ivec4 + (parameters + (declare (in) ivec4 value)) + ((return (expression ivec4 bit_count (var_ref value) + + (signature int + (parameters + (declare (in) uint value)) + ((return (expression int bit_count (var_ref value) + + (signature ivec2 + (parameters + (declare (in) uvec2 value)) + ((return (expression ivec2 bit_count (var_ref value) + + (signature ivec3 + (parameters + (declare (in) uvec3 value)) + ((return (expression ivec3 bit_count (var_ref value) + + (signature ivec4 + (parameters + (declare (in) uvec4 value)) + ((return (expression ivec4 bit_count (var_ref value) +)) diff --git a/src/glsl/builtins/ir/bitfieldExtract.ir b/src/glsl/builtins/ir/bitfieldExtract.ir new file mode 100644 index 000..0491c82 --- /dev/null +++ b/src/glsl/builtins/ir/bitfieldExtract.ir @@ -0,0 +1,57 @@ +((function bitfieldExtract + (signature int + (parameters + (declare (in) int value) + (declare (in) int offset) + (declare (in) int bits)) + ((return (expression int bitfield_extract (var_ref value) (var_ref offset) (var_ref bits) + + (signature ivec2 + (parameters + (declare (in) ivec2 value) + (declare (in) int offset) + (declare (in) int bits)) + ((return (expression ivec2 bitfield_extract (var_ref value) (var_ref offset) (var_ref bits) + + (signature ivec3 + (parameters + (declare (in) ivec3 value) + (declare (in) int offset) + (declare (in) int bits)) + ((return (expression ivec3 bitfield_extract (var_ref value) (var_ref offset) (var_ref bits) + + (signature ivec4 + (parameters + (declare (in) ivec4 value) + (declare (in) int offset) + (declare (in) int bits)) + ((return (expression ivec4 bitfield_extract (var_ref value) (var_ref offset) (var_ref bits) + + (signature uint + (parameters + (declare (in) uint value) + (declare (in) int offset) + (declare (in) int bits)) + ((return (expression uint bitfield_extract (var_ref value) (var_ref offset) (var_ref bits) + + (signature uvec2 + (parameters + (declare (in) uvec2 value) + (declare (in) int offset) + (declare (in) int bits)) + ((return (expression uvec2 bitfield_extract (var_ref value) (var_ref offset) (var_ref bits) + + (signature uvec3 + (parameters + (declare (in) uvec3 value) + (declare (in) int offset) + (declare (in) int bits)) + ((return (expression uvec3 bitfield_extract (var_ref value) (var_ref offset) (var_ref bits) + + (signature uvec4 + (parameters + (declare (in) uvec4 value) + (declare (in) int offset) + (declare (in) int bits)) + ((return (expression uvec4 bitfield_extract (var_ref value) (var_ref offset) (var_ref bits) +)) diff --git a/src/glsl/builtins/ir/bitfieldInsert.ir b/src/glsl/builtins/ir/bitfieldInsert.ir new file mode 100644 index 000..2bb4442 --- /dev/null +++ b/src/glsl/builtins/ir/bitfieldInsert.ir @@ -0,0 +1,65 @@ +((function bitfieldInsert + (signature int + (parameters + (declare (in) int base) + (declare (in) int insert) + (declare (in) int offset) + (declare (in) int bits)) + ((return (expression int bitfield_insert (var_ref base) (var_ref
[Mesa-dev] [PATCH 04/16] glsl: Add support for new bit built-ins in ARB_gpu_shader5.
---
src/glsl/ir.cpp|8 +++-
src/glsl/ir.h | 21 -
src/glsl/ir_validate.cpp | 26 ++
src/glsl/opt_algebraic.cpp |6 +++---
src/mesa/program/ir_to_mesa.cpp|9 +
src/mesa/state_tracker/st_glsl_to_tgsi.cpp |8
6 files changed, 73 insertions(+), 5 deletions(-)
diff --git a/src/glsl/ir.cpp b/src/glsl/ir.cpp
index 05b77da..2c989c9 100644
--- a/src/glsl/ir.cpp
+++ b/src/glsl/ir.cpp
@@ -419,7 +419,7 @@ ir_expression::get_num_operands(ir_expression_operation op)
if (op = ir_last_triop)
return 3;
- if (op == ir_quadop_vector)
+ if (op = ir_last_quadop)
return 4;
assert(false);
@@ -477,6 +477,10 @@ static const char *const operator_strs[] = {
unpackHalf2x16,
unpackHalf2x16_split_x,
unpackHalf2x16_split_y,
+ bitfield_reverse,
+ bit_count,
+ find_msb,
+ find_lsb,
noise,
+,
-,
@@ -506,6 +510,8 @@ static const char *const operator_strs[] = {
packHalf2x16_split,
ubo_load,
lrp,
+ bitfield_extract,
+ bitfield_insert,
vector,
};
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index 3018e0f..277b815 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -1032,6 +1032,16 @@ enum ir_expression_operation {
ir_unop_unpack_half_2x16_split_y,
/*@}*/
+ /**
+* \name Bit operations, part of ARB_gpu_shader5.
+*/
+ /*@{*/
+ ir_unop_bitfield_reverse,
+ ir_unop_bit_count,
+ ir_unop_find_msb,
+ ir_unop_find_lsb,
+ /*@}*/
+
ir_unop_noise,
/**
@@ -1122,14 +1132,23 @@ enum ir_expression_operation {
ir_triop_lrp,
+ ir_triop_bitfield_extract,
+
/**
* A sentinel marking the last of the ternary operations.
*/
- ir_last_triop = ir_triop_lrp,
+ ir_last_triop = ir_triop_bitfield_extract,
+
+ ir_quadop_bitfield_insert,
ir_quadop_vector,
/**
+* A sentinel marking the last of the ternary operations.
+*/
+ ir_last_quadop = ir_quadop_vector,
+
+ /**
* A sentinel marking the last of all operations.
*/
ir_last_opcode = ir_quadop_vector
diff --git a/src/glsl/ir_validate.cpp b/src/glsl/ir_validate.cpp
index 699c192..4a8df69 100644
--- a/src/glsl/ir_validate.cpp
+++ b/src/glsl/ir_validate.cpp
@@ -361,6 +361,19 @@ ir_validate::visit_leave(ir_expression *ir)
assert(ir-operands[0]-type == glsl_type::uint_type);
break;
+ case ir_unop_bitfield_reverse:
+ assert(ir-operands[0]-type == ir-type);
+ assert(ir-type-is_integer());
+ break;
+
+ case ir_unop_bit_count:
+ case ir_unop_find_msb:
+ case ir_unop_find_lsb:
+ assert(ir-operands[0]-type-vector_elements ==
ir-type-vector_elements);
+ assert(ir-operands[0]-type-is_integer());
+ assert(ir-type-base_type == GLSL_TYPE_INT);
+ break;
+
case ir_unop_noise:
/* XXX what can we assert here? */
break;
@@ -474,6 +487,19 @@ ir_validate::visit_leave(ir_expression *ir)
assert(ir-operands[2]-type == ir-operands[0]-type ||
ir-operands[2]-type == glsl_type::float_type);
break;
+ case ir_triop_bitfield_extract:
+ assert(ir-operands[0]-type == ir-type);
+ assert(ir-operands[1]-type == glsl_type::int_type);
+ assert(ir-operands[2]-type == glsl_type::int_type);
+ break;
+
+ case ir_quadop_bitfield_insert:
+ assert(ir-operands[0]-type == ir-type);
+ assert(ir-operands[1]-type == ir-type);
+ assert(ir-operands[2]-type == glsl_type::int_type);
+ assert(ir-operands[3]-type == glsl_type::int_type);
+ break;
+
case ir_quadop_vector:
/* The vector operator collects some number of scalars and generates a
* vector from them.
diff --git a/src/glsl/opt_algebraic.cpp b/src/glsl/opt_algebraic.cpp
index 70e016d..d706a6a 100644
--- a/src/glsl/opt_algebraic.cpp
+++ b/src/glsl/opt_algebraic.cpp
@@ -186,12 +186,12 @@ ir_algebraic_visitor::swizzle_if_required(ir_expression
*expr,
ir_rvalue *
ir_algebraic_visitor::handle_expression(ir_expression *ir)
{
- ir_constant *op_const[3] = {NULL, NULL, NULL};
- ir_expression *op_expr[3] = {NULL, NULL, NULL};
+ ir_constant *op_const[4] = {NULL, NULL, NULL, NULL};
+ ir_expression *op_expr[4] = {NULL, NULL, NULL, NULL};
ir_expression *temp;
unsigned int i;
- assert(ir-get_num_operands() = 3);
+ assert(ir-get_num_operands() = 4);
for (i = 0; i ir-get_num_operands(); i++) {
if (ir-operands[i]-type-is_matrix())
return ir;
diff --git a/src/mesa/program/ir_to_mesa.cpp b/src/mesa/program/ir_to_mesa.cpp
index 14cf5ba..c6f6bf4 100644
--- a/src/mesa/program/ir_to_mesa.cpp
+++ b/src/mesa/program/ir_to_mesa.cpp
@@ -1444,6 +1444,10 @@ ir_to_mesa_visitor::visit(ir_expression *ir)
case ir_unop_unpack_half_2x16_split_x:
case ir_unop_unpack_half_2x16_split_y:
case ir_binop_pack_half_2x16_split:
+ case ir_unop_bitfield_reverse:
+ case
[Mesa-dev] [PATCH 00/16] Bit built-ins for ARB_gpu_shader5
This series, available at git://people.freedesktop.org/~mattst88/mesa arb_gpu_shader5 adds support for the bit built-ins for ARB_gpu_shader5 to the GLSL compiler and the i965 driver. Interesting parts of the series - - New IR operations for each built-in, plus two operations that match i965 and Radeon hardware. - 3x new lowering passes, for bitfieldInsert to BFM/BFI instructions, bitfieldInsert to BFM/bitops (for i965 VS), and bitfieldExtract to bitops (for i965 VS). - Addition of 3-src destination and shared-source fields and types on i965 to accommodate the BFE and BFI2 instructions. - Don't bother scalarizing the BFI1 (BFM) instruction in the i965 FS, since a single BFM generated from bitfieldInsert() feeds multiple scalarized BFI2 (BFI) instructions. Potential improvements: - Make 3-source instructions work in the i965 VS, and simply use BFE and BFI2 (and remove two of the lowering passes). - Alternatively, optimize the code generated by the lowering passes - Emit 3-src instructions if working on scalar data. - Do a slightly more efficient lowering if the data type is unsigned. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 05/16] glsl: Add constant evaluation of bit built-ins.
---
src/glsl/ir_constant_expression.cpp | 123 +++
1 files changed, 123 insertions(+), 0 deletions(-)
diff --git a/src/glsl/ir_constant_expression.cpp
b/src/glsl/ir_constant_expression.cpp
index c09e56a..119fe59 100644
--- a/src/glsl/ir_constant_expression.cpp
+++ b/src/glsl/ir_constant_expression.cpp
@@ -1248,6 +1248,102 @@ ir_expression::constant_expression_value(struct
hash_table *variable_context)
}
break;
+ case ir_unop_bitfield_reverse:
+ /* http://graphics.stanford.edu/~seander/bithacks.html#BitReverseObvious
*/
+ for (unsigned c = 0; c components; c++) {
+ unsigned int v = op[0]-value.u[c]; // input bits to be reversed
+ unsigned int r = v; // r will be reversed bits of v; first get LSB of
v
+ int s = sizeof(v) * CHAR_BIT - 1; // extra shift needed at end
+
+ for (v = 1; v; v = 1) {
+r = 1;
+r |= v 1;
+s--;
+ }
+ r = s; // shift when v's highest bits are zero
+
+ data.u[c] = r;
+ }
+ break;
+
+ case ir_unop_bit_count:
+ for (unsigned c = 0; c components; c++) {
+ unsigned count = 0;
+ unsigned v = op[0]-value.u[c];
+
+ for (; v; count++) {
+v = v - 1;
+ }
+ data.u[c] = count;
+ }
+ break;
+
+ case ir_unop_find_msb:
+ for (unsigned c = 0; c components; c++) {
+ int v = op[0]-value.i[c];
+
+ if (v == 0 || (op[0]-type-base_type == GLSL_TYPE_INT v == -1))
+data.i[c] = -1;
+ else {
+int count = 0;
+int top_bit = op[0]-type-base_type == GLSL_TYPE_UINT
+ ? 0 : v (1 31);
+
+while (((v (1 31)) == top_bit) count != 32) {
+ count++;
+ v = 1;
+}
+
+data.i[c] = count;
+ }
+ }
+ break;
+
+ case ir_unop_find_lsb:
+ for (unsigned c = 0; c components; c++) {
+ if (op[0]-value.i[c] == 0)
+data.i[c] = -1;
+ else {
+unsigned pos = 0;
+unsigned v = op[0]-value.u[c];
+
+for (; !(v 1); v = 1) {
+ pos++;
+}
+data.u[c] = pos;
+ }
+ }
+ break;
+
+ case ir_triop_bitfield_extract: {
+ int offset = op[1]-value.i[0];
+ int bits = op[2]-value.i[0];
+
+ for (unsigned c = 0; c components; c++) {
+ if (bits == 0)
+data.u[c] = 0;
+ else if (offset 0 || bits 0)
+data.u[c] = 0; /* Undefined, per spec. */
+ else if (offset + bits 32)
+data.u[c] = 0; /* Undefined, per spec. */
+ else {
+if (op[0]-type-base_type == GLSL_TYPE_INT) {
+ /* int so that the right shift will sign-extend. */
+ int value = op[0]-value.i[c];
+ value = 32 - bits - offset;
+ value = 32 - bits;
+ data.i[c] = value;
+} else {
+ unsigned value = op[0]-value.u[c];
+ value = 32 - bits - offset;
+ value = 32 - bits;
+ data.u[c] = value;
+}
+ }
+ }
+ break;
+ }
+
case ir_triop_lrp: {
assert(op[0]-type-base_type == GLSL_TYPE_FLOAT);
assert(op[1]-type-base_type == GLSL_TYPE_FLOAT);
@@ -1261,6 +1357,33 @@ ir_expression::constant_expression_value(struct
hash_table *variable_context)
break;
}
+ case ir_quadop_bitfield_insert: {
+ int offset = op[2]-value.i[0];
+ int bits = op[3]-value.i[0];
+
+ for (unsigned c = 0; c components; c++) {
+ if (bits == 0)
+data.u[c] = op[0]-value.u[c];
+ else if (offset 0 || bits 0)
+data.u[c] = 0; /* Undefined, per spec. */
+ else if (offset + bits 32)
+data.u[c] = 0; /* Undefined, per spec. */
+ else {
+unsigned insert_mask = ((1 bits) - 1) offset;
+
+unsigned insert = op[1]-value.u[c];
+insert = offset;
+insert = insert_mask;
+
+unsigned base = op[0]-value.u[c];
+base = ~insert_mask;
+
+data.u[c] = base | insert;
+ }
+ }
+ break;
+ }
+
case ir_quadop_vector:
for (unsigned c = 0; c this-type-vector_elements; c++) {
switch (this-type-base_type) {
--
1.7.8.6
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 06/16] glsl: Add a pass to lower bitfield-insert into bfm+bfi.
i965/Gen7+ and Radeon/Evergreen+ have bfm/bfi instructions to implement
bitfieldInsert() from ARB_gpu_shader5.
---
src/glsl/ir.cpp |2 +
src/glsl/ir.h | 18
src/glsl/ir_optimization.h |1 +
src/glsl/ir_validate.cpp| 12 +++
src/glsl/lower_instructions.cpp | 42 +++
src/mesa/program/ir_to_mesa.cpp |2 +
6 files changed, 77 insertions(+), 0 deletions(-)
diff --git a/src/glsl/ir.cpp b/src/glsl/ir.cpp
index 2c989c9..2c54525 100644
--- a/src/glsl/ir.cpp
+++ b/src/glsl/ir.cpp
@@ -508,8 +508,10 @@ static const char *const operator_strs[] = {
max,
pow,
packHalf2x16_split,
+ bfm,
ubo_load,
lrp,
+ bfi,
bitfield_extract,
bitfield_insert,
vector,
diff --git a/src/glsl/ir.h b/src/glsl/ir.h
index 277b815..f23dc19 100644
--- a/src/glsl/ir.h
+++ b/src/glsl/ir.h
@@ -1118,6 +1118,15 @@ enum ir_expression_operation {
/*@}*/
/**
+* \name First half of a lowered bitfieldInsert() operation.
+*
+* \see lower_instructions::bitfield_insert_to_bfm_bfi
+*/
+ /*@{*/
+ ir_binop_bfm,
+ /*@}*/
+
+ /**
* Load a value the size of a given GLSL type from a uniform block.
*
* operand0 is the ir_constant uniform block index in the linked shader.
@@ -1132,6 +1141,15 @@ enum ir_expression_operation {
ir_triop_lrp,
+ /**
+* \name Second half of a lowered bitfieldInsert() operation.
+*
+* \see lower_instructions::bitfield_insert_to_bfm_bfi
+*/
+ /*@{*/
+ ir_triop_bfi,
+ /*@}*/
+
ir_triop_bitfield_extract,
/**
diff --git a/src/glsl/ir_optimization.h b/src/glsl/ir_optimization.h
index a8885d7..49b1475 100644
--- a/src/glsl/ir_optimization.h
+++ b/src/glsl/ir_optimization.h
@@ -37,6 +37,7 @@
#define MOD_TO_FRACT 0x20
#define INT_DIV_TO_MUL_RCP 0x40
#define LRP_TO_ARITH 0x80
+#define BITFIELD_INSERT_TO_BFM_BFI 0x100
/**
* \see class lower_packing_builtins_visitor
diff --git a/src/glsl/ir_validate.cpp b/src/glsl/ir_validate.cpp
index 4a8df69..26f09c7 100644
--- a/src/glsl/ir_validate.cpp
+++ b/src/glsl/ir_validate.cpp
@@ -474,6 +474,12 @@ ir_validate::visit_leave(ir_expression *ir)
assert(ir-operands[1]-type == glsl_type::float_type);
break;
+ case ir_binop_bfm:
+ assert(ir-type-is_integer());
+ assert(ir-operands[0]-type-is_integer());
+ assert(ir-operands[1]-type-is_integer());
+ break;
+
case ir_binop_ubo_load:
assert(ir-operands[0]-as_constant());
assert(ir-operands[0]-type == glsl_type::uint_type);
@@ -487,6 +493,12 @@ ir_validate::visit_leave(ir_expression *ir)
assert(ir-operands[2]-type == ir-operands[0]-type ||
ir-operands[2]-type == glsl_type::float_type);
break;
+ case ir_triop_bfi:
+ assert(ir-operands[0]-type-is_integer());
+ assert(ir-operands[1]-type == ir-operands[2]-type);
+ assert(ir-operands[1]-type == ir-type);
+ break;
+
case ir_triop_bitfield_extract:
assert(ir-operands[0]-type == ir-type);
assert(ir-operands[1]-type == glsl_type::int_type);
diff --git a/src/glsl/lower_instructions.cpp b/src/glsl/lower_instructions.cpp
index 1ce7b7c..ff9715d 100644
--- a/src/glsl/lower_instructions.cpp
+++ b/src/glsl/lower_instructions.cpp
@@ -38,6 +38,7 @@
* - LOG_TO_LOG2
* - MOD_TO_FRACT
* - LRP_TO_ARITH
+ * - BITFIELD_INSERT_TO_BFM_BFI
*
* SUB_TO_ADD_NEG:
* ---
@@ -84,6 +85,15 @@
* LRP_TO_ARITH:
* -
* Converts ir_triop_lrp to (op0 * (1.0f - op2)) + (op1 * op2).
+ *
+ * BITFIELD_INSERT_TO_BFM_BFI:
+ * ---
+ * Breaks ir_quadop_bitfield_insert into ir_binop_bfm (bitfield mask) and
+ * ir_triop_bfi (bitfield insert).
+ *
+ * Many GPUs implement the bitfieldInsert() built-in from ARB_gpu_shader_5
+ * with a pair of instructions.
+ *
*/
#include main/core.h /* for M_LOG2E */
@@ -114,6 +124,7 @@ private:
void pow_to_exp2(ir_expression *);
void log_to_log2(ir_expression *);
void lrp_to_arith(ir_expression *);
+ void bitfield_insert_to_bfm_bfi(ir_expression *);
};
/**
@@ -298,6 +309,32 @@ lower_instructions_visitor::lrp_to_arith(ir_expression *ir)
this-progress = true;
}
+void
+lower_instructions_visitor::bitfield_insert_to_bfm_bfi(ir_expression *ir)
+{
+ /* Translates
+*ir_quadop_bitfield_insert base insert offset bits
+* into
+*ir_triop_bfi (ir_binop_bfm bits offset) insert base
+*/
+
+ /* Save op0 */
+ ir_variable *temp = new(ir) ir_variable(ir-operands[0]-type, bfi_base,
+ ir_var_temporary);
+ this-base_ir-insert_before(temp);
+ this-base_ir-insert_before(assign(temp, ir-operands[0]));
+
+ ir-operation = ir_triop_bfi;
+ ir-operands[0] = new(ir) ir_expression(ir_binop_bfm, ir-type,
+ swizzle_(ir-operands[3]),
+
[Mesa-dev] [PATCH 07/16] glsl: Add bitfieldInsert-to-bfm/bitops lowering pass.
---
src/glsl/ir_optimization.h |1 +
src/glsl/lower_instructions.cpp | 61 +++
2 files changed, 62 insertions(+), 0 deletions(-)
diff --git a/src/glsl/ir_optimization.h b/src/glsl/ir_optimization.h
index 49b1475..445dc49 100644
--- a/src/glsl/ir_optimization.h
+++ b/src/glsl/ir_optimization.h
@@ -38,6 +38,7 @@
#define INT_DIV_TO_MUL_RCP 0x40
#define LRP_TO_ARITH 0x80
#define BITFIELD_INSERT_TO_BFM_BFI 0x100
+#define BITFIELD_INSERT_TO_BFM_BITOPS 0x200
/**
* \see class lower_packing_builtins_visitor
diff --git a/src/glsl/lower_instructions.cpp b/src/glsl/lower_instructions.cpp
index ff9715d..1c1cad8 100644
--- a/src/glsl/lower_instructions.cpp
+++ b/src/glsl/lower_instructions.cpp
@@ -39,6 +39,7 @@
* - MOD_TO_FRACT
* - LRP_TO_ARITH
* - BITFIELD_INSERT_TO_BFM_BFI
+ * - BITFIELD_INSERT_TO_BFM_BITOPS
*
* SUB_TO_ADD_NEG:
* ---
@@ -91,9 +92,20 @@
* Breaks ir_quadop_bitfield_insert into ir_binop_bfm (bitfield mask) and
* ir_triop_bfi (bitfield insert).
*
+ * Mutually exclusive with BITFIELD_INSERT_TO_BFM_BITOPS.
+ *
* Many GPUs implement the bitfieldInsert() built-in from ARB_gpu_shader_5
* with a pair of instructions.
*
+ * BITFIELD_INSERT_TO_BFM_BITOPS:
+ * --
+ * Breaks ir_quadop_bitfield_insert into ir_binop_bfm (bitfield mask) and
+ * bit operations simulating ir_triop_bfi (bitfield insert).
+ *
+ * Mutually exclusive with BITFIELD_INSERT_TO_BFM_BITOPS.
+ *
+ * It's difficult to use vector three-source instructions in i965's vertex
+ * shader, so don't emit ir_triop_bfi, but rather bit operations.
*/
#include main/core.h /* for M_LOG2E */
@@ -125,6 +137,7 @@ private:
void log_to_log2(ir_expression *);
void lrp_to_arith(ir_expression *);
void bitfield_insert_to_bfm_bfi(ir_expression *);
+ void bitfield_insert_to_bfm_bitops(ir_expression *ir);
};
/**
@@ -335,6 +348,52 @@
lower_instructions_visitor::bitfield_insert_to_bfm_bfi(ir_expression *ir)
this-progress = true;
}
+void lower_instructions_visitor::bitfield_insert_to_bfm_bitops(ir_expression
*ir)
+{
+ /* Translates
+*ir_quadop_bitfield_insert base insert offset bits
+* into
+*(or (and base (not insert_mask))
+*(and ( insert offset) insert_mask))
+* where insert_mask is
+*(bfm bits offset)
+*/
+ ir_variable *base = new(ir) ir_variable(ir-operands[0]-type, bfi_base,
+ ir_var_temporary);
+ this-base_ir-insert_before(base);
+ this-base_ir-insert_before(assign(base, ir-operands[0]));
+
+ ir_variable *insert = new(ir) ir_variable(ir-operands[1]-type,
bfi_insert,
+ ir_var_temporary);
+ this-base_ir-insert_before(insert);
+ this-base_ir-insert_before(assign(insert, ir-operands[1]));
+
+ ir_variable *offset = new(ir) ir_variable(ir-operands[2]-type,
bfi_offset,
+ ir_var_temporary);
+ this-base_ir-insert_before(offset);
+ this-base_ir-insert_before(assign(offset, ir-operands[2]));
+
+ ir_variable *bits = new(ir) ir_variable(ir-operands[3]-type, bfi_bits,
+ ir_var_temporary);
+ this-base_ir-insert_before(bits);
+ this-base_ir-insert_before(assign(bits, ir-operands[3]));
+
+ ir_variable *insert_mask = new(ir) ir_variable(glsl_type::int_type,
+ insert_mask,
+ ir_var_temporary);
+ this-base_ir-insert_before(insert_mask);
+ this-base_ir-insert_before(assign(insert_mask,
+ new(ir) ir_expression(ir_binop_bfm,
ir-type,
+
swizzle_(bits),
+
swizzle_(offset;
+
+ ir-operation = ir_binop_bit_or;
+ ir-operands[0] = bit_and(base, bit_not(insert_mask));
+ ir-operands[1] = bit_and(lshift(insert, offset), insert_mask);
+ ir-operands[2] = NULL;
+ ir-operands[3] = NULL;
+}
+
ir_visitor_status
lower_instructions_visitor::visit_leave(ir_expression *ir)
{
@@ -379,6 +438,8 @@ lower_instructions_visitor::visit_leave(ir_expression *ir)
case ir_quadop_bitfield_insert:
if (lowering(BITFIELD_INSERT_TO_BFM_BFI))
bitfield_insert_to_bfm_bfi(ir);
+ else if (lowering(BITFIELD_INSERT_TO_BFM_BITOPS))
+ bitfield_insert_to_bfm_bitops(ir);
break;
default:
--
1.7.8.6
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 08/16] glsl: Add BFE-to-bitops lowering pass.
---
src/glsl/ir_optimization.h |1 +
src/glsl/lower_instructions.cpp | 82 +++
2 files changed, 83 insertions(+), 0 deletions(-)
diff --git a/src/glsl/ir_optimization.h b/src/glsl/ir_optimization.h
index 445dc49..c5405e5 100644
--- a/src/glsl/ir_optimization.h
+++ b/src/glsl/ir_optimization.h
@@ -39,6 +39,7 @@
#define LRP_TO_ARITH 0x80
#define BITFIELD_INSERT_TO_BFM_BFI 0x100
#define BITFIELD_INSERT_TO_BFM_BITOPS 0x200
+#define BFE_TO_BITOPS 0x400
/**
* \see class lower_packing_builtins_visitor
diff --git a/src/glsl/lower_instructions.cpp b/src/glsl/lower_instructions.cpp
index 1c1cad8..d49c419 100644
--- a/src/glsl/lower_instructions.cpp
+++ b/src/glsl/lower_instructions.cpp
@@ -40,6 +40,7 @@
* - LRP_TO_ARITH
* - BITFIELD_INSERT_TO_BFM_BFI
* - BITFIELD_INSERT_TO_BFM_BITOPS
+ * - BFE_TO_BITOPS
*
* SUB_TO_ADD_NEG:
* ---
@@ -106,6 +107,10 @@
*
* It's difficult to use vector three-source instructions in i965's vertex
* shader, so don't emit ir_triop_bfi, but rather bit operations.
+ *
+ * BFE_TO_BITOPS:
+ * --
+ * Breaks ir_triop_bitfield_extract into bit operations (and, or, shift).
*/
#include main/core.h /* for M_LOG2E */
@@ -138,6 +143,7 @@ private:
void lrp_to_arith(ir_expression *);
void bitfield_insert_to_bfm_bfi(ir_expression *);
void bitfield_insert_to_bfm_bitops(ir_expression *ir);
+ void bfe_to_bitops(ir_expression *);
};
/**
@@ -394,6 +400,77 @@ void
lower_instructions_visitor::bitfield_insert_to_bfm_bitops(ir_expression *ir
ir-operands[3] = NULL;
}
+void
+lower_instructions_visitor::bfe_to_bitops(ir_expression *ir)
+{
+ /* Translates
+*(bfe value offset bits)
+* into
+*(asr (shl value (- (- 32 bits) offset)) (- 32 bits))
+*
+* which more simply is
+*value = 32 - bits - offset;
+*value = 32 - bits; // = is ASR.
+*
+* but some hardware (like i965) can only shift by 0-31, so the corner case
+* of bits == 0 leads to shifting by 0 instead of 32. Instead, do
+*if (bits == 0)
+* result = 0;
+*else {
+* value = 32 - bits - offset;
+* value = 32 - bits; // = is ASR.
+* result = value;
+*}
+*/
+
+ /* TODO:
+*- Allow hardware that can shift by 32 to avoid the branch.
+*- Allow skipping the lowering pass if type of value is scalar.
+*- Emit (value offset) (1 bits) - 1) for unsigned values.
+*/
+
+ ir_variable *value = new(ir) ir_variable(ir-operands[0]-type, bfe_value,
+ir_var_temporary);
+ this-base_ir-insert_before(value);
+ this-base_ir-insert_before(assign(value, ir-operands[0]));
+
+ ir_variable *offset = new(ir) ir_variable(ir-operands[1]-type,
bfe_offset,
+ ir_var_temporary);
+ this-base_ir-insert_before(offset);
+ this-base_ir-insert_before(assign(offset, ir-operands[1]));
+
+ ir_variable *bits = new(ir) ir_variable(ir-operands[2]-type, bfe_bits,
+ ir_var_temporary);
+ this-base_ir-insert_before(bits);
+ this-base_ir-insert_before(assign(bits, ir-operands[2]));
+
+ ir_constant *immed_32 = new(ir) ir_constant(32);
+ ir_variable *width_minus_bits = new(ir) ir_variable(glsl_type::int_type,
+ width_minus_bits,
+ ir_var_temporary);
+ this-base_ir-insert_before(width_minus_bits);
+ this-base_ir-insert_before(assign(width_minus_bits, sub(immed_32, bits)));
+
+ ir_variable *result = new(ir) ir_variable(ir-type, bfe_result,
+ ir_var_temporary);
+ this-base_ir-insert_before(result);
+
+ ir_if *bits_zero_if = if_tree(equal(bits, new(ir) ir_constant(0)),
+ assign(result, new(ir) ir_constant(0)),
+ assign(result,
+rshift(lshift(value,
swizzle_(sub(width_minus_bits, offset))),
+
swizzle_(width_minus_bits;
+ this-base_ir-insert_before(bits_zero_if);
+
+ /* XXX: Seems like there should be a better way of doing this. */
+ ir-operation = ir_binop_add;
+ ir-operands[0] = new(ir) ir_dereference_variable(result);
+ ir-operands[1] = new(ir) ir_constant(0);
+ ir-operands[2] = NULL;
+
+ this-progress = true;
+}
+
ir_visitor_status
lower_instructions_visitor::visit_leave(ir_expression *ir)
{
@@ -442,6 +519,11 @@ lower_instructions_visitor::visit_leave(ir_expression *ir)
bitfield_insert_to_bfm_bitops(ir);
break;
+ case ir_triop_bitfield_extract:
+ if (lowering(BFE_TO_BITOPS))
+ bfe_to_bitops(ir);
+ break;
+
default:
return visit_continue;
}
--
1.7.8.6
[Mesa-dev] [PATCH 09/16] i965: Add Gen7+ fields to brw_instruction and add comments.
---
src/mesa/drivers/dri/i965/brw_structs.h | 31 +++
1 files changed, 19 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_structs.h
b/src/mesa/drivers/dri/i965/brw_structs.h
index 75365e0..c322edf 100644
--- a/src/mesa/drivers/dri/i965/brw_structs.h
+++ b/src/mesa/drivers/dri/i965/brw_structs.h
@@ -824,7 +824,7 @@ struct brw_instruction
GLuint access_mode:1;
GLuint mask_control:1;
GLuint dependency_control:2;
- GLuint compression_control:2; /* gen6: quater control */
+ GLuint compression_control:2; /* gen6: quarter control */
GLuint thread_control:2;
GLuint predicate_control:4;
GLuint predicate_inverse:1;
@@ -849,7 +849,7 @@ struct brw_instruction
GLuint src0_reg_type:3;
GLuint src1_reg_file:2;
GLuint src1_reg_type:3;
-GLuint pad:1;
+ GLuint nibctrl:1; /* gen7+ */
GLuint dest_subreg_nr:5;
GLuint dest_reg_nr:8;
GLuint dest_horiz_stride:2;
@@ -864,7 +864,7 @@ struct brw_instruction
GLuint src0_reg_type:3;
GLuint src1_reg_file:2;/* 0x0c00 */
GLuint src1_reg_type:3;/* 0x7000 */
-GLuint pad:1;
+ GLuint nibctrl:1; /* gen7+ */
GLint dest_indirect_offset:10; /* offset against the deref'd address
reg */
GLuint dest_subreg_nr:3; /* subnr for the address reg a0.x */
GLuint dest_horiz_stride:2;
@@ -879,7 +879,7 @@ struct brw_instruction
GLuint src0_reg_type:3;
GLuint src1_reg_file:2;
GLuint src1_reg_type:3;
-GLuint pad:1;
+ GLuint nibctrl:1; /* gen7+ */
GLuint dest_writemask:4;
GLuint dest_subreg_nr:1;
GLuint dest_reg_nr:8;
@@ -893,7 +893,9 @@ struct brw_instruction
GLuint dest_reg_type:3;
GLuint src0_reg_file:2;
GLuint src0_reg_type:3;
-GLuint pad0:6;
+ GLuint src1_reg_file:2;
+ GLuint src1_reg_type:3;
+ GLuint nibctrl:1; /* gen7+ */
GLuint dest_writemask:4;
GLint dest_indirect_offset:6;
GLuint dest_subreg_nr:3;
@@ -914,16 +916,21 @@ struct brw_instruction
} branch_gen6;
struct {
-GLuint dest_reg_file:1;
+ GLuint dest_reg_file:1; /* gen6, not gen7+ */
GLuint flag_subreg_num:1;
-GLuint pad0:2;
+ GLuint flag_reg_nr:1; /* gen7+ */
+ GLuint pad0:1;
GLuint src0_abs:1;
GLuint src0_negate:1;
GLuint src1_abs:1;
GLuint src1_negate:1;
GLuint src2_abs:1;
GLuint src2_negate:1;
-GLuint pad1:7;
+ GLuint src_type:2; /* gen7+ */
+ GLuint dst_type:2; /* gen7+ */
+ GLuint pad1:1;
+ GLuint nibctrl:1; /* gen7+ */
+ GLuint pad2:1;
GLuint dest_writemask:4;
GLuint dest_subreg_nr:3;
GLuint dest_reg_nr:8;
@@ -945,7 +952,7 @@ struct brw_instruction
GLuint src0_width:3;
GLuint src0_vert_stride:4;
GLuint flag_subreg_nr:1;
-GLuint flag_reg_nr:1;
+ GLuint flag_reg_nr:1; /* gen7+ */
GLuint pad:5;
} da1;
@@ -960,7 +967,7 @@ struct brw_instruction
GLuint src0_width:3;
GLuint src0_vert_stride:4;
GLuint flag_subreg_nr:1;
-GLuint flag_reg_nr:1;
+ GLuint flag_reg_nr:1; /* gen7+ */
GLuint pad:5;
} ia1;
@@ -978,7 +985,7 @@ struct brw_instruction
GLuint pad0:1;
GLuint src0_vert_stride:4;
GLuint flag_subreg_nr:1;
-GLuint flag_reg_nr:1;
+ GLuint flag_reg_nr:1; /* gen7+ */
GLuint pad1:5;
} da16;
@@ -996,7 +1003,7 @@ struct brw_instruction
GLuint pad0:1;
GLuint src0_vert_stride:4;
GLuint flag_subreg_nr:1;
-GLuint flag_reg_nr:1;
+ GLuint flag_reg_nr:1; /* gen7+ */
GLuint pad1:5;
} ia16;
--
1.7.8.6
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[Mesa-dev] [PATCH 10/16] i965: Add 3-src destination and shared-source type macros.
---
src/mesa/drivers/dri/i965/brw_defines.h | 11 +++
1 files changed, 11 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index 38f0356..a5d9452 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -777,6 +777,17 @@ enum opcode {
#define BRW_REGISTER_TYPE_V 6/* packed int vector, immediates only,
uword dest only */
#define BRW_REGISTER_TYPE_F 7
+/* SNB adds 3-src instructions (MAD and LRP) that only operate on floats, so
+ * the types were implied. IVB adds BFE and BFI2 that operate on doublewords
+ * and unsigned doublewords, so a new field is also available in the da3src
+ * struct (part of struct brw_instruction.bits1 in brw_structs.h) to select
+ * dst and shared-src types. The values are different from BRW_REGISTER_TYPE_*.
+ */
+#define BRW_3SRC_TYPE_F 0
+#define BRW_3SRC_TYPE_D 1
+#define BRW_3SRC_TYPE_UD 2
+#define BRW_3SRC_TYPE_DF 3
+
#define BRW_ARF_NULL 0x00
#define BRW_ARF_ADDRESS 0x10
#define BRW_ARF_ACCUMULATOR 0x20
--
1.7.8.6
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[Mesa-dev] [PATCH 11/16] i965/gen7: Set src/dst types for 3-src instructions.
Also update asserts to allow BFE and BFI2, which take (unsigned)
doubleword arguments.
---
src/mesa/drivers/dri/i965/brw_eu_emit.c | 34 +++---
1 files changed, 30 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index dda562f..f6dd2e2 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -788,6 +788,7 @@ static struct brw_instruction *brw_alu3(struct brw_compile
*p,
struct brw_reg src1,
struct brw_reg src2)
{
+ struct intel_context *intel = p-brw-intel;
struct brw_instruction *insn = next_insn(p, opcode);
gen7_convert_mrf_to_grf(p, dest);
@@ -798,7 +799,9 @@ static struct brw_instruction *brw_alu3(struct brw_compile
*p,
dest.file == BRW_MESSAGE_REGISTER_FILE);
assert(dest.nr 128);
assert(dest.address_mode == BRW_ADDRESS_DIRECT);
- assert(dest.type == BRW_REGISTER_TYPE_F);
+ assert(dest.type == BRW_REGISTER_TYPE_F ||
+ dest.type == BRW_REGISTER_TYPE_D ||
+ dest.type == BRW_REGISTER_TYPE_UD);
insn-bits1.da3src.dest_reg_file = (dest.file == BRW_MESSAGE_REGISTER_FILE);
insn-bits1.da3src.dest_reg_nr = dest.nr;
insn-bits1.da3src.dest_subreg_nr = dest.subnr / 16;
@@ -808,7 +811,9 @@ static struct brw_instruction *brw_alu3(struct brw_compile
*p,
assert(src0.file == BRW_GENERAL_REGISTER_FILE);
assert(src0.address_mode == BRW_ADDRESS_DIRECT);
assert(src0.nr 128);
- assert(src0.type == BRW_REGISTER_TYPE_F);
+ assert(src0.type == BRW_REGISTER_TYPE_F ||
+ src0.type == BRW_REGISTER_TYPE_D ||
+ src0.type == BRW_REGISTER_TYPE_UD);
insn-bits2.da3src.src0_swizzle = src0.dw1.bits.swizzle;
insn-bits2.da3src.src0_subreg_nr = get_3src_subreg_nr(src0);
insn-bits2.da3src.src0_reg_nr = src0.nr;
@@ -819,7 +824,8 @@ static struct brw_instruction *brw_alu3(struct brw_compile
*p,
assert(src1.file == BRW_GENERAL_REGISTER_FILE);
assert(src1.address_mode == BRW_ADDRESS_DIRECT);
assert(src1.nr 128);
- assert(src1.type == BRW_REGISTER_TYPE_F);
+ assert(src1.type == BRW_REGISTER_TYPE_F ||
+ src1.type == BRW_REGISTER_TYPE_D);
insn-bits2.da3src.src1_swizzle = src1.dw1.bits.swizzle;
insn-bits2.da3src.src1_subreg_nr_low = get_3src_subreg_nr(src1) 0x3;
insn-bits3.da3src.src1_subreg_nr_high = get_3src_subreg_nr(src1) 2;
@@ -831,7 +837,8 @@ static struct brw_instruction *brw_alu3(struct brw_compile
*p,
assert(src2.file == BRW_GENERAL_REGISTER_FILE);
assert(src2.address_mode == BRW_ADDRESS_DIRECT);
assert(src2.nr 128);
- assert(src2.type == BRW_REGISTER_TYPE_F);
+ assert(src2.type == BRW_REGISTER_TYPE_F ||
+ src2.type == BRW_REGISTER_TYPE_D);
insn-bits3.da3src.src2_swizzle = src2.dw1.bits.swizzle;
insn-bits3.da3src.src2_subreg_nr = get_3src_subreg_nr(src2);
insn-bits3.da3src.src2_rep_ctrl = src2.vstride == BRW_VERTICAL_STRIDE_0;
@@ -839,6 +846,25 @@ static struct brw_instruction *brw_alu3(struct brw_compile
*p,
insn-bits1.da3src.src2_abs = src2.abs;
insn-bits1.da3src.src2_negate = src2.negate;
+ if (intel-gen = 7) {
+ assert(dest.type == src0.type);
+
+ switch (dest.type) {
+ case BRW_REGISTER_TYPE_F:
+ insn-bits1.da3src.src_type = BRW_3SRC_TYPE_F;
+ insn-bits1.da3src.dst_type = BRW_3SRC_TYPE_F;
+ break;
+ case BRW_REGISTER_TYPE_D:
+ insn-bits1.da3src.src_type = BRW_3SRC_TYPE_D;
+ insn-bits1.da3src.dst_type = BRW_3SRC_TYPE_D;
+ break;
+ case BRW_REGISTER_TYPE_UD:
+ insn-bits1.da3src.src_type = BRW_3SRC_TYPE_UD;
+ insn-bits1.da3src.dst_type = BRW_3SRC_TYPE_UD;
+ break;
+ }
+ }
+
return insn;
}
--
1.7.8.6
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[Mesa-dev] [PATCH 12/16] i965: Add support for emitting and disassembling bit instructions.
Specifically
bfe - for bitfieldExtract()
bfi1 and bfi2 - for bitfieldInsert()
bfrev - for bitfieldReverse()
cbit - for bitCount()
fbh - for findMSB()
fbl - for findLSB()
---
src/mesa/drivers/dri/i965/brw_defines.h |7 +++
src/mesa/drivers/dri/i965/brw_disasm.c |7 +++
src/mesa/drivers/dri/i965/brw_eu.h |7 +++
src/mesa/drivers/dri/i965/brw_eu_emit.c |7 +++
4 files changed, 28 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index a5d9452..62a79d6 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -647,6 +647,10 @@ enum opcode {
BRW_OPCODE_CMPN = 17,
BRW_OPCODE_F32TO16 = 19,
BRW_OPCODE_F16TO32 = 20,
+ BRW_OPCODE_BFREV = 23,
+ BRW_OPCODE_BFE =24,
+ BRW_OPCODE_BFI1 = 25,
+ BRW_OPCODE_BFI2 = 26,
BRW_OPCODE_JMPI = 32,
BRW_OPCODE_IF = 34,
BRW_OPCODE_IFF =35,
@@ -676,6 +680,9 @@ enum opcode {
BRW_OPCODE_MAC =72,
BRW_OPCODE_MACH = 73,
BRW_OPCODE_LZD =74,
+ BRW_OPCODE_FBH =75,
+ BRW_OPCODE_FBL =76,
+ BRW_OPCODE_CBIT = 77,
BRW_OPCODE_SAD2 = 80,
BRW_OPCODE_SADA2 = 81,
BRW_OPCODE_DP4 =84,
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c
b/src/mesa/drivers/dri/i965/brw_disasm.c
index 8736764..0b881b7 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -43,6 +43,10 @@ const struct opcode_desc opcode_descs[128] = {
[BRW_OPCODE_LZD] = { .name = lzd, .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_F32TO16] = { .name = f32to16, .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_F16TO32] = { .name = f16to32, .nsrc = 1, .ndst = 1 },
+[BRW_OPCODE_BFREV] = { .name = bfrev, .nsrc = 1, .ndst = 1},
+[BRW_OPCODE_FBH] = { .name = fbh, .nsrc = 1, .ndst = 1},
+[BRW_OPCODE_FBL] = { .name = fbl, .nsrc = 1, .ndst = 1},
+[BRW_OPCODE_CBIT] = { .name = cbit, .nsrc = 1, .ndst = 1},
[BRW_OPCODE_MUL] = { .name = mul, .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_MAC] = { .name = mac, .nsrc = 2, .ndst = 1 },
@@ -70,6 +74,9 @@ const struct opcode_desc opcode_descs[128] = {
[BRW_OPCODE_ASR] = { .name = asr, .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_CMP] = { .name = cmp, .nsrc = 2, .ndst = 1 },
[BRW_OPCODE_CMPN] = { .name = cmpn, .nsrc = 2, .ndst = 1 },
+[BRW_OPCODE_BFE] = { .name = bfe, .nsrc = 3, .ndst = 1},
+[BRW_OPCODE_BFI1] = { .name = bfe1, .nsrc = 2, .ndst = 1},
+[BRW_OPCODE_BFI2] = { .name = bfe2, .nsrc = 3, .ndst = 1},
[BRW_OPCODE_SEND] = { .name = send, .nsrc = 1, .ndst = 1 },
[BRW_OPCODE_SENDC] = { .name = sendc, .nsrc = 1, .ndst = 1 },
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h
b/src/mesa/drivers/dri/i965/brw_eu.h
index 9683b13..ce8843d 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -176,6 +176,13 @@ ALU2(LINE)
ALU2(PLN)
ALU3(MAD)
ALU3(LRP)
+ALU1(BFREV)
+ALU3(BFE)
+ALU2(BFI1)
+ALU3(BFI2)
+ALU1(FBH)
+ALU1(FBL)
+ALU1(CBIT)
ROUND(RNDZ)
ROUND(RNDE)
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c
b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index f6dd2e2..d2f8fe6 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -951,6 +951,13 @@ ALU2(LINE)
ALU2(PLN)
ALU3(MAD)
ALU3(LRP)
+ALU1(BFREV)
+ALU3(BFE)
+ALU2(BFI1)
+ALU3(BFI2)
+ALU1(FBH)
+ALU1(FBL)
+ALU1(CBIT)
ROUND(RNDZ)
ROUND(RNDE)
--
1.7.8.6
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[Mesa-dev] [PATCH 13/16] i965/fs: Add support for bit instructions.
Don't bother scalarizing ir_binop_bfm, since its results are
identical for all channels.
---
src/mesa/drivers/dri/i965/brw_fs.cpp |7 +++
src/mesa/drivers/dri/i965/brw_fs.h |7 +++
.../dri/i965/brw_fs_channel_expressions.cpp| 37 +++
src/mesa/drivers/dri/i965/brw_fs_emit.cpp | 48
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 29
5 files changed, 128 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 5f659b1..f060a7c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs.cpp
@@ -173,6 +173,13 @@ ALU2(SHL)
ALU2(SHR)
ALU2(ASR)
ALU3(LRP)
+ALU1(BFREV)
+ALU3(BFE)
+ALU2(BFI1)
+ALU3(BFI2)
+ALU1(FBH)
+ALU1(FBL)
+ALU1(CBIT)
/** Gen4 predicated IF. */
fs_inst *
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index 86a9ec5..fe7eddc 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.h
+++ b/src/mesa/drivers/dri/i965/brw_fs.h
@@ -288,6 +288,13 @@ public:
uint32_t condition);
fs_inst *LRP(fs_reg dst, fs_reg a, fs_reg y, fs_reg x);
fs_inst *DEP_RESOLVE_MOV(int grf);
+ fs_inst *BFREV(fs_reg dst, fs_reg value);
+ fs_inst *BFE(fs_reg dst, fs_reg bits, fs_reg offset, fs_reg value);
+ fs_inst *BFI1(fs_reg dst, fs_reg bits, fs_reg offset);
+ fs_inst *BFI2(fs_reg dst, fs_reg bfi1_dst, fs_reg insert, fs_reg base);
+ fs_inst *FBH(fs_reg dst, fs_reg value);
+ fs_inst *FBL(fs_reg dst, fs_reg value);
+ fs_inst *CBIT(fs_reg dst, fs_reg value);
int type_size(const struct glsl_type *type);
fs_inst *get_instruction_generating_reg(fs_inst *start,
diff --git a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
index 30d8d9b..ee362e3 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
@@ -216,6 +216,10 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment
*ir)
case ir_unop_cos_reduced:
case ir_unop_dFdx:
case ir_unop_dFdy:
+ case ir_unop_bitfield_reverse:
+ case ir_unop_bit_count:
+ case ir_unop_find_msb:
+ case ir_unop_find_lsb:
for (i = 0; i vector_elements; i++) {
ir_rvalue *op0 = get_element(op_var[0], i);
@@ -338,11 +342,26 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment
*ir)
assert(!noise should have been broken down to function call);
break;
+ case ir_binop_bfm: {
+ /* Does not need to be scalarized, since its result will be identical
+ * for all channels.
+ */
+ ir_rvalue *op0 = get_element(op_var[0], 0);
+ ir_rvalue *op1 = get_element(op_var[1], 0);
+
+ assign(ir, 0, new(mem_ctx) ir_expression(expr-operation,
+ element_type,
+ op0,
+ op1));
+ break;
+ }
+
case ir_binop_ubo_load:
assert(!not yet supported);
break;
case ir_triop_lrp:
+ case ir_triop_bitfield_extract:
for (i = 0; i vector_elements; i++) {
ir_rvalue *op0 = get_element(op_var[0], i);
ir_rvalue *op1 = get_element(op_var[1], i);
@@ -356,6 +375,23 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment
*ir)
}
break;
+ case ir_triop_bfi: {
+ /* Only a single BFM is needed for multiple BFIs. */
+ ir_rvalue *op0 = get_element(op_var[0], 0);
+
+ for (i = 0; i vector_elements; i++) {
+ ir_rvalue *op1 = get_element(op_var[1], i);
+ ir_rvalue *op2 = get_element(op_var[2], i);
+
+ assign(ir, i, new(mem_ctx) ir_expression(expr-operation,
+ element_type,
+ op0,
+ op1,
+ op2));
+ }
+ break;
+ }
+
case ir_unop_pack_snorm_2x16:
case ir_unop_pack_snorm_4x8:
case ir_unop_pack_unorm_2x16:
@@ -366,6 +402,7 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment
*ir)
case ir_unop_unpack_unorm_2x16:
case ir_unop_unpack_unorm_4x8:
case ir_unop_unpack_half_2x16:
+ case ir_quadop_bitfield_insert:
case ir_quadop_vector:
assert(!should have been lowered);
break;
diff --git a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
index 0f6b715..b7c85ef 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_emit.cpp
@@ -1209,6 +1209,54 @@ fs_generator::generate_code(exec_list *instructions)
case BRW_OPCODE_SEL:
brw_SEL(p, dst, src[0], src[1]);
break;
+ case BRW_OPCODE_BFREV:
+ /* BFREV only supports UD type for src and
[Mesa-dev] [PATCH 14/16] i965/vs: Add support for bit instructions.
---
src/mesa/drivers/dri/i965/brw_vec4.h |7 +++
src/mesa/drivers/dri/i965/brw_vec4_emit.cpp| 29 ++
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 48
3 files changed, 84 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index 697ab86..45c1f7a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++ b/src/mesa/drivers/dri/i965/brw_vec4.h
@@ -386,6 +386,13 @@ public:
vec4_instruction *PULL_CONSTANT_LOAD(dst_reg dst, src_reg index);
vec4_instruction *SCRATCH_READ(dst_reg dst, src_reg index);
vec4_instruction *SCRATCH_WRITE(dst_reg dst, src_reg src, src_reg index);
+ vec4_instruction *BFREV(dst_reg dst, src_reg value);
+ vec4_instruction *BFE(dst_reg dst, src_reg bits, src_reg offset, src_reg
value);
+ vec4_instruction *BFI1(dst_reg dst, src_reg bits, src_reg offset);
+ vec4_instruction *BFI2(dst_reg dst, src_reg bfi1_dst, src_reg insert,
src_reg base);
+ vec4_instruction *FBH(dst_reg dst, src_reg value);
+ vec4_instruction *FBL(dst_reg dst, src_reg value);
+ vec4_instruction *CBIT(dst_reg dst, src_reg value);
int implied_mrf_writes(vec4_instruction *inst);
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
index c9963bf..6916bd8 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_emit.cpp
@@ -838,6 +838,35 @@ vec4_generator::generate_code(exec_list *instructions)
brw_F16TO32(p, dst, src[0]);
break;
+ case BRW_OPCODE_BFREV:
+ /* BFREV only supports UD type for src and dst. */
+ brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
+ retype(src[0], BRW_REGISTER_TYPE_UD));
+ break;
+ case BRW_OPCODE_FBH:
+ /* FBH only supports UD type for dst. */
+ brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
+ break;
+ case BRW_OPCODE_FBL:
+ /* FBL only supports UD type for dst. */
+ brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
+ break;
+ case BRW_OPCODE_CBIT:
+ /* CBIT only supports UD type for dst. */
+ brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
+ break;
+
+ case BRW_OPCODE_BFE:
+ brw_BFE(p, dst, src[0], src[1], src[2]);
+ break;
+
+ case BRW_OPCODE_BFI1:
+ brw_BFI1(p, dst, src[0], src[1]);
+ break;
+ case BRW_OPCODE_BFI2:
+ brw_BFI2(p, dst, src[0], src[1], src[2]);
+ break;
+
case BRW_OPCODE_IF:
if (inst-src[0].file != BAD_FILE) {
/* The instruction has an embedded compare (only allowed on gen6) */
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
index 2fb8482..d46c3f7 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
@@ -107,6 +107,14 @@ vec4_visitor::emit(enum opcode opcode)
src0, src1); \
}
+#define ALU3(op) \
+ vec4_instruction * \
+ vec4_visitor::op(dst_reg dst, src_reg src0, src_reg src1, src_reg src2)\
+ { \
+ return new(mem_ctx) vec4_instruction(this, BRW_OPCODE_##op, dst, \
+ src0, src1, src2); \
+ }
+
ALU1(NOT)
ALU1(MOV)
ALU1(FRC)
@@ -127,6 +135,13 @@ ALU2(DPH)
ALU2(SHL)
ALU2(SHR)
ALU2(ASR)
+ALU1(BFREV)
+ALU3(BFE)
+ALU2(BFI1)
+ALU3(BFI2)
+ALU1(FBH)
+ALU1(FBL)
+ALU1(CBIT)
/** Gen4 predicated IF. */
vec4_instruction *
@@ -1350,6 +1365,19 @@ vec4_visitor::visit(ir_expression *ir)
assert(!derivatives not valid in vertex shader);
break;
+ case ir_unop_bitfield_reverse:
+ emit(BFREV(result_dst, op[0]));
+ break;
+ case ir_unop_bit_count:
+ emit(CBIT(result_dst, op[0]));
+ break;
+ case ir_unop_find_msb:
+ emit(FBH(result_dst, op[0]));
+ break;
+ case ir_unop_find_lsb:
+ emit(FBL(result_dst, op[0]));
+ break;
+
case ir_unop_noise:
assert(!not reached: should be handled by lower_noise);
break;
@@ -1550,6 +1578,10 @@ vec4_visitor::visit(ir_expression *ir)
inst = emit(SHR(result_dst, op[0], op[1]));
break;
+ case ir_binop_bfm:
+ emit(BFI1(result_dst, op[0], op[1]));
+ break;
+
case ir_binop_ubo_load: {
ir_constant *uniform_block = ir-operands[0]-as_constant();
ir_constant *const_offset_ir = ir-operands[1]-as_constant();
@@ -1599,6 +1631,22 @@ vec4_visitor::visit(ir_expression *ir)
assert(!not reached: should be handled by lrp_to_arith);
break;
+ case ir_triop_bfi:
+ emit(BFI2(result_dst, op[0], op[1], op[2]));
+
[Mesa-dev] [PATCH 15/16] i965: Lower bitfieldExtract and bitfieldInsert.
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 14 ++
1 files changed, 14 insertions(+), 0 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index b3bd1b9..15a0440 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -151,6 +151,20 @@ brw_link_shader(struct gl_context *ctx, struct
gl_shader_program *shProg)
* must precede lower_instructions().
*/
brw_lower_packing_builtins(brw, (gl_shader_type) stage, shader-ir);
+
+ /* bitfield lowering passes insert subtraction instructions which need
+ * to be lowered, so it must precede lower_instructions(SUB_TO_ADD_NEG).
+ */
+ int bfe_to_bitops = 0, bitfield_insert = 0;
+ if (intel-gen = 7) {
+ bfe_to_bitops = stage != MESA_SHADER_FRAGMENT
+ ? BFE_TO_BITOPS : 0;
+ bitfield_insert = stage != MESA_SHADER_FRAGMENT
+ ? BITFIELD_INSERT_TO_BFM_BITOPS
+ : BITFIELD_INSERT_TO_BFM_BFI;
+ }
+ lower_instructions(shader-ir, bfe_to_bitops | bitfield_insert);
+
do_mat_op_to_vec(shader-ir);
const int lrp_to_arith = (intel-gen 6 || stage !=
MESA_SHADER_FRAGMENT)
? LRP_TO_ARITH : 0;
--
1.7.8.6
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[Mesa-dev] [PATCH 16/16] i965: Print the correct dst and shared-src types for 3-src instructions.
---
src/mesa/drivers/dri/i965/brw_disasm.c | 26 ++
1 files changed, 22 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c
b/src/mesa/drivers/dri/i965/brw_disasm.c
index 0b881b7..556e63a 100644
--- a/src/mesa/drivers/dri/i965/brw_disasm.c
+++ b/src/mesa/drivers/dri/i965/brw_disasm.c
@@ -468,6 +468,19 @@ static int print_opcode (FILE *file, int id)
return 0;
}
+static int three_source_type_to_reg_type(int three_source_type)
+{
+ switch (three_source_type) {
+ case BRW_3SRC_TYPE_F:
+ return BRW_REGISTER_TYPE_F;
+ case BRW_3SRC_TYPE_D:
+ return BRW_REGISTER_TYPE_D;
+ case BRW_3SRC_TYPE_UD:
+ return BRW_REGISTER_TYPE_UD;
+ }
+ return -1;
+}
+
static int reg (FILE *file, GLuint _reg_file, GLuint _reg_nr)
{
interr = 0;
@@ -594,7 +607,9 @@ static int dest_3src (FILE *file, struct brw_instruction
*inst)
format (file, .%d, inst-bits1.da3src.dest_subreg_nr);
string (file, 1);
err |= control (file, writemask, writemask,
inst-bits1.da3src.dest_writemask, NULL);
-err |= control (file, dest reg encoding, reg_encoding,
BRW_REGISTER_TYPE_F, NULL);
+err |= control (file, dest reg encoding, reg_encoding,
+three_source_type_to_reg_type(inst-bits1.da3src.dst_type),
+NULL);
return 0;
}
@@ -733,7 +748,8 @@ static int src0_3src (FILE *file, struct brw_instruction
*inst)
format (file, .%d, inst-bits2.da3src.src0_subreg_nr);
string (file, 4,1,1);
err |= control (file, src da16 reg type, reg_encoding,
- BRW_REGISTER_TYPE_F, NULL);
+three_source_type_to_reg_type(inst-bits1.da3src.src_type),
+NULL);
/*
* Three kinds of swizzle display:
* identity - nothing printed
@@ -785,7 +801,8 @@ static int src1_3src (FILE *file, struct brw_instruction
*inst)
format (file, .%d, src1_subreg_nr);
string (file, 4,1,1);
err |= control (file, src da16 reg type, reg_encoding,
- BRW_REGISTER_TYPE_F, NULL);
+three_source_type_to_reg_type(inst-bits1.da3src.src_type),
+NULL);
/*
* Three kinds of swizzle display:
* identity - nothing printed
@@ -836,7 +853,8 @@ static int src2_3src (FILE *file, struct brw_instruction
*inst)
format (file, .%d, inst-bits3.da3src.src2_subreg_nr);
string (file, 4,1,1);
err |= control (file, src da16 reg type, reg_encoding,
- BRW_REGISTER_TYPE_F, NULL);
+three_source_type_to_reg_type(inst-bits1.da3src.src_type),
+NULL);
/*
* Three kinds of swizzle display:
* identity - nothing printed
--
1.7.8.6
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[Mesa-dev] [PATCH] mesa: Allow custom text to be inserted in version string at buildtime
This allows maintainers/packagers/testers to tag the build with
information that will be reported by GL_VERSION.
If the environemt variable or make variable MESA_VERSION_STRING_EXTRA is
set, then its values will appear in the GL_VERSION string immediately
after Mesa X.Y and before (git-xxx).
This patch implements supports MESA_VERSION_STRING_EXTRA only for Android.
Other build systems are left as an excercise.
CC: Matt Turner matts...@gmail.com
CC: Tapani Pälli tapani.pa...@intel.com
Signed-off-by: Chad Versace chad.vers...@linux.intel.com
---
src/mesa/Android.libmesa_dricore.mk | 4
src/mesa/main/version.c | 3 +++
2 files changed, 7 insertions(+)
diff --git a/src/mesa/Android.libmesa_dricore.mk
b/src/mesa/Android.libmesa_dricore.mk
index 00c0694..20706a1 100644
--- a/src/mesa/Android.libmesa_dricore.mk
+++ b/src/mesa/Android.libmesa_dricore.mk
@@ -52,6 +52,10 @@ endif # MESA_ENABLE_ASM
LOCAL_CFLAGS := \
$(patsubst %,-DFEATURE_%=1,$(MESA_ENABLED_APIS))
+ifneq ($(strip $(MESA_VERSION_STRING_EXTRA)),)
+LOCAL_CFLAGS +=
-DMESA_VERSION_STRING_EXTRA=\$(MESA_VERSION_STRING_EXTRA)\
+endif
+
LOCAL_C_INCLUDES := \
$(call intermediates-dir-for STATIC_LIBRARIES,libmesa_program,,) \
$(MESA_TOP)/src/mapi \
diff --git a/src/mesa/main/version.c b/src/mesa/main/version.c
index ecca446..3092323 100644
--- a/src/mesa/main/version.c
+++ b/src/mesa/main/version.c
@@ -100,6 +100,9 @@ create_version_string(struct gl_context *ctx, const char
*prefix)
if (ctx-VersionString) {
_mesa_snprintf(ctx-VersionString, max,
%s%u.%u%s Mesa PACKAGE_VERSION
+#ifdef MESA_VERSION_STRING_EXTRA
+ MESA_VERSION_STRING_EXTRA
+#endif
#ifdef MESA_GIT_SHA1
( MESA_GIT_SHA1 )
#endif
--
1.8.1.4
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Re: [Mesa-dev] [PATCH 04/16] glsl: Add support for new bit built-ins in ARB_gpu_shader5.
In the last hunk: + case ir_binop_bfm: + case ir_triop_bfi: These look like leftovers? -- Chris ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 1/4] gallium/dri: Allow drivers to support DRI Image v7
On Mon, 2013-04-22 at 21:38 +1000, Dave Airlie wrote: On Mon, Apr 22, 2013 at 9:09 PM, Jose Fonseca jfons...@vmware.com wrote: - Original Message - From: Christopher James Halse Rogers r...@ubuntu.com This is only exposed by drivers wich support the new PIPE_CAP_PRIME parameter, for PRIME import/export. What does exactly PIPE_CAP_PRIME entail? Please document it. Also why is it needed at all? pipe drivers should be able to render to/from any buffer the winsys can hand it I don't think we need special treatment here, maybe just have the generic code ask the generic kernel cap for prime support. It's perhaps not in the right place, but I couldn't find a better one. A generic solution in the dri state tracker querying DRM_CAP_PRIME would be possible, but I think suboptimal - you really want to know if the winsys can handle dma-buf fds, and that's hidden. It's easy enough to keep PIPE_CAP_PRIME and make the pipe drivers not pull in drm.h, if that's accepable. If its not acceptable, and it's ok to lie about driver support for image v7 then I can gate it in the dri state tracker. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Re: [Mesa-dev] [PATCH 05/16] glsl: Add constant evaluation of bit built-ins.
+ case ir_unop_find_msb:
+ for (unsigned c = 0; c components; c++) {
+ int v = op[0]-value.i[c];
+
+ if (v == 0 || (op[0]-type-base_type == GLSL_TYPE_INT v == -1))
+data.i[c] = -1;
+ else {
+int count = 0;
+int top_bit = op[0]-type-base_type == GLSL_TYPE_UINT
+ ? 0 : v (1 31);
+
+while (((v (1 31)) == top_bit) count != 32) {
+ count++;
+ v = 1;
+}
+
+data.i[c] = count;
Assuming the bits are numbered from the LSB, this probably wants to be
data.i[c] = 32 - count;
-- Chris
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Re: [Mesa-dev] [PATCH 04/16] glsl: Add support for new bit built-ins in ARB_gpu_shader5.
Scratch that -- I see what they're for. They seem to be missing from enum ir_expression_operation though. -- Chris On Tue, Apr 23, 2013 at 1:33 PM, Chris Forbes chr...@ijw.co.nz wrote: In the last hunk: + case ir_binop_bfm: + case ir_triop_bfi: These look like leftovers? -- Chris ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [Bug 62142] Mesa/demo mipmap_limits upside down with running by SOFTWARE
https://bugs.freedesktop.org/show_bug.cgi?id=62142 Gordon Jin gordon@intel.com changed: What|Removed |Added Status|RESOLVED|REOPENED Resolution|INVALID |--- Assignee|i...@freedesktop.org |mesa-dev@lists.freedesktop. ||org Summary|[IVB/HSW] Mesa/demo |Mesa/demo mipmap_limits |mipmap_limits upside down |upside down with running by |with running by SOFTWARE|SOFTWARE Component|Drivers/DRI/i965|Mesa core --- Comment #4 from Gordon Jin gordon@intel.com --- will it be a valid bug for soft render? -- You are receiving this mail because: You are the assignee for the bug. ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev
[Mesa-dev] [PATCH 2/5] r600g/compute: Don't use radeon_winsys::buffer_wait() after dispatching a kernel
From: Tom Stellard thomas.stell...@amd.com
The state tracker should be responsible for waiting for the kernel to
finish.
---
src/gallium/drivers/r600/evergreen_compute.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index 58dc36d..05e5e3d 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -314,7 +314,6 @@ static void compute_emit_cs(struct r600_context *ctx, const
uint *block_layout,
struct radeon_winsys_cs *cs = ctx-rings.gfx.cs;
unsigned flush_flags = 0;
int i;
- struct r600_resource *onebo = NULL;
struct evergreen_compute_resource *resources =
ctx-cs_shader_state.shader-resources;
@@ -390,7 +389,6 @@ static void compute_emit_cs(struct r600_context *ctx, const
uint *block_layout,
}
if (resources[i].bo) {
- onebo = resources[i].bo;
evergreen_emit_ctx_reloc(ctx,
resources[i].bo,
resources[i].usage);
@@ -431,10 +429,6 @@ static void compute_emit_cs(struct r600_context *ctx,
const uint *block_layout,
ctx-flags = 0;
COMPUTE_DBG(ctx-screen, shader started\n);
-
- ctx-ws-buffer_wait(onebo-buf, 0);
-
- COMPUTE_DBG(ctx-screen, ...\n);
}
--
1.7.11.4
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[Mesa-dev] [PATCH 4/5] r600g/compute: Use a constant buffer to store kernel parameters
From: Tom Stellard thomas.stell...@amd.com
---
src/gallium/drivers/r600/evergreen_compute.c | 47 +++---
.../drivers/r600/evergreen_compute_internal.h | 2 +-
2 files changed, 33 insertions(+), 16 deletions(-)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index 05e5e3d..9d3c1d9 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -102,6 +102,25 @@ static void evergreen_cs_set_vertex_buffer(
state-atom.dirty = true;
}
+static void evergreen_cs_set_constant_buffer(
+ struct r600_context * rctx,
+ unsigned cb_index,
+ unsigned offset,
+ unsigned size,
+ struct pipe_resource * buffer)
+
+{
+ struct r600_constbuf_state *state =
+ rctx-constbuf_state[PIPE_SHADER_COMPUTE];
+ struct pipe_constant_buffer *cb = state-cb[cb_index];
+ cb-buffer_size = size;
+ cb-buffer_offset = offset;
+ cb-buffer = buffer;
+ cb-user_buffer = NULL;
+
+ rctx-context.set_constant_buffer(rctx-context, PIPE_SHADER_COMPUTE,
cb_index, cb);
+}
+
static const struct u_resource_vtbl r600_global_buffer_vtbl =
{
u_default_resource_get_handle, /* get_handle */
@@ -189,7 +208,10 @@ void evergreen_compute_upload_input(
struct r600_context *ctx = (struct r600_context *)ctx_;
struct r600_pipe_compute *shader = ctx-cs_shader_state.shader;
int i;
- unsigned kernel_parameters_offset_bytes = 36;
+ /* We need to reserve 8 dwords (36 bytes) for implicit kernel
+* parameters.
+*/
+ unsigned input_size = shader-input_size + 36;
uint32_t * num_work_groups_start;
uint32_t * global_size_start;
uint32_t * local_size_start;
@@ -200,12 +222,9 @@ void evergreen_compute_upload_input(
}
if (!shader-kernel_param) {
- unsigned buffer_size = shader-input_size;
-
/* Add space for the grid dimensions */
- buffer_size += kernel_parameters_offset_bytes;
shader-kernel_param = r600_compute_buffer_alloc_vram(
- ctx-screen, buffer_size);
+ ctx-screen, input_size);
}
num_work_groups_start = r600_buffer_mmap_sync_with_rings(ctx,
shader-kernel_param, PIPE_TRANSFER_WRITE);
@@ -227,20 +246,16 @@ void evergreen_compute_upload_input(
/* Copy the kernel inputs */
memcpy(kernel_parameters_start, input, shader-input_size);
- for (i = 0; i (kernel_parameters_offset_bytes / 4) +
- (shader-input_size / 4); i++) {
+ for (i = 0; i (input_size / 4); i++) {
COMPUTE_DBG(ctx-screen, input %i : %i\n, i,
((unsigned*)num_work_groups_start)[i]);
}
ctx-ws-buffer_unmap(shader-kernel_param-cs_buf);
- ///ID=0 is reserved for the parameters
- evergreen_cs_set_vertex_buffer(ctx, 0, 0,
+ /* ID=0 is reserved for the parameters */
+ evergreen_cs_set_constant_buffer(ctx, 0, 0, input_size,
(struct pipe_resource*)shader-kernel_param);
- ///ID=0 is reserved for parameters
- evergreen_set_const_cache(shader, 0, shader-kernel_param,
- shader-input_size, 0);
}
static void evergreen_emit_direct_dispatch(
@@ -369,6 +384,9 @@ static void compute_emit_cs(struct r600_context *ctx, const
uint *block_layout,
ctx-cs_vertex_buffer_state.atom.num_dw = 12 *
util_bitcount(ctx-cs_vertex_buffer_state.dirty_mask);
r600_emit_atom(ctx, ctx-cs_vertex_buffer_state.atom);
+ /* Emit constant buffer state */
+ r600_emit_atom(ctx, ctx-constbuf_state[PIPE_SHADER_COMPUTE].atom);
+
/* Emit compute shader state */
r600_emit_atom(ctx, ctx-cs_shader_state.atom);
@@ -783,10 +801,9 @@ void evergreen_init_compute_state_functions(struct
r600_context *ctx)
ctx-context.set_global_binding = evergreen_set_global_binding;
ctx-context.launch_grid = evergreen_launch_grid;
- /* We always use at least two vertex buffers for compute, one for
- * parameters and one for global memory */
+ /* We always use at least one vertex buffer for parameters (id = 1)*/
ctx-cs_vertex_buffer_state.enabled_mask =
- ctx-cs_vertex_buffer_state.dirty_mask = 1 | 2;
+ ctx-cs_vertex_buffer_state.dirty_mask = 0x2;
}
diff --git a/src/gallium/drivers/r600/evergreen_compute_internal.h
b/src/gallium/drivers/r600/evergreen_compute_internal.h
index b1a180f..463cc7d 100644
--- a/src/gallium/drivers/r600/evergreen_compute_internal.h
+++ b/src/gallium/drivers/r600/evergreen_compute_internal.h
@@ -113,7 +113,7 @@ void evergreen_set_loop_const(struct r600_pipe_compute
*pipe, int id, int count,
void
[Mesa-dev] [PATCH 5/5] r600g/compute: Removed unused and untested code
From: Tom Stellard thomas.stell...@amd.com
There was a lot of code in evergreen_compute_internal.c that was not
being used at all and most of it was duplicating code from other parts
of the driver.
---
src/gallium/drivers/r600/Makefile.sources | 1 -
src/gallium/drivers/r600/compute_resource.def | 38 --
src/gallium/drivers/r600/evergreen_compute.c | 109 ++--
.../drivers/r600/evergreen_compute_internal.c | 627 -
.../drivers/r600/evergreen_compute_internal.h | 67 ---
5 files changed, 66 insertions(+), 776 deletions(-)
delete mode 100644 src/gallium/drivers/r600/compute_resource.def
delete mode 100644 src/gallium/drivers/r600/evergreen_compute_internal.c
diff --git a/src/gallium/drivers/r600/Makefile.sources
b/src/gallium/drivers/r600/Makefile.sources
index 17ea03b..ec376ef 100644
--- a/src/gallium/drivers/r600/Makefile.sources
+++ b/src/gallium/drivers/r600/Makefile.sources
@@ -16,7 +16,6 @@ C_SOURCES = \
eg_asm.c \
r600_state_common.c \
evergreen_compute.c \
- evergreen_compute_internal.c \
compute_memory_pool.c \
r600_uvd.c
diff --git a/src/gallium/drivers/r600/compute_resource.def
b/src/gallium/drivers/r600/compute_resource.def
deleted file mode 100644
index 161f506..000
--- a/src/gallium/drivers/r600/compute_resource.def
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the Software),
- * to deal in the Software without restriction, including without limitation
- * on the rights to use, copy, modify, merge, publish, distribute, sub
- * license, and/or sell copies of the Software, and to permit persons to whom
- * the Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice (including the next
- * paragraph) shall be included in all copies or substantial portions of the
- * Software.
- *
- * THE SOFTWARE IS PROVIDED AS IS, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
- * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
- * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
- * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
- * USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors:
- * Adam Rak adam@streamnovation.com
- */
-
-
-DECL_COMPUTE_RESOURCE(CONFIG, 1)
-DECL_COMPUTE_RESOURCE(CONST_MEM, 16)
-DECL_COMPUTE_RESOURCE(RAT, 12)
-DECL_COMPUTE_RESOURCE(VERT, 16)
-DECL_COMPUTE_RESOURCE(TEX, 16)
-DECL_COMPUTE_RESOURCE(SAMPLER, 18)
-DECL_COMPUTE_RESOURCE(LOOP, 32)
-DECL_COMPUTE_RESOURCE(LDS, 1)
-DECL_COMPUTE_RESOURCE(GDS, 1)
-DECL_COMPUTE_RESOURCE(EXPORT, 1)
-DECL_COMPUTE_RESOURCE(SHADER, 1)
-DECL_COMPUTE_RESOURCE(TMPRING, 4)
-DECL_COMPUTE_RESOURCE(DISPATCH, 1)
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index 9d3c1d9..f8b2a04 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -81,6 +81,68 @@ writable images will consume TEX slots, VTX slots too
because of linear indexing
*/
+struct r600_resource* r600_compute_buffer_alloc_vram(
+ struct r600_screen *screen,
+ unsigned size)
+{
+ struct pipe_resource * buffer = NULL;
+ assert(size);
+
+ buffer = pipe_buffer_create(
+ (struct pipe_screen*) screen,
+ PIPE_BIND_CUSTOM,
+ PIPE_USAGE_IMMUTABLE,
+ size);
+
+ return (struct r600_resource *)buffer;
+}
+
+
+static void evergreen_set_rat(
+ struct r600_pipe_compute *pipe,
+ int id,
+ struct r600_resource* bo,
+ int start,
+ int size)
+{
+ struct pipe_surface rat_templ;
+ struct r600_surface *surf = NULL;
+ struct r600_context *rctx = NULL;
+
+ assert(id 12);
+ assert((size 3) == 0);
+ assert((start 0xFF) == 0);
+
+ rctx = pipe-ctx;
+
+ COMPUTE_DBG(rctx-screen, bind rat: %i \n, id);
+
+ /* Create the RAT surface */
+ memset(rat_templ, 0, sizeof(rat_templ));
+ rat_templ.format = PIPE_FORMAT_R32_UINT;
+ rat_templ.u.tex.level = 0;
+ rat_templ.u.tex.first_layer = 0;
+ rat_templ.u.tex.last_layer = 0;
+
+ /* Add the RAT the list of color buffers */
+ pipe-ctx-framebuffer.state.cbufs[id] =
pipe-ctx-context.create_surface(
+ (struct pipe_context *)pipe-ctx,
+ (struct pipe_resource *)bo, rat_templ);
+
+ /* Update the number of color buffers */
+ pipe-ctx-framebuffer.state.nr_cbufs =
+ MAX2(id + 1, pipe-ctx-framebuffer.state.nr_cbufs);
+
+ /* Update the cb_target_mask
+* XXX: I think this is a
[Mesa-dev] [PATCH 2/2] i965: Remove strange comments about math functions.
---
Do these comments make sense to anyone else?
src/mesa/drivers/dri/i965/brw_defines.h |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
b/src/mesa/drivers/dri/i965/brw_defines.h
index ea5d2af..6517f24 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1034,9 +1034,9 @@ enum brw_message_target {
#define BRW_MATH_FUNCTION_EXP 3
#define BRW_MATH_FUNCTION_SQRT 4
#define BRW_MATH_FUNCTION_RSQ 5
-#define BRW_MATH_FUNCTION_SIN 6 /* was 7 */
-#define BRW_MATH_FUNCTION_COS 7 /* was 8 */
-#define BRW_MATH_FUNCTION_SINCOS 8 /* was 6 */
+#define BRW_MATH_FUNCTION_SIN 6
+#define BRW_MATH_FUNCTION_COS 7
+#define BRW_MATH_FUNCTION_SINCOS 8 /* gen4, gen5 */
#define BRW_MATH_FUNCTION_FDIV 9 /* gen6+ */
#define BRW_MATH_FUNCTION_POW 10
#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
--
1.7.8.6
___
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Re: [Mesa-dev] [PATCH 1/4] gallium/dri: Allow drivers to support DRI Image v7
On Mon, 22 Apr, 2013 at 4:38 PM, christopher.halse.rog...@canonical.com wrote: From: Christopher James Halse Rogers r...@ubuntu.com This is only exposed by drivers wich support the new PIPE_CAP_PRIME parameter, for PRIME import/export. --- This stubs out texture_from_renderbuffer, which I don't care about, but that looks like it wouldn't be terribly painful to implement if it's a blocker for the PRIME support, which I do care about. src/gallium/drivers/freedreno/freedreno_screen.c | 1 + src/gallium/drivers/i915/i915_screen.c | 1 + src/gallium/drivers/llvmpipe/lp_screen.c | 2 + src/gallium/drivers/nv30/nv30_screen.c | 1 + src/gallium/drivers/nv50/nv50_screen.c | 2 + src/gallium/drivers/nvc0/nvc0_screen.c | 2 + src/gallium/drivers/r300/r300_screen.c | 1 + src/gallium/drivers/r600/r600_pipe.c | 1 + src/gallium/drivers/radeonsi/radeonsi_pipe.c | 1 + src/gallium/drivers/softpipe/sp_screen.c | 2 + src/gallium/drivers/svga/svga_screen.c | 1 + src/gallium/include/pipe/p_defines.h | 3 +- src/gallium/include/state_tracker/drm_driver.h | 9 +- src/gallium/state_trackers/dri/drm/dri2.c | 120 +++-- .../state_trackers/egl/common/native_helper.c | 1 + src/gallium/state_trackers/egl/x11/native_dri2.c | 1 + 16 files changed, 137 insertions(+), 12 deletions(-) diff --git a/src/gallium/drivers/freedreno/freedreno_screen.c b/src/gallium/drivers/freedreno/freedreno_screen.c index 4a9a54e..db122d3 100644 --- a/src/gallium/drivers/freedreno/freedreno_screen.c +++ b/src/gallium/drivers/freedreno/freedreno_screen.c @@ -201,6 +201,7 @@ fd_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_USER_INDEX_BUFFERS: case PIPE_CAP_QUERY_PIPELINE_STATISTICS: case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: + case PIPE_CAP_PRIME: return 0; /* Stream output. */ diff --git a/src/gallium/drivers/i915/i915_screen.c b/src/gallium/drivers/i915/i915_screen.c index dfb76b3..6623dca 100644 --- a/src/gallium/drivers/i915/i915_screen.c +++ b/src/gallium/drivers/i915/i915_screen.c @@ -214,6 +214,7 @@ i915_get_param(struct pipe_screen *screen, enum pipe_cap cap) case PIPE_CAP_TEXTURE_MULTISAMPLE: case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT: case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: + case PIPE_CAP_PRIME: return 0; case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT: diff --git a/src/gallium/drivers/llvmpipe/lp_screen.c b/src/gallium/drivers/llvmpipe/lp_screen.c index 667ade1..5ff30f1 100644 --- a/src/gallium/drivers/llvmpipe/lp_screen.c +++ b/src/gallium/drivers/llvmpipe/lp_screen.c @@ -228,6 +228,8 @@ llvmpipe_get_param(struct pipe_screen *screen, enum pipe_cap param) return 1; case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER: return 0; + case PIPE_CAP_PRIME: + return 0; } /* should only get here on unhandled cases */ debug_printf(Unexpected PIPE_CAP %d query\n, param); diff --git a/src/gallium/drivers/nv30/nv30_screen.c b/src/gallium/drivers/nv30/nv30_screen.c index 5b3b470..97471a7 100644 --- a/src/gallium/drivers/nv30/nv30_screen.c +++ b/src/gallium/drivers/nv30/nv30_screen.c @@ -124,6 +124,7 @@ nv30_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT: case PIPE_CAP_QUERY_PIPELINE_STATISTICS: case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: + case PIPE_CAP_PRIME: return 0; case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY: case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY: diff --git a/src/gallium/drivers/nv50/nv50_screen.c b/src/gallium/drivers/nv50/nv50_screen.c index 5aa8ef3..1177c1b 100644 --- a/src/gallium/drivers/nv50/nv50_screen.c +++ b/src/gallium/drivers/nv50/nv50_screen.c @@ -188,6 +188,8 @@ nv50_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 0; case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50; + case PIPE_CAP_PRIME: + return 0; default: NOUVEAU_ERR(unknown PIPE_CAP %d\n, param); return 0; diff --git a/src/gallium/drivers/nvc0/nvc0_screen.c b/src/gallium/drivers/nvc0/nvc0_screen.c index 8dfd4d1..e3eff40 100644 --- a/src/gallium/drivers/nvc0/nvc0_screen.c +++ b/src/gallium/drivers/nvc0/nvc0_screen.c @@ -178,6 +178,8 @@ nvc0_screen_get_param(struct pipe_screen *pscreen, enum pipe_cap param) return 1; case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK: return PIPE_QUIRK_TEXTURE_BORDER_COLOR_SWIZZLE_NV50; + case PIPE_CAP_PRIME: + return 0; default: NOUVEAU_ERR(unknown PIPE_CAP %d\n, param); return 0; diff --git a/src/gallium/drivers/r300/r300_screen.c b/src/gallium/drivers/r300/r300_screen.c index a932be9..000c71d 100644 ---
